28 行
1.5 KiB
Plaintext
28 行
1.5 KiB
Plaintext
(version 1)
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# F.Cu horizontal, B.Cu vertical. Direction and explicit pair checks:
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# scripts/verify_pcb_layout.py + pcb-routing-rules.json.
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# Net names are unchanged; DP/DM suffixes are not presumed native pairs.
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(rule "R2 inner layers reserved for reference and power zones"
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(condition "A.Layer == 'In1.Cu' || A.Layer == 'In2.Cu'")
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(constraint disallow track))
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(rule "R2 USB differential target - requires recognized pair"
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(condition "A.hasNetclass('USB90')")
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(constraint track_width (min 0.15mm) (opt 0.28mm) (max 0.30mm))
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(constraint diff_pair_gap (min 0.15mm) (opt 0.18mm) (max 0.21mm))
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(constraint diff_pair_uncoupled (max 5mm))
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(constraint skew (max 0.5mm)))
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(rule "R2 switch copper stays on component side with no vias"
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(condition "A.hasNetclass('SWITCH')")
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(constraint disallow via)
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(constraint length (max 12mm)))
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(rule "R2 feedback and oscillator do not change layers"
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(condition "A.hasNetclass('FEEDBACK') || A.hasNetclass('CLOCK_LOCAL')")
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(constraint disallow via)
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(constraint length (max 15mm)))
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(rule "R2 switch tracks isolated from sensitive nets"
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(condition "A.Type == 'Track' && A.hasNetclass('SWITCH') && (B.hasNetclass('FEEDBACK') || B.hasNetclass('ANALOG') || B.hasNetclass('USB90') || B.hasNetclass('CLOCK_LOCAL'))")
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(constraint clearance (min 0.5mm)))
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(rule "R2 ordinary vias stay outside SMD lands"
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(condition "A.Type == 'Via' && B.Type == 'Pad' && B.Pad_Type == 'SMD'")
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(constraint physical_clearance (min 0.1mm)))
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