zhou yang和Claude Opus 5
2bfe308b30
原理图/PCB 已在 EasyEDA 里做到 12 页跨页 0 漏接，固件刚完成骨架包 A1。 这次是把已有的一切一次性纳入版本控制，没有改动任何设计内容。 纳入： - 设计与需求文档、PROGRESS.md、小米8 参考原理图 PDF 与追脚脚本 - .claude/ 下的 EasyEDA 桥接工具链与几何/网表缓存（eda-parts.json、 pcb-parts.json、pcb-pads.json、p2-ch1.json 等，是重画各页的唯一事实来源） - 117 张验证截图（本项目所有方向问题都是靠人眼看截图发现的，属于证据不是垃圾） - firmware/ 的 A1 骨架与 site/ 文档站源码 .gitignore 排除：构建产物（firmware/build、host/build、sdkconfig）、 site/node_modules、__pycache__、桥接日志 _bridge.log、脚本自标的 *.stale。 .gitattributes 默认 `* -text`：现有 .py/.json 大多是 CRLF，原样存， 不让 git 重写行尾。唯一例外是 *.sh 强制 LF —— 带 \r 的 shell 脚本 bash 跑不了。 Co-Authored-By: Claude Opus 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01QYuExfgyYa6DzRRcUso8M8
721 行
6.7 KiB
JSON
721 行
6.7 KiB
JSON
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|
|
"B4A9": [
|
|
235,
|
|
155,
|
|
"VBUS"
|
|
],
|
|
"B1A12": [
|
|
235,
|
|
165,
|
|
"GND"
|
|
]
|
|
},
|
|
"R717": {
|
|
"1": [
|
|
280,
|
|
85,
|
|
"1"
|
|
],
|
|
"2": [
|
|
320,
|
|
85,
|
|
"2"
|
|
]
|
|
},
|
|
"R718": {
|
|
"1": [
|
|
280,
|
|
145,
|
|
"1"
|
|
],
|
|
"2": [
|
|
320,
|
|
145,
|
|
"2"
|
|
]
|
|
}
|
|
} |