zhou yang和Claude Opus 5
2bfe308b30
原理图/PCB 已在 EasyEDA 里做到 12 页跨页 0 漏接，固件刚完成骨架包 A1。 这次是把已有的一切一次性纳入版本控制，没有改动任何设计内容。 纳入： - 设计与需求文档、PROGRESS.md、小米8 参考原理图 PDF 与追脚脚本 - .claude/ 下的 EasyEDA 桥接工具链与几何/网表缓存（eda-parts.json、 pcb-parts.json、pcb-pads.json、p2-ch1.json 等，是重画各页的唯一事实来源） - 117 张验证截图（本项目所有方向问题都是靠人眼看截图发现的，属于证据不是垃圾） - firmware/ 的 A1 骨架与 site/ 文档站源码 .gitignore 排除：构建产物（firmware/build、host/build、sdkconfig）、 site/node_modules、__pycache__、桥接日志 _bridge.log、脚本自标的 *.stale。 .gitattributes 默认 `* -text`：现有 .py/.json 大多是 CRLF，原样存， 不让 git 重写行尾。唯一例外是 *.sh 强制 LF —— 带 \r 的 shell 脚本 bash 跑不了。 Co-Authored-By: Claude Opus 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01QYuExfgyYa6DzRRcUso8M8
165 行
7.1 KiB
Python
165 行
7.1 KiB
Python
# -*- coding: utf-8 -*-
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u"""载板 Inner1 五块 VOn_P 电源岛的**本地几何校核**（不连 EDA，纯算）。
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/c/Python314/python .claude/inner1_check.py [--grid 0.05]
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判据（每块岛）：
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① 本网所有「内层可见」的焊盘（layer 12 通孔）都落在**同一个连通域**里；
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② 扣掉**异网焊盘 / 过孔的反焊盘**（半径 + 0.2 安全间距）之后，
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沿电流方向的**最窄断面 >= 7.0 mm**（IPC-2221 内层 0.5oz / 4 A / ΔT20K）。
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数据来自 `_pcb2_pads_full.json` / `_pcb2_vias.json`（`pcb2_pour.py --dump` 刷新）。
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岛的多边形定义是 `pcb2_pour.py` 的 `ISLANDS`，这里 import 过来，**不重复写一遍**。
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"""
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import json, os, sys
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HERE = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, HERE)
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MIL = 39.3700787401575
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CLEAR = 0.2 # MIN_CLEARANCE，见 pcb2_rules.py
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NECK_MIN = 7.0
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def load_geo():
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pads = json.load(open(os.path.join(HERE, '_pcb2_pads_full.json'), encoding='utf-8'))
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vias = json.load(open(os.path.join(HERE, '_pcb2_vias.json'), encoding='utf-8'))
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P = []
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for ref, num, net, layer, x, y, shape, hole in pads:
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if layer not in (12, 15): # 只有多层（通孔）焊盘在 Inner1 上占位
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continue
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kind = shape[0]
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if kind == 'ELLIPSE':
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hx = hy = shape[1] / MIL / 2.0
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else: # RECT / OVAL / POLYGON -> 按外接矩形保守算
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hx, hy = shape[1] / MIL / 2.0, shape[2] / MIL / 2.0
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P.append((net, x / MIL, y / MIL, hx, hy, '%s.%s' % (ref, num)))
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V = [(net, x / MIL, y / MIL, (d / MIL / 2.0) if d else 0.305)
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for net, x, y, d, h in vias]
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return P, V
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def inside(poly, x, y):
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n, c = len(poly), False
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for i in range(n):
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x1, y1 = poly[i]
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x2, y2 = poly[(i + 1) % n]
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if (y1 > y) != (y2 > y) and x < (x2 - x1) * (y - y1) / (y2 - y1) + x1:
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c = not c
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return c
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def check(name, net, poly, P, V, g, region=None):
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xs = [p[0] for p in poly]; ys = [p[1] for p in poly]
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x0, x1, y0, y1 = min(xs), max(xs), min(ys), max(ys)
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nx, ny = int(round((x1 - x0) / g)), int(round((y1 - y0) / g))
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cx = [x0 + (i + 0.5) * g for i in range(nx)]
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cy = [y0 + (j + 0.5) * g for j in range(ny)]
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cell = [[inside(poly, cx[i], cy[j]) for i in range(nx)] for j in range(ny)]
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# 反焊盘：异网的通孔焊盘 / 过孔
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def carve(px, py, hx, hy, r=None):
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a, b = (hx + CLEAR, hy + CLEAR) if r is None else (r + CLEAR, r + CLEAR)
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i0 = max(0, int((px - a - x0) / g)); i1 = min(nx - 1, int((px + a - x0) / g) + 1)
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j0 = max(0, int((py - b - y0) / g)); j1 = min(ny - 1, int((py + b - y0) / g) + 1)
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for j in range(j0, j1 + 1):
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for i in range(i0, i1 + 1):
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if not cell[j][i]:
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continue
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dx, dy = abs(cx[i] - px), abs(cy[j] - py)
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if r is None:
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if dx <= a and dy <= b:
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cell[j][i] = False
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elif (dx * dx + dy * dy) <= a * a:
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cell[j][i] = False
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carved = 0
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for pnet, px, py, hx, hy, tag in P:
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if pnet == net:
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continue
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if px + hx + CLEAR < x0 or px - hx - CLEAR > x1: continue
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if py + hy + CLEAR < y0 or py - hy - CLEAR > y1: continue
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carve(px, py, hx, hy); carved += 1
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for vnet, vx, vy, vr in V:
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if vnet == net: continue
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if vx + vr + CLEAR < x0 or vx - vr - CLEAR > x1: continue
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if vy + vr + CLEAR < y0 or vy - vr - CLEAR > y1: continue
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carve(vx, vy, 0, 0, r=vr); carved += 1
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# 连通域（4 邻接，迭代式洪泛，避免递归深度）
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lab = [[0] * nx for _ in range(ny)]
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k = 0; sizes = {}
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for j in range(ny):
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for i in range(nx):
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if not cell[j][i] or lab[j][i]:
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continue
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k += 1; st = [(j, i)]; lab[j][i] = k; n_ = 0
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while st:
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a, b = st.pop(); n_ += 1
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for da, db in ((1, 0), (-1, 0), (0, 1), (0, -1)):
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p, q = a + da, b + db
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if 0 <= p < ny and 0 <= q < nx and cell[p][q] and not lab[p][q]:
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lab[p][q] = k; st.append((p, q))
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sizes[k] = n_
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main = max(sizes, key=sizes.get) if sizes else 0
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# 本网焊盘是否都在主连通域里
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own, bad = [], []
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for pnet, px, py, hx, hy, tag in P:
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if pnet != net: continue
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if not (x0 - 1 <= px <= x1 + 1 and y0 - 1 <= py <= y1 + 1): continue
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own.append(tag)
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i = int((px - x0) / g); j = int((py - y0) / g)
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hit = False
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rr = int((max(hx, hy) + 0.3) / g) + 1
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for q in range(max(0, j - rr), min(ny, j + rr + 1)):
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for p in range(max(0, i - rr), min(nx, i + rr + 1)):
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if lab[q][p] == main: hit = True; break
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if hit: break
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if not hit: bad.append(tag)
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# 断面：逐行 / 逐列统计主连通域的铜宽
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def scan(rows):
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out = []
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for idx, line in rows:
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tot = sum(1 for v in line if v == main) * g
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run = m = 0
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for v in line:
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run = run + 1 if v == main else 0
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m = max(m, run)
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if tot > 0: out.append((tot, m * g, idx))
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return out
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# v2：7 mm 颈宽只在走廊主体（region = body_bbox）里量；穿筋的 3 mm 颈只走纹波电流
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rx0, ry0, rx1, ry1 = region if region else (x0, y0, x1, y1)
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rowsY = scan([(cy[j], [lab[j][i] if rx0 <= cx[i] <= rx1 else 0 for i in range(nx)])
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for j in range(ny) if ry0 <= cy[j] <= ry1])
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rowsX = scan([(cx[i], [lab[j][i] if ry0 <= cy[j] <= ry1 else 0 for j in range(ny)])
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for i in range(nx) if rx0 <= cx[i] <= rx1])
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my = min(rowsY); mx = min(rowsX)
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ok = (not bad) and my[0] >= NECK_MIN and mx[0] >= NECK_MIN
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print(u' %-4s %-7s %2d 焊盘 / 挖 %3d 个反焊盘 / %d 个连通域（主域 %.0f mm²）'
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% (name, net, len(own), carved, k, sizes.get(main, 0) * g * g))
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print(u' 最窄横断面 %5.2f mm（连续段 %.2f）@ y=%.2f '
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u'最窄纵断面 %5.2f mm（连续段 %.2f）@ x=%.2f %s'
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% (my[0], my[1], my[2], mx[0], mx[1], mx[2], u'✅' if ok else u'❌'))
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if bad:
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print(u' [!!] 这些本网焊盘不在主连通域里: %s' % ' '.join(bad))
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return ok
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def main():
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g = 0.05
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if '--grid' in sys.argv: g = float(sys.argv[sys.argv.index('--grid') + 1])
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from pcb2_pour import ISLANDS, island_poly, body_bbox
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P, V = load_geo()
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print(u'Inner1 电源岛几何校核（栅格 %.2f mm，安全间距 %.2f，颈宽下限 %.1f mm）'
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% (g, CLEAR, NECK_MIN))
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allok = True
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for name, net, body, branch in ISLANDS:
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allok &= check(name, net, island_poly(body, branch), P, V, g, region=body_bbox(body))
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print(u'%s' % (u'全部通过。' if allok else u'!! 有不达标的岛，先改 ISLANDS 再 --push。'))
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return 0 if allok else 1
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if __name__ == '__main__':
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sys.exit(main())
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