418 行
19 KiB
Python
418 行
19 KiB
Python
# -*- coding: utf-8 -*-
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u"""R2 刀片 PCB 的设计规则（M4c-1）。
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/c/Python314/python .claude/r2/pcb_rules.py # 只反查 + 打印，不下发
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/c/Python314/python .claude/r2/pcb_rules.py --push # 下发规则 + 差分对 + 网络指派
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/c/Python314/python .claude/r2/pcb_rules.py --audit # 读回审计
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做法照抄 R1 的 `.claude/pcb1_rules.py`，**那一份的文件头是唯一的说明书**，
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四个坑一个都没变：
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· `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装
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· `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状**
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· 下发之后**别再去 GUI 换「配置」下拉框** —— 换一次整套重置，网络指派全部悬空
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· `overwriteNetRules` / `overwriteNetByNetRules` 都是**整表覆盖**，必须先读回再合并
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## 和 R1 下板不同的四处
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1. **刀片只有一路**，所以线宽表比 R1 短：没有 `FAN12V`，`PWR12V` 也从 2.0 降到 0.8
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—— 刀片 12V 满载只有 **1.45 A**（§20.7 那颗 2 A 保险就是按它选的），
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R1 的 2.0 mm 是给整机 8~10 A 的干路用的，照抄过来只会把功率列挤死。
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2. **两对差分**，不是一对：`USB_DP/DM`（金手指 → U7 ESD）和 `USB_DPJ/DMJ`（U7 → J4 尾插）
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是被 U7 隔开的两段，各自成对。只建一对的话另一段退回默认 0.2 mm 净距规则，
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在换层过孔处会误判 —— 和 R1 §10.1b 同一个理由。
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3. **层角色**（§7.1）：L1 功率+信号 / **Inner1(L2) = 完整地平面（不许割断）** /
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Inner2(L3) = 12V + VO 灌铜 / L4(Bottom) = 控制信号。D± 走 L1、以 L2 为参考。
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4. **自动命名网只有两个**（R1 有十几个）：SW 节点和 eFuse 输出段。
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仍然**按「位号.引脚」当场反查、两端交叉校核**，不写死 `$1N137` 这种名字 ——
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再导入一次变更它就可能改名，而写死的后果是**静默失效**（DRC 干干净净，规则悬空）。
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"""
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import io
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import json
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import os
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import sys
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sys.stdout.reconfigure(encoding='utf-8')
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HERE = os.path.dirname(os.path.abspath(__file__))
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# ⚠ HERE 必须后插（在 sys.path 最前）：`.claude` 下有同名的 R1 脚本。
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sys.path.insert(0, os.path.dirname(HERE))
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sys.path.insert(0, HERE)
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from eda import run # noqa: E402
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U = json.load(io.open(os.path.join(HERE, 'r2-uuids.json'), encoding='utf-8'))
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PCB = U['boards']['BLADE']['pcb']['uuid']
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NETS_FILE = os.path.join(HERE, '_blade_pcb_nets.json')
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# ── 线宽规则（mm，外层 1 oz）────────────────────────────────────────────
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# 载流靠灌铜保证、不靠 DRC；min 一律压到 0.15~0.3，否则 0402 焊盘（0.57 宽）扇不出去。
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TRACK_RULES = {
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'PWR12V': {'strokeWidthDefault': 0.8, 'strokeWidthMin': 0.25, 'strokeWidthMax': 4.0},
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'SWNODE': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.30, 'strokeWidthMax': 4.0},
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'PWR4A': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.30, 'strokeWidthMax': 6.0},
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'PWR5V': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.20, 'strokeWidthMax': 3.0},
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'PWR1A': {'strokeWidthDefault': 0.4, 'strokeWidthMin': 0.15, 'strokeWidthMax': 2.0},
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}
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# ── 有名字的网络 → 线宽规则 ────────────────────────────────────────────
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NET_TRACK = {
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'+12V': 'PWR12V', # 金手指 B1/B2/B3 + A2/A3 → F1，1.45 A
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'+12V_F': 'PWR12V', # F1 → Buck 输入，同一路电流
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'VO': 'PWR4A', # Buck 输出 → eFuse 输入
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'VO_P': 'PWR4A', # 检流之后 → J5 电池排线，4 A
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'+5V': 'PWR5V', # 金手指 A19/A32 → U5 TPS22918
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'VBUS': 'PWR5V', # U5 → J4 尾插，手机 VBUS
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'+3V3': 'PWR1A', # 刀片逻辑（INA226 + PCA9555）≈ 3 mA，0.4 纯余量
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}
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# ── 自动命名网 → (规则, 探针, 校核端)：两端查出来必须是同一个网 ─────────
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AUTO_TRACK = {
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# SW 节点：TPS54622(VQFN-14) 的 SW = pin 11/12 → L1
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'SW': ('SWNODE', ('L1', '1'), ('U1', '11')),
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# eFuse 输出段：TPS25940A(WQFN-20) 的 OUT = pin 4~8 → Rs1 上游脚
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'VO_F': ('PWR4A', ('Rs1', '2'), ('U2', '5')),
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}
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# ── 铺铜焊盘全连接（理由同 R1：不是怕十字花烧，是**铺完之后断面要量得准**）──
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PLANE_RULE = 'PLANE-DIRECT'
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PLANE_CONNECT_DIRECT = 1
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PLANE_NETS = ['VO_P', 'VO', '+12V', '+12V_F']
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PLANE_AUTO = ['VO_F']
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# ── 差分对（mm）── 与 R1 同一组数：W 0.28 / S 0.18，以 L2 为参考 ────────
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# ⚠ 2026-09-11 下限 0.20 → 0.15：USB_DPJ/DMJ 进 J4（BM24 0.35 节距、焊盘 0.18 宽）只能 0.18，
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# 0.20 的下限会让整对 USBPHONE 在 DRC 里刷「差分对线宽」（router.DP_WJ）。
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DIFF = {'strokeWidthDefault': 0.28, 'strokeWidthMin': 0.15, 'strokeWidthMax': 0.60,
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'differentailPairSpacingDefault': 0.18, 'differentailPairSpacingMin': 0.15,
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'differentailPairLenTolerMax': 5.0}
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PAIR_RULE = 'USBPAIR'
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PAIR_CLEARANCE = 0.15
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PAIRS = [('USBEDGE', 'USB_DP', 'USB_DM'), # 金手指 → U7 USBLC6
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('USBPHONE', 'USB_DPJ', 'USB_DMJ')] # U7 → J4 BM24 尾插
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# ⚠ **0.15，不是 R1 的 0.2**。抬到 0.2 会刷出 23 条「贴片焊盘到贴片焊盘」——
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# **全部在 `J4` BM24-50DS 内部**：0.4 mm 间距的尾插座，相邻焊盘实测净距 0.168~0.171，
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# 这是买来的连接器封装本身的几何，不是摆位问题，改摆位也修不掉。
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# 0.15 仍远高于嘉立创四层板 0.09 的能力线，而板上其它最紧的一处是
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# `K1~K4` 侧键盘的 0.276（Ø1.5 盘、实测间距 1.78），也过。
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MIN_CLEARANCE = 0.15
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OPEN = ("await eda.dmt_EditorControl.openDocument('%s');"
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"await new Promise(r=>setTimeout(r,2000));" % PCB)
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def call(body, timeout=300):
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r = run(OPEN + body, timeout=timeout)
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if not r.get('success'):
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print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600])
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sys.exit(1)
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return r['result']
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def dump_nets():
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u"""重抓「位号.引脚 → 网名」。**每次导入变更之后必跑**。"""
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r = call("const out = {};"
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"for (const c of await eda.pcb_PrimitiveComponent.getAll()) {"
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" const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId("
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" c.getState_PrimitiveId());"
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" out[c.designator] = ps.map(p=>[p.padNumber, p.net]); }"
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"return out;")
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io.open(NETS_FILE, 'w', encoding='utf-8').write(json.dumps(r, ensure_ascii=False))
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print(u'已写 _blade_pcb_nets.json：%d 件' % len(r))
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return r
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def resolve_auto(nets=None):
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u"""按 (位号, 引脚) 反查自动网名并逐条断言。对不上就**不下发**。"""
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if nets is None:
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if not os.path.exists(NETS_FILE):
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nets = dump_nets()
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else:
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nets = json.load(io.open(NETS_FILE, encoding='utf-8'))
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pin = {}
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for ref, pads in nets.items():
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for pn, net in pads:
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pin[(ref, str(pn))] = net
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out, bad, seen = {}, [], {}
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for key, (_rule, probe, cross) in sorted(AUTO_TRACK.items()):
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if probe not in pin:
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bad.append(u'%s: 板上没有 %s.%s' % (key, probe[0], probe[1]))
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continue
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if cross not in pin:
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bad.append(u'%s: 板上没有校核端 %s.%s' % (key, cross[0], cross[1]))
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continue
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net, other = pin[probe], pin[cross]
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if not net or not str(net).startswith('$'):
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bad.append(u'%s: %s.%s 上是 "%s"，不是自动命名网 —— 探针写错了'
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% (key, probe[0], probe[1], net))
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continue
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if net != other:
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bad.append(u'%s: %s.%s = %s，但校核端 %s.%s = %s —— 两端不是同一个网'
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% (key, probe[0], probe[1], net, cross[0], cross[1], other))
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continue
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if net in seen:
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bad.append(u'%s 和 %s 查到同一个网 %s' % (key, seen[net], net))
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continue
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seen[net] = key
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out[key] = net
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if bad:
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print(u' [!!] 自动命名网反查失败，**没有下发任何东西**：')
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for b in bad:
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print(u' · ' + b)
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print(u' 多半是 _blade_pcb_nets.json 过期了 —— 导入变更之后要重跑 --dump。')
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sys.exit(1)
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return out
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def net_track_full(auto):
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t = dict(NET_TRACK)
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for key, net in auto.items():
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t[net] = AUTO_TRACK[key][0]
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return t
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def plane_nets_full(auto):
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return list(PLANE_NETS) + [auto[k] for k in PLANE_AUTO]
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CAP_JS = u"""
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const D = eda.pcb_Drc;
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const cur = await D.getCurrentRuleConfiguration();
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const c = JSON.parse(JSON.stringify(cur.config));
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const multi = (await D.getRuleConfiguration(
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'JLCPCB Capability(Multiple Layers Board)')).config;
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const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s;
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const PLANERULE = %s, PLANEMODE = %s;
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const setTrack = (e, mn, df, mx) => {
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for (const k of Object.keys(e.form.data))
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Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx});
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};
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const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing'];
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setTrack(T['copperThickness1oz'], 0.102, 0.254, 2.54);
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if (!T['copperThickness0.5oz']) {
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const e = JSON.parse(JSON.stringify(T['copperThickness1oz']));
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e.editName = 'copperThickness0.5oz'; e.isSetDefault = false;
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setTrack(e, 0.089, 0.254, 2.54);
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T['copperThickness0.5oz'] = e;
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}
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Object.assign(c['Physics']['Via Size']['viaSize'].form,
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{viaOuterdiameterMin: 0.3, viaInnerdiameterMin: 0.2});
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if (!SS['copperThicknessInner0.5oz']) {
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const e = JSON.parse(JSON.stringify(SS['copperThickness1oz']));
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e.editName = 'copperThicknessInner0.5oz'; e.isSetDefault = false;
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const src = multi['Spacing']['Safe Spacing']['copperThicknessInner0.5oz'].table;
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for (const k of Object.keys(e.tables))
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e.tables[k].content = JSON.parse(JSON.stringify(src));
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SS['copperThicknessInner0.5oz'] = e;
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}
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for (const name of Object.keys(TRACKS)) {
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const f = TRACKS[name];
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const e = JSON.parse(JSON.stringify(T['copperThickness1oz']));
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e.editName = name; e.isSetDefault = false; e.unit = 'mm';
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setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax);
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T[name] = e;
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}
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const dp = c['Physics']['Differential Pair']['differentialPair'].form;
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for (const k of Object.keys(dp.strokeWidthTables.data))
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Object.assign(dp.strokeWidthTables.data[k],
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{minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault,
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maxValue: DW.strokeWidthMax});
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for (const k of Object.keys(dp.diffPairSpacingTables.data))
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Object.assign(dp.diffPairSpacingTables.data[k],
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{minValue: DW.differentailPairSpacingMin,
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defaultValue: DW.differentailPairSpacingDefault});
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dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax;
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if (!SS[PAIRRULE]) {
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const e = JSON.parse(JSON.stringify(SS['copperThickness1oz']));
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e.editName = PAIRRULE; e.isSetDefault = false;
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for (const tk of Object.keys(e.tables || {}))
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for (const row of (e.tables[tk].content || []))
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for (let i = 0; i < row.length; i++)
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if (typeof row[i] === 'number') row[i] = PAIRC;
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SS[PAIRRULE] = e;
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}
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// 安全间距全表**归一到 MINC**：≤0.2 的格子（板厂能力值 0.09~0.127，以及上一版抬到
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// 0.2 的那些）一律设成 MINC；0.254 / 0.3 那几格是孔/板边相关的，**不动**。
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// ⚠ R1 那份只「抬高不降低」，所以把 MINC 从 0.2 改小是改不动的 —— 这里必须是赋值。
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let bumped = 0;
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for (const key of Object.keys(SS))
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if (key !== PAIRRULE)
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for (const tk of Object.keys(SS[key].tables || {}))
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for (const row of (SS[key].tables[tk].content || []))
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for (let i = 0; i < row.length; i++)
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if (typeof row[i] === 'number' && row[i] <= 0.2001 &&
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Math.abs(row[i] - MINC) > 1e-6) { row[i] = MINC; bumped++; }
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const CZ = c['Plane']['Copper Zone'];
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if (!CZ[PLANERULE]) {
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const e = JSON.parse(JSON.stringify(CZ['copperRegion']));
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e.editName = PLANERULE; e.isSetDefault = false;
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CZ[PLANERULE] = e;
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}
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for (const m of ['singleLayerPadModel', 'multiLayerPadModel'])
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for (const k of Object.keys(CZ[PLANERULE].form[m].data))
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CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE;
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const ok = await D.overwriteCurrentRuleConfiguration(c);
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return {ok: ok === true, bumped: bumped, name: cur.name,
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track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)};
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"""
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def push():
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auto = resolve_auto()
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track = net_track_full(auto)
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planes = plane_nets_full(auto)
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print(u' 自动网反查: ' + ' '.join(u'%s=%s' % (k, v) for k, v in sorted(auto.items())))
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r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE,
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json.dumps(PAIR_RULE), PAIR_CLEARANCE,
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json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT))
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if not r.get('ok'):
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print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效')
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sys.exit(1)
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print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track']))
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print(u' 安全间距抬高 %d 格；配置名 "%s"' % (r['bumped'], r['name']))
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n = call("""
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const P = %s;
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let k = 0;
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for (const d of await eda.pcb_Drc.getAllDifferentialPairs())
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await eda.pcb_Drc.deleteDifferentialPair(d.name);
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for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; }
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return k;
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""" % json.dumps(PAIRS))
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print(u' 差分对 %d / %d 对' % (n, len(PAIRS)))
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if n != len(PAIRS):
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print(u' [!!] 有对没建上 —— 网络名在这块板上不存在')
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n = call("""
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const T = %s, PN = %s, PR = %s;
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const pset = new Set(PN);
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const rules = await eda.pcb_Drc.getNetRules();
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let k = 0, p = 0;
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const seen = [];
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for (const r of rules) {
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if (r.type !== 'net') continue;
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if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); }
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if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; }
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}
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await eda.pcb_Drc.overwriteNetRules(rules);
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return {track: k, plane: p, seen: seen};
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""" % (json.dumps(track, ensure_ascii=False), json.dumps(planes, ensure_ascii=False),
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json.dumps(PLANE_RULE)))
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print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(track)))
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if n['track'] != len(track):
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print(u' [!!] 板上找不到: %s' % ' '.join(sorted(set(track) - set(n['seen']))))
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print(u' 铺铜全连接指派 %d / %d（%s）' % (n['plane'], len(planes), ' '.join(planes)))
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n = call("""
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const PAIRS = %s, RULE = %s;
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const cur = await eda.pcb_Drc.getNetByNetRules();
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const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : [];
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const key = e => [e.net1.name, e.net2.name].sort().join('|');
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const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|')));
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const list = [];
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let dropped = 0;
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for (const e of old) {
|
||
if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; }
|
||
list.push(e);
|
||
}
|
||
const have = new Set(list.map(key));
|
||
let k = 0;
|
||
for (const [name, dp, dm] of PAIRS) {
|
||
const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm},
|
||
rule: RULE, copperRuleName: null, planeRuleName: null};
|
||
if (have.has(key(e))) continue;
|
||
list.push(e); k++;
|
||
}
|
||
const ok = await eda.pcb_Drc.overwriteNetByNetRules(
|
||
{'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []});
|
||
const back = await eda.pcb_Drc.getNetByNetRules();
|
||
return {added: k, dropped: dropped, ok: ok === true,
|
||
now: (back['Safe Spacing'] || []).length};
|
||
""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE)))
|
||
print(u' 对内间距：新增 %d / 清掉过期 %d，现共 %d 条（%s = %.2f mm）'
|
||
% (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE))
|
||
|
||
call("await eda.pcb_Document.save(); return 1;")
|
||
print(u' 已保存')
|
||
print(u'')
|
||
print(u'⚠ 别去 GUI 的 设计 → 设计规则… 里换「配置」下拉框：换一次整套重置，')
|
||
print(u' %d 个网络的线宽指派立刻悬空，而 DRC 不会报错。' % len(track))
|
||
print(u'⚠ 再导入一次变更之后顺序是：--dump → --push，少跑 --dump 就是拿旧网名指派。')
|
||
|
||
|
||
AUDIT_JS = u"""
|
||
const c = await eda.pcb_Drc.getCurrentRuleConfiguration();
|
||
const rules = await eda.pcb_Drc.getNetRules();
|
||
const nbn = await eda.pcb_Drc.getNetByNetRules();
|
||
return {
|
||
cfgName: c && c.name,
|
||
layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(),
|
||
track: Object.keys(c.config.Physics['Track']),
|
||
half: !!c.config.Physics['Track']['copperThickness0.5oz'],
|
||
inner: !!c.config.Spacing['Safe Spacing']['copperThicknessInner0.5oz'],
|
||
pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(),
|
||
assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default')
|
||
.map(r => [r.name, r['Track']]).sort(),
|
||
planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default')
|
||
.map(r => [r.name, r['Copper Zone']]).sort(),
|
||
nbn: ((nbn && nbn['Safe Spacing']) || []).length,
|
||
};
|
||
"""
|
||
|
||
|
||
def audit():
|
||
auto = resolve_auto()
|
||
track = net_track_full(auto)
|
||
planes = plane_nets_full(auto)
|
||
r = call(AUDIT_JS)
|
||
bad = []
|
||
|
||
def chk(cond, good, msg):
|
||
print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg))
|
||
if not cond:
|
||
bad.append(msg)
|
||
|
||
print(u'──── 审计（配置 "%s"）────' % r['cfgName'])
|
||
chk(r['layers'] == 4, u'铜层数 4', u'铜层数是 %s，应为 4' % r['layers'])
|
||
chk(r['half'] and r['inner'], u'内层 0.5 oz 的线宽/间距条目都在',
|
||
u'内层 0.5 oz 条目缺失')
|
||
miss = [k for k in TRACK_RULES if k not in r['track']]
|
||
chk(not miss, u'五条线宽条目都在', u'缺线宽条目 %s' % miss)
|
||
got = dict(r['assigned'])
|
||
wrong = [(n, got.get(n), v) for n, v in sorted(track.items()) if got.get(n) != v]
|
||
chk(not wrong, u'%d 个网络的线宽指派全对' % len(track),
|
||
u'指派不对: %s' % wrong[:6])
|
||
chk(sorted(r['pairs']) == sorted([p[0] for p in PAIRS]),
|
||
u'差分对 %s' % r['pairs'], u'差分对是 %s，应为 %s' % (r['pairs'], [p[0] for p in PAIRS]))
|
||
chk(r['nbn'] == len(PAIRS), u'对内间距 %d 条' % r['nbn'],
|
||
u'对内间距 %d 条，应为 %d' % (r['nbn'], len(PAIRS)))
|
||
gotp = dict(r['planeAssigned'])
|
||
missp = [n for n in planes if gotp.get(n) != PLANE_RULE]
|
||
chk(not missp, u'铺铜全连接 %d 个网络' % len(planes), u'没指派上: %s' % missp)
|
||
print(u' ' + (u'[OK] 全部通过' if not bad else u'[X] %d 条不过' % len(bad)))
|
||
return bad
|
||
|
||
|
||
if __name__ == '__main__':
|
||
print(u'刀片 PCB=%s' % PCB)
|
||
if '--dump' in sys.argv:
|
||
dump_nets()
|
||
if '--push' in sys.argv:
|
||
push()
|
||
audit()
|
||
elif '--audit' in sys.argv:
|
||
audit()
|
||
elif '--dump' not in sys.argv:
|
||
a = resolve_auto()
|
||
t = net_track_full(a)
|
||
print(u'自动网: ' + ' '.join(u'%s=%s' % (k, v) for k, v in sorted(a.items())))
|
||
for n, v in sorted(t.items(), key=lambda kv: (kv[1], kv[0])):
|
||
print(u' %-10s -> %s' % (n, v))
|