R2 底板改 4 层（D15）：规则 / 几何 / 背面摆位 / 4 层布线与铺铜，已下发

- 规则：铜层 2→4，差分 0.28/0.18，间距 0.15，过孔 0.3/0.2（rules_base） - 几何：98×98 板框 + 4×M3，槽阵居中，L1 12V 大铜 + 指头（pcb_base） - 摆位：五插槽留 L1，其余 133 件翻到 L4；背面镜像规则实测；Hub 放走廊 2、东移 2.5 mm；扇出圈 / 小件间距 1.5（去耦例外）/ 9 A 过孔阵禁区（place_base） - 叠层按用户决定改为 L1 槽面 / L2 整层 +3V3 / L3 整层 GND / L4 器件面 - 布线：D± 七对按构造布通（USB3 掉头、USB1/2 北去掉头、USB4/5 东绕、 J23 桥），+3V3 / GND / +12V 平面网每脚一孔，0.125 网格 + PathFinder 开关（route_base、remote_route.ps1）；剩 37 个网待手工补 - 铺铜：4 层重写，入口链自南向北切段 + 断面校核（pour_base）；已下发布线 / 缝合孔 / 铜面轮廓，填铜未成功（待查） - 工具：plot_base / plot_routes / shot_base，board_check 通孔两层都算 Co-Authored-By: Claude Opus 5 <[email protected]> Claude-Session: https://claude.ai/code/session_0168Bu6SEx3cXXCJLkdnE6zB
2026-09-10 21:02:10 +08:00
@@ -0,0 +1,225 @@
+# R2 底板（BASE）剩余四页的**跨页契约** — 2026-09-08
+
+`A1-INPUT` / `A2-AUX` 已画完。本文件钉死 `A3-CTRL` / `A4-HUB` / `A5-SLOTS` / `A6-FAN`
+四页之间的**网络名、方向、器件归属、位号区段**。四页由四个子代理并行设计，
+**只有主代理能下发到 EasyEDA**（全机只有一个 EDA 客户端，`openDocument` 是全局状态，
+两个人同时推必然把图元放到别人的页上）。
+
+⛔ **子代理绝对不许**：跑 `.claude/eda.py`、`dump_page.py`、`xpage.py`、`shot.py`、
+`verify_sch.py`、任何带 `--push` 的脚本，或任何会连 `127.0.0.1:4962x` 的东西。
+你的交付物是**一个能本地自检通过的 Python 脚本**，主代理负责下发与几何验证。
+
+---
+
+## 0. 已经存在的东西（不要重画，也不要改名）
+
+| 页 | 内容 | 对外端口 / 旗 |
+|---|---|---|
+| `A1-INPUT` | J1 DC-005 → F1 → Q1 反接 → C2~C6 → Rs6 → 12V 母线；U13 INA226(0x43)；U29 TL431 泄放 | `+12V`(旗) `GND`(旗) `+3V3`(旗) `SDA` `SCL` `INA_ALERT`(端口) |
+| `A2-AUX` | U19 12V→3V3（0.5A）；U30 12V→5V（2A） | `+12V` `+3V3` `GND`(旗) `+5V`(端口，OUT) |
+
+`xpage` 现在的 4 个单实例 `+5V` / `SDA` / `SCL` / `INA_ALERT` 就是等你们补对端的。
+
+---
+
+## 1. 网络名总表（**唯一事实来源**）
+
+### 1.1 电源
+
+| 网络 | 图元类型 | 说明 |
+|---|---|---|
+| `+12V` | **Power 旗** | 全板 12V 母线 |
+| `+3V3` | **Power 旗** | U19 出来的控制轨（0.5A），给 ESP32 / mux / DAC / 刀片逻辑 |
+| `+5V` | **端口** | U30 出来的 5V（2A）。A2 已发 OUT，A4/A5 用 **IN** |
+| `+3V3_HUB` | **Power 旗**（仅 A4 页内） | U31 AMS1117 给 U32 专用，**不许**和 `+3V3` 并 |
+| `FAN_12V_SW` | **Power 旗**（仅 A6 页内） | Q7 高边开关之后的风扇 12V |
+| `GND` | **Ground 旗** | — |
+
+### 1.2 跨页信号（发出方 → 接收方）
+
+| 网络 | 发出 | 接收 | 说明 |
+|---|---|---|---|
+| `SDA` / `SCL` | A1(U13) | **A3**（上拉 + ESP32 + U35 上游 + U6/U7 DAC） | I²C **主干**，不经 mux |
+| `INA_ALERT` | A1(U13) | **A3**（ESP32 GPIO） | 开漏，上拉放在 A3 |
+| `SDA1`~`SDA5` / `SCL1`~`SCL5` | **A3**(U35 通道 0~4) | **A5**（槽 1~5） | mux 分支，**上拉在刀片上**（B2-CTRL 的 R40/R41），底板这一侧不加 |
+| `VDAC1`~`VDAC5` | **A3**(U6/U7) | **A5** | 模拟量，跨金手指进刀片 |
+| `EFUSE_EN1`~`EFUSE_EN5` | **A3**(ESP32 直驱) | **A5** | 不经 IO 扩展 |
+| `PRSNT1#`~`PRSNT5#` | **A5**(槽 **B31** 一针) | **A3**（ESP32 输入 + 上拉） | ⚠️ **2026-09-08 修正**：底板是**主板侧**，`A1` 与 `B31` 必须是**两个节点** —— `A1 → GND`、`B31 → PRSNT{n}#`。短接 A1↔B31 的是**刀片**（`b4_edge.py`，PCIe add-in card 的标准做法），插上刀片才把 B31 拉到地。若底板也照字面「镜像」把两针并成一个网，回路里一个对地通路都没有 ⇒ **插不插都读「未插入」，而 DRC/ERC/几何验证/跨页对账四道全过**。见 `a5_slots.py` 表头的对照表 |
+| `INT#` | **A5**（五槽 B11 并联） | **A3**（ESP32 + **唯一一颗 10k 上拉到 +3V3**） | 开漏 wire-OR，五槽共一个网络 |
+| `HUB_RST` | **A3**(ESP32) | **A4**(U32) | ⚠ 见 §3 的保命约束 |
+| `UP_VBUS_DET` | **A4** | **A3**(ESP32) | 电脑在不在 |
+| `USB1_DP/DM` ~ `USB5_DP/DM` | **A4**(U32 下行口 1~5) | **A5**（槽 B14/B15） | |
+| `USB6_DP` / `USB6_DM` | **A4**(U32 下行口 6) | **A3**（ESP32 原生 USB，IO19=D−/IO20=D+） | D13 |
+| `FAN_EN` | **A3**(ESP32) | **A6** | 高边总开关，复位态必须**关电** |
+| `FAN_PWM` | **A3**(ESP32) | **A6** | 两只风扇共用（A6 里经反相成 `FAN_PWM_L`） |
+| `FAN_TACH_IN` / `FAN_TACH_OUT` | **A6** | **A3**(ESP32) | 两路独立测速 |
+| `NTC1` / `NTC2` | **A6**(RT601/RT602 分压节点) | **A3**(ESP32 **ADC1** 脚) | ⚠ 必须 ADC1（IO1~IO10），ADC2 与 WiFi 冲突 |
+
+### 1.3 页内网络（不跨页，别在别的页上用这些名字）
+
+- A3：`MUX_RST#`（U35 的 RESET#，10k 上拉 + 一个 ESP32 GPIO）、`EN` / `IO0` / `TXD0` / `RXD0`（J33）
+- A4：`UP_DP` `UP_DM` `VBUS_UP` `VBUS_DET` `XTAL1` `XTAL2` `RBIAS` `VDD18` `VDD18PLL`
+  `CFGSEL0` `CFGSEL1` `NONREM0` `NONREM1`（全部沿用 R1 `C2-HUB` 的名字）
+- A6：`FAN_PWM_L` `FAN_IN_TACH_RAW` `FAN_OUT_TACH_RAW`
+- A5：无（全是 §1.2 的网络 + 电源 + 地）
+
+### 1.4 **明确不存在**的网络（R1 有、R2 没有，写了就是错）
+
+`BUCK_PG`（A2 的 U19 没引 PG）、`IOEXP_INT#`（改叫 `INT#`）、
+`EFUSE_PG*` / `EFUSE_FLT*`（eFuse 在刀片上，状态走刀片自己的 PCA9555）、
+`VBUS_EN*`（在刀片 B2-CTRL 上）、`KEY_*`（74HC595 已作废，D9）、
+`USB_DP` / `USB_DM` 不带编号的形式（那是刀片页内的名字）。
+
+---
+
+## 2. 位号区段（防撞）
+
+| 页 | 允许使用 |
+|---|---|
+| A1（已画） | `J1` `F1` `Q1` `Q3` `DZ1` `D1` `R1` `R4` `R5` `R6` `R9A~R9E` `C1~C6` `C11` `Rs6` `U13` `U29` |
+| A2（已画） | `U19` `U30` `L2` `L3` `R2` `R3` `R706` `R707` `C7~C10` `C731~C735` |
+| **A3-CTRL** | `U20` `U35` `U6` `U7` `J33`，新增无源件用 `R601~R650` / `C601~C650` |
+| **A4-HUB** | `U31` `U32` `Y1` `J23`，无源件 `R708~R730` / `C737` `C740~C759` |
+| **A5-SLOTS** / **A5B-SLOTS** | 插槽 `J34~J38`（槽 1~5）、D± 退路座 `J39~J43`，无源件 `R760~R790` / `C761~C790` |
+| **A6-FAN** | `Q6~Q10` `D2` `DZ3` `J26` `J27` `RT601` `RT602`，电容 `C736` `C738` `C739`，电阻 `R733` `R734` `R746~R757` + 新增 `R660~R699` |
+
+> ⚠️ **2026-09-08 修订**：原表里 A4 的 `C740~C760` 与 A5 的 `C760~C790` 在 `C760` 上撞车（A6 代理发现），
+> 已改成 `C740~C759` / `C761~C790`。A6 原来只点名了 `C738`，现补 `C736` / `C739`（全表仅剩的两个无主号）。
+> `A5B-SLOTS` 是 2026-09-08 新开的第七页（`e493f8bce3a51aae`），与 A5 共用同一段号。
+
+---
+
+## 3. 三条会烧板 / 会自断后路的硬约束
+
+1. **`HUB_RST` 必须外部上拉到 `+3V3_HUB`（10k），且 ESP32 复位期间 Hub 保持工作。**
+   ESP32 的控制台就挂在这颗 Hub 后面（D13），误复位 = 自断控制台 + 下次烧不进去。
+   固件侧只在启动自检脉冲一次 —— 硬件侧要保证「不驱动 = 不复位」。
+2. **`FAN_EN` 复位态必须是关电。** Q7 是 P-MOS 高边，栅极靠 Q6 拉低才导通；
+   Q6 栅极要有 100k 下拉，ESP32 高阻时风扇不转（R1 P6 已经是这个拓扑，照抄）。
+3. **`+3V3_HUB` 与 `+3V3` 是两条轨**（U32 满载 ≈420 mA，挂不进 U19 那条 0.5A 轨）。
+   两者只共地。A4 页上不许出现把它们并起来的导线或同名旗。
+
+---
+
+## 4. 器件与引脚几何（全部实测，直接用，不要自己猜）
+
+`.claude/eda-parts.json` 是器件表；下面是**这四页要用到的新器件**的引脚相对坐标（rot 0，相对元件中心）：
+
+```
+TCA9548APWR (C130026)  左列 x=-50，右列 x=+50
+  1 A0    (-50, 55)   13 SD4  (50,-55)
+  2 A1    (-50, 45)   14 SC4  (50,-45)
+  3 RESET#(-50, 35)   15 SD5  (50,-35)
+  4 SD0   (-50, 25)   16 SC5  (50,-25)
+  5 SC0   (-50, 15)   17 SD6  (50,-15)
+  6 SD1   (-50,  5)   18 SC6  (50, -5)
+  7 SC1   (-50, -5)   19 SD7  (50,  5)
+  8 SD2   (-50,-15)   20 SC7  (50, 15)
+  9 SC2   (-50,-25)   21 A2   (50, 25)
+ 10 SD3   (-50,-35)   22 SCL  (50, 35)
+ 11 SC3   (-50,-45)   23 SDA  (50, 45)
+ 12 GND   (-50,-55)   24 VCC  (50, 55)
+
+NCP18XH103F03RB (C13564)  1 (-20,0)  2 (+20,0)     无极性
+2.54mm 1*5P 直排针 (C50951)  1(-20,20) 2(-20,10) 3(-20,0) 4(-20,-10) 5(-20,-20)   全部朝左
+AMS1117-3.3 (C6186)  1 GND(-45,10)  2 VOUT(-45,0)  3 VIN(-45,-10)  4 VOUT(+45,0)
+PCIE-064-02-F-D-TH (C4597619)  A1~A32: x=-35, y=155-10*(n-1)
+                               B1~B32: x=+35, y=155-10*(n-1)
+```
+
+其余器件（ESP32-S3-WROOM-1 / DAC63204 / USB2517I / Y1 / AO3400A / AO3401A /
+SS34 / BZT52C8V2 / TYPE-C-31-M-12 / 2510-4A / A1251WV-S-4P / 各种 0402）的引脚坐标
+**从 R1 的实测 dump 里直接读**，见 §5。
+
+---
+
+## 5. R1 参照版图（已 dump 成 JSON，直接读，**不要连 EDA**）
+
+| 文件 | 是哪一页 | 给谁用 |
+|---|---|---|
+| `.claude/r2/_p3_live.json` | R1 `P3-CONTROL`（U20 ESP32 + J22 + RT601/602） | **A3**（ESP32 那一块整块搬）、**A6**（NTC 分压那一小块搬走） |
+| `.claude/r2/_p3b_live2.json` | R1 `P3B-EXPAND`（U6/U7 DAC + U23 PCA9555） | **A3**（两颗 DAC 整块搬，U23 不要） |
+| `.claude/r2/_c2hub_live.json` | R1 `C2-HUB`（U32 + Y1 + J23 + 一堆去耦） | **A4**（整页搬，加第 6 个下行口） |
+| `.claude/r2/_p6_live.json` | R1 `P6-FAN-EDL`（风扇部分 + EDL 部分） | **A6**（**只要风扇部分**，EDL 已挪去刀片 B3-PHONE） |
+| `.claude/r2/b4_edge.py` | R2 刀片 `B4-EDGE`（金手指 64 针分配） | **A5**（针位表照抄并做**逐脚对账**） |
+
+JSON 结构见 `.claude/r2/dump_page.py` 的文档串：
+`parts` = `[位号, 器件名, 子部件, x, y, rot, mirror, uuid, libraryUuid, [[脚号,脚名,x,y],...]]`，
+`wires` = **端点对**（不是折线），`flags` = `[种类, 网名, x, y, rot]`，
+`ports` = `[dir, 网名, x, y, rot]`，`texts` = `[x, y, 内容, rot, 字号]`。
+
+⚠️ **搬版图时引脚坐标是绝对坐标**：算出 `(引脚x - 元件x, 引脚y - 元件y)` 得到相对量，
+再加上你的新元件中心。**不要相信任何"方向表"**（skill §6c：同一个 `rot` 在不同型号上语义相反）。
+
+---
+
+## 6. 每页交付物
+
+一个 `.claude/r2/aN_xxx.py`，**照抄 `a1_input.py` / `a2_aux.py` 的骨架**：
+
+```python
+HERE = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, HERE)
+from schcheck import Sheet, by_rel, two_pin, pins_of, _on   # 按需
+
+PAGE, NAME = '<页uuid>', '<页名>'
+
+def placement(): ...   # [[位号, eda-parts的键, x, y, rot], ...]
+def expect():    ...   # {位号: {脚号: (绝对x, 绝对y)}}   放件后逐脚回读比对用
+def build():     ...   # 返回填好 W/F/PT/TX 的 Sheet
+
+def main():
+    s = build(); s.assert_grid()
+    errs = s.netcheck(PINS, NC, ALLOW_SPLIT)
+    s.report(len(placement()), errs)
+    if '--push' in sys.argv:
+        s.clear(); s.place(placement(), expect()); s.push_geometry()
+```
+
+**页 uuid**（`.claude/r2/r2-uuids.json` 的 `boards.BASE.pages`）：
+
+| 页 | uuid |
+|---|---|
+| A3-CTRL | `38327f806bc13133` |
+| A4-HUB | `09d583ff95cd35d9` |
+| A5-SLOTS | `2c73c5bf77f34053` |
+| A6-FAN | `68c9ffaa578572d3` |
+
+跑 `/c/Python314/python .claude/r2/aN_xxx.py`（**不带 `--push`**）必须打印出：
+
+```
+元件 N  导线 N  旗 N  端口 N  文字 N
+交叉点（不相连，供人工确认）: N
+本地自检通过（短路 0 / 漏连 0 / 悬空 0 / 旗端口全在端点）
+```
+
+---
+
+## 7. 画图硬规矩（全部来自 `.claude/skills/easyeda-sch-geometry/SKILL.md`，**先读它**）
+
+1. **Y 轴向上**（§1）。
+2. 所有坐标必须是 **5 的倍数**（§3、§8a-2b）—— 否则旗/端口静默不连。
+3. 导线只能**横平竖直**，用 `s.w(net, p1, p2, p3...)` 逐段声明。
+4. 旗 / 端口的锚点必须落在**某段导线的端点**上，不能压在中段（§8a-2），
+   也不能和元件引脚**同坐标**（§8a：那会变成零长度导线，验证过得去、重画就断）。
+5. 同一个锚点上如果有两段**共线**的导线，合并后就成了中段 —— `netcheck` 会报。
+6. 页面范围 `x 20~1145` / `y 10~812`；**标题栏**在 `x>455 且 y<192`，文字不许伸进去（§8c）。
+7. 文字宽度经验值：`右边界 ≈ x + 字号 × (中文字数 + 0.5×其余字符数)`。
+8. **叠字是这个项目的常见事故**：端口的符号+标签往锚点**左边**伸出去约 70 个单位，
+   `flag_clash` 那种「横向 <20」的判据够不着。排版时给端口左边留 ≥80 的空白。
+9. 电源/地旗的 `rot`：`0` = 符号朝上（往上挂），`180` = 朝下。极性件别信方向表，按**脚号**断言。
+10. `ALLOW_SPLIT` 只放行「靠同名旗/端口成网、导线上天然分块」的网络（`GND` `+12V` `+3V3` `+5V` 这类）。
+    信号网络出现「被拆成 N 块」就是真漏连，不许往 `ALLOW_SPLIT` 里加来消错。
+
+---
+
+## 8. 汇报格式
+
+做完后回报（**不要贴整段脚本**）：
+
+1. 脚本路径 + dry-run 的那三行统计输出（原样贴）。
+2. 本页画了什么（一句话一块）。
+3. **你发出/接收的端口清单**（网名 + dir），主代理要拿它对账。
+4. 你做的**设计决定**与依据（尤其是 GPIO 分配、strap 电平、上下拉取值）。
+5. 你发现的**风险 / 与方案文档不一致的地方**（B3=+12V 那种错就是这么揪出来的）。
+6. 交叉点清单（如果有），说明为什么可接受。
@@ -0,0 +1,38 @@
+# M6 手工补线作业单（按板上实际铜算，5 个网）
+
+布线方向约定：底层（器件面）纵向、顶层横向；信号线宽 0.15，过孔 0.6/0.3。
+⚠ 这些脚的出口都被**自家邻脚的引出脚 / 过孔**封死（如 `U2.15` 被 `EFUSE_EN` 的孔 (89.5,31) 卡到只剩 0.04 mm），脚本布线器四种办法（换顺序 / PathFinder / 只补线 / 过孔扇出）都到不了。交互式布线时先挪开挡路的那根引出脚或过孔再拉线。
+
+
+## VDAC（2 只脚）— R8.2 一根铜都没有
+  - `J1.A16`  (49.50, 3.45)  底层
+  - `R8.2`  (93.50, 49.85)  底层
+  现有铜 7.8 mm
+
+## $1N147（3 只脚）— U2.15 一根铜都没有
+  - `R9.2`  (77.20, 27.35)  底层
+  - `R10.1`  (79.33, 27.35)  底层
+  - `U2.15`  (89.75, 30.02)  底层
+  现有铜 2.1 mm
+
+## $1N156（2 只脚）— R11.1 U2.17 一根铜都没有
+  - `R11.1`  (82.33, 27.35)  底层
+  - `U2.17`  (91.00, 29.27)  底层
+  现有铜 0.0 mm
+
+## EFUSE_PG（3 只脚）— U2.2 一根铜都没有
+  - `R15.1`  (79.33, 31.35)  底层
+  - `U2.2`  (89.75, 27.02)  底层
+  - `U4.16`  (79.32, 20.12)  底层
+  现有铜 52.7 mm
+
+## $1N165（8 只脚）— R16.1 一根铜都没有
+  - `R16.1`  (79.33, 29.35)  底层
+  - `Rs1.2`  (87.87, 23.04)  底层
+  - `U2.6`  (87.75, 27.02)  底层
+  - `U2.5`  (88.25, 27.02)  底层
+  - `U2.4`  (88.75, 27.02)  底层
+  - `U2.8`  (87.00, 28.27)  底层
+  - `U2.7`  (87.00, 27.77)  底层
+  - `U3.10`  (85.05, 19.10)  底层
+  现有铜 23.1 mm
@@ -0,0 +1,92 @@
+# 手工布线作业单（13 条）
+
+布线方向约定：**底层（器件面）纵向、顶层横向**；线宽 ≥ 规则下限（信号 0.15）。
+
+## VBUS_EN（3 只脚）
+  - `R62.2`  (59.20, 14.85)  底层
+  - `U4.8`  (73.28, 19.47)  底层
+  - `U5.3`  (42.45, 21.45)  底层
+  现有铜 0.00 mm；一根都没有，整条要画
+
+## EFUSE_EN（4 只脚）
+  - `J1.A11`  (42.50, 3.45)  底层
+  - `Q1.1`  (78.55, 35.28)  底层
+  - `R14.1`  (82.33, 31.35)  底层
+  - `U2.14`  (89.25, 30.02)  底层
+  现有铜 88.19 mm；已有部分，缺的是把它们连成一片
+
+## $1N164（3 只脚）
+  - `R16.2`  (80.20, 29.35)  底层
+  - `R17.1`  (82.33, 29.35)  底层
+  - `U2.3`  (89.25, 27.02)  底层
+  现有铜 2.13 mm；已有部分，缺的是把它们连成一片
+
+## USB_DPJ（2 只脚）
+  - `J4.6`  (48.26, 19.94)  顶层
+  - `U7.3`  (49.04, 17.75)  底层
+  现有铜 0.00 mm；一根都没有，整条要画
+
+## $1N151（2 只脚）
+  - `R12.2`  (77.20, 29.35)  底层
+  - `U2.19`  (91.00, 28.27)  底层
+  现有铜 0.00 mm；一根都没有，整条要画
+
+## SCL（4 只脚）
+  - `J1.B5`  (36.50, 3.45)  顶层
+  - `R41.1`  (77.83, 25.45)  底层
+  - `U3.5`  (83.05, 14.87)  底层
+  - `U4.22`  (79.32, 16.23)  底层
+  现有铜 245.61 mm；已有部分，缺的是把它们连成一片
+
+## KEY_PWR（2 只脚）
+  - `R42.2`  (2.30, 22.85)  底层
+  - `U4.4`  (73.28, 16.88)  底层
+  现有铜 0.00 mm；一根都没有，整条要画
+
+## INT#（2 只脚）
+  - `J1.B11`  (42.50, 3.45)  顶层
+  - `U4.1`  (73.28, 14.93)  底层
+  现有铜 7.75 mm；已有部分，缺的是把它们连成一片
+
+## PRSNT#（2 只脚）
+  - `J1.A1`  (32.50, 4.00)  底层
+  - `J1.B31`  (64.50, 4.00)  顶层
+  现有铜 15.50 mm；已有部分，缺的是把它们连成一片
+
+## +3V3（14 只脚）
+  - `C13.1`  (86.38, 18.00)  底层
+  - `C40.1`  (72.30, 25.45)  底层
+  - `C69.1`  (67.30, 22.35)  底层
+  - `J1.A10`  (41.50, 3.45)  底层
+  - `J1.A9`  (40.50, 3.45)  底层
+  - `J1.B8`  (39.50, 3.45)  顶层
+  - `R13.1`  (76.33, 31.35)  底层
+  - `R15.2`  (80.20, 31.35)  底层
+  - `R18.1`  (80.83, 33.35)  底层
+  - `R40.2`  (75.70, 25.45)  底层
+  - `R41.2`  (78.70, 25.45)  底层
+  - `U3.6`  (83.05, 19.10)  底层
+  - `U4.24`  (79.32, 14.93)  底层
+  - `U6.5`  (65.30, 21.30)  底层
+  现有铜 131.15 mm；已有部分，缺的是把它们连成一片
+
+## VBUS（6 只脚）
+  - `C67.1`  (44.80, 14.85)  底层
+  - `J4.51`  (45.73, 21.00)  顶层
+  - `R64.2`  (45.70, 16.85)  底层
+  - `U5.5`  (45.15, 20.50)  底层
+  - `U5.6`  (45.15, 19.55)  底层
+  - `U7.5`  (48.09, 15.45)  底层
+  现有铜 21.65 mm；已有部分，缺的是把它们连成一片
+
+## EFUSE_FLT（3 只脚）
+  - `R13.2`  (77.20, 31.35)  底层
+  - `U2.20`  (91.00, 27.77)  底层
+  - `U4.13`  (79.32, 22.07)  底层
+  现有铜 57.31 mm；已有部分，缺的是把它们连成一片
+
+## EFUSE_PG（3 只脚）
+  - `R15.1`  (79.33, 31.35)  底层
+  - `U2.2`  (89.75, 27.02)  底层
+  - `U4.16`  (79.32, 20.12)  底层
+  现有铜 49.57 mm；已有部分，缺的是把它们连成一片
@@ -0,0 +1,968 @@
+{
+"C1": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C2": {
+"n": 2,
+"w": 5.1,
+"h": 1.6,
+"rot": -90.00000000000001,
+"fp": "CAP-TH_BD8.0-P3.50-D0.6-FD"
+},
+"C3": {
+"n": 2,
+"w": 5.1,
+"h": 1.6,
+"rot": -90.00000000000001,
+"fp": "CAP-TH_BD8.0-P3.50-D0.6-FD"
+},
+"C4": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 0,
+"fp": "C0805"
+},
+"C5": {
+"n": 2,
+"w": 3.409,
+"h": 1.349,
+"rot": 0,
+"fp": "C0805"
+},
+"C6": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C7": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 90,
+"fp": "C0805"
+},
+"C8": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C9": {
+"n": 2,
+"w": 4.671,
+"h": 1.727,
+"rot": 0,
+"fp": "C1206"
+},
+"C10": {
+"n": 2,
+"w": 4.671,
+"h": 1.727,
+"rot": 0,
+"fp": "C1206"
+},
+"C11": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 270,
+"fp": "C0402"
+},
+"C601": {
+"n": 2,
+"w": 4.671,
+"h": 1.727,
+"rot": 0,
+"fp": "C1206"
+},
+"C602": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 90,
+"fp": "C0402"
+},
+"C603": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 90,
+"fp": "C0402"
+},
+"C604": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C607": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 270,
+"fp": "C0402"
+},
+"C608": {
+"n": 2,
+"w": 3.409,
+"h": 1.349,
+"rot": 180,
+"fp": "C0805"
+},
+"C609": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 90,
+"fp": "C0402"
+},
+"C610": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 270,
+"fp": "C0402"
+},
+"C611": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 90,
+"fp": "C0805"
+},
+"C612": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 90,
+"fp": "C0402"
+},
+"C731": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 270,
+"fp": "C0805"
+},
+"C732": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 180,
+"fp": "C0805"
+},
+"C733": {
+"n": 2,
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+"fp": "C0402"
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+"C734": {
+"n": 2,
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+"rot": 0,
+"fp": "C1206"
+},
+"C735": {
+"n": 2,
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+"fp": "C1206"
+},
+"C736": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C737": {
+"n": 2,
+"w": 3.899,
+"h": 1.359,
+"rot": 270,
+"fp": "CASE-A_3216"
+},
+"C738": {
+"n": 2,
+"w": 4.671,
+"h": 1.727,
+"rot": 180,
+"fp": "C1206"
+},
+"C739": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 180,
+"fp": "C0402"
+},
+"C740": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 180,
+"fp": "C0402"
+},
+"C741": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 180,
+"fp": "C0402"
+},
+"C742": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C743": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C744": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C745": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C746": {
+"n": 2,
+"w": 1.339,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C747": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C748": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C749": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C750": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 0,
+"fp": "C0402"
+},
+"C751": {
+"n": 2,
+"w": 3.409,
+"h": 1.349,
+"rot": 0,
+"fp": "C0805"
+},
+"C752": {
+"n": 2,
+"w": 3.411,
+"h": 1.349,
+"rot": 180,
+"fp": "C0805"
+},
+"C753": {
+"n": 2,
+"w": 1.341,
+"h": 0.541,
+"rot": 90,
+"fp": "C0402"
+},
+"D1": {
+"n": 2,
+"w": 6.769,
+"h": 2.192,
+"rot": 0,
+"fp": "SMB_L4.6-W3.6-LS5.3-RD"
+},
+"D2": {
+"n": 2,
+"w": 6.398,
+"h": 1.999,
+"rot": 180,
+"fp": "SMA_L4.3-W2.6-LS5.2-RD"
+},
+"DZ1": {
+"n": 2,
+"w": 4.219,
+"h": 0.841,
+"rot": 180,
+"fp": "SOD-123_L2.7-W1.7-LS3.8-RD"
+},
+"DZ3": {
+"n": 2,
+"w": 4.597,
+"h": 0.95,
+"rot": 270,
+"fp": "SOD-123_L2.7-W1.6-LS3.7-RD-1"
+},
+"F1": {
+"n": 2,
+"w": 4.082,
+"h": 1.727,
+"rot": 0,
+"fp": "F1206"
+},
+"J1": {
+"n": 3,
+"w": 7.6,
+"h": 7.399,
+"rot": 90,
+"fp": "DC-IN-TH_DC-005-2"
+},
+"J23": {
+"n": 16,
+"w": 9.85,
+"h": 6.499,
+"rot": 0,
+"fp": "USB-C_SMD-TYPE-C-31-M-12_1"
+},
+"J26": {
+"n": 4,
+"w": 9.22,
+"h": 1.6,
+"rot": 180,
+"fp": "CONN-TH_4P-P2.54_CAX_2510-4A"
+},
+"J27": {
+"n": 4,
+"w": 9.22,
+"h": 1.6,
+"rot": 180,
+"fp": "CONN-TH_4P-P2.54_CAX_2510-4A"
+},
+"J33": {
+"n": 5,
+"w": 11.859,
+"h": 1.699,
+"rot": -90.00000000000001,
+"fp": "HDR-TH_5P-P2.54-V-M"
+},
+"J34": {
+"n": 66,
+"w": 41.999,
+"h": 9.197,
+"rot": 0,
+"fp": "PCIE-SMD_PCIE-64P11L"
+},
+"J35": {
+"n": 66,
+"w": 41.999,
+"h": 9.197,
+"rot": 0,
+"fp": "PCIE-SMD_PCIE-64P11L"
+},
+"J36": {
+"n": 66,
+"w": 41.999,
+"h": 9.197,
+"rot": 0,
+"fp": "PCIE-SMD_PCIE-64P11L"
+},
+"J37": {
+"n": 66,
+"w": 41.999,
+"h": 9.197,
+"rot": 0,
+"fp": "PCIE-SMD_PCIE-64P11L"
+},
+"J38": {
+"n": 66,
+"w": 41.999,
+"h": 9.197,
+"rot": 0,
+"fp": "PCIE-SMD_PCIE-64P11L"
+},
+"L2": {
+"n": 2,
+"w": 4.801,
+"h": 3.5,
+"rot": 180,
+"fp": "IND-SMD_L4.0-W4.0"
+},
+"L3": {
+"n": 2,
+"w": 7.6,
+"h": 3.401,
+"rot": 180,
+"fp": "IND-SMD_L7.1-W6.5"
+},
+"Q1": {
+"n": 8,
+"w": 4.384,
+"h": 7.569,
+"rot": 0,
+"fp": "SOP-8_L5.0-W4.0-P1.27-LS6.0-BL"
+},
+"Q3": {
+"n": 8,
+"w": 4.384,
+"h": 7.572,
+"rot": -90.00000000000001,
+"fp": "SOP-8_L5.0-W4.0-P1.27-LS6.0-BL"
+},
+"Q6": {
+"n": 3,
+"w": 3.0,
+"h": 2.55,
+"rot": 180,
+"fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR"
+},
+"Q7": {
+"n": 3,
+"w": 3.302,
+"h": 2.7,
+"rot": 0,
+"fp": "SOT-23_L2.9-W1.3-P1.90-LS2.4-BR"
+},
+"Q8": {
+"n": 3,
+"w": 3.002,
+"h": 2.55,
+"rot": 180,
+"fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR"
+},
+"Q9": {
+"n": 3,
+"w": 3.002,
+"h": 2.55,
+"rot": 180,
+"fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR"
+},
+"Q10": {
+"n": 3,
+"w": 3.0,
+"h": 2.55,
+"rot": 90,
+"fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR"
+},
+"R1": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R2": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R3": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 180,
+"fp": "R0402"
+},
+"R4": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 90,
+"fp": "R0402"
+},
+"R5": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R6": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 90,
+"fp": "R0402"
+},
+"R9A": {
+"n": 2,
+"w": 7.414,
+"h": 3.457,
+"rot": 0,
+"fp": "R2512"
+},
+"R9B": {
+"n": 2,
+"w": 7.414,
+"h": 3.457,
+"rot": 180,
+"fp": "R2512"
+},
+"R9C": {
+"n": 2,
+"w": 7.414,
+"h": 3.457,
+"rot": 0,
+"fp": "R2512"
+},
+"R9D": {
+"n": 2,
+"w": 7.414,
+"h": 3.457,
+"rot": 180,
+"fp": "R2512"
+},
+"R9E": {
+"n": 2,
+"w": 7.414,
+"h": 3.457,
+"rot": 0,
+"fp": "R2512"
+},
+"R601": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R602": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R603": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R604": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R605": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R606": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R607": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R608": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R609": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R610": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R611": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R614": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 90,
+"fp": "R0402"
+},
+"R615": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 0,
+"fp": "R0402"
+},
+"R616": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 270,
+"fp": "R0402"
+},
+"R617": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 180,
+"fp": "R0402"
+},
+"R660": {
+"n": 2,
+"w": 1.433,
+"h": 0.541,
+"rot": 180,
+"fp": "R0402"
+},
+"R661": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 180,
+"fp": "R0402"
+},
+"R706": {
+"n": 2,
+"w": 1.43,
+"h": 0.541,
+"rot": 180,
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@@ -0,0 +1 @@
+[]
@@ -0,0 +1,172 @@
+{
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+ "seq": [
+  {
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+  {
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+   "txt": "R709\n\t\t\t\t\n\n\t增加元件\tR709\t-\tR709\n\nR710\n\t\t\t\t\n\n\t增加元件\tR710\t-\tR710\n\nR711\n\t\t\t\t\n\n\t增加元件\tR711\t-\tR711\n\nR712\n\t\t\t\t\n\n\t增加元件\tR712\t-\tR712\n\nR716\n\t\t\t\t\n\n\t增加元件\tR716\t-\tR716\n\nR717\n\t\t\t\t\n\n\t增加元件\tR717\t-\tR717\n\nR718\n\t\t\t\t\n\n\t增加元件\tR718\t-\tR718\n\nR719\n\t\t\t\t\n\n\t增加元件\tR719\t-\tR719\n\nR720\n\t\t\t\t\n\n\t增加元件\tR720\t-\tR720\n\nR721\n\t\t\t\t\n\n\t增加元件\tR721\t-\tR721\n\nR722\n\t\t\t\t\n\n\t增加元件\tR722\t-\tR722\n\nR733\n\t\t\t\t\n\n\t增加元件\tR733\t-\tR733\n\nR734\n\t\t\t\t\n\n\t增加元件\tR734\t-\tR734\n\nR746\n\t\t\t\t\n\n\t增加元件\tR746\t-\tR746\n\nR747\n\t\t\t\t\n\n\t增加元件\tR747\t-\tR747\n\nR748\n\t\t\t\t\n\n\t增加元件\tR748\t-\tR748\n\nR749\n\t\t\t\t\n\n\t增加元件\tR749\t-\tR749\n\nR750\n\t\t\t\t"
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+  {
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+   "txt": "\t增加元件\tR712\t-\tR712\n\nR716\n\t\t\t\t\n\n\t增加元件\tR716\t-\tR716\n\nR717\n\t\t\t\t\n\n\t增加元件\tR717\t-\tR717\n\nR718\n\t\t\t\t\n\n\t增加元件\tR718\t-\tR718\n\nR719\n\t\t\t\t\n\n\t增加元件\tR719\t-\tR719\n\nR720\n\t\t\t\t\n\n\t增加元件\tR720\t-\tR720\n\nR721\n\t\t\t\t\n\n\t增加元件\tR721\t-\tR721\n\nR722\n\t\t\t\t\n\n\t增加元件\tR722\t-\tR722\n\nR733\n\t\t\t\t\n\n\t增加元件\tR733\t-\tR733\n\nR734\n\t\t\t\t\n\n\t增加元件\tR734\t-\tR734\n\nR746\n\t\t\t\t\n\n\t增加元件\tR746\t-\tR746\n\nR747\n\t\t\t\t\n\n\t增加元件\tR747\t-\tR747\n\nR748\n\t\t\t\t\n\n\t增加元件\tR748\t-\tR748\n\nR749\n\t\t\t\t\n\n\t增加元件\tR749\t-\tR749\n\nR750\n\t\t\t\t\n\n\t增加元件\tR750\t-\tR750\n\nR751\n\t\t\t\t\n\n\t增加元件\tR751\t-\tR751\n\nR752\n\t\t\t\t\n\n\t增加元件\tR752\t-\tR752\n\nR753\n\t\t\t\t\n\n\t增加元件\tR753\t-\tR753"
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--- a/显示更多
+++ b/显示更多
				`@@ -0,0 +1 @@`
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