diff --git a/.claude/_esp32_pinmap.json b/.claude/_esp32_pinmap.json index 111b9ef..1b84402 100644 --- a/.claude/_esp32_pinmap.json +++ b/.claude/_esp32_pinmap.json @@ -28,32 +28,26 @@ "EFUSE_EN2": 5, "EFUSE_EN3": 6, "EFUSE_EN4": 7, - "SCL": 8, + "EFUSE_EN5": 12, + "FAN_PWM": 24, + "FAN_TACH": 25, + "IOEXP_INT#": 31, + "KEY_OE#": 23, + "KEY_RCLK": 11, "KEY_SER": 9, "KEY_SRCLK": 10, - "KEY_RCLK": 11, - "EFUSE_EN5": 12, + "NTC1": 39, + "NTC2": 38, + "SCL": 8, + "SDA": 22, + "UP_VBUS_DET": 36, "VBUS_EN1": 17, "VBUS_EN2": 18, "VBUS_EN3": 19, "VBUS_EN4": 20, - "VBUS_EN5": 21, - "SDA": 22, - "KEY_OE#": 23, - "FAN_PWM": 24, - "FAN_TACH": 25, - "IOEXP_INT#": 31, - "UP_VBUS_DET": 36, - "NTC2": 38, - "NTC1": 39 + "VBUS_EN5": 21 }, "pin2io": { - "4": "IO4", - "5": "IO5", - "6": "IO6", - "7": "IO7", - "8": "IO15", - "9": "IO16", "10": "IO17", "11": "IO18", "12": "IO8", @@ -67,12 +61,56 @@ "24": "IO47", "25": "IO48", "31": "IO38", - "36": "IO44", - "38": "IO2", - "39": "IO1", "32": "IO39", "33": "IO40", "34": "IO41", - "35": "IO42" + "35": "IO42", + "36": "IO44", + "38": "IO2", + "39": "IO1", + "4": "IO4", + "5": "IO5", + "6": "IO6", + "7": "IO7", + "8": "IO15", + "9": "IO16" + }, + "r2_base": { + "EFUSE_EN1": 21, + "EFUSE_EN2": 20, + "EFUSE_EN3": 19, + "EFUSE_EN4": 18, + "EFUSE_EN5": 17, + "FAN_EN": 7, + "FAN_PWM": 6, + "FAN_TACH_IN": 5, + "FAN_TACH_OUT": 4, + "HUB_RST": 12, + "INA_ALERT": 31, + "INT#": 32, + "IO0": 27, + "MUX_RST#": 33, + "NTC1": 39, + "NTC2": 38, + "PRSNT1#": 11, + "PRSNT2#": 10, + "PRSNT3#": 9, + "PRSNT4#": 8, + "PRSNT5#": 22, + "SCL": 35, + "SDA": 34, + "UP_VBUS_DET": 23, + "USB6_DM": 13, + "USB6_DP": 14 + }, + "r2_base_nc": { + "15": "IO3 strapping(JTAG_SEL)", + "16": "IO46 strapping + input-only", + "24": "IO47 备用", + "25": "IO48 备用", + "26": "IO45 strapping(VDD_SPI)", + "28": "IO35 留给 R8 版八线 PSRAM", + "29": "IO36 同上", + "30": "IO37 同上" } } \ No newline at end of file diff --git a/.claude/_p1_import_rows.json b/.claude/_p1_import_rows.json index bf582f2..4944af7 100644 --- a/.claude/_p1_import_rows.json +++ b/.claude/_p1_import_rows.json @@ -1,6 +1,35 @@ { "opened": true, - "seq": [], + "seq": [ + { + "top": 0, + "txt": "DZ3\n\t\t\t\t\n\n\t修改封装\tSOD-123_L2.7-W1.6-LS3.7-RD-1:封装\tSOD-123_L2.7-W1.6-LS3.7-RD-1\tSOT-23_L2.9-W1.3-P1.90-LS2.4-BR\n\nJ1\n\t\t\t\t\n\n\t移除元件\tJ1\tJ1\t\n\nJ26\n\t\t\t\t\n\n\t修改封装\tCONN-TH_4P-P2.54_CAX_2510-4A:封装\tCONN-TH_4P-P2.54_CAX_2510-4A\tR0402\n\nJ27\n\t\t\t\t\n\n\t修改属性\tJ26:通道ID\t$17I175\t$17I174\n\n\t修改属性\tJ26:位号\tJ27\tJ26\n\n\t修改网络\tJ26:3\tFAN_OUT_TACH_RAW\tFAN_IN_TACH_RAW\n\nQ7\n\t\t\t\t\n\n\t修改封装\tSOT-23_L2.9-W1.3-P1.90-LS2.4-BR:封装\tSOT-23_L2.9-W1.3-P1.90-LS2.4-BR\tCONN-TH_4P-P2.54_CAX_2510-4A\n\nQ8\n\t\t\t\t\n\n\t修改封装\tSOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR:封装\tSOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR\tR0402" + }, + { + "top": 188, + "txt": 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at end of file diff --git a/.claude/_pcb1_i2c_l3_routes.json b/.claude/_pcb1_i2c_l3_routes.json index ecac97f..b70c15a 100644 --- a/.claude/_pcb1_i2c_l3_routes.json +++ b/.claude/_pcb1_i2c_l3_routes.json @@ -1 +1 @@ -{"segs": [["SCL", 1, 74.2254, 52.6537, 74.2254, 53.7792, 0.2], ["SCL", 2, 77.2, 52.0, 74.5, 52.0, 0.2], ["SCL", 2, 74.5, 52.0, 74.0, 51.5, 0.2], ["SCL", 2, 74.0, 51.5, 74.0, 51.3, 0.2], ["SCL", 2, 74.0, 51.3, 73.9, 51.2, 0.2], ["SCL", 1, 73.9, 51.2, 73.9, 51.3, 0.2], ["SCL", 1, 73.9, 51.3, 74.2, 51.6, 0.2], ["SCL", 1, 74.2, 51.6, 74.2, 51.9, 0.2], ["SCL", 16, 115.2, 37.2, 121.0, 43.0, 0.2], ["SCL", 16, 121.0, 43.0, 121.0, 43.2, 0.2], ["SCL", 2, 121.0, 43.2, 121.9, 44.1, 0.2], ["SCL", 2, 121.9, 44.1, 121.9, 44.4, 0.2], ["SCL", 2, 121.9, 44.4, 122.4, 44.9, 0.2], ["SCL", 2, 122.4, 44.9, 122.5, 44.9, 0.2], ["SCL", 2, 122.5, 44.9, 126.5, 48.9, 0.2], ["SCL", 2, 126.5, 48.9, 126.5, 49.0, 0.2], ["SCL", 2, 126.5, 49.0, 126.6, 49.1, 0.2], ["SCL", 2, 73.6, 51.2, 72.4, 50.0, 0.2], ["SCL", 2, 72.4, 50.0, 61.1, 50.0, 0.2], ["SCL", 16, 61.1, 50.0, 58.6, 50.0, 0.2], ["SCL", 16, 58.6, 50.0, 58.5, 49.9, 0.2], ["SCL", 16, 58.5, 49.9, 58.4, 49.9, 0.2], ["SCL", 2, 58.4, 49.9, 48.2, 49.9, 0.2], ["SCL", 16, 60.2, 50.1, 60.2, 62.2, 0.2], ["SCL", 16, 60.2, 62.2, 57.3, 65.1, 0.2], ["SCL", 16, 57.3, 65.1, 37.2, 65.1, 0.2], ["SCL", 16, 37.2, 65.1, 36.7, 64.6, 0.2], ["SCL", 16, 47.9, 65.1, 47.9, 75.8, 0.2], ["SCL", 16, 47.9, 75.8, 48.0, 75.9, 0.2], ["SCL", 1, 48.0, 75.9, 47.9, 75.8, 0.2], ["SCL", 1, 47.9, 75.8, 47.9, 73.3, 0.2], ["SCL", 1, 47.9, 73.3, 48.2, 73.0, 0.2], ["SCL", 1, 48.2, 73.0, 50.7, 73.0, 0.2], ["SCL", 1, 50.7, 73.0, 52.4, 74.7, 0.2], ["SCL", 16, 35.0, 64.6, 34.5, 65.1, 0.2], ["SCL", 16, 34.5, 65.1, 6.7, 65.1, 0.2], ["SCL", 16, 6.7, 65.1, 6.5, 64.9, 0.2], ["SCL", 16, 6.5, 64.9, 6.5, 60.3, 0.2], ["SCL", 16, 6.5, 60.3, 7.6, 59.2, 0.2], ["SCL", 16, 7.6, 59.2, 29.1, 59.2, 0.2], ["SCL", 16, 29.1, 59.2, 29.8, 58.5, 0.2], ["SCL", 16, 29.8, 58.5, 29.8, 58.4, 0.2], ["SCL", 1, 29.8, 58.4, 29.8, 58.1, 0.2], ["SCL", 1, 29.8, 58.1, 29.2, 57.5, 0.2], ["SCL", 1, 29.2, 57.5, 22.1, 57.5, 0.2], ["SCL", 1, 22.1, 57.5, 15.7, 51.1, 0.2], ["SCL", 1, 15.7, 51.1, 15.7, 51.0, 0.2], ["SCL", 1, 15.7, 51.0, 15.6, 50.9, 0.2], ["SCL", 16, 6.8, 65.1, 6.8, 87.6, 0.2], ["SCL", 1, 6.8, 87.6, 6.8, 93.6, 0.2], ["SDA", 1, 73.5752, 52.6537, 73.5752, 53.7792, 0.2], ["SDA", 16, 80.0, 41.7, 80.0, 42.6, 0.2], ["SDA", 16, 80.0, 42.6, 78.1, 44.5, 0.2], ["SDA", 16, 78.1, 44.5, 73.4, 44.5, 0.2], ["SDA", 16, 73.4, 44.5, 72.9, 45.0, 0.2], ["SDA", 16, 72.9, 45.0, 72.9, 54.8, 0.2], ["SDA", 1, 72.9, 54.8, 73.5, 54.2, 0.2], ["SDA", 1, 73.5, 54.2, 73.5, 53.8, 0.2], ["SDA", 2, 72.6, 54.8, 71.8, 54.8, 0.2], ["SDA", 2, 71.8, 54.8, 70.0, 53.0, 0.2], ["SDA", 2, 70.0, 53.0, 70.0, 51.9, 0.2], ["SDA", 2, 70.0, 51.9, 69.9, 51.8, 0.2], ["SDA", 1, 69.9, 51.8, 70.6, 51.1, 0.2], ["SDA", 1, 70.6, 51.1, 70.6, 48.7, 0.2], ["SDA", 1, 70.6, 48.7, 70.5, 48.6, 0.2], ["SDA", 2, 70.5, 48.6, 70.5, 48.8, 0.2], ["SDA", 2, 70.5, 48.8, 69.9, 49.4, 0.2], ["SDA", 2, 69.9, 49.4, 61.6, 49.4, 0.2], ["SDA", 2, 61.6, 49.4, 61.5, 49.3, 0.2], ["SDA", 2, 61.5, 49.3, 60.7, 49.3, 0.2], ["SDA", 2, 60.7, 49.3, 60.4, 49.6, 0.2], ["SDA", 2, 60.4, 49.6, 60.4, 50.4, 0.2], ["SDA", 2, 60.4, 50.4, 60.9, 50.9, 0.2], ["SDA", 16, 60.9, 50.9, 60.9, 59.6, 0.2], ["SDA", 1, 60.9, 59.6, 55.8, 59.6, 0.2], ["SDA", 1, 55.8, 59.6, 49.2, 53.0, 0.2], ["SDA", 1, 49.2, 53.0, 49.2, 52.9, 0.2], ["SDA", 1, 49.2, 52.9, 49.1, 52.8, 0.2], ["SDA", 16, 60.9, 59.9, 60.9, 64.0, 0.2], ["SDA", 16, 60.9, 64.0, 53.9, 71.0, 0.2], ["SDA", 16, 53.9, 71.0, 53.3, 71.0, 0.2], ["SDA", 16, 53.3, 71.0, 49.5, 74.8, 0.2], ["SDA", 16, 49.5, 74.8, 49.5, 75.5, 0.2], ["SDA", 16, 49.5, 75.5, 48.4, 76.6, 0.2], ["SDA", 16, 48.4, 76.6, 45.2, 76.6, 0.2], ["SDA", 16, 45.2, 76.6, 34.4, 65.8, 0.2], ["SDA", 16, 49.5, 75.6, 50.9, 77.0, 0.2], ["SDA", 16, 50.9, 77.0, 51.0, 77.0, 0.2], ["SDA", 16, 51.0, 77.0, 51.1, 77.1, 0.2], ["SDA", 16, 33.9, 66.0, 15.5, 84.4, 0.2], ["SDA", 16, 15.5, 84.4, 15.5, 85.5, 0.2], ["SDA", 16, 15.5, 85.5, 15.3, 85.7, 0.2], ["SDA", 16, 15.3, 85.7, 15.0, 85.7, 0.2], ["SDA", 16, 15.0, 85.7, 13.2, 87.5, 0.2], ["SDA", 16, 13.2, 87.5, 11.5, 87.5, 0.2], ["SDA", 16, 11.5, 87.5, 11.4, 87.6, 0.2], ["SDA", 2, 11.4, 87.6, 11.4, 94.0, 0.2], ["SDA", 2, 11.4, 94.0, 9.7, 95.7, 0.2], ["SDA", 1, 102.5, 31.0, 102.5, 38.1, 0.2], ["SDA", 16, 102.5, 38.1, 102.5, 49.0, 0.2], ["SDA", 2, 102.5, 49.0, 102.5, 56.9, 0.2], ["SDA", 16, 102.5, 56.9, 102.5, 64.9, 0.2], ["SDA", 16, 102.5, 64.9, 102.7, 65.1, 0.2], ["SDA", 16, 102.7, 65.1, 128.7, 65.1, 0.2], ["SDA", 16, 128.7, 65.1, 133.9, 70.3, 0.2], ["SDA", 16, 133.9, 70.3, 134.2, 70.3, 0.2], ["SDA", 16, 134.2, 70.3, 139.2, 75.3, 0.2], ["SDA", 16, 139.2, 75.3, 139.6, 75.3, 0.2], ["SDA", 16, 139.6, 75.3, 139.7, 75.4, 0.2]], "vias": [["SCL", 73.9, 51.2], ["SCL", 121.0, 43.2], ["SCL", 61.1, 50.0], ["SCL", 58.4, 49.9], ["SCL", 48.0, 75.9], ["SCL", 29.8, 58.4], ["SCL", 6.8, 87.6], ["SDA", 72.9, 54.8], ["SDA", 69.9, 51.8], ["SDA", 70.5, 48.6], ["SDA", 60.9, 50.9], ["SDA", 60.9, 59.6], ["SDA", 11.4, 87.6], ["SDA", 102.5, 38.1], ["SDA", 102.5, 49.0], ["SDA", 102.5, 56.9]]} \ No newline at end of file +{"segs": [["POGO3_PWR", 1, 125.4, 97.7, 125.7, 97.7, 0.2], ["POGO3_PWR", 2, 125.7, 97.7, 129.9, 97.7, 0.2], ["POGO3_PWR", 1, 129.9, 97.7, 131.6, 96.0, 0.2], ["POGO3_PWR", 1, 131.6, 96.0, 133.1, 96.0, 0.2], ["POGO3_PWR", 2, 133.1, 96.0, 136.1, 93.0, 0.2], ["POGO3_PWR", 1, 136.1, 93.0, 136.1, 87.6, 0.2], ["POGO3_PWR", 16, 136.1, 87.6, 140.6, 83.1, 0.2], ["POGO3_PWR", 16, 140.6, 83.1, 140.6, 75.9, 0.2], ["POGO3_PWR", 16, 140.6, 75.9, 140.7, 75.8, 0.2], ["POGO3_PWR", 16, 140.7, 75.8, 140.7, 72.8, 0.2], ["POGO3_PWR", 16, 140.7, 72.8, 132.8, 64.9, 0.2], ["POGO3_PWR", 16, 132.8, 64.9, 132.8, 64.7, 0.2], ["POGO3_PWR", 16, 132.8, 64.7, 132.7, 64.6, 0.2], ["POGO3_VDN", 2, 125.4, 93.9, 128.1, 96.6, 0.2], ["POGO3_VDN", 2, 128.1, 96.6, 128.8, 96.6, 0.2], ["POGO3_VDN", 2, 128.8, 96.6, 128.9, 96.7, 0.2], ["POGO3_VDN", 1, 128.9, 96.7, 129.6, 96.0, 0.2], ["POGO3_VDN", 1, 129.6, 96.0, 130.5, 96.0, 0.2], ["POGO3_VDN", 2, 130.5, 96.0, 131.2, 96.7, 0.2], ["POGO3_VDN", 2, 131.2, 96.7, 133.5, 96.7, 0.2], ["POGO3_VDN", 2, 133.5, 96.7, 136.3, 93.9, 0.2], ["POGO3_VDN", 1, 136.3, 93.9, 136.8, 93.4, 0.2], ["POGO3_VDN", 1, 136.8, 93.4, 136.8, 89.6, 0.2], ["POGO3_VDN", 1, 136.8, 89.6, 138.2, 88.2, 0.2], ["POGO3_VDN", 2, 138.2, 88.2, 138.7, 87.7, 0.2], ["POGO3_VDN", 2, 138.7, 87.7, 138.8, 87.7, 0.2], ["POGO3_VDN", 2, 138.8, 87.7, 138.9, 87.6, 0.2], ["POGO3_VDN", 2, 138.9, 87.6, 139.4, 87.6, 0.2], ["POGO3_VDN", 2, 139.4, 87.6, 140.4, 86.6, 0.2], ["POGO3_VDN", 16, 140.4, 86.6, 140.4, 84.7, 0.2], ["POGO3_VDN", 16, 140.4, 84.7, 142.2, 82.9, 0.2], ["POGO3_VDN", 16, 142.2, 82.9, 142.2, 82.8, 0.2], ["POGO3_VDN", 16, 142.2, 82.8, 143.3, 81.7, 0.2], ["POGO3_VDN", 16, 143.3, 81.7, 143.3, 79.0, 0.2], ["POGO3_VDN", 16, 143.3, 79.0, 141.7, 77.4, 0.2], ["POGO3_VDN", 16, 141.7, 77.4, 141.7, 73.8, 0.2], ["POGO3_VDN", 16, 141.7, 73.8, 142.2, 73.3, 0.2], ["POGO3_VDN", 16, 142.2, 73.3, 142.2, 71.8, 0.2], ["POGO3_VDN", 16, 142.2, 71.8, 137.8, 67.4, 0.2], ["POGO3_VDN", 16, 137.8, 67.4, 137.8, 64.7, 0.2], ["POGO3_VDN", 16, 137.8, 64.7, 137.7, 64.6, 0.2], ["POGO4_VDN", 1, 62.5, 31.8, 59.2, 35.1, 0.2], ["POGO4_VDN", 1, 59.2, 35.1, 57.4, 35.1, 0.2], ["POGO4_VDN", 1, 57.4, 35.1, 57.3, 35.2, 0.2], ["POGO4_VDN", 2, 57.3, 35.2, 57.1, 35.0, 0.2], ["POGO4_VDN", 2, 57.1, 35.0, 54.2, 35.0, 0.2], ["POGO4_VDN", 2, 54.2, 35.0, 53.4, 35.8, 0.2], ["POGO4_VDN", 16, 53.4, 35.8, 51.9, 37.3, 0.2], ["POGO4_VDN", 16, 51.9, 37.3, 38.1, 37.3, 0.2], ["POGO4_VDN", 16, 38.1, 37.3, 34.5, 40.9, 0.2], ["POGO4_VDN", 16, 34.5, 40.9, 34.5, 41.0, 0.2], ["POGO4_VDN", 1, 34.5, 41.0, 34.5, 56.4, 0.2], ["POGO4_VDN", 1, 34.5, 56.4, 32.5, 58.4, 0.2], ["POGO4_VDN", 16, 32.5, 58.4, 31.0, 59.9, 0.2], ["POGO4_VDN", 16, 31.0, 59.9, 27.0, 59.9, 0.2], ["POGO4_VDN", 16, 27.0, 59.9, 26.5, 60.4, 0.2], ["POGO5_PWR", 1, 142.9, 27.8, 142.9, 28.4, 0.2], ["POGO5_PWR", 2, 142.9, 28.4, 142.9, 30.5, 0.2], ["POGO5_PWR", 2, 142.9, 30.5, 143.0, 30.6, 0.2], ["POGO5_PWR", 1, 143.0, 30.6, 143.4, 31.0, 0.2], ["POGO5_PWR", 1, 143.4, 31.0, 143.4, 33.2, 0.2], ["POGO5_PWR", 2, 143.4, 33.2, 143.4, 35.4, 0.2], ["POGO5_PWR", 2, 143.4, 35.4, 143.1, 35.7, 0.2], ["POGO5_PWR", 2, 143.1, 35.7, 142.9, 35.7, 0.2], ["POGO5_PWR", 2, 142.9, 35.7, 142.4, 36.2, 0.2], ["POGO5_PWR", 2, 142.4, 36.2, 142.0, 36.2, 0.2], ["POGO5_PWR", 2, 142.0, 36.2, 141.9, 36.3, 0.2], ["POGO5_PWR", 16, 141.9, 36.3, 144.8, 39.2, 0.2], ["POGO5_PWR", 16, 144.8, 39.2, 144.8, 39.7, 0.2], ["POGO5_PWR", 16, 144.8, 39.7, 145.1, 40.0, 0.2], ["POGO5_PWR", 16, 145.1, 40.0, 147.8, 40.0, 0.2], ["POGO5_PWR", 16, 147.8, 40.0, 148.1, 40.3, 0.2], ["POGO5_PWR", 16, 148.1, 40.3, 148.1, 46.0, 0.2], ["POGO5_PWR", 16, 148.1, 46.0, 135.6, 58.5, 0.2], ["POGO5_PWR", 16, 135.6, 58.5, 134.6, 58.5, 0.2], ["POGO5_PWR", 16, 134.6, 58.5, 132.7, 60.4, 0.2], ["POGO5_VUP", 2, 146.9, 27.7, 149.9, 27.7, 0.2], ["POGO5_VUP", 2, 149.9, 27.7, 150.3, 28.1, 0.2], ["POGO5_VUP", 2, 150.3, 28.1, 150.3, 30.7, 0.2], ["POGO5_VUP", 1, 150.3, 30.7, 150.3, 34.3, 0.2], ["POGO5_VUP", 16, 150.3, 34.3, 150.3, 34.4, 0.2], ["POGO5_VUP", 16, 150.3, 34.4, 150.1, 34.6, 0.2], ["POGO5_VUP", 16, 150.1, 34.6, 150.1, 47.7, 0.2], ["POGO5_VUP", 16, 150.1, 47.7, 149.6, 48.2, 0.2], ["POGO5_VUP", 16, 149.6, 48.2, 147.4, 48.2, 0.2], ["POGO5_VUP", 16, 147.4, 48.2, 135.2, 60.4, 0.2], ["SCL", 1, 74.2239, 52.6517, 74.2239, 53.7772, 0.2], ["SCL", 16, 115.9, 39.2, 116.3, 38.8, 0.2], ["SCL", 16, 116.3, 38.8, 116.3, 38.1, 0.2], ["SCL", 16, 116.3, 38.1, 115.9, 37.7, 0.2], ["SCL", 16, 115.9, 37.7, 115.8, 37.7, 0.2], ["SCL", 16, 115.8, 37.7, 115.4, 37.3, 0.2], ["SCL", 16, 115.4, 37.3, 115.3, 37.3, 0.2], ["SCL", 16, 115.3, 37.3, 115.2, 37.2, 0.2], ["SCL", 1, 106.1, 33.5, 106.1, 30.2, 0.2], ["SCL", 1, 106.1, 30.2, 107.5, 28.8, 0.2], ["SCL", 16, 116.3, 38.9, 117.0, 38.9, 0.2], ["SCL", 16, 117.0, 38.9, 119.9, 41.8, 0.2], ["SCL", 16, 119.9, 41.8, 119.9, 42.1, 0.2], ["SCL", 2, 119.9, 42.1, 122.0, 44.2, 0.2], ["SCL", 2, 122.0, 44.2, 122.0, 44.5, 0.2], ["SCL", 2, 122.0, 44.5, 122.3, 44.8, 0.2], ["SCL", 2, 122.3, 44.8, 122.4, 44.8, 0.2], ["SCL", 2, 122.4, 44.8, 126.1, 48.5, 0.2], ["SCL", 2, 126.1, 48.5, 126.1, 48.6, 0.2], ["SCL", 2, 126.1, 48.6, 126.2, 48.7, 0.2], ["SCL", 2, 77.2, 52.0, 73.7, 52.0, 0.2], ["SCL", 2, 73.7, 52.0, 72.9, 51.2, 0.2], ["SCL", 1, 72.9, 51.2, 73.8, 51.2, 0.2], ["SCL", 1, 73.8, 51.2, 74.2, 51.6, 0.2], ["SCL", 1, 74.2, 51.6, 74.2, 51.9, 0.2], ["SCL", 2, 72.6, 51.2, 71.4, 50.0, 0.2], ["SCL", 2, 71.4, 50.0, 61.1, 50.0, 0.2], ["SCL", 16, 61.1, 50.0, 48.3, 50.0, 0.2], ["SCL", 16, 48.3, 50.0, 48.2, 49.9, 0.2], ["SCL", 16, 60.2, 50.1, 60.2, 62.2, 0.2], ["SCL", 16, 60.2, 62.2, 57.3, 65.1, 0.2], ["SCL", 16, 57.3, 65.1, 37.2, 65.1, 0.2], ["SCL", 16, 37.2, 65.1, 36.7, 64.6, 0.2], ["SCL", 16, 47.9, 65.1, 47.9, 75.8, 0.2], ["SCL", 16, 47.9, 75.8, 48.0, 75.9, 0.2], ["SCL", 1, 48.0, 75.9, 47.9, 75.8, 0.2], ["SCL", 1, 47.9, 75.8, 47.9, 73.3, 0.2], ["SCL", 1, 47.9, 73.3, 48.2, 73.0, 0.2], ["SCL", 1, 48.2, 73.0, 50.7, 73.0, 0.2], ["SCL", 1, 50.7, 73.0, 52.4, 74.7, 0.2], ["SCL", 16, 35.0, 64.6, 34.5, 65.1, 0.2], ["SCL", 16, 34.5, 65.1, 6.7, 65.1, 0.2], ["SCL", 16, 6.7, 65.1, 6.5, 64.9, 0.2], ["SCL", 16, 6.5, 64.9, 6.5, 60.3, 0.2], ["SCL", 16, 6.5, 60.3, 7.6, 59.2, 0.2], ["SCL", 16, 7.6, 59.2, 28.4, 59.2, 0.2], ["SCL", 16, 28.4, 59.2, 29.1, 58.5, 0.2], ["SCL", 16, 29.1, 58.5, 29.1, 58.4, 0.2], ["SCL", 1, 29.1, 58.4, 29.1, 58.0, 0.2], ["SCL", 1, 29.1, 58.0, 28.6, 57.5, 0.2], ["SCL", 1, 28.6, 57.5, 22.1, 57.5, 0.2], ["SCL", 1, 22.1, 57.5, 15.7, 51.1, 0.2], ["SCL", 16, 6.8, 65.1, 6.8, 87.6, 0.2], ["SCL", 1, 6.8, 87.6, 6.8, 93.6, 0.2], ["SDA", 1, 73.5762, 52.6517, 73.5762, 53.7772, 0.2], ["SDA", 2, 84.4, 41.2, 82.9, 42.7, 0.2], ["SDA", 2, 82.9, 42.7, 82.9, 44.0, 0.2], ["SDA", 2, 82.9, 44.0, 82.8, 44.1, 0.2], ["SDA", 16, 81.3, 49.9, 78.9, 49.9, 0.2], ["SDA", 16, 78.9, 49.9, 75.5, 53.3, 0.2], ["SDA", 16, 75.5, 53.3, 74.7, 53.3, 0.2], ["SDA", 16, 74.7, 53.3, 73.6, 54.4, 0.2], ["SDA", 1, 73.6, 54.4, 73.6, 53.8, 0.2], ["SDA", 1, 73.3, 54.4, 72.9, 54.8, 0.2], ["SDA", 1, 72.9, 54.8, 71.0, 54.8, 0.2], ["SDA", 1, 71.0, 54.8, 70.9, 54.7, 0.2], ["SDA", 1, 70.9, 54.7, 68.9, 54.7, 0.2], ["SDA", 1, 68.9, 54.7, 67.8, 55.8, 0.2], ["SDA", 2, 67.8, 55.8, 67.0, 55.0, 0.2], ["SDA", 2, 67.0, 55.0, 66.6, 55.0, 0.2], ["SDA", 2, 66.6, 55.0, 66.5, 54.9, 0.2], ["SDA", 1, 66.5, 54.9, 64.4, 54.9, 0.2], ["SDA", 1, 64.4, 54.9, 59.7, 59.6, 0.2], ["SDA", 1, 59.7, 59.6, 55.8, 59.6, 0.2], ["SDA", 1, 55.8, 59.6, 49.2, 53.0, 0.2], ["SDA", 16, 60.9, 58.5, 60.9, 64.0, 0.2], ["SDA", 16, 60.9, 64.0, 53.9, 71.0, 0.2], ["SDA", 16, 53.9, 71.0, 53.3, 71.0, 0.2], ["SDA", 16, 53.3, 71.0, 49.5, 74.8, 0.2], ["SDA", 16, 49.5, 74.8, 49.5, 75.5, 0.2], ["SDA", 16, 49.5, 75.5, 48.4, 76.6, 0.2], ["SDA", 16, 48.4, 76.6, 45.2, 76.6, 0.2], ["SDA", 16, 45.2, 76.6, 34.4, 65.8, 0.2], ["SDA", 16, 49.5, 75.6, 50.9, 77.0, 0.2], ["SDA", 16, 50.9, 77.0, 51.0, 77.0, 0.2], ["SDA", 16, 51.0, 77.0, 51.1, 77.1, 0.2], ["SDA", 16, 33.9, 66.0, 15.5, 84.4, 0.2], ["SDA", 16, 15.5, 84.4, 15.5, 85.5, 0.2], ["SDA", 16, 15.5, 85.5, 15.3, 85.7, 0.2], ["SDA", 16, 15.3, 85.7, 15.0, 85.7, 0.2], ["SDA", 16, 15.0, 85.7, 13.2, 87.5, 0.2], ["SDA", 16, 13.2, 87.5, 11.5, 87.5, 0.2], ["SDA", 16, 11.5, 87.5, 11.4, 87.6, 0.2], ["SDA", 2, 11.4, 87.6, 11.4, 94.0, 0.2], ["SDA", 2, 11.4, 94.0, 9.7, 95.7, 0.2], ["SDA", 16, 102.5, 57.2, 102.5, 64.9, 0.2], ["SDA", 16, 102.5, 64.9, 102.7, 65.1, 0.2], ["SDA", 16, 102.7, 65.1, 128.7, 65.1, 0.2], ["SDA", 16, 128.7, 65.1, 138.9, 75.3, 0.2], ["SDA", 16, 138.9, 75.3, 139.6, 75.3, 0.2], ["SDA", 16, 139.6, 75.3, 139.7, 75.4, 0.2]], "vias": [["POGO3_PWR", 125.7, 97.7], ["POGO3_PWR", 129.9, 97.7], ["POGO3_PWR", 133.1, 96.0], ["POGO3_PWR", 136.1, 93.0], ["POGO3_PWR", 136.1, 87.6], ["POGO3_VDN", 125.4, 93.9], ["POGO3_VDN", 128.9, 96.7], ["POGO3_VDN", 130.5, 96.0], ["POGO3_VDN", 136.3, 93.9], ["POGO3_VDN", 138.2, 88.2], ["POGO3_VDN", 140.4, 86.6], ["POGO4_VDN", 57.3, 35.2], ["POGO4_VDN", 53.4, 35.8], ["POGO4_VDN", 34.5, 41.0], ["POGO4_VDN", 32.5, 58.4], ["POGO5_PWR", 142.9, 28.4], ["POGO5_PWR", 143.0, 30.6], ["POGO5_PWR", 143.4, 33.2], ["POGO5_PWR", 141.9, 36.3], ["POGO5_VUP", 146.9, 27.7], ["POGO5_VUP", 150.3, 30.7], ["POGO5_VUP", 150.3, 34.3], ["SCL", 119.9, 42.1], ["SCL", 72.9, 51.2], ["SCL", 61.1, 50.0], ["SCL", 48.0, 75.9], ["SCL", 29.1, 58.4], ["SCL", 6.8, 87.6], ["SDA", 73.6, 54.4], ["SDA", 67.8, 55.8], ["SDA", 66.5, 54.9], ["SDA", 60.9, 58.5], ["SDA", 11.4, 87.6]]} \ No newline at end of file diff --git a/.claude/_pcb1_place_now.json b/.claude/_pcb1_place_now.json index f043a40..601d4e3 100644 --- a/.claude/_pcb1_place_now.json +++ b/.claude/_pcb1_place_now.json @@ -1 +1 @@ -{"comp": [["C1", 25.5001, 68.0001, 0, 1], ["C2", 6.5001, 84.5, 0, 1], ["C3", 16, 84.5, 0, 1], ["C4", 30.5001, 80.0001, 180, 1], ["C5", 30.5001, 83.0001, 180, 1], ["C6", 30.5001, 86.0001, 180, 1], ["C7", 19, 108.4999, 0, 1], ["C8", 23.5001, 108.4999, 0, 1], ["C9", 19, 112.4999, 0, 1], ["C10", 24.5001, 112.4999, 0, 1], ["C11", 11, 99.0001, 0, 1], ["C101", 12.2999, 26.8, 90, 1], ["C102", 12.2999, 30.45, 90, 1], ["C103", 12.2999, 23.2001, 90, 1], ["C104", 21.2999, 24.5001, 90, 1], ["C105", 20.7, 29.1, 0, 1], ["C106", 15.0929, 42.6001, 0, 1], ["C107", 15.0929, 40.5, 0, 1], ["C108", 16.7, 37.9999, 0, 1], ["C109", 28.2999, 18.5001, 0, 1], ["C110", 21.8001, 18.5001, 0, 1], ["C111", 21.8001, 20.7, 0, 1], ["C112", 18.2999, 20.7, 0, 1], ["C113", 18.8001, 51.8, 0, 1], ["C114", 22.8001, 47.5, 0, 1], ["C201", 55.5889, 98.7001, 270, 1], ["C202", 55.5889, 95.0501, 270, 1], ["C203", 55.5889, 102.3, 270, 1], ["C204", 46.5889, 101.0001, 270, 1], ["C205", 47.1889, 96.4001, 180, 1], ["C206", 52.7959, 82.9, 180, 1], ["C207", 52.7959, 85.0001, 180, 1], ["C208", 51.1889, 87.5, 180, 1], ["C209", 39.5889, 107, 180, 1], ["C210", 46.0891, 107, 180, 1], ["C211", 46.0891, 104.7999, 180, 1], ["C212", 49.5889, 104.7999, 180, 1], ["C213", 49.0891, 73.6999, 180, 1], ["C214", 45.0891, 78.0001, 180, 1], ["C301", 143.969, 98.7001, 270, 1], ["C302", 143.969, 95.0501, 270, 1], ["C303", 143.969, 102.3, 270, 1], ["C304", 134.969, 101.0001, 270, 1], ["C305", 135.5689, 96.4001, 180, 1], ["C306", 141.176, 82.9, 180, 1], ["C307", 141.176, 85.0001, 180, 1], ["C308", 139.5689, 87.5, 180, 1], ["C309", 127.969, 107, 180, 1], ["C310", 134.4691, 107, 180, 1], ["C311", 134.4691, 104.7999, 180, 1], ["C312", 137.969, 104.7999, 180, 1], ["C313", 137.4691, 73.6999, 180, 1], ["C314", 133.4691, 78.0001, 180, 1], ["C401", 43.9689, 26.8, 90, 1], ["C402", 43.9689, 30.45, 90, 1], ["C403", 43.9689, 23.2001, 90, 1], ["C404", 52.9689, 24.5001, 90, 1], ["C405", 52.369, 29.1, 0, 1], ["C406", 46.7619, 42.6001, 0, 1], ["C407", 46.7619, 40.5, 0, 1], ["C408", 48.369, 37.9999, 0, 1], ["C409", 59.9689, 18.5001, 0, 1], ["C410", 53.469, 18.5001, 0, 1], ["C411", 53.469, 20.7, 0, 1], ["C412", 49.9689, 20.7, 0, 1], ["C413", 50.469, 51.8, 0, 1], ["C414", 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1], ["J22", 154.4, 51.9999, 90, 1], ["L2", 25.5001, 104, 0, 1], ["L101", 19, 33.5001, 180, 1], ["L201", 48.8889, 92.0001, 0, 1], ["L301", 137.269, 92.0001, 0, 1], ["L401", 50.6689, 33.5001, 180, 1], ["L501", 130.1999, 33.5001, 180, 1], ["Q1", 24, 74.5, 270, 1], ["Q3", 25.5001, 119, 0, 1], ["Q101", 22.1, 50.9999, 0, 1], ["Q102", 22.1, 54.9999, 0, 1], ["Q103", 32.2999, 27.5001, 0, 1], ["Q104", 36.2999, 27.5001, 0, 1], ["Q105", 32.2999, 31.5001, 0, 1], ["Q201", 45.7891, 74.5, 180, 1], ["Q202", 45.7891, 70.5, 180, 1], ["Q203", 35.589, 98.0001, 180, 1], ["Q204", 31.589, 98.0001, 180, 1], ["Q205", 35.589, 94.0001, 180, 1], ["Q301", 134.1689, 74.5, 180, 1], ["Q302", 134.1689, 70.5, 180, 1], ["Q303", 123.969, 98.0001, 180, 1], ["Q304", 119.969, 98.0001, 180, 1], ["Q305", 123.969, 94.0001, 180, 1], ["Q401", 53.769, 50.9999, 0, 1], ["Q402", 53.769, 54.9999, 0, 1], ["Q403", 63.9689, 27.5001, 0, 1], ["Q404", 67.9689, 27.5001, 0, 1], ["Q405", 63.9689, 31.5001, 0, 1], ["Q501", 133.3, 50.9999, 0, 1], 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32.2999, 37.9999, 0, 1], ["R124", 36.2999, 37.9999, 0, 1], ["R125", 32.2999, 40.9999, 0, 1], ["R201", 56.5889, 107, 180, 1], ["R202", 56.5889, 104.7999, 180, 1], ["R203", 42.5889, 107, 180, 1], ["R204", 42.5889, 104.7999, 180, 1], ["R205", 39.5889, 104.7999, 180, 1], ["R206", 49.5889, 107, 180, 1], ["R207", 53.089, 107, 180, 1], ["R208", 53.089, 104.7999, 180, 1], ["R209", 48.5889, 78.0001, 180, 1], ["R210", 48.5889, 80.0001, 180, 1], ["R211", 48.5889, 82.0001, 180, 1], ["R212", 45.0891, 80.0001, 180, 1], ["R213", 45.0891, 82.0001, 180, 1], ["R214", 41.5889, 78.0001, 180, 1], ["R215", 41.5889, 80.0001, 180, 1], ["R216", 41.5889, 82.0001, 180, 1], ["R217", 41.5889, 84.0001, 180, 1], ["R218", 43.1889, 74.5, 180, 1], ["R219", 41.7891, 70.0001, 270, 1], ["R220", 31.589, 94.0001, 180, 1], ["R221", 35.589, 90.4999, 180, 1], ["R222", 31.589, 90.4999, 180, 1], ["R223", 35.589, 87.5, 180, 1], ["R224", 31.589, 87.5, 180, 1], ["R225", 35.589, 84.5, 180, 1], ["R301", 144.969, 107, 180, 1], ["R302", 144.969, 104.7999, 180, 1], ["R303", 130.969, 107, 180, 1], ["R304", 130.969, 104.7999, 180, 1], ["R305", 127.969, 104.7999, 180, 1], ["R306", 137.969, 107, 180, 1], ["R307", 141.4691, 107, 180, 1], ["R308", 141.4691, 104.7999, 180, 1], ["R309", 136.969, 78.0001, 180, 1], ["R310", 136.969, 80.0001, 180, 1], ["R311", 136.969, 82.0001, 180, 1], ["R312", 133.4691, 80.0001, 180, 1], ["R313", 133.4691, 82.0001, 180, 1], ["R314", 129.969, 78.0001, 180, 1], ["R315", 129.969, 80.0001, 180, 1], ["R316", 129.969, 82.0001, 180, 1], ["R317", 129.969, 84.0001, 180, 1], ["R318", 131.569, 74.5, 180, 1], ["R319", 130.1689, 70.0001, 270, 1], ["R320", 119.969, 94.0001, 180, 1], ["R321", 123.969, 90.4999, 180, 1], ["R322", 119.969, 90.4999, 180, 1], ["R323", 123.969, 87.5, 180, 1], ["R324", 119.969, 87.5, 180, 1], ["R325", 123.969, 84.5, 180, 1], ["R401", 42.9689, 18.5001, 0, 1], ["R402", 42.9689, 20.7, 0, 1], ["R403", 56.9689, 18.5001, 0, 1], ["R404", 56.9689, 20.7, 0, 1], ["R405", 59.9689, 20.7, 0, 1], ["R406", 49.9689, 18.5001, 0, 1], ["R407", 46.469, 18.5001, 0, 1], ["R408", 46.469, 20.7, 0, 1], ["R409", 50.9689, 47.5, 0, 1], ["R410", 50.9689, 45.5, 0, 1], ["R411", 50.9689, 43.5, 0, 1], ["R412", 54.469, 45.5, 0, 1], ["R413", 54.469, 43.5, 0, 1], ["R414", 57.9689, 47.5, 0, 1], ["R415", 57.9689, 45.5, 0, 1], ["R416", 57.9689, 43.5, 0, 1], ["R417", 57.9689, 41.5, 0, 1], ["R418", 56.3689, 50.9999, 0, 1], ["R419", 57.769, 55.5, 90, 1], ["R420", 67.9689, 31.5001, 0, 1], ["R421", 63.9689, 34.9999, 0, 1], ["R422", 67.9689, 34.9999, 0, 1], ["R423", 63.9689, 37.9999, 0, 1], ["R424", 67.9689, 37.9999, 0, 1], ["R425", 63.9689, 40.9999, 0, 1], ["R501", 122.4999, 18.5001, 0, 1], ["R502", 122.4999, 20.7, 0, 1], ["R503", 136.5001, 18.5001, 0, 1], ["R504", 136.5001, 20.7, 0, 1], ["R505", 139.5001, 20.7, 0, 1], ["R506", 129.5001, 18.5001, 0, 1], ["R507", 126, 18.5001, 0, 1], ["R508", 126, 20.7, 0, 1], ["R509", 130.5001, 47.5, 0, 1], ["R510", 130.5001, 45.5, 0, 1], ["R511", 130.5001, 43.5, 0, 1], ["R512", 134, 45.5, 0, 1], ["R513", 134, 43.5, 0, 1], ["R514", 137.5001, 47.5, 0, 1], ["R515", 137.5001, 45.5, 0, 1], ["R516", 137.5001, 43.5, 0, 1], ["R517", 137.5001, 41.5, 0, 1], ["R518", 135.8999, 50.9999, 0, 1], ["R519", 137.3, 55.5, 90, 1], ["R520", 147.5001, 31.5001, 0, 1], ["R521", 143.5001, 34.9999, 0, 1], ["R522", 147.5001, 34.9999, 0, 1], ["R523", 143.5001, 37.9999, 0, 1], ["R524", 147.5001, 37.9999, 0, 1], ["R525", 143.5001, 40.9999, 0, 1], ["R601", 98.1009, 14.1821, 90, 1], ["R602", 150.703, 51.194, 90, 1], ["R603", 150.703, 54.1939, 90, 1], ["R604", 86.3389, 28.4729, 0, 1], ["R605", 98.1509, 18.194, 90, 1], ["R606", 78.124, 45.2079, 0, 1], ["R607", 79.996, 45.1531, 0, 1], ["R608", 72.137, 46.7469, 90, 1], ["R609", 91.8921, 56.6811, 0, 1], ["R614", 77.058, 39.8229, 90, 1], ["R615", 78.6569, 35.526, 0, 1], ["R616", 107.048, 36.5219, 90, 1], ["R617", 108.647, 32.225, 0, 1], ["R618", 77.4319, 9.524, 0, 1], ["R619", 76.9851, 12.2431, 90, 1], ["Rs6", 6.5001, 93.4999, 0, 1], ["Rs101", 14.2999, 56.8, 180, 1], ["Rs201", 53.5889, 68.6999, 0, 1], ["Rs301", 141.969, 68.6999, 0, 1], ["Rs401", 45.9689, 56.8, 180, 1], ["Rs501", 125.4999, 56.8, 180, 1], ["RT601", 70.8, 35.9999, 90, 1], ["RT602", 70.8, 25.9999, 90, 1], ["U1", 16.8001, 27.5001, 0, 1], ["U2", 51.0891, 98.0001, 180, 1], ["U3", 139.4691, 98.0001, 180, 1], ["U4", 48.469, 27.5001, 0, 1], ["U5", 128, 27.5001, 0, 1], ["U6", 79.58, 38.0101, 0, 1], ["U7", 109.57, 34.7101, 0, 1], ["U8", 14.2999, 51.8, 0, 1], ["U9", 53.5889, 73.6999, 180, 1], ["U10", 141.969, 73.6999, 180, 1], ["U11", 45.9689, 51.8, 0, 1], ["U12", 125.4999, 51.8, 0, 1], ["U13", 6.5001, 99.0001, 0, 1], ["U14", 14.2999, 45.8, 180, 1], ["U15", 53.5889, 79.7001, 0, 1], ["U16", 141.969, 79.7001, 0, 1], ["U17", 45.9689, 45.8, 180, 1], ["U18", 125.4999, 45.8, 180, 1], ["U19", 19, 104, 0, 1], ["U20", 88.0001, 18.2001, 180, 1], ["U21", 92.25, 52.37, 0, 1], ["U22", 92.84, 38.0101, 0, 1], ["U23", 76.5, 49.6301, 0, 1], ["U29", 12.5001, 94.0001, 0, 1], ["C731", 68.2, 72.0001, 270, 1], ["C732", 70.6999, 72.0001, 270, 1], ["C733", 64.0001, 69.6001, 180, 1], ["C734", 77.5, 78.0001, 90, 1], ["C735", 80.0001, 78.0001, 90, 1], ["L3", 70.5, 78.0001, 0, 1], ["R706", 59.9999, 73.5, 0, 1], ["R707", 59.9999, 71.5, 180, 1], ["R731", 101.4999, 78.0001, 0, 1], ["U30", 64.0001, 72.0001, 0, 1], ["U33", 92.0001, 71.0001, 0, 1], ["R733", 98.0001, 80.5, 0, 1], ["R734", 101.4999, 80.5, 0, 1], ["C738", 102, 74.0001, 0, 1], ["R730", 98.0001, 78.0001, 0, 1], ["D2", 108.4999, 69.5, 0, 1], ["R732", 105, 78.0001, 0, 1], ["C739", 107, 74.0001, 0, 1], ["Q6", 102, 69.5, 0, 1], ["J24", 31.9999, 62.5, 0, 1], ["J25", 128, 62.5, 0, 1], ["F1", 17.5001, 74.5, 90, 1], ["R9A", 18, 100.4999, 0, 1], ["R9B", 18, 96.4999, 0, 1], ["R9C", 25.9999, 96.4999, 0, 1], ["R9D", 25.9999, 92.0001, 0, 1], ["R9E", 18, 92.0001, 0, 1], ["J1", 8.5001, 72.0001, 270, 1], ["J26", 5, 16, 0, 1], ["J27", 5, 29.9999, 0, 1], ["J28", 100.0001, 112.7001, 0, 1], ["J29", 154.9001, 16, 0, 1], ["J30", 154.9001, 29.9999, 0, 1]], "th": [["GND", 5, 5, 5.999, 5.999], ["GND", 155, 5, 5.999, 5.999], ["GND", 5, 120, 5.999, 5.999], ["GND", 155, 120, 5.999, 5.999], ["GND", 8.25, 84.5, 1.6, 1.6], ["$1N236", 4.75, 84.5, 1.6, 1.6], ["GND", 17.75, 84.5, 1.6, 1.6], ["$1N236", 14.25, 84.5, 1.6, 1.6], ["GND", 151.926, 48.8, 0, 0], ["GND", 151.926, 55.2, 0, 0], ["", 151.926, 54.4, 0, 0], ["", 151.926, 49.6, 0, 0], ["GND", 156.874, 56.325, 1.199, 1.801], ["GND", 152.694, 56.325, 1.199, 1.999], ["GND", 152.694, 47.675, 1.199, 1.999], ["GND", 156.874, 47.675, 1.199, 1.801], ["GND", 16.8, 27.5, 0, 0], ["GND", 51.089, 98, 0, 0], ["GND", 139.469, 98, 0, 0], ["GND", 48.469, 27.5, 0, 0], ["GND", 128, 27.5, 0, 0], ["GND", 79.58, 38.01, 0, 0], ["GND", 109.57, 34.71, 0, 0], ["GND", 7.87, 61.23, 1.575, 1.801], ["VO1_P", 7.87, 63.77, 1.801, 1.801], ["GND", 10.41, 61.23, 1.801, 1.801], ["VO1_P", 10.41, 63.77, 1.801, 1.801], ["GND", 12.95, 61.23, 1.801, 1.801], ["VO1_P", 12.95, 63.77, 1.801, 1.801], ["GND", 15.49, 61.23, 1.801, 1.801], ["+5V", 15.49, 63.77, 1.801, 1.801], ["GND", 18.03, 61.23, 1.801, 1.801], ["+5V", 18.03, 63.77, 1.801, 1.801], ["POGO4_PWR", 20.57, 61.23, 1.801, 1.801], ["POGO1_PWR", 20.57, 63.77, 1.801, 1.801], ["POGO4_VUP", 23.11, 61.23, 1.801, 1.801], ["POGO1_VUP", 23.11, 63.77, 1.801, 1.801], ["POGO4_VDN", 25.65, 61.23, 1.801, 1.801], ["POGO1_VDN", 25.65, 63.77, 1.801, 1.801], ["EDL_EN4", 28.19, 61.23, 1.801, 1.801], ["EDL_EN1", 28.19, 63.77, 1.801, 1.801], ["VBUS_EN4", 30.73, 61.23, 1.801, 1.801], ["VBUS_EN1", 30.73, 63.77, 1.801, 1.801], ["+5V", 33.27, 61.23, 1.801, 1.801], ["SDA", 33.27, 63.77, 1.801, 1.801], ["+5V", 35.81, 61.23, 1.801, 1.801], ["SCL", 35.81, 63.77, 1.801, 1.801], ["UP_VBUS_DET", 38.35, 61.23, 1.801, 1.801], ["GND", 38.35, 63.77, 1.801, 1.801], ["GND", 40.89, 61.23, 1.801, 1.801], ["GND", 40.89, 63.77, 1.801, 1.801], ["VO4_P", 43.43, 61.23, 1.801, 1.801], ["GND", 43.43, 63.77, 1.801, 1.801], ["VO4_P", 45.97, 61.23, 1.801, 1.801], ["GND", 45.97, 63.77, 1.801, 1.801], ["VO4_P", 48.51, 61.23, 1.801, 1.801], ["GND", 48.51, 63.77, 1.801, 1.801], ["GND", 51.05, 61.23, 1.801, 1.801], ["VO2_P", 51.05, 63.77, 1.801, 1.801], ["GND", 53.59, 61.23, 1.801, 1.801], ["VO2_P", 53.59, 63.77, 1.801, 1.801], ["GND", 56.13, 61.23, 1.801, 1.801], ["VO2_P", 56.13, 63.77, 1.801, 1.801], ["+5V", 103.87, 61.23, 1.575, 1.801], ["+5V", 103.87, 63.77, 1.801, 1.801], ["+5V", 106.41, 61.23, 1.801, 1.801], ["+5V", 106.41, 63.77, 1.801, 1.801], ["VBUS_EN5", 108.95, 61.23, 1.801, 1.801], ["POGO2_PWR", 108.95, 63.77, 1.801, 1.801], ["EDL_EN5", 111.49, 61.23, 1.801, 1.801], ["POGO2_VUP", 111.49, 63.77, 1.801, 1.801], ["GND", 114.03, 61.23, 1.801, 1.801], ["POGO2_VDN", 114.03, 63.77, 1.801, 1.801], ["GND", 116.57, 61.23, 1.801, 1.801], ["EDL_EN2", 116.57, 63.77, 1.801, 1.801], ["GND", 119.11, 61.23, 1.801, 1.801], ["VBUS_EN2", 119.11, 63.77, 1.801, 1.801], ["GND", 121.65, 61.23, 1.801, 1.801], ["HUB_RST", 121.65, 63.77, 1.801, 1.801], ["VO5_P", 124.19, 61.23, 1.801, 1.801], ["GND", 124.19, 63.77, 1.801, 1.801], ["VO5_P", 126.73, 61.23, 1.801, 1.801], ["GND", 126.73, 63.77, 1.801, 1.801], ["VO5_P", 129.27, 61.23, 1.801, 1.801], ["GND", 129.27, 63.77, 1.801, 1.801], ["POGO5_PWR", 131.81, 61.23, 1.801, 1.801], ["POGO3_PWR", 131.81, 63.77, 1.801, 1.801], ["POGO5_VUP", 134.35, 61.23, 1.801, 1.801], ["POGO3_VUP", 134.35, 63.77, 1.801, 1.801], ["POGO5_VDN", 136.89, 61.23, 1.801, 1.801], ["POGO3_VDN", 136.89, 63.77, 1.801, 1.801], ["GND", 139.43, 61.23, 1.801, 1.801], ["VO3_P", 139.43, 63.77, 1.801, 1.801], ["GND", 141.97, 61.23, 1.801, 1.801], ["VO3_P", 141.97, 63.77, 1.801, 1.801], ["GND", 144.51, 61.23, 1.801, 1.801], ["VO3_P", 144.51, 63.77, 1.801, 1.801], ["GND", 147.05, 61.23, 1.801, 1.801], ["EDL_EN3", 147.05, 63.77, 1.801, 1.801], ["GND", 149.59, 61.23, 1.801, 1.801], ["VBUS_EN3", 149.59, 63.77, 1.801, 1.801], ["+5V", 152.13, 61.23, 1.801, 1.801], ["+5V", 152.13, 63.77, 1.801, 1.801], ["GND", 13.5, 74.5, 2.499, 2.499], ["$1N223", 13.5, 69.5, 2.499, 2.499], ["", 3.5, 66.5, 1.801, 1.801], ["", 3.5, 77.5, 1.801, 1.801], ["+12V", 2.46, 16, 1.801, 1.801], ["$17N151", 5, 16, 1.801, 1.801], ["$17N154", 7.54, 16, 1.801, 1.801], ["+12V", 2.46, 30, 1.801, 1.801], ["$17N151", 5, 30, 1.801, 1.801], ["$17N154", 7.54, 30, 1.801, 1.801], ["+12V", 97.46, 112.7, 1.801, 1.801], ["$17N151", 100, 112.7, 1.801, 1.801], ["$17N154", 102.54, 112.7, 1.801, 1.801], ["+12V", 152.36, 16, 1.801, 1.801], ["$17N151", 154.9, 16, 1.801, 1.801], ["$17N154", 157.44, 16, 1.801, 1.801], ["+12V", 152.36, 30, 1.801, 1.801], ["$17N151", 154.9, 30, 1.801, 1.801], ["$17N154", 157.44, 30, 1.801, 1.801]], "via": [["GND", 30.35, 71.814, 0.61], ["GND", 30.35, 72.464, 0.61], ["GND", 31, 71.814, 0.61], ["GND", 31, 72.464, 0.61], ["GND", 31.65, 71.814, 0.61], ["GND", 31.65, 72.464, 0.61], ["GND", 16.3, 27, 0.61], ["GND", 16.3, 28, 0.61], ["GND", 17.3, 27, 0.61], ["GND", 17.3, 28, 0.61], ["GND", 16.8, 27.5, 0.61], ["GND", 50.589, 97.5, 0.61], ["GND", 50.589, 98.5, 0.61], ["GND", 51.589, 97.5, 0.61], ["GND", 51.589, 98.5, 0.61], ["GND", 51.089, 98, 0.61], ["GND", 138.969, 97.5, 0.61], ["GND", 138.969, 98.5, 0.61], ["GND", 139.969, 97.5, 0.61], ["GND", 139.969, 98.5, 0.61], ["GND", 139.469, 98, 0.61], ["GND", 47.969, 27, 0.61], ["GND", 47.969, 28, 0.61], ["GND", 48.969, 27, 0.61], ["GND", 48.969, 28, 0.61], ["GND", 48.469, 27.5, 0.61], ["GND", 127.5, 27, 0.61], ["GND", 127.5, 28, 0.61], ["GND", 128.5, 27, 0.61], ["GND", 128.5, 28, 0.61], ["GND", 128, 27.5, 0.61], ["GND", 79.255, 37.685, 0.61], ["GND", 79.255, 38.335, 0.61], ["GND", 79.905, 37.685, 0.61], ["GND", 79.905, 38.335, 0.61], ["GND", 109.245, 34.385, 0.61], ["GND", 109.245, 35.035, 0.61], ["GND", 109.895, 34.385, 0.61], ["GND", 109.895, 35.035, 0.61], ["GND", 13.65, 45.475, 0.61], ["GND", 13.65, 46.125, 0.61], ["GND", 14.3, 45.475, 0.61], ["GND", 14.3, 46.125, 0.61], ["GND", 14.95, 45.475, 0.61], ["GND", 14.95, 46.125, 0.61], ["GND", 52.939, 79.375, 0.61], ["GND", 52.939, 80.025, 0.61], ["GND", 53.589, 79.375, 0.61], ["GND", 53.589, 80.025, 0.61], ["GND", 54.239, 79.375, 0.61], ["GND", 54.239, 80.025, 0.61], ["GND", 141.319, 79.375, 0.61], ["GND", 141.319, 80.025, 0.61], ["GND", 141.969, 79.375, 0.61], ["GND", 141.969, 80.025, 0.61], ["GND", 142.619, 79.375, 0.61], ["GND", 142.619, 80.025, 0.61], ["GND", 45.319, 45.475, 0.61], ["GND", 45.319, 46.125, 0.61], ["GND", 45.969, 45.475, 0.61], ["GND", 45.969, 46.125, 0.61], ["GND", 46.619, 45.475, 0.61], ["GND", 46.619, 46.125, 0.61], ["GND", 124.85, 45.475, 0.61], ["GND", 124.85, 46.125, 0.61], ["GND", 125.5, 45.475, 0.61], ["GND", 125.5, 46.125, 0.61], ["GND", 126.15, 45.475, 0.61], ["GND", 126.15, 46.125, 0.61], ["GND", 21.066, 90.7, 0.61], ["GND", 21.066, 91.35, 0.61], ["GND", 21.066, 92, 0.61], ["GND", 21.066, 92.65, 0.61], ["GND", 21.066, 93.3, 0.61], ["GND", 32.975, 80, 0.61], ["GND", 32.975, 83, 0.61], ["GND", 31.789, 86, 0.61], ["GND", 18.565, 109.863, 0.61], ["GND", 19.047, 112.5, 0.61], ["GND", 24.547, 112.5, 0.61], ["GND", 12.289, 99, 0.61], ["GND", 13.775, 27.8, 0.61], ["GND", 13.775, 31.45, 0.61], ["GND", 13.775, 22.2, 0.61], ["GND", 22.168, 24.92, 0.61], ["GND", 18.32, 42.6, 0.61], ["GND", 18.325, 40.5, 0.61], ["GND", 17.989, 38, 0.61], ["GND", 29.588, 18.5, 0.61], ["GND", 23.324, 18.5, 0.61], ["GND", 23.089, 20.7, 0.61], ["GND", 19.588, 20.7, 0.61], ["GND", 20.089, 51.8, 0.61], ["GND", 24.324, 47.5, 0.61], ["GND", 54.114, 97.7, 0.61], ["GND", 54.114, 94.05, 0.61], ["GND", 54.114, 103.3, 0.61], ["GND", 47.457, 100.58, 0.61], ["GND", 49.569, 82.9, 0.61], ["GND", 52.843, 85, 0.61], ["GND", 50.769, 88.368, 0.61], ["GND", 39.169, 107.869, 0.61], ["GND", 45.544, 107.979, 0.61], ["GND", 45.669, 105.668, 0.61], ["GND", 49.169, 105.668, 0.61], ["GND", 48.669, 74.568, 0.61], ["GND", 44.544, 78.979, 0.61], ["GND", 142.494, 97.7, 0.61], ["GND", 142.494, 94.05, 0.61], ["GND", 142.494, 103.3, 0.61], ["GND", 135.837, 100.58, 0.61], ["GND", 137.949, 82.9, 0.61], ["GND", 141.223, 85, 0.61], ["GND", 139.149, 88.368, 0.61], ["GND", 127.549, 107.869, 0.61], ["GND", 133.924, 107.979, 0.61], ["GND", 134.049, 105.668, 0.61], ["GND", 137.549, 105.668, 0.61], ["GND", 137.049, 74.568, 0.61], ["GND", 132.924, 78.979, 0.61], ["GND", 45.444, 27.8, 0.61], ["GND", 45.444, 31.45, 0.61], ["GND", 45.444, 22.2, 0.61], ["GND", 53.837, 24.92, 0.61], ["GND", 49.989, 42.6, 0.61], ["GND", 49.994, 40.5, 0.61], ["GND", 49.658, 38, 0.61], ["GND", 61.258, 18.5, 0.61], ["GND", 54.993, 18.5, 0.61], ["GND", 54.758, 20.7, 0.61], ["GND", 51.257, 20.7, 0.61], ["GND", 51.758, 51.8, 0.61], ["GND", 55.993, 47.5, 0.61], ["GND", 124.975, 27.8, 0.61], ["GND", 124.975, 31.45, 0.61], ["GND", 124.975, 22.2, 0.61], ["GND", 133.369, 24.92, 0.61], ["GND", 129.52, 42.6, 0.61], ["GND", 129.525, 40.5, 0.61], ["GND", 129.189, 38, 0.61], ["GND", 140.789, 18.5, 0.61], ["GND", 134.524, 18.5, 0.61], ["GND", 134.289, 20.7, 0.61], ["GND", 130.789, 20.7, 0.61], ["GND", 131.289, 51.8, 0.61], ["GND", 135.524, 47.5, 0.61], ["GND", 101.29, 12.167, 0.61], ["GND", 98.151, 9.285, 0.61], ["GND", 99.703, 13.416, 0.61], ["GND", 96.991, 56.681, 0.61], ["GND", 97.581, 42.322, 0.61], ["GND", 72.137, 54.081, 0.61], ["GND", 80.793, 40.496, 0.61], ["GND", 84.004, 40.511, 0.61], ["GND", 78.03, 39.608, 0.61], ["GND", 110.781, 37.194, 0.61], ["GND", 113.995, 37.21, 0.61], ["GND", 108.021, 36.306, 0.61], ["GND", 77.865, 13.933, 0.61], ["GND", 23.52, 52.963, 0.61], ["GND", 24.197, 55.95, 0.61], ["GND", 34.397, 28.45, 0.61], ["GND", 38.397, 28.45, 0.61], ["GND", 34.397, 32.45, 0.61], ["GND", 45.886, 73.55, 0.61], ["GND", 45.886, 69.55, 0.61], ["GND", 35.686, 97.05, 0.61], ["GND", 31.686, 97.05, 0.61], ["GND", 35.686, 93.05, 0.61], ["GND", 134.266, 73.55, 0.61], ["GND", 134.266, 69.55, 0.61], ["GND", 124.066, 97.05, 0.61], ["GND", 120.066, 97.05, 0.61], ["GND", 124.066, 93.05, 0.61], ["GND", 55.189, 52.963, 0.61], ["GND", 55.866, 55.95, 0.61], ["GND", 66.066, 28.45, 0.61], ["GND", 70.066, 28.45, 0.61], ["GND", 66.066, 32.45, 0.61], ["GND", 134.72, 52.963, 0.61], ["GND", 135.397, 55.95, 0.61], ["GND", 145.597, 28.45, 0.61], ["GND", 149.597, 28.45, 0.61], ["GND", 145.597, 32.45, 0.61], ["GND", 26.675, 71.5, 0.61], ["GND", 20.567, 116.892, 0.61], ["GND", 20.567, 119.391, 0.61], ["GND", 12.624, 20.7, 0.61], ["GND", 24.867, 19.392, 0.61], ["GND", 29.624, 20.7, 0.61], ["GND", 20.624, 45.5, 0.61], ["GND", 20.624, 43.5, 0.61], ["GND", 22.367, 46.392, 0.61], ["GND", 27.624, 47.5, 0.61], ["GND", 27.624, 41.5, 0.61], ["GND", 33.624, 35, 0.61], ["GND", 33.624, 38, 0.61], ["GND", 33.624, 41, 0.61], ["GND", 55.265, 104.8, 0.61], ["GND", 43.913, 107, 0.61], ["GND", 39.156, 105.691, 0.61], ["GND", 48.156, 80.892, 0.61], ["GND", 48.156, 82.892, 0.61], ["GND", 46.414, 80, 0.61], ["GND", 41.156, 78.892, 0.61], ["GND", 41.156, 84.892, 0.61], ["GND", 35.156, 91.392, 0.61], ["GND", 35.156, 88.392, 0.61], ["GND", 35.156, 85.392, 0.61], ["GND", 143.645, 104.8, 0.61], ["GND", 132.293, 107, 0.61], ["GND", 127.536, 105.691, 0.61], ["GND", 136.536, 80.892, 0.61], ["GND", 136.536, 82.892, 0.61], ["GND", 134.794, 80, 0.61], ["GND", 129.536, 78.892, 0.61], ["GND", 129.536, 84.892, 0.61], ["GND", 123.536, 91.392, 0.61], ["GND", 123.536, 88.392, 0.61], ["GND", 123.536, 85.392, 0.61], ["GND", 44.293, 20.7, 0.61], ["GND", 56.536, 19.392, 0.61], ["GND", 61.293, 20.7, 0.61], ["GND", 52.293, 45.5, 0.61], ["GND", 52.293, 43.5, 0.61], ["GND", 54.036, 46.392, 0.61], ["GND", 59.293, 47.5, 0.61], ["GND", 59.293, 41.5, 0.61], ["GND", 65.293, 35, 0.61], ["GND", 65.293, 38, 0.61], ["GND", 65.293, 41, 0.61], ["GND", 123.824, 20.7, 0.61], ["GND", 136.067, 19.392, 0.61], ["GND", 140.825, 20.7, 0.61], ["GND", 131.825, 45.5, 0.61], ["GND", 131.825, 43.5, 0.61], ["GND", 133.567, 46.392, 0.61], ["GND", 138.825, 47.5, 0.61], ["GND", 138.825, 41.5, 0.61], ["GND", 144.825, 35, 0.61], ["GND", 144.825, 38, 0.61], ["GND", 144.825, 41, 0.61], ["GND", 150.703, 52.518, 0.61], ["GND", 151.044, 55.45, 0.61], ["GND", 77.883, 36.35, 0.61], ["GND", 107.873, 33.049, 0.61], ["GND", 71.891, 36.753, 0.61], ["GND", 71.891, 26.753, 0.61], ["GND", 15.075, 29.174, 0.61], ["GND", 14.222, 28.854, 0.61], ["GND", 52.814, 96.326, 0.61], ["GND", 53.667, 96.647, 0.61], ["GND", 141.194, 96.326, 0.61], ["GND", 142.048, 96.647, 0.61], ["GND", 46.744, 29.174, 0.61], ["GND", 45.891, 28.854, 0.61], ["GND", 126.275, 29.174, 0.61], ["GND", 125.422, 28.854, 0.61], ["GND", 12.579, 50.196, 0.61], ["GND", 13.8, 51.012, 0.61], ["GND", 14.8, 55.232, 0.61], ["GND", 55.31, 75.304, 0.61], ["GND", 53.089, 72.912, 0.61], ["GND", 142.469, 77.132, 0.61], ["GND", 141.469, 72.912, 0.61], ["GND", 46.469, 55.232, 0.61], ["GND", 123.779, 50.196, 0.61], ["GND", 126, 55.232, 0.61], ["GND", 5.5, 98.212, 0.61], ["GND", 7, 102.432, 0.61], ["GND", 16.524, 44.3, 0.61], ["GND", 16.524, 47.3, 0.61], ["GND", 51.365, 81.2, 0.61], ["GND", 51.365, 78.2, 0.61], ["GND", 139.745, 81.2, 0.61], ["GND", 139.745, 78.2, 0.61], ["GND", 48.193, 44.3, 0.61], ["GND", 48.193, 47.3, 0.61], ["GND", 127.724, 44.3, 0.61], ["GND", 127.724, 47.3, 0.61], ["GND", 21.476, 103.05, 0.61], ["GND", 95.375, 9.305, 0.61], ["GND", 80.625, 9.305, 0.61], ["GND", 88.535, 19.475, 0.61], ["GND", 89.935, 19.475, 0.61], ["GND", 92.036, 18.425, 0.61], ["GND", 92.036, 15.625, 0.61], ["GND", 89.066, 14.576, 0.61], ["GND", 87.051, 16.06, 0.61], ["GND", 87.051, 17.46, 0.61], ["GND", 92.036, 17.025, 0.61], ["GND", 90.49, 14.636, 0.61], ["GND", 98.225, 49.634, 0.61], ["GND", 98.815, 35.275, 0.61], ["GND", 74.225, 47.957, 0.61], ["GND", 73.575, 45.258, 0.61], ["GND", 81.424, 46.608, 0.61], ["GND", 79.425, 47.957, 0.61], ["GND", 75.525, 54.002, 0.61], ["GND", 74.875, 51.303, 0.61], ["GND", 76.175, 51.303, 0.61], ["GND", 76.825, 54.002, 0.61], ["GND", 12.597, 94, 0.61], ["GND", 66.837, 71.565, 0.61], ["GND", 72.175, 71, 0.61], ["GND", 78.127, 81.107, 0.61], ["GND", 81.639, 79.593, 0.61], ["GND", 59.567, 72.392, 0.61], ["GND", 64.224, 71.05, 0.61], ["GND", 97.975, 68.265, 0.61], ["GND", 101.067, 81.392, 0.61], ["GND", 105.232, 74, 0.61], ["GND", 106.324, 78, 0.61], ["GND", 108.289, 74, 0.61], ["GND", 104.097, 70.45, 0.61], ["GND", 77.033, 11.012, 0.61], ["GND", 150.728, 48.589, 0.61], ["GND", 150.236, 55.498, 0.61], ["+12V", 21.475, 108.5, 0.61], ["+12V", 21.043, 109.543, 0.61], ["+12V", 20, 109.975, 0.61], ["+12V", 13.775, 25.8, 0.61], ["+12V", 10.937, 26.365, 0.61], ["+12V", 10.937, 25.235, 0.61], ["+12V", 13.663, 30.015, 0.61], ["+12V", 10.937, 30.015, 0.61], ["+12V", 10.324, 29.45, 0.61], ["+12V", 13.775, 24.2, 0.61], ["+12V", 10.824, 24.2, 0.61], ["+12V", 14.125, 24.956, 0.61], ["+12V", 22.168, 24.08, 0.61], ["+12V", 57.064, 99.7, 0.61], ["+12V", 54.226, 100.265, 0.61], ["+12V", 54.226, 99.135, 0.61], ["+12V", 57.064, 96.05, 0.61], ["+12V", 54.226, 95.485, 0.61], ["+12V", 57.864, 96.05, 0.61], ["+12V", 57.064, 101.3, 0.61], ["+12V", 54.226, 101.865, 0.61], ["+12V", 53.613, 101.3, 0.61], ["+12V", 47.457, 101.42, 0.61], ["+12V", 145.444, 99.7, 0.61], ["+12V", 142.606, 100.265, 0.61], ["+12V", 142.606, 99.135, 0.61], ["+12V", 145.444, 96.05, 0.61], ["+12V", 142.606, 95.485, 0.61], ["+12V", 146.244, 96.05, 0.61], ["+12V", 145.444, 101.3, 0.61], ["+12V", 142.606, 101.865, 0.61], ["+12V", 141.993, 101.3, 0.61], ["+12V", 135.837, 101.42, 0.61], ["+12V", 45.444, 25.8, 0.61], ["+12V", 42.606, 26.365, 0.61], ["+12V", 42.606, 25.235, 0.61], ["+12V", 45.332, 30.015, 0.61], ["+12V", 42.606, 30.015, 0.61], ["+12V", 41.993, 29.45, 0.61], ["+12V", 45.444, 24.2, 0.61], ["+12V", 42.493, 24.2, 0.61], ["+12V", 45.794, 24.956, 0.61], ["+12V", 53.837, 24.08, 0.61], ["+12V", 124.975, 25.8, 0.61], ["+12V", 122.137, 26.365, 0.61], ["+12V", 122.137, 25.235, 0.61], ["+12V", 124.863, 30.015, 0.61], ["+12V", 122.137, 30.015, 0.61], ["+12V", 121.524, 29.45, 0.61], ["+12V", 124.975, 24.2, 0.61], ["+12V", 122.024, 24.2, 0.61], ["+12V", 125.325, 24.956, 0.61], ["+12V", 133.369, 24.08, 0.61], ["+12V", 23.595, 117.789, 0.61], ["+12V", 24.865, 117.789, 0.61], ["+12V", 26.135, 117.789, 0.61], ["+12V", 19.324, 118.5, 0.61], ["+12V", 19.324, 121, 0.61], ["+12V", 24.867, 21.592, 0.61], ["+12V", 43.913, 104.8, 0.61], ["+12V", 132.293, 104.8, 0.61], ["+12V", 56.536, 21.592, 0.61], ["+12V", 136.067, 21.592, 0.61], ["+12V", 8, 91, 0.61], ["+12V", 8.9, 91, 0.61], ["+12V", 9.8, 91, 0.61], ["+12V", 10.7, 91, 0.61], ["+12V", 8, 90, 0.61], ["+12V", 8.9, 90, 0.61], ["+12V", 9.8, 90, 0.61], ["+12V", 10.7, 90, 0.61], ["+12V", 8, 89, 0.61], ["+12V", 8.9, 89, 0.61], ["+12V", 9.8, 89, 0.61], ["+12V", 10.7, 89, 0.61], ["+12V", 14.722, 25.647, 0.61], ["+12V", 14.151, 27, 0.61], ["+12V", 15.075, 24.926, 0.61], ["+12V", 53.467, 99.653, 0.61], ["+12V", 53.738, 98.5, 0.61], ["+12V", 52.814, 100.124, 0.61], ["+12V", 141.847, 99.653, 0.61], ["+12V", 142.118, 98.5, 0.61], ["+12V", 141.194, 100.124, 0.61], ["+12V", 46.391, 25.647, 0.61], ["+12V", 45.82, 27, 0.61], ["+12V", 46.744, 24.926, 0.61], ["+12V", 125.922, 25.647, 0.61], ["+12V", 125.351, 27, 0.61], ["+12V", 126.275, 24.926, 0.61], ["+12V", 21.476, 104.95, 0.61], ["+12V", 18.776, 104, 0.61], ["+12V", 69.243, 74.043, 0.61], ["+12V", 68.2, 74.476, 0.61], ["+12V", 67.157, 74.043, 0.61], ["+12V", 72.175, 73, 0.61], ["+12V", 71.743, 74.043, 0.61], ["+12V", 70.7, 74.476, 0.61], ["+12V", 66.476, 72.95, 0.61], ["+12V", 63.776, 72, 0.61], ["+12V", 102.047, 74, 0.61], ["+12V", 101.567, 75.159, 0.61], ["+12V", 100.407, 75.639, 0.61], ["+12V", 97.567, 78.892, 0.61], ["+12V", 108.214, 69.5, 0.61], ["+12V", 107.653, 70.853, 0.61], ["+12V", 106.3, 71.414, 0.61], ["+3V3", 18.38, 52.668, 0.61], ["+3V3", 50.049, 52.668, 0.61], ["+3V3", 129.58, 52.668, 0.61], ["+3V3", 101.019, 10.994, 0.61], ["+3V3", 95.282, 57.55, 0.61], ["+3V3", 95.872, 43.19, 0.61], ["+3V3", 79.084, 41.364, 0.61], ["+3V3", 109.072, 38.062, 0.61], ["+3V3", 22.367, 44.392, 0.61], ["+3V3", 27.624, 45.5, 0.61], ["+3V3", 23.375, 51, 0.61], ["+3V3", 54.036, 44.392, 0.61], ["+3V3", 58.402, 46.392, 0.61], ["+3V3", 55.045, 51, 0.61], ["+3V3", 133.567, 44.392, 0.61], ["+3V3", 138.825, 45.5, 0.61], ["+3V3", 134.575, 51, 0.61], ["+3V3", 85.906, 29.365, 0.61], ["+3V3", 99.043, 17.761, 0.61], ["+3V3", 76.8, 45.208, 0.61], ["+3V3", 79.563, 44.261, 0.61], ["+3V3", 91.459, 57.573, 0.61], ["+3V3", 76.166, 39.39, 0.61], ["+3V3", 106.156, 36.089, 0.61], ["+3V3", 76.369, 10.154, 0.61], ["+3V3", 76.094, 11.81, 0.61], ["+3V3", 16.622, 53.91, 0.61], ["+3V3", 44.248, 50.196, 0.61], ["+3V3", 45.469, 51.012, 0.61], ["+3V3", 48.291, 53.91, 0.61], ["+3V3", 127.822, 53.91, 0.61], ["+3V3", 95.375, 10.575, 0.61], ["+3V3", 94.575, 10.575, 0.61], ["+3V3", 93.775, 10.575, 0.61], ["+3V3", 87.805, 56.636, 0.61], ["+3V3", 95.425, 53.575, 0.61], ["+3V3", 88.395, 42.276, 0.61], ["+3V3", 96.015, 39.215, 0.61], ["+3V3", 87.555, 75.266, 0.61], ["+3V3", 95.175, 75.266, 0.61], ["VO1_P", 26.997, 54.599, 0.61], ["VO1_P", 26.1, 54.777, 0.61], ["VO1_P", 25.203, 54.599, 0.61], ["VO1_P", 19.71, 56.8, 0.61], ["VO1_P", 19.531, 57.697, 0.61], ["VO1_P", 19.023, 58.457, 0.61], ["VO1_P", 14.3, 52.588, 0.61], ["VO2_P", 40.892, 70.901, 0.61], ["VO2_P", 41.789, 70.723, 0.61], ["VO2_P", 42.686, 70.901, 0.61], ["VO2_P", 52.866, 68.7, 0.61], ["VO2_P", 52.688, 69.597, 0.61], ["VO2_P", 51.419, 70.865, 0.61], ["VO2_P", 53.589, 70.268, 0.61], ["VO3_P", 128.512, 71.409, 0.61], ["VO3_P", 129.272, 70.901, 0.61], ["VO3_P", 130.169, 70.723, 0.61], ["VO3_P", 141.246, 68.7, 0.61], ["VO3_P", 141.068, 69.597, 0.61], ["VO3_P", 139.8, 70.865, 0.61], ["VO3_P", 141.969, 70.268, 0.61], ["VO4_P", 59.426, 54.091, 0.61], ["VO4_P", 58.666, 54.599, 0.61], ["VO4_P", 57.769, 54.777, 0.61], ["VO4_P", 51.379, 56.8, 0.61], ["VO4_P", 51.2, 57.697, 0.61], ["VO4_P", 50.692, 58.457, 0.61], ["VO4_P", 45.969, 52.588, 0.61], ["VO5_P", 138.957, 54.091, 0.61], ["VO5_P", 138.197, 54.599, 0.61], ["VO5_P", 137.3, 54.777, 0.61], ["VO5_P", 130.91, 56.8, 0.61], ["VO5_P", 130.731, 57.697, 0.61], ["VO5_P", 130.223, 58.457, 0.61], ["VO5_P", 125.5, 52.588, 0.61], ["$10N653", 135.05, 99.25, 0.61], ["$10N653", 139.9, 95.25, 0.61], ["$10N655", 141, 106.8, 0.61], ["$10N655", 142.485, 104.8, 0.61], ["$10N659", 135.5, 107, 0.61], ["$10N659", 137.1, 106.9, 0.61], ["$10N687", 138.625, 80.075, 0.61], ["$10N687", 134.825, 77.675, 0.61], ["$10N699", 144.9, 85.4, 0.61], ["$10N699", 125.7, 90.7, 0.61], ["$10N699", 122.5, 91.2, 0.61], ["$10N699", 117.3, 86, 0.61], ["$10N699", 117.3, 83.8, 0.61], ["$10N699", 130.984, 82.001, 0.61], ["$10N707", 118.5, 91.7, 0.61], ["$10N707", 118.968, 98.951, 0.61], ["$12N842", 58.625, 18.5, 0.61], ["$12N842", 50.725, 26.325, 0.61], ["$12N843", 61.7, 24.1, 0.61], ["$12N843", 64.2, 21.6, 0.61], ["$12N855", 50.05, 45.25, 0.61], ["$12N855", 46.95, 43.3, 0.61], ["$12N877", 44.15, 49.05, 0.61], ["$12N886", 65.05, 35.85, 0.61], ["$12N886", 63.9, 26.05, 0.61], ["$14N655", 128.5, 20.2, 0.61], ["$14N655", 127.1, 18.8, 0.61], ["$14N655", 124.984, 20.701, 0.61], ["$14N663", 138.15, 18.5, 0.61], ["$14N663", 130.625, 26.3, 0.61], ["$14N664", 133.2, 26.6, 0.61], ["$14N664", 137.517, 20.701, 0.61], ["$14N698", 123.675, 49.075, 0.61], ["$14N698", 137.125, 41.6, 0.61], ["$14N698", 137.725, 42.8, 0.61], ["$14N707", 148, 35, 0.61], ["$14N707", 142.485, 38.001, 0.61], ["$14N719", 148.5, 39.4, 0.61], ["$14N719", 147.4, 40.7, 0.61], ["$14N719", 149.4, 36.6, 0.61], ["$14N719", 149.1, 29.5, 0.61], ["$14N719", 144.501, 30.551, 0.61], ["$16N18", 63.05, 70.2, 0.61], ["$16N18", 64, 72.85, 0.61], ["$16N18", 67.701, 78.001, 0.61], ["$17N148", 98.3, 91.4, 0.61], ["$17N148", 99, 94.4, 0.61], ["$17N148", 100.4, 95.8, 0.61], ["$17N148", 115.1, 85, 0.61], ["$17N148", 117.1, 81.9, 0.61], ["$17N148", 117.1, 79.2, 0.61], ["$17N148", 106.7, 73, 0.61], ["$17N148", 103.5, 68.5, 0.61], ["$17N151", 100.6, 71.6, 0.61], ["$17N151", 81.2, 51.8, 0.61], ["$17N151", 73.6, 50, 0.61], ["$1N244", 22.05, 116.75, 0.61], ["$1N244", 14.933, 100.501, 0.61], ["$1N263", 17.1, 98, 0.61], ["$1N263", 15.6, 96.6, 0.61], ["$1N266", 24.15, 92, 0.61], ["$1N266", 16.25, 93.3, 0.61], ["$2N655", 17.5, 20.6, 0.61], ["$2N655", 15.6, 18.7, 0.61], ["$2N655", 13.783, 20.701, 0.61], ["$2N657", 20.9, 22, 0.61], ["$2N657", 17.7, 25, 0.61], ["$2N663", 25.675, 19.65, 0.61], ["$2N663", 19.425, 26.3, 0.61], ["$2N664", 21, 26.85, 0.61], ["$2N664", 26.316, 20.701, 0.61], ["$2N689", 36.5, 30, 0.61], ["$2N689", 33.2, 26.9, 0.61], ["$2N689", 30.1, 26.1, 0.61], ["$2N689", 27, 34.7, 0.61], ["$2N689", 31.284, 35.001, 0.61], ["$2N698", 12.475, 49.075, 0.61], ["$2N699", 13.8, 47.4, 0.61], ["$2N699", 16.1, 49.8, 0.61], ["$2N699", 23.4, 48.4, 0.61], ["$2N699", 25.1, 46.8, 0.61], ["$3N172", 94.575, 13.75, 0.61], ["$3N172", 98.101, 15.197, 0.61], ["$8N653", 41.8, 105.7, 0.61], ["$8N653", 52, 95.5, 0.61], ["$8N655", 50.4, 105.1, 0.61], ["$8N655", 52, 106.7, 0.61], ["$8N655", 54.1, 105.6, 0.61], ["$8N657", 47.2, 103.7, 0.61], ["$8N657", 50.1, 100.6, 0.61], ["$8N659", 47.2, 107, 0.61], ["$8N659", 48.7, 106.9, 0.61], ["$8N663", 40.95, 107, 0.61], ["$8N663", 48.475, 99.2, 0.61], ["$8N664", 45, 101.4, 0.61], ["$8N664", 41.573, 104.8, 0.61], ["$8N676", 49.3, 80.2, 0.61], ["$8N676", 52.6, 82.3, 0.61], ["$8N689", 30.6, 95.9, 0.61], ["$8N689", 34.59, 98.951, 0.61], ["$8N689", 35.8, 96.1, 0.61], ["$8N689", 35.5, 94.1, 0.61], ["$8N689", 36.605, 90.5, 0.61], ["$8N699", 56.6, 85.3, 0.61], ["$8N699", 47.5, 86.9, 0.61], ["$8N707", 31.1, 90.5, 0.61], ["$8N707", 36.2, 87.7, 0.61], ["$8N707", 30.589, 98.951, 0.61], ["$8N719", 34.3, 89, 0.61], ["$8N719", 34.59, 94.95, 0.61], ["+3V3", 51.8, 75.2, 0.61], ["+3V3", 55.3, 76.9, 0.61], ["+5V", 62.7, 48.6, 0.61], ["+5V", 64.9, 50.8, 0.61], ["+5V", 61.7, 67.9, 0.61], ["+5V", 73.299, 78.001, 0.61], ["BLD_A", 20.5, 113.9, 0.61], ["BLD_A", 13.75, 95.8, 0.61], ["BLD_REF", 17.85, 117.7, 0.61], ["BLD_REF", 16.55, 103.7, 0.61], ["BUCK_PG", 65.8, 51.7, 0.61], ["BUCK_PG", 65.8, 62.7, 0.61], ["BUCK_PG", 49.2, 30.2, 0.61], ["BUCK_PG", 17.7, 30, 0.61], ["EDL_EN1", 59.5, 81.3, 0.61], ["EDL_EN1", 24.4, 85.3, 0.61], ["EDL_EN1", 19.3, 84.2, 0.61], ["EDL_EN1", 23.2, 75, 0.61], ["EFUSE_EN5", 133.4, 41.65, 0.61], ["EFUSE_EN5", 132.8, 44.9, 0.61], ["EFUSE_EN5", 126.1, 42.6, 0.61], ["EFUSE_EN5", 96, 23.1, 0.61], ["EFUSE_FLT1", 23.3, 43.5, 0.61], ["EFUSE_FLT1", 17.4, 47, 0.61], ["EFUSE_FLT3", 139, 77.6, 0.61], ["EFUSE_FLT3", 146.3, 76.5, 0.61], ["EFUSE_FLT3", 148.5, 76.5, 0.61], ["EFUSE_FLT3", 140.7, 42.2, 0.61], ["EFUSE_FLT3", 134.1, 38.8, 0.61], ["EFUSE_FLT3", 120, 36.4, 0.61], ["EFUSE_FLT3", 81.5, 36.2, 0.61], ["EFUSE_FLT3", 75.8, 48.1, 0.61], ["EFUSE_FLT5", 131, 44.6, 0.61], ["EFUSE_FLT5", 128.6, 47, 0.61], ["EFUSE_FLT5", 134.35, 42.95, 0.61], ["EFUSE_FLT5", 134.25, 41.5, 0.61], ["EFUSE_FLT5", 132.9, 40.2, 0.61], ["EFUSE_FLT5", 123.3, 39.85, 0.61], ["EFUSE_FLT5", 88.6, 44.15, 0.61], ["EFUSE_FLT5", 87.3, 42.85, 0.61], ["EFUSE_FLT5", 78.65, 42.15, 0.61], ["EFUSE_FLT5", 78.1, 43.45, 0.61], ["EFUSE_FLT5", 76.55, 43.15, 0.61], ["EFUSE_FLT5", 75.05, 48.55, 0.61], ["EFUSE_PG1", 22.2, 48.4, 0.61], ["EFUSE_PG1", 25.284, 45.499, 0.61], ["EFUSE_PG1", 69.6, 48.65, 0.61], ["EFUSE_PG1", 69.9, 50.7, 0.61], ["EFUSE_PG1", 76.2, 54.65, 0.61], ["EFUSE_PG1", 78.5, 54.65, 0.61], ["EFUSE_PG1", 80.075, 53.779, 0.61], ["EFUSE_PG2", 50.2, 75.2, 0.61], ["EFUSE_PG2", 41.5, 75.3, 0.61], ["EFUSE_PG2", 39.3, 74.2, 0.61], ["EFUSE_PG2", 37.2, 74.3, 0.61], ["EFUSE_PG2", 39.5, 78.4, 0.61], ["EFUSE_PG2", 42.605, 80, 0.61], ["EFUSE_PG3", 132.5, 76.35, 0.61], ["EFUSE_PG3", 130.984, 80, 0.61], ["EFUSE_PG4", 53.2, 44.05, 0.61], ["EFUSE_PG4", 56.6, 44.75, 0.61], ["EFUSE_PG5", 130.4, 48.4, 0.61], ["EFUSE_PG5", 135.6, 45.1, 0.61], ["FB3V3", 17.5, 116, 0.61], ["FB3V3", 22.7, 116, 0.61], ["FB3V3", 15.9, 110.1, 0.61], ["FB3V3", 15.9, 105.85, 0.61], ["INA_ALERT", 114.1, 51.5, 0.61], ["INA_ALERT", 120.3, 57.7, 0.61], ["K4_VDN", 79.9, 34.4, 0.61], ["K4_VDN", 86.3, 35.35, 0.61], ["KEY_OE#", 91.9, 52.2, 0.61], ["KEY_OE#", 92.204, 42.032, 0.61], ["KEY_OE#", 90, 38.1, 0.61], ["KEY_OE#", 85.2, 30, 0.61], ["NTC1", 80.6, 13.8, 0.61], ["NTC1", 63.8, 28.3, 0.61], ["NTC1", 60.6, 28.7, 0.61], ["NTC1", 70.8, 35.248, 0.61], ["NTC2", 74.3, 21.7, 0.61], ["NTC2", 70.8, 25.248, 0.61], ["POGO1_VDN", 31.5, 30, 0.61], ["POGO1_VDN", 26.6, 26.1, 0.61], ["POGO1_VDN", 19.1, 22.7, 0.61], ["POGO1_VDN", 10.7, 31.4, 0.61], ["POGO1_VDN", 11.2, 68.5, 0.61], ["POGO1_VDN", 21.6, 67.8, 0.61], ["POGO1_VUP", 34.9, 27.5, 0.61], ["POGO1_VUP", 24.7, 25.4, 0.61], ["POGO1_VUP", 19.8, 23.4, 0.61], ["POGO1_VUP", 11, 32.3, 0.61], ["POGO1_VUP", 9.3, 67.8, 0.61], ["POGO1_VUP", 20.7, 66.2, 0.61], ["POGO2_PWR", 102.3, 95.4, 0.61], ["POGO2_PWR", 114.5, 83.2, 0.61], ["POGO2_PWR", 115.7, 80.8, 0.61], ["POGO2_PWR", 115.7, 70.9, 0.61], ["POGO2_PWR", 111.6, 66.4, 0.61], ["POGO2_VDN", 44.6, 94, 0.61], ["POGO2_VDN", 59.6, 93.3, 0.61], ["POGO2_VDN", 102.3, 91.7, 0.61], ["POGO2_VDN", 103.7, 90.3, 0.61], ["POGO2_VDN", 115, 81.5, 0.61], ["POGO2_VDN", 115, 69, 0.61], ["POGO2_VDN", 115, 66.4, 0.61], ["POGO2_VUP", 32.8, 98, 0.61], ["POGO2_VUP", 59.2, 94.8, 0.61], ["POGO2_VUP", 102.3, 92.8, 0.61], ["POGO2_VUP", 113.2, 81.9, 0.61], ["POGO2_VUP", 114.3, 80.8, 0.61], ["POGO2_VUP", 114.3, 68.3, 0.61], ["POGO2_VUP", 114.1, 66.4, 0.61], ["POGO3_VUP", 120.95, 94.8, 0.61], ["POGO3_VUP", 119.2, 89.65, 0.61], ["POGO3_VUP", 117.85, 81.3, 0.61], ["POGO3_VUP", 117.85, 69.9, 0.61], ["POGO3_VUP", 119.2, 66.95, 0.61], ["POGO3_VUP", 120.35, 59.85, 0.61], ["SCL", 126.8, 49.3, 0.61], ["SCL", 95.9, 33.3, 0.61], ["SCL", 47.9, 49.85, 0.61], ["SCL", 7.4, 95.2, 0.61], ["SDA", 108.9, 31.1, 0.61], ["SDA", 87.354, 28.474, 0.61], ["SDA", 86.096, 27.094, 0.61], ["SDA", 80.6, 36.5, 0.61], ["SDA", 6.8, 98.25, 0.61], ["SR_CAS", 96.3, 55.1, 0.61], ["SR_CAS", 89.3, 42.85, 0.61], ["VBUS_EN3", 91.3, 22.9, 0.61], ["VBUS_EN3", 100.5, 19.1, 0.61], ["VBUS_EN3", 146.7, 39.3, 0.61], ["VBUS_EN3", 152.8, 74.5, 0.61], ["VBUS_EN3", 151.8, 66, 0.61], ["VO1", 20.1, 29.95, 0.61], ["VO1", 23.2, 26.85, 0.61], ["VO2", 53.4, 92.65, 0.61], ["VO2", 56.15, 92.65, 0.61], ["VO3", 141, 93.45, 0.61], ["VO3", 145.985, 107, 0.61], ["VO5", 125, 44.4, 0.61], ["VO5", 129.485, 47.5, 0.61], ["VO5", 125.7, 32.85, 0.61], ["VO5", 122.9, 32.85, 0.61], ["$10N719", 128.6, 84.5, 0.61], ["$10N719", 144.1, 83, 0.61], ["$10N719", 144.1, 87.4, 0.61], ["$10N719", 127.8, 93.4, 0.61], ["$12N834", 46.9, 18.2, 0.61], ["$12N834", 45.3, 19.8, 0.61], ["$12N836", 47.6, 17.65, 0.61], ["$12N836", 44.45, 19.85, 0.61], ["$12N836", 47.05, 24.05, 0.61], ["$12N836", 48.45, 24.35, 0.61], ["$14N653", 137.7, 19.8, 0.61], ["$14N653", 127.1, 30, 0.61], ["$14N657", 131.7, 21, 0.61], ["$14N657", 126.5, 22.5, 0.61], ["$14N657", 126.5, 23.9, 0.61], ["$14N657", 128.5, 24.7, 0.61], ["$14N689", 136.8, 29.1, 0.61], ["$14N689", 135.5, 30, 0.61], ["$14N689", 140.5, 35, 0.61], ["$14N689", 142.7, 35, 0.61], ["$14N699", 122.15, 45.6, 0.61], ["$14N699", 121.2, 44.65, 0.61], ["$14N699", 123.4, 41.95, 0.61], ["$14N699", 131.05, 41.9, 0.61], ["$17N151", 103.5, 66, 0.61], ["$17N151", 113.6, 53.2, 0.61], ["$17N151", 122.7, 44.1, 0.61], ["$17N154", 102.2, 76.1, 0.61], ["$17N154", 101.8, 60.9, 0.61], ["$17N154", 120.3, 50.3, 0.61], ["$17N154", 139.1, 39.3, 0.61], ["$17N154", 145.5, 39.3, 0.61], ["$1N227", 20.3, 73.5, 0.61], ["$1N227", 20.3, 70.5, 0.61], ["+3V3", 55.25, 76.275, 0.61], ["+3V3", 51.925, 75.825, 0.61], ["EFUSE_EN3", 149.5, 52.1, 0.61], ["EFUSE_EN3", 144.3, 42.4, 0.61], ["EFUSE_EN3", 140.5, 38.6, 0.61], ["EFUSE_EN3", 134.9, 37, 0.61], ["EFUSE_EN3", 121.6, 34.3, 0.61], ["EFUSE_EN3", 115, 32.4, 0.61], ["EFUSE_EN3", 96.9, 15.8, 0.61], ["GATE", 26.1, 68.2, 0.61], ["GATE", 27.4, 69.1, 0.61], ["INA_ALERT", 34.9, 69.8, 0.61], ["INA_ALERT", 11.2, 70.8, 0.61], ["INA_ALERT", 11.2, 78.1, 0.61], ["INA_ALERT", 7.1, 94.3, 0.61], ["POGO5_VDN", 142.2, 32.1, 0.61], ["POGO5_VDN", 139.7, 59.2, 0.61], ["SCL", 102.1, 24.2, 0.61], ["SCL", 103.3, 25.4, 0.61], ["SCL", 107.6, 31.4, 0.61], ["SCL", 109.6, 33.1, 0.61], ["SDA", 140, 75.4, 0.61], ["VDAC5", 126.434, 21.271, 0.61], ["VDAC5", 116.7, 29.5, 0.61], ["SCL", 114.9, 37.2, 0.61], ["SDA", 80, 41.4, 0.61], ["SDA", 34.1, 65.8, 0.61], ["SDA", 51.3, 77.3, 0.61], ["SDA", 102.5, 30.7, 0.61], ["SCL", 73.9, 51.2, 0.61], ["SCL", 121, 43.2, 0.61], ["SCL", 61.1, 50, 0.61], ["SCL", 58.4, 49.9, 0.61], ["SCL", 48, 75.9, 0.61], ["SCL", 29.8, 58.4, 0.61], ["SCL", 6.8, 87.6, 0.61], ["SDA", 72.9, 54.8, 0.61], ["SDA", 69.9, 51.8, 0.61], ["SDA", 70.5, 48.6, 0.61], ["SDA", 60.9, 50.9, 0.61], ["SDA", 60.9, 59.6, 0.61], ["SDA", 11.4, 87.6, 0.61], ["SDA", 102.5, 38.1, 0.61], ["SDA", 102.5, 49, 0.61], ["SDA", 102.5, 56.9, 0.61], ["GND", 14.8, 5, 0.61], ["GND", 38.5, 5, 0.61], ["GND", 62.2, 5, 0.61], ["GND", 110.3, 5, 0.61], ["GND", 129, 5, 0.61], ["GND", 147.7, 5, 0.61], ["$10N732", 135.1, 75.5, 0.61], ["$10N732", 133.85, 76.8, 0.61], ["$10N732", 127.85, 73.35, 0.61], ["$10N732", 127.85, 69.25, 0.61], ["$12N878", 43.85, 39.65, 0.61], ["$12N878", 49.45, 34.4, 0.61], ["$12N878", 51.35, 34.4, 0.61], ["$12N878", 65.3, 39.65, 0.61], ["$12N878", 64, 41.85, 0.61], ["$12N878", 60.1, 42.15, 0.61], ["$17N154", 95.1, 59.5, 0.61], ["$17N154", 90, 59.5, 0.61], ["$17N154", 74.4, 49.5, 0.61], ["$2N653", 25.7, 18.65, 0.61], ["$2N653", 9.65, 31.15, 0.61], ["$2N653", 8.85, 32.3, 0.61], ["$2N653", 10.4, 33.85, 0.61], ["$2N653", 11.75, 32.75, 0.61], ["$2N653", 15.85, 30, 0.61], ["$2N676", 20.375, 47.15, 0.61], ["$2N676", 21.275, 46.05, 0.61], ["$2N676", 28.95, 43.95, 0.61], ["$2N676", 28.95, 40.7, 0.61], ["$2N676", 17.7, 39.15, 0.61], ["$2N698", 18.9, 44.4, 0.61], ["$2N707", 31.2, 36.7, 0.61], ["$2N707", 29.7, 37.6, 0.61], ["$2N707", 35.4, 25.8, 0.61], ["$2N707", 37.3, 26.551, 0.61], ["$2N719", 32.2, 38.9, 0.61], ["$2N719", 34.5, 34.7, 0.61], ["$2N732", 28.2, 56.8, 0.61], ["$2N732", 28.2, 58.2, 0.61], ["$8N687", 49.1, 81.1, 0.61], ["$8N687", 46.4, 79, 0.61], ["+3V3", 131.5, 80.7, 0.61], ["+3V3", 123.25, 71.6, 0.61], ["+3V3", 125.15, 71.6, 0.61], ["+3V3", 131.9, 75.15, 0.61], ["+3V3", 134.225, 75.125, 0.61], ["+3V3", 137.675, 75.125, 0.61], ["+3V3", 137.1, 75.5, 0.61], ["+3V3", 143.35, 77.1, 0.61], ["+5V", 86.3, 68.2, 0.61], ["+5V", 91.9, 65.2, 0.61], ["+5V", 93.4, 63.7, 0.61], ["+5V", 101, 63.7, 0.61], ["EFUSE_EN3", 141.5, 82.525, 0.61], ["EFUSE_EN3", 138.6, 76.075, 0.61], ["EFUSE_EN3", 134.75, 76.85, 0.61], ["EFUSE_EN3", 135.7, 82.95, 0.61], ["EFUSE_EN3", 137.7, 84.825, 0.61], ["EFUSE_EN3", 139.975, 88.325, 0.61], ["EFUSE_EN3", 138.55, 92.425, 0.61], ["EFUSE_EN3", 145.6, 84.5, 0.61], ["EFUSE_EN3", 145.575, 80.775, 0.61], ["EFUSE_EN3", 145.7, 81.4, 0.61], ["EFUSE_EN3", 145.7, 85.9, 0.61], ["EFUSE_EN3", 132.8, 92.8, 0.61], ["EFUSE_EN3", 123, 96.1, 0.61], ["EFUSE_EN3", 102, 100.4, 0.61], ["EFUSE_EN3", 99, 101.2, 0.61], ["EFUSE_EN3", 89.5, 91.4, 0.61], ["EFUSE_EN3", 90.2, 75.7, 0.61], ["EFUSE_EN3", 93.9, 72, 0.61], ["EFUSE_EN3", 95.4, 70.5, 0.61], ["EFUSE_EN3", 97.6, 70.5, 0.61], ["EFUSE_EN3", 103.5, 67.6, 0.61], ["EFUSE_EN3", 113.6, 73, 0.61], ["EFUSE_EN3", 131, 78.1, 0.61], ["EFUSE_EN3", 131, 78.9, 0.61], ["EFUSE_EN3", 133.2, 75.4, 0.61], ["EFUSE_FLT1", 24.1, 43.5, 0.61], ["EFUSE_FLT1", 41.7, 43.3, 0.61], ["EFUSE_FLT1", 43.8, 41.2, 0.61], ["EFUSE_FLT1", 57.5, 39.7, 0.61], ["EFUSE_FLT1", 72.6, 43.1, 0.61], ["EFUSE_FLT1", 74.7, 45.3, 0.61], ["EFUSE_PG3", 104.4, 65.8, 0.61], ["EFUSE_PG3", 95.1, 62.5, 0.61], ["EFUSE_PG3", 91.8, 62.5, 0.61], ["INA_ALERT", 133.25, 49.85, 0.61], ["INA_ALERT", 138.45, 49.85, 0.61], ["INA_ALERT", 147.95, 59.75, 0.61], ["INA_ALERT", 143.75, 75.15, 0.61], ["INA_ALERT", 148, 74.8, 0.61], ["INA_ALERT", 145, 87.7, 0.61], ["INA_ALERT", 129.5, 95, 0.61], ["INA_ALERT", 103.7, 99.7, 0.61], ["INA_ALERT", 100.4, 99.7, 0.61], ["INA_ALERT", 99, 99.8, 0.61], ["INA_ALERT", 68.8, 87.5, 0.61], ["INA_ALERT", 62.1, 80.8, 0.61], ["INA_ALERT", 59.7, 78.4, 0.61], ["INA_ALERT", 58.6, 77.3, 0.61], ["K4_VUP", 79.05, 34.25, 0.61], ["K4_VUP", 80.55, 33.1, 0.61], ["SDA", 84.325, 35.975, 0.61], ["SDA", 85.325, 40.1, 0.61], ["SDA", 81.325, 41.15, 0.61], ["SDA", 80, 36.225, 0.61], ["VO1", 13.8, 44.4, 0.61], ["VO1", 17.9, 47.8, 0.61], ["VO2", 46.775, 83.175, 0.61], ["VO2", 48.975, 78.25, 0.61], ["VO3", 137.425, 83.575, 0.61], ["VO3", 137.775, 78.325, 0.61]], "line": [["GND", 1, 32.155, 80, 32.975, 80, 0.3], ["GND", 1, 32.155, 83, 32.975, 83, 0.3], ["GND", 1, 31.12, 86, 31.789, 86, 0.3], ["GND", 1, 18.565, 109.124, 18.565, 109.863, 0.3], ["GND", 1, 18.1, 112.5, 19.047, 112.5, 0.3], ["GND", 1, 23.6, 112.5, 24.547, 112.5, 0.3], ["GND", 1, 11.62, 99, 12.289, 99, 0.3], ["GND", 1, 12.924, 27.8, 13.775, 27.8, 0.3], ["GND", 1, 12.924, 31.45, 13.775, 31.45, 0.3], ["GND", 1, 12.924, 22.2, 13.775, 22.2, 0.3], ["GND", 1, 21.52, 24.92, 22.168, 24.92, 0.3], ["GND", 1, 17.378, 42.6, 18.32, 42.6, 0.3], ["GND", 1, 17.378, 40.5, 18.325, 40.5, 0.3], ["GND", 1, 17.32, 38, 17.989, 38, 0.3], ["GND", 1, 28.92, 18.5, 29.588, 18.5, 0.3], ["GND", 1, 22.69, 18.5, 23.324, 18.5, 0.3], ["GND", 1, 22.42, 20.7, 23.089, 20.7, 0.3], ["GND", 1, 18.92, 20.7, 19.588, 20.7, 0.3], ["GND", 1, 19.42, 51.8, 20.089, 51.8, 0.3], ["GND", 1, 23.69, 47.5, 24.324, 47.5, 0.3], ["GND", 1, 54.965, 97.7, 54.114, 97.7, 0.3], ["GND", 1, 54.965, 94.05, 54.114, 94.05, 0.3], ["GND", 1, 54.965, 103.3, 54.114, 103.3, 0.3], ["GND", 1, 46.809, 100.58, 47.457, 100.58, 0.3], ["GND", 1, 50.51, 82.9, 49.569, 82.9, 0.3], ["GND", 1, 51.896, 85, 52.843, 85, 0.3], ["GND", 1, 50.769, 87.72, 50.769, 88.368, 0.3], ["GND", 1, 39.169, 107.221, 39.169, 107.869, 0.3], ["GND", 1, 45.544, 107.221, 45.544, 107.979, 0.3], ["GND", 1, 45.669, 105.02, 45.669, 105.668, 0.3], ["GND", 1, 49.169, 105.02, 49.169, 105.668, 0.3], ["GND", 1, 48.669, 73.92, 48.669, 74.568, 0.3], ["GND", 1, 44.544, 78.221, 44.544, 78.979, 0.3], ["GND", 1, 143.345, 97.7, 142.494, 97.7, 0.3], ["GND", 1, 143.345, 94.05, 142.494, 94.05, 0.3], ["GND", 1, 143.345, 103.3, 142.494, 103.3, 0.3], ["GND", 1, 135.189, 100.58, 135.837, 100.58, 0.3], ["GND", 1, 138.89, 82.9, 137.949, 82.9, 0.3], ["GND", 1, 140.276, 85, 141.223, 85, 0.3], ["GND", 1, 139.149, 87.72, 139.149, 88.368, 0.3], ["GND", 1, 127.549, 107.221, 127.549, 107.869, 0.3], ["GND", 1, 133.924, 107.221, 133.924, 107.979, 0.3], ["GND", 1, 134.049, 105.02, 134.049, 105.668, 0.3], ["GND", 1, 137.549, 105.02, 137.549, 105.668, 0.3], ["GND", 1, 137.049, 73.92, 137.049, 74.568, 0.3], ["GND", 1, 132.924, 78.221, 132.924, 78.979, 0.3], ["GND", 1, 44.593, 27.8, 45.444, 27.8, 0.3], ["GND", 1, 44.593, 31.45, 45.444, 31.45, 0.3], ["GND", 1, 44.593, 22.2, 45.444, 22.2, 0.3], ["GND", 1, 53.189, 24.92, 53.837, 24.92, 0.3], ["GND", 1, 49.047, 42.6, 49.989, 42.6, 0.3], ["GND", 1, 49.047, 40.5, 49.994, 40.5, 0.3], ["GND", 1, 48.989, 38, 49.658, 38, 0.3], ["GND", 1, 60.589, 18.5, 61.258, 18.5, 0.3], ["GND", 1, 54.359, 18.5, 54.993, 18.5, 0.3], ["GND", 1, 54.089, 20.7, 54.758, 20.7, 0.3], ["GND", 1, 50.589, 20.7, 51.257, 20.7, 0.3], ["GND", 1, 51.089, 51.8, 51.758, 51.8, 0.3], ["GND", 1, 55.359, 47.5, 55.993, 47.5, 0.3], ["GND", 1, 124.124, 27.8, 124.975, 27.8, 0.3], ["GND", 1, 124.124, 31.45, 124.975, 31.45, 0.3], ["GND", 1, 124.124, 22.2, 124.975, 22.2, 0.3], ["GND", 1, 132.721, 24.92, 133.369, 24.92, 0.3], ["GND", 1, 128.579, 42.6, 129.52, 42.6, 0.3], ["GND", 1, 128.579, 40.5, 129.525, 40.5, 0.3], ["GND", 1, 128.52, 38, 129.189, 38, 0.3], ["GND", 1, 140.12, 18.5, 140.789, 18.5, 0.3], ["GND", 1, 133.89, 18.5, 134.524, 18.5, 0.3], ["GND", 1, 133.62, 20.7, 134.289, 20.7, 0.3], ["GND", 1, 130.12, 20.7, 130.789, 20.7, 0.3], ["GND", 1, 130.62, 51.8, 131.289, 51.8, 0.3], ["GND", 1, 134.89, 47.5, 135.524, 47.5, 0.3], ["GND", 1, 100.465, 12.167, 101.29, 12.167, 0.3], ["GND", 1, 98.151, 9.954, 98.151, 9.285, 0.3], ["GND", 1, 98.382, 12.977, 99.703, 13.416, 0.3], ["GND", 1, 96.322, 56.681, 96.991, 56.681, 0.3], ["GND", 1, 96.912, 42.322, 97.581, 42.322, 0.3], ["GND", 1, 72.137, 53.413, 72.137, 54.081, 0.3], ["GND", 1, 80.124, 40.496, 80.793, 40.496, 0.3], ["GND", 1, 83.153, 40.511, 84.004, 40.511, 0.3], ["GND", 1, 78.03, 40.277, 78.03, 39.608, 0.3], ["GND", 1, 110.112, 37.194, 110.781, 37.194, 0.3], ["GND", 1, 113.144, 37.21, 113.995, 37.21, 0.3], ["GND", 1, 108.021, 36.975, 108.021, 36.306, 0.3], ["GND", 1, 77.865, 13.264, 77.865, 13.933, 0.3], ["GND", 1, 23.52, 52.225, 23.52, 52.963, 0.3], ["GND", 1, 23.55, 55.95, 24.197, 55.95, 0.3], ["GND", 1, 33.75, 28.45, 34.397, 28.45, 0.3], ["GND", 1, 37.75, 28.45, 38.397, 28.45, 0.3], ["GND", 1, 33.75, 32.45, 34.397, 32.45, 0.3], ["GND", 1, 45.24, 73.55, 45.886, 73.55, 0.3], ["GND", 1, 45.24, 69.55, 45.886, 69.55, 0.3], ["GND", 1, 35.039, 97.05, 35.686, 97.05, 0.3], ["GND", 1, 31.039, 97.05, 31.686, 97.05, 0.3], ["GND", 1, 35.039, 93.05, 35.686, 93.05, 0.3], ["GND", 1, 133.619, 73.55, 134.266, 73.55, 0.3], ["GND", 1, 133.619, 69.55, 134.266, 69.55, 0.3], ["GND", 1, 123.419, 97.05, 124.066, 97.05, 0.3], ["GND", 1, 119.419, 97.05, 120.066, 97.05, 0.3], ["GND", 1, 123.419, 93.05, 124.066, 93.05, 0.3], ["GND", 1, 55.189, 52.225, 55.189, 52.963, 0.3], ["GND", 1, 55.219, 55.95, 55.866, 55.95, 0.3], ["GND", 1, 65.419, 28.45, 66.066, 28.45, 0.3], ["GND", 1, 69.419, 28.45, 70.066, 28.45, 0.3], ["GND", 1, 65.419, 32.45, 66.066, 32.45, 0.3], ["GND", 1, 134.72, 52.225, 134.72, 52.963, 0.3], ["GND", 1, 134.75, 55.95, 135.397, 55.95, 0.3], ["GND", 1, 144.95, 28.45, 145.597, 28.45, 0.3], ["GND", 1, 148.95, 28.45, 149.597, 28.45, 0.3], ["GND", 1, 144.95, 32.45, 145.597, 32.45, 0.3], ["GND", 1, 27.334, 71.5, 26.675, 71.5, 0.3], ["GND", 1, 20.567, 116.221, 20.567, 116.892, 0.3], ["GND", 1, 20.567, 118.72, 20.567, 119.391, 0.3], ["GND", 1, 11.966, 20.7, 12.624, 20.7, 0.3], ["GND", 1, 24.867, 18.721, 24.867, 19.392, 0.3], ["GND", 1, 28.966, 20.7, 29.624, 20.7, 0.3], ["GND", 1, 19.966, 45.5, 20.624, 45.5, 0.3], ["GND", 1, 19.966, 43.5, 20.624, 43.5, 0.3], ["GND", 1, 22.367, 45.721, 22.367, 46.392, 0.3], ["GND", 1, 26.966, 47.5, 27.624, 47.5, 0.3], ["GND", 1, 26.966, 41.5, 27.624, 41.5, 0.3], ["GND", 1, 32.966, 35, 33.624, 35, 0.3], ["GND", 1, 32.966, 38, 33.624, 38, 0.3], ["GND", 1, 32.966, 41, 33.624, 41, 0.3], ["GND", 1, 55.923, 104.8, 55.265, 104.8, 0.3], ["GND", 1, 43.255, 107, 43.913, 107, 0.3], ["GND", 1, 39.156, 105.02, 39.156, 105.691, 0.3], ["GND", 1, 48.156, 80.221, 48.156, 80.892, 0.3], ["GND", 1, 48.156, 82.221, 48.156, 82.892, 0.3], ["GND", 1, 45.755, 80, 46.414, 80, 0.3], ["GND", 1, 41.156, 78.221, 41.156, 78.892, 0.3], ["GND", 1, 41.156, 84.221, 41.156, 84.892, 0.3], ["GND", 1, 35.156, 90.72, 35.156, 91.392, 0.3], ["GND", 1, 35.156, 87.72, 35.156, 88.392, 0.3], ["GND", 1, 35.156, 84.72, 35.156, 85.392, 0.3], ["GND", 1, 144.303, 104.8, 143.645, 104.8, 0.3], ["GND", 1, 131.635, 107, 132.293, 107, 0.3], ["GND", 1, 127.536, 105.02, 127.536, 105.691, 0.3], ["GND", 1, 136.536, 80.221, 136.536, 80.892, 0.3], ["GND", 1, 136.536, 82.221, 136.536, 82.892, 0.3], ["GND", 1, 134.135, 80, 134.794, 80, 0.3], ["GND", 1, 129.536, 78.221, 129.536, 78.892, 0.3], ["GND", 1, 129.536, 84.221, 129.536, 84.892, 0.3], ["GND", 1, 123.536, 90.72, 123.536, 91.392, 0.3], ["GND", 1, 123.536, 87.72, 123.536, 88.392, 0.3], ["GND", 1, 123.536, 84.72, 123.536, 85.392, 0.3], ["GND", 1, 43.635, 20.7, 44.293, 20.7, 0.3], ["GND", 1, 56.536, 18.721, 56.536, 19.392, 0.3], ["GND", 1, 60.635, 20.7, 61.293, 20.7, 0.3], ["GND", 1, 51.635, 45.5, 52.293, 45.5, 0.3], ["GND", 1, 51.635, 43.5, 52.293, 43.5, 0.3], ["GND", 1, 54.036, 45.721, 54.036, 46.392, 0.3], ["GND", 1, 58.635, 47.5, 59.293, 47.5, 0.3], ["GND", 1, 58.635, 41.5, 59.293, 41.5, 0.3], ["GND", 1, 64.635, 35, 65.293, 35, 0.3], ["GND", 1, 64.635, 38, 65.293, 38, 0.3], ["GND", 1, 64.635, 41, 65.293, 41, 0.3], ["GND", 1, 123.166, 20.7, 123.824, 20.7, 0.3], ["GND", 1, 136.067, 18.721, 136.067, 19.392, 0.3], ["GND", 1, 140.166, 20.7, 140.825, 20.7, 0.3], ["GND", 1, 131.166, 45.5, 131.825, 45.5, 0.3], ["GND", 1, 131.166, 43.5, 131.825, 43.5, 0.3], ["GND", 1, 133.567, 45.721, 133.567, 46.392, 0.3], ["GND", 1, 138.166, 47.5, 138.825, 47.5, 0.3], ["GND", 1, 138.166, 41.5, 138.825, 41.5, 0.3], ["GND", 1, 144.166, 35, 144.825, 35, 0.3], ["GND", 1, 144.166, 38, 144.825, 38, 0.3], ["GND", 1, 144.166, 41, 144.825, 41, 0.3], ["GND", 1, 150.703, 51.86, 150.703, 52.518, 0.3], ["GND", 1, 150.923, 54.86, 151.044, 55.45, 0.3], ["GND", 1, 77.991, 35.746, 77.883, 36.35, 0.3], ["GND", 1, 107.981, 32.446, 107.873, 33.049, 0.3], ["GND", 1, 71.182, 36.753, 71.891, 36.753, 0.3], ["GND", 1, 71.182, 26.753, 71.891, 26.753, 0.3], ["GND", 1, 15.075, 28.09, 15.075, 28.5, 0.3], ["GND", 1, 15.075, 28.5, 15.075, 29.174, 0.3], ["GND", 1, 14.725, 28.59, 14.222, 28.854, 0.3], ["GND", 1, 52.814, 97.41, 52.814, 97, 0.3], ["GND", 1, 52.814, 97, 52.814, 96.326, 0.3], ["GND", 1, 53.164, 96.91, 53.667, 96.647, 0.3], ["GND", 1, 141.194, 97.41, 141.194, 97, 0.3], ["GND", 1, 141.194, 97, 141.194, 96.326, 0.3], ["GND", 1, 141.544, 96.91, 142.048, 96.647, 0.3], ["GND", 1, 46.744, 28.09, 46.744, 28.5, 0.3], ["GND", 1, 46.744, 28.5, 46.744, 29.174, 0.3], ["GND", 1, 46.394, 28.59, 45.891, 28.854, 0.3], ["GND", 1, 126.275, 28.09, 126.275, 28.5, 0.3], ["GND", 1, 126.275, 28.5, 126.275, 29.174, 0.3], ["GND", 1, 125.925, 28.59, 125.422, 28.854, 0.3], ["GND", 1, 13.21, 50.196, 12.579, 50.196, 0.3], ["GND", 1, 13.8, 50.45, 13.8, 51.012, 0.3], ["GND", 1, 14.8, 54.67, 14.8, 55.232, 0.3], ["GND", 1, 54.679, 75.304, 55.31, 75.304, 0.3], ["GND", 1, 53.089, 72.35, 53.089, 72.912, 0.3], ["GND", 1, 142.469, 76.57, 142.469, 77.132, 0.3], ["GND", 1, 141.469, 72.35, 141.469, 72.912, 0.3], ["GND", 1, 46.469, 54.67, 46.469, 55.232, 0.3], ["GND", 1, 124.41, 50.196, 123.779, 50.196, 0.3], ["GND", 1, 126, 54.67, 126, 55.232, 0.3], ["GND", 1, 5.5, 97.65, 5.5, 98.212, 0.3], ["GND", 1, 7, 101.87, 7, 102.432, 0.3], ["GND", 1, 15.65, 44.3, 16.524, 44.3, 0.3], ["GND", 1, 15.65, 47.3, 16.524, 47.3, 0.3], ["GND", 1, 52.239, 81.2, 51.365, 81.2, 0.3], ["GND", 1, 52.239, 78.2, 51.365, 78.2, 0.3], ["GND", 1, 140.619, 81.2, 139.745, 81.2, 0.3], ["GND", 1, 140.619, 78.2, 139.745, 78.2, 0.3], ["GND", 1, 47.319, 44.3, 48.193, 44.3, 0.3], ["GND", 1, 47.319, 47.3, 48.193, 47.3, 0.3], ["GND", 1, 126.85, 44.3, 127.724, 44.3, 0.3], ["GND", 1, 126.85, 47.3, 127.724, 47.3, 0.3], ["GND", 1, 20.85, 103.05, 21.476, 103.05, 0.3], ["GND", 1, 96.05, 9.305, 95.375, 9.305, 0.3], ["GND", 1, 79.951, 9.305, 80.625, 9.305, 0.3], ["GND", 1, 88.5, 18.825, 88.535, 19.475, 0.3], ["GND", 1, 89.9, 18.825, 89.935, 19.475, 0.3], ["GND", 1, 91.3, 18.425, 92.036, 18.425, 0.3], ["GND", 1, 91.3, 15.625, 92.036, 15.625, 0.3], ["GND", 1, 89.101, 15.226, 89.066, 14.576, 0.3], ["GND", 1, 87.701, 16.025, 87.051, 16.06, 0.3], ["GND", 1, 87.701, 17.425, 87.051, 17.46, 0.3], ["GND", 1, 91.3, 17.025, 92.036, 17.025, 0.3], ["GND", 1, 89.9, 16.626, 90.49, 14.636, 0.3], ["GND", 1, 96.946, 49.634, 98.225, 49.634, 0.3], ["GND", 1, 97.536, 35.275, 98.815, 35.275, 0.3], ["GND", 1, 74.225, 47.383, 74.225, 47.957, 0.3], ["GND", 1, 73.575, 45.832, 73.575, 45.258, 0.3], ["GND", 1, 80.224, 46.608, 81.424, 46.608, 0.3], ["GND", 1, 79.425, 47.383, 79.425, 47.957, 0.3], ["GND", 1, 75.525, 53.428, 75.525, 54.002, 0.3], ["GND", 1, 74.875, 51.877, 74.875, 51.303, 0.3], ["GND", 1, 76.175, 51.877, 76.175, 51.303, 0.3], ["GND", 1, 76.825, 53.428, 76.825, 54.002, 0.3], ["GND", 1, 11.951, 94, 12.597, 94, 0.3], ["GND", 1, 67.576, 71.565, 66.837, 71.565, 0.3], ["GND", 1, 71.324, 71, 72.175, 71, 0.3], ["GND", 1, 78.127, 80.286, 78.127, 81.107, 0.3], ["GND", 1, 80.814, 79.593, 81.639, 79.593, 0.3], ["GND", 1, 59.567, 71.72, 59.567, 72.392, 0.3], ["GND", 1, 64.85, 71.05, 64.224, 71.05, 0.3], ["GND", 1, 96.696, 68.265, 97.975, 68.265, 0.3], ["GND", 1, 101.067, 80.72, 101.067, 81.392, 0.3], ["GND", 1, 104.286, 74, 105.232, 74, 0.3], ["GND", 1, 105.666, 78, 106.324, 78, 0.3], ["GND", 1, 107.62, 74, 108.289, 74, 0.3], ["GND", 1, 103.45, 70.45, 104.097, 70.45, 0.3], ["GND", 1, 77.652, 11.037, 77.033, 11.012, 0.3], ["GND", 1, 151.676, 48.589, 150.728, 48.589, 0.3], ["GND", 1, 151.676, 55.498, 150.236, 55.498, 0.3], ["GND", 1, 79.83, 39.16, 79.83, 38.71, 0.3], ["GND", 1, 109.82, 35.86, 109.82, 35.41, 0.3], ["+12V", 1, 20.655, 108.5, 21.475, 108.5, 1], ["+12V", 1, 20.655, 109.124, 21.043, 109.543, 1], ["+12V", 1, 20, 109.124, 20, 109.975, 1], ["+12V", 1, 12.924, 25.8, 13.775, 25.8, 1], ["+12V", 1, 11.676, 26.365, 10.937, 26.365, 1], ["+12V", 1, 11.676, 25.235, 10.937, 25.235, 1], ["+12V", 1, 12.924, 30.015, 13.663, 30.015, 1], ["+12V", 1, 11.676, 30.015, 10.937, 30.015, 1], ["+12V", 1, 11.676, 29.45, 10.324, 29.45, 1], ["+12V", 1, 12.924, 24.2, 13.775, 24.2, 1], ["+12V", 1, 11.676, 24.2, 10.824, 24.2, 1], ["+12V", 1, 12.924, 24.855, 14.125, 24.956, 1], ["+12V", 1, 21.52, 24.08, 22.168, 24.08, 0.45], ["+12V", 1, 54.965, 100.265, 54.226, 100.265, 1], ["+12V", 1, 54.965, 99.135, 54.226, 99.135, 1], ["+12V", 1, 54.965, 95.485, 54.226, 95.485, 1], ["+12V", 1, 56.213, 96.05, 57.064, 96.05, 1], ["+12V", 1, 57.064, 96.05, 57.864, 96.05, 1], ["+12V", 1, 56.213, 101.3, 57.064, 101.3, 1], ["+12V", 1, 54.965, 101.865, 54.226, 101.865, 1], ["+12V", 1, 54.965, 101.3, 53.613, 101.3, 1], ["+12V", 1, 46.809, 101.42, 47.457, 101.42, 0.45], ["+12V", 1, 143.345, 100.265, 142.606, 100.265, 1], ["+12V", 1, 143.345, 99.135, 142.606, 99.135, 1], ["+12V", 1, 143.345, 95.485, 142.606, 95.485, 1], ["+12V", 1, 144.593, 96.05, 145.444, 96.05, 1], ["+12V", 1, 145.444, 96.05, 146.244, 96.05, 1], ["+12V", 1, 144.593, 101.3, 145.444, 101.3, 1], ["+12V", 1, 143.345, 101.865, 142.606, 101.865, 1], ["+12V", 1, 143.345, 101.3, 141.993, 101.3, 1], ["+12V", 1, 135.189, 101.42, 135.837, 101.42, 0.45], ["+12V", 1, 44.593, 25.8, 45.444, 25.8, 1], ["+12V", 1, 43.345, 26.365, 42.606, 26.365, 1], ["+12V", 1, 43.345, 25.235, 42.606, 25.235, 1], ["+12V", 1, 44.593, 30.015, 45.332, 30.015, 1], ["+12V", 1, 43.345, 30.015, 42.606, 30.015, 1], ["+12V", 1, 43.345, 29.45, 41.993, 29.45, 1], ["+12V", 1, 44.593, 24.2, 45.444, 24.2, 1], ["+12V", 1, 43.345, 24.2, 42.493, 24.2, 1], ["+12V", 1, 44.593, 24.855, 45.794, 24.956, 1], ["+12V", 1, 53.189, 24.08, 53.837, 24.08, 0.45], ["+12V", 1, 124.124, 25.8, 124.975, 25.8, 1], ["+12V", 1, 122.876, 26.365, 122.137, 26.365, 1], ["+12V", 1, 122.876, 25.235, 122.137, 25.235, 1], ["+12V", 1, 124.124, 30.015, 124.863, 30.015, 1], ["+12V", 1, 122.876, 30.015, 122.137, 30.015, 1], ["+12V", 1, 122.876, 29.45, 121.524, 29.45, 1], ["+12V", 1, 124.124, 24.2, 124.975, 24.2, 1], ["+12V", 1, 122.876, 24.2, 122.024, 24.2, 1], ["+12V", 1, 124.124, 24.855, 125.325, 24.956, 1], ["+12V", 1, 132.721, 24.08, 133.369, 24.08, 0.45], ["+12V", 1, 23.595, 117.199, 23.595, 117.789, 0.517], ["+12V", 1, 24.865, 117.199, 24.865, 117.789, 0.517], ["+12V", 1, 26.135, 117.199, 26.135, 117.789, 0.517], ["+12V", 1, 18.666, 118.5, 19.324, 118.5, 0.487], ["+12V", 1, 18.666, 121, 19.324, 121, 0.487], ["+12V", 1, 24.867, 20.921, 24.867, 21.592, 0.487], ["+12V", 1, 43.255, 104.8, 43.913, 104.8, 0.487], ["+12V", 1, 131.635, 104.8, 132.293, 104.8, 0.487], ["+12V", 1, 56.536, 20.921, 56.536, 21.592, 0.487], ["+12V", 1, 136.067, 20.921, 136.067, 21.592, 0.487], ["+12V", 1, 8.975, 91.822, 8, 91, 1], ["+12V", 1, 8.975, 91.822, 8.9, 91, 1], ["+12V", 1, 10.158, 91.822, 10.7, 91, 1], ["+12V", 1, 8.975, 91.822, 8, 90, 1], ["+12V", 1, 8.975, 91.822, 8.9, 90, 1], ["+12V", 1, 10.158, 91.822, 10.7, 90, 1], ["+12V", 1, 8.975, 91.822, 8, 89, 1], ["+12V", 1, 8.975, 91.822, 8.9, 89, 1], ["+12V", 1, 9.8, 91.822, 9.8, 91, 1], ["+12V", 1, 9.8, 91, 9.8, 90, 1], ["+12V", 1, 9.8, 90, 9.8, 89, 1], ["+12V", 1, 10.158, 91.822, 10.7, 89, 1], ["+12V", 1, 14.725, 26.41, 14.722, 25.647, 0.3], ["+12V", 1, 14.725, 27, 14.151, 27, 0.3], ["+12V", 1, 15.075, 27.41, 15.075, 27, 0.3], ["+12V", 1, 15.075, 27, 15.075, 26.5, 0.3], ["+12V", 1, 15.075, 26.5, 15.075, 24.926, 0.3], ["+12V", 1, 53.164, 99.09, 53.467, 99.653, 0.3], ["+12V", 1, 53.164, 98.5, 53.738, 98.5, 0.3], ["+12V", 1, 52.814, 98.09, 52.814, 98.5, 0.3], ["+12V", 1, 52.814, 98.5, 52.814, 99, 0.3], ["+12V", 1, 52.814, 99, 52.814, 100.124, 0.3], ["+12V", 1, 141.544, 99.09, 141.847, 99.653, 0.3], ["+12V", 1, 141.544, 98.5, 142.118, 98.5, 0.3], ["+12V", 1, 141.194, 98.09, 141.194, 98.5, 0.3], ["+12V", 1, 141.194, 98.5, 141.194, 99, 0.3], ["+12V", 1, 141.194, 99, 141.194, 100.124, 0.3], ["+12V", 1, 46.394, 26.41, 46.391, 25.647, 0.3], ["+12V", 1, 46.394, 27, 45.82, 27, 0.3], ["+12V", 1, 46.744, 27.41, 46.744, 27, 0.3], ["+12V", 1, 46.744, 27, 46.744, 26.5, 0.3], ["+12V", 1, 46.744, 26.5, 46.744, 24.926, 0.3], ["+12V", 1, 125.925, 26.41, 125.922, 25.647, 0.3], ["+12V", 1, 125.925, 27, 125.351, 27, 0.3], ["+12V", 1, 126.275, 27.41, 126.275, 27, 0.3], ["+12V", 1, 126.275, 27, 126.275, 26.5, 0.3], ["+12V", 1, 126.275, 26.5, 126.275, 24.926, 0.3], ["+12V", 1, 20.85, 104.95, 21.476, 104.95, 0.539], ["+12V", 1, 18.15, 104, 18.776, 104, 0.539], ["+12V", 1, 68.824, 73.655, 69.243, 74.043, 1], ["+12V", 1, 68.2, 73.655, 68.2, 74.476, 1], ["+12V", 1, 67.576, 73.655, 67.157, 74.043, 1], ["+12V", 1, 71.324, 73, 72.175, 73, 1], ["+12V", 1, 71.324, 73.655, 71.743, 74.043, 1], ["+12V", 1, 70.7, 73.655, 70.7, 74.476, 1], ["+12V", 1, 65.85, 72.95, 66.476, 72.95, 0.539], ["+12V", 1, 63.15, 72, 63.776, 72, 0.539], ["+12V", 1, 101.1, 74, 102.047, 74, 1], ["+12V", 1, 101.1, 74.814, 101.567, 75.159, 1], ["+12V", 1, 100.407, 74.814, 100.407, 75.639, 1], ["+12V", 1, 97.567, 78.221, 97.567, 78.892, 0.487], ["+12V", 1, 107.25, 69.5, 108.214, 69.5, 1], ["+12V", 1, 107.25, 70.45, 107.653, 70.853, 1], ["+12V", 1, 106.3, 70.45, 106.3, 71.414, 1], ["+3V3", 1, 18.38, 52.021, 18.38, 52.668, 0.45], ["+3V3", 1, 50.049, 52.021, 50.049, 52.668, 0.45], ["+3V3", 1, 129.58, 52.021, 129.58, 52.668, 0.45], ["+3V3", 1, 98.371, 10.994, 101.019, 10.994, 0.45], ["+3V3", 1, 95.282, 56.902, 95.282, 57.55, 0.45], ["+3V3", 1, 95.872, 42.543, 95.872, 43.19, 0.45], ["+3V3", 1, 79.084, 40.717, 79.084, 41.364, 0.45], ["+3V3", 1, 109.072, 37.415, 109.072, 38.062, 0.45], ["+3V3", 1, 22.367, 43.721, 22.367, 44.392, 0.487], ["+3V3", 1, 26.966, 45.5, 27.624, 45.5, 0.487], ["+3V3", 1, 24.034, 51, 23.375, 51, 0.487], ["+3V3", 1, 54.036, 43.721, 54.036, 44.392, 0.487], ["+3V3", 1, 58.402, 45.721, 58.402, 46.392, 0.487], ["+3V3", 1, 55.703, 51, 55.045, 51, 0.487], ["+3V3", 1, 133.567, 43.721, 133.567, 44.392, 0.487], ["+3V3", 1, 138.166, 45.5, 138.825, 45.5, 0.487], ["+3V3", 1, 135.234, 51, 134.575, 51, 0.487], ["+3V3", 1, 85.906, 28.693, 85.906, 29.365, 0.487], ["+3V3", 1, 98.371, 17.761, 99.043, 17.761, 0.487], ["+3V3", 1, 77.458, 45.208, 76.8, 45.208, 0.487], ["+3V3", 1, 79.563, 44.933, 79.563, 44.261, 0.487], ["+3V3", 1, 91.459, 56.902, 91.459, 57.573, 0.487], ["+3V3", 1, 76.838, 39.39, 76.166, 39.39, 0.487], ["+3V3", 1, 106.828, 36.089, 106.156, 36.089, 0.487], ["+3V3", 1, 76.766, 9.745, 76.369, 10.154, 0.487], ["+3V3", 1, 76.765, 11.81, 76.094, 11.81, 0.487], ["+3V3", 1, 15.39, 53.91, 16.622, 53.91, 0.3], ["+3V3", 1, 44.879, 50.196, 44.248, 50.196, 0.3], ["+3V3", 1, 45.469, 50.45, 45.469, 51.012, 0.3], ["+3V3", 1, 47.059, 53.91, 48.291, 53.91, 0.3], ["+3V3", 1, 126.59, 53.91, 127.822, 53.91, 0.3], ["+3V3", 1, 96.05, 10.575, 95.375, 10.575, 0.5], ["+3V3", 1, 95.375, 10.575, 94.575, 10.575, 0.5], ["+3V3", 1, 94.575, 10.575, 93.775, 10.575, 0.5], ["+3V3", 1, 87.805, 56.041, 87.805, 56.636, 0.5], ["+3V3", 1, 95.425, 54.17, 95.425, 53.575, 0.5], ["+3V3", 1, 88.395, 41.681, 88.395, 42.276, 0.5], ["+3V3", 1, 96.015, 39.81, 96.015, 39.215, 0.5], ["+3V3", 1, 87.555, 74.671, 87.555, 75.266, 0.5], ["+3V3", 1, 95.175, 74.671, 95.175, 75.266, 0.5], ["+3V3", 1, 79.33, 39.86, 79.33, 40.376, 0.2], ["+3V3", 1, 109.32, 36.56, 109.32, 37.074, 0.2], ["VO1_P", 1, 26.997, 53.025, 26.997, 54.599, 1], ["VO1_P", 1, 26.1, 53.025, 26.1, 54.777, 1], ["VO1_P", 1, 25.203, 53.025, 25.203, 54.599, 1], ["VO1_P", 1, 17.958, 56.8, 19.71, 56.8, 1], ["VO1_P", 1, 17.958, 57.697, 19.531, 57.697, 1], ["VO1_P", 1, 17.958, 58.457, 19.023, 58.457, 1], ["VO1_P", 1, 14.3, 53.15, 14.3, 52.588, 0.3], ["VO2_P", 1, 40.892, 72.475, 40.892, 70.901, 1], ["VO2_P", 1, 41.789, 72.475, 41.789, 70.723, 1], ["VO2_P", 1, 42.686, 72.475, 42.686, 70.901, 1], ["VO2_P", 1, 51.114, 68.7, 52.866, 68.7, 1], ["VO2_P", 1, 51.114, 69.597, 52.688, 69.597, 1], ["VO2_P", 1, 51.114, 70.378, 51.419, 70.865, 1], ["VO2_P", 1, 53.589, 70.83, 53.589, 70.268, 0.3], ["VO3_P", 1, 128.512, 72.475, 128.512, 71.409, 1], ["VO3_P", 1, 129.272, 72.475, 129.272, 70.901, 1], ["VO3_P", 1, 130.169, 72.475, 130.169, 70.723, 1], ["VO3_P", 1, 139.494, 68.7, 141.246, 68.7, 1], ["VO3_P", 1, 139.494, 69.597, 141.068, 69.597, 1], ["VO3_P", 1, 139.494, 70.378, 139.8, 70.865, 1], ["VO3_P", 1, 141.969, 70.83, 141.969, 70.268, 0.3], ["VO4_P", 1, 59.426, 53.025, 59.426, 54.091, 1], ["VO4_P", 1, 58.666, 53.025, 58.666, 54.599, 1], ["VO4_P", 1, 57.769, 53.025, 57.769, 54.777, 1], ["VO4_P", 1, 49.627, 56.8, 51.379, 56.8, 1], ["VO4_P", 1, 49.627, 57.697, 51.2, 57.697, 1], ["VO4_P", 1, 49.627, 58.457, 50.692, 58.457, 1], ["VO4_P", 1, 45.969, 53.15, 45.969, 52.588, 0.3], ["VO5_P", 1, 138.957, 53.025, 138.957, 54.091, 1], ["VO5_P", 1, 138.197, 53.025, 138.197, 54.599, 1], ["VO5_P", 1, 137.3, 53.025, 137.3, 54.777, 1], ["VO5_P", 1, 129.158, 56.8, 130.91, 56.8, 1], ["VO5_P", 1, 129.158, 57.697, 130.731, 57.697, 1], ["VO5_P", 1, 129.158, 58.457, 130.223, 58.457, 1], ["VO5_P", 1, 125.5, 53.15, 125.5, 52.588, 0.3], ["+12V", 1, 12.301, 25.799, 14.9, 26.5, 1], ["+12V", 1, 14.9, 26.5, 14.9, 27.45, 0.4], ["+12V", 1, 10.85, 24.201, 12.301, 24.201, 0.8], ["+12V", 1, 10.85, 25.799, 12.301, 25.799, 0.8], ["+12V", 1, 10.85, 24.201, 10.85, 25.799, 0.8], ["+12V", 1, 10.85, 25.799, 10.85, 29.449, 0.8], ["+12V", 1, 10.85, 29.449, 12.301, 29.449, 0.8], ["$2N665", 1, 18.524, 27.501, 19.5, 27.501, 0.3], ["$2N665", 1, 19.5, 27.501, 19.5, 28.001, 0.3], ["$2N665", 1, 18.524, 28.001, 19.5, 28.001, 0.3], ["$2N665", 1, 19.8, 28, 21.8, 28, 1.2], ["$2N665", 1, 21.8, 28, 21.8, 32.1, 1.5], ["$2N667", 1, 18.524, 28.501, 19.2, 29.25, 0.3], ["$2N667", 1, 19.2, 29.25, 20.279, 29.25, 0.3], ["VO1", 1, 16.2, 33.9, 16.2, 34.9, 1.5], ["VO1", 1, 13.5, 37.6, 16.2, 34.9, 1.5], ["VO1", 1, 13.5, 40.5, 13.5, 42.6, 1.35], ["VO1", 1, 13.5, 42.6, 13.5, 43.9, 1.35], ["VO1", 1, 13.5, 38.2, 16.279, 38.001, 0.5], ["VO1", 1, 13.5, 37.6, 13.5, 38.2, 1.35], ["VO1", 1, 13.5, 38.2, 13.5, 40.5, 1.35], ["VO1", 1, 13.5, 43.9, 12.6, 43.9, 0.3], ["VO1", 1, 12.6, 43.9, 12.301, 44.2, 0.3], ["VO1", 1, 12.301, 44.2, 12.301, 45.05, 0.3], ["VO1", 1, 12.301, 45.05, 12.301, 45.5, 0.3], ["$2N699", 1, 12.301, 46.25, 12.301, 46.55, 0.6], ["$2N699", 1, 12.301, 46.55, 12.301, 47.34, 0.6], ["$2N699", 1, 13.699, 47.34, 12.301, 47.34, 1], ["$2N699", 1, 12.301, 47.34, 11.95, 47.34, 1], ["$2N699", 1, 11.95, 47.34, 11.35, 47.94, 1.2], ["$2N699", 1, 11.35, 47.94, 11.35, 55.6, 1.2], ["$2N699", 1, 13.26, 53.909, 13.26, 55.4, 0.3], ["$2N699", 1, 13.26, 55.4, 13.06, 55.6, 0.3], ["$2N699", 1, 13.06, 55.6, 11.6, 55.6, 0.3], ["VO1_P", 1, 13.8, 53.909, 13.8, 55.8, 0.3], ["VO1_P", 1, 13.8, 55.8, 14, 56, 0.3], ["VO1_P", 1, 14, 56, 16.9, 56, 0.3], ["$2N651", 1, 16.05, 25.776, 16.05, 20, 0.25], ["$2N651", 1, 16.05, 20, 15.45, 19.4, 0.25], ["$2N651", 1, 15.45, 19.4, 14.366, 19.4, 0.25], ["$2N651", 1, 14.366, 19.4, 14.366, 18.501, 0.25], ["$2N651", 1, 14.366, 18.501, 11.732, 18.501, 0.25], ["$2N651", 1, 11.732, 18.501, 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15.425, 48.075, 0.2], ["EFUSE_PG1", 1, 15.425, 48.075, 17.675, 50.325, 0.2], ["EFUSE_PG1", 1, 80.075, 52.654, 80.075, 53.779, 0.2], ["EFUSE_PG1", 1, 17.675, 50.325, 19.6, 48.4, 0.2], ["EFUSE_PG1", 1, 19.6, 48.4, 22.2, 48.4, 0.2], ["EFUSE_PG1", 2, 22.2, 48.4, 25.284, 45.499, 0.2], ["EFUSE_PG1", 2, 25.55, 45.6, 26.75, 46.8, 0.2], ["EFUSE_PG1", 2, 26.75, 46.8, 47.7, 46.8, 0.2], ["EFUSE_PG1", 2, 47.7, 46.8, 47.85, 46.65, 0.2], ["EFUSE_PG1", 2, 47.85, 46.65, 53.3, 46.65, 0.2], ["EFUSE_PG1", 2, 53.3, 46.65, 53.7, 47.05, 0.2], ["EFUSE_PG1", 2, 53.7, 47.05, 55.45, 47.05, 0.2], ["EFUSE_PG1", 2, 55.45, 47.05, 55.65, 46.85, 0.2], ["EFUSE_PG1", 2, 55.65, 46.85, 57.85, 46.85, 0.2], ["EFUSE_PG1", 2, 57.85, 46.85, 58.05, 47.05, 0.2], ["EFUSE_PG1", 2, 58.05, 47.05, 58.75, 47.05, 0.2], ["EFUSE_PG1", 2, 58.75, 47.05, 58.95, 46.85, 0.2], ["EFUSE_PG1", 2, 58.95, 46.85, 67.8, 46.85, 0.2], ["EFUSE_PG1", 2, 67.8, 46.85, 69.6, 48.65, 0.2], ["EFUSE_PG1", 1, 69.6, 48.65, 69.9, 48.95, 0.2], ["EFUSE_PG1", 1, 69.9, 48.95, 69.9, 50.7, 0.2], ["EFUSE_PG1", 2, 69.9, 50.7, 73.85, 54.65, 0.2], ["EFUSE_PG1", 2, 73.85, 54.65, 76.2, 54.65, 0.2], ["EFUSE_PG1", 1, 76.2, 54.65, 78.5, 54.65, 0.2], ["EFUSE_PG1", 2, 78.5, 54.65, 79.35, 53.8, 0.2], ["EFUSE_PG1", 2, 79.35, 53.8, 80.075, 53.779, 0.2], ["EFUSE_PG2", 1, 42.022, 80, 42.605, 80, 0.2], ["EFUSE_PG2", 1, 52.84, 78.199, 52.828, 77.6, 0.2], ["EFUSE_PG2", 1, 52.828, 77.6, 52.65, 77.425, 0.2], ["EFUSE_PG2", 1, 52.65, 77.425, 52.475, 77.425, 0.2], ["EFUSE_PG2", 1, 52.475, 77.425, 50.25, 75.15, 0.2], ["EFUSE_PG2", 1, 79.425, 52.654, 79.425, 53.779, 0.2], ["EFUSE_PG2", 1, 50.25, 75.15, 50.2, 75.2, 0.2], ["EFUSE_PG2", 2, 50.2, 75.2, 41.5, 75.3, 0.2], ["EFUSE_PG2", 1, 41.5, 75.3, 40.4, 74.2, 0.2], ["EFUSE_PG2", 1, 40.4, 74.2, 39.3, 74.2, 0.2], ["EFUSE_PG2", 2, 39.3, 74.2, 37.2, 74.3, 0.2], ["EFUSE_PG2", 1, 37.2, 74.3, 39.5, 76.6, 0.2], ["EFUSE_PG2", 1, 39.5, 76.6, 39.5, 78.4, 0.2], ["EFUSE_PG2", 2, 39.5, 78.4, 40.7, 79.6, 0.2], ["EFUSE_PG2", 2, 40.7, 79.6, 42.2, 79.6, 0.2], ["EFUSE_PG2", 2, 42.2, 79.6, 42.605, 80, 0.2], ["EFUSE_PG3", 1, 130.401, 80, 130.984, 80, 0.2], ["EFUSE_PG3", 1, 141.219, 78.199, 141.204, 77.6, 0.2], ["EFUSE_PG3", 1, 141.204, 77.6, 141.025, 77.425, 0.2], ["EFUSE_PG3", 1, 141.025, 77.425, 140.85, 77.425, 0.2], ["EFUSE_PG3", 1, 140.85, 77.425, 138.6, 75.175, 0.2], ["EFUSE_PG3", 1, 138.6, 75.175, 137.6, 76.15, 0.2], ["EFUSE_PG3", 1, 137.6, 76.15, 132.7, 76.15, 0.2], ["EFUSE_PG3", 1, 132.7, 76.15, 132.5, 76.35, 0.2], ["EFUSE_PG3", 2, 132.5, 76.35, 131.7, 76.35, 0.2], ["EFUSE_PG3", 2, 131.7, 76.35, 130.3, 77.75, 0.2], ["EFUSE_PG3", 2, 130.3, 77.75, 130.3, 79.3, 0.2], ["EFUSE_PG3", 2, 130.3, 79.3, 130.984, 80, 0.2], ["EFUSE_PG4", 1, 57.536, 45.499, 56.953, 45.499, 0.2], ["EFUSE_PG4", 1, 46.718, 47.3, 46.743, 47.9, 0.2], ["EFUSE_PG4", 1, 46.743, 47.9, 46.925, 48.075, 0.2], ["EFUSE_PG4", 1, 46.925, 48.075, 47.1, 48.075, 0.2], ["EFUSE_PG4", 1, 47.1, 48.075, 49.35, 50.325, 0.2], ["EFUSE_PG4", 1, 78.124, 52.654, 78.124, 53.779, 0.2], ["EFUSE_PG4", 1, 49.35, 50.325, 51, 48.65, 0.2], ["EFUSE_PG4", 1, 51, 48.65, 51.5, 48.65, 0.2], ["EFUSE_PG4", 1, 51.5, 48.65, 52.45, 47.7, 0.2], ["EFUSE_PG4", 1, 52.45, 47.7, 52.45, 46.3, 0.2], ["EFUSE_PG4", 1, 52.45, 46.3, 53.2, 45.55, 0.2], ["EFUSE_PG4", 1, 53.2, 45.55, 53.2, 44.05, 0.2], ["EFUSE_PG4", 2, 53.2, 44.05, 53.5, 43.75, 0.2], ["EFUSE_PG4", 2, 53.5, 43.75, 55.6, 43.75, 0.2], ["EFUSE_PG4", 2, 55.6, 43.75, 56.6, 44.75, 0.2], ["EFUSE_PG4", 1, 56.6, 44.75, 56.95, 45.1, 0.2], ["EFUSE_PG4", 1, 56.95, 45.1, 56.953, 45.499, 0.2], ["EFUSE_PG5", 1, 126.251, 47.3, 126.27, 47.9, 0.2], ["EFUSE_PG5", 1, 126.27, 47.9, 126.45, 48.075, 0.2], ["EFUSE_PG5", 1, 126.45, 48.075, 126.625, 48.075, 0.2], ["EFUSE_PG5", 1, 126.625, 48.075, 128.875, 50.325, 0.2], ["EFUSE_PG5", 1, 77.474, 52.654, 77.474, 53.779, 0.2], ["EFUSE_PG5", 1, 128.875, 50.325, 130.4, 48.8, 0.2], ["EFUSE_PG5", 1, 130.4, 48.8, 130.4, 48.4, 0.2], ["EFUSE_PG5", 2, 130.4, 48.4, 133.1, 45.7, 0.2], ["EFUSE_PG5", 2, 133.1, 45.7, 135, 45.7, 0.2], ["EFUSE_PG5", 2, 135, 45.7, 135.6, 45.1, 0.2], ["EFUSE_PG5", 1, 135.6, 45.1, 136, 45.5, 0.2], ["EFUSE_PG5", 1, 136, 45.5, 137.069, 45.499, 0.2], ["FB3V3", 1, 17.651, 104.95, 16.801, 104.95, 0.2], ["FB3V3", 1, 17.5, 116, 17.567, 115.999, 0.2], ["FB3V3", 2, 17.5, 116, 19.1, 117.6, 0.2], ["FB3V3", 2, 19.1, 117.6, 22.4, 117.6, 0.2], ["FB3V3", 2, 22.4, 117.6, 22.6, 117.4, 0.2], ["FB3V3", 2, 22.6, 117.4, 22.777, 116.918, 0.2], ["FB3V3", 2, 22.777, 116.918, 22.7, 116, 0.2], ["FB3V3", 1, 22.7, 116, 21.433, 115.999, 0.2], ["FB3V3", 1, 17.3, 115.75, 16.3, 114.75, 0.2], ["FB3V3", 1, 16.3, 114.75, 16.3, 110.5, 0.2], ["FB3V3", 1, 16.3, 110.5, 15.9, 110.1, 0.2], ["FB3V3", 2, 15.9, 110.1, 15.9, 105.85, 0.2], ["FB3V3", 1, 15.9, 105.85, 16.801, 104.95, 0.2], ["GATE", 1, 25.919, 68.001, 26.469, 68.001, 0.2], ["GATE", 1, 26.469, 68.001, 26.135, 67.65, 0.2], ["GATE", 1, 26.135, 67.65, 25.316, 67.328, 0.2], ["GATE", 1, 25.316, 67.328, 24.473, 67.378, 0.2], ["GATE", 1, 24.473, 67.378, 23.878, 67.7, 0.2], ["GATE", 1, 23.878, 67.7, 23.655, 68.001, 0.2], ["GATE", 1, 25.675, 68.25, 25.675, 68.4, 0.2], ["GATE", 1, 25.675, 68.4, 21.475, 72.6, 0.2], ["GATE", 1, 21.475, 72.6, 21.232, 72.596, 0.2], ["INA_ALERT", 1, 80.428, 45.154, 81.011, 45.154, 0.2], ["INA_ALERT", 1, 14.3, 49.69, 14.3, 49.075, 0.2], ["INA_ALERT", 1, 14.3, 49.075, 14.3, 50.6, 0.2], ["INA_ALERT", 1, 14.3, 50.6, 16.625, 52.95, 0.2], ["INA_ALERT", 1, 53.589, 75.809, 53.595, 76.425, 0.2], ["INA_ALERT", 1, 53.595, 76.425, 53.6, 76.425, 0.2], ["INA_ALERT", 1, 53.6, 76.425, 53.6, 74.9, 0.2], ["INA_ALERT", 1, 53.6, 74.9, 51.25, 72.55, 0.2], ["INA_ALERT", 1, 45.969, 49.69, 45.969, 48.58, 0.2], ["INA_ALERT", 1, 125.499, 49.69, 125.5, 49.075, 0.2], ["INA_ALERT", 1, 125.5, 49.075, 125.5, 50.625, 0.2], ["INA_ALERT", 1, 125.5, 50.625, 127.825, 52.95, 0.2], ["INA_ALERT", 1, 6.5, 96.889, 6.5, 95.779, 0.2], ["INA_ALERT", 1, 78.775, 46.608, 78.775, 47.734, 0.2], ["INA_ALERT", 1, 78.7, 47.8, 78.7, 48.4, 0.2], ["INA_ALERT", 1, 78.7, 48.4, 79, 48.7, 0.2], ["INA_ALERT", 1, 79, 48.7, 80.5, 48.7, 0.2], ["INA_ALERT", 1, 80.5, 48.7, 82.1, 47.1, 0.2], ["INA_ALERT", 1, 82.1, 47.1, 82.1, 46.6, 0.2], ["INA_ALERT", 1, 82.1, 46.6, 81.723, 45.772, 0.2], ["INA_ALERT", 1, 81.723, 45.772, 81.011, 45.154, 0.2], ["INA_ALERT", 1, 82.1, 47.2, 86.4, 51.5, 0.2], ["INA_ALERT", 1, 86.4, 51.5, 114.1, 51.5, 0.2], ["INA_ALERT", 2, 114.1, 51.5, 120.3, 57.7, 0.2], ["INA_ALERT", 1, 120.3, 57.7, 122, 59.4, 0.2], ["INA_ALERT", 1, 122, 59.4, 130.7, 59.4, 0.2], ["INA_ALERT", 1, 130.7, 59.4, 131.8, 58.3, 0.2], ["INA_ALERT", 1, 131.8, 58.3, 131.8, 56.2, 0.2], ["INA_ALERT", 1, 131.8, 56.2, 128.8, 53.2, 0.2], ["INA_ALERT", 1, 128.8, 53.2, 128.153, 53.2, 0.2], ["INA_ALERT", 1, 128.153, 53.2, 127.913, 53.075, 0.2], ["INA_ALERT", 1, 127.913, 53.075, 127.825, 52.95, 0.2], ["IOEXP_INT#", 1, 72.136, 47.179, 72.136, 47.762, 0.2], ["IOEXP_INT#", 1, 72.136, 47.762, 72.9, 47, 0.2], ["IOEXP_INT#", 1, 72.9, 47, 72.925, 46.608, 0.2], ["K4_PWR", 1, 67.536, 31.501, 66.953, 31.501, 0.2], ["K4_PWR", 1, 88.394, 35.275, 88.394, 33.99, 0.2], ["K4_VDN", 1, 67.536, 38.001, 66.953, 38.001, 0.2], ["K4_VDN", 1, 90.934, 35.275, 90.934, 33.99, 0.2], ["K4_VDN", 1, 66.953, 38.001, 68.95, 36, 0.2], ["K4_VDN", 1, 68.95, 36, 76.65, 36, 0.2], ["K4_VDN", 1, 76.65, 36, 77.75, 34.9, 0.2], ["K4_VDN", 1, 77.75, 34.9, 79.4, 34.9, 0.2], ["K4_VDN", 1, 79.4, 34.9, 79.9, 34.4, 0.2], ["K4_VDN", 2, 79.9, 34.4, 80.55, 33.75, 0.2], ["K4_VDN", 2, 80.55, 33.75, 81.25, 33.75, 0.2], ["K4_VDN", 2, 81.25, 33.75, 82.85, 35.35, 0.2], ["K4_VDN", 2, 82.85, 35.35, 86.3, 35.35, 0.2], ["K4_VDN", 1, 86.3, 35.35, 88.1, 33.55, 0.2], ["K4_VDN", 1, 88.1, 33.55, 90.5, 33.55, 0.2], ["K4_VDN", 1, 90.5, 33.55, 90.934, 33.99, 0.2], ["K4_VUP", 1, 67.536, 35.001, 66.953, 35.001, 0.2], ["K4_VUP", 1, 89.664, 35.275, 89.664, 33.99, 0.2], ["KEY_OE#", 1, 91.614, 55.105, 91.013, 55.105, 0.2], ["KEY_OE#", 1, 92.204, 40.746, 92.204, 42.032, 0.2], ["KEY_OE#", 1, 91.366, 73.736, 91.366, 75.022, 0.2], ["KEY_OE#", 1, 92.909, 56.68, 92.755, 56.69, 0.2], ["KEY_OE#", 1, 92.755, 56.69, 92.729, 56.68, 0.2], ["KEY_OE#", 1, 92.729, 56.68, 92.491, 56.59, 0.2], ["KEY_OE#", 1, 92.326, 56.68, 92.729, 56.68, 0.2], ["KEY_OE#", 1, 92.729, 56.68, 92.909, 56.68, 0.2], ["KEY_OE#", 1, 92.491, 56.59, 91.013, 55.105, 0.2], ["KEY_OE#", 1, 91.9, 54.2, 91.9, 52.2, 0.2], ["KEY_OE#", 2, 91.9, 52.2, 92.2, 51.9, 0.2], ["KEY_OE#", 2, 92.2, 51.9, 92.204, 42.032, 0.2], ["KEY_OE#", 1, 92, 39.8, 90.3, 38.1, 0.2], ["KEY_OE#", 1, 90.3, 38.1, 90, 38.1, 0.2], ["KEY_OE#", 2, 90, 38.1, 85.2, 33.3, 0.2], ["KEY_OE#", 2, 85.2, 33.3, 85.2, 30, 0.2], ["KEY_OE#", 1, 85.2, 30, 84.8, 29.6, 0.2], ["KEY_OE#", 1, 84.8, 29.6, 84.826, 27.094, 0.2], ["NTC1", 1, 77.872, 9.847, 77.865, 10.095, 0.2], ["NTC1", 1, 77.872, 10.398, 77.872, 9.847, 0.2], ["NTC1", 1, 77.872, 9.847, 77.872, 9.524, 0.2], ["NTC1", 1, 78.1, 10.6, 79.251, 10.574, 0.2], ["NTC1", 1, 80, 11, 80.3, 11.15, 0.2], ["NTC1", 1, 80.3, 11.15, 80.6, 11.635, 0.2], ["NTC1", 1, 80.6, 11.635, 80.6, 13.8, 0.2], ["NTC1", 2, 80.6, 13.8, 79.7, 14.7, 0.2], ["NTC1", 2, 79.7, 14.7, 77.4, 14.7, 0.2], ["NTC1", 2, 77.4, 14.7, 63.8, 28.3, 0.2], ["NTC1", 1, 63.8, 28.3, 63.4, 28.7, 0.2], ["NTC1", 1, 63.4, 28.7, 60.6, 28.7, 0.2], ["NTC1", 2, 60.6, 28.7, 67.1, 35.2, 0.2], ["NTC1", 2, 67.1, 35.2, 70.8, 35.248, 0.2], ["NTC2", 1, 77.865, 12.225, 77.865, 11.855, 0.2], ["NTC2", 1, 76.985, 12.677, 76.985, 13.26, 0.2], ["NTC2", 1, 77.865, 11.855, 79.251, 11.844, 0.2], ["NTC2", 1, 77.6, 12.45, 77.4, 12.45, 0.2], ["NTC2", 1, 77.4, 12.45, 77, 12.85, 0.2], ["NTC2", 1, 77, 12.85, 76.985, 13.26, 0.2], ["NTC2", 1, 76.9, 13.3, 74.3, 15.9, 0.2], ["NTC2", 1, 74.3, 15.9, 74.3, 21.7, 0.2], ["NTC2", 2, 74.3, 21.7, 70.8, 25.248, 0.2], ["POGO1_VDN", 1, 31.3, 31.501, 31.5, 31.3, 0.2], ["POGO1_VDN", 1, 31.5, 31.3, 31.5, 30, 0.2], ["POGO1_VDN", 2, 31.5, 30, 27.6, 26.1, 0.2], ["POGO1_VDN", 2, 27.6, 26.1, 26.6, 26.1, 0.2], ["POGO1_VDN", 1, 26.6, 26.1, 23.2, 22.7, 0.2], ["POGO1_VDN", 1, 23.2, 22.7, 19.1, 22.7, 0.2], ["POGO1_VDN", 2, 19.1, 22.7, 18.9, 22.9, 0.2], ["POGO1_VDN", 2, 18.9, 22.9, 13.1, 22.9, 0.2], ["POGO1_VDN", 2, 13.1, 22.9, 12.4, 23.6, 0.2], ["POGO1_VDN", 2, 12.4, 23.6, 12.4, 29.7, 0.2], ["POGO1_VDN", 2, 12.4, 29.7, 10.7, 31.4, 0.2], ["POGO1_VDN", 1, 10.7, 31.4, 2.2, 39.9, 0.2], ["POGO1_VDN", 1, 2.2, 39.9, 2.2, 67.7, 0.2], ["POGO1_VDN", 1, 2.2, 67.7, 4.9, 70.4, 0.2], ["POGO1_VDN", 1, 4.9, 70.4, 8.9, 70.4, 0.2], ["POGO1_VDN", 1, 8.9, 70.4, 9.744, 70.037, 0.2], ["POGO1_VDN", 1, 9.744, 70.037, 11.2, 68.5, 0.2], ["POGO1_VDN", 2, 11.2, 68.5, 11.9, 67.8, 0.2], ["POGO1_VDN", 2, 11.9, 67.8, 21.6, 67.8, 0.2], ["POGO1_VDN", 1, 21.6, 67.8, 25.649, 63.769, 0.2], ["POGO1_VUP", 1, 35.301, 27.501, 34.9, 27.5, 0.2], ["POGO1_VUP", 2, 34.9, 27.5, 32.8, 25.4, 0.2], ["POGO1_VUP", 2, 32.8, 25.4, 24.7, 25.4, 0.2], ["POGO1_VUP", 1, 24.7, 25.4, 22.7, 23.4, 0.2], ["POGO1_VUP", 1, 22.7, 23.4, 19.8, 23.4, 0.2], ["POGO1_VUP", 2, 19.8, 23.4, 13.5, 23.4, 0.2], ["POGO1_VUP", 2, 13.5, 23.4, 12.9, 24, 0.2], ["POGO1_VUP", 2, 12.9, 24, 12.9, 30.4, 0.2], ["POGO1_VUP", 2, 12.9, 30.4, 11, 32.3, 0.2], ["POGO1_VUP", 1, 11, 32.3, 4.9, 38.4, 0.2], ["POGO1_VUP", 1, 4.9, 38.4, 4.9, 66.8, 0.2], ["POGO1_VUP", 1, 4.9, 66.8, 8, 69.9, 0.2], ["POGO1_VUP", 1, 8, 69.9, 9, 69.9, 0.2], ["POGO1_VUP", 1, 9, 69.9, 9.2, 69.7, 0.2], ["POGO1_VUP", 1, 9.2, 69.7, 9.3, 67.8, 0.2], ["POGO1_VUP", 2, 9.3, 67.8, 10.7, 66.4, 0.2], ["POGO1_VUP", 2, 10.7, 66.4, 20.5, 66.4, 0.2], ["POGO1_VUP", 2, 20.5, 66.4, 20.7, 66.2, 0.2], ["POGO1_VUP", 1, 20.7, 66.2, 23.109, 63.769, 0.2], ["POGO2_PWR", 1, 36.589, 98.001, 40.7, 102.1, 0.2], ["POGO2_PWR", 1, 40.7, 102.1, 48.7, 102.1, 0.2], ["POGO2_PWR", 1, 48.7, 102.1, 51.1, 104.5, 0.2], ["POGO2_PWR", 1, 51.1, 104.5, 51.1, 106.9, 0.2], ["POGO2_PWR", 1, 51.1, 106.9, 51.9, 107.7, 0.2], ["POGO2_PWR", 1, 51.9, 107.7, 90, 107.7, 0.2], ["POGO2_PWR", 1, 90, 107.7, 102.3, 95.4, 0.2], ["POGO2_PWR", 2, 102.3, 95.4, 114.5, 83.2, 0.2], ["POGO2_PWR", 1, 114.5, 83.2, 115.7, 82, 0.2], ["POGO2_PWR", 1, 115.7, 82, 115.7, 80.8, 0.2], ["POGO2_PWR", 2, 115.7, 80.8, 115.7, 70.9, 0.2], ["POGO2_PWR", 1, 115.7, 70.9, 113.6, 68.8, 0.2], ["POGO2_PWR", 1, 113.6, 68.8, 113.6, 68.4, 0.2], ["POGO2_PWR", 1, 113.6, 68.4, 111.6, 66.4, 0.2], ["POGO2_PWR", 2, 111.6, 66.4, 108.951, 63.769, 0.2], ["POGO2_VDN", 1, 36.589, 94, 44.6, 94, 0.2], ["POGO2_VDN", 2, 44.6, 94, 45.3, 93.3, 0.2], ["POGO2_VDN", 2, 45.3, 93.3, 59.6, 93.3, 0.2], ["POGO2_VDN", 1, 59.6, 93.3, 60.8, 92.1, 0.2], ["POGO2_VDN", 1, 60.8, 92.1, 101.9, 92.1, 0.2], ["POGO2_VDN", 1, 101.9, 92.1, 102.3, 91.7, 0.2], ["POGO2_VDN", 2, 102.3, 91.7, 103.7, 90.3, 0.2], ["POGO2_VDN", 1, 103.7, 90.3, 106.2, 90.3, 0.2], ["POGO2_VDN", 1, 106.2, 90.3, 115, 81.5, 0.2], ["POGO2_VDN", 2, 115, 81.5, 115, 69, 0.2], ["POGO2_VDN", 1, 115, 69, 115, 66.4, 0.2], ["POGO2_VDN", 2, 115, 66.4, 115, 64.8, 0.2], ["POGO2_VDN", 2, 115, 64.8, 114.031, 63.769, 0.2], ["POGO2_VUP", 1, 32.588, 98.001, 32.8, 98, 0.2], ["POGO2_VUP", 2, 32.8, 98, 36, 94.8, 0.2], ["POGO2_VUP", 2, 36, 94.8, 59.2, 94.8, 0.2], ["POGO2_VUP", 1, 59.2, 94.8, 61.2, 92.8, 0.2], ["POGO2_VUP", 1, 61.2, 92.8, 102.3, 92.8, 0.2], ["POGO2_VUP", 2, 102.3, 92.8, 113.2, 81.9, 0.2], ["POGO2_VUP", 1, 113.2, 81.9, 114.3, 80.8, 0.2], ["POGO2_VUP", 2, 114.3, 80.8, 114.3, 68.3, 0.2], ["POGO2_VUP", 1, 114.3, 68.3, 114.1, 68.1, 0.2], ["POGO2_VUP", 1, 114.1, 68.1, 114.1, 66.4, 0.2], ["POGO2_VUP", 2, 114.1, 66.4, 111.491, 63.769, 0.2], ["POGO3_VUP", 1, 120.97, 98.001, 120.95, 94.8, 0.2], ["POGO3_VUP", 2, 120.95, 94.8, 119.2, 93.05, 0.2], ["POGO3_VUP", 2, 119.2, 93.05, 119.2, 89.65, 0.2], ["POGO3_VUP", 1, 119.2, 89.65, 118.05, 88.5, 0.2], ["POGO3_VUP", 1, 118.05, 88.5, 118.05, 81.5, 0.2], ["POGO3_VUP", 1, 118.05, 81.5, 117.85, 81.3, 0.2], ["POGO3_VUP", 2, 117.85, 81.3, 117.85, 69.9, 0.2], ["POGO3_VUP", 1, 117.85, 69.9, 119.15, 68.6, 0.2], ["POGO3_VUP", 1, 119.15, 68.6, 119.2, 66.95, 0.2], ["POGO3_VUP", 2, 119.2, 66.95, 120.35, 65.8, 0.2], ["POGO3_VUP", 2, 120.35, 65.8, 120.35, 59.85, 0.2], ["POGO3_VUP", 1, 120.35, 59.85, 122.6, 59.85, 0.2], ["POGO3_VUP", 1, 122.6, 59.85, 122.9, 60.15, 0.2], ["POGO3_VUP", 1, 122.9, 60.15, 122.9, 62.25, 0.2], ["POGO3_VUP", 1, 122.9, 62.25, 123.15, 62.5, 0.2], ["POGO3_VUP", 1, 123.15, 62.5, 133.1, 62.5, 0.2], ["POGO3_VUP", 1, 133.1, 62.5, 134.351, 63.769, 0.2], ["SCL", 1, 98.15, 18.628, 98.15, 19.211, 0.2], ["SCL", 1, 109.819, 33.21, 109.819, 32.51, 0.2], ["SCL", 1, 98.15, 19.211, 97.593, 18.461, 0.2], ["SCL", 1, 97.593, 18.461, 97.076, 18.197, 0.2], ["SCL", 1, 97.076, 18.197, 96.751, 18.194, 0.2], ["SCL", 1, 109.4, 33.2, 109.319, 33.21, 0.2], ["SCL", 2, 109.9, 33, 110.9, 33, 0.15], ["SCL", 2, 110.9, 33, 114.7, 36.8, 0.15], ["SCL", 2, 114.7, 36.8, 114.7, 37.2, 0.15], ["SCL", 1, 126.8, 49.3, 126.5, 48.58, 0.15], ["SCL", 1, 104, 25.2, 95.9, 33.3, 0.2], ["SCL", 2, 95.9, 33.3, 77.2, 52, 0.2], ["SCL", 2, 48.1, 50.05, 47.9, 49.85, 0.2], ["SCL", 1, 47.9, 49.85, 47.063, 49.013, 0.2], ["SCL", 1, 46.96, 48.74, 46.97, 48.58, 0.2], ["SCL", 1, 34.95, 62.9, 34.55, 62.5, 0.2], ["SCL", 1, 34.55, 62.5, 32.15, 62.5, 0.2], ["SCL", 1, 32.15, 62.5, 32, 62.35, 0.2], ["SCL", 1, 15.3, 50.6, 15.3, 49.69, 0.2], ["SCL", 1, 15.3, 49.69, 15.301, 48.58, 0.2], ["SCL", 2, 9.4, 95.2, 7.4, 95.2, 0.2], ["SCL", 1, 7.4, 95.2, 7.501, 95.779, 0.2], ["SCL", 1, 52.588, 75.809, 52.588, 76.919, 0.2], ["SCL", 1, 140.97, 75.809, 140.97, 76.919, 0.2], ["SCL", 1, 46.97, 49.69, 46.97, 48.766, 0.2], ["SCL", 1, 46.97, 48.766, 46.97, 48.58, 0.2], ["SCL", 1, 47.063, 49.013, 46.97, 48.766, 0.2], ["SCL", 1, 46.97, 48.766, 46.96, 48.74, 0.2], ["SCL", 1, 126.5, 49.69, 126.5, 48.58, 0.2], ["SCL", 1, 7.501, 96.889, 7.501, 95.779, 0.2], ["SDA", 1, 86.771, 28.474, 87.354, 28.474, 0.2], ["SDA", 1, 110.3, 32.5, 110.3, 32.1, 0.2], ["SDA", 1, 109.3, 31.1, 108.9, 31.1, 0.2], ["SDA", 2, 108.9, 31.1, 108.5, 30.7, 0.2], ["SDA", 2, 108.5, 30.7, 89.6, 30.7, 0.2], ["SDA", 2, 89.6, 30.7, 87.354, 28.474, 0.2], ["SDA", 2, 87.2, 28.3, 86.096, 27.094, 0.2], ["SDA", 1, 80.25, 35.8, 79.831, 35.811, 0.15], ["SDA", 1, 80.4, 36.5, 80.6, 36.5, 0.2], ["SDA", 2, 80.6, 36.5, 80.9, 36.8, 0.2], ["SDA", 2, 80.9, 39.2, 80.1, 40, 0.2], ["SDA", 2, 80.1, 40, 80.1, 42.5, 0.2], ["SDA", 2, 80.1, 42.5, 78.8, 43.8, 0.2], ["SDA", 2, 78.8, 43.8, 78.8, 46.2, 0.2], ["SDA", 1, 49.3, 51.3, 49.3, 52.164, 0.2], ["SDA", 1, 49.3, 52.164, 49.05, 52.725, 0.2], ["SDA", 1, 49.05, 52.725, 48.8, 52.95, 0.2], ["SDA", 2, 52.6, 78.1, 51.8, 78.9, 0.2], ["SDA", 2, 9.4, 95.65, 6.8, 98.25, 0.2], ["SDA", 1, 6.8, 98.25, 7, 98.05, 0.2], ["SDA", 1, 7, 98.05, 7, 96.89, 0.2], ["SDA", 1, 79.831, 36.511, 79.831, 35.811, 0.2], ["SDA", 1, 110.32, 33.21, 110.32, 32.51, 0.2], ["SDA", 1, 14.801, 49.69, 14.801, 48.58, 0.2], ["SDA", 1, 53.088, 75.809, 53.088, 76.919, 0.2], ["SDA", 1, 141.468, 75.809, 141.472, 76.425, 0.2], ["SDA", 1, 141.472, 76.425, 141.475, 76.425, 0.2], ["SDA", 1, 141.475, 76.425, 141.475, 74.925, 0.15], ["SDA", 1, 46.469, 49.69, 46.472, 49.075, 0.2], ["SDA", 1, 46.472, 49.075, 46.475, 49.075, 0.2], ["SDA", 1, 46.475, 49.075, 46.475, 50.625, 0.2], ["SDA", 1, 46.475, 50.625, 48.8, 52.95, 0.2], ["SDA", 1, 125.001, 49.69, 125.001, 48.58, 0.2], ["SDA", 1, 125.999, 49.69, 125.999, 48.58, 0.2], ["SR_CAS", 1, 90.934, 40.746, 90.934, 42.032, 0.2], ["SR_CAS", 1, 96.3, 55.1, 96.694, 55.105, 0.2], ["SR_CAS", 2, 96.3, 55.1, 92.85, 55.1, 0.2], ["SR_CAS", 2, 92.85, 55.1, 89.3, 51.55, 0.2], ["SR_CAS", 2, 89.3, 51.55, 89.3, 42.85, 0.2], ["SR_CAS", 1, 89.3, 42.85, 89.725, 42.85, 0.2], ["SR_CAS", 1, 89.725, 42.85, 90.444, 42.543, 0.2], ["SR_CAS", 1, 90.444, 42.543, 90.934, 42.032, 0.2], ["SR_CAS2", 1, 97.284, 40.746, 97.885, 40.746, 0.2], ["SR_CAS2", 1, 90.096, 73.736, 90.096, 75.022, 0.2], ["SW3V3", 1, 23.081, 108.501, 22.531, 108.501, 0.5], ["SW3V3", 1, 20.351, 104, 21.2, 104, 0.599], ["SW3V3", 1, 22.531, 108.501, 22.953, 108.94, 0.35], ["SW3V3", 1, 22.953, 108.94, 23.8, 109.3, 0.35], ["SW3V3", 1, 23.8, 109.3, 24.7, 109.3, 0.35], ["SW3V3", 1, 24.7, 109.3, 25.1, 108.9, 0.35], ["SW3V3", 1, 25.1, 108.9, 25.1, 107.3, 0.35], ["SW3V3", 1, 25.1, 107.3, 21.9, 104.1, 0.35], ["SW3V3", 1, 21.9, 104.1, 21.2, 104, 0.35], ["SW3V3", 1, 23, 105, 23.901, 104, 0.5], ["VBUS_EN3", 1, 89.906, 27.094, 89.9, 24.3, 0.2], ["VBUS_EN3", 1, 89.9, 24.3, 91.3, 22.9, 0.2], ["VBUS_EN3", 2, 91.3, 22.9, 95.1, 19.1, 0.2], ["VBUS_EN3", 2, 95.1, 19.1, 100.5, 19.1, 0.2], ["VBUS_EN3", 1, 100.5, 19.1, 101.8, 17.8, 0.2], ["VBUS_EN3", 1, 101.8, 17.8, 127.2, 17.8, 0.2], ["VBUS_EN3", 1, 127.2, 17.8, 127.8, 18.4, 0.2], ["VBUS_EN3", 1, 127.8, 18.4, 127.8, 21.5, 0.2], ["VBUS_EN3", 1, 127.8, 21.5, 131.9, 25.6, 0.2], ["VBUS_EN3", 1, 131.9, 25.6, 133.3, 25.6, 0.2], ["VBUS_EN3", 1, 133.3, 25.6, 134.2, 26.5, 0.2], ["VBUS_EN3", 1, 134.2, 26.5, 134.2, 27.6, 0.2], ["VBUS_EN3", 1, 134.2, 27.6, 142.3, 35.7, 0.2], ["VBUS_EN3", 1, 142.3, 35.7, 143.7, 35.7, 0.2], ["VBUS_EN3", 1, 143.7, 35.7, 145.6, 37.6, 0.2], ["VBUS_EN3", 1, 145.6, 37.6, 145.6, 38.2, 0.2], ["VBUS_EN3", 1, 145.6, 38.2, 146.7, 39.3, 0.2], ["VBUS_EN3", 2, 146.7, 39.3, 146.7, 46.4, 0.2], ["VBUS_EN3", 2, 146.7, 46.4, 155.1, 54.8, 0.2], ["VBUS_EN3", 2, 155.1, 54.8, 155.1, 71.8, 0.2], ["VBUS_EN3", 2, 155.1, 71.8, 154.739, 72.646, 0.2], ["VBUS_EN3", 2, 154.739, 72.646, 152.8, 74.5, 0.2], ["VBUS_EN3", 1, 152.8, 74.5, 151.8, 73.5, 0.2], ["VBUS_EN3", 1, 151.8, 73.5, 151.8, 66, 0.2], ["VBUS_EN3", 2, 151.8, 66, 149.591, 63.769, 0.2], ["VDAC5", 1, 126.434, 20.701, 126.434, 21.271, 0.2], ["VDAC5", 1, 111.069, 34.46, 111.069, 34.02, 0.2], ["VO1", 1, 10.866, 18.501, 10.283, 18.501, 0.541], ["VO1", 1, 18.867, 47.5, 18.284, 47.5, 0.541], ["VO1", 1, 17.15, 31.8, 18.25, 31.8, 0.3], ["VO1", 1, 18.25, 31.8, 20.1, 29.95, 0.3], ["VO1", 2, 20.1, 29.95, 23.2, 26.85, 0.3], ["VO1", 1, 23.2, 26.85, 22.75, 26.4, 0.3], ["VO1", 1, 22.75, 26.4, 21.6, 26.4, 0.3], ["VO1", 1, 21.6, 26.4, 16.75, 21.55, 0.3], ["VO1", 1, 16.75, 21.55, 16.75, 18.65, 0.3], ["VO1", 1, 16.75, 18.65, 15.9, 17.8, 0.3], ["VO1", 1, 15.9, 17.8, 11, 17.8, 0.3], ["VO1", 1, 11, 17.8, 10.283, 18.501, 0.3], ["VO2", 1, 57.023, 107, 57.606, 107, 0.541], ["VO2", 1, 49.022, 78.001, 49.605, 78.001, 0.541], ["VO2", 1, 52.65, 92.65, 53.4, 92.65, 0.3], ["VO2", 2, 53.4, 92.65, 56.15, 92.65, 0.3], ["VO2", 1, 56.15, 92.65, 56.65, 93.15, 0.3], ["VO2", 1, 56.65, 93.15, 56.65, 93.5, 0.3], ["VO2", 1, 56.65, 93.5, 58.75, 95.6, 0.3], ["VO2", 1, 58.75, 95.6, 58.75, 105.85, 0.3], ["VO2", 1, 58.75, 105.85, 57.606, 107, 0.3], ["VO3", 1, 145.402, 107, 145.985, 107, 0.541], ["VO3", 1, 137.401, 78.001, 137.984, 78.001, 0.541], ["VO3", 2, 141, 93.45, 141.951, 94.525, 0.3], ["VO3", 2, 141.951, 94.525, 142.45, 94.75, 0.3], ["VO3", 2, 142.45, 94.75, 142.95, 94.75, 0.3], ["VO3", 2, 142.95, 94.75, 144.35, 96.15, 0.3], ["VO3", 2, 144.35, 96.15, 144.35, 105.35, 0.3], ["VO3", 2, 144.35, 105.35, 145.985, 107, 0.3], ["VO4", 1, 42.537, 18.501, 41.954, 18.501, 0.541], ["VO4", 1, 50.536, 47.5, 49.953, 47.5, 0.541], ["VO5", 1, 122.067, 18.501, 121.484, 18.501, 0.541], ["VO5", 1, 130.068, 47.5, 129.485, 47.5, 0.541], ["VO5", 2, 125, 44.4, 126.3, 44.4, 0.3], ["VO5", 2, 126.3, 44.4, 126.65, 44.75, 0.3], ["VO5", 2, 126.65, 44.75, 126.981, 45.595, 0.3], ["VO5", 2, 126.981, 45.595, 126.911, 47.417, 0.3], ["VO5", 2, 126.911, 47.417, 127.1, 47.9, 0.3], ["VO5", 2, 127.1, 47.9, 127.3, 48.1, 0.3], ["VO5", 2, 127.3, 48.1, 128.9, 48.1, 0.3], ["VO5", 2, 128.9, 48.1, 129.485, 47.5, 0.3], ["VO5", 1, 126.4, 32.85, 125.7, 32.85, 0.3], ["VO5", 2, 125.7, 32.85, 122.9, 32.85, 0.3], ["VO5", 1, 122.9, 32.85, 120.6, 30.55, 0.3], ["VO5", 1, 120.6, 30.55, 120.6, 19.4, 0.3], ["VO5", 1, 120.6, 19.4, 121.484, 18.501, 0.3], ["$10N719", 1, 125, 84.5, 128.6, 84.5, 0.2], ["$10N719", 2, 128.6, 84.5, 128.9, 84.2, 0.2], ["$10N719", 2, 128.9, 84.2, 142.9, 84.2, 0.2], ["$10N719", 2, 142.9, 84.2, 144.1, 83, 0.2], ["$10N719", 1, 144.1, 83, 144.1, 87.4, 0.2], ["$10N719", 2, 144.1, 87.4, 140.2, 91.3, 0.2], ["$10N719", 2, 140.2, 91.3, 129.9, 91.3, 0.2], ["$10N719", 2, 129.9, 91.3, 127.8, 93.4, 0.2], ["$10N719", 1, 127.8, 93.4, 126, 95.2, 0.2], ["$10N719", 1, 126, 95.2, 123.37, 95.2, 0.2], ["$10N719", 1, 123.37, 95.2, 123.085, 95.075, 0.2], ["$10N719", 1, 123.085, 95.075, 122.969, 94.95, 0.2], ["$12N834", 1, 46.9, 18.3, 46.9, 18.2, 0.2], ["$12N834", 2, 46.9, 18.2, 45.3, 19.8, 0.2], ["$12N834", 1, 45.3, 19.8, 45.8, 20.5, 0.2], ["$12N836", 1, 49.22, 25.776, 49.22, 25.076, 0.2], ["$12N836", 1, 48.9, 18.45, 48.1, 17.65, 0.15], ["$12N836", 1, 48.1, 17.65, 47.6, 17.65, 0.15], ["$12N836", 2, 47.6, 17.65, 46.898, 17.58, 0.15], ["$12N836", 2, 46.898, 17.58, 46.395, 17.769, 0.15], ["$12N836", 2, 46.395, 17.769, 44.45, 19.85, 0.15], ["$12N836", 1, 44.45, 19.85, 44.95, 20.4, 0.15], ["$12N836", 1, 44.95, 20.4, 44.95, 20.625, 0.15], ["$12N836", 1, 44.95, 20.625, 45.116, 21.002, 0.15], ["$12N836", 1, 45.116, 21.002, 45.879, 21.698, 0.15], ["$12N836", 1, 45.879, 21.698, 46.1, 22.2, 0.15], ["$12N836", 1, 46.1, 22.2, 46.1, 23.1, 0.15], ["$12N836", 1, 46.1, 23.1, 47.05, 24.05, 0.15], ["$12N836", 2, 47.05, 24.05, 47.35, 24.35, 0.15], ["$12N836", 2, 47.35, 24.35, 48.45, 24.35, 0.15], ["$12N836", 1, 48.45, 24.35, 49.22, 25.076, 0.15], ["$14N653", 1, 137.517, 18.501, 137.425, 19.289, 0.15], ["$14N653", 1, 137.425, 19.289, 137.55, 19.65, 0.15], ["$14N653", 1, 137.55, 19.65, 137.7, 19.8, 0.15], ["$14N653", 2, 137.7, 19.8, 138.2, 20.3, 0.15], ["$14N653", 2, 138.2, 20.3, 138.2, 22.7, 0.15], ["$14N653", 2, 138.2, 22.7, 131.154, 29.746, 0.15], ["$14N653", 2, 131.154, 29.746, 130.3, 30.087, 0.15], ["$14N653", 2, 130.3, 30.087, 127.1, 30, 0.15], ["$14N653", 1, 127.1, 30, 127.252, 29.925, 0.15], ["$14N657", 1, 128.75, 25.776, 128.75, 25.076, 0.2], ["$14N657", 1, 132.1, 20.8, 131.7, 21, 0.2], ["$14N657", 2, 131.7, 21, 131.3, 21.4, 0.2], ["$14N657", 2, 131.3, 21.4, 127.6, 21.4, 0.2], ["$14N657", 2, 127.6, 21.4, 126.5, 22.5, 0.2], ["$14N657", 1, 126.5, 22.5, 126.5, 23.9, 0.2], ["$14N657", 2, 126.5, 23.9, 127.3, 24.7, 0.2], ["$14N657", 2, 127.3, 24.7, 128.5, 24.7, 0.2], ["$14N657", 1, 128.5, 24.7, 128.75, 25.076, 0.2], ["$14N689", 1, 143.5, 29.1, 136.8, 29.1, 0.2], ["$14N689", 2, 136.8, 29.1, 135.9, 30, 0.2], ["$14N689", 2, 135.9, 30, 135.5, 30, 0.2], ["$14N689", 1, 135.5, 30, 140.5, 35, 0.2], ["$14N689", 2, 140.5, 35, 142.7, 35, 0.2], ["$14N689", 1, 142.7, 35, 143.068, 35.001, 0.2], ["$14N699", 1, 123.1, 46.1, 122.65, 46.1, 0.3], ["$14N699", 1, 122.65, 46.1, 122.15, 45.6, 0.3], ["$14N699", 2, 122.15, 45.6, 121.2, 44.65, 0.3], ["$14N699", 1, 121.2, 44.65, 121.2, 44.15, 0.3], ["$14N699", 1, 121.2, 44.15, 123.4, 41.95, 0.3], ["$14N699", 2, 123.4, 41.95, 131.05, 41.9, 0.3], ["$14N699", 1, 131.05, 41.9, 131.5, 42.35, 0.3], ["$14N699", 1, 131.5, 42.35, 133.9, 42.35, 0.3], ["$14N699", 1, 133.9, 42.35, 134, 42.25, 0.3], ["$14N699", 1, 134, 42.25, 135.1, 42.25, 0.3], ["$14N699", 1, 135.1, 42.25, 136.25, 43.4, 0.3], ["$16N9", 1, 61.5, 73.1, 61.5, 73, 0.2], ["$17N151", 1, 105, 68, 103.5, 66.5, 0.2], ["$17N151", 1, 103.5, 66.5, 103.5, 66, 0.2], ["$17N151", 2, 103.5, 66, 102.5, 65, 0.2], ["$17N151", 2, 102.5, 65, 102.5, 60.2, 0.2], ["$17N151", 2, 102.5, 60.2, 102.8, 59.9, 0.2], ["$17N151", 2, 102.8, 59.9, 106.9, 59.9, 0.2], ["$17N151", 2, 106.9, 59.9, 113.6, 53.2, 0.2], ["$17N151", 1, 113.6, 53.2, 122.7, 44.1, 0.2], ["$17N151", 2, 122.7, 44.1, 123.2, 43.6, 0.2], ["$17N151", 2, 123.2, 43.6, 130.3, 43.6, 0.2], ["$17N151", 2, 130.3, 43.6, 133, 40.9, 0.2], ["$17N151", 2, 133, 40.9, 133.4, 40.9, 0.2], ["$17N151", 2, 133.4, 40.9, 135.5, 38.8, 0.2], ["$17N151", 2, 135.5, 38.8, 135.5, 37.6, 0.2], ["$17N151", 2, 135.5, 37.6, 141.7, 31.4, 0.2], ["$17N151", 2, 141.7, 31.4, 153.5, 31.4, 0.2], ["$17N151", 2, 153.5, 31.4, 154.901, 29.999, 0.2], ["$17N154", 1, 102.2, 77.8, 102.2, 76.1, 0.2], ["$17N154", 2, 102.2, 76.1, 102.8, 75.5, 0.2], ["$17N154", 2, 102.8, 75.5, 102.8, 66.2, 0.2], ["$17N154", 2, 102.8, 66.2, 102, 65.4, 0.2], ["$17N154", 2, 102, 65.4, 102, 61.1, 0.2], ["$17N154", 2, 102, 61.1, 101.8, 60.9, 0.2], ["$17N154", 1, 101.8, 60.9, 102.8, 59.9, 0.2], ["$17N154", 1, 102.8, 59.9, 110.7, 59.9, 0.2], ["$17N154", 1, 110.7, 59.9, 120.3, 50.3, 0.2], ["$17N154", 2, 120.3, 50.3, 122.2, 48.4, 0.2], ["$17N154", 2, 122.2, 48.4, 124.7, 48.4, 0.2], ["$17N154", 2, 124.7, 48.4, 126.3, 50, 0.2], ["$17N154", 2, 126.3, 50, 131.8, 50, 0.2], ["$17N154", 2, 131.8, 50, 136.3, 45.5, 0.2], ["$17N154", 2, 136.3, 45.5, 136.3, 41.2, 0.2], ["$17N154", 2, 136.3, 41.2, 136.6, 40.9, 0.2], ["$17N154", 2, 136.6, 40.9, 137.5, 40.9, 0.2], ["$17N154", 2, 137.5, 40.9, 139.1, 39.3, 0.2], ["$17N154", 1, 139.1, 39.3, 145.5, 39.3, 0.2], ["$17N154", 2, 145.5, 39.3, 148.9, 35.9, 0.2], ["$17N154", 2, 148.9, 35.9, 151.5, 35.9, 0.2], ["$17N154", 2, 151.5, 35.9, 157.441, 29.999, 0.2], ["$1N227", 1, 20.3, 73.6, 20.3, 73.5, 0.574], ["$1N227", 2, 20.3, 73.5, 20.3, 70.5, 0.574], ["$1N227", 1, 20.3, 70.5, 20.345, 68.001, 0.574], ["$8N732", 1, 46.789, 70.5, 46.8, 69.3, 0.2], ["$8N732", 1, 46.8, 69.3, 44.4, 66.9, 0.2], ["$8N732", 1, 44.4, 66.9, 41.788, 66.934, 0.2], ["+12V", 1, 6.2, 100, 6.2, 99.9, 0.3], ["+3V3", 1, 50.5, 71.8, 50.6, 71.8, 0.15], ["+3V3", 1, 51.1, 71.8, 54.025, 74.725, 0.15], ["+3V3", 1, 50.6, 71.8, 51.1, 71.8, 0.195], ["+3V3", 1, 51.1, 71.8, 51.9, 71.8, 0.195], ["+3V3", 1, 54.025, 74.725, 54.025, 76.65, 0.15], ["+3V3", 1, 54.025, 76.65, 54.089, 76.714, 0.15], ["+3V3", 1, 54.089, 76.714, 54.3, 76.925, 0.15], ["+3V3", 1, 54.089, 75.809, 54.089, 76.714, 0.279], ["+3V3", 1, 54.089, 76.714, 54.089, 76.919, 0.279], ["+3V3", 1, 54.3, 76.925, 54.775, 76.925, 0.15], ["+3V3", 1, 54.775, 76.925, 54.925, 76.838, 0.15], ["+3V3", 1, 54.925, 76.838, 55.25, 76.275, 0.15], ["+3V3", 2, 55.25, 76.275, 54.8, 75.825, 0.15], ["+3V3", 2, 54.8, 75.825, 52.425, 75.825, 0.15], ["+3V3", 2, 52.425, 75.825, 51.925, 75.825, 0.15], ["+3V3", 2, 51.8, 75.2, 52.425, 75.825, 0.195], ["+3V3", 2, 52.425, 75.825, 53.5, 76.9, 0.195], ["+3V3", 1, 51.925, 75.825, 50.138, 74.038, 0.15], ["+3V3", 1, 50.138, 74.038, 50.055, 73.825, 0.15], ["+3V3", 1, 50.055, 73.825, 50.06, 73.701, 0.15], ["+3V3", 1, 49.5, 73.9, 49.4, 75.6, 0.279], ["+3V3", 1, 49.4, 75.6, 48.3, 76.7, 0.279], ["+3V3", 1, 48.3, 76.7, 47.9, 76.7, 0.279], ["+3V3", 1, 47.9, 76.7, 47.224, 76.411, 0.279], ["+3V3", 1, 47.224, 76.411, 45.745, 74.862, 0.279], ["+3V3", 1, 45.745, 74.862, 44.9, 74.5, 0.279], ["+3V3", 1, 44.9, 74.5, 44.205, 74.501, 0.279], ["EFUSE_EN3", 2, 153.5, 70.4, 153.5, 59.9, 0.2], ["EFUSE_EN3", 2, 153.5, 59.9, 149.5, 55.9, 0.2], ["EFUSE_EN3", 2, 149.5, 55.9, 149.5, 52.1, 0.2], ["EFUSE_EN3", 1, 149.5, 52.1, 144.3, 46.9, 0.2], ["EFUSE_EN3", 1, 144.3, 46.9, 144.3, 42.4, 0.2], ["EFUSE_EN3", 2, 144.3, 42.4, 140.5, 38.6, 0.2], ["EFUSE_EN3", 1, 140.5, 38.6, 138.9, 37, 0.2], ["EFUSE_EN3", 1, 138.9, 37, 134.9, 37, 0.2], ["EFUSE_EN3", 2, 134.9, 37, 132.2, 34.3, 0.2], ["EFUSE_EN3", 2, 132.2, 34.3, 121.6, 34.3, 0.2], ["EFUSE_EN3", 1, 121.6, 34.3, 120.2, 32.9, 0.2], ["EFUSE_EN3", 1, 120.2, 32.9, 115.5, 32.9, 0.2], ["EFUSE_EN3", 1, 115.5, 32.9, 115, 32.4, 0.2], ["EFUSE_EN3", 2, 115, 32.4, 99.6, 17, 0.2], ["EFUSE_EN3", 2, 99.6, 17, 98.1, 17, 0.2], ["EFUSE_EN3", 2, 98.1, 17, 96.9, 15.8, 0.2], ["EFUSE_EN3", 1, 96.9, 15.8, 96.751, 15.654, 0.2], ["GATE", 1, 28.432, 71.501, 29.015, 71.501, 0.2], ["GATE", 2, 26.1, 68.2, 27, 69.1, 0.2], ["GATE", 2, 27, 69.1, 27.4, 69.1, 0.2], ["GATE", 1, 27.4, 69.1, 29, 70.7, 0.2], ["GATE", 1, 29, 70.7, 29.015, 71.501, 0.2], ["INA_ALERT", 1, 51.2, 72.5, 47.4, 72.5, 0.2], ["INA_ALERT", 1, 47.4, 72.5, 45.6, 70.7, 0.2], ["INA_ALERT", 1, 45.6, 70.7, 43.9, 70.7, 0.2], ["INA_ALERT", 1, 43.9, 70.7, 43, 69.8, 0.2], ["INA_ALERT", 1, 43, 69.8, 34.9, 69.8, 0.2], ["INA_ALERT", 2, 34.9, 69.8, 16.5, 69.8, 0.2], ["INA_ALERT", 2, 16.5, 69.8, 15.1, 71.2, 0.2], ["INA_ALERT", 2, 15.1, 71.2, 11.6, 71.2, 0.2], ["INA_ALERT", 2, 11.6, 71.2, 11.2, 70.8, 0.2], ["INA_ALERT", 1, 11.2, 70.8, 11.2, 78.1, 0.2], ["INA_ALERT", 2, 11.2, 78.1, 11.2, 84.6, 0.2], ["INA_ALERT", 2, 11.2, 84.6, 7.1, 88.7, 0.2], ["INA_ALERT", 2, 7.1, 88.7, 7.1, 94.3, 0.2], ["INA_ALERT", 1, 7.1, 94.3, 6.7, 94.7, 0.2], ["INA_ALERT", 1, 6.7, 94.7, 6.7, 95.5, 0.2], ["INA_ALERT", 1, 6.7, 95.5, 6.5, 95.7, 0.2], ["INA_ALERT", 1, 141.975, 75.809, 141.95, 74.7, 0.2], ["INA_ALERT", 1, 141.95, 74.7, 139.675, 72.525, 0.2], ["POGO1_PWR", 1, 20.575, 63.775, 21.8, 62.55, 0.2], ["POGO1_PWR", 1, 21.8, 62.55, 24.375, 62.525, 0.2], ["POGO3_VDN", 1, 136.9, 63.775, 138.125, 62.55, 0.2], ["POGO3_VDN", 1, 138.125, 62.55, 140.7, 62.525, 0.2], ["POGO5_VDN", 1, 142.499, 31.501, 142.2, 32.1, 0.2], ["POGO5_VDN", 2, 142.2, 32.1, 139.8, 34.5, 0.2], ["POGO5_VDN", 2, 139.8, 34.5, 139.7, 59.2, 0.2], ["POGO5_VDN", 1, 139.7, 59.2, 139.3, 59.6, 0.2], ["POGO5_VDN", 1, 139.3, 59.6, 138.5, 59.6, 0.2], ["POGO5_VDN", 1, 138.5, 59.6, 136.891, 61.229, 0.2], ["SCL", 1, 52.5, 74.7, 52.5, 75, 0.2], ["SCL", 1, 98.15, 19.3, 102.1, 23.3, 0.15], ["SCL", 1, 102.1, 23.3, 102.1, 24.2, 0.15], ["SCL", 2, 102.1, 24.2, 103.3, 25.4, 0.15], ["SCL", 1, 103.3, 25.4, 104.025, 25.175, 0.15], ["SCL", 1, 104.025, 25.175, 107.6, 28.8, 0.15], ["SCL", 1, 107.6, 28.8, 107.6, 31.4, 0.15], ["SCL", 2, 107.6, 31.4, 109.3, 33.1, 0.15], ["SCL", 2, 109.3, 33.1, 109.6, 33.1, 0.15], ["SCL", 1, 109.6, 33.1, 109.819, 32.51, 0.15], ["SCL", 1, 7.1, 95.2, 7.566, 94.77, 0.2], ["SCL", 1, 7.566, 94.77, 7.75, 94.35, 0.2], ["SCL", 1, 7.75, 94.35, 7.75, 94, 0.2], ["SCL", 1, 7.75, 94, 7.4, 93.65, 0.2], ["SCL", 1, 7.4, 93.65, 6.8, 93.65, 0.2], ["SCL", 1, 6.8, 93.65, 6.05, 94.4, 0.2], ["SCL", 1, 6.05, 94.4, 6, 95.779, 0.2], ["SCL", 1, 6, 96.889, 6, 95.779, 0.2], ["SDA", 1, 125.1, 48.575, 125.9, 48.575, 0.2], ["SDA", 1, 110.2, 32, 112.6, 32, 0.2], ["SDA", 1, 110.3, 32.1, 110.2, 32, 0.2], ["SDA", 1, 110.2, 32, 109.3, 31.1, 0.2], ["SDA", 1, 112.6, 32, 115.8, 28.8, 0.2], ["SDA", 1, 140, 75.4, 140, 75, 0.2], ["SDA", 1, 140, 75, 140.779, 74.221, 0.2], ["SDA", 1, 140.779, 74.221, 140.8, 74.2, 0.2], ["SDA", 1, 141.475, 74.925, 140.779, 74.221, 0.15], ["SDA", 1, 140.779, 74.221, 139.125, 72.55, 0.15], ["VBUS_EN2", 1, 119.1, 63.775, 117.875, 62.55, 0.2], ["VBUS_EN2", 1, 117.875, 62.55, 115.3, 62.55, 0.2], ["VDAC5", 1, 111.069, 33.959, 111.769, 33.959, 0.2], ["VDAC5", 2, 126.434, 21.271, 123.6, 21.4, 0.2], ["VDAC5", 2, 123.6, 21.4, 121.3, 23.7, 0.2], ["VDAC5", 2, 121.3, 23.7, 121.3, 24.9, 0.2], ["VDAC5", 2, 121.3, 24.9, 116.7, 29.5, 0.2], ["VDAC5", 1, 116.7, 29.5, 112.353, 33.847, 0.2], ["VDAC5", 1, 112.353, 33.847, 111.985, 33.98, 0.2], ["VDAC5", 1, 111.985, 33.98, 111.769, 33.959, 0.2], ["SCL", 2, 114.7, 37.2, 114.9, 37.2, 0.2], ["SCL", 1, 15.5, 50.9, 15.5, 50.7, 0.2], ["SCL", 1, 15.5, 50.7, 15.4, 50.6, 0.2], ["SDA", 1, 50, 51.1, 49.4, 51.1, 0.2], ["SDA", 1, 49.4, 51.1, 49.3, 51.2, 0.2], ["SDA", 1, 34.1, 65.8, 34.1, 64.6, 0.2], ["SDA", 2, 51.3, 77.3, 51.5, 77.3, 0.2], ["SDA", 2, 51.5, 77.3, 52.4, 78.2, 0.2], ["SDA", 2, 9.7, 95.7, 9.4, 95.7, 0.2], ["SCL", 1, 74.225, 52.654, 74.225, 53.779, 0.2], ["SCL", 2, 77.2, 52, 74.5, 52, 0.2], ["SCL", 2, 74.5, 52, 74, 51.5, 0.2], ["SCL", 2, 74, 51.5, 74, 51.3, 0.2], ["SCL", 2, 74, 51.3, 73.9, 51.2, 0.2], ["SCL", 1, 73.9, 51.2, 73.9, 51.3, 0.2], ["SCL", 1, 73.9, 51.3, 74.2, 51.6, 0.2], ["SCL", 1, 74.2, 51.6, 74.2, 51.9, 0.2], ["SCL", 16, 115.2, 37.2, 121, 43, 0.2], ["SCL", 16, 121, 43, 121, 43.2, 0.2], ["SCL", 2, 121, 43.2, 121.9, 44.1, 0.2], ["SCL", 2, 121.9, 44.1, 121.9, 44.4, 0.2], ["SCL", 2, 121.9, 44.4, 122.4, 44.9, 0.2], ["SCL", 2, 122.4, 44.9, 122.5, 44.9, 0.2], ["SCL", 2, 122.5, 44.9, 126.5, 48.9, 0.2], ["SCL", 2, 126.5, 48.9, 126.5, 49, 0.2], ["SCL", 2, 126.5, 49, 126.6, 49.1, 0.2], ["SCL", 2, 73.6, 51.2, 72.4, 50, 0.2], ["SCL", 2, 72.4, 50, 61.1, 50, 0.2], ["SCL", 16, 61.1, 50, 58.6, 50, 0.2], ["SCL", 16, 58.6, 50, 58.5, 49.9, 0.2], ["SCL", 16, 58.5, 49.9, 58.4, 49.9, 0.2], ["SCL", 2, 58.4, 49.9, 48.2, 49.9, 0.2], ["SCL", 16, 60.2, 50.1, 60.2, 62.2, 0.2], ["SCL", 16, 60.2, 62.2, 57.3, 65.1, 0.2], ["SCL", 16, 37.2, 65.1, 36.7, 64.6, 0.2], ["SCL", 16, 47.9, 65.1, 47.9, 75.8, 0.2], ["SCL", 16, 57.3, 65.1, 47.9, 65.1, 0.2], ["SCL", 16, 47.9, 65.1, 37.2, 65.1, 0.2], ["SCL", 16, 47.9, 75.8, 48, 75.9, 0.2], ["SCL", 1, 48, 75.9, 47.9, 75.8, 0.2], ["SCL", 1, 47.9, 75.8, 47.9, 73.3, 0.2], ["SCL", 1, 47.9, 73.3, 48.2, 73, 0.2], ["SCL", 1, 48.2, 73, 50.7, 73, 0.2], ["SCL", 1, 50.7, 73, 52.4, 74.7, 0.2], ["SCL", 16, 35, 64.6, 34.5, 65.1, 0.2], ["SCL", 16, 6.7, 65.1, 6.5, 64.9, 0.2], ["SCL", 16, 6.5, 64.9, 6.5, 60.3, 0.2], ["SCL", 16, 6.5, 60.3, 7.6, 59.2, 0.2], ["SCL", 16, 7.6, 59.2, 29.1, 59.2, 0.2], ["SCL", 16, 29.1, 59.2, 29.8, 58.5, 0.2], ["SCL", 16, 29.8, 58.5, 29.8, 58.4, 0.2], ["SCL", 1, 29.8, 58.4, 29.8, 58.1, 0.2], ["SCL", 1, 29.8, 58.1, 29.2, 57.5, 0.2], ["SCL", 1, 29.2, 57.5, 22.1, 57.5, 0.2], ["SCL", 1, 22.1, 57.5, 15.7, 51.1, 0.2], ["SCL", 1, 15.7, 51.1, 15.7, 51, 0.2], ["SCL", 1, 15.7, 51, 15.6, 50.9, 0.2], ["SCL", 16, 6.8, 65.1, 6.8, 87.6, 0.2], ["SCL", 16, 34.5, 65.1, 6.8, 65.1, 0.2], ["SCL", 16, 6.8, 65.1, 6.7, 65.1, 0.2], ["SCL", 1, 6.8, 87.6, 6.8, 93.6, 0.2], ["SDA", 1, 73.575, 52.654, 73.575, 53.779, 0.2], ["SDA", 16, 80, 41.7, 80, 42.6, 0.2], ["SDA", 16, 80, 42.6, 78.1, 44.5, 0.2], ["SDA", 16, 78.1, 44.5, 73.4, 44.5, 0.2], ["SDA", 16, 73.4, 44.5, 72.9, 45, 0.2], ["SDA", 16, 72.9, 45, 72.9, 54.8, 0.2], ["SDA", 1, 72.9, 54.8, 73.5, 54.2, 0.2], ["SDA", 1, 73.5, 54.2, 73.5, 53.8, 0.2], ["SDA", 2, 72.6, 54.8, 71.8, 54.8, 0.2], ["SDA", 2, 71.8, 54.8, 70, 53, 0.2], ["SDA", 2, 70, 53, 70, 51.9, 0.2], ["SDA", 2, 70, 51.9, 69.9, 51.8, 0.2], ["SDA", 1, 69.9, 51.8, 70.6, 51.1, 0.2], ["SDA", 1, 70.6, 51.1, 70.6, 48.7, 0.2], ["SDA", 1, 70.6, 48.7, 70.5, 48.6, 0.2], ["SDA", 2, 70.5, 48.6, 70.5, 48.8, 0.2], ["SDA", 2, 70.5, 48.8, 69.9, 49.4, 0.2], ["SDA", 2, 69.9, 49.4, 61.6, 49.4, 0.2], ["SDA", 2, 61.6, 49.4, 61.5, 49.3, 0.2], ["SDA", 2, 61.5, 49.3, 60.7, 49.3, 0.2], ["SDA", 2, 60.7, 49.3, 60.4, 49.6, 0.2], ["SDA", 2, 60.4, 49.6, 60.4, 50.4, 0.2], ["SDA", 2, 60.4, 50.4, 60.9, 50.9, 0.2], ["SDA", 16, 60.9, 50.9, 60.9, 59.6, 0.2], ["SDA", 1, 60.9, 59.6, 55.8, 59.6, 0.2], ["SDA", 1, 55.8, 59.6, 49.2, 53, 0.2], ["SDA", 1, 49.2, 53, 49.2, 52.9, 0.2], ["SDA", 1, 49.2, 52.9, 49.1, 52.8, 0.2], ["SDA", 16, 60.9, 59.9, 60.9, 64, 0.2], ["SDA", 16, 60.9, 64, 53.9, 71, 0.2], ["SDA", 16, 53.9, 71, 53.3, 71, 0.2], ["SDA", 16, 53.3, 71, 49.5, 74.8, 0.2], ["SDA", 16, 49.5, 74.8, 49.5, 75.5, 0.2], ["SDA", 16, 49.5, 75.5, 48.4, 76.6, 0.2], ["SDA", 16, 48.4, 76.6, 45.2, 76.6, 0.2], ["SDA", 16, 45.2, 76.6, 34.4, 65.8, 0.2], ["SDA", 16, 49.5, 75.6, 50.9, 77, 0.2], ["SDA", 16, 50.9, 77, 51, 77, 0.2], ["SDA", 16, 51, 77, 51.1, 77.1, 0.2], ["SDA", 16, 33.9, 66, 15.5, 84.4, 0.2], ["SDA", 16, 15.5, 84.4, 15.5, 85.5, 0.2], ["SDA", 16, 15.5, 85.5, 15.3, 85.7, 0.2], ["SDA", 16, 15.3, 85.7, 15, 85.7, 0.2], ["SDA", 16, 15, 85.7, 13.2, 87.5, 0.2], ["SDA", 16, 13.2, 87.5, 11.5, 87.5, 0.2], ["SDA", 16, 11.5, 87.5, 11.4, 87.6, 0.2], ["SDA", 2, 11.4, 87.6, 11.4, 94, 0.2], ["SDA", 2, 11.4, 94, 9.7, 95.7, 0.2], ["SDA", 1, 102.5, 31, 102.5, 38.1, 0.2], ["SDA", 16, 102.5, 38.1, 102.5, 49, 0.2], ["SDA", 2, 102.5, 49, 102.5, 56.9, 0.2], ["SDA", 16, 102.5, 56.9, 102.5, 64.9, 0.2], ["SDA", 16, 102.5, 64.9, 102.7, 65.1, 0.2], ["SDA", 16, 102.7, 65.1, 128.7, 65.1, 0.2], ["SDA", 16, 128.7, 65.1, 133.9, 70.3, 0.2], ["SDA", 16, 133.9, 70.3, 134.2, 70.3, 0.2], ["SDA", 16, 134.2, 70.3, 139.2, 75.3, 0.2], ["SDA", 16, 139.2, 75.3, 139.6, 75.3, 0.2], ["SDA", 16, 139.6, 75.3, 139.7, 75.4, 0.2], ["$10N732", 1, 135.169, 70.5, 136.05, 71.4, 0.2], ["$10N732", 1, 136.05, 71.4, 136.05, 74.8, 0.2], ["$10N732", 1, 136.05, 74.8, 135.824, 75.157, 0.2], ["$10N732", 1, 135.824, 75.157, 135.1, 75.5, 0.2], ["$10N732", 2, 135.1, 75.5, 133.85, 76.8, 0.2], ["$10N732", 1, 133.85, 76.8, 133.65, 77, 0.2], ["$10N732", 1, 133.65, 77, 131.2, 77, 0.2], ["$10N732", 1, 131.2, 77, 128.1, 73.9, 0.2], ["$10N732", 1, 128.1, 73.9, 127.85, 73.35, 0.2], ["$10N732", 2, 127.85, 73.35, 127.85, 69.25, 0.2], ["$10N732", 1, 127.85, 69.25, 130.17, 66.934, 0.2], ["$12N878", 1, 43.55, 46.1, 43.3, 46.1, 0.3], ["$12N878", 1, 43.3, 46.1, 41, 43.8, 0.3], ["$12N878", 1, 41, 43.8, 41, 42.5, 0.3], ["$12N878", 1, 41, 42.5, 43.85, 39.65, 0.3], ["$12N878", 2, 43.85, 39.65, 49.1, 34.4, 0.3], ["$12N878", 2, 49.1, 34.4, 49.45, 34.4, 0.3], ["$12N878", 1, 49.45, 34.4, 51.35, 34.4, 0.3], ["$12N878", 2, 51.35, 34.4, 60.05, 34.4, 0.3], ["$12N878", 2, 60.05, 34.4, 65.3, 39.65, 0.3], ["$12N878", 1, 65.3, 39.65, 66, 40.35, 0.3], ["$12N878", 1, 66, 40.35, 66, 41.35, 0.3], ["$12N878", 1, 66, 41.35, 65.65, 41.7, 0.3], ["$12N878", 1, 65.65, 41.7, 64, 41.85, 0.3], ["$12N878", 2, 64, 41.85, 63.7, 42.15, 0.3], ["$12N878", 2, 63.7, 42.15, 60.1, 42.15, 0.3], ["$12N878", 1, 60.1, 42.15, 60.1, 43.15, 0.3], ["$12N878", 1, 60.1, 43.15, 59.05, 44.2, 0.3], ["$12N878", 1, 59.05, 44.2, 58.1, 44.2, 0.3], ["$12N878", 1, 58.1, 44.2, 57.819, 44.017, 0.3], ["$12N878", 1, 57.819, 44.017, 57.7, 43.75, 0.3], ["$17N154", 1, 101.6, 60.8, 100.3, 59.5, 0.2], ["$17N154", 1, 100.3, 59.5, 95.1, 59.5, 0.2], ["$17N154", 2, 95.1, 59.5, 90, 59.5, 0.2], ["$17N154", 1, 90, 59.5, 89.5, 59.5, 0.2], ["$17N154", 1, 89.5, 59.5, 87.1, 57.1, 0.2], ["$17N154", 1, 87.1, 57.1, 87.1, 56.5, 0.2], ["$17N154", 1, 87.1, 56.5, 80.1, 49.5, 0.2], ["$17N154", 1, 80.1, 49.5, 74.4, 49.5, 0.2], ["$17N154", 2, 74.4, 49.5, 67.7, 42.8, 0.2], ["$17N154", 2, 67.7, 42.8, 51.4, 42.8, 0.2], ["$17N154", 2, 51.4, 42.8, 50.5, 41.9, 0.2], ["$17N154", 2, 50.5, 41.9, 29.2, 41.9, 0.2], ["$17N154", 2, 29.2, 41.9, 27.1, 39.8, 0.2], ["$17N154", 2, 27.1, 39.8, 17.3, 39.8, 0.2], ["$17N154", 2, 17.3, 39.8, 7.541, 29.999, 0.2], ["$1N236", 1, 5.499, 101.111, 4.7, 100.3, 0.3], ["$1N236", 1, 4.7, 100.3, 4.7, 94.8, 0.3], ["$1N236", 1, 4.7, 94.8, 3.434, 93.5, 0.3], ["$2N653", 2, 25.7, 18.65, 24.15, 18.65, 0.2], ["$2N653", 2, 24.15, 18.65, 23.65, 19.15, 0.2], ["$2N653", 2, 23.65, 19.15, 19.95, 19.15, 0.2], ["$2N653", 2, 19.95, 19.15, 17.75, 21.35, 0.2], ["$2N653", 2, 17.75, 21.35, 13.6, 21.35, 0.2], ["$2N653", 2, 13.6, 21.35, 11.95, 23, 0.2], ["$2N653", 2, 11.95, 23, 11.95, 26.8, 0.2], ["$2N653", 2, 11.95, 26.8, 9.65, 29.1, 0.2], ["$2N653", 2, 9.65, 29.1, 9.65, 31.15, 0.2], ["$2N653", 1, 9.65, 31.15, 8.85, 31.95, 0.2], ["$2N653", 1, 8.85, 31.95, 8.85, 32.3, 0.2], ["$2N653", 2, 8.85, 32.3, 10.4, 33.85, 0.2], ["$2N653", 1, 10.4, 33.85, 11.5, 32.75, 0.2], ["$2N653", 1, 11.5, 32.75, 11.75, 32.75, 0.2], ["$2N653", 2, 11.75, 32.75, 11.75, 32.5, 0.2], ["$2N653", 2, 11.75, 32.5, 13.45, 30.8, 0.2], ["$2N653", 2, 13.45, 30.8, 15.05, 30.8, 0.2], ["$2N653", 2, 15.05, 30.8, 15.85, 30, 0.2], ["$2N653", 1, 15.85, 30, 15.95, 29.9, 0.2], ["$2N676", 1, 20.375, 47.425, 20.375, 47.15, 0.2], ["$2N676", 2, 20.375, 47.15, 21.275, 46.05, 0.2], ["$2N676", 1, 21.275, 46.05, 21.275, 45.225, 0.2], ["$2N676", 1, 21.275, 45.225, 20.925, 44.875, 0.2], ["$2N676", 1, 20.925, 44.875, 19.35, 44.875, 0.2], ["$2N676", 1, 19.35, 44.875, 19.19, 45.017, 0.2], ["$2N676", 1, 19.19, 45.017, 19.125, 45.163, 0.2], ["$2N676", 1, 19.125, 45.163, 19.125, 45.25, 0.2], ["$2N676", 2, 21.55, 45.95, 21.75, 45.75, 0.2], ["$2N676", 2, 21.75, 45.75, 24.05, 45.75, 0.2], ["$2N676", 2, 24.05, 45.75, 25.65, 44.15, 0.2], ["$2N676", 2, 25.65, 44.15, 28.75, 44.15, 0.2], ["$2N676", 2, 28.75, 44.15, 28.95, 43.95, 0.2], ["$2N676", 1, 28.95, 43.95, 28.95, 40.7, 0.2], ["$2N676", 2, 28.95, 40.7, 27.6, 39.35, 0.2], ["$2N676", 2, 27.6, 39.35, 17.9, 39.35, 0.2], ["$2N676", 2, 17.9, 39.35, 17.7, 39.15, 0.2], ["$2N676", 1, 17.7, 39.15, 15.95, 39.15, 0.2], ["$2N676", 1, 15.95, 39.15, 15.05, 40.05, 0.2], ["$2N676", 1, 15.05, 40.05, 15.05, 43.45, 0.2], ["$2N698", 2, 12.6, 48.8, 12.6, 44.4, 0.2], ["$2N698", 2, 12.6, 44.4, 13.4, 43.6, 0.2], ["$2N698", 2, 13.4, 43.6, 18.1, 43.6, 0.2], ["$2N698", 2, 18.1, 43.6, 18.9, 44.4, 0.2], ["$2N698", 1, 18.9, 44.4, 20.9, 44.4, 0.2], ["$2N698", 1, 20.9, 44.4, 21.3, 44, 0.2], ["$2N698", 1, 21.3, 44, 21.3, 43.3, 0.2], ["$2N698", 1, 21.3, 43.3, 23.1, 41.5, 0.2], ["$2N698", 1, 23.1, 41.5, 25.2, 41.5, 0.2], ["$2N698", 1, 26, 41.7, 26, 42.3, 0.2], ["$2N698", 1, 26, 42.3, 26.6, 42.9, 0.2], ["$2N698", 1, 26.6, 42.9, 26.6, 43.3, 0.2], ["$2N707", 1, 32.5, 36.7, 31.2, 36.7, 0.2], ["$2N707", 2, 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80.848, 37.03, 80, 36.225, 0.2], ["SDA", 1, 80, 36.225, 80.329, 35.811, 0.2], ["VO1", 2, 13.8, 44.4, 15.1, 44.4, 0.3], ["VO1", 2, 15.1, 44.4, 15.45, 44.75, 0.3], ["VO1", 2, 15.45, 44.75, 15.781, 45.595, 0.3], ["VO1", 2, 15.781, 45.595, 15.711, 47.417, 0.3], ["VO1", 2, 15.711, 47.417, 15.9, 47.9, 0.3], ["VO1", 2, 15.9, 47.9, 16.1, 48.1, 0.3], ["VO1", 2, 16.1, 48.1, 17.6, 48.1, 0.3], ["VO1", 2, 17.6, 48.1, 17.9, 47.8, 0.3], ["VO1", 1, 17.9, 47.8, 18.1, 47.6, 0.3], ["VO2", 1, 51.4, 87.25, 51.4, 87.05, 0.3], ["VO2", 1, 51.4, 87.05, 51.2, 86.85, 0.3], ["VO2", 1, 51.2, 86.85, 50.45, 86.85, 0.3], ["VO2", 1, 50.45, 86.85, 46.775, 83.175, 0.3], ["VO2", 2, 46.775, 83.175, 42.875, 79.275, 0.3], ["VO2", 2, 42.875, 79.275, 42.875, 78.625, 0.3], ["VO2", 2, 42.875, 78.625, 43.225, 78.275, 0.3], ["VO2", 2, 43.225, 78.275, 48.975, 78.25, 0.3], ["VO3", 1, 139.775, 87.25, 139.775, 87.05, 0.3], ["VO3", 1, 139.775, 87.05, 139.575, 86.85, 0.3], ["VO3", 1, 139.575, 86.85, 139.25, 86.85, 0.3], ["VO3", 1, 139.25, 86.85, 138.45, 86.05, 0.3], ["VO3", 1, 138.45, 86.05, 138.45, 84.6, 0.3], ["VO3", 1, 138.45, 84.6, 137.425, 83.575, 0.3], ["VO3", 2, 137.425, 83.575, 137.275, 83.425, 0.3], ["VO3", 2, 137.275, 83.425, 137.275, 82.425, 0.3], ["VO3", 2, 137.275, 82.425, 139.3, 80.4, 0.3], ["VO3", 2, 139.3, 80.4, 139.3, 79.95, 0.3], ["VO3", 2, 139.3, 79.95, 139.154, 79.614, 0.3], ["VO3", 2, 139.154, 79.614, 137.775, 78.325, 0.3], ["VO3", 1, 137.775, 78.325, 137.775, 78.25, 0.3], ["VO4", 1, 44.45, 37.4, 41.55, 34.5, 0.3], ["VO4", 1, 41.55, 34.5, 37.5, 34.5, 0.3], ["VO4", 1, 37.5, 34.5, 34.75, 31.75, 0.3], ["VO4", 1, 34.75, 31.75, 34.75, 29.5, 0.3], ["VO4", 1, 34.75, 29.5, 36.2, 28.05, 0.3], ["VO4", 1, 36.2, 28.05, 36.2, 24.25, 0.3], ["VO4", 1, 36.2, 24.25, 41.954, 18.501, 0.3]]} \ No newline at end of file +{"comp": [["C1", -4.5001, 68.0001, 0, 1], ["C2", 6.5001, 84.5, 0, 1], ["C3", 16, 84.5, 0, 1], ["C4", 30.5001, 80.0001, 180, 1], ["C5", 30.5001, 83.0001, 180, 1], ["C6", 30.5001, 86.0001, 180, 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0, 1], ["U13", 6.5001, 99.0001, 0, 1], ["U14", 14.2999, 45.8, 180, 1], ["U15", 53.5889, 79.7001, 0, 1], ["U16", 141.969, 79.7001, 0, 1], ["U17", 45.9689, 45.8, 180, 1], ["U18", 125.4999, 45.8, 180, 1], ["U19", 19, 104, 0, 1], ["U20", 88.0001, 18.2001, 180, 1], ["U23", 76.5, 49.6301, 0, 1], ["U29", 12.5001, 94.0001, 0, 1], ["C731", 68.2, 72.0001, 270, 1], ["C732", 70.6999, 72.0001, 270, 1], ["C733", 64.0001, 69.6001, 180, 1], ["C734", 77.5, 78.0001, 90, 1], ["C735", 80.0001, 78.0001, 90, 1], ["L3", 70.5, 78.0001, 0, 1], ["R706", 59.9999, 73.5, 0, 1], ["R707", 59.9999, 71.5, 180, 1], ["U30", 64.0001, 72.0001, 0, 1], ["R733", 98.0001, 80.5, 0, 1], ["R734", 101.4999, 80.5, 0, 1], ["C738", 105, 120, 0, 1], ["D2", 111.4999, 120, 0, 1], ["Q6", 102, 69.5, 0, 1], ["F1", -12.5001, 74.5, 90, 1], ["R9A", 18, 100.4999, 0, 1], ["R9B", 18, 96.4999, 0, 1], ["R9C", 25.9999, 96.4999, 0, 1], ["R9D", 25.9999, 92.0001, 0, 1], ["R9E", 18, 92.0001, 0, 1], ["J24", 31.9999, 62.5, 0, 1], ["J25", 128, 62.5, 0, 1], ["DZ3", 99.4999, 120, 0, 1], ["J26", -23.8999, 115, 0, 1], ["J27", 183.9001, 115, 0, 1], ["Q7", 95.0001, 120, 0, 1], ["Q8", 95.0001, 116, 0, 1], ["Q9", -25.9999, 104, 0, 1], ["Q10", 180.9999, 104, 0, 1], ["R746", 91.0001, 120, 0, 1], ["R747", 91.0001, 116, 0, 1], ["R748", 99.4999, 116, 0, 1], ["R749", 103, 116, 0, 1], ["R750", -25.9999, 108, 0, 1], ["R751", -21, 108, 0, 1], ["R752", -21, 104, 0, 1], ["R753", -25.9999, 100.0001, 0, 1], ["R754", 180.9999, 108, 0, 1], ["R755", 185.9999, 108, 0, 1], ["R756", 185.9999, 104, 0, 1], ["R757", 180.9999, 100.0001, 0, 1], ["J1", -18.8001, 72.0001, 0, 1]], "th": [["GND", -22, 3, 5.999, 5.999], ["GND", 182, 3, 5.999, 5.999], ["GND", -26, 126, 5.999, 5.999], ["GND", 186, 126, 5.999, 5.999], ["GND", -23, 55, 5.999, 5.999], ["GND", 183, 40, 5.999, 5.999], ["GND", 8.25, 84.5, 1.6, 1.6], ["$1N236", 4.75, 84.5, 1.6, 1.6], ["GND", 17.75, 84.5, 1.6, 1.6], ["$1N236", 14.25, 84.5, 1.6, 1.6], ["GND", 181.926, 48.8, 0, 0], ["GND", 181.926, 55.2, 0, 0], ["", 181.926, 54.4, 0, 0], ["", 181.926, 49.6, 0, 0], ["GND", 186.874, 56.325, 1.199, 1.801], ["GND", 182.694, 56.325, 1.199, 1.999], ["GND", 182.694, 47.675, 1.199, 1.999], ["GND", 186.874, 47.675, 1.199, 1.801], ["GND", 16.8, 27.5, 0, 0], ["GND", 51.089, 98, 0, 0], ["GND", 139.469, 98, 0, 0], ["GND", 48.469, 27.5, 0, 0], ["GND", 128, 27.5, 0, 0], ["GND", 79.58, 38.01, 0, 0], ["GND", 109.57, 34.71, 0, 0], ["GND", 7.87, 61.23, 1.575, 1.801], ["VO1_P", 7.87, 63.77, 1.801, 1.801], ["GND", 10.41, 61.23, 1.801, 1.801], ["VO1_P", 10.41, 63.77, 1.801, 1.801], ["GND", 12.95, 61.23, 1.801, 1.801], ["VO1_P", 12.95, 63.77, 1.801, 1.801], ["GND", 15.49, 61.23, 1.801, 1.801], ["+5V", 15.49, 63.77, 1.801, 1.801], ["GND", 18.03, 61.23, 1.801, 1.801], ["+5V", 18.03, 63.77, 1.801, 1.801], ["GND", 20.57, 61.23, 1.801, 1.801], ["GND", 20.57, 63.77, 1.801, 1.801], ["GND", 23.11, 61.23, 1.801, 1.801], ["GND", 23.11, 63.77, 1.801, 1.801], ["GND", 25.65, 61.23, 1.801, 1.801], ["GND", 25.65, 63.77, 1.801, 1.801], ["GND", 28.19, 61.23, 1.801, 1.801], ["GND", 28.19, 63.77, 1.801, 1.801], ["VBUS_EN4", 30.73, 61.23, 1.801, 1.801], ["VBUS_EN1", 30.73, 63.77, 1.801, 1.801], ["+5V", 33.27, 61.23, 1.801, 1.801], ["SDA", 33.27, 63.77, 1.801, 1.801], ["+5V", 35.81, 61.23, 1.801, 1.801], ["SCL", 35.81, 63.77, 1.801, 1.801], ["UP_VBUS_DET", 38.35, 61.23, 1.801, 1.801], ["GND", 38.35, 63.77, 1.801, 1.801], ["GND", 40.89, 61.23, 1.801, 1.801], ["GND", 40.89, 63.77, 1.801, 1.801], ["VO4_P", 43.43, 61.23, 1.801, 1.801], ["GND", 43.43, 63.77, 1.801, 1.801], ["VO4_P", 45.97, 61.23, 1.801, 1.801], ["GND", 45.97, 63.77, 1.801, 1.801], ["VO4_P", 48.51, 61.23, 1.801, 1.801], ["GND", 48.51, 63.77, 1.801, 1.801], ["GND", 51.05, 61.23, 1.801, 1.801], ["VO2_P", 51.05, 63.77, 1.801, 1.801], ["GND", 53.59, 61.23, 1.801, 1.801], ["VO2_P", 53.59, 63.77, 1.801, 1.801], ["GND", 56.13, 61.23, 1.801, 1.801], ["VO2_P", 56.13, 63.77, 1.801, 1.801], ["+5V", 103.87, 61.23, 1.575, 1.801], ["+5V", 103.87, 63.77, 1.801, 1.801], ["+5V", 106.41, 61.23, 1.801, 1.801], ["+5V", 106.41, 63.77, 1.801, 1.801], ["VBUS_EN5", 108.95, 61.23, 1.801, 1.801], ["KEY_SER", 108.95, 63.77, 1.801, 1.801], ["GND", 111.49, 61.23, 1.801, 1.801], ["KEY_SRCLK", 111.49, 63.77, 1.801, 1.801], ["GND", 114.03, 61.23, 1.801, 1.801], ["KEY_RCLK", 114.03, 63.77, 1.801, 1.801], ["GND", 116.57, 61.23, 1.801, 1.801], ["KEY_OE#", 116.57, 63.77, 1.801, 1.801], ["GND", 119.11, 61.23, 1.801, 1.801], ["VBUS_EN2", 119.11, 63.77, 1.801, 1.801], ["GND", 121.65, 61.23, 1.801, 1.801], ["GND", 121.65, 63.77, 1.801, 1.801], ["VO5_P", 124.19, 61.23, 1.801, 1.801], ["GND", 124.19, 63.77, 1.801, 1.801], ["VO5_P", 126.73, 61.23, 1.801, 1.801], ["GND", 126.73, 63.77, 1.801, 1.801], ["VO5_P", 129.27, 61.23, 1.801, 1.801], ["GND", 129.27, 63.77, 1.801, 1.801], ["GND", 131.81, 61.23, 1.801, 1.801], ["GND", 131.81, 63.77, 1.801, 1.801], ["GND", 134.35, 61.23, 1.801, 1.801], ["GND", 134.35, 63.77, 1.801, 1.801], ["GND", 136.89, 61.23, 1.801, 1.801], ["GND", 136.89, 63.77, 1.801, 1.801], ["GND", 139.43, 61.23, 1.801, 1.801], ["VO3_P", 139.43, 63.77, 1.801, 1.801], ["GND", 141.97, 61.23, 1.801, 1.801], ["VO3_P", 141.97, 63.77, 1.801, 1.801], ["GND", 144.51, 61.23, 1.801, 1.801], ["VO3_P", 144.51, 63.77, 1.801, 1.801], ["GND", 147.05, 61.23, 1.801, 1.801], ["GND", 147.05, 63.77, 1.801, 1.801], ["GND", 149.59, 61.23, 1.801, 1.801], ["VBUS_EN3", 149.59, 63.77, 1.801, 1.801], ["+5V", 152.13, 61.23, 1.801, 1.801], ["+5V", 152.13, 63.77, 1.801, 1.801], ["GND", -27.71, 115, 1.6, 1.6], ["FAN_12V_SW", -25.17, 115, 1.6, 1.6], ["FAN_IN_TACH_RAW", -22.63, 115, 1.6, 1.6], ["FAN_PWM_L", -20.09, 115, 1.6, 1.6], ["GND", 180.09, 115, 1.6, 1.6], ["FAN_12V_SW", 182.63, 115, 1.6, 1.6], ["FAN_OUT_TACH_RAW", 185.17, 115, 1.6, 1.6], ["FAN_PWM_L", 187.71, 115, 1.6, 1.6], ["GND", -18.3, 69.65, 3.599, 1.6], ["GND", -21.8, 74.35, 1.6, 3.8], ["$1N223", -15.8, 74.35, 1.6, 3.8]], "via": [["GND", 30.35, 71.814, 0.61], ["GND", 30.35, 72.464, 0.61], ["GND", 31, 71.814, 0.61], ["GND", 31, 72.464, 0.61], ["GND", 31.65, 71.814, 0.61], ["GND", 31.65, 72.464, 0.61], ["GND", 16.3, 27, 0.61], ["GND", 16.3, 28, 0.61], ["GND", 17.3, 27, 0.61], ["GND", 17.3, 28, 0.61], ["GND", 16.8, 27.5, 0.61], ["GND", 50.589, 97.5, 0.61], ["GND", 50.589, 98.5, 0.61], ["GND", 51.589, 97.5, 0.61], ["GND", 51.589, 98.5, 0.61], ["GND", 51.089, 98, 0.61], ["GND", 138.969, 97.5, 0.61], ["GND", 138.969, 98.5, 0.61], ["GND", 139.969, 97.5, 0.61], ["GND", 139.969, 98.5, 0.61], ["GND", 139.469, 98, 0.61], ["GND", 47.969, 27, 0.61], ["GND", 47.969, 28, 0.61], ["GND", 48.969, 27, 0.61], ["GND", 48.969, 28, 0.61], ["GND", 48.469, 27.5, 0.61], ["GND", 127.5, 27, 0.61], ["GND", 127.5, 28, 0.61], ["GND", 128.5, 27, 0.61], ["GND", 128.5, 28, 0.61], ["GND", 128, 27.5, 0.61], ["GND", 79.255, 37.685, 0.61], ["GND", 79.255, 38.335, 0.61], ["GND", 79.905, 37.685, 0.61], ["GND", 79.905, 38.335, 0.61], ["GND", 109.245, 34.385, 0.61], ["GND", 109.245, 35.035, 0.61], ["GND", 109.895, 34.385, 0.61], ["GND", 109.895, 35.035, 0.61], ["GND", 13.65, 45.475, 0.61], ["GND", 13.65, 46.125, 0.61], ["GND", 14.3, 45.475, 0.61], ["GND", 14.3, 46.125, 0.61], ["GND", 14.95, 45.475, 0.61], ["GND", 14.95, 46.125, 0.61], ["GND", 52.939, 79.375, 0.61], ["GND", 52.939, 80.025, 0.61], ["GND", 53.589, 79.375, 0.61], ["GND", 53.589, 80.025, 0.61], ["GND", 54.239, 79.375, 0.61], ["GND", 54.239, 80.025, 0.61], ["GND", 141.319, 79.375, 0.61], ["GND", 141.319, 80.025, 0.61], ["GND", 141.969, 79.375, 0.61], ["GND", 141.969, 80.025, 0.61], ["GND", 142.619, 79.375, 0.61], ["GND", 142.619, 80.025, 0.61], ["GND", 45.319, 45.475, 0.61], ["GND", 45.319, 46.125, 0.61], ["GND", 45.969, 45.475, 0.61], ["GND", 45.969, 46.125, 0.61], ["GND", 46.619, 45.475, 0.61], ["GND", 46.619, 46.125, 0.61], ["GND", 124.85, 45.475, 0.61], ["GND", 124.85, 46.125, 0.61], ["GND", 125.5, 45.475, 0.61], ["GND", 125.5, 46.125, 0.61], ["GND", 126.15, 45.475, 0.61], ["GND", 126.15, 46.125, 0.61], ["GND", 21.066, 90.7, 0.61], ["GND", 21.066, 91.35, 0.61], ["GND", 21.066, 92, 0.61], ["GND", 21.066, 92.65, 0.61], ["GND", 21.066, 93.3, 0.61], ["GND", 32.975, 80, 0.61], ["GND", 32.975, 83, 0.61], ["GND", 31.789, 86, 0.61], ["GND", 18.565, 109.863, 0.61], ["GND", 19.047, 112.5, 0.61], ["GND", 24.547, 112.5, 0.61], ["GND", 12.289, 99, 0.61], ["GND", 13.775, 27.8, 0.61], ["GND", 13.775, 31.45, 0.61], ["GND", 13.775, 22.2, 0.61], ["GND", 22.168, 24.92, 0.61], ["GND", 18.32, 42.6, 0.61], ["GND", 18.325, 40.5, 0.61], ["GND", 17.989, 38, 0.61], ["GND", 29.588, 18.5, 0.61], ["GND", 23.324, 18.5, 0.61], ["GND", 23.089, 20.7, 0.61], ["GND", 19.588, 20.7, 0.61], ["GND", 20.089, 51.8, 0.61], ["GND", 24.324, 47.5, 0.61], ["GND", 54.114, 97.7, 0.61], ["GND", 54.114, 94.05, 0.61], ["GND", 54.114, 103.3, 0.61], ["GND", 47.457, 100.58, 0.61], ["GND", 49.569, 82.9, 0.61], ["GND", 52.843, 85, 0.61], ["GND", 50.769, 88.368, 0.61], ["GND", 39.169, 107.869, 0.61], ["GND", 45.544, 107.979, 0.61], ["GND", 45.669, 105.668, 0.61], ["GND", 49.169, 105.668, 0.61], ["GND", 48.669, 74.568, 0.61], ["GND", 44.544, 78.979, 0.61], ["GND", 142.494, 97.7, 0.61], ["GND", 142.494, 94.05, 0.61], ["GND", 142.494, 103.3, 0.61], ["GND", 135.837, 100.58, 0.61], ["GND", 137.949, 82.9, 0.61], ["GND", 141.223, 85, 0.61], ["GND", 139.149, 88.368, 0.61], ["GND", 127.549, 107.869, 0.61], ["GND", 133.924, 107.979, 0.61], ["GND", 134.049, 105.668, 0.61], ["GND", 137.549, 105.668, 0.61], ["GND", 137.049, 74.568, 0.61], ["GND", 132.924, 78.979, 0.61], ["GND", 45.444, 27.8, 0.61], ["GND", 45.444, 31.45, 0.61], ["GND", 45.444, 22.2, 0.61], ["GND", 53.837, 24.92, 0.61], ["GND", 49.989, 42.6, 0.61], ["GND", 49.994, 40.5, 0.61], ["GND", 49.658, 38, 0.61], ["GND", 61.258, 18.5, 0.61], ["GND", 54.993, 18.5, 0.61], ["GND", 54.758, 20.7, 0.61], ["GND", 51.257, 20.7, 0.61], ["GND", 51.758, 51.8, 0.61], ["GND", 55.993, 47.5, 0.61], ["GND", 124.975, 27.8, 0.61], ["GND", 124.975, 31.45, 0.61], ["GND", 124.975, 22.2, 0.61], ["GND", 133.369, 24.92, 0.61], ["GND", 129.52, 42.6, 0.61], ["GND", 129.525, 40.5, 0.61], ["GND", 129.189, 38, 0.61], ["GND", 140.789, 18.5, 0.61], ["GND", 134.524, 18.5, 0.61], ["GND", 134.289, 20.7, 0.61], ["GND", 130.789, 20.7, 0.61], ["GND", 131.289, 51.8, 0.61], ["GND", 135.524, 47.5, 0.61], ["GND", 101.29, 12.167, 0.61], ["GND", 98.151, 9.285, 0.61], ["GND", 99.703, 13.416, 0.61], ["GND", 96.991, 56.681, 0.61], ["GND", 97.581, 42.322, 0.61], ["GND", 72.137, 54.081, 0.61], ["GND", 80.793, 40.496, 0.61], ["GND", 84.004, 40.511, 0.61], ["GND", 78.03, 39.608, 0.61], ["GND", 110.781, 37.194, 0.61], ["GND", 113.995, 37.21, 0.61], ["GND", 108.021, 36.306, 0.61], ["GND", 77.865, 13.933, 0.61], ["GND", 23.52, 52.963, 0.61], ["GND", 24.197, 55.95, 0.61], ["GND", 34.397, 28.45, 0.61], ["GND", 38.397, 28.45, 0.61], ["GND", 34.397, 32.45, 0.61], ["GND", 45.886, 73.55, 0.61], ["GND", 45.886, 69.55, 0.61], ["GND", 35.686, 97.05, 0.61], ["GND", 31.686, 97.05, 0.61], ["GND", 35.686, 93.05, 0.61], ["GND", 134.266, 73.55, 0.61], ["GND", 134.266, 69.55, 0.61], ["GND", 124.066, 97.05, 0.61], ["GND", 120.066, 97.05, 0.61], ["GND", 124.066, 93.05, 0.61], ["GND", 55.189, 52.963, 0.61], ["GND", 55.866, 55.95, 0.61], ["GND", 66.066, 28.45, 0.61], ["GND", 70.066, 28.45, 0.61], ["GND", 66.066, 32.45, 0.61], ["GND", 134.72, 52.963, 0.61], ["GND", 135.397, 55.95, 0.61], ["GND", 145.597, 28.45, 0.61], ["GND", 149.597, 28.45, 0.61], ["GND", 145.597, 32.45, 0.61], ["GND", 26.675, 71.5, 0.61], ["GND", 20.567, 116.892, 0.61], ["GND", 20.567, 119.391, 0.61], ["GND", 12.624, 20.7, 0.61], ["GND", 24.867, 19.392, 0.61], ["GND", 29.624, 20.7, 0.61], ["GND", 20.624, 45.5, 0.61], ["GND", 20.624, 43.5, 0.61], ["GND", 22.367, 46.392, 0.61], ["GND", 27.624, 47.5, 0.61], ["GND", 27.624, 41.5, 0.61], ["GND", 33.624, 35, 0.61], ["GND", 33.624, 38, 0.61], ["GND", 33.624, 41, 0.61], ["GND", 55.265, 104.8, 0.61], ["GND", 43.913, 107, 0.61], ["GND", 39.156, 105.691, 0.61], ["GND", 48.156, 80.892, 0.61], ["GND", 48.156, 82.892, 0.61], ["GND", 46.414, 80, 0.61], ["GND", 41.156, 78.892, 0.61], ["GND", 41.156, 84.892, 0.61], ["GND", 35.156, 91.392, 0.61], ["GND", 35.156, 88.392, 0.61], ["GND", 35.156, 85.392, 0.61], ["GND", 143.645, 104.8, 0.61], ["GND", 132.293, 107, 0.61], ["GND", 127.536, 105.691, 0.61], ["GND", 136.536, 80.892, 0.61], ["GND", 136.536, 82.892, 0.61], ["GND", 134.794, 80, 0.61], ["GND", 129.536, 78.892, 0.61], ["GND", 129.536, 84.892, 0.61], ["GND", 123.536, 91.392, 0.61], ["GND", 123.536, 88.392, 0.61], ["GND", 123.536, 85.392, 0.61], ["GND", 44.293, 20.7, 0.61], ["GND", 56.536, 19.392, 0.61], ["GND", 61.293, 20.7, 0.61], ["GND", 52.293, 45.5, 0.61], ["GND", 52.293, 43.5, 0.61], ["GND", 54.036, 46.392, 0.61], ["GND", 59.293, 47.5, 0.61], ["GND", 59.293, 41.5, 0.61], ["GND", 65.293, 35, 0.61], ["GND", 65.293, 38, 0.61], ["GND", 65.293, 41, 0.61], ["GND", 123.824, 20.7, 0.61], ["GND", 136.067, 19.392, 0.61], ["GND", 140.825, 20.7, 0.61], ["GND", 131.825, 45.5, 0.61], ["GND", 131.825, 43.5, 0.61], ["GND", 133.567, 46.392, 0.61], ["GND", 138.825, 47.5, 0.61], ["GND", 138.825, 41.5, 0.61], ["GND", 144.825, 35, 0.61], ["GND", 144.825, 38, 0.61], ["GND", 144.825, 41, 0.61], ["GND", 150.703, 52.518, 0.61], ["GND", 151.044, 55.45, 0.61], ["GND", 77.883, 36.35, 0.61], ["GND", 107.873, 33.049, 0.61], ["GND", 71.891, 36.753, 0.61], ["GND", 71.891, 26.753, 0.61], ["GND", 15.075, 29.174, 0.61], ["GND", 14.222, 28.854, 0.61], ["GND", 52.814, 96.326, 0.61], ["GND", 53.667, 96.647, 0.61], ["GND", 141.194, 96.326, 0.61], ["GND", 142.048, 96.647, 0.61], ["GND", 46.744, 29.174, 0.61], ["GND", 45.891, 28.854, 0.61], ["GND", 126.275, 29.174, 0.61], ["GND", 125.422, 28.854, 0.61], ["GND", 12.579, 50.196, 0.61], ["GND", 13.8, 51.012, 0.61], ["GND", 14.8, 55.232, 0.61], ["GND", 55.31, 75.304, 0.61], ["GND", 53.089, 72.912, 0.61], ["GND", 142.469, 77.132, 0.61], ["GND", 141.469, 72.912, 0.61], ["GND", 46.469, 55.232, 0.61], ["GND", 123.779, 50.196, 0.61], ["GND", 126, 55.232, 0.61], ["GND", 5.5, 98.212, 0.61], ["GND", 7, 102.432, 0.61], ["GND", 16.524, 44.3, 0.61], ["GND", 16.524, 47.3, 0.61], ["GND", 51.365, 81.2, 0.61], ["GND", 51.365, 78.2, 0.61], ["GND", 139.745, 81.2, 0.61], ["GND", 139.745, 78.2, 0.61], ["GND", 48.193, 44.3, 0.61], ["GND", 48.193, 47.3, 0.61], ["GND", 127.724, 44.3, 0.61], ["GND", 127.724, 47.3, 0.61], ["GND", 21.476, 103.05, 0.61], ["GND", 95.375, 9.305, 0.61], ["GND", 80.625, 9.305, 0.61], ["GND", 88.535, 19.475, 0.61], ["GND", 89.935, 19.475, 0.61], ["GND", 92.036, 18.425, 0.61], ["GND", 92.036, 15.625, 0.61], ["GND", 89.066, 14.576, 0.61], ["GND", 87.051, 16.06, 0.61], ["GND", 87.051, 17.46, 0.61], ["GND", 92.036, 17.025, 0.61], ["GND", 90.49, 14.636, 0.61], ["GND", 98.225, 49.634, 0.61], ["GND", 98.815, 35.275, 0.61], ["GND", 74.225, 47.957, 0.61], ["GND", 73.575, 45.258, 0.61], ["GND", 81.424, 46.608, 0.61], ["GND", 79.425, 47.957, 0.61], ["GND", 75.525, 54.002, 0.61], ["GND", 74.875, 51.303, 0.61], ["GND", 76.175, 51.303, 0.61], ["GND", 76.825, 54.002, 0.61], ["GND", 12.597, 94, 0.61], ["GND", 66.837, 71.565, 0.61], ["GND", 72.175, 71, 0.61], ["GND", 78.127, 81.107, 0.61], ["GND", 81.639, 79.593, 0.61], ["GND", 59.567, 72.392, 0.61], ["GND", 64.224, 71.05, 0.61], ["GND", 97.975, 68.265, 0.61], ["GND", 105.232, 74, 0.61], ["GND", 106.324, 78, 0.61], ["GND", 108.289, 74, 0.61], ["GND", 104.097, 70.45, 0.61], ["GND", 77.033, 11.012, 0.61], ["GND", 150.728, 48.589, 0.61], ["GND", 150.236, 55.498, 0.61], ["+12V", 21.475, 108.5, 0.61], ["+12V", 21.043, 109.543, 0.61], ["+12V", 20, 109.975, 0.61], ["+12V", 13.775, 25.8, 0.61], ["+12V", 10.937, 26.365, 0.61], ["+12V", 10.937, 25.235, 0.61], ["+12V", 13.663, 30.015, 0.61], ["+12V", 10.937, 30.015, 0.61], ["+12V", 10.324, 29.45, 0.61], ["+12V", 13.775, 24.2, 0.61], ["+12V", 10.824, 24.2, 0.61], ["+12V", 14.125, 24.956, 0.61], ["+12V", 22.168, 24.08, 0.61], ["+12V", 57.064, 99.7, 0.61], ["+12V", 54.226, 100.265, 0.61], ["+12V", 54.226, 99.135, 0.61], ["+12V", 57.064, 96.05, 0.61], ["+12V", 54.226, 95.485, 0.61], ["+12V", 57.864, 96.05, 0.61], ["+12V", 57.064, 101.3, 0.61], ["+12V", 54.226, 101.865, 0.61], ["+12V", 53.613, 101.3, 0.61], ["+12V", 47.457, 101.42, 0.61], ["+12V", 145.444, 99.7, 0.61], ["+12V", 142.606, 100.265, 0.61], ["+12V", 142.606, 99.135, 0.61], ["+12V", 145.444, 96.05, 0.61], ["+12V", 142.606, 95.485, 0.61], ["+12V", 146.244, 96.05, 0.61], ["+12V", 145.444, 101.3, 0.61], ["+12V", 142.606, 101.865, 0.61], ["+12V", 141.993, 101.3, 0.61], ["+12V", 135.837, 101.42, 0.61], ["+12V", 45.444, 25.8, 0.61], ["+12V", 42.606, 26.365, 0.61], ["+12V", 42.606, 25.235, 0.61], ["+12V", 45.332, 30.015, 0.61], ["+12V", 42.606, 30.015, 0.61], ["+12V", 41.993, 29.45, 0.61], ["+12V", 45.444, 24.2, 0.61], ["+12V", 42.493, 24.2, 0.61], ["+12V", 45.794, 24.956, 0.61], ["+12V", 53.837, 24.08, 0.61], ["+12V", 124.975, 25.8, 0.61], ["+12V", 122.137, 26.365, 0.61], ["+12V", 122.137, 25.235, 0.61], ["+12V", 124.863, 30.015, 0.61], ["+12V", 122.137, 30.015, 0.61], ["+12V", 121.524, 29.45, 0.61], ["+12V", 124.975, 24.2, 0.61], ["+12V", 122.024, 24.2, 0.61], ["+12V", 125.325, 24.956, 0.61], ["+12V", 133.369, 24.08, 0.61], ["+12V", 23.595, 117.789, 0.61], ["+12V", 24.865, 117.789, 0.61], ["+12V", 26.135, 117.789, 0.61], ["+12V", 19.324, 118.5, 0.61], ["+12V", 19.324, 121, 0.61], ["+12V", 24.867, 21.592, 0.61], ["+12V", 43.913, 104.8, 0.61], ["+12V", 132.293, 104.8, 0.61], ["+12V", 56.536, 21.592, 0.61], ["+12V", 136.067, 21.592, 0.61], ["+12V", 8, 91, 0.61], ["+12V", 8.9, 91, 0.61], ["+12V", 9.8, 91, 0.61], ["+12V", 10.7, 91, 0.61], ["+12V", 8, 90, 0.61], ["+12V", 8.9, 90, 0.61], ["+12V", 9.8, 90, 0.61], ["+12V", 10.7, 90, 0.61], ["+12V", 8, 89, 0.61], ["+12V", 8.9, 89, 0.61], ["+12V", 9.8, 89, 0.61], ["+12V", 10.7, 89, 0.61], ["+12V", 14.722, 25.647, 0.61], ["+12V", 14.151, 27, 0.61], ["+12V", 15.075, 24.926, 0.61], ["+12V", 53.467, 99.653, 0.61], ["+12V", 53.738, 98.5, 0.61], ["+12V", 52.814, 100.124, 0.61], ["+12V", 141.847, 99.653, 0.61], ["+12V", 142.118, 98.5, 0.61], ["+12V", 141.194, 100.124, 0.61], ["+12V", 46.391, 25.647, 0.61], ["+12V", 45.82, 27, 0.61], ["+12V", 46.744, 24.926, 0.61], ["+12V", 125.922, 25.647, 0.61], ["+12V", 125.351, 27, 0.61], ["+12V", 126.275, 24.926, 0.61], ["+12V", 21.476, 104.95, 0.61], ["+12V", 18.776, 104, 0.61], ["+12V", 69.243, 74.043, 0.61], ["+12V", 68.2, 74.476, 0.61], ["+12V", 67.157, 74.043, 0.61], ["+12V", 72.175, 73, 0.61], ["+12V", 71.743, 74.043, 0.61], ["+12V", 70.7, 74.476, 0.61], ["+12V", 66.476, 72.95, 0.61], ["+12V", 63.776, 72, 0.61], ["+12V", 102.047, 74, 0.61], ["+12V", 101.567, 75.159, 0.61], ["+12V", 100.407, 75.639, 0.61], ["+12V", 97.567, 78.892, 0.61], ["+3V3", 18.38, 52.668, 0.61], ["+3V3", 50.049, 52.668, 0.61], ["+3V3", 129.58, 52.668, 0.61], ["+3V3", 101.019, 10.994, 0.61], ["+3V3", 79.084, 41.364, 0.61], ["+3V3", 109.072, 38.062, 0.61], ["+3V3", 22.367, 44.392, 0.61], ["+3V3", 27.624, 45.5, 0.61], ["+3V3", 23.375, 51, 0.61], ["+3V3", 54.036, 44.392, 0.61], ["+3V3", 58.402, 46.392, 0.61], ["+3V3", 55.045, 51, 0.61], ["+3V3", 133.567, 44.392, 0.61], ["+3V3", 138.825, 45.5, 0.61], ["+3V3", 134.575, 51, 0.61], ["+3V3", 85.906, 29.365, 0.61], ["+3V3", 99.043, 17.761, 0.61], ["+3V3", 76.8, 45.208, 0.61], ["+3V3", 79.563, 44.261, 0.61], ["+3V3", 76.166, 39.39, 0.61], ["+3V3", 106.156, 36.089, 0.61], ["+3V3", 76.369, 10.154, 0.61], ["+3V3", 76.094, 11.81, 0.61], ["+3V3", 16.622, 53.91, 0.61], ["+3V3", 44.248, 50.196, 0.61], ["+3V3", 45.469, 51.012, 0.61], ["+3V3", 48.291, 53.91, 0.61], ["+3V3", 127.822, 53.91, 0.61], ["+3V3", 95.375, 10.575, 0.61], ["+3V3", 94.575, 10.575, 0.61], ["+3V3", 93.775, 10.575, 0.61], ["+3V3", 87.805, 56.636, 0.61], ["+3V3", 95.175, 75.266, 0.61], ["VO1_P", 26.997, 54.599, 0.61], ["VO1_P", 26.1, 54.777, 0.61], ["VO1_P", 25.203, 54.599, 0.61], ["VO1_P", 19.71, 56.8, 0.61], ["VO1_P", 19.531, 57.697, 0.61], ["VO1_P", 19.023, 58.457, 0.61], ["VO1_P", 14.3, 52.588, 0.61], ["VO2_P", 40.892, 70.901, 0.61], ["VO2_P", 41.789, 70.723, 0.61], ["VO2_P", 42.686, 70.901, 0.61], ["VO2_P", 52.866, 68.7, 0.61], ["VO2_P", 52.688, 69.597, 0.61], ["VO2_P", 51.419, 70.865, 0.61], ["VO2_P", 53.589, 70.268, 0.61], ["VO3_P", 128.512, 71.409, 0.61], ["VO3_P", 129.272, 70.901, 0.61], ["VO3_P", 130.169, 70.723, 0.61], ["VO3_P", 141.246, 68.7, 0.61], ["VO3_P", 141.068, 69.597, 0.61], ["VO3_P", 139.8, 70.865, 0.61], ["VO3_P", 141.969, 70.268, 0.61], ["VO4_P", 59.426, 54.091, 0.61], ["VO4_P", 58.666, 54.599, 0.61], ["VO4_P", 57.769, 54.777, 0.61], ["VO4_P", 51.379, 56.8, 0.61], ["VO4_P", 51.2, 57.697, 0.61], ["VO4_P", 50.692, 58.457, 0.61], ["VO4_P", 45.969, 52.588, 0.61], ["VO5_P", 138.957, 54.091, 0.61], ["VO5_P", 138.197, 54.599, 0.61], ["VO5_P", 137.3, 54.777, 0.61], ["VO5_P", 130.91, 56.8, 0.61], ["VO5_P", 130.731, 57.697, 0.61], ["VO5_P", 130.223, 58.457, 0.61], ["VO5_P", 125.5, 52.588, 0.61], ["$10N653", 135.05, 99.25, 0.61], ["$10N653", 139.9, 95.25, 0.61], ["$10N655", 141, 106.8, 0.61], ["$10N655", 142.485, 104.8, 0.61], ["$10N659", 135.5, 107, 0.61], ["$10N659", 137.1, 106.9, 0.61], ["$10N687", 138.625, 80.075, 0.61], ["$10N687", 134.825, 77.675, 0.61], ["$10N699", 144.9, 85.4, 0.61], ["$10N699", 125.7, 90.7, 0.61], ["$10N699", 122.5, 91.2, 0.61], ["$10N699", 117.3, 86, 0.61], ["$10N699", 117.3, 83.8, 0.61], ["$10N699", 130.984, 82.001, 0.61], ["$12N842", 58.625, 18.5, 0.61], ["$12N842", 50.725, 26.325, 0.61], ["$12N843", 61.7, 24.1, 0.61], ["$12N843", 64.2, 21.6, 0.61], ["$12N855", 50.05, 45.25, 0.61], ["$12N855", 46.95, 43.3, 0.61], ["$12N877", 44.15, 49.05, 0.61], ["$14N655", 128.5, 20.2, 0.61], ["$14N655", 127.1, 18.8, 0.61], ["$14N655", 124.984, 20.701, 0.61], ["$14N663", 138.15, 18.5, 0.61], ["$14N663", 130.625, 26.3, 0.61], ["$14N664", 133.2, 26.6, 0.61], ["$14N664", 137.517, 20.701, 0.61], ["$14N698", 123.675, 49.075, 0.61], ["$14N698", 137.125, 41.6, 0.61], ["$14N698", 137.725, 42.8, 0.61], ["$16N18", 63.05, 70.2, 0.61], ["$16N18", 64, 72.85, 0.61], ["$16N18", 67.701, 78.001, 0.61], ["$1N244", 22.05, 116.75, 0.61], ["$1N244", 14.933, 100.501, 0.61], ["$1N263", 17.1, 98, 0.61], ["$1N263", 15.6, 96.6, 0.61], ["$1N266", 24.15, 92, 0.61], ["$1N266", 16.25, 93.3, 0.61], ["$2N655", 17.5, 20.6, 0.61], ["$2N655", 15.6, 18.7, 0.61], ["$2N655", 13.783, 20.701, 0.61], ["$2N657", 20.9, 22, 0.61], ["$2N657", 17.7, 25, 0.61], ["$2N663", 25.675, 19.65, 0.61], ["$2N663", 19.425, 26.3, 0.61], ["$2N664", 21, 26.85, 0.61], ["$2N664", 26.316, 20.701, 0.61], ["$2N698", 12.475, 49.075, 0.61], ["$2N699", 13.8, 47.4, 0.61], ["$2N699", 16.1, 49.8, 0.61], ["$2N699", 23.4, 48.4, 0.61], ["$2N699", 25.1, 46.8, 0.61], ["$3N172", 94.575, 13.75, 0.61], ["$3N172", 98.101, 15.197, 0.61], ["$8N653", 41.8, 105.7, 0.61], ["$8N653", 52, 95.5, 0.61], ["$8N655", 50.4, 105.1, 0.61], ["$8N655", 52, 106.7, 0.61], ["$8N655", 54.1, 105.6, 0.61], ["$8N657", 47.2, 103.7, 0.61], ["$8N657", 50.1, 100.6, 0.61], ["$8N659", 47.2, 107, 0.61], ["$8N659", 48.7, 106.9, 0.61], ["$8N663", 40.95, 107, 0.61], ["$8N663", 48.475, 99.2, 0.61], ["$8N664", 45, 101.4, 0.61], ["$8N664", 41.573, 104.8, 0.61], ["$8N676", 49.3, 80.2, 0.61], ["$8N676", 52.6, 82.3, 0.61], ["$8N699", 56.6, 85.3, 0.61], ["$8N699", 47.5, 86.9, 0.61], ["+3V3", 51.8, 75.2, 0.61], ["+3V3", 55.3, 76.9, 0.61], ["+5V", 62.7, 48.6, 0.61], ["+5V", 64.9, 50.8, 0.61], ["+5V", 61.7, 67.9, 0.61], ["+5V", 73.299, 78.001, 0.61], ["BLD_A", 20.5, 113.9, 0.61], ["BLD_A", 13.75, 95.8, 0.61], ["BLD_REF", 17.85, 117.7, 0.61], ["BLD_REF", 16.55, 103.7, 0.61], ["EFUSE_EN5", 133.4, 41.65, 0.61], ["EFUSE_EN5", 132.8, 44.9, 0.61], ["EFUSE_EN5", 126.1, 42.6, 0.61], ["EFUSE_EN5", 96, 23.1, 0.61], ["EFUSE_FLT1", 23.3, 43.5, 0.61], ["EFUSE_FLT1", 17.4, 47, 0.61], ["EFUSE_FLT3", 139, 77.6, 0.61], ["EFUSE_FLT3", 146.3, 76.5, 0.61], ["EFUSE_FLT3", 148.5, 76.5, 0.61], ["EFUSE_FLT3", 140.7, 42.2, 0.61], ["EFUSE_FLT3", 134.1, 38.8, 0.61], ["EFUSE_FLT3", 120, 36.4, 0.61], ["EFUSE_FLT3", 75.8, 48.1, 0.61], ["EFUSE_FLT5", 131, 44.6, 0.61], ["EFUSE_FLT5", 128.6, 47, 0.61], ["EFUSE_FLT5", 134.35, 42.95, 0.61], ["EFUSE_FLT5", 134.25, 41.5, 0.61], ["EFUSE_FLT5", 132.9, 40.2, 0.61], ["EFUSE_FLT5", 123.3, 39.85, 0.61], ["EFUSE_FLT5", 88.6, 44.15, 0.61], ["EFUSE_FLT5", 87.3, 42.85, 0.61], ["EFUSE_FLT5", 78.65, 42.15, 0.61], ["EFUSE_FLT5", 78.1, 43.45, 0.61], ["EFUSE_FLT5", 76.55, 43.15, 0.61], ["EFUSE_FLT5", 75.05, 48.55, 0.61], ["EFUSE_PG1", 22.2, 48.4, 0.61], ["EFUSE_PG1", 25.284, 45.499, 0.61], ["EFUSE_PG2", 50.2, 75.2, 0.61], ["EFUSE_PG2", 41.5, 75.3, 0.61], ["EFUSE_PG2", 39.3, 74.2, 0.61], ["EFUSE_PG2", 37.2, 74.3, 0.61], ["EFUSE_PG2", 39.5, 78.4, 0.61], ["EFUSE_PG2", 42.605, 80, 0.61], ["EFUSE_PG3", 132.5, 76.35, 0.61], ["EFUSE_PG3", 130.984, 80, 0.61], ["EFUSE_PG4", 53.2, 44.05, 0.61], ["EFUSE_PG4", 56.6, 44.75, 0.61], ["EFUSE_PG5", 130.4, 48.4, 0.61], ["EFUSE_PG5", 135.6, 45.1, 0.61], ["FB3V3", 17.5, 116, 0.61], ["FB3V3", 22.7, 116, 0.61], ["FB3V3", 15.9, 110.1, 0.61], ["FB3V3", 15.9, 105.85, 0.61], ["INA_ALERT", 114.1, 51.5, 0.61], ["INA_ALERT", 120.3, 57.7, 0.61], ["NTC1", 80.6, 13.8, 0.61], ["NTC1", 63.8, 28.3, 0.61], ["NTC1", 60.6, 28.7, 0.61], ["NTC1", 70.8, 35.248, 0.61], ["NTC2", 74.3, 21.7, 0.61], ["NTC2", 70.8, 25.248, 0.61], ["SCL", 126.8, 49.3, 0.61], ["SCL", 95.9, 33.3, 0.61], ["SCL", 47.9, 49.85, 0.61], ["SCL", 7.4, 95.2, 0.61], ["SDA", 108.9, 31.1, 0.61], ["SDA", 87.354, 28.474, 0.61], ["SDA", 86.096, 27.094, 0.61], ["SDA", 6.8, 98.25, 0.61], ["VBUS_EN3", 91.3, 22.9, 0.61], ["VBUS_EN3", 100.5, 19.1, 0.61], ["VBUS_EN3", 146.7, 39.3, 0.61], ["VBUS_EN3", 152.8, 74.5, 0.61], ["VBUS_EN3", 151.8, 66, 0.61], ["VO1", 20.1, 29.95, 0.61], ["VO1", 23.2, 26.85, 0.61], ["VO2", 53.4, 92.65, 0.61], ["VO2", 56.15, 92.65, 0.61], ["VO3", 141, 93.45, 0.61], ["VO3", 145.985, 107, 0.61], ["VO5", 125, 44.4, 0.61], ["VO5", 129.485, 47.5, 0.61], ["VO5", 125.7, 32.85, 0.61], ["VO5", 122.9, 32.85, 0.61], ["$12N834", 46.9, 18.2, 0.61], ["$12N834", 45.3, 19.8, 0.61], ["$12N836", 47.6, 17.65, 0.61], ["$12N836", 44.45, 19.85, 0.61], ["$12N836", 47.05, 24.05, 0.61], ["$12N836", 48.45, 24.35, 0.61], ["$14N653", 137.7, 19.8, 0.61], ["$14N653", 127.1, 30, 0.61], ["$14N657", 131.7, 21, 0.61], ["$14N657", 126.5, 22.5, 0.61], ["$14N657", 126.5, 23.9, 0.61], ["$14N657", 128.5, 24.7, 0.61], ["$14N699", 122.15, 45.6, 0.61], ["$14N699", 121.2, 44.65, 0.61], ["$14N699", 123.4, 41.95, 0.61], ["$14N699", 131.05, 41.9, 0.61], ["+3V3", 55.25, 76.275, 0.61], ["+3V3", 51.925, 75.825, 0.61], ["EFUSE_EN3", 149.5, 52.1, 0.61], ["EFUSE_EN3", 144.3, 42.4, 0.61], ["EFUSE_EN3", 140.5, 38.6, 0.61], ["EFUSE_EN3", 134.9, 37, 0.61], ["EFUSE_EN3", 121.6, 34.3, 0.61], ["EFUSE_EN3", 115, 32.4, 0.61], ["EFUSE_EN3", 96.9, 15.8, 0.61], ["INA_ALERT", 34.9, 69.8, 0.61], ["INA_ALERT", 11.2, 70.8, 0.61], ["INA_ALERT", 11.2, 78.1, 0.61], ["INA_ALERT", 7.1, 94.3, 0.61], ["SCL", 102.1, 24.2, 0.61], ["SCL", 103.3, 25.4, 0.61], ["SCL", 109.6, 33.1, 0.61], ["SDA", 140, 75.4, 0.61], ["VDAC5", 126.434, 21.271, 0.61], ["VDAC5", 116.7, 29.5, 0.61], ["SCL", 114.9, 37.2, 0.61], ["SDA", 34.1, 65.8, 0.61], ["SDA", 51.3, 77.3, 0.61], ["SDA", 102.5, 30.7, 0.61], ["SDA", 102.5, 38.1, 0.61], ["SDA", 102.5, 49, 0.61], ["SDA", 102.5, 56.9, 0.61], ["GND", 14.8, 5, 0.61], ["GND", 38.5, 5, 0.61], ["GND", 62.2, 5, 0.61], ["GND", 110.3, 5, 0.61], ["GND", 129, 5, 0.61], ["GND", 147.7, 5, 0.61], ["$10N732", 135.1, 75.5, 0.61], ["$10N732", 133.85, 76.8, 0.61], ["$10N732", 127.85, 73.35, 0.61], ["$10N732", 127.85, 69.25, 0.61], ["$12N878", 43.85, 39.65, 0.61], ["$12N878", 49.45, 34.4, 0.61], ["$12N878", 51.35, 34.4, 0.61], ["$12N878", 65.3, 39.65, 0.61], ["$12N878", 64, 41.85, 0.61], ["$12N878", 60.1, 42.15, 0.61], ["$2N653", 25.7, 18.65, 0.61], ["$2N653", 9.65, 31.15, 0.61], ["$2N653", 8.85, 32.3, 0.61], ["$2N653", 10.4, 33.85, 0.61], ["$2N653", 11.75, 32.75, 0.61], ["$2N653", 15.85, 30, 0.61], ["$2N676", 20.375, 47.15, 0.61], ["$2N676", 21.275, 46.05, 0.61], ["$2N676", 28.95, 43.95, 0.61], ["$2N676", 28.95, 40.7, 0.61], ["$2N676", 17.7, 39.15, 0.61], ["$2N698", 18.9, 44.4, 0.61], ["$2N732", 28.2, 56.8, 0.61], ["$2N732", 28.2, 58.2, 0.61], ["$8N687", 49.1, 81.1, 0.61], ["$8N687", 46.4, 79, 0.61], ["+3V3", 131.5, 80.7, 0.61], ["+3V3", 123.25, 71.6, 0.61], ["+3V3", 125.15, 71.6, 0.61], ["+3V3", 131.9, 75.15, 0.61], ["+3V3", 134.225, 75.125, 0.61], ["+3V3", 137.675, 75.125, 0.61], ["+3V3", 137.1, 75.5, 0.61], ["+3V3", 143.35, 77.1, 0.61], ["+5V", 86.3, 68.2, 0.61], ["+5V", 91.9, 65.2, 0.61], ["+5V", 93.4, 63.7, 0.61], ["+5V", 101, 63.7, 0.61], ["EFUSE_EN3", 141.5, 82.525, 0.61], ["EFUSE_EN3", 138.6, 76.075, 0.61], ["EFUSE_EN3", 134.75, 76.85, 0.61], ["EFUSE_EN3", 135.7, 82.95, 0.61], ["EFUSE_EN3", 137.7, 84.825, 0.61], ["EFUSE_EN3", 139.975, 88.325, 0.61], ["EFUSE_EN3", 138.55, 92.425, 0.61], ["EFUSE_EN3", 145.6, 84.5, 0.61], ["EFUSE_EN3", 145.575, 80.775, 0.61], ["EFUSE_EN3", 145.7, 81.4, 0.61], ["EFUSE_EN3", 145.7, 85.9, 0.61], ["EFUSE_EN3", 132.8, 92.8, 0.61], ["EFUSE_EN3", 123, 96.1, 0.61], ["EFUSE_EN3", 102, 100.4, 0.61], ["EFUSE_EN3", 99, 101.2, 0.61], ["EFUSE_EN3", 89.5, 91.4, 0.61], ["EFUSE_EN3", 90.2, 75.7, 0.61], ["EFUSE_EN3", 93.9, 72, 0.61], ["EFUSE_EN3", 95.4, 70.5, 0.61], ["EFUSE_EN3", 97.6, 70.5, 0.61], ["EFUSE_EN3", 103.5, 67.6, 0.61], ["EFUSE_EN3", 113.6, 73, 0.61], ["EFUSE_EN3", 131, 78.1, 0.61], ["EFUSE_EN3", 131, 78.9, 0.61], ["EFUSE_EN3", 133.2, 75.4, 0.61], ["EFUSE_FLT1", 24.1, 43.5, 0.61], ["EFUSE_FLT1", 41.7, 43.3, 0.61], ["EFUSE_FLT1", 43.8, 41.2, 0.61], ["EFUSE_FLT1", 57.5, 39.7, 0.61], ["EFUSE_FLT1", 72.6, 43.1, 0.61], ["EFUSE_FLT1", 74.7, 45.3, 0.61], ["EFUSE_PG3", 104.4, 65.8, 0.61], ["EFUSE_PG3", 95.1, 62.5, 0.61], ["EFUSE_PG3", 91.8, 62.5, 0.61], ["INA_ALERT", 133.25, 49.85, 0.61], ["INA_ALERT", 138.45, 49.85, 0.61], ["INA_ALERT", 147.95, 59.75, 0.61], ["INA_ALERT", 143.75, 75.15, 0.61], ["INA_ALERT", 148, 74.8, 0.61], ["INA_ALERT", 145, 87.7, 0.61], ["INA_ALERT", 129.5, 95, 0.61], ["INA_ALERT", 103.7, 99.7, 0.61], ["INA_ALERT", 100.4, 99.7, 0.61], ["INA_ALERT", 99, 99.8, 0.61], ["INA_ALERT", 68.8, 87.5, 0.61], ["INA_ALERT", 62.1, 80.8, 0.61], ["INA_ALERT", 59.7, 78.4, 0.61], ["INA_ALERT", 58.6, 77.3, 0.61], ["VO1", 13.8, 44.4, 0.61], ["VO1", 17.9, 47.8, 0.61], ["VO2", 46.775, 83.175, 0.61], ["VO2", 48.975, 78.25, 0.61], ["VO3", 137.425, 83.575, 0.61], ["VO3", 137.775, 78.325, 0.61], ["$12N832", 57.4, 19.7, 0.61], ["$12N832", 47.7, 30.2, 0.61], ["$12N855", 51.4, 47.3, 0.61], ["+3V3", 77.425, 45.25, 0.61], ["+3V3", 76.875, 50.825, 0.61], ["BUCK_PG", 65.5, 47.6, 0.61], ["BUCK_PG", 64.4, 48.7, 0.61], ["BUCK_PG", 65.8, 51.7, 0.61], ["BUCK_PG", 65.8, 62.7, 0.61], ["BUCK_PG", 51.2, 35.3, 0.61], ["BUCK_PG", 50.9, 33.6, 0.61], ["BUCK_PG", 46.3, 30.7, 0.61], ["BUCK_PG", 17.7, 30, 0.61], ["EFUSE_EN1", 29.7, 40.1, 0.61], ["EFUSE_EN1", 58.3, 29.8, 0.61], ["EFUSE_EN2", 53.15, 83.95, 0.61], ["EFUSE_EN2", 43.7, 79.05, 0.61], ["EFUSE_EN2", 58.6, 81, 0.61], ["EFUSE_EN2", 69.3, 75.2, 0.61], ["EFUSE_EN2", 69.1, 51.2, 0.61], ["EFUSE_EN2", 70.5, 44.5, 0.61], ["EFUSE_EN2", 82.286, 27.094, 0.61], ["EFUSE_EN4", 52.95, 37.3, 0.61], ["EFUSE_EN4", 54.5, 35.75, 0.61], ["EFUSE_PG1", 49.05, 47.55, 0.61], ["EFUSE_PG1", 49.45, 49.25, 0.61], ["EFUSE_PG1", 64.05, 60.4, 0.61], ["EFUSE_PG1", 70.85, 60.4, 0.61], ["EFUSE_PG1", 80.075, 53.779, 0.61], ["EFUSE_PG4", 67.5, 50.7, 0.61], ["EFUSE_PG4", 74.7, 54.4, 0.61], ["EFUSE_PG5", 135.9, 39.5, 0.61], ["EFUSE_PG5", 134.3, 37.9, 0.61], ["EFUSE_PG5", 123, 35.7, 0.61], ["EFUSE_PG5", 117.8, 40.9, 0.61], ["EFUSE_PG5", 103.4, 46, 0.61], ["EFUSE_PG5", 83.2, 47.1, 0.61], ["EFUSE_PG5", 79.3, 51, 0.61], ["IOEXP_INT#", 72.3, 44.5, 0.61], ["IOEXP_INT#", 71.9, 41.2, 0.61], ["IOEXP_INT#", 70.4, 38.3, 0.61], ["IOEXP_INT#", 79.251, 20.734, 0.61], ["SDA", 81.7, 35.3, 0.61], ["SDA", 82.8, 45.45, 0.61], ["SDA", 83.75, 46.4, 0.61], ["UP_VBUS_DET", 64.1, 25.1, 0.61], ["UP_VBUS_DET", 41.7, 39.4, 0.61], ["UP_VBUS_DET", 39.7, 44.7, 0.61], ["UP_VBUS_DET", 41.1, 46.1, 0.61], ["VBUS_EN1", 78.6, 18.2, 0.61], ["VBUS_EN1", 73.6, 19.6, 0.61], ["VBUS_EN1", 55.3, 25.3, 0.61], ["VBUS_EN1", 14.6, 34.5, 0.61], ["VBUS_EN1", 11.2, 67.1, 0.61], ["VBUS_EN4", 79.3, 15.9, 0.61], ["VBUS_EN4", 67, 28.7, 0.61], ["VBUS_EN4", 54.6, 36.8, 0.61], ["VBUS_EN4", 41.5, 40.8, 0.61], ["VDAC1", 15.3, 22.1, 0.61], ["VDAC1", 22.6, 21.6, 0.61], ["VDAC1", 33.2, 24.8, 0.61], ["VDAC1", 40.4, 30, 0.61], ["VDAC1", 50.9, 32.7, 0.61], ["VDAC1", 69.7, 37.3, 0.61], ["VDAC3", 141, 105.2, 0.61], ["VDAC3", 116.4, 77.4, 0.61], ["VDAC3", 101.8, 70.4, 0.61], ["VDAC3", 96.3, 64.9, 0.61], ["VDAC3", 95.5, 58.5, 0.61], ["VDAC4", 47.075, 21.275, 0.61], ["VO4", 45.5, 44.45, 0.61], ["VO4", 49.9, 47.25, 0.61], ["GND", 77.8, 35.4, 0.61], ["GND", 107.2, 32.8, 0.61], ["SDA", 81.6, 49.9, 0.61], ["EFUSE_EN1", 19.2, 40.65, 0.61], ["EFUSE_EN1", 15, 39.15, 0.61], ["EFUSE_FLT3", 115.6, 38.45, 0.61], ["EFUSE_FLT3", 106.35, 38.85, 0.61], ["EFUSE_FLT3", 82.65, 37.25, 0.61], ["SCL", 106.1, 33.8, 0.61], ["SCL", 104.6, 34, 0.61], ["SCL", 108.4, 42.9, 0.61], ["SCL", 115.7, 39.4, 0.61], ["VDAC3", 101.85, 43.25, 0.61], ["VDAC3", 110.8, 38.2, 0.61], ["VDAC3", 111.6, 35.6, 0.61], ["VDAC4", 54.7, 19.8, 0.61], ["VDAC4", 60.2, 17.15, 0.61], ["VDAC4", 74.95, 16.2, 0.61], ["VDAC4", 77.95, 16.2, 0.61], ["VDAC4", 78.3, 30.55, 0.61], ["VDAC4", 79.85, 34.65, 0.61], ["VDAC4", 81.75, 37.2, 0.61], ["SCL", 119.9, 42.1, 0.61], ["SCL", 72.9, 51.2, 0.61], ["SCL", 61.1, 50, 0.61], ["SCL", 48, 75.9, 0.61], ["SCL", 29.1, 58.4, 0.61], ["SCL", 6.8, 87.6, 0.61], ["SDA", 73.6, 54.4, 0.61], ["SDA", 67.8, 55.8, 0.61], ["SDA", 66.5, 54.9, 0.61], ["SDA", 60.9, 58.5, 0.61], ["SDA", 11.4, 87.6, 0.61], ["EFUSE_FLT2", 46.6, 84.05, 0.61], ["EFUSE_FLT2", 84.4, 45.8, 0.61], ["EFUSE_FLT2", 80.5, 44.15, 0.61], ["EFUSE_FLT2", 79.2, 42.85, 0.61], ["EFUSE_FLT2", 75.7, 43.05, 0.61], ["EFUSE_FLT2", 75, 44.45, 0.61], ["KEY_OE#", 84.8, 29.9, 0.61], ["KEY_OE#", 87.9, 40.1, 0.61], ["KEY_OE#", 89.2, 42.8, 0.61], ["KEY_OE#", 90.3, 58.6, 0.61], ["KEY_OE#", 90.7, 61.8, 0.61], ["KEY_OE#", 90.7, 63.7, 0.61], ["KEY_OE#", 100.5, 78.8, 0.61], ["KEY_OE#", 111.1, 71.6, 0.61], ["KEY_OE#", 114, 66.4, 0.61], ["KEY_RCLK", 93.9, 31.35, 0.61], ["KEY_RCLK", 93.9, 34.35, 0.61], ["KEY_RCLK", 95.2, 36.2, 0.61], ["KEY_RCLK", 98.35, 48.75, 0.61], ["KEY_RCLK", 99.55, 50.85, 0.61], ["KEY_RCLK", 108.45, 57.4, 0.61], ["KEY_RCLK", 111.15, 58.5, 0.61], ["KEY_SER", 88, 32.15, 0.61], ["KEY_SER", 88.55, 39.5, 0.61], ["KEY_SER", 91.65, 42.85, 0.61], ["KEY_SER", 97.4, 52.3, 0.61], ["KEY_SER", 103.15, 54, 0.61], ["KEY_SER", 108.6, 56.55, 0.61], ["KEY_SER", 109.9, 57.85, 0.61], ["KEY_SRCLK", 94.55, 36.8, 0.61], ["KEY_SRCLK", 98.25, 52.15, 0.61], ["KEY_SRCLK", 109.35, 59.25, 0.61], ["VBUS_EN2", 103.15, 50.85, 0.61], ["VBUS_EN2", 99.6, 47.75, 0.61], ["VBUS_EN2", 96.5, 34.9, 0.61], ["VBUS_EN5", 117.55, 54, 0.61], ["VBUS_EN5", 117.95, 41.75, 0.61], ["VBUS_EN5", 119.8, 39.85, 0.61], ["VBUS_EN5", 96.85, 20.65, 0.61], ["GND", 0.35, 71.814, 0.61], ["GND", 0.35, 72.464, 0.61], ["GND", 1, 71.814, 0.61], ["GND", 1, 72.464, 0.61], ["GND", 1.65, 71.814, 0.61], ["GND", 1.65, 72.464, 0.61], ["GND", 100.81, 13.326, 0.61], ["GND", 80.726, 41.326, 0.61], ["GND", 81.617, 41.075, 0.61], ["GND", 77.592, 34.395, 0.61], ["GND", 107.324, 31.726, 0.61], ["GND", 109.759, 39.457, 0.61], ["+3V3", 108.919, 39.457, 0.61]], "line": [["GND", 1, 32.155, 80, 32.975, 80, 0.3], ["GND", 1, 32.155, 83, 32.975, 83, 0.3], ["GND", 1, 31.12, 86, 31.789, 86, 0.3], ["GND", 1, 18.565, 109.124, 18.565, 109.863, 0.3], ["GND", 1, 18.1, 112.5, 19.047, 112.5, 0.3], ["GND", 1, 23.6, 112.5, 24.547, 112.5, 0.3], ["GND", 1, 11.62, 99, 12.289, 99, 0.3], ["GND", 1, 12.924, 27.8, 13.775, 27.8, 0.3], ["GND", 1, 12.924, 31.45, 13.775, 31.45, 0.3], ["GND", 1, 12.924, 22.2, 13.775, 22.2, 0.3], ["GND", 1, 21.52, 24.92, 22.168, 24.92, 0.3], ["GND", 1, 17.378, 42.6, 18.32, 42.6, 0.3], ["GND", 1, 17.378, 40.5, 18.325, 40.5, 0.3], ["GND", 1, 17.32, 38, 17.989, 38, 0.3], ["GND", 1, 28.92, 18.5, 29.588, 18.5, 0.3], ["GND", 1, 22.69, 18.5, 23.324, 18.5, 0.3], ["GND", 1, 22.42, 20.7, 23.089, 20.7, 0.3], ["GND", 1, 18.92, 20.7, 19.588, 20.7, 0.3], ["GND", 1, 19.42, 51.8, 20.089, 51.8, 0.3], ["GND", 1, 23.69, 47.5, 24.324, 47.5, 0.3], ["GND", 1, 54.965, 97.7, 54.114, 97.7, 0.3], ["GND", 1, 54.965, 94.05, 54.114, 94.05, 0.3], ["GND", 1, 54.965, 103.3, 54.114, 103.3, 0.3], ["GND", 1, 46.809, 100.58, 47.457, 100.58, 0.3], ["GND", 1, 50.51, 82.9, 49.569, 82.9, 0.3], ["GND", 1, 51.896, 85, 52.843, 85, 0.3], ["GND", 1, 50.769, 87.72, 50.769, 88.368, 0.3], ["GND", 1, 39.169, 107.221, 39.169, 107.869, 0.3], ["GND", 1, 45.544, 107.221, 45.544, 107.979, 0.3], ["GND", 1, 45.669, 105.02, 45.669, 105.668, 0.3], ["GND", 1, 49.169, 105.02, 49.169, 105.668, 0.3], ["GND", 1, 48.669, 73.92, 48.669, 74.568, 0.3], ["GND", 1, 44.544, 78.221, 44.544, 78.979, 0.3], ["GND", 1, 143.345, 97.7, 142.494, 97.7, 0.3], ["GND", 1, 143.345, 94.05, 142.494, 94.05, 0.3], ["GND", 1, 143.345, 103.3, 142.494, 103.3, 0.3], ["GND", 1, 135.189, 100.58, 135.837, 100.58, 0.3], ["GND", 1, 138.89, 82.9, 137.949, 82.9, 0.3], ["GND", 1, 140.276, 85, 141.223, 85, 0.3], ["GND", 1, 139.149, 87.72, 139.149, 88.368, 0.3], ["GND", 1, 127.549, 107.221, 127.549, 107.869, 0.3], ["GND", 1, 133.924, 107.221, 133.924, 107.979, 0.3], ["GND", 1, 134.049, 105.02, 134.049, 105.668, 0.3], ["GND", 1, 137.549, 105.02, 137.549, 105.668, 0.3], ["GND", 1, 137.049, 73.92, 137.049, 74.568, 0.3], ["GND", 1, 132.924, 78.221, 132.924, 78.979, 0.3], ["GND", 1, 44.593, 27.8, 45.444, 27.8, 0.3], ["GND", 1, 44.593, 31.45, 45.444, 31.45, 0.3], ["GND", 1, 44.593, 22.2, 45.444, 22.2, 0.3], ["GND", 1, 53.189, 24.92, 53.837, 24.92, 0.3], ["GND", 1, 49.047, 42.6, 49.989, 42.6, 0.3], ["GND", 1, 49.047, 40.5, 49.994, 40.5, 0.3], ["GND", 1, 48.989, 38, 49.658, 38, 0.3], ["GND", 1, 60.589, 18.5, 61.258, 18.5, 0.3], ["GND", 1, 54.359, 18.5, 54.993, 18.5, 0.3], ["GND", 1, 54.089, 20.7, 54.758, 20.7, 0.3], ["GND", 1, 50.589, 20.7, 51.257, 20.7, 0.3], ["GND", 1, 51.089, 51.8, 51.758, 51.8, 0.3], ["GND", 1, 55.359, 47.5, 55.993, 47.5, 0.3], ["GND", 1, 124.124, 27.8, 124.975, 27.8, 0.3], ["GND", 1, 124.124, 31.45, 124.975, 31.45, 0.3], ["GND", 1, 124.124, 22.2, 124.975, 22.2, 0.3], ["GND", 1, 132.721, 24.92, 133.369, 24.92, 0.3], ["GND", 1, 128.579, 42.6, 129.52, 42.6, 0.3], ["GND", 1, 128.579, 40.5, 129.525, 40.5, 0.3], ["GND", 1, 128.52, 38, 129.189, 38, 0.3], ["GND", 1, 140.12, 18.5, 140.789, 18.5, 0.3], ["GND", 1, 133.89, 18.5, 134.524, 18.5, 0.3], ["GND", 1, 133.62, 20.7, 134.289, 20.7, 0.3], ["GND", 1, 130.12, 20.7, 130.789, 20.7, 0.3], ["GND", 1, 130.62, 51.8, 131.289, 51.8, 0.3], ["GND", 1, 134.89, 47.5, 135.524, 47.5, 0.3], ["GND", 1, 100.465, 12.167, 101.29, 12.167, 0.3], ["GND", 1, 98.151, 9.954, 98.151, 9.285, 0.3], ["GND", 1, 98.382, 12.977, 99.703, 13.416, 0.3], ["GND", 1, 96.322, 56.681, 96.991, 56.681, 0.3], ["GND", 1, 96.912, 42.322, 97.581, 42.322, 0.3], ["GND", 1, 72.137, 53.413, 72.137, 54.081, 0.3], ["GND", 1, 80.124, 40.496, 80.793, 40.496, 0.3], ["GND", 1, 83.153, 40.511, 84.004, 40.511, 0.3], ["GND", 1, 110.112, 37.194, 110.781, 37.194, 0.3], ["GND", 1, 113.144, 37.21, 113.995, 37.21, 0.3], ["GND", 1, 77.865, 13.264, 77.865, 13.933, 0.3], ["GND", 1, 23.52, 52.225, 23.52, 52.963, 0.3], ["GND", 1, 23.55, 55.95, 24.197, 55.95, 0.3], ["GND", 1, 33.75, 28.45, 34.397, 28.45, 0.3], ["GND", 1, 37.75, 28.45, 38.397, 28.45, 0.3], ["GND", 1, 33.75, 32.45, 34.397, 32.45, 0.3], ["GND", 1, 45.24, 73.55, 45.886, 73.55, 0.3], ["GND", 1, 45.24, 69.55, 45.886, 69.55, 0.3], ["GND", 1, 35.039, 97.05, 35.686, 97.05, 0.3], ["GND", 1, 31.039, 97.05, 31.686, 97.05, 0.3], ["GND", 1, 35.039, 93.05, 35.686, 93.05, 0.3], ["GND", 1, 133.619, 73.55, 134.266, 73.55, 0.3], ["GND", 1, 133.619, 69.55, 134.266, 69.55, 0.3], ["GND", 1, 123.419, 97.05, 124.066, 97.05, 0.3], ["GND", 1, 119.419, 97.05, 120.066, 97.05, 0.3], ["GND", 1, 123.419, 93.05, 124.066, 93.05, 0.3], ["GND", 1, 55.189, 52.225, 55.189, 52.963, 0.3], ["GND", 1, 55.219, 55.95, 55.866, 55.95, 0.3], ["GND", 1, 65.419, 28.45, 66.066, 28.45, 0.3], ["GND", 1, 69.419, 28.45, 70.066, 28.45, 0.3], ["GND", 1, 65.419, 32.45, 66.066, 32.45, 0.3], ["GND", 1, 134.72, 52.225, 134.72, 52.963, 0.3], ["GND", 1, 134.75, 55.95, 135.397, 55.95, 0.3], ["GND", 1, 144.95, 28.45, 145.597, 28.45, 0.3], ["GND", 1, 148.95, 28.45, 149.597, 28.45, 0.3], ["GND", 1, 144.95, 32.45, 145.597, 32.45, 0.3], ["GND", 1, 27.334, 71.5, 26.675, 71.5, 0.3], ["GND", 1, 20.567, 116.221, 20.567, 116.892, 0.3], ["GND", 1, 20.567, 118.72, 20.567, 119.391, 0.3], ["GND", 1, 11.966, 20.7, 12.624, 20.7, 0.3], ["GND", 1, 24.867, 18.721, 24.867, 19.392, 0.3], ["GND", 1, 28.966, 20.7, 29.624, 20.7, 0.3], ["GND", 1, 19.966, 45.5, 20.624, 45.5, 0.3], ["GND", 1, 19.966, 43.5, 20.624, 43.5, 0.3], ["GND", 1, 22.367, 45.721, 22.367, 46.392, 0.3], ["GND", 1, 26.966, 47.5, 27.624, 47.5, 0.3], ["GND", 1, 26.966, 41.5, 27.624, 41.5, 0.3], ["GND", 1, 32.966, 35, 33.624, 35, 0.3], ["GND", 1, 32.966, 38, 33.624, 38, 0.3], ["GND", 1, 32.966, 41, 33.624, 41, 0.3], ["GND", 1, 55.923, 104.8, 55.265, 104.8, 0.3], ["GND", 1, 43.255, 107, 43.913, 107, 0.3], ["GND", 1, 39.156, 105.02, 39.156, 105.691, 0.3], ["GND", 1, 48.156, 80.221, 48.156, 80.892, 0.3], ["GND", 1, 48.156, 82.221, 48.156, 82.892, 0.3], ["GND", 1, 45.755, 80, 46.414, 80, 0.3], ["GND", 1, 41.156, 78.221, 41.156, 78.892, 0.3], ["GND", 1, 41.156, 84.221, 41.156, 84.892, 0.3], ["GND", 1, 35.156, 90.72, 35.156, 91.392, 0.3], ["GND", 1, 35.156, 87.72, 35.156, 88.392, 0.3], ["GND", 1, 35.156, 84.72, 35.156, 85.392, 0.3], ["GND", 1, 144.303, 104.8, 143.645, 104.8, 0.3], ["GND", 1, 131.635, 107, 132.293, 107, 0.3], ["GND", 1, 127.536, 105.02, 127.536, 105.691, 0.3], ["GND", 1, 136.536, 80.221, 136.536, 80.892, 0.3], ["GND", 1, 136.536, 82.221, 136.536, 82.892, 0.3], ["GND", 1, 134.135, 80, 134.794, 80, 0.3], ["GND", 1, 129.536, 78.221, 129.536, 78.892, 0.3], ["GND", 1, 129.536, 84.221, 129.536, 84.892, 0.3], ["GND", 1, 123.536, 90.72, 123.536, 91.392, 0.3], ["GND", 1, 123.536, 87.72, 123.536, 88.392, 0.3], ["GND", 1, 123.536, 84.72, 123.536, 85.392, 0.3], ["GND", 1, 43.635, 20.7, 44.293, 20.7, 0.3], ["GND", 1, 56.536, 18.721, 56.536, 19.392, 0.3], ["GND", 1, 60.635, 20.7, 61.293, 20.7, 0.3], ["GND", 1, 51.635, 45.5, 52.293, 45.5, 0.3], ["GND", 1, 51.635, 43.5, 52.293, 43.5, 0.3], ["GND", 1, 54.036, 45.721, 54.036, 46.392, 0.3], ["GND", 1, 58.635, 47.5, 59.293, 47.5, 0.3], ["GND", 1, 58.635, 41.5, 59.293, 41.5, 0.3], ["GND", 1, 64.635, 35, 65.293, 35, 0.3], ["GND", 1, 64.635, 38, 65.293, 38, 0.3], ["GND", 1, 64.635, 41, 65.293, 41, 0.3], ["GND", 1, 123.166, 20.7, 123.824, 20.7, 0.3], ["GND", 1, 136.067, 18.721, 136.067, 19.392, 0.3], ["GND", 1, 140.166, 20.7, 140.825, 20.7, 0.3], ["GND", 1, 131.166, 45.5, 131.825, 45.5, 0.3], ["GND", 1, 131.166, 43.5, 131.825, 43.5, 0.3], ["GND", 1, 133.567, 45.721, 133.567, 46.392, 0.3], ["GND", 1, 138.166, 47.5, 138.825, 47.5, 0.3], ["GND", 1, 138.166, 41.5, 138.825, 41.5, 0.3], ["GND", 1, 144.166, 35, 144.825, 35, 0.3], ["GND", 1, 144.166, 38, 144.825, 38, 0.3], ["GND", 1, 144.166, 41, 144.825, 41, 0.3], ["GND", 1, 150.703, 51.86, 150.703, 52.518, 0.3], ["GND", 1, 150.923, 54.86, 151.044, 55.45, 0.3], ["GND", 1, 77.991, 35.746, 77.883, 36.35, 0.3], ["GND", 1, 107.981, 32.446, 107.873, 33.049, 0.3], ["GND", 1, 71.182, 36.753, 71.891, 36.753, 0.3], ["GND", 1, 71.182, 26.753, 71.891, 26.753, 0.3], ["GND", 1, 15.075, 28.09, 15.075, 28.5, 0.3], ["GND", 1, 15.075, 28.5, 15.075, 29.174, 0.3], ["GND", 1, 14.725, 28.59, 14.222, 28.854, 0.3], ["GND", 1, 52.814, 97.41, 52.814, 97, 0.3], ["GND", 1, 52.814, 97, 52.814, 96.326, 0.3], ["GND", 1, 53.164, 96.91, 53.667, 96.647, 0.3], ["GND", 1, 141.194, 97.41, 141.194, 97, 0.3], ["GND", 1, 141.194, 97, 141.194, 96.326, 0.3], ["GND", 1, 141.544, 96.91, 142.048, 96.647, 0.3], ["GND", 1, 46.744, 28.09, 46.744, 28.5, 0.3], ["GND", 1, 46.744, 28.5, 46.744, 29.174, 0.3], ["GND", 1, 46.394, 28.59, 45.891, 28.854, 0.3], ["GND", 1, 126.275, 28.09, 126.275, 28.5, 0.3], ["GND", 1, 126.275, 28.5, 126.275, 29.174, 0.3], ["GND", 1, 125.925, 28.59, 125.422, 28.854, 0.3], ["GND", 1, 13.21, 50.196, 12.579, 50.196, 0.3], ["GND", 1, 13.8, 50.45, 13.8, 51.012, 0.3], ["GND", 1, 14.8, 54.67, 14.8, 55.232, 0.3], ["GND", 1, 54.679, 75.304, 55.31, 75.304, 0.3], ["GND", 1, 53.089, 72.35, 53.089, 72.912, 0.3], ["GND", 1, 142.469, 76.57, 142.469, 77.132, 0.3], ["GND", 1, 141.469, 72.35, 141.469, 72.912, 0.3], ["GND", 1, 46.469, 54.67, 46.469, 55.232, 0.3], ["GND", 1, 124.41, 50.196, 123.779, 50.196, 0.3], ["GND", 1, 126, 54.67, 126, 55.232, 0.3], ["GND", 1, 5.5, 97.65, 5.5, 98.212, 0.3], ["GND", 1, 7, 101.87, 7, 102.432, 0.3], ["GND", 1, 15.65, 44.3, 16.524, 44.3, 0.3], ["GND", 1, 15.65, 47.3, 16.524, 47.3, 0.3], ["GND", 1, 52.239, 81.2, 51.365, 81.2, 0.3], ["GND", 1, 52.239, 78.2, 51.365, 78.2, 0.3], ["GND", 1, 140.619, 81.2, 139.745, 81.2, 0.3], ["GND", 1, 140.619, 78.2, 139.745, 78.2, 0.3], ["GND", 1, 47.319, 44.3, 48.193, 44.3, 0.3], ["GND", 1, 47.319, 47.3, 48.193, 47.3, 0.3], ["GND", 1, 126.85, 44.3, 127.724, 44.3, 0.3], ["GND", 1, 126.85, 47.3, 127.724, 47.3, 0.3], ["GND", 1, 20.85, 103.05, 21.476, 103.05, 0.3], ["GND", 1, 96.05, 9.305, 95.375, 9.305, 0.3], ["GND", 1, 79.951, 9.305, 80.625, 9.305, 0.3], ["GND", 1, 88.5, 18.825, 88.535, 19.475, 0.3], ["GND", 1, 89.9, 18.825, 89.935, 19.475, 0.3], ["GND", 1, 91.3, 18.425, 92.036, 18.425, 0.3], ["GND", 1, 91.3, 15.625, 92.036, 15.625, 0.3], ["GND", 1, 89.101, 15.226, 89.066, 14.576, 0.3], ["GND", 1, 87.701, 16.025, 87.051, 16.06, 0.3], ["GND", 1, 87.701, 17.425, 87.051, 17.46, 0.3], ["GND", 1, 91.3, 17.025, 92.036, 17.025, 0.3], ["GND", 1, 89.9, 16.626, 90.49, 14.636, 0.3], ["GND", 1, 96.946, 49.634, 98.225, 49.634, 0.3], ["GND", 1, 97.536, 35.275, 98.815, 35.275, 0.3], ["GND", 1, 74.225, 47.383, 74.225, 47.957, 0.3], ["GND", 1, 73.575, 45.832, 73.575, 45.258, 0.3], ["GND", 1, 80.224, 46.608, 81.424, 46.608, 0.3], ["GND", 1, 79.425, 47.383, 79.425, 47.957, 0.3], ["GND", 1, 75.525, 53.428, 75.525, 54.002, 0.3], ["GND", 1, 74.875, 51.877, 74.875, 51.303, 0.3], ["GND", 1, 76.175, 51.877, 76.175, 51.303, 0.3], ["GND", 1, 76.825, 53.428, 76.825, 54.002, 0.3], ["GND", 1, 11.951, 94, 12.597, 94, 0.3], ["GND", 1, 67.576, 71.565, 66.837, 71.565, 0.3], ["GND", 1, 71.324, 71, 72.175, 71, 0.3], ["GND", 1, 78.127, 80.286, 78.127, 81.107, 0.3], ["GND", 1, 80.814, 79.593, 81.639, 79.593, 0.3], ["GND", 1, 59.567, 71.72, 59.567, 72.392, 0.3], ["GND", 1, 64.85, 71.05, 64.224, 71.05, 0.3], ["GND", 1, 96.696, 68.265, 97.975, 68.265, 0.3], ["GND", 1, 104.286, 74, 105.232, 74, 0.3], ["GND", 1, 105.666, 78, 106.324, 78, 0.3], ["GND", 1, 107.62, 74, 108.289, 74, 0.3], ["GND", 1, 103.45, 70.45, 104.097, 70.45, 0.3], ["GND", 1, 77.652, 11.037, 77.033, 11.012, 0.3], ["GND", 1, 151.676, 48.589, 150.728, 48.589, 0.3], ["GND", 1, 151.676, 55.498, 150.236, 55.498, 0.3], ["GND", 1, 79.83, 39.16, 79.83, 38.71, 0.3], ["GND", 1, 109.82, 35.86, 109.82, 35.41, 0.3], ["+12V", 1, 20.655, 108.5, 21.475, 108.5, 1], ["+12V", 1, 20.655, 109.124, 21.043, 109.543, 1], ["+12V", 1, 20, 109.124, 20, 109.975, 1], ["+12V", 1, 12.924, 25.8, 13.775, 25.8, 1], ["+12V", 1, 11.676, 26.365, 10.937, 26.365, 1], ["+12V", 1, 11.676, 25.235, 10.937, 25.235, 1], ["+12V", 1, 12.924, 30.015, 13.663, 30.015, 1], ["+12V", 1, 11.676, 30.015, 10.937, 30.015, 1], ["+12V", 1, 11.676, 29.45, 10.324, 29.45, 1], ["+12V", 1, 12.924, 24.2, 13.775, 24.2, 1], ["+12V", 1, 11.676, 24.2, 10.824, 24.2, 1], ["+12V", 1, 12.924, 24.855, 14.125, 24.956, 1], ["+12V", 1, 21.52, 24.08, 22.168, 24.08, 0.45], ["+12V", 1, 54.965, 100.265, 54.226, 100.265, 1], ["+12V", 1, 54.965, 99.135, 54.226, 99.135, 1], ["+12V", 1, 54.965, 95.485, 54.226, 95.485, 1], ["+12V", 1, 56.213, 96.05, 57.064, 96.05, 1], ["+12V", 1, 57.064, 96.05, 57.864, 96.05, 1], ["+12V", 1, 56.213, 101.3, 57.064, 101.3, 1], ["+12V", 1, 54.965, 101.865, 54.226, 101.865, 1], ["+12V", 1, 54.965, 101.3, 53.613, 101.3, 1], ["+12V", 1, 46.809, 101.42, 47.457, 101.42, 0.45], ["+12V", 1, 143.345, 100.265, 142.606, 100.265, 1], ["+12V", 1, 143.345, 99.135, 142.606, 99.135, 1], ["+12V", 1, 143.345, 95.485, 142.606, 95.485, 1], ["+12V", 1, 144.593, 96.05, 145.444, 96.05, 1], ["+12V", 1, 145.444, 96.05, 146.244, 96.05, 1], ["+12V", 1, 144.593, 101.3, 145.444, 101.3, 1], ["+12V", 1, 143.345, 101.865, 142.606, 101.865, 1], ["+12V", 1, 143.345, 101.3, 141.993, 101.3, 1], ["+12V", 1, 135.189, 101.42, 135.837, 101.42, 0.45], ["+12V", 1, 44.593, 25.8, 45.444, 25.8, 1], ["+12V", 1, 43.345, 26.365, 42.606, 26.365, 1], ["+12V", 1, 43.345, 25.235, 42.606, 25.235, 1], ["+12V", 1, 44.593, 30.015, 45.332, 30.015, 1], ["+12V", 1, 43.345, 30.015, 42.606, 30.015, 1], ["+12V", 1, 43.345, 29.45, 41.993, 29.45, 1], ["+12V", 1, 44.593, 24.2, 45.444, 24.2, 1], ["+12V", 1, 43.345, 24.2, 42.493, 24.2, 1], ["+12V", 1, 44.593, 24.855, 45.794, 24.956, 1], ["+12V", 1, 53.189, 24.08, 53.837, 24.08, 0.45], ["+12V", 1, 124.124, 25.8, 124.975, 25.8, 1], ["+12V", 1, 122.876, 26.365, 122.137, 26.365, 1], ["+12V", 1, 122.876, 25.235, 122.137, 25.235, 1], ["+12V", 1, 124.124, 30.015, 124.863, 30.015, 1], ["+12V", 1, 122.876, 30.015, 122.137, 30.015, 1], ["+12V", 1, 122.876, 29.45, 121.524, 29.45, 1], ["+12V", 1, 124.124, 24.2, 124.975, 24.2, 1], ["+12V", 1, 122.876, 24.2, 122.024, 24.2, 1], ["+12V", 1, 124.124, 24.855, 125.325, 24.956, 1], ["+12V", 1, 132.721, 24.08, 133.369, 24.08, 0.45], ["+12V", 1, 23.595, 117.199, 23.595, 117.789, 0.517], ["+12V", 1, 24.865, 117.199, 24.865, 117.789, 0.517], ["+12V", 1, 26.135, 117.199, 26.135, 117.789, 0.517], ["+12V", 1, 18.666, 118.5, 19.324, 118.5, 0.487], ["+12V", 1, 18.666, 121, 19.324, 121, 0.487], ["+12V", 1, 24.867, 20.921, 24.867, 21.592, 0.487], ["+12V", 1, 43.255, 104.8, 43.913, 104.8, 0.487], ["+12V", 1, 131.635, 104.8, 132.293, 104.8, 0.487], ["+12V", 1, 56.536, 20.921, 56.536, 21.592, 0.487], ["+12V", 1, 136.067, 20.921, 136.067, 21.592, 0.487], ["+12V", 1, 8.975, 91.822, 8, 91, 1], ["+12V", 1, 8.975, 91.822, 8.9, 91, 1], ["+12V", 1, 10.158, 91.822, 10.7, 91, 1], ["+12V", 1, 8.975, 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0.2], ["EFUSE_EN5", 1, 96, 23.1, 96.751, 23.274, 0.2], ["EFUSE_FLT1", 1, 23.233, 43.5, 23.817, 43.5, 0.2], ["EFUSE_FLT1", 1, 16.299, 46.551, 17.049, 46.551, 0.2], ["EFUSE_FLT1", 2, 23.3, 43.5, 21.8, 43.5, 0.2], ["EFUSE_FLT1", 2, 21.8, 43.5, 21.1, 44.2, 0.2], ["EFUSE_FLT1", 2, 21.1, 44.2, 20.2, 44.2, 0.2], ["EFUSE_FLT1", 2, 20.2, 44.2, 17.4, 47, 0.2], ["EFUSE_FLT1", 1, 17.4, 47, 17.049, 46.551, 0.2], ["EFUSE_FLT2", 1, 44.656, 82.001, 44.073, 82.001, 0.2], ["EFUSE_FLT2", 1, 51.59, 78.951, 50.84, 78.951, 0.2], ["EFUSE_FLT2", 1, 75.526, 46.608, 75.526, 45.483, 0.2], ["EFUSE_FLT2", 1, 44.073, 82.001, 44.7, 82.65, 0.2], ["EFUSE_FLT2", 1, 44.7, 82.65, 46.4, 82.65, 0.2], ["EFUSE_FLT2", 1, 46.4, 82.65, 47.1, 81.95, 0.2], ["EFUSE_FLT2", 1, 47.1, 81.95, 47.1, 77.75, 0.2], ["EFUSE_FLT2", 1, 47.1, 77.75, 47.5, 77.35, 0.2], ["EFUSE_FLT2", 1, 47.5, 77.35, 49.9, 77.35, 0.2], ["EFUSE_FLT2", 1, 49.9, 77.35, 50.25, 77.7, 0.2], ["EFUSE_FLT2", 1, 50.25, 77.7, 50.25, 78.35, 0.2], ["EFUSE_FLT2", 1, 50.25, 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132.9, 43.2, 0.2], ["EFUSE_FLT5", 1, 132.9, 43.2, 132.9, 43.6, 0.2], ["EFUSE_FLT5", 1, 132.9, 43.6, 131.9, 44.6, 0.2], ["EFUSE_FLT5", 1, 131.9, 44.6, 131, 44.6, 0.2], ["EFUSE_FLT5", 2, 131, 44.6, 128.6, 47, 0.2], ["EFUSE_FLT5", 1, 128.6, 47, 128.25, 46.551, 0.2], ["EFUSE_FLT5", 2, 134.35, 42.95, 134.25, 41.5, 0.2], ["EFUSE_FLT5", 1, 134.25, 41.5, 132.9, 40.2, 0.2], ["EFUSE_FLT5", 2, 132.9, 40.2, 132.55, 39.85, 0.2], ["EFUSE_FLT5", 2, 132.55, 39.85, 123.3, 39.85, 0.2], ["EFUSE_FLT5", 1, 123.3, 39.85, 117.9, 45.25, 0.2], ["EFUSE_FLT5", 1, 117.9, 45.25, 89.7, 45.25, 0.2], ["EFUSE_FLT5", 1, 89.7, 45.25, 88.6, 44.15, 0.2], ["EFUSE_FLT5", 2, 88.6, 44.15, 87.3, 42.85, 0.2], ["EFUSE_FLT5", 1, 87.3, 42.85, 86.6, 42.15, 0.2], ["EFUSE_FLT5", 1, 86.6, 42.15, 78.65, 42.15, 0.2], ["EFUSE_FLT5", 2, 78.65, 42.15, 78.1, 42.7, 0.2], ["EFUSE_FLT5", 2, 78.1, 42.7, 78.1, 43.45, 0.2], ["EFUSE_FLT5", 1, 78.1, 43.45, 76.75, 43.35, 0.2], ["EFUSE_FLT5", 1, 76.75, 43.35, 76.55, 43.15, 0.2], ["EFUSE_FLT5", 2, 76.55, 43.15, 75.65, 44.05, 0.2], ["EFUSE_FLT5", 2, 75.65, 44.05, 75.65, 47.25, 0.2], ["EFUSE_FLT5", 2, 75.65, 47.25, 75.15, 47.75, 0.2], ["EFUSE_FLT5", 2, 75.15, 47.75, 75.05, 48.55, 0.2], ["EFUSE_FLT5", 1, 75.05, 48.55, 75.25, 48.75, 0.2], ["EFUSE_FLT5", 1, 75.25, 48.75, 76, 48.75, 0.2], ["EFUSE_FLT5", 1, 76, 48.75, 76.846, 48.389, 0.2], ["EFUSE_FLT5", 1, 76.846, 48.389, 77.474, 47.734, 0.2], ["EFUSE_PG1", 1, 25.867, 45.499, 25.284, 45.499, 0.2], ["EFUSE_PG1", 1, 15.049, 47.3, 15.069, 47.9, 0.2], ["EFUSE_PG1", 1, 15.069, 47.9, 15.25, 48.075, 0.2], ["EFUSE_PG1", 1, 15.25, 48.075, 15.425, 48.075, 0.2], ["EFUSE_PG1", 1, 15.425, 48.075, 17.675, 50.325, 0.2], ["EFUSE_PG1", 1, 80.075, 52.654, 80.075, 53.779, 0.2], ["EFUSE_PG1", 1, 17.675, 50.325, 19.6, 48.4, 0.2], ["EFUSE_PG1", 1, 19.6, 48.4, 22.2, 48.4, 0.2], ["EFUSE_PG1", 2, 22.2, 48.4, 25.284, 45.499, 0.2], ["EFUSE_PG2", 1, 42.022, 80, 42.605, 80, 0.2], ["EFUSE_PG2", 1, 52.84, 78.199, 52.828, 77.6, 0.2], ["EFUSE_PG2", 1, 52.828, 77.6, 52.65, 77.425, 0.2], ["EFUSE_PG2", 1, 52.65, 77.425, 52.475, 77.425, 0.2], ["EFUSE_PG2", 1, 52.475, 77.425, 50.25, 75.15, 0.2], ["EFUSE_PG2", 1, 79.425, 52.654, 79.425, 53.779, 0.2], ["EFUSE_PG2", 1, 50.25, 75.15, 50.2, 75.2, 0.2], ["EFUSE_PG2", 2, 50.2, 75.2, 41.5, 75.3, 0.2], ["EFUSE_PG2", 1, 41.5, 75.3, 40.4, 74.2, 0.2], ["EFUSE_PG2", 1, 40.4, 74.2, 39.3, 74.2, 0.2], ["EFUSE_PG2", 2, 39.3, 74.2, 37.2, 74.3, 0.2], ["EFUSE_PG2", 1, 37.2, 74.3, 39.5, 76.6, 0.2], ["EFUSE_PG2", 1, 39.5, 76.6, 39.5, 78.4, 0.2], ["EFUSE_PG2", 2, 39.5, 78.4, 40.7, 79.6, 0.2], ["EFUSE_PG2", 2, 40.7, 79.6, 42.2, 79.6, 0.2], ["EFUSE_PG2", 2, 42.2, 79.6, 42.605, 80, 0.2], ["EFUSE_PG3", 1, 130.401, 80, 130.984, 80, 0.2], ["EFUSE_PG3", 1, 141.219, 78.199, 141.204, 77.6, 0.2], ["EFUSE_PG3", 1, 141.204, 77.6, 141.025, 77.425, 0.2], ["EFUSE_PG3", 1, 141.025, 77.425, 140.85, 77.425, 0.2], ["EFUSE_PG3", 1, 140.85, 77.425, 138.6, 75.175, 0.2], ["EFUSE_PG3", 1, 138.6, 75.175, 137.6, 76.15, 0.2], ["EFUSE_PG3", 1, 137.6, 76.15, 132.7, 76.15, 0.2], ["EFUSE_PG3", 1, 132.7, 76.15, 132.5, 76.35, 0.2], ["EFUSE_PG3", 2, 132.5, 76.35, 131.7, 76.35, 0.2], ["EFUSE_PG3", 2, 131.7, 76.35, 130.3, 77.75, 0.2], ["EFUSE_PG3", 2, 130.3, 77.75, 130.3, 79.3, 0.2], ["EFUSE_PG3", 2, 130.3, 79.3, 130.984, 80, 0.2], ["EFUSE_PG4", 1, 57.536, 45.499, 56.953, 45.499, 0.2], ["EFUSE_PG4", 1, 46.718, 47.3, 46.743, 47.9, 0.2], ["EFUSE_PG4", 1, 46.743, 47.9, 46.925, 48.075, 0.2], ["EFUSE_PG4", 1, 46.925, 48.075, 47.1, 48.075, 0.2], ["EFUSE_PG4", 1, 47.1, 48.075, 49.35, 50.325, 0.2], ["EFUSE_PG4", 1, 78.124, 52.654, 78.124, 53.779, 0.2], ["EFUSE_PG4", 1, 49.35, 50.325, 51, 48.65, 0.2], ["EFUSE_PG4", 1, 51, 48.65, 51.5, 48.65, 0.2], ["EFUSE_PG4", 1, 51.5, 48.65, 52.45, 47.7, 0.2], ["EFUSE_PG4", 1, 52.45, 47.7, 52.45, 46.3, 0.2], ["EFUSE_PG4", 1, 52.45, 46.3, 53.2, 45.55, 0.2], ["EFUSE_PG4", 1, 53.2, 45.55, 53.2, 44.05, 0.2], ["EFUSE_PG4", 2, 53.2, 44.05, 53.5, 43.75, 0.2], ["EFUSE_PG4", 2, 53.5, 43.75, 55.6, 43.75, 0.2], ["EFUSE_PG4", 2, 55.6, 43.75, 56.6, 44.75, 0.2], ["EFUSE_PG4", 1, 56.6, 44.75, 56.95, 45.1, 0.2], ["EFUSE_PG4", 1, 56.95, 45.1, 56.953, 45.499, 0.2], ["EFUSE_PG5", 1, 126.251, 47.3, 126.27, 47.9, 0.2], ["EFUSE_PG5", 1, 126.27, 47.9, 126.45, 48.075, 0.2], ["EFUSE_PG5", 1, 126.45, 48.075, 126.625, 48.075, 0.2], ["EFUSE_PG5", 1, 126.625, 48.075, 128.875, 50.325, 0.2], ["EFUSE_PG5", 1, 77.474, 52.654, 77.474, 53.779, 0.2], ["EFUSE_PG5", 1, 128.875, 50.325, 130.4, 48.8, 0.2], ["EFUSE_PG5", 1, 130.4, 48.8, 130.4, 48.4, 0.2], ["EFUSE_PG5", 2, 130.4, 48.4, 133.1, 45.7, 0.2], ["EFUSE_PG5", 2, 133.1, 45.7, 135, 45.7, 0.2], ["EFUSE_PG5", 2, 135, 45.7, 135.6, 45.1, 0.2], ["EFUSE_PG5", 1, 135.6, 45.1, 136, 45.5, 0.2], ["EFUSE_PG5", 1, 136, 45.5, 137.069, 45.499, 0.2], ["FB3V3", 1, 17.651, 104.95, 16.801, 104.95, 0.2], ["FB3V3", 1, 17.5, 116, 17.567, 115.999, 0.2], ["FB3V3", 2, 17.5, 116, 19.1, 117.6, 0.2], ["FB3V3", 2, 19.1, 117.6, 22.4, 117.6, 0.2], ["FB3V3", 2, 22.4, 117.6, 22.6, 117.4, 0.2], ["FB3V3", 2, 22.6, 117.4, 22.777, 116.918, 0.2], ["FB3V3", 2, 22.777, 116.918, 22.7, 116, 0.2], ["FB3V3", 1, 22.7, 116, 21.433, 115.999, 0.2], ["FB3V3", 1, 17.3, 115.75, 16.3, 114.75, 0.2], ["FB3V3", 1, 16.3, 114.75, 16.3, 110.5, 0.2], ["FB3V3", 1, 16.3, 110.5, 15.9, 110.1, 0.2], ["FB3V3", 2, 15.9, 110.1, 15.9, 105.85, 0.2], ["FB3V3", 1, 15.9, 105.85, 16.801, 104.95, 0.2], ["INA_ALERT", 1, 80.428, 45.154, 81.011, 45.154, 0.2], ["INA_ALERT", 1, 14.3, 49.69, 14.3, 49.075, 0.2], ["INA_ALERT", 1, 14.3, 49.075, 14.3, 50.6, 0.2], ["INA_ALERT", 1, 14.3, 50.6, 16.625, 52.95, 0.2], ["INA_ALERT", 1, 53.589, 75.809, 53.595, 76.425, 0.2], ["INA_ALERT", 1, 53.595, 76.425, 53.6, 76.425, 0.2], ["INA_ALERT", 1, 53.6, 76.425, 53.6, 74.9, 0.2], ["INA_ALERT", 1, 53.6, 74.9, 51.25, 72.55, 0.2], ["INA_ALERT", 1, 45.969, 49.69, 45.969, 48.58, 0.2], ["INA_ALERT", 1, 125.499, 49.69, 125.5, 49.075, 0.2], ["INA_ALERT", 1, 125.5, 49.075, 125.5, 50.625, 0.2], ["INA_ALERT", 1, 125.5, 50.625, 127.825, 52.95, 0.2], ["INA_ALERT", 1, 6.5, 96.889, 6.5, 95.779, 0.2], ["INA_ALERT", 1, 78.775, 46.608, 78.775, 47.734, 0.2], ["INA_ALERT", 1, 78.7, 47.8, 78.7, 48.4, 0.2], ["INA_ALERT", 1, 78.7, 48.4, 79, 48.7, 0.2], ["INA_ALERT", 1, 79, 48.7, 80.5, 48.7, 0.2], ["INA_ALERT", 1, 80.5, 48.7, 82.1, 47.1, 0.2], ["INA_ALERT", 1, 82.1, 47.1, 82.1, 46.6, 0.2], ["INA_ALERT", 1, 82.1, 46.6, 81.723, 45.772, 0.2], ["INA_ALERT", 1, 81.723, 45.772, 81.011, 45.154, 0.2], ["INA_ALERT", 1, 82.1, 47.2, 86.4, 51.5, 0.2], ["INA_ALERT", 1, 86.4, 51.5, 114.1, 51.5, 0.2], ["INA_ALERT", 2, 114.1, 51.5, 120.3, 57.7, 0.2], ["INA_ALERT", 1, 120.3, 57.7, 122, 59.4, 0.2], ["INA_ALERT", 1, 122, 59.4, 130.7, 59.4, 0.2], ["INA_ALERT", 1, 130.7, 59.4, 131.8, 58.3, 0.2], ["INA_ALERT", 1, 131.8, 58.3, 131.8, 56.2, 0.2], ["INA_ALERT", 1, 131.8, 56.2, 128.8, 53.2, 0.2], ["INA_ALERT", 1, 128.8, 53.2, 128.153, 53.2, 0.2], ["INA_ALERT", 1, 128.153, 53.2, 127.913, 53.075, 0.2], ["INA_ALERT", 1, 127.913, 53.075, 127.825, 52.95, 0.2], ["IOEXP_INT#", 1, 72.136, 47.179, 72.136, 47.762, 0.2], ["IOEXP_INT#", 1, 72.136, 47.762, 72.9, 47, 0.2], ["IOEXP_INT#", 1, 72.9, 47, 72.925, 46.608, 0.2], ["NTC1", 1, 77.872, 9.847, 77.865, 10.095, 0.2], ["NTC1", 1, 77.872, 10.398, 77.872, 9.847, 0.2], ["NTC1", 1, 77.872, 9.847, 77.872, 9.524, 0.2], ["NTC1", 1, 78.1, 10.6, 79.251, 10.574, 0.2], ["NTC1", 1, 80, 11, 80.3, 11.15, 0.2], ["NTC1", 1, 80.3, 11.15, 80.6, 11.635, 0.2], ["NTC1", 1, 80.6, 11.635, 80.6, 13.8, 0.2], ["NTC1", 2, 80.6, 13.8, 79.7, 14.7, 0.2], ["NTC1", 2, 79.7, 14.7, 77.4, 14.7, 0.2], ["NTC1", 2, 77.4, 14.7, 63.8, 28.3, 0.2], ["NTC1", 1, 63.8, 28.3, 63.4, 28.7, 0.2], ["NTC1", 1, 63.4, 28.7, 60.6, 28.7, 0.2], ["NTC1", 2, 60.6, 28.7, 67.1, 35.2, 0.2], ["NTC1", 2, 67.1, 35.2, 70.8, 35.248, 0.2], ["NTC2", 1, 77.865, 12.225, 77.865, 11.855, 0.2], ["NTC2", 1, 76.985, 12.677, 76.985, 13.26, 0.2], ["NTC2", 1, 77.865, 11.855, 79.251, 11.844, 0.2], ["NTC2", 1, 77.6, 12.45, 77.4, 12.45, 0.2], ["NTC2", 1, 77.4, 12.45, 77, 12.85, 0.2], ["NTC2", 1, 77, 12.85, 76.985, 13.26, 0.2], ["NTC2", 1, 76.9, 13.3, 74.3, 15.9, 0.2], ["NTC2", 1, 74.3, 15.9, 74.3, 21.7, 0.2], ["NTC2", 2, 74.3, 21.7, 70.8, 25.248, 0.2], ["SCL", 1, 98.15, 18.628, 98.15, 19.211, 0.2], ["SCL", 1, 109.819, 33.21, 109.819, 32.51, 0.2], ["SCL", 1, 98.15, 19.211, 97.593, 18.461, 0.2], ["SCL", 1, 97.593, 18.461, 97.076, 18.197, 0.2], ["SCL", 1, 97.076, 18.197, 96.751, 18.194, 0.2], ["SCL", 1, 109.4, 33.2, 109.319, 33.21, 0.2], ["SCL", 1, 126.8, 49.3, 126.5, 48.58, 0.15], ["SCL", 1, 104, 25.2, 95.9, 33.3, 0.2], ["SCL", 2, 95.9, 33.3, 77.2, 52, 0.2], ["SCL", 2, 48.1, 50.05, 47.9, 49.85, 0.2], ["SCL", 1, 47.9, 49.85, 47.063, 49.013, 0.2], ["SCL", 1, 46.96, 48.74, 46.97, 48.58, 0.2], ["SCL", 1, 34.95, 62.9, 34.55, 62.5, 0.2], ["SCL", 1, 34.55, 62.5, 32.15, 62.5, 0.2], ["SCL", 1, 32.15, 62.5, 32, 62.35, 0.2], ["SCL", 1, 15.3, 50.6, 15.3, 49.69, 0.2], ["SCL", 1, 15.3, 49.69, 15.301, 48.58, 0.2], ["SCL", 2, 9.4, 95.2, 7.4, 95.2, 0.2], ["SCL", 1, 7.4, 95.2, 7.501, 95.779, 0.2], ["SCL", 1, 52.588, 75.809, 52.588, 76.919, 0.2], ["SCL", 1, 140.97, 75.809, 140.97, 76.919, 0.2], ["SCL", 1, 46.97, 49.69, 46.97, 48.766, 0.2], ["SCL", 1, 46.97, 48.766, 46.97, 48.58, 0.2], ["SCL", 1, 47.063, 49.013, 46.97, 48.766, 0.2], ["SCL", 1, 46.97, 48.766, 46.96, 48.74, 0.2], ["SCL", 1, 126.5, 49.69, 126.5, 48.58, 0.2], ["SCL", 1, 7.501, 96.889, 7.501, 95.779, 0.2], ["SDA", 1, 86.771, 28.474, 87.354, 28.474, 0.2], ["SDA", 1, 110.3, 32.5, 110.3, 32.1, 0.2], ["SDA", 1, 109.3, 31.1, 108.9, 31.1, 0.2], ["SDA", 2, 108.9, 31.1, 108.5, 30.7, 0.2], ["SDA", 2, 108.5, 30.7, 89.6, 30.7, 0.2], ["SDA", 2, 89.6, 30.7, 87.354, 28.474, 0.2], ["SDA", 2, 87.2, 28.3, 86.096, 27.094, 0.2], ["SDA", 1, 80.25, 35.8, 79.831, 35.811, 0.15], ["SDA", 1, 49.3, 51.3, 49.3, 52.164, 0.2], ["SDA", 1, 49.3, 52.164, 49.05, 52.725, 0.2], ["SDA", 1, 49.05, 52.725, 48.8, 52.95, 0.2], ["SDA", 2, 52.6, 78.1, 51.8, 78.9, 0.2], ["SDA", 2, 9.4, 95.65, 6.8, 98.25, 0.2], ["SDA", 1, 6.8, 98.25, 7, 98.05, 0.2], ["SDA", 1, 7, 98.05, 7, 96.89, 0.2], ["SDA", 1, 79.831, 36.511, 79.831, 35.811, 0.2], ["SDA", 1, 110.32, 33.21, 110.32, 32.51, 0.2], ["SDA", 1, 14.801, 49.69, 14.801, 48.58, 0.2], ["SDA", 1, 53.088, 75.809, 53.088, 76.919, 0.2], ["SDA", 1, 141.468, 75.809, 141.472, 76.425, 0.2], ["SDA", 1, 141.472, 76.425, 141.475, 76.425, 0.2], ["SDA", 1, 141.475, 76.425, 141.475, 74.925, 0.15], ["SDA", 1, 46.469, 49.69, 46.472, 49.075, 0.2], ["SDA", 1, 46.472, 49.075, 46.475, 49.075, 0.2], ["SDA", 1, 46.475, 49.075, 46.475, 50.625, 0.2], ["SDA", 1, 46.475, 50.625, 48.8, 52.95, 0.2], ["SDA", 1, 125.001, 49.69, 125.001, 48.58, 0.2], ["SDA", 1, 125.999, 49.69, 125.999, 48.58, 0.2], ["SW3V3", 1, 23.081, 108.501, 22.531, 108.501, 0.5], ["SW3V3", 1, 20.351, 104, 21.2, 104, 0.599], ["SW3V3", 1, 22.531, 108.501, 22.953, 108.94, 0.35], ["SW3V3", 1, 22.953, 108.94, 23.8, 109.3, 0.35], ["SW3V3", 1, 23.8, 109.3, 24.7, 109.3, 0.35], ["SW3V3", 1, 24.7, 109.3, 25.1, 108.9, 0.35], ["SW3V3", 1, 25.1, 108.9, 25.1, 107.3, 0.35], ["SW3V3", 1, 25.1, 107.3, 21.9, 104.1, 0.35], ["SW3V3", 1, 21.9, 104.1, 21.2, 104, 0.35], ["SW3V3", 1, 23, 105, 23.901, 104, 0.5], ["VBUS_EN3", 1, 89.906, 27.094, 89.9, 24.3, 0.2], ["VBUS_EN3", 1, 89.9, 24.3, 91.3, 22.9, 0.2], ["VBUS_EN3", 2, 91.3, 22.9, 95.1, 19.1, 0.2], ["VBUS_EN3", 2, 95.1, 19.1, 100.5, 19.1, 0.2], ["VBUS_EN3", 1, 100.5, 19.1, 101.8, 17.8, 0.2], ["VBUS_EN3", 1, 101.8, 17.8, 127.2, 17.8, 0.2], ["VBUS_EN3", 1, 127.2, 17.8, 127.8, 18.4, 0.2], ["VBUS_EN3", 1, 127.8, 18.4, 127.8, 21.5, 0.2], ["VBUS_EN3", 1, 127.8, 21.5, 131.9, 25.6, 0.2], ["VBUS_EN3", 1, 131.9, 25.6, 133.3, 25.6, 0.2], ["VBUS_EN3", 1, 133.3, 25.6, 134.2, 26.5, 0.2], ["VBUS_EN3", 1, 134.2, 26.5, 134.2, 27.6, 0.2], ["VBUS_EN3", 1, 134.2, 27.6, 142.3, 35.7, 0.2], ["VBUS_EN3", 1, 142.3, 35.7, 143.7, 35.7, 0.2], ["VBUS_EN3", 1, 143.7, 35.7, 145.6, 37.6, 0.2], ["VBUS_EN3", 1, 145.6, 37.6, 145.6, 38.2, 0.2], ["VBUS_EN3", 1, 145.6, 38.2, 146.7, 39.3, 0.2], ["VBUS_EN3", 2, 146.7, 39.3, 146.7, 46.4, 0.2], ["VBUS_EN3", 2, 146.7, 46.4, 155.1, 54.8, 0.2], ["VBUS_EN3", 2, 155.1, 54.8, 155.1, 71.8, 0.2], ["VBUS_EN3", 2, 155.1, 71.8, 154.739, 72.646, 0.2], ["VBUS_EN3", 2, 154.739, 72.646, 152.8, 74.5, 0.2], ["VBUS_EN3", 1, 152.8, 74.5, 151.8, 73.5, 0.2], ["VBUS_EN3", 1, 151.8, 73.5, 151.8, 66, 0.2], ["VBUS_EN3", 2, 151.8, 66, 149.591, 63.769, 0.2], ["VDAC5", 1, 126.434, 20.701, 126.434, 21.271, 0.2], ["VDAC5", 1, 111.069, 34.46, 111.069, 34.02, 0.2], ["VO1", 1, 10.866, 18.501, 10.283, 18.501, 0.541], ["VO1", 1, 18.867, 47.5, 18.284, 47.5, 0.541], ["VO1", 1, 17.15, 31.8, 18.25, 31.8, 0.3], ["VO1", 1, 18.25, 31.8, 20.1, 29.95, 0.3], ["VO1", 2, 20.1, 29.95, 23.2, 26.85, 0.3], ["VO1", 1, 23.2, 26.85, 22.75, 26.4, 0.3], ["VO1", 1, 22.75, 26.4, 21.6, 26.4, 0.3], ["VO1", 1, 21.6, 26.4, 16.75, 21.55, 0.3], ["VO1", 1, 16.75, 21.55, 16.75, 18.65, 0.3], ["VO1", 1, 16.75, 18.65, 15.9, 17.8, 0.3], ["VO1", 1, 15.9, 17.8, 11, 17.8, 0.3], ["VO1", 1, 11, 17.8, 10.283, 18.501, 0.3], ["VO2", 1, 57.023, 107, 57.606, 107, 0.541], ["VO2", 1, 49.022, 78.001, 49.605, 78.001, 0.541], ["VO2", 1, 52.65, 92.65, 53.4, 92.65, 0.3], ["VO2", 2, 53.4, 92.65, 56.15, 92.65, 0.3], ["VO2", 1, 56.15, 92.65, 56.65, 93.15, 0.3], ["VO2", 1, 56.65, 93.15, 56.65, 93.5, 0.3], ["VO2", 1, 56.65, 93.5, 58.75, 95.6, 0.3], ["VO2", 1, 58.75, 95.6, 58.75, 105.85, 0.3], ["VO2", 1, 58.75, 105.85, 57.606, 107, 0.3], ["VO3", 1, 145.402, 107, 145.985, 107, 0.541], ["VO3", 1, 137.401, 78.001, 137.984, 78.001, 0.541], ["VO3", 2, 141, 93.45, 141.951, 94.525, 0.3], ["VO3", 2, 141.951, 94.525, 142.45, 94.75, 0.3], ["VO3", 2, 142.45, 94.75, 142.95, 94.75, 0.3], ["VO3", 2, 142.95, 94.75, 144.35, 96.15, 0.3], ["VO3", 2, 144.35, 96.15, 144.35, 105.35, 0.3], ["VO3", 2, 144.35, 105.35, 145.985, 107, 0.3], ["VO4", 1, 42.537, 18.501, 41.954, 18.501, 0.541], ["VO4", 1, 50.536, 47.5, 49.953, 47.5, 0.541], ["VO5", 1, 122.067, 18.501, 121.484, 18.501, 0.541], ["VO5", 1, 130.068, 47.5, 129.485, 47.5, 0.541], ["VO5", 2, 125, 44.4, 126.3, 44.4, 0.3], ["VO5", 2, 126.3, 44.4, 126.65, 44.75, 0.3], ["VO5", 2, 126.65, 44.75, 126.981, 45.595, 0.3], ["VO5", 2, 126.981, 45.595, 126.911, 47.417, 0.3], ["VO5", 2, 126.911, 47.417, 127.1, 47.9, 0.3], ["VO5", 2, 127.1, 47.9, 127.3, 48.1, 0.3], ["VO5", 2, 127.3, 48.1, 128.9, 48.1, 0.3], ["VO5", 2, 128.9, 48.1, 129.485, 47.5, 0.3], ["VO5", 1, 126.4, 32.85, 125.7, 32.85, 0.3], ["VO5", 2, 125.7, 32.85, 122.9, 32.85, 0.3], ["VO5", 1, 122.9, 32.85, 120.6, 30.55, 0.3], ["VO5", 1, 120.6, 30.55, 120.6, 19.4, 0.3], ["VO5", 1, 120.6, 19.4, 121.484, 18.501, 0.3], ["$12N834", 1, 46.9, 18.3, 46.9, 18.2, 0.2], ["$12N834", 2, 46.9, 18.2, 45.3, 19.8, 0.2], ["$12N834", 1, 45.3, 19.8, 45.8, 20.5, 0.2], ["$12N836", 1, 49.22, 25.776, 49.22, 25.076, 0.2], ["$12N836", 1, 48.9, 18.45, 48.1, 17.65, 0.15], ["$12N836", 1, 48.1, 17.65, 47.6, 17.65, 0.15], ["$12N836", 2, 47.6, 17.65, 46.898, 17.58, 0.15], ["$12N836", 2, 46.898, 17.58, 46.395, 17.769, 0.15], ["$12N836", 2, 46.395, 17.769, 44.45, 19.85, 0.15], ["$12N836", 1, 44.45, 19.85, 44.95, 20.4, 0.15], ["$12N836", 1, 44.95, 20.4, 44.95, 20.625, 0.15], ["$12N836", 1, 44.95, 20.625, 45.116, 21.002, 0.15], ["$12N836", 1, 45.116, 21.002, 45.879, 21.698, 0.15], ["$12N836", 1, 45.879, 21.698, 46.1, 22.2, 0.15], ["$12N836", 1, 46.1, 22.2, 46.1, 23.1, 0.15], ["$12N836", 1, 46.1, 23.1, 47.05, 24.05, 0.15], ["$12N836", 2, 47.05, 24.05, 47.35, 24.35, 0.15], ["$12N836", 2, 47.35, 24.35, 48.45, 24.35, 0.15], ["$12N836", 1, 48.45, 24.35, 49.22, 25.076, 0.15], ["$14N653", 1, 137.517, 18.501, 137.425, 19.289, 0.15], ["$14N653", 1, 137.425, 19.289, 137.55, 19.65, 0.15], ["$14N653", 1, 137.55, 19.65, 137.7, 19.8, 0.15], ["$14N653", 2, 137.7, 19.8, 138.2, 20.3, 0.15], ["$14N653", 2, 138.2, 20.3, 138.2, 22.7, 0.15], ["$14N653", 2, 138.2, 22.7, 131.154, 29.746, 0.15], ["$14N653", 2, 131.154, 29.746, 130.3, 30.087, 0.15], ["$14N653", 2, 130.3, 30.087, 127.1, 30, 0.15], ["$14N653", 1, 127.1, 30, 127.252, 29.925, 0.15], ["$14N657", 1, 128.75, 25.776, 128.75, 25.076, 0.2], ["$14N657", 1, 132.1, 20.8, 131.7, 21, 0.2], ["$14N657", 2, 131.7, 21, 131.3, 21.4, 0.2], ["$14N657", 2, 131.3, 21.4, 127.6, 21.4, 0.2], ["$14N657", 2, 127.6, 21.4, 126.5, 22.5, 0.2], ["$14N657", 1, 126.5, 22.5, 126.5, 23.9, 0.2], ["$14N657", 2, 126.5, 23.9, 127.3, 24.7, 0.2], ["$14N657", 2, 127.3, 24.7, 128.5, 24.7, 0.2], ["$14N657", 1, 128.5, 24.7, 128.75, 25.076, 0.2], ["$14N699", 1, 123.1, 46.1, 122.65, 46.1, 0.3], ["$14N699", 1, 122.65, 46.1, 122.15, 45.6, 0.3], ["$14N699", 2, 122.15, 45.6, 121.2, 44.65, 0.3], ["$14N699", 1, 121.2, 44.65, 121.2, 44.15, 0.3], ["$14N699", 1, 121.2, 44.15, 123.4, 41.95, 0.3], ["$14N699", 2, 123.4, 41.95, 131.05, 41.9, 0.3], ["$14N699", 1, 131.05, 41.9, 131.5, 42.35, 0.3], ["$14N699", 1, 131.5, 42.35, 133.9, 42.35, 0.3], ["$14N699", 1, 133.9, 42.35, 134, 42.25, 0.3], ["$14N699", 1, 134, 42.25, 135.1, 42.25, 0.3], ["$14N699", 1, 135.1, 42.25, 136.25, 43.4, 0.3], ["$16N9", 1, 61.5, 73.1, 61.5, 73, 0.2], ["$8N732", 1, 46.789, 70.5, 46.8, 69.3, 0.2], ["$8N732", 1, 46.8, 69.3, 44.4, 66.9, 0.2], ["$8N732", 1, 44.4, 66.9, 41.788, 66.934, 0.2], ["+12V", 1, 6.2, 100, 6.2, 99.9, 0.3], ["+3V3", 1, 50.5, 71.8, 50.6, 71.8, 0.15], ["+3V3", 1, 51.1, 71.8, 54.025, 74.725, 0.15], ["+3V3", 1, 50.6, 71.8, 51.1, 71.8, 0.195], ["+3V3", 1, 51.1, 71.8, 51.9, 71.8, 0.195], ["+3V3", 1, 54.025, 74.725, 54.025, 76.65, 0.15], ["+3V3", 1, 54.025, 76.65, 54.089, 76.714, 0.15], ["+3V3", 1, 54.089, 76.714, 54.3, 76.925, 0.15], ["+3V3", 1, 54.089, 75.809, 54.089, 76.714, 0.279], ["+3V3", 1, 54.089, 76.714, 54.089, 76.919, 0.279], ["+3V3", 1, 54.3, 76.925, 54.775, 76.925, 0.15], ["+3V3", 1, 54.775, 76.925, 54.925, 76.838, 0.15], ["+3V3", 1, 54.925, 76.838, 55.25, 76.275, 0.15], ["+3V3", 2, 55.25, 76.275, 54.8, 75.825, 0.15], ["+3V3", 2, 54.8, 75.825, 52.425, 75.825, 0.15], ["+3V3", 2, 52.425, 75.825, 51.925, 75.825, 0.15], ["+3V3", 2, 51.8, 75.2, 52.425, 75.825, 0.195], ["+3V3", 2, 52.425, 75.825, 53.5, 76.9, 0.195], ["+3V3", 1, 51.925, 75.825, 50.138, 74.038, 0.15], ["+3V3", 1, 50.138, 74.038, 50.055, 73.825, 0.15], ["+3V3", 1, 50.055, 73.825, 50.06, 73.701, 0.15], ["+3V3", 1, 49.5, 73.9, 49.4, 75.6, 0.279], ["+3V3", 1, 49.4, 75.6, 48.3, 76.7, 0.279], ["+3V3", 1, 48.3, 76.7, 47.9, 76.7, 0.279], ["+3V3", 1, 47.9, 76.7, 47.224, 76.411, 0.279], ["+3V3", 1, 47.224, 76.411, 45.745, 74.862, 0.279], ["+3V3", 1, 45.745, 74.862, 44.9, 74.5, 0.279], ["+3V3", 1, 44.9, 74.5, 44.205, 74.501, 0.279], ["EFUSE_EN3", 2, 153.5, 70.4, 153.5, 59.9, 0.2], ["EFUSE_EN3", 2, 153.5, 59.9, 149.5, 55.9, 0.2], ["EFUSE_EN3", 2, 149.5, 55.9, 149.5, 52.1, 0.2], ["EFUSE_EN3", 1, 149.5, 52.1, 144.3, 46.9, 0.2], ["EFUSE_EN3", 1, 144.3, 46.9, 144.3, 42.4, 0.2], ["EFUSE_EN3", 2, 144.3, 42.4, 140.5, 38.6, 0.2], ["EFUSE_EN3", 1, 140.5, 38.6, 138.9, 37, 0.2], ["EFUSE_EN3", 1, 138.9, 37, 134.9, 37, 0.2], ["EFUSE_EN3", 2, 134.9, 37, 132.2, 34.3, 0.2], ["EFUSE_EN3", 2, 132.2, 34.3, 121.6, 34.3, 0.2], ["EFUSE_EN3", 1, 121.6, 34.3, 120.2, 32.9, 0.2], ["EFUSE_EN3", 1, 120.2, 32.9, 115.5, 32.9, 0.2], ["EFUSE_EN3", 1, 115.5, 32.9, 115, 32.4, 0.2], ["EFUSE_EN3", 2, 115, 32.4, 99.6, 17, 0.2], ["EFUSE_EN3", 2, 99.6, 17, 98.1, 17, 0.2], ["EFUSE_EN3", 2, 98.1, 17, 96.9, 15.8, 0.2], ["EFUSE_EN3", 1, 96.9, 15.8, 96.751, 15.654, 0.2], ["INA_ALERT", 1, 51.2, 72.5, 47.4, 72.5, 0.2], ["INA_ALERT", 1, 47.4, 72.5, 45.6, 70.7, 0.2], ["INA_ALERT", 1, 45.6, 70.7, 43.9, 70.7, 0.2], ["INA_ALERT", 1, 43.9, 70.7, 43, 69.8, 0.2], ["INA_ALERT", 1, 43, 69.8, 34.9, 69.8, 0.2], ["INA_ALERT", 2, 34.9, 69.8, 16.5, 69.8, 0.2], ["INA_ALERT", 2, 16.5, 69.8, 15.1, 71.2, 0.2], ["INA_ALERT", 2, 15.1, 71.2, 11.6, 71.2, 0.2], ["INA_ALERT", 2, 11.6, 71.2, 11.2, 70.8, 0.2], ["INA_ALERT", 1, 11.2, 70.8, 11.2, 78.1, 0.2], ["INA_ALERT", 2, 11.2, 78.1, 11.2, 84.6, 0.2], ["INA_ALERT", 2, 11.2, 84.6, 7.1, 88.7, 0.2], ["INA_ALERT", 2, 7.1, 88.7, 7.1, 94.3, 0.2], ["INA_ALERT", 1, 7.1, 94.3, 6.7, 94.7, 0.2], ["INA_ALERT", 1, 6.7, 94.7, 6.7, 95.5, 0.2], ["INA_ALERT", 1, 6.7, 95.5, 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["EFUSE_EN3", 1, 89.5, 91.4, 90.2, 90.7, 0.2], ["EFUSE_EN3", 1, 90.2, 90.7, 90.2, 75.7, 0.2], ["EFUSE_EN3", 2, 90.2, 75.7, 93.9, 72, 0.2], ["EFUSE_EN3", 1, 93.9, 72, 95.4, 70.5, 0.2], ["EFUSE_EN3", 2, 95.4, 70.5, 97.6, 70.5, 0.2], ["EFUSE_EN3", 1, 97.6, 70.5, 98.5, 70.5, 0.2], ["EFUSE_EN3", 1, 98.5, 70.5, 101.4, 67.6, 0.2], ["EFUSE_EN3", 1, 101.4, 67.6, 103.5, 67.6, 0.2], ["EFUSE_EN3", 2, 103.5, 67.6, 105.3, 67.6, 0.2], ["EFUSE_EN3", 2, 105.3, 67.6, 105.7, 68, 0.2], ["EFUSE_EN3", 2, 105.7, 68, 108.6, 68, 0.2], ["EFUSE_EN3", 2, 108.6, 68, 113.6, 73, 0.2], ["EFUSE_EN3", 1, 113.6, 73, 125.9, 73, 0.2], ["EFUSE_EN3", 1, 125.9, 73, 130.901, 78.001, 0.2], ["EFUSE_EN3", 1, 130.401, 78.001, 130.901, 78.001, 0.2], ["EFUSE_EN3", 1, 130.901, 78.001, 130.984, 78.001, 0.2], ["EFUSE_EN3", 2, 131, 78.1, 131.2, 78.3, 0.2], ["EFUSE_EN3", 2, 133.2, 78.3, 133.15, 78.25, 0.2], ["EFUSE_EN3", 2, 133.15, 78.25, 132.195, 78.217, 0.2], ["EFUSE_EN3", 2, 132.195, 78.217, 131.984, 78.3, 0.2], ["EFUSE_EN3", 2, 131.984, 78.3, 131.35, 78.55, 0.2], ["EFUSE_EN3", 2, 131.2, 78.3, 131.984, 78.3, 0.2], ["EFUSE_EN3", 2, 131.984, 78.3, 133.2, 78.3, 0.2], ["EFUSE_EN3", 2, 131.35, 78.55, 131, 78.9, 0.2], ["EFUSE_EN3", 1, 131, 78.9, 130.986, 78.086, 0.2], ["EFUSE_EN3", 1, 130.986, 78.086, 130.984, 78.001, 0.2], ["EFUSE_EN3", 1, 130.901, 78.001, 130.986, 78.086, 0.2], ["EFUSE_EN3", 1, 130.986, 78.086, 131, 78.1, 0.2], ["EFUSE_EN3", 2, 133.2, 78.2, 133.2, 75.4, 0.2], ["EFUSE_EN3", 1, 133.2, 75.4, 133.17, 75.451, 0.2], ["EFUSE_FLT1", 1, 74.876, 46.608, 74.876, 45.483, 0.2], ["EFUSE_FLT1", 1, 23.9, 43.5, 24.1, 43.5, 0.2], ["EFUSE_FLT1", 2, 24.1, 43.5, 24.3, 43.3, 0.2], ["EFUSE_FLT1", 2, 24.3, 43.3, 41.7, 43.3, 0.2], ["EFUSE_FLT1", 1, 41.7, 43.3, 43.8, 41.2, 0.2], ["EFUSE_FLT1", 2, 43.8, 41.2, 56, 41.2, 0.2], ["EFUSE_FLT1", 2, 56, 41.2, 57.5, 39.7, 0.2], ["EFUSE_FLT1", 1, 57.5, 39.7, 60.9, 39.7, 0.2], ["EFUSE_FLT1", 1, 60.9, 39.7, 64.3, 43.1, 0.2], ["EFUSE_FLT1", 1, 64.3, 43.1, 72.6, 43.1, 0.2], ["EFUSE_FLT1", 2, 72.6, 43.1, 74.7, 45.3, 0.2], ["EFUSE_FLT1", 1, 74.7, 45.3, 74.876, 45.483, 0.2], ["EFUSE_PG3", 1, 78.775, 52.654, 78.775, 53.779, 0.2], ["EFUSE_PG3", 2, 130.3, 77.7, 120.3, 67.7, 0.15], ["EFUSE_PG3", 2, 120.3, 67.7, 118.8, 67.5, 0.15], ["EFUSE_PG3", 2, 118.8, 67.5, 106.1, 67.5, 0.15], ["EFUSE_PG3", 2, 106.1, 67.5, 104.4, 65.8, 0.15], ["EFUSE_PG3", 1, 104.4, 65.8, 103.9, 65.3, 0.15], ["EFUSE_PG3", 1, 103.9, 65.3, 97.9, 65.3, 0.15], ["EFUSE_PG3", 1, 97.9, 65.3, 95.1, 62.5, 0.15], ["EFUSE_PG3", 2, 95.1, 62.5, 91.8, 62.5, 0.15], ["EFUSE_PG3", 1, 91.8, 62.5, 87.4, 62.5, 0.15], ["EFUSE_PG3", 1, 87.4, 62.5, 78.775, 53.779, 0.15], ["INA_ALERT", 1, 128.85, 53.15, 128.85, 51.45, 0.2], ["INA_ALERT", 1, 128.85, 51.45, 130, 50.3, 0.2], ["INA_ALERT", 1, 130, 50.3, 132.8, 50.3, 0.2], ["INA_ALERT", 1, 132.8, 50.3, 133.25, 49.85, 0.2], ["INA_ALERT", 2, 133.25, 49.85, 138.45, 49.85, 0.2], ["INA_ALERT", 1, 138.45, 49.85, 140.35, 51.75, 0.2], ["INA_ALERT", 1, 140.35, 51.75, 140.35, 52.15, 0.2], ["INA_ALERT", 1, 140.35, 52.15, 147.95, 59.75, 0.2], ["INA_ALERT", 2, 147.95, 59.75, 148.3, 60.1, 0.2], ["INA_ALERT", 2, 148.3, 60.1, 148.3, 73.45, 0.2], ["INA_ALERT", 2, 148.3, 73.45, 146.8, 74.95, 0.2], ["INA_ALERT", 2, 146.8, 74.95, 143.95, 74.95, 0.2], ["INA_ALERT", 2, 143.95, 74.95, 143.75, 75.15, 0.2], ["INA_ALERT", 1, 143.75, 75.15, 143.356, 74.756, 0.2], ["INA_ALERT", 1, 143.356, 74.756, 143.1, 74.656, 0.2], ["INA_ALERT", 1, 143.1, 74.656, 142.05, 74.7, 0.2], ["INA_ALERT", 2, 147.5, 74.3, 148, 74.8, 0.2], ["INA_ALERT", 1, 148, 74.8, 149.2, 76, 0.2], ["INA_ALERT", 1, 149.2, 76, 149.2, 83.5, 0.2], ["INA_ALERT", 1, 149.2, 83.5, 145, 87.7, 0.2], ["INA_ALERT", 2, 145, 87.7, 140.9, 91.8, 0.2], ["INA_ALERT", 2, 140.9, 91.8, 132.7, 91.8, 0.2], ["INA_ALERT", 2, 132.7, 91.8, 129.5, 95, 0.2], ["INA_ALERT", 1, 129.5, 95, 124.8, 99.7, 0.2], ["INA_ALERT", 1, 124.8, 99.7, 103.7, 99.7, 0.2], ["INA_ALERT", 2, 103.7, 99.7, 100.4, 99.7, 0.2], ["INA_ALERT", 1, 100.4, 99.7, 99, 99.8, 0.2], ["INA_ALERT", 2, 99, 99.8, 86.7, 87.5, 0.2], ["INA_ALERT", 2, 86.7, 87.5, 68.8, 87.5, 0.2], ["INA_ALERT", 1, 68.8, 87.5, 62.1, 80.8, 0.2], ["INA_ALERT", 2, 62.1, 80.8, 59.7, 78.4, 0.2], ["INA_ALERT", 1, 59.7, 78.4, 58.6, 77.3, 0.2], ["INA_ALERT", 2, 58.6, 77.3, 58.3, 77.6, 0.2], ["INA_ALERT", 2, 58.3, 77.6, 52.8, 77.6, 0.2], ["INA_ALERT", 2, 52.8, 77.6, 51.8, 76.6, 0.2], ["INA_ALERT", 2, 51.8, 76.6, 41.6, 76.6, 0.2], ["INA_ALERT", 2, 41.6, 76.6, 40, 75, 0.2], ["INA_ALERT", 2, 40, 75, 40, 73.7, 0.2], ["INA_ALERT", 2, 40, 73.7, 39.8, 73.5, 0.2], ["INA_ALERT", 2, 39.8, 73.5, 38.9, 73.5, 0.2], ["INA_ALERT", 2, 38.9, 73.5, 35.2, 69.8, 0.2], ["VO1", 2, 13.8, 44.4, 15.1, 44.4, 0.3], ["VO1", 2, 15.1, 44.4, 15.45, 44.75, 0.3], ["VO1", 2, 15.45, 44.75, 15.781, 45.595, 0.3], ["VO1", 2, 15.781, 45.595, 15.711, 47.417, 0.3], ["VO1", 2, 15.711, 47.417, 15.9, 47.9, 0.3], ["VO1", 2, 15.9, 47.9, 16.1, 48.1, 0.3], ["VO1", 2, 16.1, 48.1, 17.6, 48.1, 0.3], ["VO1", 2, 17.6, 48.1, 17.9, 47.8, 0.3], ["VO1", 1, 17.9, 47.8, 18.1, 47.6, 0.3], ["VO2", 1, 51.4, 87.25, 51.4, 87.05, 0.3], ["VO2", 1, 51.4, 87.05, 51.2, 86.85, 0.3], ["VO2", 1, 51.2, 86.85, 50.45, 86.85, 0.3], ["VO2", 1, 50.45, 86.85, 46.775, 83.175, 0.3], ["VO2", 2, 46.775, 83.175, 42.875, 79.275, 0.3], ["VO2", 2, 42.875, 79.275, 42.875, 78.625, 0.3], ["VO2", 2, 42.875, 78.625, 43.225, 78.275, 0.3], ["VO2", 2, 43.225, 78.275, 48.975, 78.25, 0.3], ["VO3", 1, 139.775, 87.25, 139.775, 87.05, 0.3], ["VO3", 1, 139.775, 87.05, 139.575, 86.85, 0.3], ["VO3", 1, 139.575, 86.85, 139.25, 86.85, 0.3], ["VO3", 1, 139.25, 86.85, 138.45, 86.05, 0.3], ["VO3", 1, 138.45, 86.05, 138.45, 84.6, 0.3], ["VO3", 1, 138.45, 84.6, 137.425, 83.575, 0.3], ["VO3", 2, 137.425, 83.575, 137.275, 83.425, 0.3], ["VO3", 2, 137.275, 83.425, 137.275, 82.425, 0.3], ["VO3", 2, 137.275, 82.425, 139.3, 80.4, 0.3], ["VO3", 2, 139.3, 80.4, 139.3, 79.95, 0.3], ["VO3", 2, 139.3, 79.95, 139.154, 79.614, 0.3], ["VO3", 2, 139.154, 79.614, 137.775, 78.325, 0.3], ["VO3", 1, 137.775, 78.325, 137.775, 78.25, 0.3], ["VO4", 1, 44.45, 37.4, 41.55, 34.5, 0.3], ["VO4", 1, 41.55, 34.5, 37.5, 34.5, 0.3], ["VO4", 1, 37.5, 34.5, 34.75, 31.75, 0.3], ["VO4", 1, 34.75, 31.75, 34.75, 29.5, 0.3], ["VO4", 1, 34.75, 29.5, 36.2, 28.05, 0.3], ["VO4", 1, 36.2, 28.05, 36.2, 24.25, 0.3], ["VO4", 1, 36.2, 24.25, 41.954, 18.501, 0.3], ["$12N832", 1, 57.4, 18.7, 57.4, 19.7, 0.2], ["$12N832", 2, 57.4, 19.7, 57, 20.1, 0.2], ["$12N832", 2, 57, 20.1, 56.6, 20.1, 0.2], ["$12N832", 2, 56.6, 20.1, 53.1, 23.6, 0.2], ["$12N832", 2, 53.1, 23.6, 53.1, 26.2, 0.2], ["$12N832", 2, 53.1, 26.2, 49.2, 30.1, 0.2], ["$12N832", 2, 49.2, 30.1, 47.7, 30.2, 0.2], ["$12N832", 1, 47.7, 30.2, 47.7, 30, 0.2], ["$12N855", 2, 50.2, 45.5, 51.4, 46.7, 0.2], ["$12N855", 2, 51.4, 46.7, 51.4, 47.3, 0.2], ["$6N545", 1, 110.32, 36.21, 110.65, 36.55, 0.2], ["$6N545", 1, 110.65, 36.55, 111.15, 36.55, 0.2], ["$6N545", 1, 111.15, 36.55, 111.45, 36.85, 0.2], ["$6N545", 1, 111.45, 36.85, 111.45, 38.1, 0.2], ["$6N545", 1, 111.45, 38.1, 111.65, 38.3, 0.2], ["$6N545", 1, 111.65, 38.3, 114.8, 38.3, 0.2], ["$6N545", 1, 114.8, 38.3, 115.55, 37.55, 0.2], ["$6N545", 1, 115.55, 37.55, 115.55, 36.85, 0.2], ["$6N545", 1, 115.55, 36.85, 115.25, 36.55, 0.2], ["$6N545", 1, 115.25, 36.55, 114.7, 36.55, 0.2], ["$6N545", 1, 114.7, 36.55, 114.325, 36.175, 0.2], ["$6N545", 1, 114.325, 36.175, 113.3, 35.2, 0.2], ["$6N545", 1, 113.3, 35.2, 112.521, 35.21, 0.2], ["+3V3", 1, 72.136, 46.314, 72.136, 45.732, 0.15], ["+3V3", 1, 76.6, 45, 76.808, 45.208, 0.15], ["+3V3", 1, 76.808, 45.208, 76.85, 45.25, 0.15], ["+3V3", 1, 77.458, 45.208, 76.808, 45.208, 0.487], ["+3V3", 1, 76.808, 45.208, 76.8, 45.208, 0.487], ["+3V3", 2, 77.425, 45.25, 76.875, 45.8, 0.15], ["+3V3", 2, 76.875, 45.8, 76.875, 50.825, 0.15], ["+3V3", 1, 76.875, 50.825, 76.65, 50.6, 0.15], ["+3V3", 1, 76.65, 50.6, 73.3, 50.6, 0.15], ["+3V3", 1, 73.3, 50.6, 73, 50.3, 0.15], ["+3V3", 1, 73, 50.3, 73, 49.225, 0.15], ["+3V3", 1, 73, 49.225, 71.55, 47.775, 0.15], ["+3V3", 1, 71.55, 47.775, 71.55, 46.631, 0.15], ["+3V3", 1, 71.55, 46.631, 71.55, 46.3, 0.15], ["+3V3", 1, 71.6, 46.55, 71.55, 46.631, 0.279], ["+3V3", 1, 71.55, 46.631, 71.3, 47.035, 0.279], ["+3V3", 1, 71.55, 46.3, 72.136, 45.732, 0.15], ["BUCK_PG", 1, 17.551, 29.225, 17.551, 29.925, 0.2], ["BUCK_PG", 1, 65.8, 43.8, 65.5, 44.1, 0.15], ["BUCK_PG", 1, 65.5, 44.1, 65.5, 47.6, 0.15], ["BUCK_PG", 2, 65.5, 47.6, 64.4, 48.7, 0.15], ["BUCK_PG", 1, 64.4, 48.7, 65.8, 50.1, 0.15], ["BUCK_PG", 1, 65.8, 50.1, 65.8, 51.7, 0.15], ["BUCK_PG", 2, 65.8, 51.7, 65.8, 62.7, 0.15], ["BUCK_PG", 1, 65.8, 62.7, 57.9, 70.6, 0.15], ["BUCK_PG", 1, 57.9, 70.6, 57.9, 89.2, 0.15], ["BUCK_PG", 1, 57.9, 89.2, 53, 94.1, 0.15], ["BUCK_PG", 1, 53, 94.1, 52.2, 94.1, 0.15], ["BUCK_PG", 1, 52.2, 94.1, 51.361, 94.468, 0.15], ["BUCK_PG", 1, 51.361, 94.468, 50.34, 95.576, 0.15], ["BUCK_PG", 1, 78.4, 45, 78.15, 44.45, 0.15], ["BUCK_PG", 1, 78.15, 44.45, 77.395, 44.48, 0.15], ["BUCK_PG", 1, 77.395, 44.48, 76.55, 44.15, 0.15], ["BUCK_PG", 1, 76.55, 44.15, 76.2, 43.8, 0.15], ["BUCK_PG", 1, 76.2, 43.8, 65.8, 43.8, 0.15], ["BUCK_PG", 1, 65.8, 43.8, 62.8, 43.8, 0.15], ["BUCK_PG", 1, 62.8, 43.8, 59.8, 40.8, 0.15], ["BUCK_PG", 1, 59.8, 40.8, 57.5, 40.8, 0.15], ["BUCK_PG", 1, 57.5, 40.8, 53.3, 36.6, 0.15], ["BUCK_PG", 1, 53.3, 36.6, 52.5, 36.6, 0.15], ["BUCK_PG", 1, 52.5, 36.6, 51.2, 35.3, 0.15], ["BUCK_PG", 2, 51.2, 35.3, 50.6, 34.7, 0.15], ["BUCK_PG", 2, 50.6, 34.7, 50.6, 33.9, 0.15], ["BUCK_PG", 2, 50.6, 33.9, 50.9, 33.6, 0.15], ["BUCK_PG", 1, 50.9, 33.6, 51.274, 33.332, 0.15], ["BUCK_PG", 1, 51.274, 33.332, 51.6, 32.7, 0.15], ["BUCK_PG", 1, 51.6, 32.7, 51.6, 32.3, 0.15], ["BUCK_PG", 1, 49.22, 29.925, 51.6, 32.3, 0.15], ["BUCK_PG", 1, 49.3, 30.1, 48.5, 30.9, 0.2], ["BUCK_PG", 1, 48.5, 30.9, 46.5, 30.9, 0.2], ["BUCK_PG", 1, 46.5, 30.9, 46.3, 30.7, 0.2], ["BUCK_PG", 2, 46.3, 30.7, 18.4, 30.7, 0.2], ["BUCK_PG", 2, 18.4, 30.7, 17.7, 30, 0.2], ["BUCK_PG", 1, 17.7, 30, 17.551, 29.925, 0.2], ["EFUSE_EN1", 1, 25.867, 47.5, 25.284, 47.5, 0.2], ["EFUSE_EN1", 1, 14.549, 44.3, 14.575, 40.3, 0.2], ["EFUSE_EN1", 1, 25.3, 47.6, 23.1, 49.8, 0.2], ["EFUSE_EN1", 1, 23.1, 49.8, 23.101, 50.051, 0.2], ["EFUSE_EN1", 1, 26, 47.3, 26.05, 47.05, 0.2], ["EFUSE_EN1", 1, 26.05, 47.05, 26.355, 46.8, 0.2], ["EFUSE_EN1", 1, 26.355, 46.8, 27.5, 46.8, 0.2], ["EFUSE_EN1", 1, 27.5, 46.8, 29.7, 44.6, 0.2], ["EFUSE_EN1", 1, 29.7, 44.6, 29.7, 40.1, 0.2], ["EFUSE_EN1", 2, 29.7, 40.1, 42.3, 40.1, 0.2], ["EFUSE_EN1", 2, 42.3, 40.1, 52.6, 29.8, 0.2], ["EFUSE_EN1", 2, 52.6, 29.8, 58.3, 29.8, 0.2], ["EFUSE_EN1", 1, 58.3, 29.8, 63.7, 24.4, 0.2], ["EFUSE_EN1", 1, 63.7, 24.4, 73.7, 24.4, 0.2], ["EFUSE_EN1", 1, 73.7, 24.4, 78.2, 19.9, 0.2], ["EFUSE_EN1", 1, 78.2, 19.9, 78.62, 19.9, 0.2], ["EFUSE_EN1", 1, 78.62, 19.9, 79.075, 19.682, 0.2], ["EFUSE_EN1", 1, 79.075, 19.682, 79.251, 19.464, 0.2], ["EFUSE_EN2", 1, 42.022, 78.001, 42.605, 78.001, 0.2], ["EFUSE_EN2", 1, 53.34, 81.201, 53.325, 83.775, 0.2], ["EFUSE_EN2", 1, 53.325, 83.775, 53.15, 83.95, 0.2], ["EFUSE_EN2", 2, 53.15, 83.95, 53.475, 84.275, 0.2], ["EFUSE_EN2", 2, 53.475, 85.2, 53.488, 84.95, 0.2], ["EFUSE_EN2", 2, 53.488, 84.95, 53.475, 84.918, 0.2], ["EFUSE_EN2", 2, 53.475, 84.918, 53.323, 84.523, 0.2], ["EFUSE_EN2", 2, 53.475, 84.275, 53.475, 84.918, 0.2], ["EFUSE_EN2", 2, 53.475, 84.918, 53.475, 85.2, 0.2], ["EFUSE_EN2", 2, 53.323, 84.523, 51.05, 82.25, 0.2], ["EFUSE_EN2", 2, 51.05, 82.25, 46.8, 82.25, 0.2], ["EFUSE_EN2", 2, 46.8, 82.25, 43.7, 79.05, 0.2], ["EFUSE_EN2", 1, 43.7, 79.05, 42.605, 78.001, 0.2], ["EFUSE_EN2", 1, 42.7, 78, 44.641, 76.059, 0.2], ["EFUSE_EN2", 1, 44.641, 76.059, 44.795, 75.675, 0.2], ["EFUSE_EN2", 1, 44.795, 75.675, 44.79, 75.451, 0.2], ["EFUSE_EN2", 2, 53.4, 83.8, 56.2, 81, 0.2], ["EFUSE_EN2", 2, 56.2, 81, 58.6, 81, 0.2], ["EFUSE_EN2", 1, 58.6, 81, 63.7, 75.9, 0.2], ["EFUSE_EN2", 1, 63.7, 75.9, 68.6, 75.9, 0.2], ["EFUSE_EN2", 1, 68.6, 75.9, 69.3, 75.2, 0.2], ["EFUSE_EN2", 2, 69.3, 75.2, 70, 74.5, 0.2], ["EFUSE_EN2", 2, 70, 74.5, 70, 53.9, 0.2], ["EFUSE_EN2", 2, 70, 53.9, 69.2, 53.1, 0.2], ["EFUSE_EN2", 2, 69.2, 53.1, 69.1, 51.2, 0.2], ["EFUSE_EN2", 1, 69.1, 51.2, 68.9, 51, 0.2], ["EFUSE_EN2", 1, 68.9, 51, 68.9, 46.1, 0.2], ["EFUSE_EN2", 1, 68.9, 46.1, 70.5, 44.5, 0.2], ["EFUSE_EN2", 2, 70.5, 44.5, 70.5, 39.3, 0.2], ["EFUSE_EN2", 2, 70.5, 39.3, 82.156, 27.644, 0.2], ["EFUSE_EN2", 2, 82.156, 27.644, 82.293, 27.297, 0.2], ["EFUSE_EN2", 2, 82.293, 27.297, 82.286, 27.094, 0.2], ["EFUSE_EN4", 1, 57.536, 47.5, 56.953, 47.5, 0.2], ["EFUSE_EN4", 1, 46.218, 44.3, 46.25, 40.3, 0.2], ["EFUSE_EN4", 1, 46.25, 40.3, 47.25, 39.3, 0.2], ["EFUSE_EN4", 1, 47.25, 39.3, 52, 39.3, 0.2], ["EFUSE_EN4", 1, 52, 39.3, 55.95, 43.25, 0.2], ["EFUSE_EN4", 1, 55.95, 43.25, 55.95, 46.45, 0.2], ["EFUSE_EN4", 1, 55.95, 46.45, 56.953, 47.5, 0.2], ["EFUSE_EN4", 1, 57, 47.6, 54.77, 50.051, 0.2], ["EFUSE_EN4", 1, 52, 39.2, 52.95, 38.25, 0.2], ["EFUSE_EN4", 1, 52.95, 38.25, 52.95, 37.3, 0.2], ["EFUSE_EN4", 2, 52.95, 37.3, 54.5, 35.75, 0.2], ["EFUSE_EN4", 1, 54.5, 35.75, 54.85, 35.4, 0.2], ["EFUSE_EN4", 1, 54.85, 35.4, 54.85, 32.25, 0.2], ["EFUSE_EN4", 1, 54.85, 32.25, 63.15, 23.95, 0.2], ["EFUSE_EN4", 1, 63.15, 23.95, 73.05, 23.95, 0.2], ["EFUSE_EN4", 1, 73.05, 23.95, 74.95, 22.05, 0.2], ["EFUSE_EN4", 1, 74.95, 22.05, 74.95, 20.75, 0.2], ["EFUSE_EN4", 1, 74.95, 20.75, 78.3, 17.4, 0.2], ["EFUSE_EN4", 1, 78.3, 17.4, 78.75, 17.4, 0.2], ["EFUSE_EN4", 1, 78.75, 17.4, 79.251, 16.924, 0.2], ["EFUSE_PG1", 2, 25.55, 45.6, 26.75, 46.8, 0.2], ["EFUSE_PG1", 2, 26.75, 46.8, 47.7, 46.8, 0.2], ["EFUSE_PG1", 2, 47.7, 46.8, 47.85, 46.65, 0.2], ["EFUSE_PG1", 2, 47.85, 46.65, 48.3, 46.65, 0.2], ["EFUSE_PG1", 2, 48.3, 46.65, 48.671, 46.868, 0.2], ["EFUSE_PG1", 2, 48.671, 46.868, 49.05, 47.55, 0.2], ["EFUSE_PG1", 1, 49.05, 47.55, 49.45, 47.95, 0.2], ["EFUSE_PG1", 1, 49.45, 47.95, 49.45, 49.25, 0.2], ["EFUSE_PG1", 2, 49.45, 49.25, 58.95, 49.25, 0.2], ["EFUSE_PG1", 2, 58.95, 49.25, 59.95, 50.25, 0.2], ["EFUSE_PG1", 2, 59.95, 50.25, 60.1, 53.75, 0.2], ["EFUSE_PG1", 2, 60.1, 53.75, 60.1, 59.8, 0.2], ["EFUSE_PG1", 2, 60.1, 59.8, 60.7, 60.4, 0.2], ["EFUSE_PG1", 2, 60.7, 60.4, 64.05, 60.4, 0.2], ["EFUSE_PG1", 1, 64.05, 60.4, 70.85, 60.4, 0.2], ["EFUSE_PG1", 2, 70.85, 60.4, 73.5, 60.4, 0.2], ["EFUSE_PG1", 2, 73.5, 60.4, 80.075, 53.779, 0.2], ["EFUSE_PG4", 1, 57.7, 45.3, 57.75, 45.05, 0.2], ["EFUSE_PG4", 1, 57.75, 45.05, 58.055, 44.8, 0.2], ["EFUSE_PG4", 1, 58.055, 44.8, 61.6, 44.8, 0.2], ["EFUSE_PG4", 1, 61.6, 44.8, 67.5, 50.7, 0.2], ["EFUSE_PG4", 2, 67.5, 50.7, 67.7, 50.5, 0.2], ["EFUSE_PG4", 2, 67.7, 50.5, 70.8, 50.5, 0.2], ["EFUSE_PG4", 2, 70.8, 50.5, 74.7, 54.4, 0.2], ["EFUSE_PG4", 1, 74.7, 54.4, 75, 54.7, 0.2], ["EFUSE_PG4", 1, 75, 54.7, 76.9, 54.7, 0.2], ["EFUSE_PG4", 1, 76.9, 54.7, 77.707, 54.305, 0.2], ["EFUSE_PG4", 1, 77.707, 54.305, 78.1, 53.8, 0.2], ["EFUSE_PG5", 2, 135, 45.7, 135.1, 40.3, 0.2], ["EFUSE_PG5", 2, 135.1, 40.3, 135.9, 39.5, 0.2], ["EFUSE_PG5", 1, 135.9, 39.5, 134.3, 37.9, 0.2], ["EFUSE_PG5", 2, 134.3, 37.9, 132.1, 35.7, 0.2], ["EFUSE_PG5", 2, 132.1, 35.7, 123, 35.7, 0.2], ["EFUSE_PG5", 1, 123, 35.7, 117.8, 40.9, 0.2], ["EFUSE_PG5", 2, 117.8, 40.9, 112.7, 46, 0.2], ["EFUSE_PG5", 2, 112.7, 46, 103.4, 46, 0.2], ["EFUSE_PG5", 1, 103.4, 46, 102.3, 47.1, 0.2], ["EFUSE_PG5", 1, 102.3, 47.1, 83.2, 47.1, 0.2], ["EFUSE_PG5", 2, 83.2, 47.1, 79.3, 51, 0.2], ["EFUSE_PG5", 1, 79.3, 51, 78, 51, 0.2], ["EFUSE_PG5", 1, 78, 51, 77.5, 51.5, 0.2], ["EFUSE_PG5", 1, 77.5, 51.5, 77.5, 51.9, 0.2], ["IOEXP_INT#", 1, 72.8, 45.8, 72.3, 45.3, 0.2], ["IOEXP_INT#", 1, 72.3, 45.3, 72.3, 44.5, 0.2], ["IOEXP_INT#", 2, 72.3, 44.5, 71.9, 44.1, 0.2], ["IOEXP_INT#", 2, 71.9, 44.1, 71.9, 41.2, 0.2], ["IOEXP_INT#", 1, 71.9, 41.2, 70.4, 39.7, 0.2], ["IOEXP_INT#", 1, 70.4, 39.7, 70.4, 38.3, 0.2], ["IOEXP_INT#", 2, 70.4, 38.3, 70.4, 36.8, 0.2], ["IOEXP_INT#", 2, 70.4, 36.8, 79.3, 27.9, 0.2], ["IOEXP_INT#", 2, 79.3, 27.9, 79.251, 20.734, 0.2], ["SDA", 1, 86.6, 28.7, 86.6, 29.65, 0.2], ["SDA", 1, 86.6, 29.65, 85.6, 30.65, 0.2], ["SDA", 1, 85.6, 30.65, 82, 30.65, 0.2], ["SDA", 1, 82, 30.65, 79.9, 32.75, 0.2], ["SDA", 1, 79.9, 32.75, 79.9, 33.45, 0.2], ["SDA", 1, 79.9, 33.45, 80.55, 34.1, 0.2], ["SDA", 1, 80.55, 34.1, 80.55, 35.6, 0.2], ["SDA", 1, 80.55, 35.6, 80.329, 35.818, 0.2], ["SDA", 1, 80.329, 35.818, 80.304, 35.843, 0.2], ["SDA", 1, 80.329, 36.5, 80.329, 35.818, 0.2], ["SDA", 1, 80.329, 35.818, 80.329, 35.811, 0.2], ["SDA", 1, 80.4, 36.5, 80.4, 36.1, 0.2], ["SDA", 1, 80.4, 36.1, 81.2, 35.3, 0.2], ["SDA", 1, 81.2, 35.3, 81.7, 35.3, 0.2], ["SDA", 2, 81.7, 35.3, 84.9, 38.5, 0.2], ["SDA", 2, 84.9, 38.5, 84.9, 40.8, 0.2], ["SDA", 2, 84.9, 40.8, 84.5, 41.2, 0.2], ["SDA", 2, 82.8, 44.1, 82.8, 45.45, 0.15], ["SDA", 1, 82.8, 45.45, 83.75, 46.4, 0.15], ["SDA", 2, 83.75, 46.4, 83.82, 47.102, 0.15], ["SDA", 2, 83.82, 47.102, 83.637, 47.611, 0.15], ["SDA", 2, 83.637, 47.611, 78.75, 52.45, 0.15], ["UP_VBUS_DET", 1, 83.556, 27.094, 83.578, 27.447, 0.2], ["UP_VBUS_DET", 1, 83.578, 27.447, 83.35, 28.05, 0.2], ["UP_VBUS_DET", 1, 83.35, 28.05, 83.1, 28.3, 0.2], ["UP_VBUS_DET", 1, 83.1, 28.3, 71.1, 28.3, 0.2], ["UP_VBUS_DET", 1, 71.1, 28.3, 70.5, 27.7, 0.2], ["UP_VBUS_DET", 1, 70.5, 27.7, 70.2, 27.6, 0.2], ["UP_VBUS_DET", 1, 70.2, 27.6, 69.9, 27.184, 0.2], ["UP_VBUS_DET", 1, 69.9, 27.184, 69.9, 25.9, 0.2], ["UP_VBUS_DET", 1, 69.9, 25.9, 69.1, 25.1, 0.2], ["UP_VBUS_DET", 1, 69.1, 25.1, 64.1, 25.1, 0.2], ["UP_VBUS_DET", 2, 64.1, 25.1, 56.7, 25.1, 0.2], ["UP_VBUS_DET", 2, 56.7, 25.1, 55.8, 26, 0.2], ["UP_VBUS_DET", 2, 55.8, 26, 55.5, 26, 0.2], ["UP_VBUS_DET", 2, 55.5, 26, 47.8, 33.7, 0.2], ["UP_VBUS_DET", 2, 47.8, 33.7, 47.4, 33.7, 0.2], ["UP_VBUS_DET", 2, 47.4, 33.7, 41.7, 39.4, 0.2], ["UP_VBUS_DET", 1, 41.7, 39.4, 39.7, 41.4, 0.2], ["UP_VBUS_DET", 1, 39.7, 41.4, 39.7, 44.7, 0.2], ["UP_VBUS_DET", 2, 39.7, 44.7, 41.1, 46.1, 0.2], ["UP_VBUS_DET", 1, 41.1, 46.1, 41.1, 58.4, 0.2], ["UP_VBUS_DET", 1, 41.1, 58.4, 38.349, 61.229, 0.2], ["VBUS_EN1", 1, 79.251, 18.194, 78.6, 18.2, 0.2], ["VBUS_EN1", 2, 78.6, 18.2, 77.2, 19.6, 0.2], ["VBUS_EN1", 2, 77.2, 19.6, 73.6, 19.6, 0.2], ["VBUS_EN1", 1, 73.6, 19.6, 70.9, 22.3, 0.2], ["VBUS_EN1", 1, 70.9, 22.3, 58.3, 22.3, 0.2], ["VBUS_EN1", 1, 58.3, 22.3, 55.3, 25.3, 0.2], ["VBUS_EN1", 2, 55.3, 25.3, 47.4, 33.2, 0.2], ["VBUS_EN1", 2, 47.4, 33.2, 15.9, 33.2, 0.2], ["VBUS_EN1", 2, 15.9, 33.2, 14.6, 34.5, 0.2], ["VBUS_EN1", 1, 14.6, 34.5, 6.5, 42.6, 0.2], ["VBUS_EN1", 1, 6.5, 42.6, 6.599, 64.8, 0.2], ["VBUS_EN1", 1, 6.599, 64.8, 6.9, 65.1, 0.2], ["VBUS_EN1", 1, 6.9, 65.1, 9.2, 65.1, 0.2], ["VBUS_EN1", 1, 9.2, 65.1, 11.2, 67.1, 0.2], ["VBUS_EN1", 2, 11.2, 67.1, 27.4, 67.1, 0.2], ["VBUS_EN1", 2, 27.4, 67.1, 30.729, 63.769, 0.2], ["VBUS_EN4", 1, 79.251, 15.654, 79.3, 15.9, 0.2], ["VBUS_EN4", 2, 79.3, 15.9, 79.3, 18.7, 0.2], ["VBUS_EN4", 2, 79.3, 18.7, 72, 26, 0.2], ["VBUS_EN4", 2, 72, 26, 69.7, 26, 0.2], ["VBUS_EN4", 2, 69.7, 26, 67, 28.7, 0.2], ["VBUS_EN4", 1, 67, 28.7, 66.5, 29.2, 0.2], ["VBUS_EN4", 1, 66.5, 29.2, 62.2, 29.2, 0.2], ["VBUS_EN4", 1, 62.2, 29.2, 54.6, 36.8, 0.2], ["VBUS_EN4", 2, 54.6, 36.8, 52.7, 38.7, 0.2], ["VBUS_EN4", 2, 52.7, 38.7, 46, 38.7, 0.2], ["VBUS_EN4", 2, 46, 38.7, 44.3, 40.4, 0.2], ["VBUS_EN4", 2, 44.3, 40.4, 42.9, 40.4, 0.2], ["VBUS_EN4", 2, 42.9, 40.4, 42.7, 40.6, 0.2], ["VBUS_EN4", 2, 42.7, 40.6, 41.7, 40.6, 0.2], ["VBUS_EN4", 2, 41.7, 40.6, 41.5, 40.8, 0.2], ["VBUS_EN4", 1, 41.5, 40.8, 40.4, 41.9, 0.2], ["VBUS_EN4", 1, 40.4, 41.9, 40.4, 51.5, 0.2], ["VBUS_EN4", 1, 40.4, 51.5, 30.729, 61.229, 0.2], ["VDAC1", 1, 15.232, 20.701, 15.232, 21.271, 0.2], ["VDAC1", 1, 78.08, 37.259, 77.38, 37.259, 0.2], ["VDAC1", 1, 78.08, 37.76, 77.38, 37.76, 0.2], ["VDAC1", 1, 15.232, 21.271, 15.3, 22.1, 0.2], ["VDAC1", 2, 15.3, 22.1, 19.7, 22, 0.2], ["VDAC1", 2, 19.7, 22, 20.4, 21.3, 0.2], ["VDAC1", 2, 20.4, 21.3, 22.3, 21.3, 0.2], ["VDAC1", 2, 22.3, 21.3, 22.6, 21.6, 0.2], ["VDAC1", 1, 22.6, 21.6, 23.7, 21.6, 0.2], ["VDAC1", 1, 23.7, 21.6, 26.9, 24.8, 0.2], ["VDAC1", 1, 26.9, 24.8, 33.2, 24.8, 0.2], ["VDAC1", 2, 33.2, 24.8, 35.2, 26.8, 0.2], ["VDAC1", 2, 35.2, 26.8, 35.6, 26.8, 0.2], ["VDAC1", 2, 35.6, 26.8, 38, 29.2, 0.2], ["VDAC1", 2, 38, 29.2, 39.6, 29.2, 0.2], ["VDAC1", 2, 39.6, 29.2, 40.4, 30, 0.2], ["VDAC1", 1, 40.4, 30, 43, 32.6, 0.2], ["VDAC1", 1, 43, 32.6, 45, 32.6, 0.2], ["VDAC1", 1, 45, 32.6, 45.82, 32.216, 0.2], ["VDAC1", 1, 45.82, 32.216, 46.18, 31.784, 0.2], ["VDAC1", 1, 46.18, 31.784, 47, 31.4, 0.2], ["VDAC1", 1, 47, 31.4, 49.6, 31.4, 0.2], ["VDAC1", 1, 49.6, 31.4, 50.9, 32.7, 0.2], ["VDAC1", 2, 50.9, 32.7, 60.8, 32.7, 0.2], ["VDAC1", 2, 60.8, 32.7, 65.4, 37.3, 0.2], ["VDAC1", 2, 65.4, 37.3, 69.7, 37.3, 0.2], ["VDAC1", 1, 69.7, 37.3, 70, 37.6, 0.2], ["VDAC1", 1, 70, 37.6, 76.88, 37.6, 0.2], ["VDAC1", 1, 76.88, 37.6, 77.24, 37.43, 0.2], ["VDAC1", 1, 77.24, 37.43, 77.38, 37.259, 0.2], ["VDAC1", 1, 77.2, 37.6, 77.38, 37.76, 0.2], ["VDAC2", 1, 52.657, 104.8, 52.657, 105.371, 0.2], ["VDAC2", 1, 81.079, 38.76, 81.079, 39.2, 0.2], ["VDAC2", 1, 81.079, 38.26, 81.079, 38.7, 0.2], ["VDAC3", 1, 141.036, 104.8, 141.036, 105.371, 0.2], ["VDAC3", 1, 141.036, 105.371, 141, 105.2, 0.2], ["VDAC3", 2, 141, 105.2, 138.5, 105.2, 0.2], ["VDAC3", 2, 138.5, 105.2, 118.6, 85.3, 0.2], ["VDAC3", 2, 118.6, 85.3, 117.6, 85.3, 0.2], ["VDAC3", 2, 117.6, 85.3, 116.4, 84.1, 0.2], ["VDAC3", 2, 116.4, 84.1, 116.4, 77.4, 0.2], ["VDAC3", 1, 116.4, 77.4, 111.3, 72.3, 0.2], ["VDAC3", 1, 111.3, 72.3, 105.6, 72.3, 0.2], ["VDAC3", 1, 105.6, 72.3, 105.1, 71.8, 0.2], ["VDAC3", 1, 105.1, 71.8, 102.8, 71.8, 0.2], ["VDAC3", 1, 102.8, 71.8, 102.1, 71.1, 0.2], ["VDAC3", 1, 102.1, 71.1, 102.1, 70.7, 0.2], ["VDAC3", 1, 102.1, 70.7, 101.8, 70.4, 0.2], ["VDAC3", 2, 101.8, 70.4, 96.3, 64.9, 0.2], ["VDAC3", 1, 96.3, 64.9, 94.4, 63, 0.2], ["VDAC3", 1, 94.4, 63, 94.4, 59.4, 0.2], ["VDAC3", 1, 94.4, 59.4, 94.764, 58.835, 0.2], ["VDAC3", 1, 94.764, 58.835, 95.5, 58.5, 0.2], ["VDAC3", 2, 95.5, 58.5, 96, 58, 0.2], ["VDAC3", 2, 96, 58, 96, 57, 0.2], ["VDAC3", 2, 96, 57, 96.36, 56.153, 0.2], ["VDAC3", 2, 96.36, 56.153, 98.54, 54.047, 0.2], ["VDAC3", 2, 98.54, 54.047, 98.9, 53.2, 0.2], ["VDAC3", 2, 98.9, 53.2, 98.9, 49.4, 0.2], ["VDAC4", 1, 46.901, 20.701, 46.9, 21.187, 0.2], ["VDAC4", 1, 46.9, 21.187, 46.988, 21.275, 0.2], ["VDAC4", 1, 46.988, 21.275, 47.075, 21.275, 0.2], ["VDAC4", 2, 47.075, 21.275, 47.925, 21.275, 0.2], ["VDAC4", 2, 47.925, 21.275, 49.95, 23.3, 0.2], ["VO4", 2, 45.5, 44.45, 46.65, 44.45, 0.3], ["VO4", 2, 46.65, 44.45, 47.95, 45.75, 0.3], ["VO4", 2, 47.95, 45.75, 48.4, 45.75, 0.3], ["VO4", 2, 48.4, 45.75, 49.9, 47.25, 0.3], ["GND", 1, 78.222, 35.226, 77.8, 35.4, 0.3], ["GND", 1, 108.215, 31.926, 107.2, 32.8, 0.3], ["SCL", 1, 79.329, 36.51, 79.329, 35.99, 0.2], ["SCL", 2, 126.3, 48.7, 126.4, 48.7, 0.2], ["SCL", 2, 126.4, 48.7, 126.5, 48.8, 0.2], ["SDA", 2, 81.5, 49.8, 81.6, 49.9, 0.2], ["SDA", 2, 102.5, 38.4, 102.5, 48.7, 0.2], ["$6N532", 1, 78.829, 39.51, 78.829, 40.21, 0.2], ["$6N547", 1, 108.821, 36.21, 108.821, 36.91, 0.2], ["+3V3", 1, 79.3, 40.6, 79.3, 40.4, 0.195], ["+3V3", 1, 109.3, 37.25, 109.3, 37.15, 0.195], ["EFUSE_EN1", 1, 29.4, 40.05, 19.8, 40.05, 0.2], ["EFUSE_EN1", 1, 19.8, 40.05, 19.2, 40.65, 0.2], ["EFUSE_EN1", 2, 19.2, 40.65, 18.7, 41.15, 0.2], ["EFUSE_EN1", 2, 18.7, 41.15, 17, 41.15, 0.2], ["EFUSE_EN1", 2, 17, 41.15, 15, 39.15, 0.2], ["EFUSE_EN1", 1, 15, 39.15, 14.6, 39.55, 0.2], ["EFUSE_EN1", 1, 14.6, 39.55, 14.6, 40.25, 0.2], ["EFUSE_FLT3", 1, 119.7, 36.45, 117.7, 38.45, 0.2], ["EFUSE_FLT3", 1, 117.7, 38.45, 115.6, 38.45, 0.2], ["EFUSE_FLT3", 2, 115.6, 38.45, 115.2, 38.85, 0.2], ["EFUSE_FLT3", 2, 115.2, 38.85, 106.35, 38.85, 0.2], ["EFUSE_FLT3", 1, 106.35, 38.85, 96.85, 38.85, 0.2], ["EFUSE_FLT3", 1, 96.85, 38.85, 96.6, 38.85, 0.2], ["EFUSE_FLT3", 1, 97.1, 39.1, 96.85, 38.85, 0.2], ["EFUSE_FLT3", 1, 96.85, 38.85, 95.4, 37.4, 0.2], ["EFUSE_FLT3", 1, 96.6, 38.85, 95.2, 37.45, 0.2], ["EFUSE_FLT3", 1, 95.2, 37.45, 82.85, 37.45, 0.2], ["EFUSE_FLT3", 1, 82.85, 37.45, 82.65, 37.25, 0.2], ["EFUSE_FLT3", 2, 82.65, 37.25, 80.65, 39.25, 0.2], ["EFUSE_FLT3", 2, 80.65, 39.25, 80.2, 39.25, 0.2], ["EFUSE_FLT3", 2, 80.2, 39.25, 77.45, 42, 0.2], ["EFUSE_FLT3", 2, 77.45, 42, 77.45, 43.55, 0.2], ["EFUSE_FLT3", 2, 77.45, 43.55, 76.15, 44.85, 0.2], ["EFUSE_FLT3", 2, 76.15, 44.85, 76.1, 47.7, 0.2], ["SCL", 2, 109.9, 33, 109.5, 33.4, 0.15], ["SCL", 2, 109.5, 33.4, 108.41, 33.582, 0.15], ["SCL", 2, 108.41, 33.582, 108.25, 33.7, 0.15], ["SCL", 2, 108.25, 33.7, 108.088, 33.8, 0.15], ["SCL", 2, 108.088, 33.8, 106.1, 33.8, 0.15], ["SCL", 1, 106.1, 33.8, 105.9, 34, 0.15], ["SCL", 1, 105.9, 34, 104.6, 34, 0.15], ["SCL", 2, 104.6, 34, 104.8, 34.2, 0.15], ["SCL", 2, 104.8, 34.2, 104.8, 39.3, 0.15], ["SCL", 2, 104.8, 39.3, 108.4, 42.9, 0.15], ["SCL", 1, 108.4, 42.9, 111.9, 39.4, 0.15], ["SCL", 1, 111.9, 39.4, 115.7, 39.4, 0.15], ["SCL", 2, 115.9, 37.7, 115.2, 37.7, 0.15], ["SCL", 2, 115.2, 37.7, 114.8, 37.3, 0.15], ["VBUS_EN5", 1, 108.95, 61.225, 110.175, 62.45, 0.2], ["VBUS_EN5", 1, 110.175, 62.45, 112.75, 62.5, 0.2], ["VDAC3", 1, 111.069, 35.461, 111.769, 35.461, 0.2], ["VDAC3", 1, 111.069, 34.96, 111.769, 34.96, 0.2], ["VDAC3", 2, 98.95, 49.35, 100.8, 47.5, 0.2], ["VDAC3", 2, 100.8, 47.5, 100.8, 44.3, 0.2], ["VDAC3", 2, 100.8, 44.3, 101.85, 43.25, 0.2], ["VDAC3", 1, 101.85, 43.25, 106.95, 43.25, 0.2], ["VDAC3", 1, 106.95, 43.25, 110.8, 39.4, 0.2], ["VDAC3", 1, 110.8, 39.4, 110.8, 38.2, 0.2], ["VDAC3", 2, 110.8, 38.2, 111.45, 37.55, 0.2], ["VDAC3", 2, 111.45, 37.55, 111.6, 35.6, 0.2], ["VDAC3", 1, 111.6, 35.6, 111.769, 35.461, 0.2], ["VDAC3", 1, 111.65, 35.3, 111.769, 34.96, 0.2], ["VDAC4", 1, 81.079, 37.76, 81.779, 37.76, 0.2], ["VDAC4", 1, 81.079, 37.259, 81.779, 37.259, 0.2], ["VDAC4", 2, 50.05, 23.3, 53.55, 19.8, 0.2], ["VDAC4", 2, 53.55, 19.8, 54.7, 19.8, 0.2], ["VDAC4", 1, 54.7, 19.8, 55.65, 18.85, 0.2], ["VDAC4", 1, 55.65, 18.85, 55.65, 18.25, 0.2], ["VDAC4", 1, 55.65, 18.25, 56.05, 17.85, 0.2], ["VDAC4", 1, 56.05, 17.85, 59.5, 17.85, 0.2], ["VDAC4", 1, 59.5, 17.85, 60.2, 17.15, 0.2], ["VDAC4", 2, 60.2, 17.15, 61.15, 16.2, 0.2], ["VDAC4", 2, 61.15, 16.2, 74.95, 16.2, 0.2], ["VDAC4", 1, 74.95, 16.2, 77.95, 16.2, 0.2], ["VDAC4", 2, 77.95, 16.2, 78.9, 15.25, 0.2], ["VDAC4", 2, 78.9, 15.25, 79.65, 15.25, 0.2], ["VDAC4", 2, 79.65, 15.25, 79.95, 15.55, 0.2], ["VDAC4", 2, 79.95, 15.55, 79.95, 28.9, 0.2], ["VDAC4", 2, 79.95, 28.9, 78.3, 30.55, 0.2], ["VDAC4", 1, 78.3, 30.55, 78.3, 32.55, 0.2], ["VDAC4", 1, 78.3, 32.55, 79.85, 34.1, 0.2], ["VDAC4", 1, 79.85, 34.1, 79.85, 34.65, 0.2], ["VDAC4", 2, 79.85, 34.65, 81.75, 36.55, 0.2], ["VDAC4", 2, 81.75, 36.55, 81.75, 37.2, 0.2], ["VDAC4", 1, 81.75, 37.2, 81.779, 37.259, 0.2], ["VDAC4", 1, 81.8, 37.5, 81.779, 37.76, 0.2], ["SCL", 1, 74.224, 52.652, 74.224, 53.777, 0.2], ["SCL", 16, 115.9, 39.2, 116.3, 38.8, 0.2], ["SCL", 16, 116.3, 38.8, 116.3, 38.1, 0.2], ["SCL", 16, 116.3, 38.1, 115.9, 37.7, 0.2], ["SCL", 16, 115.9, 37.7, 115.8, 37.7, 0.2], ["SCL", 16, 115.8, 37.7, 115.4, 37.3, 0.2], ["SCL", 16, 115.4, 37.3, 115.3, 37.3, 0.2], ["SCL", 16, 115.3, 37.3, 115.2, 37.2, 0.2], ["SCL", 1, 106.1, 33.5, 106.1, 30.2, 0.2], ["SCL", 1, 106.1, 30.2, 107.5, 28.8, 0.2], ["SCL", 16, 116.3, 38.9, 117, 38.9, 0.2], ["SCL", 16, 117, 38.9, 119.9, 41.8, 0.2], ["SCL", 16, 119.9, 41.8, 119.9, 42.1, 0.2], ["SCL", 2, 119.9, 42.1, 122, 44.2, 0.2], ["SCL", 2, 122, 44.2, 122, 44.5, 0.2], ["SCL", 2, 122, 44.5, 122.3, 44.8, 0.2], ["SCL", 2, 122.3, 44.8, 122.4, 44.8, 0.2], ["SCL", 2, 122.4, 44.8, 126.1, 48.5, 0.2], ["SCL", 2, 126.1, 48.5, 126.1, 48.6, 0.2], ["SCL", 2, 126.1, 48.6, 126.2, 48.7, 0.2], ["SCL", 2, 77.2, 52, 73.7, 52, 0.2], ["SCL", 2, 73.7, 52, 72.9, 51.2, 0.2], ["SCL", 1, 72.9, 51.2, 73.8, 51.2, 0.2], ["SCL", 1, 73.8, 51.2, 74.2, 51.6, 0.2], ["SCL", 1, 74.2, 51.6, 74.2, 51.9, 0.2], ["SCL", 2, 72.6, 51.2, 71.4, 50, 0.2], ["SCL", 2, 71.4, 50, 61.1, 50, 0.2], ["SCL", 16, 61.1, 50, 48.3, 50, 0.2], ["SCL", 16, 48.3, 50, 48.2, 49.9, 0.2], ["SCL", 16, 60.2, 50.1, 60.2, 62.2, 0.2], ["SCL", 16, 60.2, 62.2, 57.3, 65.1, 0.2], ["SCL", 16, 37.2, 65.1, 36.7, 64.6, 0.2], ["SCL", 16, 47.9, 65.1, 47.9, 75.8, 0.2], ["SCL", 16, 57.3, 65.1, 47.9, 65.1, 0.2], ["SCL", 16, 47.9, 65.1, 37.2, 65.1, 0.2], ["SCL", 16, 47.9, 75.8, 48, 75.9, 0.2], ["SCL", 1, 48, 75.9, 47.9, 75.8, 0.2], ["SCL", 1, 47.9, 75.8, 47.9, 73.3, 0.2], ["SCL", 1, 47.9, 73.3, 48.2, 73, 0.2], ["SCL", 1, 48.2, 73, 50.7, 73, 0.2], ["SCL", 1, 50.7, 73, 52.4, 74.7, 0.2], ["SCL", 16, 35, 64.6, 34.5, 65.1, 0.2], ["SCL", 16, 6.7, 65.1, 6.5, 64.9, 0.2], ["SCL", 16, 6.5, 64.9, 6.5, 60.3, 0.2], ["SCL", 16, 6.5, 60.3, 7.6, 59.2, 0.2], ["SCL", 16, 7.6, 59.2, 28.4, 59.2, 0.2], ["SCL", 16, 28.4, 59.2, 29.1, 58.5, 0.2], ["SCL", 16, 29.1, 58.5, 29.1, 58.4, 0.2], ["SCL", 1, 29.1, 58.4, 29.1, 58, 0.2], ["SCL", 1, 29.1, 58, 28.6, 57.5, 0.2], ["SCL", 1, 28.6, 57.5, 22.1, 57.5, 0.2], ["SCL", 1, 22.1, 57.5, 15.7, 51.1, 0.2], ["SCL", 16, 6.8, 65.1, 6.8, 87.6, 0.2], ["SCL", 16, 34.5, 65.1, 6.8, 65.1, 0.2], ["SCL", 16, 6.8, 65.1, 6.7, 65.1, 0.2], ["SCL", 1, 6.8, 87.6, 6.8, 93.6, 0.2], ["SDA", 1, 73.576, 52.652, 73.576, 53.777, 0.2], ["SDA", 2, 84.4, 41.2, 82.9, 42.7, 0.2], ["SDA", 2, 82.9, 42.7, 82.9, 44, 0.2], ["SDA", 2, 82.9, 44, 82.8, 44.1, 0.2], ["SDA", 16, 81.3, 49.9, 78.9, 49.9, 0.2], ["SDA", 16, 78.9, 49.9, 75.5, 53.3, 0.2], ["SDA", 16, 75.5, 53.3, 74.7, 53.3, 0.2], ["SDA", 16, 74.7, 53.3, 73.6, 54.4, 0.2], ["SDA", 1, 73.6, 54.4, 73.6, 53.8, 0.2], ["SDA", 1, 73.3, 54.4, 72.9, 54.8, 0.2], ["SDA", 1, 72.9, 54.8, 71, 54.8, 0.2], ["SDA", 1, 71, 54.8, 70.9, 54.7, 0.2], ["SDA", 1, 70.9, 54.7, 68.9, 54.7, 0.2], ["SDA", 1, 68.9, 54.7, 67.8, 55.8, 0.2], ["SDA", 2, 67.8, 55.8, 67, 55, 0.2], ["SDA", 2, 67, 55, 66.6, 55, 0.2], ["SDA", 2, 66.6, 55, 66.5, 54.9, 0.2], ["SDA", 1, 66.5, 54.9, 64.4, 54.9, 0.2], ["SDA", 1, 64.4, 54.9, 59.7, 59.6, 0.2], ["SDA", 1, 59.7, 59.6, 55.8, 59.6, 0.2], ["SDA", 1, 55.8, 59.6, 49.2, 53, 0.2], ["SDA", 16, 60.9, 58.5, 60.9, 64, 0.2], ["SDA", 16, 60.9, 64, 53.9, 71, 0.2], ["SDA", 16, 53.9, 71, 53.3, 71, 0.2], ["SDA", 16, 53.3, 71, 49.5, 74.8, 0.2], ["SDA", 16, 49.5, 74.8, 49.5, 75.5, 0.2], ["SDA", 16, 49.5, 75.5, 48.4, 76.6, 0.2], ["SDA", 16, 48.4, 76.6, 45.2, 76.6, 0.2], ["SDA", 16, 45.2, 76.6, 34.4, 65.8, 0.2], ["SDA", 16, 49.5, 75.6, 50.9, 77, 0.2], ["SDA", 16, 50.9, 77, 51, 77, 0.2], ["SDA", 16, 51, 77, 51.1, 77.1, 0.2], ["SDA", 16, 33.9, 66, 15.5, 84.4, 0.2], ["SDA", 16, 15.5, 84.4, 15.5, 85.5, 0.2], ["SDA", 16, 15.5, 85.5, 15.3, 85.7, 0.2], ["SDA", 16, 15.3, 85.7, 15, 85.7, 0.2], ["SDA", 16, 15, 85.7, 13.2, 87.5, 0.2], ["SDA", 16, 13.2, 87.5, 11.5, 87.5, 0.2], ["SDA", 16, 11.5, 87.5, 11.4, 87.6, 0.2], ["SDA", 2, 11.4, 87.6, 11.4, 94, 0.2], ["SDA", 2, 11.4, 94, 9.7, 95.7, 0.2], ["SDA", 16, 102.5, 57.2, 102.5, 64.9, 0.2], ["SDA", 16, 102.5, 64.9, 102.7, 65.1, 0.2], ["SDA", 16, 102.7, 65.1, 128.7, 65.1, 0.2], ["SDA", 16, 128.7, 65.1, 138.9, 75.3, 0.2], ["SDA", 16, 138.9, 75.3, 139.6, 75.3, 0.2], ["SDA", 16, 139.6, 75.3, 139.7, 75.4, 0.2], ["$1N236", 1, 5.499, 101.11, 4.7, 100.3, 0.3], ["$1N236", 1, 4.7, 100.3, 4.7, 94.8, 0.3], ["$1N236", 1, 4.7, 94.8, 3.434, 93.5, 0.3], ["+12V", 1, 6.5, 101.11, 6, 101.11, 0.3], ["+12V", 1, 6, 101.11, 6.2, 100.9, 0.3], ["+12V", 1, 6, 101.11, 6.2, 100.9, 0.3], ["+12V", 1, 6.2, 100.9, 6.2, 100, 0.3], ["+12V", 1, 6.2, 100, 8.2, 97.9, 0.3], ["+12V", 1, 8.2, 97.9, 8.2, 94.9, 0.3], ["+12V", 1, 8.2, 94.9, 9.566, 93.5, 0.3], ["+3V3", 1, 95.3, 74.5, 95.4, 72.8, 0.279], ["EFUSE_FLT2", 1, 46.1, 82.7, 46.1, 83.55, 0.2], ["EFUSE_FLT2", 1, 46.1, 83.55, 46.6, 84.05, 0.2], ["EFUSE_FLT2", 2, 46.6, 84.05, 48.2, 85.65, 0.2], ["EFUSE_FLT2", 2, 48.2, 85.65, 55.25, 85.65, 0.2], ["EFUSE_FLT2", 2, 55.25, 85.65, 56.25, 84.65, 0.2], ["EFUSE_FLT2", 2, 56.25, 84.65, 67.8, 84.65, 0.2], ["EFUSE_FLT2", 2, 67.8, 84.65, 80.75, 71.7, 0.2], ["EFUSE_FLT2", 2, 80.75, 71.7, 80.75, 52.35, 0.2], ["EFUSE_FLT2", 2, 80.75, 52.35, 80.55, 52.15, 0.2], ["EFUSE_FLT2", 2, 80.55, 52.15, 80.55, 51.45, 0.2], ["EFUSE_FLT2", 2, 80.55, 51.45, 80.85, 51.15, 0.2], ["EFUSE_FLT2", 2, 80.85, 51.15, 81.35, 51.15, 0.2], ["EFUSE_FLT2", 2, 81.35, 51.15, 84.4, 48.1, 0.2], ["EFUSE_FLT2", 2, 84.4, 48.1, 84.4, 45.8, 0.2], ["EFUSE_FLT2", 1, 84.4, 45.8, 83.15, 44.55, 0.2], ["EFUSE_FLT2", 1, 83.15, 44.55, 80.9, 44.55, 0.2], ["EFUSE_FLT2", 1, 80.9, 44.55, 80.5, 44.15, 0.2], ["EFUSE_FLT2", 2, 80.5, 44.15, 79.2, 42.85, 0.2], ["EFUSE_FLT2", 1, 79.2, 42.85, 77.2, 42.8, 0.2], ["EFUSE_FLT2", 1, 77.2, 42.8, 76.9, 42.5, 0.2], ["EFUSE_FLT2", 1, 76.9, 42.5, 76.5, 42.5, 0.2], ["EFUSE_FLT2", 1, 76.5, 42.5, 75.998, 42.722, 0.2], ["EFUSE_FLT2", 1, 75.998, 42.722, 75.7, 43.05, 0.2], ["EFUSE_FLT2", 2, 75.7, 43.05, 75.2, 43.55, 0.2], ["EFUSE_FLT2", 2, 75.2, 43.55, 75.2, 44.25, 0.2], ["EFUSE_FLT2", 2, 75.2, 44.25, 75, 44.45, 0.2], ["EFUSE_FLT2", 1, 75, 44.45, 75.5, 45.4, 0.2], ["KEY_OE#", 1, 84.826, 27.094, 84.8, 29.9, 0.2], ["KEY_OE#", 2, 84.8, 29.9, 87.9, 33, 0.2], ["KEY_OE#", 2, 87.9, 33, 87.9, 40.1, 0.2], ["KEY_OE#", 1, 87.9, 40.1, 89.1, 41.3, 0.2], ["KEY_OE#", 1, 89.1, 41.3, 89.2, 42.8, 0.2], ["KEY_OE#", 2, 89.2, 42.8, 89.3, 57.6, 0.2], ["KEY_OE#", 2, 89.3, 57.6, 90.3, 58.6, 0.2], ["KEY_OE#", 1, 90.3, 58.6, 90.7, 59, 0.2], ["KEY_OE#", 1, 90.7, 59, 90.7, 61.8, 0.2], ["KEY_OE#", 2, 90.7, 61.8, 90.7, 63.7, 0.2], ["KEY_OE#", 1, 90.7, 63.7, 90.4, 64, 0.2], ["KEY_OE#", 1, 90.4, 64, 90.4, 71.7, 0.2], ["KEY_OE#", 1, 90.4, 71.7, 94.7, 76, 0.2], ["KEY_OE#", 1, 94.7, 76, 97.4, 76, 0.2], ["KEY_OE#", 1, 97.4, 76, 98.24, 76.366, 0.2], ["KEY_OE#", 1, 98.24, 76.366, 100.5, 78.8, 0.2], ["KEY_OE#", 2, 100.5, 78.8, 104.3, 78.8, 0.2], ["KEY_OE#", 2, 104.3, 78.8, 105.8, 77.3, 0.2], ["KEY_OE#", 2, 105.8, 77.3, 106.2, 77.3, 0.2], ["KEY_OE#", 2, 106.2, 77.3, 111.1, 72.4, 0.2], ["KEY_OE#", 2, 111.1, 72.4, 111.1, 71.6, 0.2], ["KEY_OE#", 1, 111.1, 71.6, 113.634, 69.241, 0.2], ["KEY_OE#", 1, 113.634, 69.241, 114, 68.4, 0.2], ["KEY_OE#", 1, 114, 68.4, 114, 66.4, 0.2], ["KEY_OE#", 2, 114, 66.4, 116.571, 63.769, 0.2], ["KEY_RCLK", 1, 92.446, 27.094, 92.45, 29.9, 0.2], ["KEY_RCLK", 1, 92.45, 29.9, 93.9, 31.35, 0.2], ["KEY_RCLK", 2, 93.9, 31.35, 93.9, 34.35, 0.2], ["KEY_RCLK", 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88, 28.206, 88, 32.15, 0.2], ["KEY_SER", 2, 88, 32.15, 88.35, 32.5, 0.2], ["KEY_SER", 2, 88.35, 32.5, 88.35, 39.3, 0.2], ["KEY_SER", 2, 88.35, 39.3, 88.55, 39.5, 0.2], ["KEY_SER", 1, 88.55, 39.5, 91.65, 42.6, 0.2], ["KEY_SER", 1, 91.65, 42.6, 91.65, 42.85, 0.2], ["KEY_SER", 2, 91.65, 42.85, 91.65, 46.55, 0.2], ["KEY_SER", 2, 91.65, 46.55, 97.4, 52.3, 0.2], ["KEY_SER", 1, 97.4, 52.3, 97.9, 52.8, 0.2], ["KEY_SER", 1, 97.9, 52.8, 101.95, 52.8, 0.2], ["KEY_SER", 1, 101.95, 52.8, 103.15, 54, 0.2], ["KEY_SER", 2, 103.15, 54, 105.7, 56.55, 0.2], ["KEY_SER", 2, 105.7, 56.55, 108.6, 56.55, 0.2], ["KEY_SER", 1, 108.6, 56.55, 109.9, 57.85, 0.2], ["KEY_SER", 2, 109.9, 57.85, 107.989, 59.674, 0.2], ["KEY_SER", 2, 107.989, 59.674, 107.7, 60.35, 0.2], ["KEY_SER", 2, 107.7, 60.35, 107.7, 62.5, 0.2], ["KEY_SER", 2, 107.7, 62.5, 108.951, 63.769, 0.2], ["KEY_SRCLK", 1, 88.636, 27.094, 88.65, 30.9, 0.2], ["KEY_SRCLK", 1, 88.65, 30.9, 94.55, 36.8, 0.2], ["KEY_SRCLK", 2, 94.55, 36.8, 94.55, 48.45, 0.2], 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112.75, 58.8, 0.2], ["VBUS_EN5", 1, 112.75, 58.8, 117.55, 54, 0.2], ["VBUS_EN5", 2, 117.55, 54, 117.95, 53.6, 0.2], ["VBUS_EN5", 2, 117.95, 53.6, 117.95, 41.75, 0.2], ["VBUS_EN5", 1, 117.95, 41.75, 119.8, 39.85, 0.2], ["VBUS_EN5", 2, 119.8, 39.85, 100.8, 20.85, 0.2], ["VBUS_EN5", 2, 100.8, 20.85, 97.05, 20.85, 0.2], ["VBUS_EN5", 2, 97.05, 20.85, 96.85, 20.65, 0.2], ["VBUS_EN5", 1, 96.85, 20.65, 96.751, 20.734, 0.2], ["+3V3", 1, 79.084, 40.717, 79.084, 40.994, 0.45], ["+3V3", 1, 79.084, 40.994, 79.084, 41.364, 0.45], ["+3V3", 1, 109.072, 37.415, 109.072, 37.695, 0.45], ["+3V3", 1, 109.072, 37.695, 109.072, 38.062, 0.45], ["GND", 1, 100.465, 12.86, 100.81, 13.326, 0.3], ["GND", 1, 80.123, 41.215, 80.726, 41.326, 0.3], ["GND", 1, 82.356, 41.075, 81.617, 41.075, 0.3], ["GND", 1, 77.989, 34.805, 77.592, 34.395, 0.3], ["GND", 1, 107.982, 31.726, 107.324, 31.726, 0.3], ["GND", 1, 109.759, 37.916, 109.759, 39.457, 0.3], ["+3V3", 1, 108.919, 37.916, 108.919, 39.457, 0.45]]} \ No newline at end of file diff --git a/.claude/_pcb1_polypads.json b/.claude/_pcb1_polypads.json index 6a1a01e..e545cde 100644 --- a/.claude/_pcb1_polypads.json +++ b/.claude/_pcb1_polypads.json @@ -1 +1 @@ -[{"net": "GND", "x": 151.9259, "y": 48.8, "num": "A1B12", "layer": 1, "pts": [6006.923, 1933.068, "L", 6006.923, 1921.258, 6006.929, 1921.258, 6006.929, 1909.447, 5955.747, 1909.447, 5955.747, 1921.257, 5955.741, 1921.257, 5955.741, 1933.068, 6006.923, 1933.068]}, {"net": "GND", "x": 151.9259, "y": 55.2, "num": "B1A12", "layer": 1, "pts": [5955.741, 2161.413, "L", 5955.741, 2173.224, 5955.741, 2173.225, 5955.741, 2185.036, 6006.921, 2185.036, 6006.921, 2173.225, 6006.921, 2173.224, 6006.921, 2161.413, 5955.741, 2161.413]}, {"net": "", "x": 151.9259, "y": 54.4002, "num": "B4A9", "layer": 1, "pts": [6006.921, 2153.546, "L", 6006.921, 2141.735, 6006.921, 2141.734, 6006.921, 2129.923, 5955.741, 2129.923, 5955.741, 2141.734, 5955.741, 2141.735, 5955.741, 2153.546, 6006.921, 2153.546]}, {"net": "", "x": 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13.783, 20.701], ["$2N657", 20.9, 22], ["$2N657", 17.7, 25], ["$2N663", 25.675, 19.65], ["$2N663", 19.425, 26.3], ["$2N664", 21, 26.85], ["$2N664", 26.316, 20.701], ["$2N698", 12.475, 49.075], ["$2N699", 13.8, 47.4], ["$2N699", 16.1, 49.8], ["$2N699", 23.4, 48.4], ["$2N699", 25.1, 46.8], ["$3N172", 94.575, 13.75], ["$3N172", 98.101, 15.197], ["$8N653", 41.8, 105.7], ["$8N653", 52, 95.5], ["$8N655", 50.4, 105.1], ["$8N655", 52, 106.7], ["$8N655", 54.1, 105.6], ["$8N657", 47.2, 103.7], ["$8N657", 50.1, 100.6], ["$8N659", 47.2, 107], ["$8N659", 48.7, 106.9], ["$8N663", 40.95, 107], ["$8N663", 48.475, 99.2], ["$8N664", 45, 101.4], ["$8N664", 41.573, 104.8], ["$8N676", 49.3, 80.2], ["$8N676", 52.6, 82.3], ["$8N699", 56.6, 85.3], ["$8N699", 47.5, 86.9], ["+3V3", 51.8, 75.2], ["+3V3", 55.3, 76.9], ["+5V", 62.7, 48.6], ["+5V", 64.9, 50.8], ["+5V", 61.7, 67.9], ["+5V", 73.299, 78.001], ["BLD_A", 20.5, 113.9], ["BLD_A", 13.75, 95.8], ["BLD_REF", 17.85, 117.7], ["BLD_REF", 16.55, 103.7], ["EFUSE_EN5", 133.4, 41.65], ["EFUSE_EN5", 132.8, 44.9], ["EFUSE_EN5", 126.1, 42.6], ["EFUSE_EN5", 96, 23.1], ["EFUSE_FLT1", 23.3, 43.5], ["EFUSE_FLT1", 17.4, 47], ["EFUSE_FLT3", 139, 77.6], ["EFUSE_FLT3", 146.3, 76.5], ["EFUSE_FLT3", 148.5, 76.5], ["EFUSE_FLT3", 140.7, 42.2], ["EFUSE_FLT3", 134.1, 38.8], ["EFUSE_FLT3", 120, 36.4], ["EFUSE_FLT3", 75.8, 48.1], ["EFUSE_FLT5", 131, 44.6], ["EFUSE_FLT5", 128.6, 47], ["EFUSE_FLT5", 134.35, 42.95], ["EFUSE_FLT5", 134.25, 41.5], ["EFUSE_FLT5", 132.9, 40.2], ["EFUSE_FLT5", 123.3, 39.85], ["EFUSE_FLT5", 88.6, 44.15], ["EFUSE_FLT5", 87.3, 42.85], ["EFUSE_FLT5", 78.65, 42.15], ["EFUSE_FLT5", 78.1, 43.45], ["EFUSE_FLT5", 76.55, 43.15], ["EFUSE_FLT5", 75.05, 48.55], ["EFUSE_PG1", 22.2, 48.4], ["EFUSE_PG1", 25.284, 45.499], ["EFUSE_PG2", 50.2, 75.2], ["EFUSE_PG2", 41.5, 75.3], ["EFUSE_PG2", 39.3, 74.2], ["EFUSE_PG2", 37.2, 74.3], ["EFUSE_PG2", 39.5, 78.4], ["EFUSE_PG2", 42.605, 80], ["EFUSE_PG3", 132.5, 76.35], ["EFUSE_PG3", 130.984, 80], ["EFUSE_PG4", 53.2, 44.05], ["EFUSE_PG4", 56.6, 44.75], ["EFUSE_PG5", 130.4, 48.4], ["EFUSE_PG5", 135.6, 45.1], ["FB3V3", 17.5, 116], ["FB3V3", 22.7, 116], ["FB3V3", 15.9, 110.1], ["FB3V3", 15.9, 105.85], ["INA_ALERT", 114.1, 51.5], ["INA_ALERT", 120.3, 57.7], ["NTC1", 80.6, 13.8], ["NTC1", 63.8, 28.3], ["NTC1", 60.6, 28.7], ["NTC1", 70.8, 35.248], ["NTC2", 74.3, 21.7], ["NTC2", 70.8, 25.248], ["SCL", 126.8, 49.3], ["SCL", 95.9, 33.3], ["SCL", 47.9, 49.85], ["SCL", 7.4, 95.2], ["SDA", 108.9, 31.1], ["SDA", 87.354, 28.474], ["SDA", 86.096, 27.094], ["SDA", 6.8, 98.25], ["VBUS_EN3", 91.3, 22.9], ["VBUS_EN3", 100.5, 19.1], ["VBUS_EN3", 146.7, 39.3], ["VBUS_EN3", 152.8, 74.5], ["VBUS_EN3", 151.8, 66], ["VO1", 20.1, 29.95], ["VO1", 23.2, 26.85], ["VO2", 53.4, 92.65], ["VO2", 56.15, 92.65], ["VO3", 141, 93.45], ["VO3", 145.985, 107], ["VO5", 125, 44.4], ["VO5", 129.485, 47.5], ["VO5", 125.7, 32.85], ["VO5", 122.9, 32.85], ["$12N834", 46.9, 18.2], ["$12N834", 45.3, 19.8], ["$12N836", 47.6, 17.65], ["$12N836", 44.45, 19.85], ["$12N836", 47.05, 24.05], ["$12N836", 48.45, 24.35], ["$14N653", 137.7, 19.8], ["$14N653", 127.1, 30], ["$14N657", 131.7, 21], ["$14N657", 126.5, 22.5], ["$14N657", 126.5, 23.9], ["$14N657", 128.5, 24.7], ["$14N699", 122.15, 45.6], ["$14N699", 121.2, 44.65], ["$14N699", 123.4, 41.95], ["$14N699", 131.05, 41.9], ["+3V3", 55.25, 76.275], ["+3V3", 51.925, 75.825], ["EFUSE_EN3", 149.5, 52.1], ["EFUSE_EN3", 144.3, 42.4], ["EFUSE_EN3", 140.5, 38.6], ["EFUSE_EN3", 134.9, 37], ["EFUSE_EN3", 121.6, 34.3], ["EFUSE_EN3", 115, 32.4], ["EFUSE_EN3", 96.9, 15.8], ["INA_ALERT", 34.9, 69.8], ["INA_ALERT", 11.2, 70.8], ["INA_ALERT", 11.2, 78.1], ["INA_ALERT", 7.1, 94.3], ["SCL", 102.1, 24.2], ["SCL", 103.3, 25.4], ["SCL", 109.6, 33.1], ["SDA", 140, 75.4], ["VDAC5", 126.434, 21.271], ["VDAC5", 116.7, 29.5], ["SCL", 114.9, 37.2], ["SDA", 34.1, 65.8], ["SDA", 51.3, 77.3], ["SDA", 102.5, 30.7], ["SDA", 102.5, 38.1], ["SDA", 102.5, 49], ["SDA", 102.5, 56.9], ["GND", 14.8, 5], ["GND", 38.5, 5], ["GND", 62.2, 5], ["GND", 110.3, 5], ["GND", 129, 5], ["GND", 147.7, 5], ["$10N732", 135.1, 75.5], ["$10N732", 133.85, 76.8], ["$10N732", 127.85, 73.35], ["$10N732", 127.85, 69.25], ["$12N878", 43.85, 39.65], ["$12N878", 49.45, 34.4], ["$12N878", 51.35, 34.4], ["$12N878", 65.3, 39.65], ["$12N878", 64, 41.85], ["$12N878", 60.1, 42.15], ["$2N653", 25.7, 18.65], ["$2N653", 9.65, 31.15], ["$2N653", 8.85, 32.3], ["$2N653", 10.4, 33.85], ["$2N653", 11.75, 32.75], ["$2N653", 15.85, 30], ["$2N676", 20.375, 47.15], ["$2N676", 21.275, 46.05], ["$2N676", 28.95, 43.95], ["$2N676", 28.95, 40.7], ["$2N676", 17.7, 39.15], ["$2N698", 18.9, 44.4], ["$2N732", 28.2, 56.8], ["$2N732", 28.2, 58.2], ["$8N687", 49.1, 81.1], ["$8N687", 46.4, 79], ["+3V3", 131.5, 80.7], ["+3V3", 123.25, 71.6], ["+3V3", 125.15, 71.6], ["+3V3", 131.9, 75.15], ["+3V3", 134.225, 75.125], ["+3V3", 137.675, 75.125], ["+3V3", 137.1, 75.5], ["+3V3", 143.35, 77.1], ["+5V", 86.3, 68.2], ["+5V", 91.9, 65.2], ["+5V", 93.4, 63.7], ["+5V", 101, 63.7], ["EFUSE_EN3", 141.5, 82.525], ["EFUSE_EN3", 138.6, 76.075], ["EFUSE_EN3", 134.75, 76.85], ["EFUSE_EN3", 135.7, 82.95], ["EFUSE_EN3", 137.7, 84.825], ["EFUSE_EN3", 139.975, 88.325], ["EFUSE_EN3", 138.55, 92.425], ["EFUSE_EN3", 145.6, 84.5], ["EFUSE_EN3", 145.575, 80.775], ["EFUSE_EN3", 145.7, 81.4], ["EFUSE_EN3", 145.7, 85.9], ["EFUSE_EN3", 132.8, 92.8], ["EFUSE_EN3", 123, 96.1], ["EFUSE_EN3", 102, 100.4], ["EFUSE_EN3", 99, 101.2], ["EFUSE_EN3", 89.5, 91.4], ["EFUSE_EN3", 90.2, 75.7], ["EFUSE_EN3", 93.9, 72], ["EFUSE_EN3", 95.4, 70.5], ["EFUSE_EN3", 97.6, 70.5], ["EFUSE_EN3", 103.5, 67.6], ["EFUSE_EN3", 113.6, 73], ["EFUSE_EN3", 131, 78.1], ["EFUSE_EN3", 131, 78.9], ["EFUSE_EN3", 133.2, 75.4], ["EFUSE_FLT1", 24.1, 43.5], ["EFUSE_FLT1", 41.7, 43.3], ["EFUSE_FLT1", 43.8, 41.2], ["EFUSE_FLT1", 57.5, 39.7], ["EFUSE_FLT1", 72.6, 43.1], ["EFUSE_FLT1", 74.7, 45.3], ["EFUSE_PG3", 104.4, 65.8], ["EFUSE_PG3", 95.1, 62.5], ["EFUSE_PG3", 91.8, 62.5], ["INA_ALERT", 133.25, 49.85], ["INA_ALERT", 138.45, 49.85], ["INA_ALERT", 147.95, 59.75], ["INA_ALERT", 143.75, 75.15], ["INA_ALERT", 148, 74.8], ["INA_ALERT", 145, 87.7], ["INA_ALERT", 129.5, 95], ["INA_ALERT", 103.7, 99.7], ["INA_ALERT", 100.4, 99.7], ["INA_ALERT", 99, 99.8], ["INA_ALERT", 68.8, 87.5], ["INA_ALERT", 62.1, 80.8], ["INA_ALERT", 59.7, 78.4], ["INA_ALERT", 58.6, 77.3], ["VO1", 13.8, 44.4], ["VO1", 17.9, 47.8], ["VO2", 46.775, 83.175], ["VO2", 48.975, 78.25], ["VO3", 137.425, 83.575], ["VO3", 137.775, 78.325], ["$12N832", 57.4, 19.7], ["$12N832", 47.7, 30.2], ["$12N855", 51.4, 47.3], ["+3V3", 77.425, 45.25], ["+3V3", 76.875, 50.825], ["BUCK_PG", 65.5, 47.6], ["BUCK_PG", 64.4, 48.7], ["BUCK_PG", 65.8, 51.7], ["BUCK_PG", 65.8, 62.7], ["BUCK_PG", 51.2, 35.3], ["BUCK_PG", 50.9, 33.6], ["BUCK_PG", 46.3, 30.7], ["BUCK_PG", 17.7, 30], ["EFUSE_EN1", 29.7, 40.1], ["EFUSE_EN1", 58.3, 29.8], ["EFUSE_EN2", 53.15, 83.95], ["EFUSE_EN2", 43.7, 79.05], ["EFUSE_EN2", 58.6, 81], ["EFUSE_EN2", 69.3, 75.2], ["EFUSE_EN2", 69.1, 51.2], ["EFUSE_EN2", 70.5, 44.5], ["EFUSE_EN2", 82.286, 27.094], ["EFUSE_EN4", 52.95, 37.3], ["EFUSE_EN4", 54.5, 35.75], ["EFUSE_PG1", 49.05, 47.55], ["EFUSE_PG1", 49.45, 49.25], ["EFUSE_PG1", 64.05, 60.4], ["EFUSE_PG1", 70.85, 60.4], ["EFUSE_PG1", 80.075, 53.779], ["EFUSE_PG4", 67.5, 50.7], ["EFUSE_PG4", 74.7, 54.4], ["EFUSE_PG5", 135.9, 39.5], ["EFUSE_PG5", 134.3, 37.9], ["EFUSE_PG5", 123, 35.7], ["EFUSE_PG5", 117.8, 40.9], ["EFUSE_PG5", 103.4, 46], ["EFUSE_PG5", 83.2, 47.1], ["EFUSE_PG5", 79.3, 51], ["IOEXP_INT#", 72.3, 44.5], ["IOEXP_INT#", 71.9, 41.2], ["IOEXP_INT#", 70.4, 38.3], ["IOEXP_INT#", 79.251, 20.734], ["SDA", 81.7, 35.3], ["SDA", 82.8, 45.45], ["SDA", 83.75, 46.4], ["UP_VBUS_DET", 64.1, 25.1], ["UP_VBUS_DET", 41.7, 39.4], ["UP_VBUS_DET", 39.7, 44.7], ["UP_VBUS_DET", 41.1, 46.1], ["VBUS_EN1", 78.6, 18.2], ["VBUS_EN1", 73.6, 19.6], ["VBUS_EN1", 55.3, 25.3], ["VBUS_EN1", 14.6, 34.5], ["VBUS_EN1", 11.2, 67.1], ["VBUS_EN4", 79.3, 15.9], ["VBUS_EN4", 67, 28.7], ["VBUS_EN4", 54.6, 36.8], ["VBUS_EN4", 41.5, 40.8], ["VDAC1", 15.3, 22.1], ["VDAC1", 22.6, 21.6], ["VDAC1", 33.2, 24.8], ["VDAC1", 40.4, 30], ["VDAC1", 50.9, 32.7], ["VDAC1", 69.7, 37.3], ["VDAC3", 141, 105.2], ["VDAC3", 116.4, 77.4], ["VDAC3", 101.8, 70.4], ["VDAC3", 96.3, 64.9], ["VDAC3", 95.5, 58.5], ["VDAC4", 47.075, 21.275], ["VO4", 45.5, 44.45], ["VO4", 49.9, 47.25], ["GND", 77.8, 35.4], ["GND", 107.2, 32.8], ["SDA", 81.6, 49.9], ["EFUSE_EN1", 19.2, 40.65], ["EFUSE_EN1", 15, 39.15], ["EFUSE_FLT3", 115.6, 38.45], ["EFUSE_FLT3", 106.35, 38.85], ["EFUSE_FLT3", 82.65, 37.25], ["SCL", 106.1, 33.8], ["SCL", 104.6, 34], ["SCL", 108.4, 42.9], ["SCL", 115.7, 39.4], ["VDAC3", 101.85, 43.25], ["VDAC3", 110.8, 38.2], ["VDAC3", 111.6, 35.6], ["VDAC4", 54.7, 19.8], ["VDAC4", 60.2, 17.15], ["VDAC4", 74.95, 16.2], ["VDAC4", 77.95, 16.2], ["VDAC4", 78.3, 30.55], ["VDAC4", 79.85, 34.65], ["VDAC4", 81.75, 37.2], ["SCL", 119.9, 42.1], ["SCL", 72.9, 51.2], ["SCL", 61.1, 50], ["SCL", 48, 75.9], ["SCL", 29.1, 58.4], ["SCL", 6.8, 87.6], ["SDA", 73.6, 54.4], ["SDA", 67.8, 55.8], ["SDA", 66.5, 54.9], ["SDA", 60.9, 58.5], ["SDA", 11.4, 87.6], ["EFUSE_FLT2", 46.6, 84.05], ["EFUSE_FLT2", 84.4, 45.8], ["EFUSE_FLT2", 80.5, 44.15], ["EFUSE_FLT2", 79.2, 42.85], ["EFUSE_FLT2", 75.7, 43.05], ["EFUSE_FLT2", 75, 44.45], ["KEY_OE#", 84.8, 29.9], ["KEY_OE#", 87.9, 40.1], ["KEY_OE#", 89.2, 42.8], ["KEY_OE#", 90.3, 58.6], ["KEY_OE#", 90.7, 61.8], ["KEY_OE#", 90.7, 63.7], ["KEY_OE#", 100.5, 78.8], ["KEY_OE#", 111.1, 71.6], ["KEY_OE#", 114, 66.4], ["KEY_RCLK", 93.9, 31.35], ["KEY_RCLK", 93.9, 34.35], ["KEY_RCLK", 95.2, 36.2], ["KEY_RCLK", 98.35, 48.75], ["KEY_RCLK", 99.55, 50.85], ["KEY_RCLK", 108.45, 57.4], ["KEY_RCLK", 111.15, 58.5], ["KEY_SER", 88, 32.15], ["KEY_SER", 88.55, 39.5], ["KEY_SER", 91.65, 42.85], ["KEY_SER", 97.4, 52.3], ["KEY_SER", 103.15, 54], ["KEY_SER", 108.6, 56.55], ["KEY_SER", 109.9, 57.85], ["KEY_SRCLK", 94.55, 36.8], ["KEY_SRCLK", 98.25, 52.15], ["KEY_SRCLK", 109.35, 59.25], ["VBUS_EN2", 103.15, 50.85], ["VBUS_EN2", 99.6, 47.75], ["VBUS_EN2", 96.5, 34.9], ["VBUS_EN5", 117.55, 54], ["VBUS_EN5", 117.95, 41.75], ["VBUS_EN5", 119.8, 39.85], ["VBUS_EN5", 96.85, 20.65], ["GND", 0.35, 71.814], ["GND", 0.35, 72.464], ["GND", 1, 71.814], ["GND", 1, 72.464], ["GND", 1.65, 71.814], ["GND", 1.65, 72.464], ["GND", 100.81, 13.326], ["GND", 80.726, 41.326], ["GND", 81.617, 41.075], ["GND", 77.592, 34.395], ["GND", 107.324, 31.726], ["GND", 109.759, 39.457], ["+3V3", 108.919, 39.457]]} \ No newline at end of file diff --git a/.claude/_pcb1_sig_plan.json b/.claude/_pcb1_sig_plan.json index 8ef0fa6..fe6f5c9 100644 --- a/.claude/_pcb1_sig_plan.json +++ b/.claude/_pcb1_sig_plan.json @@ -1 +1 @@ -{"$1N236\u0000FORCE:U13.10:Rs6.1": [[5.4991, 101.1106, 1, 0.3], [4.7, 100.3, 1, 0.3], [4.7, 94.8, 1, 0.3], [3.4341, 93.5004, 1, 0.3]], "+12V\u0000FORCE:U13.9:Rs6.2": [[5.9995, 101.1106, 1, 0.3], [6.2, 100.9, 1, 0.3], [6.2, 100.0, 1, 0.3], [8.2, 97.9, 1, 0.3], [8.2, 94.9, 1, 0.3], [9.5656, 93.5004, 1, 0.3]], "+12V\u0000FORCE:U13.8:U13.9": [[6.4998, 101.1106, 1, 0.3], [5.9995, 101.1106, 1, 0.3]], "INA_ALERT\u00000": [[128.85, 53.15, 1, 0.2], [128.85, 51.45, 1, 0.2], [130.0, 50.3, 1, 0.2], [132.8, 50.3, 1, 0.2], [133.25, 49.85, 1, 0.2], [133.25, 49.85, 2, 0.2], [138.45, 49.85, 2, 0.2], [138.45, 49.85, 1, 0.2], [140.35, 51.75, 1, 0.2], [140.35, 52.15, 1, 0.2], [147.95, 59.75, 1, 0.2], [147.95, 59.75, 2, 0.2], [148.3, 60.1, 2, 0.2], [148.3, 73.45, 2, 0.2], [146.8, 74.95, 2, 0.2], [143.95, 74.95, 2, 0.2], [143.75, 75.15, 2, 0.2], [143.75, 75.15, 1, 0.2], [143.3561, 74.7561, 1, 0.2], [143.1001, 74.6562, 1, 0.2], [142.05, 74.7, 1, 0.2]], "INA_ALERT\u00001": [[147.5, 74.3, 2, 0.2], [148.0, 74.8, 2, 0.2], [148.0, 74.8, 1, 0.2], [149.2, 76.0, 1, 0.2], [149.2, 83.5, 1, 0.2], [145.0, 87.7, 1, 0.2], [145.0, 87.7, 2, 0.2], [140.9, 91.8, 2, 0.2], [132.7, 91.8, 2, 0.2], [129.5, 95.0, 2, 0.2], [129.5, 95.0, 1, 0.2], [124.8, 99.7, 1, 0.2], [103.7, 99.7, 1, 0.2], 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72.8, 1, 0.2]], "K3_PWR\u00000": [[120.2, 94.2, 1, 0.2], [120.15, 94.45, 1, 0.2], [119.845, 94.7, 1, 0.2], [106.6, 94.7, 1, 0.2], [103.7, 97.6, 1, 0.2], [103.7, 97.6, 2, 0.2], [102.3, 99.0, 2, 0.2], [102.3, 99.0, 1, 0.2], [100.8, 100.5, 1, 0.2], [98.3, 100.5, 1, 0.2], [98.3, 100.5, 2, 0.2], [97.3, 99.5, 2, 0.2], [97.3, 99.2, 2, 0.2], [97.3, 99.2, 1, 0.2], [97.3, 93.5, 1, 0.2], [97.3, 93.5, 2, 0.2], [85.3, 81.5, 2, 0.2], [85.3, 65.4, 2, 0.2], [88.9, 61.8, 2, 0.2], [88.9, 61.8, 1, 0.2], [91.9, 58.8, 1, 0.2], [92.7, 58.8, 1, 0.2], [92.7, 58.8, 2, 0.2], [93.2, 58.3, 2, 0.2], [96.5, 58.3, 2, 0.2], [96.5, 58.3, 1, 0.2], [97.7, 57.1, 1, 0.2], [97.7, 52.2, 1, 0.2], [97.7, 52.2, 2, 0.2], [97.6, 50.8, 2, 0.2], [97.6, 50.8, 1, 0.2], [97.4, 51.0, 1, 0.2], [94.8, 51.0, 1, 0.2], [94.4, 50.6, 1, 0.2]], "POGO1_PWR\u00000": [[24.45, 62.5, 1, 0.2], [26.7, 62.5, 1, 0.2], [26.9, 62.3, 1, 0.2], [26.9, 60.2, 1, 0.2], [27.15, 59.95, 1, 0.2], [29.2, 59.95, 1, 0.2], [30.45, 58.7, 1, 0.2], [30.45, 28.35, 1, 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44.45, 1, 0.2], [75.5, 45.4, 1, 0.2]], "VBUS_EN2\u00000": [[118.25, 62.9, 2, 0.2], [117.85, 62.5, 2, 0.2], [117.85, 56.45, 2, 0.2], [113.95, 52.55, 2, 0.2], [104.85, 52.55, 2, 0.2], [103.15, 50.85, 2, 0.2], [103.15, 50.85, 1, 0.2], [100.05, 47.75, 1, 0.2], [99.6, 47.75, 1, 0.2], [99.6, 47.75, 2, 0.2], [99.6, 38.0, 2, 0.2], [96.5, 34.9, 2, 0.2], [96.5, 34.9, 1, 0.2], [91.65, 30.05, 1, 0.2], [91.65, 27.8788, 1, 0.2], [91.4129, 27.3221, 1, 0.2], [91.1759, 27.0942, 1, 0.2]], "KEY_SRCLK\u00000": [[88.6359, 27.0942, 1, 0.2], [88.65, 30.9, 1, 0.2], [94.55, 36.8, 1, 0.2], [94.55, 36.8, 2, 0.2], [94.55, 48.45, 2, 0.2], [98.25, 52.15, 2, 0.2], [98.25, 52.15, 1, 0.2], [102.25, 52.15, 1, 0.2], [109.35, 59.25, 1, 0.2], [109.35, 59.25, 2, 0.2], [110.2, 60.1, 2, 0.2], [110.2, 62.45, 2, 0.2], [111.4908, 63.7692, 2, 0.2]], "KEY_RCLK\u00000": [[92.4459, 27.0942, 1, 0.2], [92.45, 29.9, 1, 0.2], [93.9, 31.35, 1, 0.2], [93.9, 31.35, 2, 0.2], [93.9, 34.35, 2, 0.2], [93.9, 34.35, 1, 0.2], [95.2, 35.65, 1, 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1, 0.2]], "BUCK_PG\u00006\u0000c1\u0000c5": [[78.1243, 46.6126, 1, 0.2], [78.1243, 47.734, 1, 0.2]], "BUCK_PG\u00007\u0000c0\u0000c0": [[78.9598, 45.2089, 1, 0.2], [78.6515, 45.38, 1, 0.2]], "BUCK_PG\u00007\u0000c0\u0000c1": [[78.6515, 45.38, 1, 0.2], [78.6515, 45.38, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c0": [[78.6515, 45.38, 1, 0.2], [78.6515, 45.38, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c1": [[78.6515, 45.38, 1, 0.2], [78.3, 45.575, 1, 0.2], [78.25, 45.65, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c2": [[78.1919, 46.6126, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c3": [[78.1919, 46.6126, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c4": [[78.1919, 46.6126, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c1\u0000c5": [[78.1919, 46.6126, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c2": [[78.1919, 46.6126, 1, 0.2], [78.1919, 46.6126, 1, 0.2]], "BUCK_PG\u00007\u0000c3": [[78.1919, 46.6126, 1, 0.2], [78.1243, 47.734, 1, 0.2]], "BUCK_PG\u00008\u0000c0": [[78.4, 45.0, 1, 0.15], [78.4, 44.7, 1, 0.15], [78.15, 44.45, 1, 0.15]], "BUCK_PG\u00008\u0000c1": [[78.15, 44.45, 1, 0.15], [77.5, 43.8, 1, 0.15], [65.8, 43.8, 1, 0.15]], "BUCK_PG\u00008\u0000c2\u0000c0": [[65.8, 43.8, 1, 0.15], [62.7, 43.8, 1, 0.15], [59.7, 40.8, 1, 0.15], [57.4, 40.8, 1, 0.15], [52.0, 35.4, 1, 0.15], [52.0, 32.7, 1, 0.15], [49.3475, 30.0524, 1, 0.15]], "BUCK_PG\u00008\u0000c2\u0000c1": [[49.3475, 30.0524, 1, 0.15], [49.3475, 30.0524, 1, 0.15]], "BUCK_PG\u00008\u0000c3\u0000c0": [[49.3475, 30.0524, 1, 0.15], [49.3475, 30.0524, 1, 0.15]], "BUCK_PG\u00008\u0000c3\u0000c1": [[49.3475, 30.0524, 1, 0.15], [49.2201, 29.9253, 1, 0.15]], "BUCK_PG\u00009": [[49.3, 30.1, 1, 0.2], [49.2, 30.2, 1, 0.2], [49.2, 30.2, 2, 0.2], [48.7, 30.7, 2, 0.2], [18.4, 30.7, 2, 0.2], [17.7, 30.0, 2, 0.2], [17.7, 30.0, 1, 0.2], [17.5514, 29.9253, 1, 0.2]], "EDL_EN1\u00000": [[88.8264, 73.7362, 1, 0.2], [88.8264, 75.0217, 1, 0.2]], "EDL_EN1\u00001\u0000c0\u0000c0": [[88.8264, 75.0217, 1, 0.2], [86.7427, 77.2359, 1, 0.2], [85.9, 77.6, 1, 0.2], [77.1, 77.6, 1, 0.2], [74.6, 80.1, 1, 0.2], [60.7, 80.1, 1, 0.2], [59.5, 81.3, 1, 0.2], [59.5, 81.3, 2, 0.2], [54.6, 86.2, 2, 0.2], [33.2, 86.2, 2, 0.2], [32.3, 85.3, 2, 0.2], [24.4, 85.3, 2, 0.2], [24.4, 85.3, 1, 0.2], [23.3, 84.2, 1, 0.2], [19.3, 84.2, 1, 0.2], [19.3, 84.2, 2, 0.2], [23.2, 80.3, 2, 0.2], [23.2, 75.0, 2, 0.2], [23.2, 75.0, 1, 0.2], [23.2, 72.2, 1, 0.2], [28.2, 67.2, 1, 0.2], [28.1889, 63.7692, 1, 0.2]], "EDL_EN1\u00001\u0000c0\u0000c1": [[28.1889, 63.7692, 1, 0.2], [28.1889, 63.7692, 1, 0.2]], "EDL_EN1\u00001\u0000c1": [[28.1889, 63.7692, 1, 0.2], [28.1889, 63.7692, 1, 0.2]], "EDL_EN2\u00000\u0000c0": [[87.5564, 68.265, 1, 0.2], [87.5564, 68.2648, 1, 0.2]], "EDL_EN2\u00000\u0000c1": [[87.5564, 68.2648, 1, 0.2], [87.5564, 68.2648, 1, 0.2]], "EDL_EN2\u00000\u0000c2": [[87.5564, 68.2648, 1, 0.2], [87.5564, 68.2647, 1, 0.2]], "EDL_EN2\u00000\u0000c3": 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66.9795, 1, 0.2]], "EFUSE_EN1\u00000\u0000c0": [[25.8673, 47.5005, 1, 0.2], [25.3, 47.5005, 1, 0.2]], "EFUSE_EN1\u00000\u0000c1": [[25.3, 47.5005, 1, 0.2], [25.2841, 47.5005, 1, 0.2]], "EFUSE_EN1\u00001": [[14.5491, 44.3001, 1, 0.2], [14.575, 40.3, 1, 0.2]], "EFUSE_EN1\u00002": [[25.3, 47.6, 1, 0.2], [23.1, 49.8, 1, 0.2], [23.1013, 50.0507, 1, 0.2]], "EFUSE_EN2\u00000\u0000c0": [[42.0217, 78.0009, 1, 0.2], [42.0217, 78.0009, 1, 0.2]], "EFUSE_EN2\u00000\u0000c1\u0000c0": [[42.0217, 78.0009, 1, 0.2], [42.0217, 78.0009, 1, 0.2]], "EFUSE_EN2\u00000\u0000c1\u0000c1": [[42.0217, 78.0009, 1, 0.2], [42.6049, 78.0009, 1, 0.2]], "EFUSE_EN2\u00001\u0000c0": [[53.34, 81.2012, 1, 0.2], [53.34, 81.2012, 1, 0.2]], "EFUSE_EN2\u00001\u0000c1\u0000c0": [[53.34, 81.2012, 1, 0.2], [53.34, 81.2012, 1, 0.2]], "EFUSE_EN2\u00001\u0000c1\u0000c1": [[53.34, 81.2012, 1, 0.2], [53.325, 83.775, 1, 0.2], [53.15, 83.95, 1, 0.2], [53.15, 83.95, 2, 0.2], [53.475, 84.275, 2, 0.2], [53.475, 85.2, 2, 0.2]], "EFUSE_EN2\u00002\u0000c0": [[53.475, 85.2, 2, 0.2], [53.4875, 84.95, 2, 0.2], [53.323, 84.523, 2, 0.2], [51.05, 82.25, 2, 0.2], [46.8, 82.25, 2, 0.2], [43.55, 78.95, 2, 0.2], [43.55, 78.95, 1, 0.2], [42.6518, 78.048, 1, 0.2]], "EFUSE_EN2\u00002\u0000c1\u0000c0": [[42.6518, 78.048, 1, 0.2], [42.6518, 78.048, 1, 0.2]], "EFUSE_EN2\u00002\u0000c1\u0000c1": [[42.6518, 78.048, 1, 0.2], [42.6049, 78.0009, 1, 0.2]], "EFUSE_EN2\u00003\u0000c0\u0000c0": [[42.7, 78.0, 1, 0.2], [44.6411, 76.0589, 1, 0.2], [44.7952, 75.6754, 1, 0.2], [44.7904, 75.4507, 1, 0.2]], "EFUSE_EN2\u00003\u0000c0\u0000c1": [[44.7904, 75.4507, 1, 0.2], [44.7904, 75.4507, 1, 0.2]], "EFUSE_EN2\u00003\u0000c1": [[44.7904, 75.4507, 1, 0.2], [44.7904, 75.4507, 1, 0.2]], "EFUSE_EN2\u00004": [[53.3, 83.7, 2, 0.2], [61.7, 75.3, 2, 0.2], [61.7, 69.2, 2, 0.2], [61.7, 69.2, 1, 0.2], [66.5, 64.4, 1, 0.2], [66.5, 57.1, 1, 0.2], [66.5, 57.1, 2, 0.2], [66.5, 50.8, 2, 0.2], [66.5, 50.8, 1, 0.2], [70.6, 46.7, 1, 0.2], [70.6, 44.5, 1, 0.2], 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[[78.7746, 52.6537, 1, 0.2], [78.7746, 52.6537, 1, 0.2]], "EFUSE_PG3\u00002\u0000c1\u0000c0": [[78.7746, 52.6537, 1, 0.2], [78.7746, 52.6537, 1, 0.2]], "EFUSE_PG3\u00003\u0000c0": [[138.6, 75.175, 1, 0.2], [137.6, 76.15, 1, 0.2], [132.7, 76.15, 1, 0.2], [132.5, 76.35, 1, 0.2], [132.5, 76.35, 2, 0.2], [131.7, 76.35, 2, 0.2], [130.325, 77.725, 2, 0.2]], "EFUSE_PG3\u00003\u0000c1": [[130.325, 77.725, 2, 0.2], [130.3, 77.75, 2, 0.2], [130.3, 79.3, 2, 0.2], [130.9843, 79.9998, 2, 0.2], [130.9843, 79.9998, 1, 0.2], [130.9843, 79.9998, 1, 0.2]], "EFUSE_PG4\u00000\u0000c0": [[57.5361, 45.499, 1, 0.2], [57.5361, 45.499, 1, 0.2]], "EFUSE_PG4\u00000\u0000c1\u0000c0": [[57.5361, 45.499, 1, 0.2], [57.5361, 45.499, 1, 0.2]], "EFUSE_PG4\u00000\u0000c1\u0000c1": [[57.5361, 45.499, 1, 0.2], [56.9529, 45.499, 1, 0.2]], "EFUSE_PG4\u00001": [[46.7182, 47.2999, 1, 0.2], [46.7428, 47.9001, 1, 0.2], [46.925, 48.075, 1, 0.2], [47.1, 48.075, 1, 0.2], [49.35, 50.325, 1, 0.2]], "EFUSE_PG4\u00002\u0000c0": [[78.1243, 52.6537, 1, 0.2], [78.1243, 52.6537, 1, 0.2]], "EFUSE_PG4\u00002\u0000c1\u0000c0": [[78.1243, 52.6537, 1, 0.2], [78.1243, 52.6537, 1, 0.2]], "EFUSE_PG4\u00002\u0000c1\u0000c1": [[78.1243, 52.6537, 1, 0.2], [78.1243, 53.7792, 1, 0.2]], "EFUSE_PG4\u00003": [[49.35, 50.325, 1, 0.2], [51.0, 48.65, 1, 0.2], [51.5, 48.65, 1, 0.2], [52.45, 47.7, 1, 0.2], [52.45, 46.3, 1, 0.2], [53.2, 45.55, 1, 0.2], [53.2, 44.05, 1, 0.2], [53.2, 44.05, 2, 0.2], [53.5, 43.75, 2, 0.2], [55.6, 43.75, 2, 0.2], [56.6, 44.75, 2, 0.2], [56.6, 44.75, 1, 0.2], [56.95, 45.1, 1, 0.2], [56.9529, 45.499, 1, 0.2]], "EFUSE_PG5\u00000\u0000c0": [[137.0686, 45.499, 1, 0.2], [137.0686, 45.499, 1, 0.2]], "EFUSE_PG5\u00000\u0000c1\u0000c0": [[137.0686, 45.499, 1, 0.2], [137.0686, 45.499, 1, 0.2]], "EFUSE_PG5\u00000\u0000c1\u0000c1": [[137.0686, 45.499, 1, 0.2], [136.4853, 45.499, 1, 0.2]], "EFUSE_PG5\u00001": [[126.2507, 47.2999, 1, 0.2], [126.2695, 47.9001, 1, 0.2], [126.45, 48.075, 1, 0.2], [126.625, 48.075, 1, 0.2], [128.875, 50.325, 1, 0.2]], "EFUSE_PG5\u00002\u0000c0": [[77.4741, 52.6537, 1, 0.2], [77.4741, 52.6537, 1, 0.2]], "EFUSE_PG5\u00002\u0000c1\u0000c0": [[77.4741, 52.6537, 1, 0.2], [77.4741, 52.6537, 1, 0.2]], "EFUSE_PG5\u00002\u0000c1\u0000c1": [[77.4741, 52.6537, 1, 0.2], [77.4741, 53.7792, 1, 0.2]], "EFUSE_PG5\u00003": [[128.875, 50.325, 1, 0.2], [130.4, 48.8, 1, 0.2], [130.4, 48.4, 1, 0.2], [130.4, 48.4, 2, 0.2], [133.1, 45.7, 2, 0.2], [135.0, 45.7, 2, 0.2], [135.6, 45.1, 2, 0.2], [135.6, 45.1, 1, 0.2], [136.0, 45.5, 1, 0.2], [136.4853, 45.499, 1, 0.2]], "FAN_PWM\u00000\u0000c0": [[83.55, 27.1, 1, 0.2], [83.55, 27.0942, 1, 0.2]], "FAN_PWM\u00000\u0000c1": [[83.55, 27.0942, 1, 0.2], [83.55, 26.025, 1, 0.2], [85.8, 23.775, 1, 0.2]], "FAN_TACH\u00000\u0000c0": [[101.0666, 78.0009, 1, 0.2], [101.0666, 78.0009, 1, 0.2]], "FAN_TACH\u00000\u0000c1\u0000c0": [[101.0666, 78.0009, 1, 0.2], [101.0666, 78.0009, 1, 0.2]], "FAN_TACH\u00000\u0000c1\u0000c1": [[101.0666, 78.0009, 1, 0.2], [100.4834, 78.0009, 1, 0.2]], "FAN_TACH\u00001\u0000c0": [[104.5667, 78.0009, 1, 0.2], [104.5667, 78.0009, 1, 0.2]], "FAN_TACH\u00001\u0000c1\u0000c0": [[104.5667, 78.0009, 1, 0.2], [104.5667, 78.0009, 1, 0.2]], "FAN_TACH\u00001\u0000c1\u0000c1": [[104.5667, 78.0009, 1, 0.2], [103.9835, 78.0009, 1, 0.2]], "FAN_TACH\u00002\u0000c0": [[100.4834, 78.0009, 1, 0.2], [101.0, 78.0, 1, 0.2], [101.0, 78.0, 2, 0.2], [102.0, 78.0003, 2, 0.2]], "FAN_TACH\u00002\u0000c1": [[102.0, 78.0003, 2, 0.2], [103.9835, 78.0009, 2, 0.2], [103.9835, 78.0009, 1, 0.2], [103.9835, 78.0009, 1, 0.2]], "FAN_TACH\u00003\u0000c0\u0000c0": [[102.0, 78.0, 2, 0.2], [102.0, 78.0003, 2, 0.2]], "FAN_TACH\u00003\u0000c0\u0000c1": [[102.0, 78.0003, 2, 0.2], [102.0, 78.0003, 2, 0.2]], "FAN_TACH\u00003\u0000c0\u0000c2": [[102.0, 78.0003, 2, 0.2], [102.0, 90.6, 2, 0.2], [101.4, 91.2, 2, 0.2], [101.4, 93.2, 2, 0.2], [102.0, 93.8, 2, 0.2], [102.6, 93.8, 2, 0.2], [104.0, 92.4, 2, 0.2], [104.0, 92.4, 1, 0.2], [120.2, 92.4, 1, 0.2], [123.0, 89.6, 1, 0.2], [136.6, 89.6, 1, 0.2], [138.0, 88.2, 1, 0.2], [138.0, 88.2, 2, 0.2], [138.8, 87.4, 2, 0.2], [140.8, 87.4, 2, 0.2], [149.4, 78.8, 2, 0.2], [149.4, 76.8, 2, 0.2], [154.4, 71.8, 2, 0.2], [154.4, 71.8, 1, 0.2], [154.4, 46.4, 1, 0.2], [148.0, 40.0, 1, 0.2], [136.8, 40.0, 1, 0.2], [134.8, 38.0, 1, 0.2], [134.8, 38.0, 2, 0.2], [132.4, 35.6, 2, 0.2], [120.6, 35.6, 2, 0.2], [97.2, 12.2, 2, 0.2], [95.2, 12.2, 2, 0.2], [95.2, 12.2, 1, 0.2], [95.2, 16.6, 1, 0.2], [91.4, 20.4, 1, 0.2], [88.2, 20.4, 1, 0.2], [82.4473, 26.1527, 1, 0.2], [82.243, 26.7471, 1, 0.2], [82.2859, 27.0942, 1, 0.2]], "FAN_TACH\u00003\u0000c0\u0000c3": [[82.2859, 27.0942, 1, 0.2], [82.2859, 27.0942, 1, 0.2]], "FAN_TACH\u00003\u0000c1": [[82.2859, 27.0942, 1, 0.2], [82.2859, 27.0942, 1, 0.2]], "FB3V3\u00000\u0000c0": [[17.5667, 115.9992, 1, 0.2], [17.5667, 115.9992, 1, 0.2]], "FB3V3\u00000\u0000c1\u0000c0": [[17.5667, 115.9992, 1, 0.2], [17.5667, 115.9992, 1, 0.2]], "FB3V3\u00000\u0000c1\u0000c1": [[17.5667, 115.9992, 1, 0.2], [16.9835, 115.9992, 1, 0.2]], "FB3V3\u00001": [[21.4326, 115.9992, 1, 0.2], [22.0158, 115.9992, 1, 0.2]], "FB3V3\u00002\u0000c0": [[17.6505, 104.9502, 1, 0.2], [17.6505, 104.9502, 1, 0.2]], "FB3V3\u00002\u0000c1\u0000c0": [[17.6505, 104.9502, 1, 0.2], [17.6505, 104.9502, 1, 0.2]], "FB3V3\u00002\u0000c1\u0000c1": [[17.6505, 104.9502, 1, 0.2], [16.8006, 104.9502, 1, 0.2]], "FB3V3\u00003": [[16.9835, 115.9992, 1, 0.2], [17.5, 116.0, 1, 0.2], [17.5, 116.0, 2, 0.2], [19.1, 117.6, 2, 0.2], [22.4, 117.6, 2, 0.2], [22.6, 117.4, 2, 0.2], [22.7765, 116.9181, 2, 0.2], [22.7, 116.0, 2, 0.2], [22.7, 116.0, 1, 0.2], [22.0158, 115.9992, 1, 0.2]], "FB3V3\u00004": [[17.3, 115.75, 1, 0.2], [16.3, 114.75, 1, 0.2], [16.3, 110.5, 1, 0.2], [15.9, 110.1, 1, 0.2], [15.9, 110.1, 2, 0.2], [15.9, 105.85, 2, 0.2], [15.9, 105.85, 1, 0.2], [16.8006, 104.9502, 1, 0.2]], "GATE\u00000": [[25.9192, 68.0011, 1, 0.2], [26.4694, 68.0011, 1, 0.2]], "GATE\u00001\u0000c0": [[21.2317, 72.596, 1, 0.2], [21.2317, 72.596, 1, 0.2]], "GATE\u00001\u0000c1\u0000c0": [[21.2317, 72.596, 1, 0.2], [21.2317, 72.596, 1, 0.2]], "GATE\u00001\u0000c1\u0000c1": [[21.2317, 72.596, 1, 0.2], [21.2316, 72.596, 1, 0.2]], "GATE\u00001\u0000c1\u0000c2": [[21.2316, 72.596, 1, 0.2], [21.2316, 72.596, 1, 0.2]], "GATE\u00001\u0000c1\u0000c3": [[21.2316, 72.596, 1, 0.2], [20.0144, 72.596, 1, 0.2]], "GATE\u00002\u0000c0": [[28.4322, 71.501, 1, 0.2], [28.4322, 71.501, 1, 0.2]], "GATE\u00002\u0000c1\u0000rr\u0000c0": [[28.4322, 71.501, 1, 0.2], [28.4322, 71.501, 1, 0.2]], "GATE\u00002\u0000c1\u0000rr\u0000c1": [[28.4322, 71.501, 1, 0.2], [29.0154, 71.501, 1, 0.2]], "GATE\u00003\u0000c0\u0000c0": [[26.4694, 68.0011, 1, 0.2], [26.2071, 67.7263, 1, 0.2]], "GATE\u00003\u0000c0\u0000c1": [[26.2071, 67.7263, 1, 0.2], [26.2071, 67.7263, 1, 0.2]], "GATE\u00003\u0000c1\u0000c0": [[26.2071, 67.7263, 1, 0.2], [26.207, 67.7262, 1, 0.2]], "GATE\u00003\u0000c1\u0000c1": [[26.207, 67.7262, 1, 0.2], [26.1347, 67.6505, 1, 0.2], [25.3162, 67.3285, 1, 0.2], [24.4733, 67.378, 1, 0.2], [23.8775, 67.7005, 1, 0.2], [23.6551, 68.0011, 1, 0.2]], "GATE\u00004\u0000rr": [[26.1, 68.2, 1, 0.2], [26.1, 68.2, 2, 0.2], [27.0, 69.1, 2, 0.2], [27.4, 69.1, 2, 0.2], [27.4, 69.1, 1, 0.2], [29.0, 70.7, 1, 0.2], [29.0154, 71.501, 1, 0.2]], "GATE\u00005\u0000c0": [[25.675, 68.25, 1, 0.2], [25.675, 68.4, 1, 0.2], [21.475, 72.6, 1, 0.2], [21.2317, 72.5993, 1, 0.2]], "GATE\u00005\u0000c1\u0000c0": [[21.2317, 72.5993, 1, 0.2], [21.2317, 72.5993, 1, 0.2]], "GATE\u00005\u0000c1\u0000c1": [[21.2317, 72.5993, 1, 0.2], [21.2316, 72.5993, 1, 0.2]], "GATE\u00005\u0000c2": [[21.2316, 72.5993, 1, 0.2], [20.0144, 72.596, 1, 0.2]], "HUB_RST\u00000\u0000c0": [[96.0142, 35.2753, 1, 0.2], [96.0142, 35.2753, 1, 0.2]], "HUB_RST\u00000\u0000c1\u0000c0": [[96.0142, 35.2753, 1, 0.2], [96.0142, 35.2753, 1, 0.2]], "HUB_RST\u00000\u0000c1\u0000c1": [[96.0142, 35.2753, 1, 0.2], [96.0142, 33.9898, 1, 0.2]], "INA_ALERT\u00000": [[128.85, 53.15, 1, 0.2], [128.85, 51.45, 1, 0.2], [130.0, 50.3, 1, 0.2], [132.8, 50.3, 1, 0.2], [133.25, 49.85, 1, 0.2], [133.25, 49.85, 2, 0.2], [138.45, 49.85, 2, 0.2], [138.45, 49.85, 1, 0.2], [140.35, 51.75, 1, 0.2], [140.35, 52.15, 1, 0.2], [147.95, 59.75, 1, 0.2], [147.95, 59.75, 2, 0.2], [148.3, 60.1, 2, 0.2], [148.3, 73.45, 2, 0.2], [146.8, 74.95, 2, 0.2], [143.95, 74.95, 2, 0.2], [143.75, 75.15, 2, 0.2], [143.75, 75.15, 1, 0.2], [143.3561, 74.7561, 1, 0.2], [143.1001, 74.6562, 1, 0.2], [142.05, 74.7, 1, 0.2]], "INA_ALERT\u00001\u0000c0": [[14.3002, 49.69, 1, 0.2], [14.3001, 49.075, 1, 0.2], [14.3, 49.075, 1, 0.2], [14.3, 49.69, 1, 0.2]], "INA_ALERT\u00001\u0000c1\u0000c0": [[14.3, 49.69, 1, 0.2], [14.3, 49.69, 1, 0.2]], "INA_ALERT\u00001\u0000c1\u0000c1": [[14.3, 49.69, 1, 0.2], [14.3, 50.6, 1, 0.2], [16.625, 52.95, 1, 0.2]], "INA_ALERT\u00002\u0000c0\u0000c0": [[53.5889, 75.8089, 1, 0.2], [53.5889, 75.809, 1, 0.2]], "INA_ALERT\u00002\u0000c0\u0000c1": [[53.5889, 75.809, 1, 0.2], [53.595, 76.425, 1, 0.2], [53.6, 76.425, 1, 0.2], [53.6, 75.8089, 1, 0.2]], "INA_ALERT\u00002\u0000c1\u0000c0": [[53.6, 75.8089, 1, 0.2], [53.6, 75.8089, 1, 0.2]], "INA_ALERT\u00002\u0000c1\u0000c1": [[53.6, 75.8089, 1, 0.2], [53.6, 74.9, 1, 0.2], [51.25, 72.55, 1, 0.2]], "INA_ALERT\u00003\u0000c0\u0000rr": [[141.975, 75.8089, 1, 0.2]], "INA_ALERT\u00003\u0000c1\u0000rr\u0000c0": [[141.975, 75.8089, 1, 0.2], [141.975, 75.8087, 1, 0.2]], "INA_ALERT\u00003\u0000c1\u0000rr\u0000c1": [[141.975, 75.8087, 1, 0.2], [141.95, 74.7, 1, 0.2], [139.675, 72.525, 1, 0.2]], "INA_ALERT\u00004": [[45.9689, 49.69, 1, 0.2], [45.9689, 48.5798, 1, 0.2]], "INA_ALERT\u00005\u0000c0\u0000c0": [[125.4989, 49.69, 1, 0.2], [125.4989, 49.69, 1, 0.2]], "INA_ALERT\u00005\u0000c0\u0000c1": [[125.4989, 49.69, 1, 0.2], [125.4995, 49.075, 1, 0.2], [125.5, 49.075, 1, 0.2], [125.5, 49.69, 1, 0.2]], "INA_ALERT\u00005\u0000c1\u0000c0": [[125.5, 49.69, 1, 0.2], [125.5, 49.69, 1, 0.2]], "INA_ALERT\u00005\u0000c1\u0000c1": [[125.5, 49.69, 1, 0.2], [125.5, 50.625, 1, 0.2], [127.825, 52.95, 1, 0.2]], "INA_ALERT\u00006": [[6.4998, 96.8891, 1, 0.2], [6.4998, 95.7788, 1, 0.2]], "INA_ALERT\u00007\u0000c0": [[78.7746, 46.6085, 1, 0.2], [78.7746, 46.6085, 1, 0.2]], "INA_ALERT\u00007\u0000c1\u0000c0": [[78.7746, 46.6085, 1, 0.2], [78.7746, 46.6085, 1, 0.2]], "INA_ALERT\u00007\u0000c1\u0000c1": [[78.7746, 46.6085, 1, 0.2], [78.7746, 47.734, 1, 0.2]], "INA_ALERT\u00008\u0000c0": [[78.7, 47.8, 1, 0.2], [78.7, 48.4, 1, 0.2], [79.0, 48.7, 1, 0.2], [80.5, 48.7, 1, 0.2], [82.05, 47.15, 1, 0.2]], "INA_ALERT\u00008\u0000c1": [[82.05, 47.15, 1, 0.2], [82.1, 47.1, 1, 0.2], [82.1, 46.6, 1, 0.2], [81.7226, 45.7721, 1, 0.2], [81.0113, 45.1541, 1, 0.2]], "INA_ALERT\u00009": [[82.1, 47.2, 1, 0.2], [86.4, 51.5, 1, 0.2], [114.1, 51.5, 1, 0.2], [114.1, 51.5, 2, 0.2], [120.3, 57.7, 2, 0.2], [120.3, 57.7, 1, 0.2], [122.0, 59.4, 1, 0.2], [130.7, 59.4, 1, 0.2], [131.8, 58.3, 1, 0.2], [131.8, 56.2, 1, 0.2], [128.8, 53.2, 1, 0.2], [128.1526, 53.2, 1, 0.2], [127.9125, 53.075, 1, 0.2], [127.825, 52.95, 1, 0.2]], "IOEXP_INT#\u00000": [[72.136, 47.179, 1, 0.2], [72.136, 47.7622, 1, 0.2]], "IOEXP_INT#\u00001\u0000c0": [[72.9249, 46.6085, 1, 0.2], [72.9249, 46.6082, 1, 0.2]], "IOEXP_INT#\u00001\u0000c1": [[72.9249, 46.6082, 1, 0.2], [72.9249, 46.6082, 1, 0.2]], "IOEXP_INT#\u00001\u0000c2": [[72.9249, 46.6082, 1, 0.2], [72.9249, 46.6082, 1, 0.2]], "IOEXP_INT#\u00001\u0000c3": [[72.9249, 46.6082, 1, 0.2], [72.9249, 46.6082, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4": [[72.9249, 46.6082, 1, 0.2], [72.9249, 45.483, 1, 0.2]], "IOEXP_INT#\u00002\u0000c0": [[72.136, 47.7622, 1, 0.2], [72.4276, 47.4713, 1, 0.2]], "IOEXP_INT#\u00002\u0000c1\u0000c0": [[72.4276, 47.4713, 1, 0.2], [72.4276, 47.4713, 1, 0.2]], "IOEXP_INT#\u00002\u0000c1\u0000c1": [[72.4276, 47.4713, 1, 0.2], [72.9, 47.0, 1, 0.2], [72.9064, 46.6082, 1, 0.2]], "IOEXP_INT#\u00002\u0000c1\u0000c2": [[72.9064, 46.6082, 1, 0.2], [72.9064, 46.6082, 1, 0.2]], "IOEXP_INT#\u00002\u0000c2": [[72.9064, 46.6082, 1, 0.2], [72.9064, 46.6082, 1, 0.2]], "IOEXP_INT#\u00002\u0000c3\u0000c0": [[72.9064, 46.6082, 1, 0.2], [72.9064, 46.6082, 1, 0.2]], "IOEXP_INT#\u00002\u0000c3\u0000c1": [[72.9064, 46.6082, 1, 0.2], [72.9249, 45.483, 1, 0.2]], "K1_PWR\u00000": [[35.8673, 31.5011, 1, 0.2], [35.2841, 31.5011, 1, 0.2]], "K1_PWR\u00001": [[89.0742, 55.1051, 1, 0.2], [89.0742, 56.3906, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c0": [[35.2841, 31.5011, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c1": [[35.5802, 31.7927, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c1": [[35.5802, 31.7927, 1, 0.2], [36.4, 32.6, 1, 0.2], [45.0, 32.6, 1, 0.2], [45.8201, 32.2159, 1, 0.2], [46.1799, 31.7841, 1, 0.2], [47.0, 31.4, 1, 0.2], [49.6, 31.4, 1, 0.2], [49.6, 31.4, 2, 0.2], [54.3, 26.7, 2, 0.2], [56.9, 26.7, 2, 0.2], [56.9, 26.7, 1, 0.2], [59.7, 26.7, 1, 0.2], [59.7, 26.7, 2, 0.2], [64.4, 31.4, 2, 0.2], [77.9, 31.4, 2, 0.2], [77.9, 31.4, 1, 0.2], [80.9, 34.4, 1, 0.2], [80.9, 34.4, 2, 0.2], [84.7, 38.2, 2, 0.2], [84.7, 43.4, 2, 0.2], [83.9, 44.2, 2, 0.2], [83.9, 44.2, 1, 0.2], [83.9, 47.9, 1, 0.2], [83.9, 47.9, 2, 0.2], [89.1, 53.1, 2, 0.2], [89.0742, 56.3906, 2, 0.2], [89.0742, 56.3906, 1, 0.2], [89.0742, 56.3906, 1, 0.2]], "K1_VDN\u00000": [[35.8673, 38.0009, 1, 0.2], [35.2841, 38.0009, 1, 0.2]], "K1_VDN\u00001": [[89.0742, 49.6339, 1, 0.2], [89.0742, 48.3484, 1, 0.2]], "K1_VUP\u00000": [[35.8673, 35.0012, 1, 0.2], [35.2841, 35.0012, 1, 0.2]], "K1_VUP\u00001": [[87.8042, 49.6339, 1, 0.2], [87.8042, 48.3484, 1, 0.2]], "K2_PWR\u00000\u0000c0": [[32.0218, 94.0004, 1, 0.2], [32.0218, 94.0004, 1, 0.2]], "K2_PWR\u00000\u0000c1\u0000c0": [[32.0218, 94.0004, 1, 0.2], [32.0218, 94.0004, 1, 0.2]], "K2_PWR\u00000\u0000c1\u0000c1": [[32.0218, 94.0004, 1, 0.2], [32.605, 94.0004, 1, 0.2]], "K2_PWR\u00001": [[90.3442, 49.6339, 1, 0.2], [90.3442, 48.3484, 1, 0.2]], "K2_PWR\u00002": [[32.605, 94.0004, 1, 0.2], [32.2, 94.0, 1, 0.2], [32.2, 94.0, 2, 0.2], [27.6, 89.4, 2, 0.2], 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0.2], [113.8, 46.2, 1, 0.2], [112.8, 47.2, 1, 0.2], [92.8, 47.2, 1, 0.2], [91.6142, 48.3484, 1, 0.2]], "K3_PWR\u00000": [[120.2, 94.2, 1, 0.2], [120.15, 94.45, 1, 0.2], [119.845, 94.7, 1, 0.2], [106.6, 94.7, 1, 0.2], [103.7, 97.6, 1, 0.2], [103.7, 97.6, 2, 0.2], [102.3, 99.0, 2, 0.2], [102.3, 99.0, 1, 0.2], [100.8, 100.5, 1, 0.2], [98.3, 100.5, 1, 0.2], [98.3, 100.5, 2, 0.2], [97.3, 99.5, 2, 0.2], [97.3, 99.2, 2, 0.2], [97.3, 99.2, 1, 0.2], [97.3, 93.5, 1, 0.2], [97.3, 93.5, 2, 0.2], [85.3, 81.5, 2, 0.2], [85.3, 65.4, 2, 0.2], [88.9, 61.8, 2, 0.2], [88.9, 61.8, 1, 0.2], [91.9, 58.8, 1, 0.2], [92.7, 58.8, 1, 0.2], [92.7, 58.8, 2, 0.2], [93.2, 58.3, 2, 0.2], [96.5, 58.3, 2, 0.2], [96.5, 58.3, 1, 0.2], [97.7, 57.1, 1, 0.2], [97.7, 52.2, 1, 0.2], [97.7, 52.2, 2, 0.2], [97.6, 50.8, 2, 0.2], [97.6, 50.8, 1, 0.2], [97.4, 51.0, 1, 0.2], [94.8, 51.0, 1, 0.2], [94.4, 50.6, 1, 0.2]], "K3_PWR\u00001": [[94.1542, 49.6339, 1, 0.2], [94.1542, 48.3484, 1, 0.2]], "K3_VDN\u00000\u0000rr": [[120.4011, 87.5005, 1, 0.2], [120.9843, 87.5005, 1, 0.2]], "K3_VDN\u00001\u0000c0": [[89.6642, 40.7464, 1, 0.2], [89.6642, 40.7464, 1, 0.2]], "K3_VDN\u00001\u0000c1\u0000c0": [[89.6642, 40.7464, 1, 0.2], [89.6642, 40.7464, 1, 0.2]], "K3_VDN\u00001\u0000c1\u0000c1": [[89.6642, 40.7464, 1, 0.2], [89.6642, 42.032, 1, 0.2]], "K3_VDN\u00002\u0000rr": [[120.9843, 87.5005, 1, 0.2], [121.8643, 88.4531, 1, 0.2], [122.2, 88.6, 1, 0.2], [122.4, 88.6, 1, 0.2], [122.4, 88.6, 2, 0.2], [123.2, 89.4, 2, 0.2], [139.8, 89.4, 2, 0.2], [150.2, 79.0, 2, 0.2], [150.2, 78.4, 2, 0.2], [154.4, 74.2, 2, 0.2], [154.4, 74.2, 1, 0.2], [155.4, 73.2, 1, 0.2], [155.4, 43.8, 1, 0.2], [148.6, 37.0, 1, 0.2], [146.2, 37.0, 1, 0.2], [146.2, 37.0, 2, 0.2], [145.1, 37.0, 2, 0.2], [144.2655, 37.3716, 2, 0.2], [143.0007, 38.777, 2, 0.2], [142.5, 39.0, 2, 0.2], [142.2, 39.0, 2, 0.2], [140.8, 37.6, 2, 0.2], [140.8, 36.6, 2, 0.2], [140.8, 36.6, 1, 0.2], [134.6, 30.4, 1, 0.2], [134.6, 29.2, 1, 0.2], [134.6, 29.2, 2, 0.2], [139.0, 24.8, 2, 0.2], [139.0, 18.0, 2, 0.2], [138.6, 17.6, 2, 0.2], [113.8, 17.6, 2, 0.2], [108.8, 22.6, 2, 0.2], [108.8, 22.6, 1, 0.2], [107.6, 23.8, 1, 0.2], [107.6, 23.8, 2, 0.2], [119.0, 35.2, 2, 0.2], [119.0, 36.6, 2, 0.2], [121.6, 39.2, 2, 0.2], [121.6, 39.2, 1, 0.2], [121.6, 39.5, 1, 0.2], [121.3834, 40.0076, 1, 0.2], [116.8, 44.4, 1, 0.2], [116.8, 44.4, 2, 0.2], [103.6, 57.6, 2, 0.2], [96.6, 57.6, 2, 0.2], [95.6, 56.6, 2, 0.2], [93.4, 56.6, 2, 0.2], [88.6, 51.8, 2, 0.2], [88.6, 48.0, 2, 0.2], [88.4, 47.8, 2, 0.2], [88.4, 47.8, 1, 0.2], [90.2, 46.2, 1, 0.2], [90.2, 46.2, 2, 0.2], [90.2, 42.2, 2, 0.2], [89.8, 41.8, 2, 0.2], [89.8, 41.8, 1, 0.2], [89.6642, 42.032, 1, 0.2]], "K3_VUP\u00000": [[120.4011, 90.5002, 1, 0.2], [120.9843, 90.5002, 1, 0.2]], "K3_VUP\u00001": [[95.4242, 49.6339, 1, 0.2], [95.4242, 48.3484, 1, 0.2]], "K3_VUP\u00002\u0000c0": [[120.9843, 90.5002, 1, 0.2], [120.6945, 90.2086, 1, 0.2]], "K3_VUP\u00002\u0000c1\u0000c0": [[120.6945, 90.2086, 1, 0.2], [120.6945, 90.2086, 1, 0.2]], "K3_VUP\u00002\u0000c1\u0000c1": [[120.6945, 90.2086, 1, 0.2], [118.5, 88.0, 1, 0.2], [118.5, 80.7, 1, 0.2], [118.5, 80.7, 2, 0.2], [118.5, 68.25, 2, 0.2], [118.5, 68.25, 1, 0.2], [118.5, 66.4, 1, 0.2], [118.5, 66.4, 2, 0.2], [117.85, 65.75, 2, 0.2], [117.85, 56.25, 2, 0.2], [113.45, 51.85, 2, 0.2], [113.45, 51.5, 2, 0.2], [112.8, 50.85, 2, 0.2], [112.8, 50.85, 1, 0.2], [110.25, 48.3, 1, 0.2], [95.4242, 48.3484, 1, 0.2]], "K4_PWR\u00000\u0000c0": [[67.5361, 31.5011, 1, 0.2], [67.5361, 31.5011, 1, 0.2]], "K4_PWR\u00000\u0000c1\u0000c0": [[67.5361, 31.5011, 1, 0.2], [67.5361, 31.5011, 1, 0.2]], "K4_PWR\u00000\u0000c1\u0000c1": [[67.5361, 31.5011, 1, 0.2], [66.9529, 31.5011, 1, 0.2]], "K4_PWR\u00001\u0000c0": [[88.3942, 35.2753, 1, 0.2], [88.3942, 35.2753, 1, 0.2]], "K4_PWR\u00001\u0000c1\u0000c0": [[88.3942, 35.2753, 1, 0.2], [88.3942, 35.2753, 1, 0.2]], "K4_PWR\u00001\u0000c1\u0000c1": [[88.3942, 35.2753, 1, 0.2], [88.3942, 33.9898, 1, 0.2]], "K4_VDN\u00000\u0000c0": [[67.5361, 38.0009, 1, 0.2], [67.5361, 38.0009, 1, 0.2]], "K4_VDN\u00000\u0000c1\u0000c0": [[67.5361, 38.0009, 1, 0.2], [67.5361, 38.0009, 1, 0.2]], "K4_VDN\u00000\u0000c1\u0000c1": [[67.5361, 38.0009, 1, 0.2], [66.9529, 38.0009, 1, 0.2]], "K4_VDN\u00001\u0000c0": [[90.9342, 35.2753, 1, 0.2], [90.9342, 35.2753, 1, 0.2]], "K4_VDN\u00001\u0000c1\u0000c0": [[90.9342, 35.2753, 1, 0.2], [90.9342, 35.2753, 1, 0.2]], "K4_VDN\u00001\u0000c1\u0000c1": [[90.9342, 35.2753, 1, 0.2], [90.9342, 33.9898, 1, 0.2]], "K4_VDN\u00002\u0000c0\u0000c0": [[66.9529, 38.0009, 1, 0.2], [67.2439, 37.7093, 1, 0.2]], "K4_VDN\u00002\u0000c0\u0000c1": [[67.2439, 37.7093, 1, 0.2], [67.2439, 37.7093, 1, 0.2]], "K4_VDN\u00002\u0000c1\u0000c0": [[67.2439, 37.7093, 1, 0.2], [67.2439, 37.7093, 1, 0.2]], "K4_VDN\u00002\u0000c1\u0000c1": [[67.2439, 37.7093, 1, 0.2], [68.95, 36.0, 1, 0.2], [76.65, 36.0, 1, 0.2], [77.75, 34.9, 1, 0.2], [79.4, 34.9, 1, 0.2], [79.9, 34.4, 1, 0.2], [79.9, 34.4, 2, 0.2], [80.55, 33.75, 2, 0.2], [81.25, 33.75, 2, 0.2], [82.85, 35.35, 2, 0.2], [86.3, 35.35, 2, 0.2], [86.3, 35.35, 1, 0.2], [88.1, 33.55, 1, 0.2], [90.5, 33.55, 1, 0.2], [90.9342, 33.9898, 1, 0.2]], "K4_VUP\u00000\u0000c0": [[67.5361, 35.0012, 1, 0.2], [67.5361, 35.0012, 1, 0.2]], "K4_VUP\u00000\u0000c1\u0000c0": [[67.5361, 35.0012, 1, 0.2], [67.5361, 35.0012, 1, 0.2]], "K4_VUP\u00000\u0000c1\u0000c1": [[67.5361, 35.0012, 1, 0.2], [66.9529, 35.0012, 1, 0.2]], "K4_VUP\u00001\u0000c0": [[89.6642, 35.2753, 1, 0.2], [89.6642, 35.2753, 1, 0.2]], "K4_VUP\u00001\u0000c1\u0000c0": [[89.6642, 35.2753, 1, 0.2], [89.6642, 35.2753, 1, 0.2]], "K4_VUP\u00001\u0000c1\u0000c1": [[89.6642, 35.2753, 1, 0.2], [89.6642, 33.9898, 1, 0.2]], "K5_PWR\u00000\u0000c0": [[147.0686, 31.5011, 1, 0.2], [147.0686, 31.5011, 1, 0.2]], "K5_PWR\u00000\u0000c1\u0000rr\u0000c0": [[147.0686, 31.5011, 1, 0.2], [147.0686, 31.5011, 1, 0.2]], "K5_PWR\u00000\u0000c1\u0000rr\u0000c1": [[147.0686, 31.5011, 1, 0.2], [146.4853, 31.5011, 1, 0.2]], "K5_PWR\u00001\u0000c0": [[92.2042, 35.2753, 1, 0.2], [92.2042, 35.2753, 1, 0.2]], "K5_PWR\u00001\u0000c1\u0000rr\u0000c0": [[92.2042, 35.2753, 1, 0.2], [92.2042, 35.2753, 1, 0.2]], "K5_PWR\u00001\u0000c1\u0000rr\u0000c1": [[92.2042, 35.2753, 1, 0.2], [92.2042, 33.9898, 1, 0.2]], "K5_PWR\u00002\u0000rr": [[146.4853, 31.5011, 1, 0.2], [144.0, 31.5, 1, 0.2], [143.3, 30.8, 1, 0.2], [141.1, 30.8, 1, 0.2], [140.4, 31.5, 1, 0.2], [140.4, 31.5, 2, 0.2], [138.3, 33.6, 2, 0.2], [119.7, 33.6, 2, 0.2], [119.7, 33.6, 1, 0.2], [115.0, 38.3, 1, 0.2], [110.0, 38.3, 1, 0.2], [110.0, 38.3, 2, 0.2], [109.5, 38.8, 2, 0.2], [97.9, 38.8, 2, 0.2], [97.5, 38.4, 2, 0.2], [97.5, 38.4, 1, 0.2], [96.0, 36.9, 1, 0.2], [93.1, 36.9, 1, 0.2], [92.8, 36.6, 1, 0.2], [92.8, 34.6, 1, 0.2], [92.2042, 33.9898, 1, 0.2]], "K5_VDN\u00000\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c1": [[147.0686, 38.0009, 1, 0.2], [146.4853, 38.0009, 1, 0.2]], "K5_VDN\u00001\u0000c0": [[94.7442, 35.2753, 1, 0.2], [94.7442, 35.2753, 1, 0.2]], "K5_VDN\u00001\u0000c1\u0000c0": [[94.7442, 35.2753, 1, 0.2], [94.7442, 35.2753, 1, 0.2]], "K5_VDN\u00001\u0000c1\u0000c1": [[94.7442, 35.2753, 1, 0.2], [94.7442, 33.9898, 1, 0.2]], "K5_VUP\u00000": [[146.8, 34.8, 1, 0.2], [145.5, 33.5, 1, 0.2], [142.5, 33.5, 1, 0.2], [141.7, 32.7, 1, 0.2], [140.4, 32.7, 1, 0.2], [139.2, 31.5, 1, 0.2], [139.2, 31.5, 2, 0.2], [138.4, 30.7, 2, 0.2], [116.8, 30.7, 2, 0.2], [114.8, 28.7, 2, 0.2], [114.8, 28.7, 1, 0.2], [110.8, 24.7, 1, 0.2], [102.7, 24.7, 1, 0.2], [93.5, 33.9, 1, 0.2]], "K5_VUP\u00000\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c1": [[147.0686, 35.0012, 1, 0.2], [146.4853, 35.0012, 1, 0.2]], "K5_VUP\u00001\u0000c0": [[93.4742, 35.2753, 1, 0.2], [93.4742, 35.2753, 1, 0.2]], "K5_VUP\u00001\u0000c1\u0000c0": [[93.4742, 35.2753, 1, 0.2], [93.4742, 35.2753, 1, 0.2]], "K5_VUP\u00001\u0000c1\u0000c1": [[93.4742, 35.2753, 1, 0.2], [93.4742, 33.9898, 1, 0.2]], "KEY_OE#\u00000\u0000c0": [[92.3262, 56.6803, 1, 0.2], [92.454, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c1": [[92.454, 56.6803, 1, 0.2], [92.454, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c2": [[92.454, 56.6803, 1, 0.2], [92.9094, 56.6803, 1, 0.2]], "KEY_OE#\u00001": [[91.6142, 55.1051, 1, 0.2], [91.0132, 55.1051, 1, 0.2]], "KEY_OE#\u00002\u0000c0": [[92.2042, 40.7464, 1, 0.2], [92.2042, 40.7464, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c0": [[92.2042, 40.7464, 1, 0.2], [92.2042, 40.7464, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c1": [[92.2042, 40.7464, 1, 0.2], [92.2042, 42.032, 1, 0.2]], "KEY_OE#\u00003": [[91.3664, 73.7362, 1, 0.2], [91.3664, 75.0217, 1, 0.2]], "KEY_OE#\u00004\u0000c0\u0000c0": [[92.9094, 56.6803, 1, 0.2], [92.7547, 56.6902, 1, 0.2], [92.4907, 56.5901, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c0\u0000c1": [[92.454, 56.5532, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c0": [[92.454, 56.5532, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c1": [[92.454, 56.5532, 1, 0.2], [91.3122, 55.4056, 1, 0.2]], "KEY_OE#\u00004\u0000c2": [[91.3122, 55.4056, 1, 0.2], [91.0132, 55.1051, 1, 0.2]], "KEY_OE#\u00005": [[91.9, 54.2, 1, 0.2], [91.9, 52.2, 1, 0.2], [91.9, 52.2, 2, 0.2], [92.2, 51.9, 2, 0.2], [92.2042, 42.032, 2, 0.2], [92.2042, 42.032, 1, 0.2], [92.2042, 42.032, 1, 0.2]], "KEY_OE#\u00006": [[92.0, 39.8, 1, 0.2], [90.3, 38.1, 1, 0.2], [90.0, 38.1, 1, 0.2], [90.0, 38.1, 2, 0.2], [85.2, 33.3, 2, 0.2], [85.2, 30.0, 2, 0.2], [85.2, 30.0, 1, 0.2], [84.8, 29.6, 1, 0.2], [84.8259, 27.0942, 1, 0.2]], "KEY_RCLK\u00000": [[93.1, 56.0, 1, 0.2], [93.4, 56.3, 1, 0.2], [93.4, 62.1, 1, 0.2], [90.9, 64.6, 1, 0.2], [90.9, 65.8, 1, 0.2], [91.3, 66.2, 1, 0.2], [91.7, 66.2, 1, 0.2], [92.2, 66.7, 1, 0.2], [92.2, 66.7, 2, 0.2], [93.1, 67.6, 2, 0.2], [93.1, 69.9, 2, 0.2], [93.1, 69.9, 1, 0.2], [92.9, 70.1, 1, 0.2], [92.9, 72.8, 1, 0.2]], "KEY_RCLK\u00001\u0000c0": [[93.4742, 40.7464, 1, 0.2], [93.4742, 40.7464, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c0": [[93.4742, 40.7464, 1, 0.2], [93.4742, 40.7464, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c1": [[93.4742, 40.7464, 1, 0.2], [93.4742, 42.032, 1, 0.2]], "KEY_RCLK\u00002": [[92.6364, 73.7362, 1, 0.2], [92.6364, 75.0217, 1, 0.2]], "KEY_RCLK\u00003\u0000c0\u0000c0": [[92.8842, 56.2106, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c0": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.9, 52.2, 1, 0.15], [92.9, 52.2, 2, 0.15], [93.5, 51.6, 2, 0.15], [93.4811, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c3\u0000c0": [[93.4811, 44.6001, 2, 0.15], [93.4811, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c3\u0000c1": [[93.4811, 44.6001, 2, 0.15], [93.4742, 42.032, 2, 0.15], [93.4742, 42.032, 1, 0.15], [93.4742, 42.032, 1, 0.15]], "KEY_RCLK\u00004": [[93.5, 44.6, 2, 0.2], [94.0, 44.6, 2, 0.2], [94.0, 44.6, 1, 0.2], [95.6, 44.6, 1, 0.2], [95.6, 44.6, 2, 0.2], [96.7, 43.5, 2, 0.2], [96.7, 34.6, 2, 0.2], [97.1, 34.2, 2, 0.2], [97.1, 33.2, 2, 0.2], [98.4, 31.9, 2, 0.2], [98.4, 31.9, 1, 0.2], [100.3, 30.0, 1, 0.2], [100.3, 30.0, 2, 0.2], [96.8, 26.5, 2, 0.2], [96.7512, 22.004, 2, 0.2], [96.7512, 22.004, 1, 0.2], [96.7512, 22.004, 1, 0.2]], "KEY_SER\u00000": [[90.3442, 55.1051, 1, 0.2], [90.3442, 56.3906, 1, 0.2]], "KEY_SRCLK\u00000\u0000c0": [[94.1542, 55.1051, 1, 0.2], [94.1542, 55.1052, 1, 0.2]], "KEY_SRCLK\u00000\u0000c1": [[94.1542, 55.1052, 1, 0.2], [94.1542, 55.1052, 1, 0.2]], "KEY_SRCLK\u00000\u0000c2": [[94.1542, 55.1052, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c3": [[94.1542, 55.1053, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4": [[94.1542, 55.1053, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00001\u0000c0": [[94.7442, 40.7464, 1, 0.2], [94.7442, 40.7464, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c0": [[94.7442, 40.7464, 1, 0.2], [94.7442, 40.7464, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c1": [[94.7442, 40.7464, 1, 0.2], [94.7442, 42.032, 1, 0.2]], "KEY_SRCLK\u00002": [[93.9064, 73.7362, 1, 0.2], [93.9064, 75.0217, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0": [[94.1542, 56.3906, 1, 0.2], [94.1682, 55.1053, 1, 0.2]], "KEY_SRCLK\u00003\u0000c1": [[94.1682, 55.1053, 1, 0.2], [94.1682, 55.1052, 1, 0.2]], "KEY_SRCLK\u00003\u0000c2": [[94.1682, 55.1052, 1, 0.2], [94.2, 52.2, 1, 0.2], [94.2, 52.2, 2, 0.2], [94.7, 51.7, 2, 0.2], [94.7442, 42.032, 2, 0.2], [94.7442, 42.032, 1, 0.2], [94.7442, 42.032, 1, 0.2]], "KEY_SRCLK\u00004\u0000rr": [[94.9, 41.8, 2, 0.2], [94.9, 35.5, 2, 0.2], [96.6, 33.8, 2, 0.2], [96.6, 32.8, 2, 0.2], [95.7, 31.9, 2, 0.2], [94.4, 31.9, 2, 0.2], [94.4, 31.9, 1, 0.2], [97.9, 28.4, 1, 0.2], [97.8041, 21.4, 1, 0.2], [97.5, 21.1, 1, 0.2], [97.2, 21.1, 1, 0.2], [96.7512, 20.734, 1, 0.2]], "NTC1\u00000\u0000c0": [[77.8721, 10.3975, 1, 0.2], [77.8721, 10.3975, 1, 0.2]], "NTC1\u00000\u0000c1\u0000c0": [[77.8721, 10.3975, 1, 0.2], [77.8721, 10.3975, 1, 0.2]], "NTC1\u00000\u0000c1\u0000c1": [[77.8721, 10.3975, 1, 0.2], [77.8721, 10.0945, 1, 0.2]], "NTC1\u00000\u0000c2": [[77.8721, 10.0945, 1, 0.2], [77.8721, 10.0945, 1, 0.2]], "NTC1\u00000\u0000c3": [[77.8721, 10.0945, 1, 0.2], [77.8721, 9.8473, 1, 0.2]], "NTC1\u00001\u0000c0": [[77.8645, 9.524, 1, 0.2], [77.8645, 9.8473, 1, 0.2]], "NTC1\u00001\u0000c1": [[77.8645, 9.8473, 1, 0.2], [77.8645, 9.8473, 1, 0.2]], "NTC1\u00001\u0000c2": [[77.8645, 9.8473, 1, 0.2], [77.8645, 10.0945, 1, 0.2]], "NTC1\u00002\u0000c0": [[77.8721, 9.8473, 1, 0.2], [77.8721, 9.8475, 1, 0.2]], "NTC1\u00002\u0000c1": [[77.8721, 9.8475, 1, 0.2], [77.8721, 9.8475, 1, 0.2]], "NTC1\u00002\u0000c2": [[77.8721, 9.8475, 1, 0.2], [77.8721, 9.8475, 1, 0.2]], "NTC1\u00002\u0000c3": [[77.8721, 9.8475, 1, 0.2], [77.8721, 9.8475, 1, 0.2]], "NTC1\u00002\u0000c4": [[77.8721, 9.8475, 1, 0.2], [77.8645, 10.0943, 1, 0.2]], "NTC1\u00002\u0000c5": [[77.8645, 10.0943, 1, 0.2], [77.8645, 10.0943, 1, 0.2]], "NTC1\u00002\u0000c6": [[77.8645, 10.0943, 1, 0.2], [77.8645, 10.0943, 1, 0.2]], "NTC1\u00002\u0000c7": [[77.8645, 10.0943, 1, 0.2], [77.8645, 10.0943, 1, 0.2]], "NTC1\u00002\u0000c8": [[77.8645, 10.0943, 1, 0.2], [77.8645, 10.0945, 1, 0.2]], "NTC1\u00003\u0000c0\u0000c0": [[78.1, 10.6, 1, 0.2], [79.2506, 10.574, 1, 0.2]], "NTC1\u00003\u0000c0\u0000c1": [[79.2506, 10.574, 1, 0.2], [79.2506, 10.574, 1, 0.2]], "NTC1\u00003\u0000c1": [[79.2506, 10.574, 1, 0.2], [79.2506, 10.574, 1, 0.2]], "NTC1\u00004": [[80.0, 11.0, 1, 0.2], [80.3, 11.15, 1, 0.2], [80.6, 11.6354, 1, 0.2], [80.6, 13.8, 1, 0.2], [80.6, 13.8, 2, 0.2], [79.7, 14.7, 2, 0.2], [77.4, 14.7, 2, 0.2], [63.8, 28.3, 2, 0.2], [63.8, 28.3, 1, 0.2], [63.4, 28.7, 1, 0.2], [60.6, 28.7, 1, 0.2], [60.6, 28.7, 2, 0.2], [67.1, 35.2, 2, 0.2], [70.8, 35.2476, 2, 0.2], [70.8, 35.2476, 1, 0.2], [70.8, 35.2476, 1, 0.2]], "NTC2\u00000": [[77.865, 12.225, 1, 0.2], [77.865, 11.8548, 1, 0.2]], "NTC2\u00001\u0000c0": [[76.9854, 12.6772, 1, 0.2], [76.9854, 12.7709, 1, 0.2]], "NTC2\u00001\u0000c1": [[76.9854, 12.7709, 1, 0.2], [76.9854, 12.7709, 1, 0.2]], "NTC2\u00001\u0000c2": [[76.9854, 12.7709, 1, 0.2], [76.9854, 12.7709, 1, 0.2]], "NTC2\u00001\u0000c3": [[76.9854, 12.7709, 1, 0.2], [76.9854, 12.7709, 1, 0.2]], "NTC2\u00001\u0000c4": [[76.9854, 12.7709, 1, 0.2], [76.9854, 13.2604, 1, 0.2]], "NTC2\u00002\u0000c0\u0000c0": [[77.865, 11.8548, 1, 0.2], [79.2506, 11.844, 1, 0.2]], "NTC2\u00002\u0000c0\u0000c1": [[79.2506, 11.844, 1, 0.2], [79.2506, 11.844, 1, 0.2]], "NTC2\u00002\u0000c1": [[79.2506, 11.844, 1, 0.2], [79.2506, 11.844, 1, 0.2]], "NTC2\u00003\u0000c0": [[77.6, 12.45, 1, 0.2], [77.4, 12.45, 1, 0.2], [77.0791, 12.7709, 1, 0.2]], "NTC2\u00003\u0000c1": [[77.0791, 12.7709, 1, 0.2], [77.0791, 12.7709, 1, 0.2]], "NTC2\u00003\u0000c2\u0000c0": [[77.0791, 12.7709, 1, 0.2], [77.0791, 12.7709, 1, 0.2]], "NTC2\u00003\u0000c2\u0000c1": [[77.0791, 12.7709, 1, 0.2], [77.0, 12.85, 1, 0.2], [76.9854, 13.2604, 1, 0.2]], "NTC2\u00004": [[76.9, 13.3, 1, 0.2], [74.3, 15.9, 1, 0.2], [74.3, 21.7, 1, 0.2], [74.3, 21.7, 2, 0.2], [70.8, 25.2476, 2, 0.2], [70.8, 25.2476, 1, 0.2], [70.8, 25.2476, 1, 0.2]], "POGO1_PWR\u00000": [[24.45, 62.5, 1, 0.2], [26.7, 62.5, 1, 0.2], [26.9, 62.3, 1, 0.2], [26.9, 60.2, 1, 0.2], [27.15, 59.95, 1, 0.2], [29.2, 59.95, 1, 0.2], [30.45, 58.7, 1, 0.2], [30.45, 28.35, 1, 0.2], [31.3004, 27.5006, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c0": [[31.3004, 31.5011, 1, 0.2], [31.5, 31.3, 1, 0.2], [31.5, 30.0, 1, 0.2], [31.5, 30.0, 2, 0.2], [27.6, 26.1, 2, 0.2], [26.6, 26.1, 2, 0.2], [26.6, 26.1, 1, 0.2], [23.2, 22.7, 1, 0.2], [19.1, 22.7, 1, 0.2], [19.1, 22.7, 2, 0.2], [18.9, 22.9, 2, 0.2], [13.1, 22.9, 2, 0.2], [12.4, 23.6, 2, 0.2], [12.4, 29.7, 2, 0.2], [10.7, 31.4, 2, 0.2], [10.7, 31.4, 1, 0.2], [2.2, 39.9, 1, 0.2], [2.2, 67.7, 1, 0.2], [4.9, 70.4, 1, 0.2], [8.9, 70.4, 1, 0.2], [9.7439, 70.037, 1, 0.2], [11.2, 68.5, 1, 0.2], [11.2, 68.5, 2, 0.2], [11.9, 67.8, 2, 0.2], [21.6, 67.8, 2, 0.2], [21.6, 67.8, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c0": [[35.3009, 27.5006, 1, 0.2], [34.9, 27.5, 1, 0.2], [34.9, 27.5, 2, 0.2], [32.8, 25.4, 2, 0.2], [24.7, 25.4, 2, 0.2], [24.7, 25.4, 1, 0.2], [22.7, 23.4, 1, 0.2], [19.8, 23.4, 1, 0.2], [19.8, 23.4, 2, 0.2], [13.5, 23.4, 2, 0.2], [12.9, 24.0, 2, 0.2], [12.9, 30.4, 2, 0.2], [11.0, 32.3, 2, 0.2], [11.0, 32.3, 1, 0.2], [4.9, 38.4, 1, 0.2], [4.9, 66.8, 1, 0.2], [8.0, 69.9, 1, 0.2], [9.0, 69.9, 1, 0.2], [9.2, 69.7, 1, 0.2], [9.3, 67.8, 1, 0.2], [9.3, 67.8, 2, 0.2], [10.7, 66.4, 2, 0.2], [20.5, 66.4, 2, 0.2], [20.7, 66.2, 2, 0.2], [20.7, 66.2, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO2_PWR\u00000": [[36.5887, 98.0009, 1, 0.2], [40.7, 102.1, 1, 0.2], [48.7, 102.1, 1, 0.2], [51.1, 104.5, 1, 0.2], [51.1, 106.9, 1, 0.2], [51.9, 107.7, 1, 0.2], [90.0, 107.7, 1, 0.2], [102.3, 95.4, 1, 0.2], [102.3, 95.4, 2, 0.2], [114.5, 83.2, 2, 0.2], [114.5, 83.2, 1, 0.2], [115.7, 82.0, 1, 0.2], [115.7, 80.8, 1, 0.2], [115.7, 80.8, 2, 0.2], [115.7, 70.9, 2, 0.2], [115.7, 70.9, 1, 0.2], [113.6, 68.8, 1, 0.2], [113.6, 68.4, 1, 0.2], [111.6, 66.4, 1, 0.2], [111.6, 66.4, 2, 0.2], [108.9508, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1": [[36.5887, 94.0004, 1, 0.2], [44.6, 94.0, 1, 0.2], [44.6, 94.0, 2, 0.2], [45.3, 93.3, 2, 0.2], [59.6, 93.3, 2, 0.2], [59.6, 93.3, 1, 0.2], [60.8, 92.1, 1, 0.2], [101.9, 92.1, 1, 0.2], [102.3, 91.7, 1, 0.2], [102.3, 91.7, 2, 0.2], [103.7, 90.3, 2, 0.2], [103.7, 90.3, 1, 0.2], [106.2, 90.3, 1, 0.2], [115.0, 81.5, 1, 0.2], [115.0, 81.5, 2, 0.2], [115.0, 69.0, 2, 0.2], [115.0, 69.0, 1, 0.2], [115.0, 66.4, 1, 0.2], [115.0, 66.4, 2, 0.2], [115.0, 64.8, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VUP\u00000\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c1": [[32.5882, 98.0009, 1, 0.2], [32.8, 98.0, 1, 0.2], [32.8, 98.0, 2, 0.2], [36.0, 94.8, 2, 0.2], [59.2, 94.8, 2, 0.2], [59.2, 94.8, 1, 0.2], [61.2, 92.8, 1, 0.2], [102.3, 92.8, 1, 0.2], [102.3, 92.8, 2, 0.2], [113.2, 81.9, 2, 0.2], [113.2, 81.9, 1, 0.2], [114.3, 80.8, 1, 0.2], [114.3, 80.8, 2, 0.2], [114.3, 68.3, 2, 0.2], [114.3, 68.3, 1, 0.2], [114.1, 68.1, 1, 0.2], [114.1, 66.4, 1, 0.2], [114.1, 66.4, 2, 0.2], [111.4908, 63.7692, 2, 0.2]], "POGO3_VDN\u00000": [[136.9, 63.775, 1, 0.2], [138.125, 62.55, 1, 0.2], [140.7, 62.525, 1, 0.2]], "POGO3_VUP\u00000\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c1": [[120.97, 98.0009, 1, 0.2], [120.95, 94.8, 1, 0.2], [120.95, 94.8, 2, 0.2], [119.2, 93.05, 2, 0.2], [119.2, 89.65, 2, 0.2], [119.2, 89.65, 1, 0.2], [118.05, 88.5, 1, 0.2], [118.05, 81.5, 1, 0.2], [117.85, 81.3, 1, 0.2], [117.85, 81.3, 2, 0.2], [117.85, 69.9, 2, 0.2], [117.85, 69.9, 1, 0.2], [119.15, 68.6, 1, 0.2], [119.2, 66.95, 1, 0.2], [119.2, 66.95, 2, 0.2], [120.35, 65.8, 2, 0.2], [120.35, 59.85, 2, 0.2], [120.35, 59.85, 1, 0.2], [122.6, 59.85, 1, 0.2], [122.9, 60.15, 1, 0.2], [122.9, 62.25, 1, 0.2], [123.15, 62.5, 1, 0.2], [133.1, 62.5, 1, 0.2], [134.3508, 63.7692, 1, 0.2]], "POGO5_VDN\u00000\u0000c0": [[142.4991, 31.5011, 1, 0.2], [142.4991, 31.5011, 1, 0.2]], "POGO5_VDN\u00000\u0000c1": [[142.4991, 31.5011, 1, 0.2], [142.2, 32.1, 1, 0.2], [142.2, 32.1, 2, 0.2], [139.8, 34.5, 2, 0.2], [139.7, 59.2, 2, 0.2], [139.7, 59.2, 1, 0.2], [139.3, 59.6, 1, 0.2], [138.5, 59.6, 1, 0.2], [136.8908, 61.2292, 1, 0.2]], "SCL\u00000\u0000c0": [[47.9, 77.5, 2, 0.2], [47.9, 75.9, 2, 0.2], [47.9, 75.9, 1, 0.2], [47.9, 75.8, 1, 0.2]], "SCL\u00000\u0000c1": [[47.9, 75.8, 1, 0.2], [47.9, 73.3, 1, 0.2]], "SCL\u00000\u0000c2": [[47.9, 73.3, 1, 0.2], [47.9, 73.2, 1, 0.2], [48.1, 73.0, 1, 0.2], [48.2, 73.0, 1, 0.2]], "SCL\u00000\u0000c3": [[48.2, 73.0, 1, 0.2], [50.7, 73.0, 1, 0.2]], "SCL\u00000\u0000c4": [[50.7, 73.0, 1, 0.2], [50.8, 73.0, 1, 0.2], [52.45, 74.65, 1, 0.2]], "SCL\u00000\u0000c5": [[52.45, 74.65, 1, 0.2], [52.5, 74.7, 1, 0.2], [52.5, 75.0, 1, 0.2]], "SCL\u00001\u0000c0": [[109.8192, 33.21, 1, 0.2], [109.8192, 33.21, 1, 0.2]], "SCL\u00001\u0000c1\u0000c0": [[109.8192, 33.21, 1, 0.2], [109.8192, 33.21, 1, 0.2]], "SCL\u00001\u0000c1\u0000c1": [[109.8192, 33.21, 1, 0.2], [109.8192, 32.5099, 1, 0.2]], "SCL\u000010\u0000c0\u0000c0": [[98.1499, 19.2113, 1, 0.2], [98.1498, 19.2112, 1, 0.2]], "SCL\u000010\u0000c0\u0000c1": [[98.1498, 19.2112, 1, 0.2], [97.8709, 18.835, 1, 0.2]], "SCL\u000010\u0000c1": [[97.8709, 18.835, 1, 0.2], [97.5932, 18.4606, 1, 0.2], [97.0756, 18.197, 1, 0.2], [96.7512, 18.194, 1, 0.2]], "SCL\u000011\u0000c0\u0000rr\u0000c0": [[98.15, 19.3, 1, 0.15], [102.1, 23.3, 1, 0.15], [102.1, 24.2, 1, 0.15], [102.1, 24.2, 2, 0.15], [103.3, 25.4, 2, 0.15], [103.3, 25.4, 1, 0.15], [103.9951, 25.1843, 1, 0.15]], "SCL\u000011\u0000c0\u0000rr\u0000c1": [[103.9951, 25.1843, 1, 0.15], [104.025, 25.175, 1, 0.15]], "SCL\u000011\u0000c1\u0000rr\u0000c0": [[104.025, 25.175, 1, 0.15], [104.0252, 25.1752, 1, 0.15]], "SCL\u000011\u0000c1\u0000rr\u0000c1": [[104.0252, 25.1752, 1, 0.15], [107.6, 28.8, 1, 0.15], [107.6, 31.4, 1, 0.15], [107.6, 31.4, 2, 0.15], [109.3, 33.1, 2, 0.15], [109.6, 33.1, 2, 0.15], [109.6, 33.1, 1, 0.15], [109.8192, 32.5099, 1, 0.15]], "SCL\u000012": [[109.4, 33.2, 1, 0.2], [109.3188, 33.21, 1, 0.2]], "SCL\u000013\u0000c0": [[109.9, 33.0, 2, 0.15], [110.9, 33.0, 2, 0.15], [114.7, 36.8, 2, 0.15], [114.7, 37.2, 2, 0.15], [114.8, 37.3, 2, 0.15]], "SCL\u000013\u0000c1": [[114.8, 37.3, 2, 0.15], [114.8, 37.3, 2, 0.15]], "SCL\u000013\u0000c2": [[114.8, 37.3, 2, 0.15], [120.85, 43.35, 2, 0.15]], "SCL\u000013\u0000c3": [[120.85, 43.35, 2, 0.15], [120.85, 43.35, 2, 0.15]], "SCL\u000013\u0000c4": [[120.85, 43.35, 2, 0.15], [121.75, 44.25, 2, 0.15]], "SCL\u000013\u0000c5": [[121.75, 44.25, 2, 0.15], [121.75, 44.25, 2, 0.15]], "SCL\u000013\u0000c6": [[121.75, 44.25, 2, 0.15], [121.9, 44.4, 2, 0.15]], "SCL\u000013\u0000c7": [[121.9, 44.4, 2, 0.15], [121.9, 44.4, 2, 0.15]], "SCL\u000013\u0000c8": [[121.9, 44.4, 2, 0.15], [122.4, 44.9, 2, 0.15]], "SCL\u000013\u0000c9": [[122.4, 44.9, 2, 0.15], [122.4, 44.9, 2, 0.15]], "SCL\u000013\u0000c10": [[122.4, 44.9, 2, 0.15], [122.45, 44.95, 2, 0.15]], "SCL\u000013\u0000c11": [[122.45, 44.95, 2, 0.15], [122.45, 44.95, 2, 0.15]], "SCL\u000013\u0000c12": [[122.45, 44.95, 2, 0.15], [126.45, 48.95, 2, 0.15]], "SCL\u000013\u0000c13": [[126.45, 48.95, 2, 0.15], [126.45, 48.95, 2, 0.15]], "SCL\u000013\u0000c14": [[126.45, 48.95, 2, 0.15], [126.5, 49.0, 2, 0.15]], "SCL\u000013\u0000c15": [[126.5, 49.0, 2, 0.15], [126.5, 49.0, 2, 0.15]], "SCL\u000013\u0000c16": [[126.5, 49.0, 2, 0.15], [126.6, 49.1, 2, 0.15]], "SCL\u000013\u0000c17": [[126.6, 49.1, 2, 0.15], [126.8, 49.3, 2, 0.15], [126.8, 49.3, 1, 0.15], [126.4996, 48.5798, 1, 0.15]], "SCL\u000014": [[104.0, 25.2, 1, 0.2], [95.9, 33.3, 1, 0.2], [95.9, 33.3, 2, 0.2], [77.2, 52.0, 2, 0.2], [76.4, 52.0, 2, 0.2], [74.4, 54.0, 2, 0.2], [74.4, 54.0, 1, 0.2], [74.2254, 53.7792, 1, 0.2]], "SCL\u000015\u0000c0\u0000c0": [[74.1, 53.95, 2, 0.2], [70.2, 50.05, 2, 0.2], [61.1, 50.05, 2, 0.2]], "SCL\u000015\u0000c0\u0000c1": [[61.1, 50.05, 2, 0.2], [61.1, 50.05, 2, 0.2]], "SCL\u000015\u0000c0\u0000c2": [[61.1, 50.05, 2, 0.2], [60.3, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c0": [[60.3, 50.05, 2, 0.2], [58.4, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c1": [[58.4, 50.05, 2, 0.2], [58.4, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c2": [[58.4, 50.05, 2, 0.2], [48.2, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c3": [[48.2, 50.05, 2, 0.2], [48.1, 50.05, 2, 0.2], [48.075, 50.025, 2, 0.2]], "SCL\u000015\u0000c1\u0000c4": [[48.075, 50.025, 2, 0.2], [47.9, 49.85, 2, 0.2], [47.9, 49.85, 1, 0.2], [47.0634, 49.0134, 1, 0.2], [46.9599, 48.7399, 1, 0.2], [46.9697, 48.5798, 1, 0.2]], "SCL\u000016\u0000c0\u0000c0": [[60.3, 50.1, 2, 0.2], [60.3, 73.6, 2, 0.2], [56.3, 77.6, 2, 0.2], [47.8997, 77.5387, 2, 0.2]], "SCL\u000016\u0000c0\u0000c1": [[47.8997, 77.5387, 2, 0.2], [42.6, 77.5, 2, 0.2], [40.05, 74.95, 2, 0.2]], "SCL\u000016\u0000c1\u0000c0": [[40.05, 74.95, 2, 0.2], [40.0, 74.9, 2, 0.2], [40.0, 68.0, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c1\u0000c1": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c2": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000017\u0000c0\u0000c0": [[34.95, 62.9, 1, 0.2], [34.55, 62.5, 1, 0.2], [32.15, 62.5, 1, 0.2], [32.0, 62.35, 1, 0.2], [32.0, 60.1, 1, 0.2], [30.05, 58.15, 1, 0.2]], "SCL\u000017\u0000c0\u0000c1": [[30.05, 58.15, 1, 0.2], [29.9, 58.0, 1, 0.2]], "SCL\u000017\u0000c0\u0000c2": [[29.9, 58.0, 1, 0.2], [29.9, 58.0, 1, 0.2]], "SCL\u000017\u0000c0\u0000c3": [[29.9, 58.0, 1, 0.2], [29.45, 57.55, 1, 0.2], [29.2, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c4": [[29.2, 57.55, 1, 0.2], [29.2, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c5": [[29.2, 57.55, 1, 0.2], [22.25, 57.55, 1, 0.2], [22.15, 57.45, 1, 0.2]], "SCL\u000017\u0000c0\u0000c6": [[22.15, 57.45, 1, 0.2], [22.15, 57.45, 1, 0.2]], "SCL\u000017\u0000c0\u0000c7": [[22.15, 57.45, 1, 0.2], [15.75, 51.05, 1, 0.2]], "SCL\u000017\u0000c0\u0000c8": [[15.75, 51.05, 1, 0.2], [15.75, 51.05, 1, 0.2]], "SCL\u000017\u0000c0\u0000c9": [[15.75, 51.05, 1, 0.2], [15.7, 51.0, 1, 0.2]], "SCL\u000017\u0000c0\u0000c10": [[15.7, 51.0, 1, 0.2], [15.55, 50.85, 1, 0.2]], "SCL\u000017\u0000c0\u0000c11": [[15.55, 50.85, 1, 0.2], [15.45, 50.75, 1, 0.2]], "SCL\u000017\u0000c0\u0000c12": [[15.45, 50.75, 1, 0.2], [15.45, 50.75, 1, 0.2]], "SCL\u000017\u0000c0\u0000c13": [[15.45, 50.75, 1, 0.2], [15.35, 50.65, 1, 0.2]], "SCL\u000017\u0000c0\u0000c14": [[15.35, 50.65, 1, 0.2], [15.3, 50.6, 1, 0.2], [15.3, 50.6, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15": [[15.3, 50.6, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c16": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c1": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c2": [[15.3004, 49.69, 1, 0.2], [15.3009, 48.5798, 1, 0.2]], "SCL\u000018": [[40.0, 75.0, 2, 0.2], [29.6, 75.0, 2, 0.2], [9.4, 95.2, 2, 0.2], [7.4, 95.2, 2, 0.2], [7.4, 95.2, 1, 0.2], [7.5006, 95.7788, 1, 0.2]], "SCL\u000019\u0000rr": [[7.1, 95.2, 1, 0.2], [7.5663, 94.7696, 1, 0.2], [7.75, 94.35, 1, 0.2], [7.75, 94.0, 1, 0.2], [7.4, 93.65, 1, 0.2], [6.8, 93.65, 1, 0.2], [6.05, 94.4, 1, 0.2], [5.9995, 95.7788, 1, 0.2]], "SCL\u00002": [[15.3009, 49.69, 1, 0.2], [15.3009, 48.5798, 1, 0.2]], "SCL\u00003": [[52.5881, 75.8089, 1, 0.2], [52.5881, 76.9191, 1, 0.2]], "SCL\u00004": [[140.97, 75.8089, 1, 0.2], [140.97, 76.9191, 1, 0.2]], "SCL\u00005": [[46.9697, 49.69, 1, 0.2], [46.9697, 48.5798, 1, 0.2]], "SCL\u00006": [[126.4996, 49.69, 1, 0.2], [126.4996, 48.5798, 1, 0.2]], "SCL\u00007\u0000rr": [[5.9995, 96.8891, 1, 0.2], [5.9995, 95.7788, 1, 0.2]], "SCL\u00008": [[7.5006, 96.8891, 1, 0.2], [7.5006, 95.7788, 1, 0.2]], "SCL\u00009\u0000c0": [[74.2254, 52.6537, 1, 0.2], [74.2254, 52.6537, 1, 0.2]], "SCL\u00009\u0000c1\u0000c0": [[74.2254, 52.6537, 1, 0.2], [74.2254, 52.6537, 1, 0.2]], "SCL\u00009\u0000c1\u0000c1": [[74.2254, 52.6537, 1, 0.2], [74.2254, 53.7792, 1, 0.2]], "SDA\u00000": [[125.1, 48.575, 1, 0.2], [125.9, 48.575, 1, 0.2]], "SDA\u00000\u0000c0": [[86.7712, 28.4739, 1, 0.2], [86.7712, 28.4739, 1, 0.2]], "SDA\u00000\u0000c1\u0000c0": [[86.7712, 28.4739, 1, 0.2], [86.7712, 28.4739, 1, 0.2]], "SDA\u00000\u0000c1\u0000c1": [[86.7712, 28.4739, 1, 0.2], [87.3544, 28.4739, 1, 0.2]], "SDA\u00001": [[110.2, 32.0, 1, 0.2], [112.6, 32.0, 1, 0.2], [115.8, 28.8, 1, 0.2], [119.6, 28.8, 1, 0.2], [119.6, 28.8, 2, 0.2], [119.8, 28.6, 2, 0.2], [121.2, 28.6, 2, 0.2], [123.0, 26.8, 2, 0.2], [123.0, 24.8, 2, 0.2], [124.6, 23.2, 2, 0.2], [131.2, 23.2, 2, 0.2], [131.2, 23.2, 1, 0.2], [146.8, 23.2, 1, 0.2], [150.6, 27.0, 1, 0.2], [150.6, 38.0, 1, 0.2], [158.4, 45.8, 1, 0.2], [158.4, 71.4, 1, 0.2], [154.4, 75.4, 1, 0.2], [154.4, 75.4, 2, 0.2], [152.6, 77.2, 2, 0.2], [152.6, 77.2, 1, 0.2], [151.0, 75.6, 1, 0.2], [147.0, 75.6, 1, 0.2], [147.0, 75.6, 2, 0.2], [146.8, 75.4, 2, 0.2], [140.0, 75.4, 2, 0.2], [140.0, 75.4, 1, 0.2], [140.0, 75.0, 1, 0.2], [140.8, 74.2, 1, 0.2]], "SDA\u000010": [[7.0002, 96.8891, 1, 0.2], [7.0002, 95.7788, 1, 0.2]], "SDA\u000011\u0000c0": [[73.5752, 52.6537, 1, 0.2], [73.5752, 52.6537, 1, 0.2]], "SDA\u000011\u0000c1\u0000c0": [[73.5752, 52.6537, 1, 0.2], [73.5752, 52.6537, 1, 0.2]], "SDA\u000011\u0000c1\u0000c1": [[73.5752, 52.6537, 1, 0.2], [73.5752, 52.6538, 1, 0.2]], "SDA\u000011\u0000c1\u0000c2": [[73.5752, 52.6538, 1, 0.2], [73.5752, 52.6538, 1, 0.2]], "SDA\u000011\u0000c1\u0000c3": [[73.5752, 52.6538, 1, 0.2], [73.5752, 52.6538, 1, 0.2]], "SDA\u000011\u0000c1\u0000c4": [[73.5752, 52.6538, 1, 0.2], [73.5752, 52.6538, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5": [[73.5752, 52.6538, 1, 0.2], [73.5752, 53.7792, 1, 0.2]], "SDA\u000012\u0000c0": [[110.3, 32.5, 1, 0.2], [110.3, 32.1, 1, 0.2], [110.2, 32.0, 1, 0.2]], "SDA\u000012\u0000c1": [[110.2, 32.0, 1, 0.2], [109.3, 31.1, 1, 0.2], [108.9, 31.1, 1, 0.2], [108.9, 31.1, 2, 0.2], [108.5, 30.7, 2, 0.2], [102.5, 30.7, 2, 0.2]], "SDA\u000012\u0000c2": [[102.5, 30.7, 2, 0.2], [89.6, 30.7, 2, 0.2], [87.3544, 28.4739, 2, 0.2], [87.3544, 28.4739, 1, 0.2], [87.3544, 28.4739, 1, 0.2]], "SDA\u000013": [[87.2, 28.3, 2, 0.2], [86.0959, 27.0942, 2, 0.2], [86.0959, 27.0942, 1, 0.2], [86.0959, 27.0942, 1, 0.2]], "SDA\u000015": [[80.25, 35.8, 1, 0.15], [79.8312, 35.8112, 1, 0.15]], "SDA\u000016\u0000c0\u0000c0": [[80.4, 36.5, 1, 0.2], [80.6, 36.5, 1, 0.2], [80.6, 36.5, 2, 0.2], [80.9, 36.8, 2, 0.2], [80.9, 39.2, 2, 0.2], [80.1, 40.0, 2, 0.2], [80.1, 41.4, 2, 0.2]], "SDA\u000016\u0000c0\u0000c1": [[80.1, 41.4, 2, 0.2], [80.1, 42.5, 2, 0.2], [78.8, 43.8, 2, 0.2], [78.8, 46.2, 2, 0.2], [73.9, 51.2, 2, 0.2], [73.9, 51.2, 1, 0.2], [73.6, 51.5, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c1": [[73.5874, 52.6538, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c2\u0000c0": [[73.5874, 52.6538, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c2\u0000c1": [[73.5874, 52.6538, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c2\u0000c2": [[73.5874, 52.6538, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c2\u0000c3": [[73.5874, 52.6538, 1, 0.2], [73.5874, 52.6538, 1, 0.2]], "SDA\u000016\u0000c2\u0000c4": [[73.5874, 52.6538, 1, 0.2], [73.5752, 53.7792, 1, 0.2]], "SDA\u000017\u0000c0\u0000c0": [[73.6, 51.2, 2, 0.2], [71.7, 49.3, 2, 0.2], [69.9, 49.3, 2, 0.2]], "SDA\u000017\u0000c0\u0000c1": [[69.9, 49.3, 2, 0.2], [69.9, 49.3, 2, 0.2]], "SDA\u000017\u0000c0\u0000c2": [[69.9, 49.3, 2, 0.2], [61.6, 49.3, 2, 0.2]], "SDA\u000017\u0000c0\u0000c3": [[61.6, 49.3, 2, 0.2], [61.6, 49.3, 2, 0.2]], "SDA\u000017\u0000c0\u0000c4": [[61.6, 49.3, 2, 0.2], [61.5, 49.3, 2, 0.2]], "SDA\u000017\u0000c0\u0000c5": [[61.5, 49.3, 2, 0.2], [61.0, 49.3, 2, 0.2]], "SDA\u000017\u0000c1\u0000c0": [[61.0, 49.3, 2, 0.2], [60.7, 49.3, 2, 0.2]], "SDA\u000017\u0000c1\u0000c1": [[60.7, 49.3, 2, 0.2], [51.3, 49.3, 2, 0.2], [51.3, 49.3, 1, 0.2], [49.45, 51.15, 1, 0.2]], "SDA\u000017\u0000c1\u0000c2": [[49.45, 51.15, 1, 0.2], [49.45, 51.15, 1, 0.2]], "SDA\u000017\u0000c1\u0000c3": [[49.45, 51.15, 1, 0.2], [49.35, 51.25, 1, 0.2]], "SDA\u000017\u0000c1\u0000c4": [[49.35, 51.25, 1, 0.2], [49.3, 51.3, 1, 0.2], [49.3, 52.1637, 1, 0.2], [49.05, 52.725, 1, 0.2], [49.0459, 52.7287, 1, 0.2]], "SDA\u000017\u0000c1\u0000c5": [[49.0459, 52.7287, 1, 0.2], [49.0459, 52.7287, 1, 0.2]], "SDA\u000017\u0000c1\u0000c6": [[49.0459, 52.7287, 1, 0.2], [49.0403, 52.7337, 1, 0.2]], "SDA\u000017\u0000c1\u0000c7": [[49.0403, 52.7337, 1, 0.2], [48.8, 52.95, 1, 0.2]], "SDA\u000018\u0000c0\u0000c0": [[61.0, 49.3, 2, 0.2], [61.0, 49.3, 1, 0.2], [61.0, 50.9, 1, 0.2]], "SDA\u000018\u0000c0\u0000c1": [[61.0, 50.9, 1, 0.2], [61.0, 59.6, 1, 0.2]], "SDA\u000018\u0000c0\u0000c2": [[61.0, 59.6, 1, 0.2], [61.0, 59.6, 1, 0.2]], "SDA\u000018\u0000c0\u0000c3": [[61.0, 59.6, 1, 0.2], [61.0, 60.4, 1, 0.2], [61.0, 60.4, 2, 0.2], [61.0, 73.8, 2, 0.2], [56.7, 78.1, 2, 0.2], [52.6, 78.1, 2, 0.2], [52.45, 78.25, 2, 0.2]], "SDA\u000018\u0000c0\u0000c4": [[52.45, 78.25, 2, 0.2], [51.8, 78.9, 2, 0.2], [45.6, 78.9, 2, 0.2], [45.0, 78.3, 2, 0.2], [42.3, 78.3, 2, 0.2], [40.4, 76.4, 2, 0.2], [40.4, 76.4, 1, 0.2], [36.3, 72.3, 1, 0.2]], "SDA\u000018\u0000c1\u0000c0": [[36.3, 72.3, 1, 0.2], [33.3, 69.3, 1, 0.2], [33.2689, 63.7692, 1, 0.2]], "SDA\u000018\u0000c1\u0000c1": [[33.2689, 63.7692, 1, 0.2], [33.2689, 63.7692, 1, 0.2]], "SDA\u000018\u0000c2": [[33.2689, 63.7692, 1, 0.2], [33.2689, 63.7692, 1, 0.2]], "SDA\u000019\u0000c0\u0000c0": [[36.25, 72.35, 1, 0.2], [32.95, 75.65, 1, 0.2], [32.95, 75.65, 2, 0.2], [12.95, 95.65, 2, 0.2], [9.7, 95.65, 2, 0.2]], "SDA\u000019\u0000c0\u0000c1": [[9.7, 95.65, 2, 0.2], [9.7, 95.65, 2, 0.2]], "SDA\u000019\u0000c0\u0000c2": [[9.7, 95.65, 2, 0.2], [9.4, 95.65, 2, 0.2], [9.375, 95.675, 2, 0.2]], "SDA\u000019\u0000c0\u0000c3": [[9.375, 95.675, 2, 0.2], [6.8, 98.25, 2, 0.2], [6.8, 98.25, 1, 0.2], [7.0, 98.05, 1, 0.2], [7.0001, 96.8891, 1, 0.2]], "SDA\u000019\u0000c0\u0000c4": [[7.0001, 96.8891, 1, 0.2], [7.0001, 96.8891, 1, 0.2]], "SDA\u000019\u0000c1": [[7.0001, 96.8891, 1, 0.2], [7.0001, 96.8891, 1, 0.2]], "SDA\u000019\u0000c2": [[7.0001, 96.8891, 1, 0.2], [7.0002, 95.7788, 1, 0.2]], "SDA\u00002": [[79.8312, 36.5112, 1, 0.2], [79.8312, 35.8112, 1, 0.2]], "SDA\u00003\u0000c0": [[110.3196, 33.21, 1, 0.2], [110.3196, 33.21, 1, 0.2]], "SDA\u00003\u0000c1\u0000c0": [[110.3196, 33.21, 1, 0.2], [110.3196, 33.21, 1, 0.2]], "SDA\u00003\u0000c1\u0000c1": [[110.3196, 33.21, 1, 0.2], [110.3196, 32.5099, 1, 0.2]], "SDA\u00004": [[14.8005, 49.69, 1, 0.2], [14.8005, 48.5798, 1, 0.2]], "SDA\u00005": [[53.0885, 75.8089, 1, 0.2], [53.0885, 76.9191, 1, 0.2]], "SDA\u00006\u0000c0\u0000c0": [[141.4679, 75.8089, 1, 0.2], [141.4679, 75.8089, 1, 0.2]], "SDA\u00006\u0000c0\u0000c1": [[141.4679, 75.8089, 1, 0.2], [141.4718, 76.425, 1, 0.2], [141.475, 76.425, 1, 0.15], [141.475, 75.8089, 1, 0.15]], "SDA\u00006\u0000c1\u0000c0": [[141.475, 75.8089, 1, 0.15], [141.475, 75.8089, 1, 0.15]], "SDA\u00006\u0000c1\u0000c1": [[141.475, 75.8089, 1, 0.15], [141.475, 74.925, 1, 0.15], [140.7786, 74.2212, 1, 0.15]], "SDA\u00006\u0000c1\u0000c2": [[140.7786, 74.2212, 1, 0.15], [139.125, 72.55, 1, 0.15]], "SDA\u00007\u0000c0\u0000c0": [[46.4693, 49.69, 1, 0.2], [46.4693, 49.69, 1, 0.2]], "SDA\u00007\u0000c0\u0000c1": [[46.4693, 49.69, 1, 0.2], [46.4724, 49.075, 1, 0.2], [46.475, 49.075, 1, 0.2], [46.475, 49.69, 1, 0.2]], "SDA\u00007\u0000c1\u0000c0": [[46.475, 49.69, 1, 0.2], [46.475, 49.69, 1, 0.2]], "SDA\u00007\u0000c1\u0000c1": [[46.475, 49.69, 1, 0.2], [46.475, 50.625, 1, 0.2], [48.8, 52.95, 1, 0.2]], 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1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c1": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c10": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c11": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c12": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c13": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c14": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c15": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c16": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6065, 1, 0.2]], "IOEXP_INT#\u00001\u0000c4\u0000c0\u0000c2": [[72.9249, 46.6079, 1, 0.2], [72.9249, 46.6079, 1, 0.2]], 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1, 0.2]], "IOEXP_INT#\u00002\u0000c3\u0000c1\u0000c9\u0000c3\u0000c0": [[72.9064, 46.6065, 1, 0.2], [72.9064, 46.6065, 1, 0.2]], "IOEXP_INT#\u00002\u0000c3\u0000c1\u0000c9\u0000c3\u0000c1": [[72.9064, 46.6065, 1, 0.2], [72.9064, 46.6062, 1, 0.2]], "K1_PWR\u00000": [[35.8673, 31.5011, 1, 0.2], [35.2841, 31.5011, 1, 0.2]], "K1_PWR\u00001\u0000c0": [[87.8053, 49.6342, 1, 0.2], [87.8053, 49.6342, 1, 0.2]], "K1_PWR\u00001\u0000c1": [[87.8053, 49.6342, 1, 0.2], [87.8053, 48.3486, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c0\u0000c0\u0000c0": [[35.2841, 31.5011, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c0\u0000c0\u0000c1": [[35.5802, 31.7927, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c0\u0000c1": [[35.5802, 31.7927, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c0\u0000c1": [[35.5802, 31.7927, 1, 0.2], [35.5802, 31.7927, 1, 0.2]], "K1_PWR\u00002\u0000c1": [[35.5802, 31.7927, 1, 0.2], [36.4, 32.6, 1, 0.2], [45.0, 32.6, 1, 0.2], [45.8201, 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35.2753, 1, 0.2], [92.2042, 33.9898, 1, 0.2]], "K5_PWR\u00002\u0000rr": [[146.4853, 31.5011, 1, 0.2], [144.0, 31.5, 1, 0.2], [143.3, 30.8, 1, 0.2], [141.1, 30.8, 1, 0.2], [140.4, 31.5, 1, 0.2], [140.4, 31.5, 2, 0.2], [138.3, 33.6, 2, 0.2], [119.7, 33.6, 2, 0.2], [119.7, 33.6, 1, 0.2], [115.0, 38.3, 1, 0.2], [110.0, 38.3, 1, 0.2], [110.0, 38.3, 2, 0.2], [109.5, 38.8, 2, 0.2], [97.9, 38.8, 2, 0.2], [97.5, 38.4, 2, 0.2], [97.5, 38.4, 1, 0.2], [96.0, 36.9, 1, 0.2], [93.1, 36.9, 1, 0.2], [92.8, 36.6, 1, 0.2], [92.8, 34.6, 1, 0.2], [92.2042, 33.9898, 1, 0.2]], "K5_VDN\u00000\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1": [[147.0686, 38.0009, 1, 0.2], [146.4853, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c1\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[147.0686, 38.0009, 1, 0.2], [147.0686, 38.0009, 1, 0.2]], "K5_VDN\u00000\u0000c1\u0000c1\u0000c1\u0000c1": [[147.0686, 38.0009, 1, 0.2], [146.4853, 38.0009, 1, 0.2]], "K5_VDN\u00001": [[93.4745, 35.2755, 1, 0.2], [93.4745, 33.99, 1, 0.2]], "K5_VDN\u00001\u0000c0": [[94.7442, 35.2753, 1, 0.2], [94.7442, 35.2753, 1, 0.2]], "K5_VDN\u00001\u0000c1\u0000c0": [[94.7442, 35.2753, 1, 0.2], [94.7442, 35.2753, 1, 0.2]], "K5_VDN\u00001\u0000c1\u0000c1": [[94.7442, 35.2753, 1, 0.2], [94.7442, 33.9898, 1, 0.2]], "K5_VDN\u00002": [[146.4853, 38.0009, 1, 0.2], [146.5, 35.7, 1, 0.2], [145.15, 34.35, 1, 0.2], [141.9, 34.35, 1, 0.2], [139.85, 32.3, 1, 0.2], [139.85, 32.3, 2, 0.2], [138.65, 33.5, 2, 0.2], [125.3, 33.65, 2, 0.2], [125.3, 33.65, 1, 0.2], [125.3, 34.65, 1, 0.2], [118.5, 41.45, 1, 0.2], [118.5, 41.45, 2, 0.2], [118.5, 40.65, 2, 0.2], [118.1, 40.25, 2, 0.2], [109.0, 40.25, 2, 0.2], [109.0, 40.25, 1, 0.2], [108.5, 39.75, 1, 0.2], [100.35, 39.75, 1, 0.2], [100.35, 39.75, 2, 0.2], [98.15, 37.55, 2, 0.2], [98.15, 36.2, 2, 0.2], [98.15, 36.2, 1, 0.2], [97.75, 36.6, 1, 0.2], [94.25, 36.6, 1, 0.2], [94.1, 36.45, 1, 0.2], [94.1, 34.65, 1, 0.2], [93.4745, 33.99, 1, 0.2]], "K5_VUP\u00000\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1": [[147.0686, 35.0012, 1, 0.2], [146.4853, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c1\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[147.0686, 35.0012, 1, 0.2], [147.0686, 35.0012, 1, 0.2]], "K5_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c1": [[147.0686, 35.0012, 1, 0.2], [146.4853, 35.0012, 1, 0.2]], "K5_VUP\u00001": [[94.7445, 35.2755, 1, 0.2], [94.7445, 33.99, 1, 0.2]], "K5_VUP\u00001\u0000c0": [[93.4742, 35.2753, 1, 0.2], [93.4742, 35.2753, 1, 0.2]], "K5_VUP\u00001\u0000c1\u0000c0": [[93.4742, 35.2753, 1, 0.2], [93.4742, 35.2753, 1, 0.2]], "K5_VUP\u00001\u0000c1\u0000c1": [[93.4742, 35.2753, 1, 0.2], [93.4742, 33.9898, 1, 0.2]], "K5_VUP\u00002": [[146.4853, 35.0012, 1, 0.2], [145.4, 33.9, 1, 0.2], [142.45, 33.9, 1, 0.2], [140.2, 31.65, 1, 0.2], [139.2, 31.65, 1, 0.2], [139.2, 31.65, 2, 0.2], [138.75, 32.1, 2, 0.2], [122.65, 32.1, 2, 0.2], [119.35, 35.4, 2, 0.2], [119.35, 39.4, 2, 0.2], [120.45, 40.5, 2, 0.2], [120.45, 40.5, 1, 0.2], [116.6, 44.35, 1, 0.2], [111.3, 44.35, 1, 0.2], [111.1, 44.55, 1, 0.2], [111.1, 44.55, 2, 0.2], [107.9, 41.35, 2, 0.2], [107.9, 41.35, 1, 0.2], [106.95, 40.4, 1, 0.2], [106.95, 40.4, 2, 0.2], [105.35, 38.8, 2, 0.2], [105.35, 31.35, 2, 0.2], [105.35, 31.35, 1, 0.2], [102.0, 28.15, 1, 0.2], [102.0, 28.15, 2, 0.2], [101.05, 27.2, 2, 0.2], [101.05, 27.2, 1, 0.2], [99.05, 29.2, 1, 0.2], [98.55, 29.2, 1, 0.2], [98.55, 29.2, 2, 0.2], [97.7, 30.05, 2, 0.2], [96.95, 30.05, 2, 0.2], [96.95, 30.05, 1, 0.2], [95.25, 31.75, 1, 0.2], [95.25, 33.5, 1, 0.2], [94.7445, 33.99, 1, 0.2]], "KEY_OE#\u00000\u0000c0\u0000c0": [[92.3262, 56.6803, 1, 0.2], [92.4527, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c0\u0000c1": [[92.4527, 56.6803, 1, 0.2], [92.4527, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c0\u0000c2": [[92.4527, 56.6803, 1, 0.2], [92.454, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c1": [[92.454, 56.6803, 1, 0.2], [92.454, 56.6803, 1, 0.2]], "KEY_OE#\u00000\u0000c2": [[92.454, 56.6803, 1, 0.2], [92.9094, 56.6803, 1, 0.2]], "KEY_OE#\u00001": [[91.6142, 55.1051, 1, 0.2], [91.0132, 55.1051, 1, 0.2]], "KEY_OE#\u00002\u0000c0": [[92.2042, 40.7464, 1, 0.2], [92.2042, 40.7464, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c0": [[92.2042, 40.7464, 1, 0.2], [92.2042, 40.7464, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c1\u0000c0\u0000c0": [[92.2042, 40.7464, 1, 0.2], [92.2042, 40.7467, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c1\u0000c0\u0000c1": [[92.2042, 40.7467, 1, 0.2], [92.2042, 40.7467, 1, 0.2]], "KEY_OE#\u00002\u0000c1\u0000c1\u0000c1": [[92.2042, 40.7467, 1, 0.2], [92.2042, 42.032, 1, 0.2]], "KEY_OE#\u00003": [[91.3664, 73.7362, 1, 0.2], [91.3664, 75.0217, 1, 0.2]], "KEY_OE#\u00004\u0000c0\u0000c0": [[92.9094, 56.6803, 1, 0.2], [92.7547, 56.6902, 1, 0.2], [92.4907, 56.5901, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c0\u0000c1": [[92.454, 56.5532, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c0": [[92.454, 56.5532, 1, 0.2], [92.454, 56.5532, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c1\u0000c0": [[92.454, 56.5532, 1, 0.2], [92.4527, 56.5519, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c1\u0000c1\u0000c0": [[92.4527, 56.5519, 1, 0.2], [91.3128, 55.4062, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c1\u0000c1\u0000c1": [[91.3128, 55.4062, 1, 0.2], [91.3128, 55.4062, 1, 0.2]], "KEY_OE#\u00004\u0000c1\u0000c1\u0000c2": [[91.3128, 55.4062, 1, 0.2], [91.3122, 55.4056, 1, 0.2]], "KEY_OE#\u00004\u0000c2": [[91.3122, 55.4056, 1, 0.2], [91.0132, 55.1051, 1, 0.2]], "KEY_OE#\u00005": [[91.9, 54.2, 1, 0.2], [91.9, 52.2, 1, 0.2], [91.9, 52.2, 2, 0.2], [92.2, 51.9, 2, 0.2], [92.2042, 42.032, 2, 0.2], [92.2042, 42.032, 1, 0.2], [92.2042, 42.032, 1, 0.2]], "KEY_OE#\u00006": [[92.0, 39.8, 1, 0.2], [90.3, 38.1, 1, 0.2], [90.0, 38.1, 1, 0.2], [90.0, 38.1, 2, 0.2], [85.2, 33.3, 2, 0.2], [85.2, 30.0, 2, 0.2], [85.2, 30.0, 1, 0.2], [84.8, 29.6, 1, 0.2], [84.8259, 27.0942, 1, 0.2]], "KEY_RCLK\u00000\u0000c0": [[92.8853, 55.1053, 1, 0.2], [92.8853, 55.1053, 1, 0.2]], "KEY_RCLK\u00000\u0000c1": [[92.8853, 55.1053, 1, 0.2], [92.8853, 56.2106, 1, 0.2]], "KEY_RCLK\u00000\u0000c2": [[92.8853, 56.2106, 1, 0.2], [92.8853, 56.2108, 1, 0.2]], "KEY_RCLK\u00001\u0000c0": [[93.4742, 40.7464, 1, 0.2], [93.4742, 40.7464, 1, 0.2]], "KEY_RCLK\u00001\u0000c1": [[93.4745, 42.032, 1, 0.2], [93.4745, 42.032, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c0": [[93.4742, 40.7464, 1, 0.2], [93.4742, 40.7464, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c1\u0000c0\u0000c0": [[93.4742, 40.7464, 1, 0.2], [93.4742, 40.7467, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c1\u0000c0\u0000c1": [[93.4742, 40.7467, 1, 0.2], [93.4742, 40.7467, 1, 0.2]], "KEY_RCLK\u00001\u0000c1\u0000c1\u0000c1": [[93.4742, 40.7467, 1, 0.2], [93.4742, 42.032, 1, 0.2]], "KEY_RCLK\u00001\u0000c2": [[93.4745, 42.032, 1, 0.2], [93.4745, 42.0322, 1, 0.2]], "KEY_RCLK\u00002": [[92.6364, 73.7362, 1, 0.2], [92.6364, 75.0217, 1, 0.2]], "KEY_RCLK\u00003\u0000c0": [[92.8853, 56.2108, 1, 0.15], [92.8853, 56.2106, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c0": [[92.8842, 56.2106, 1, 0.15], [92.8842, 56.2106, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c1": [[92.8842, 56.2106, 1, 0.15], [92.8842, 56.2106, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c2": [[92.8842, 56.2106, 1, 0.15], [92.8842, 56.2106, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c3": [[92.8842, 56.2106, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c4": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c5": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c0\u0000c6": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c1": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c0\u0000c2": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c0\u0000c1": [[92.8886, 55.1053, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c0\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c10": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c11": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c12": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c13": [[92.8894, 55.1051, 1, 0.15], [92.9, 52.2, 1, 0.15], [92.9, 52.2, 2, 0.15], [93.5, 51.6, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c14": [[93.4813, 44.6001, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c15": [[93.4813, 44.6001, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c16": [[93.4813, 44.6001, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c17": [[93.4813, 44.6001, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c18": [[93.4813, 44.6001, 2, 0.15], [93.4813, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c19": [[93.4813, 44.6001, 2, 0.15], [93.4745, 42.0322, 2, 0.15], [93.4745, 42.0322, 1, 0.15], [93.4745, 42.0322, 1, 0.15]], "KEY_RCLK\u00003\u0000c2": [[92.8894, 55.1053, 1, 0.15], [92.8894, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c0": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c0": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c1": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c2": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c3": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c4": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c5": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c6": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c7": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c8": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c9": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c10": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c11": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c12": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c13": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c14": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c15": [[92.8886, 55.1051, 1, 0.15], [92.8886, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c2\u0000c1\u0000c16": [[92.8886, 55.1051, 1, 0.15], [92.9, 52.2, 1, 0.15], [92.9, 52.2, 2, 0.15], [93.5, 51.6, 2, 0.15], [93.4811, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c3": [[92.8894, 55.1053, 1, 0.15], [92.8894, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c3\u0000c0": [[93.4811, 44.6001, 2, 0.15], [93.4811, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c3\u0000c1\u0000c0": [[93.4811, 44.6001, 2, 0.15], [93.4811, 44.6001, 2, 0.15]], "KEY_RCLK\u00003\u0000c3\u0000c1\u0000c1": [[93.4811, 44.6001, 2, 0.15], [93.4742, 42.032, 2, 0.15], [93.4742, 42.032, 1, 0.15], [93.4742, 42.032, 1, 0.15]], "KEY_RCLK\u00003\u0000c4": [[92.8894, 55.1053, 1, 0.15], [92.8894, 55.1053, 1, 0.15]], "KEY_RCLK\u00003\u0000c5": [[92.8894, 55.1053, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c6": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c7": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c8": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00003\u0000c9": [[92.8894, 55.1051, 1, 0.15], [92.8894, 55.1051, 1, 0.15]], "KEY_RCLK\u00004\u0000c0\u0000c0": [[93.6, 41.8, 2, 0.2], [93.6, 40.1, 2, 0.2], [96.4, 37.3, 2, 0.2], [96.4, 37.3, 1, 0.2], [98.0, 37.3, 1, 0.2], [101.0, 34.3, 1, 0.2], [101.0, 29.3, 1, 0.2], [101.0, 29.3, 2, 0.2], [98.1, 26.4, 2, 0.2], [92.6, 26.4, 2, 0.2], [92.6, 26.4, 1, 0.2], [92.5, 26.5, 1, 0.2], [92.4131, 26.7408, 1, 0.2], [92.4459, 27.0942, 1, 0.2]], "KEY_RCLK\u00004\u0000c0\u0000c1": [[92.4459, 27.0942, 1, 0.2], [92.4459, 27.0942, 1, 0.2]], "KEY_RCLK\u00004\u0000c1": [[92.4459, 27.0942, 1, 0.2], [92.4459, 27.0942, 1, 0.2]], "KEY_RCLK\u00005": [[93.1, 56.0, 1, 0.2], [93.2, 56.0, 1, 0.2], [93.2, 56.0, 2, 0.2], [93.2, 58.1, 2, 0.2], [92.5, 58.8, 2, 0.2], [91.8, 58.8, 2, 0.2], [91.8, 58.8, 1, 0.2], [91.0, 59.6, 1, 0.2], [91.0, 60.9, 1, 0.2], [91.0, 60.9, 2, 0.2], [84.8, 67.1, 2, 0.2], [84.8, 72.4, 2, 0.2], [85.4, 73.0, 2, 0.2], [85.4, 73.0, 1, 0.2], [86.1, 72.3, 1, 0.2], [91.8, 72.395, 1, 0.2], [92.1, 72.7, 1, 0.2], [92.1, 74.5, 1, 0.2], [92.6364, 75.0217, 1, 0.2]], "KEY_SER\u00000": [[87.3659, 27.0942, 1, 0.2], [87.85, 27.6, 1, 0.2], [87.8944, 28.0444, 1, 0.2], [87.95, 28.125, 1, 0.2], [87.95, 28.125, 1, 0.2], [88.0, 28.2059, 1, 0.2], [88.0, 32.15, 1, 0.2], [88.0, 32.15, 2, 0.2], [88.35, 32.5, 2, 0.2], [88.35, 39.3, 2, 0.2], [88.55, 39.5, 2, 0.2], [88.55, 39.5, 1, 0.2], [91.65, 42.6, 1, 0.2], [91.65, 42.85, 1, 0.2], [91.65, 42.85, 2, 0.2], [91.65, 46.55, 2, 0.2], [97.4, 52.3, 2, 0.2], [97.4, 52.3, 1, 0.2], [97.9, 52.8, 1, 0.2], [101.95, 52.8, 1, 0.2], [103.15, 54.0, 1, 0.2], [103.15, 54.0, 2, 0.2], [105.7, 56.55, 2, 0.2], [108.6, 56.55, 2, 0.2], [108.6, 56.55, 1, 0.2], [109.9, 57.85, 1, 0.2], [109.9, 57.85, 2, 0.2], [107.9893, 59.6738, 2, 0.2], [107.7, 60.35, 2, 0.2], [107.7, 62.5, 2, 0.2], [108.9508, 63.7692, 2, 0.2]], "KEY_SER\u00000\u0000c0": [[90.3442, 55.1051, 1, 0.2], [90.3442, 55.1053, 1, 0.2]], "KEY_SER\u00000\u0000c1": [[90.3453, 55.1053, 1, 0.2], [90.3453, 56.3906, 1, 0.2]], "KEY_SER\u00000\u0000c1\u0000c0": [[90.3442, 55.1053, 1, 0.2], [90.3442, 55.1053, 1, 0.2]], "KEY_SER\u00000\u0000c1\u0000c1": [[90.3442, 55.1053, 1, 0.2], [90.3442, 56.3906, 1, 0.2]], "KEY_SER\u00000\u0000c2": [[90.3453, 56.3906, 1, 0.2], [90.3453, 56.3908, 1, 0.2]], "KEY_SRCLK\u00000": [[88.6359, 27.0942, 1, 0.2], [88.65, 30.9, 1, 0.2], [94.55, 36.8, 1, 0.2], [94.55, 36.8, 2, 0.2], [94.55, 48.45, 2, 0.2], [98.25, 52.15, 2, 0.2], [98.25, 52.15, 1, 0.2], [102.25, 52.15, 1, 0.2], [109.35, 59.25, 1, 0.2], [109.35, 59.25, 2, 0.2], [110.2, 60.1, 2, 0.2], [110.2, 62.45, 2, 0.2], [111.4908, 63.7692, 2, 0.2]], "KEY_SRCLK\u00000\u0000c0": [[94.1542, 55.1051, 1, 0.2], [94.1542, 55.1052, 1, 0.2]], "KEY_SRCLK\u00000\u0000c1": [[94.1542, 55.1052, 1, 0.2], [94.1542, 55.1052, 1, 0.2]], "KEY_SRCLK\u00000\u0000c10": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c11": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c12": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c13": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c14": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c15": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c16": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c17": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c18": [[94.1553, 55.1055, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c19": [[94.1553, 55.1055, 1, 0.2], [94.1553, 56.3906, 1, 0.2]], "KEY_SRCLK\u00000\u0000c2": [[94.1542, 55.1052, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c20": [[94.1553, 56.3906, 1, 0.2], [94.1553, 56.3906, 1, 0.2]], "KEY_SRCLK\u00000\u0000c21": [[94.1553, 56.3906, 1, 0.2], [94.1553, 56.3908, 1, 0.2]], "KEY_SRCLK\u00000\u0000c3": [[94.1542, 55.1053, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c0": [[94.1542, 55.1053, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c0": [[94.1542, 55.1053, 1, 0.2], [94.1542, 55.1053, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c1": [[94.1542, 55.1053, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c10": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c11": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c12": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c13": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c14": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c15": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c16": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c17": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c18": [[94.1542, 55.1055, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c19": [[94.1542, 55.1055, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c2": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c3": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c4": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c5": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c6": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c7": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c8": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c4\u0000c1\u0000c9": [[94.1542, 55.1054, 1, 0.2], [94.1542, 55.1055, 1, 0.2]], "KEY_SRCLK\u00000\u0000c5": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c6": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c7": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c8": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1054, 1, 0.2]], "KEY_SRCLK\u00000\u0000c9": [[94.1553, 55.1054, 1, 0.2], [94.1553, 55.1055, 1, 0.2]], "KEY_SRCLK\u00001\u0000c0": [[94.7442, 40.7464, 1, 0.2], [94.7442, 40.7464, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1": [[94.7445, 42.032, 1, 0.2], [94.7445, 42.032, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c0": [[94.7442, 40.7464, 1, 0.2], [94.7442, 40.7464, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c1\u0000c0\u0000c0": [[94.7442, 40.7464, 1, 0.2], [94.7442, 40.7467, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c1\u0000c0\u0000c1": [[94.7442, 40.7467, 1, 0.2], [94.7442, 40.7467, 1, 0.2]], "KEY_SRCLK\u00001\u0000c1\u0000c1\u0000c1": [[94.7442, 40.7467, 1, 0.2], [94.7442, 42.032, 1, 0.2]], "KEY_SRCLK\u00001\u0000c2": [[94.7445, 42.032, 1, 0.2], [94.7445, 42.0322, 1, 0.2]], "KEY_SRCLK\u00002": [[93.9064, 73.7362, 1, 0.2], [93.9064, 75.0217, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0": [[94.1553, 56.3908, 1, 0.2], [94.1553, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c0": [[94.1542, 56.3906, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c1": [[94.1542, 56.3906, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c2": [[94.1542, 56.3906, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c3": [[94.1542, 56.3906, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c4": [[94.1542, 56.3906, 1, 0.2], [94.1542, 56.3906, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c5": [[94.1542, 56.3906, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c6": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c7": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c8": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c9": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c10": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c11": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c12": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c13": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c14": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c15": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c16": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c17": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c18": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c19": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c20": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c21": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c22": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c23": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c24": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1057, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c25": [[94.1682, 55.1057, 1, 0.2], [94.1682, 55.1056, 1, 0.2]], "KEY_SRCLK\u00003\u0000c0\u0000c0\u0000c26": [[94.1682, 55.1056, 1, 0.2], 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0.2], [74.3, 15.9, 1, 0.2], [74.3, 21.7, 1, 0.2], [74.3, 21.7, 2, 0.2], [70.8, 25.2476, 2, 0.2], [70.8, 25.2476, 1, 0.2], [70.8, 25.2476, 1, 0.2]], "POGO1_PWR\u00000": [[24.45, 62.5, 1, 0.2], [26.7, 62.5, 1, 0.2], [26.9, 62.3, 1, 0.2], [26.9, 60.2, 1, 0.2], [27.15, 59.95, 1, 0.2], [29.2, 59.95, 1, 0.2], [30.45, 58.7, 1, 0.2], [30.45, 28.35, 1, 0.2], [31.3004, 27.5006, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c0\u0000c0\u0000c0": [[31.3004, 31.5011, 1, 0.2], [31.5, 31.3, 1, 0.2], [31.5, 30.0, 1, 0.2], [31.5, 30.0, 2, 0.2], [27.6, 26.1, 2, 0.2], [26.6, 26.1, 2, 0.2], [26.6, 26.1, 1, 0.2], [23.2, 22.7, 1, 0.2], [19.1, 22.7, 1, 0.2], [19.1, 22.7, 2, 0.2], [18.9, 22.9, 2, 0.2], [13.1, 22.9, 2, 0.2], [12.4, 23.6, 2, 0.2], [12.4, 29.7, 2, 0.2], [10.7, 31.4, 2, 0.2], [10.7, 31.4, 1, 0.2], [2.2, 39.9, 1, 0.2], [2.2, 67.7, 1, 0.2], [4.9, 70.4, 1, 0.2], [8.9, 70.4, 1, 0.2], [9.7439, 70.037, 1, 0.2], [11.2, 68.5, 1, 0.2], [11.2, 68.5, 2, 0.2], [11.9, 67.8, 2, 0.2], [21.6, 67.8, 2, 0.2], [21.6, 67.8, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c0\u0000c0\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c0\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c0\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VDN\u00000\u0000c1": [[25.6489, 63.7692, 1, 0.2], [25.6489, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c0\u0000c0\u0000c0": [[35.3009, 27.5006, 1, 0.2], [34.9, 27.5, 1, 0.2], [34.9, 27.5, 2, 0.2], [32.8, 25.4, 2, 0.2], [24.7, 25.4, 2, 0.2], [24.7, 25.4, 1, 0.2], [22.7, 23.4, 1, 0.2], [19.8, 23.4, 1, 0.2], [19.8, 23.4, 2, 0.2], [13.5, 23.4, 2, 0.2], [12.9, 24.0, 2, 0.2], [12.9, 30.4, 2, 0.2], [11.0, 32.3, 2, 0.2], [11.0, 32.3, 1, 0.2], [4.9, 38.4, 1, 0.2], [4.9, 66.8, 1, 0.2], [8.0, 69.9, 1, 0.2], [9.0, 69.9, 1, 0.2], [9.2, 69.7, 1, 0.2], [9.3, 67.8, 1, 0.2], [9.3, 67.8, 2, 0.2], [10.7, 66.4, 2, 0.2], [20.5, 66.4, 2, 0.2], [20.7, 66.2, 2, 0.2], [20.7, 66.2, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c0\u0000c0\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c0\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c0\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO1_VUP\u00000\u0000c1": [[23.1089, 63.7692, 1, 0.2], [23.1089, 63.7692, 1, 0.2]], "POGO2_PWR\u00000": [[36.5887, 98.0009, 1, 0.2], [40.7, 102.1, 1, 0.2], [48.7, 102.1, 1, 0.2], [51.1, 104.5, 1, 0.2], [51.1, 106.9, 1, 0.2], [51.9, 107.7, 1, 0.2], [90.0, 107.7, 1, 0.2], [102.3, 95.4, 1, 0.2], [102.3, 95.4, 2, 0.2], [114.5, 83.2, 2, 0.2], [114.5, 83.2, 1, 0.2], [115.7, 82.0, 1, 0.2], [115.7, 80.8, 1, 0.2], [115.7, 80.8, 2, 0.2], [115.7, 70.9, 2, 0.2], [115.7, 70.9, 1, 0.2], [113.6, 68.8, 1, 0.2], [113.6, 68.4, 1, 0.2], [111.6, 66.4, 1, 0.2], [111.6, 66.4, 2, 0.2], [108.9508, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[36.5887, 94.0004, 1, 0.2], [36.5887, 94.0004, 1, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1\u0000c1\u0000c1": [[36.5887, 94.0004, 1, 0.2], [44.6, 94.0, 1, 0.2], [44.6, 94.0, 2, 0.2], [45.3, 93.3, 2, 0.2], [59.6, 93.3, 2, 0.2], [59.6, 93.3, 1, 0.2], [60.8, 92.1, 1, 0.2], [101.9, 92.1, 1, 0.2], [102.3, 91.7, 1, 0.2], [102.3, 91.7, 2, 0.2], [103.7, 90.3, 2, 0.2], [103.7, 90.3, 1, 0.2], [106.2, 90.3, 1, 0.2], [115.0, 81.5, 1, 0.2], [115.0, 81.5, 2, 0.2], [115.0, 69.0, 2, 0.2], [115.0, 69.0, 1, 0.2], [115.0, 66.4, 1, 0.2], [115.0, 66.4, 2, 0.2], [115.0, 64.8, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1\u0000c1\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c1\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c1\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VDN\u00000\u0000c2": [[114.0308, 63.7692, 2, 0.2], [114.0308, 63.7692, 2, 0.2]], "POGO2_VUP\u00000\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c1\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[32.5882, 98.0009, 1, 0.2], [32.5882, 98.0009, 1, 0.2]], "POGO2_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c1": [[32.5882, 98.0009, 1, 0.2], [32.8, 98.0, 1, 0.2], [32.8, 98.0, 2, 0.2], [36.0, 94.8, 2, 0.2], [59.2, 94.8, 2, 0.2], [59.2, 94.8, 1, 0.2], [61.2, 92.8, 1, 0.2], [102.3, 92.8, 1, 0.2], [102.3, 92.8, 2, 0.2], [113.2, 81.9, 2, 0.2], [113.2, 81.9, 1, 0.2], [114.3, 80.8, 1, 0.2], [114.3, 80.8, 2, 0.2], [114.3, 68.3, 2, 0.2], [114.3, 68.3, 1, 0.2], [114.1, 68.1, 1, 0.2], [114.1, 66.4, 1, 0.2], [114.1, 66.4, 2, 0.2], [111.4908, 63.7692, 2, 0.2]], "POGO3_VDN\u00000": [[136.9, 63.775, 1, 0.2], [138.125, 62.55, 1, 0.2], [140.7, 62.525, 1, 0.2]], "POGO3_VUP\u00000\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c1\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[120.97, 98.0009, 1, 0.2], [120.97, 98.0009, 1, 0.2]], "POGO3_VUP\u00000\u0000c1\u0000c1\u0000c1\u0000c1": [[120.97, 98.0009, 1, 0.2], [120.95, 94.8, 1, 0.2], [120.95, 94.8, 2, 0.2], [119.2, 93.05, 2, 0.2], [119.2, 89.65, 2, 0.2], [119.2, 89.65, 1, 0.2], [118.05, 88.5, 1, 0.2], [118.05, 81.5, 1, 0.2], [117.85, 81.3, 1, 0.2], [117.85, 81.3, 2, 0.2], [117.85, 69.9, 2, 0.2], [117.85, 69.9, 1, 0.2], [119.15, 68.6, 1, 0.2], [119.2, 66.95, 1, 0.2], [119.2, 66.95, 2, 0.2], [120.35, 65.8, 2, 0.2], [120.35, 59.85, 2, 0.2], [120.35, 59.85, 1, 0.2], [122.6, 59.85, 1, 0.2], [122.9, 60.15, 1, 0.2], [122.9, 62.25, 1, 0.2], [123.15, 62.5, 1, 0.2], [133.1, 62.5, 1, 0.2], [134.3508, 63.7692, 1, 0.2]], "POGO4_PWR\u00000\u0000c0": [[62.9692, 27.5006, 1, 0.15], [62.9692, 27.5006, 1, 0.15]], "POGO4_PWR\u00000\u0000c1": [[62.9692, 27.5006, 1, 0.15], [62.4, 28.0, 1, 0.15], [62.4, 28.0, 2, 0.15], [62.4, 28.9, 2, 0.15], [63.1, 29.6, 2, 0.15], [67.2, 29.6, 2, 0.15], [67.2, 29.6, 1, 0.15], [67.55, 29.25, 1, 0.15], [67.8785, 28.4055, 1, 0.15], [67.8, 26.6, 1, 0.15], [67.8, 26.6, 2, 0.15], [70.0, 24.4, 2, 0.15], [70.0, 23.2, 2, 0.15], [70.0, 23.2, 1, 0.15], [69.8, 23.0, 1, 0.15], [67.0, 23.0, 1, 0.15], [67.0, 23.0, 2, 0.15], [65.6, 21.6, 2, 0.15], [65.6, 21.6, 1, 0.15], [60.4, 16.4, 1, 0.15], [11.4, 16.4, 1, 0.15], [9.0, 18.8, 1, 0.15], [8.9, 31.1, 1, 0.15], [7.4, 32.6, 1, 0.15], [7.4, 33.6, 1, 0.15], [7.4, 33.6, 2, 0.15], [7.4, 49.8, 2, 0.15], [7.4, 49.8, 1, 0.15], [7.4, 56.8, 1, 0.15], [10.5, 59.9, 1, 0.15], [18.8, 59.9, 1, 0.15], [19.6453, 60.2617, 1, 0.15], [20.5689, 61.2292, 1, 0.15]], "POGO4_VUP\u00000\u0000c0": [[66.9697, 27.5006, 1, 0.2], [66.9697, 27.5006, 1, 0.2]], "POGO4_VUP\u00000\u0000c1": [[66.9697, 27.5006, 1, 0.2], [65.8, 27.5, 1, 0.2], [65.8, 27.5, 2, 0.2], [64.3, 29.0, 2, 0.2], [63.3, 29.0, 2, 0.2], [63.1, 28.8, 2, 0.2], [63.1, 28.3, 2, 0.2], [63.4737, 27.4678, 2, 0.2], [64.5263, 26.5322, 2, 0.2], [64.9, 25.7, 2, 0.2], [64.9, 21.1, 2, 0.2], [61.6, 17.8, 2, 0.2], [51.2, 17.8, 2, 0.2], [51.2, 17.8, 1, 0.2], [50.3, 16.9, 1, 0.2], [34.6, 16.9, 1, 0.2], [30.1, 21.4, 1, 0.2], [27.5, 21.4, 1, 0.2], [26.3, 22.6, 1, 0.2], [26.3, 22.6, 2, 0.2], [18.9, 30.0, 2, 0.2], [18.9, 30.0, 1, 0.2], [18.2, 30.7, 1, 0.2], [15.6, 30.7, 1, 0.2], [13.9, 32.4, 1, 0.2], [13.9, 34.1, 1, 0.2], [10.9, 37.1, 1, 0.2], [10.9, 37.1, 2, 0.2], [10.9, 46.6, 2, 0.2], [10.9, 46.6, 1, 0.2], [10.2, 47.3, 1, 0.2], [10.2, 58.8, 1, 0.2], [10.8, 59.4, 1, 0.2], [21.3, 59.4, 1, 0.2], [23.1089, 61.2292, 1, 0.2]], "POGO5_VDN\u00000\u0000c0": [[142.4991, 31.5011, 1, 0.2], [142.4991, 31.5011, 1, 0.2]], "POGO5_VDN\u00000\u0000c1\u0000c0": [[142.4991, 31.5011, 1, 0.2], [142.4991, 31.5011, 1, 0.2]], "POGO5_VDN\u00000\u0000c1\u0000c1\u0000c0": [[142.4991, 31.5011, 1, 0.2], [142.4991, 31.5011, 1, 0.2]], "POGO5_VDN\u00000\u0000c1\u0000c1\u0000c1": [[142.4991, 31.5011, 1, 0.2], [142.2, 32.1, 1, 0.2], [142.2, 32.1, 2, 0.2], [139.8, 34.5, 2, 0.2], [139.7, 59.2, 2, 0.2], [139.7, 59.2, 1, 0.2], [139.3, 59.6, 1, 0.2], [138.5, 59.6, 1, 0.2], [136.8908, 61.2292, 1, 0.2]], "SCL\u00000\u0000c0": [[47.9, 77.5, 2, 0.2], [47.9, 75.9, 2, 0.2], [47.9, 75.9, 1, 0.2], [47.9, 75.8, 1, 0.2]], "SCL\u00000\u0000c1": [[47.9, 75.8, 1, 0.2], [47.9, 73.3, 1, 0.2]], "SCL\u00000\u0000c2": [[47.9, 73.3, 1, 0.2], [47.9, 73.2, 1, 0.2], [48.1, 73.0, 1, 0.2], [48.2, 73.0, 1, 0.2]], "SCL\u00000\u0000c3": [[48.2, 73.0, 1, 0.2], [50.7, 73.0, 1, 0.2]], "SCL\u00000\u0000c4": [[50.7, 73.0, 1, 0.2], [50.8, 73.0, 1, 0.2], [52.45, 74.65, 1, 0.2]], "SCL\u00000\u0000c5": [[52.45, 74.65, 1, 0.2], [52.5, 74.7, 1, 0.2], [52.5, 75.0, 1, 0.2]], "SCL\u00001\u0000c0": [[109.8192, 33.21, 1, 0.2], [109.8192, 33.21, 1, 0.2]], "SCL\u00001\u0000c1\u0000c0": [[109.8192, 33.21, 1, 0.2], [109.8192, 33.21, 1, 0.2]], "SCL\u00001\u0000c1\u0000c1": [[109.8192, 33.21, 1, 0.2], [109.8192, 32.5099, 1, 0.2]], "SCL\u000010\u0000c0\u0000c0": [[98.1499, 19.2113, 1, 0.2], [98.1498, 19.2112, 1, 0.2]], "SCL\u000010\u0000c0\u0000c1\u0000c0": [[98.1498, 19.2112, 1, 0.2], [98.1498, 19.2112, 1, 0.2]], "SCL\u000010\u0000c0\u0000c1\u0000c1\u0000c0": [[98.1498, 19.2112, 1, 0.2], [98.1498, 19.2112, 1, 0.2]], "SCL\u000010\u0000c0\u0000c1\u0000c1\u0000c1\u0000c0": [[98.1498, 19.2112, 1, 0.2], [98.1498, 19.2112, 1, 0.2]], "SCL\u000010\u0000c0\u0000c1\u0000c1\u0000c1\u0000c1": [[98.1498, 19.2112, 1, 0.2], [97.8709, 18.835, 1, 0.2]], "SCL\u000010\u0000c1\u0000c0": [[97.8709, 18.835, 1, 0.2], [97.8701, 18.8339, 1, 0.2]], "SCL\u000010\u0000c1\u0000c1\u0000c0": [[97.8701, 18.8339, 1, 0.2], [97.8701, 18.8339, 1, 0.2]], "SCL\u000010\u0000c1\u0000c1\u0000c1\u0000c0": [[97.8701, 18.8339, 1, 0.2], [97.8701, 18.8339, 1, 0.2]], "SCL\u000010\u0000c1\u0000c1\u0000c1\u0000c1": [[97.8701, 18.8339, 1, 0.2], [97.5932, 18.4606, 1, 0.2], [97.0756, 18.197, 1, 0.2], [96.7512, 18.194, 1, 0.2]], "SCL\u000011\u0000c0\u0000rr\u0000c0": [[98.15, 19.3, 1, 0.15], [102.1, 23.3, 1, 0.15], [102.1, 24.2, 1, 0.15], [102.1, 24.2, 2, 0.15], [103.3, 25.4, 2, 0.15], [103.3, 25.4, 1, 0.15], [103.9951, 25.1843, 1, 0.15]], "SCL\u000011\u0000c0\u0000rr\u0000c1\u0000c0": [[103.9951, 25.1843, 1, 0.15], [103.9951, 25.1843, 1, 0.15]], "SCL\u000011\u0000c0\u0000rr\u0000c1\u0000c1\u0000c0": [[103.9951, 25.1843, 1, 0.15], [103.9951, 25.1843, 1, 0.15]], "SCL\u000011\u0000c0\u0000rr\u0000c1\u0000c1\u0000c1\u0000c0": [[103.9951, 25.1843, 1, 0.15], [103.9951, 25.1843, 1, 0.15]], "SCL\u000011\u0000c0\u0000rr\u0000c1\u0000c1\u0000c1\u0000c1": [[103.9951, 25.1843, 1, 0.15], [104.025, 25.175, 1, 0.15]], "SCL\u000011\u0000c1\u0000rr\u0000c0": [[104.025, 25.175, 1, 0.15], [104.0252, 25.1752, 1, 0.15]], "SCL\u000011\u0000c1\u0000rr\u0000c1\u0000c0": [[104.0252, 25.1752, 1, 0.15], [107.5507, 28.75, 1, 0.15]], "SCL\u000011\u0000c1\u0000rr\u0000c1\u0000c1": [[107.5507, 28.75, 1, 0.15], [107.6, 28.8, 1, 0.15], [107.6, 31.4, 1, 0.15], [107.6, 31.4, 2, 0.15], [109.3, 33.1, 2, 0.15], [109.6, 33.1, 2, 0.15], [109.6, 33.1, 1, 0.15], [109.8192, 32.5099, 1, 0.15]], "SCL\u000012\u0000c0": [[109.4, 33.2, 1, 0.2], [109.319, 33.21, 1, 0.2]], "SCL\u000012\u0000c1": [[109.319, 33.21, 1, 0.2], [109.3188, 33.21, 1, 0.2]], "SCL\u000013\u0000c0\u0000rr": [[109.9, 33.0, 2, 0.15], [109.5, 33.4, 2, 0.15], [108.4103, 33.5816, 2, 0.15], [108.25, 33.7, 2, 0.15], [108.25, 33.7, 2, 0.15], [108.0882, 33.8, 2, 0.15], [106.1, 33.8, 2, 0.15], [106.1, 33.8, 1, 0.15], [105.9, 34.0, 1, 0.15], [104.6, 34.0, 1, 0.15], [104.6, 34.0, 2, 0.15], [104.8, 34.2, 2, 0.15], [104.8, 39.3, 2, 0.15], [108.4, 42.9, 2, 0.15], [108.4, 42.9, 1, 0.15], [111.9, 39.4, 1, 0.15], [115.7, 39.4, 1, 0.15], [115.7, 39.4, 2, 0.15], [116.3, 38.8, 2, 0.15], [116.3, 38.1, 2, 0.15], [115.9, 37.7, 2, 0.15], [115.2, 37.7, 2, 0.15], [114.8, 37.3, 2, 0.15]], "SCL\u000013\u0000c1": [[114.8, 37.3, 2, 0.15], [114.8, 37.3, 2, 0.15]], "SCL\u000013\u0000c10": [[122.4, 44.9, 2, 0.15], [122.45, 44.95, 2, 0.15]], "SCL\u000013\u0000c11": [[122.45, 44.95, 2, 0.15], [122.45, 44.95, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c0": [[122.45, 44.95, 2, 0.15], [126.05, 48.55, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c1": [[126.05, 48.55, 2, 0.15], [126.05, 48.55, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c2": [[126.05, 48.55, 2, 0.15], [126.1, 48.6, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c3": [[126.1, 48.6, 2, 0.15], [126.1, 48.6, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c4": [[126.1, 48.6, 2, 0.15], [126.2, 48.7, 2, 0.15]], "SCL\u000013\u0000c12\u0000c0\u0000c5": [[126.2, 48.7, 2, 0.15], [126.25, 48.75, 2, 0.15]], "SCL\u000013\u0000c12\u0000c1": [[126.25, 48.75, 2, 0.15], [126.25, 48.75, 2, 0.15]], "SCL\u000013\u0000c12\u0000c2": [[126.25, 48.75, 2, 0.15], [126.3, 48.8, 2, 0.15]], "SCL\u000013\u0000c12\u0000c3": [[126.3, 48.8, 2, 0.15], [126.3, 48.8, 2, 0.15]], "SCL\u000013\u0000c12\u0000c4": [[126.3, 48.8, 2, 0.15], [126.4, 48.9, 2, 0.15]], "SCL\u000013\u0000c12\u0000c5": [[126.4, 48.9, 2, 0.15], [126.45, 48.95, 2, 0.15]], "SCL\u000013\u0000c13": [[126.45, 48.95, 2, 0.15], [126.45, 48.95, 2, 0.15]], "SCL\u000013\u0000c14": [[126.45, 48.95, 2, 0.15], [126.5, 49.0, 2, 0.15]], "SCL\u000013\u0000c15": [[126.5, 49.0, 2, 0.15], [126.5, 49.0, 2, 0.15]], "SCL\u000013\u0000c16": [[126.5, 49.0, 2, 0.15], [126.6, 49.1, 2, 0.15]], "SCL\u000013\u0000c17": [[126.6, 49.1, 2, 0.15], [126.8, 49.3, 2, 0.15], [126.8, 49.3, 1, 0.15], [126.4996, 48.5798, 1, 0.15]], "SCL\u000013\u0000c2\u0000c0": [[114.8, 37.3, 2, 0.15], [119.75, 42.25, 2, 0.15]], "SCL\u000013\u0000c2\u0000c1": [[119.75, 42.25, 2, 0.15], [119.75, 42.25, 2, 0.15]], "SCL\u000013\u0000c2\u0000c2": [[119.75, 42.25, 2, 0.15], [120.85, 43.35, 2, 0.15]], "SCL\u000013\u0000c3": [[120.85, 43.35, 2, 0.15], [120.85, 43.35, 2, 0.15]], "SCL\u000013\u0000c4": [[120.85, 43.35, 2, 0.15], [121.75, 44.25, 2, 0.15]], "SCL\u000013\u0000c5": [[121.75, 44.25, 2, 0.15], [121.75, 44.25, 2, 0.15]], "SCL\u000013\u0000c6\u0000c0": [[121.75, 44.25, 2, 0.15], [121.85, 44.35, 2, 0.15]], "SCL\u000013\u0000c6\u0000c1": [[121.85, 44.35, 2, 0.15], [121.85, 44.35, 2, 0.15]], "SCL\u000013\u0000c6\u0000c2": [[121.85, 44.35, 2, 0.15], [121.9, 44.4, 2, 0.15]], "SCL\u000013\u0000c7": [[121.9, 44.4, 2, 0.15], [121.9, 44.4, 2, 0.15]], "SCL\u000013\u0000c8\u0000c0": [[121.9, 44.4, 2, 0.15], [122.0, 44.5, 2, 0.15]], "SCL\u000013\u0000c8\u0000c1": [[122.0, 44.5, 2, 0.15], [122.0, 44.5, 2, 0.15]], "SCL\u000013\u0000c8\u0000c2": [[122.0, 44.5, 2, 0.15], [122.3, 44.8, 2, 0.15]], "SCL\u000013\u0000c8\u0000c3": [[122.3, 44.8, 2, 0.15], [122.3, 44.8, 2, 0.15]], "SCL\u000013\u0000c8\u0000c4": [[122.3, 44.8, 2, 0.15], [122.35, 44.85, 2, 0.15]], "SCL\u000013\u0000c8\u0000c5": [[122.35, 44.85, 2, 0.15], [122.35, 44.85, 2, 0.15]], "SCL\u000013\u0000c8\u0000c6": [[122.35, 44.85, 2, 0.15], [122.4, 44.9, 2, 0.15]], "SCL\u000013\u0000c9": [[122.4, 44.9, 2, 0.15], [122.4, 44.9, 2, 0.15]], "SCL\u000014": [[104.0, 25.2, 1, 0.2], [95.9, 33.3, 1, 0.2], [95.9, 33.3, 2, 0.2], [77.2, 52.0, 2, 0.2], [76.4, 52.0, 2, 0.2], [74.4, 54.0, 2, 0.2], [74.4, 54.0, 1, 0.2], [74.2254, 53.7792, 1, 0.2]], "SCL\u000015\u0000c0\u0000c0": [[74.1, 53.95, 2, 0.2], [70.2, 50.05, 2, 0.2], [61.1, 50.05, 2, 0.2]], "SCL\u000015\u0000c0\u0000c1": [[61.1, 50.05, 2, 0.2], [61.1, 50.05, 2, 0.2]], "SCL\u000015\u0000c0\u0000c2": [[61.1, 50.05, 2, 0.2], [60.3, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c0": [[60.3, 50.05, 2, 0.2], [58.4, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c1": [[58.4, 50.05, 2, 0.2], [58.4, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c2": [[58.4, 50.05, 2, 0.2], [48.2, 50.05, 2, 0.2]], "SCL\u000015\u0000c1\u0000c3": [[48.2, 50.05, 2, 0.2], [48.1, 50.05, 2, 0.2], [48.075, 50.025, 2, 0.2]], "SCL\u000015\u0000c1\u0000c4": [[48.075, 50.025, 2, 0.2], [47.9, 49.85, 2, 0.2], [47.9, 49.85, 1, 0.2], [47.0634, 49.0134, 1, 0.2], [46.9599, 48.7399, 1, 0.2], [46.9697, 48.5798, 1, 0.2]], "SCL\u000016\u0000c0\u0000c0\u0000c0\u0000c0\u0000c0": [[60.3, 50.1, 2, 0.2], [60.3, 73.6, 2, 0.2], [56.3, 77.6, 2, 0.2], [47.8997, 77.5387, 2, 0.2]], "SCL\u000016\u0000c0\u0000c0\u0000c0\u0000c0\u0000c1": [[47.8997, 77.5387, 2, 0.2], [47.8997, 77.5387, 2, 0.2]], "SCL\u000016\u0000c0\u0000c0\u0000c0\u0000c1": [[47.8997, 77.5387, 2, 0.2], [47.8997, 77.5387, 2, 0.2]], "SCL\u000016\u0000c0\u0000c0\u0000c1": [[47.8997, 77.5387, 2, 0.2], [47.8997, 77.5387, 2, 0.2]], "SCL\u000016\u0000c0\u0000c1": [[47.8997, 77.5387, 2, 0.2], [42.6, 77.5, 2, 0.2], [40.05, 74.95, 2, 0.2]], "SCL\u000016\u0000c1\u0000c0\u0000c0\u0000c0\u0000c0": [[40.05, 74.95, 2, 0.2], [40.0, 74.9, 2, 0.2], [40.0, 68.0, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c1\u0000c0\u0000c0\u0000c0\u0000c1": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c1\u0000c0\u0000c0\u0000c1": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c1\u0000c0\u0000c1": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c1\u0000c1": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000016\u0000c2": [[35.8089, 63.7692, 2, 0.2], [35.8089, 63.7692, 2, 0.2]], "SCL\u000017\u0000c0\u0000c0": [[34.95, 62.9, 1, 0.2], [34.55, 62.5, 1, 0.2], [32.15, 62.5, 1, 0.2], [32.0, 62.35, 1, 0.2], [32.0, 60.1, 1, 0.2], [30.05, 58.15, 1, 0.2]], "SCL\u000017\u0000c0\u0000c1": [[30.05, 58.15, 1, 0.2], [29.9, 58.0, 1, 0.2]], "SCL\u000017\u0000c0\u0000c10": [[15.7, 51.0, 1, 0.2], [15.55, 50.85, 1, 0.2]], "SCL\u000017\u0000c0\u0000c11": [[15.55, 50.85, 1, 0.2], [15.45, 50.75, 1, 0.2]], "SCL\u000017\u0000c0\u0000c12": [[15.45, 50.75, 1, 0.2], [15.45, 50.75, 1, 0.2]], "SCL\u000017\u0000c0\u0000c13": [[15.45, 50.75, 1, 0.2], [15.35, 50.65, 1, 0.2]], "SCL\u000017\u0000c0\u0000c14": [[15.35, 50.65, 1, 0.2], [15.3, 50.6, 1, 0.2], [15.3, 50.6, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c0": [[15.3, 50.6, 1, 0.2], [15.3, 50.6, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c1\u0000c0": [[15.3, 50.6, 1, 0.2], [15.3, 50.6, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c1\u0000c1\u0000c0": [[15.3, 50.6, 1, 0.2], [15.3, 50.6, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c1\u0000c1\u0000c1": [[15.3, 50.6, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c1\u0000c1\u0000c2": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c1\u0000c2": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c15\u0000c2": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c16": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c0\u0000c2": [[29.9, 58.0, 1, 0.2], [29.9, 58.0, 1, 0.2]], "SCL\u000017\u0000c0\u0000c3": [[29.9, 58.0, 1, 0.2], [29.45, 57.55, 1, 0.2], [29.2, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c4": [[29.2, 57.55, 1, 0.2], [29.2, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c5\u0000c0": [[29.2, 57.55, 1, 0.2], [28.6, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c5\u0000c1": [[28.6, 57.55, 1, 0.2], [28.6, 57.55, 1, 0.2]], "SCL\u000017\u0000c0\u0000c5\u0000c2": [[28.6, 57.55, 1, 0.2], [22.25, 57.55, 1, 0.2], [22.15, 57.45, 1, 0.2]], "SCL\u000017\u0000c0\u0000c6": [[22.15, 57.45, 1, 0.2], [22.15, 57.45, 1, 0.2]], "SCL\u000017\u0000c0\u0000c7": [[22.15, 57.45, 1, 0.2], [15.75, 51.05, 1, 0.2]], "SCL\u000017\u0000c0\u0000c8": [[15.75, 51.05, 1, 0.2], [15.75, 51.05, 1, 0.2]], "SCL\u000017\u0000c0\u0000c9": [[15.75, 51.05, 1, 0.2], [15.7, 51.0, 1, 0.2]], "SCL\u000017\u0000c1": [[15.3004, 49.69, 1, 0.2], [15.3004, 49.69, 1, 0.2]], "SCL\u000017\u0000c2": [[15.3004, 49.69, 1, 0.2], [15.3009, 48.5798, 1, 0.2]], "SCL\u000018": [[40.0, 75.0, 2, 0.2], [29.6, 75.0, 2, 0.2], [9.4, 95.2, 2, 0.2], [7.4, 95.2, 2, 0.2], [7.4, 95.2, 1, 0.2], [7.5006, 95.7788, 1, 0.2]], "SCL\u000019\u0000rr": [[7.1, 95.2, 1, 0.2], [7.5663, 94.7696, 1, 0.2], [7.75, 94.35, 1, 0.2], [7.75, 94.0, 1, 0.2], [7.4, 93.65, 1, 0.2], [6.8, 93.65, 1, 0.2], [6.05, 94.4, 1, 0.2], [5.9995, 95.7788, 1, 0.2]], "SCL\u00002": [[15.3009, 49.69, 1, 0.2], [15.3009, 48.5798, 1, 0.2]], "SCL\u00003": [[52.5881, 75.8089, 1, 0.2], [52.5881, 76.9191, 1, 0.2]], "SCL\u00004": [[140.97, 75.8089, 1, 0.2], [140.97, 76.9191, 1, 0.2]], "SCL\u00005": [[46.9697, 49.69, 1, 0.2], [46.9697, 48.5798, 1, 0.2]], "SCL\u00006": [[126.4996, 49.69, 1, 0.2], [126.4996, 48.5798, 1, 0.2]], "SCL\u00007\u0000rr": [[5.9995, 96.8891, 1, 0.2], [5.9995, 95.7788, 1, 0.2]], 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35.8428, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c1": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c2": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c3": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c4": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c5": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8147, 1, 0.2]], "SDA\u00001\u0000c1\u0000rr\u0000rr\u0000c1\u0000c6": [[80.329, 35.8147, 1, 0.2], [80.329, 35.8112, 1, 0.2]], "SDA\u00001\u0000c2": [[140.7787, 74.2213, 1, 0.2], [140.8, 74.2, 1, 0.2]], "SDA\u000010": [[7.0002, 96.8891, 1, 0.2], [7.0002, 95.7788, 1, 0.2]], "SDA\u000011\u0000c0": [[73.5752, 52.6537, 1, 0.2], [73.5752, 52.6537, 1, 0.2]], "SDA\u000011\u0000c1\u0000c0": [[73.5752, 52.6537, 1, 0.2], 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0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c6": [[73.5752, 52.6545, 1, 0.2], [73.5752, 52.6545, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c7": [[73.5752, 52.6545, 1, 0.2], [73.5752, 52.6545, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c8": [[73.5752, 52.6545, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c9": [[73.5752, 52.6546, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c10": [[73.5752, 52.6546, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c11": [[73.5752, 52.6546, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c12": [[73.5752, 52.6546, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c13": [[73.5752, 52.6546, 1, 0.2], [73.5752, 52.6546, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c17\u0000c14": [[73.5752, 52.6546, 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[73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c3": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c4": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c5": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c6": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c7": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c8": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000011\u0000c1\u0000c5\u0000rr\u0000c9": [[73.5752, 52.6539, 1, 0.2], [73.5752, 52.6539, 1, 0.2]], "SDA\u000012\u0000c0": [[110.3, 32.5, 1, 0.2], [110.3, 32.1, 1, 0.2], [110.2, 32.0, 1, 0.2]], "SDA\u000012\u0000c1": [[110.2, 32.0, 1, 0.2], [109.3, 31.1, 1, 0.2], [108.9, 31.1, 1, 0.2], [108.9, 31.1, 2, 0.2], [108.5, 30.7, 2, 0.2], [102.5, 30.7, 2, 0.2]], "SDA\u000012\u0000c2": [[102.5, 30.7, 2, 0.2], [89.6, 30.7, 2, 0.2], [87.3544, 28.4739, 2, 0.2], [87.3544, 28.4739, 1, 0.2], [87.3544, 28.4739, 1, 0.2]], "SDA\u000013": [[87.2, 28.3, 2, 0.2], [86.0959, 27.0942, 2, 0.2], [86.0959, 27.0942, 1, 0.2], [86.0959, 27.0942, 1, 0.2]], "SDA\u000014\u0000rr\u0000c0\u0000rr\u0000c0\u0000c0": [[86.6, 28.7, 1, 0.2], [86.6, 29.65, 1, 0.2], [85.6, 30.65, 1, 0.2], [82.0, 30.65, 1, 0.2], [79.9, 32.75, 1, 0.2], [79.9, 33.45, 1, 0.2], [80.55, 34.1, 1, 0.2], [80.55, 35.6, 1, 0.2], [80.3324, 35.8147, 1, 0.2]], "SDA\u000014\u0000rr\u0000c0\u0000rr\u0000c0\u0000c1": [[80.3324, 35.8147, 1, 0.2], [80.3324, 35.8147, 1, 0.2]], "SDA\u000014\u0000rr\u0000c0\u0000rr\u0000c0\u0000c2": [[80.3324, 35.8147, 1, 0.2], [80.3324, 35.8147, 1, 0.2]], "SDA\u000014\u0000rr\u0000c0\u0000rr\u0000c0\u0000c3": [[80.3324, 35.8147, 1, 0.2], [80.3324, 35.8147, 1, 0.2]], "SDA\u000014\u0000rr\u0000c0\u0000rr\u0000c1": [[80.3324, 35.8147, 1, 0.2], [80.3324, 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"VBUS_EN5\u00000\u0000c0": [[108.95, 61.225, 1, 0.2], [108.9525, 61.2275, 1, 0.2]], "VBUS_EN5\u00000\u0000c1": [[108.9525, 61.2275, 1, 0.2], [110.175, 62.45, 1, 0.2], [112.75, 62.5, 1, 0.2]], "VDAC1\u00000\u0000c0": [[15.2324, 20.701, 1, 0.2], [15.2324, 20.701, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c0": [[15.2324, 20.701, 1, 0.2], [15.2324, 20.701, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c1": [[15.2324, 20.701, 1, 0.2], [15.2324, 21.271, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c2": [[15.2324, 21.271, 1, 0.2], [15.2324, 21.2715, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c1\u0000c0": [[15.2324, 20.701, 1, 0.2], [15.2324, 20.701, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c1\u0000c1\u0000c0": [[15.2324, 20.701, 1, 0.2], [15.2324, 20.701, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c1\u0000c1\u0000c1\u0000c0": [[15.2324, 20.701, 1, 0.2], [15.2324, 20.701, 1, 0.2]], "VDAC1\u00000\u0000c1\u0000c1\u0000c1\u0000c1\u0000c1": [[15.2324, 20.701, 1, 0.2], [15.2324, 21.271, 1, 0.2]], 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["EFUSE_EN3", 2, 142.9, 81.4, 145.7, 81.4, 0.2], ["EFUSE_EN3", 1, 145.7, 81.4, 145.7, 85.9, 0.2], ["EFUSE_EN3", 2, 145.7, 85.9, 145.7, 88.2, 0.2], ["EFUSE_EN3", 2, 145.7, 88.2, 141.6, 92.3, 0.2], ["EFUSE_EN3", 2, 141.6, 92.3, 133.3, 92.3, 0.2], ["EFUSE_EN3", 2, 133.3, 92.3, 132.8, 92.8, 0.2], ["EFUSE_EN3", 1, 132.8, 92.8, 131.5, 94.1, 0.2], ["EFUSE_EN3", 1, 131.5, 94.1, 128.0, 94.1, 0.2], ["EFUSE_EN3", 1, 128.0, 94.1, 126.4, 95.7, 0.2], ["EFUSE_EN3", 1, 126.4, 95.7, 123.4, 95.7, 0.2], ["EFUSE_EN3", 1, 123.4, 95.7, 123.0, 96.1, 0.2], ["EFUSE_EN3", 2, 123.0, 96.1, 118.7, 100.4, 0.2], ["EFUSE_EN3", 2, 118.7, 100.4, 102.0, 100.4, 0.2], ["EFUSE_EN3", 1, 102.0, 100.4, 101.2, 101.2, 0.2], ["EFUSE_EN3", 1, 101.2, 101.2, 99.0, 101.2, 0.2], ["EFUSE_EN3", 2, 99.0, 101.2, 97.8, 101.2, 0.2], ["EFUSE_EN3", 2, 97.8, 101.2, 89.5, 92.9, 0.2], ["EFUSE_EN3", 2, 89.5, 92.9, 89.5, 91.4, 0.2], ["EFUSE_EN3", 1, 89.5, 91.4, 90.2, 90.7, 0.2], ["EFUSE_EN3", 1, 90.2, 90.7, 90.2, 75.7, 0.2], ["EFUSE_EN3", 2, 90.2, 75.7, 93.9, 72.0, 0.2], ["EFUSE_EN3", 1, 93.9, 72.0, 95.4, 70.5, 0.2], ["EFUSE_EN3", 2, 95.4, 70.5, 97.6, 70.5, 0.2], ["EFUSE_EN3", 1, 97.6, 70.5, 98.5, 70.5, 0.2], ["EFUSE_EN3", 1, 98.5, 70.5, 101.4, 67.6, 0.2], ["EFUSE_EN3", 1, 101.4, 67.6, 103.5, 67.6, 0.2], ["EFUSE_EN3", 2, 103.5, 67.6, 105.3, 67.6, 0.2], ["EFUSE_EN3", 2, 105.3, 67.6, 105.7, 68.0, 0.2], ["EFUSE_EN3", 2, 105.7, 68.0, 108.6, 68.0, 0.2], ["EFUSE_EN3", 2, 108.6, 68.0, 113.6, 73.0, 0.2], ["EFUSE_EN3", 1, 113.6, 73.0, 125.9, 73.0, 0.2], ["EFUSE_EN3", 1, 125.9, 73.0, 131.0, 78.1, 0.2], ["EFUSE_EN3", 2, 131.0, 78.1, 131.2, 78.3, 0.2], ["EFUSE_EN3", 2, 131.2, 78.3, 133.2, 78.3, 0.2], ["EFUSE_EN3", 2, 133.2, 78.3, 133.15, 78.25, 0.2], ["EFUSE_EN3", 2, 133.15, 78.25, 132.1947, 78.2171, 0.2], ["EFUSE_EN3", 2, 132.1947, 78.2171, 131.35, 78.55, 0.2], ["EFUSE_EN3", 2, 131.35, 78.55, 131.0, 78.9, 0.2], ["EFUSE_EN3", 1, 131.0, 78.9, 130.9843, 78.0009, 0.2], ["EFUSE_EN3", 2, 133.2, 78.2, 133.2, 75.4, 0.2], ["EFUSE_EN3", 1, 133.2, 75.4, 133.1697, 75.4507, 0.2], ["EFUSE_FLT1", 1, 74.8757, 46.6085, 74.8757, 45.483, 0.2], ["EFUSE_FLT1", 1, 23.9, 43.5, 24.1, 43.5, 0.2], ["EFUSE_FLT1", 2, 24.1, 43.5, 24.3, 43.3, 0.2], ["EFUSE_FLT1", 2, 24.3, 43.3, 41.7, 43.3, 0.2], ["EFUSE_FLT1", 1, 41.7, 43.3, 43.8, 41.2, 0.2], ["EFUSE_FLT1", 2, 43.8, 41.2, 56.0, 41.2, 0.2], ["EFUSE_FLT1", 2, 56.0, 41.2, 57.5, 39.7, 0.2], ["EFUSE_FLT1", 1, 57.5, 39.7, 60.9, 39.7, 0.2], ["EFUSE_FLT1", 1, 60.9, 39.7, 64.3, 43.1, 0.2], ["EFUSE_FLT1", 1, 64.3, 43.1, 72.6, 43.1, 0.2], ["EFUSE_FLT1", 2, 72.6, 43.1, 74.7, 45.3, 0.2], ["EFUSE_FLT1", 1, 74.7, 45.3, 74.8757, 45.483, 0.2], ["EFUSE_PG3", 1, 78.7746, 52.6537, 78.7746, 53.7792, 0.2], ["EFUSE_PG3", 2, 130.3, 77.7, 120.3, 67.7, 0.15], ["EFUSE_PG3", 2, 120.3, 67.7, 118.8, 67.5, 0.15], ["EFUSE_PG3", 2, 118.8, 67.5, 106.1, 67.5, 0.15], ["EFUSE_PG3", 2, 106.1, 67.5, 104.4, 65.8, 0.15], ["EFUSE_PG3", 1, 104.4, 65.8, 103.9, 65.3, 0.15], ["EFUSE_PG3", 1, 103.9, 65.3, 97.9, 65.3, 0.15], ["EFUSE_PG3", 1, 97.9, 65.3, 95.1, 62.5, 0.15], ["EFUSE_PG3", 2, 95.1, 62.5, 91.8, 62.5, 0.15], ["EFUSE_PG3", 1, 91.8, 62.5, 87.4, 62.5, 0.15], ["EFUSE_PG3", 1, 87.4, 62.5, 78.7746, 53.7792, 0.15], ["INA_ALERT", 1, 128.85, 53.15, 128.85, 51.45, 0.2], ["INA_ALERT", 1, 128.85, 51.45, 130.0, 50.3, 0.2], ["INA_ALERT", 1, 130.0, 50.3, 132.8, 50.3, 0.2], ["INA_ALERT", 1, 132.8, 50.3, 133.25, 49.85, 0.2], ["INA_ALERT", 2, 133.25, 49.85, 138.45, 49.85, 0.2], ["INA_ALERT", 1, 138.45, 49.85, 140.35, 51.75, 0.2], ["INA_ALERT", 1, 140.35, 51.75, 140.35, 52.15, 0.2], ["INA_ALERT", 1, 140.35, 52.15, 147.95, 59.75, 0.2], ["INA_ALERT", 2, 147.95, 59.75, 148.3, 60.1, 0.2], ["INA_ALERT", 2, 148.3, 60.1, 148.3, 73.45, 0.2], ["INA_ALERT", 2, 148.3, 73.45, 146.8, 74.95, 0.2], ["INA_ALERT", 2, 146.8, 74.95, 143.95, 74.95, 0.2], ["INA_ALERT", 2, 143.95, 74.95, 143.75, 75.15, 0.2], ["INA_ALERT", 1, 143.75, 75.15, 143.3561, 74.7561, 0.2], ["INA_ALERT", 1, 143.3561, 74.7561, 143.1001, 74.6562, 0.2], ["INA_ALERT", 1, 143.1001, 74.6562, 142.05, 74.7, 0.2], ["INA_ALERT", 2, 147.5, 74.3, 148.0, 74.8, 0.2], ["INA_ALERT", 1, 148.0, 74.8, 149.2, 76.0, 0.2], ["INA_ALERT", 1, 149.2, 76.0, 149.2, 83.5, 0.2], ["INA_ALERT", 1, 149.2, 83.5, 145.0, 87.7, 0.2], ["INA_ALERT", 2, 145.0, 87.7, 140.9, 91.8, 0.2], ["INA_ALERT", 2, 140.9, 91.8, 132.7, 91.8, 0.2], ["INA_ALERT", 2, 132.7, 91.8, 129.5, 95.0, 0.2], ["INA_ALERT", 1, 129.5, 95.0, 124.8, 99.7, 0.2], ["INA_ALERT", 1, 124.8, 99.7, 103.7, 99.7, 0.2], ["INA_ALERT", 2, 103.7, 99.7, 100.4, 99.7, 0.2], ["INA_ALERT", 1, 100.4, 99.7, 99.0, 99.8, 0.2], ["INA_ALERT", 2, 99.0, 99.8, 86.7, 87.5, 0.2], ["INA_ALERT", 2, 86.7, 87.5, 68.8, 87.5, 0.2], ["INA_ALERT", 1, 68.8, 87.5, 62.1, 80.8, 0.2], ["INA_ALERT", 2, 62.1, 80.8, 59.7, 78.4, 0.2], ["INA_ALERT", 1, 59.7, 78.4, 58.6, 77.3, 0.2], ["INA_ALERT", 2, 58.6, 77.3, 58.3, 77.6, 0.2], ["INA_ALERT", 2, 58.3, 77.6, 52.8, 77.6, 0.2], ["INA_ALERT", 2, 52.8, 77.6, 51.8, 76.6, 0.2], ["INA_ALERT", 2, 51.8, 76.6, 41.6, 76.6, 0.2], ["INA_ALERT", 2, 41.6, 76.6, 40.0, 75.0, 0.2], ["INA_ALERT", 2, 40.0, 75.0, 40.0, 73.7, 0.2], ["INA_ALERT", 2, 40.0, 73.7, 39.8, 73.5, 0.2], ["INA_ALERT", 2, 39.8, 73.5, 38.9, 73.5, 0.2], ["INA_ALERT", 2, 38.9, 73.5, 35.2, 69.8, 0.2], ["K3_PWR", 1, 120.2, 94.2, 120.15, 94.45, 0.2], ["K3_PWR", 1, 120.15, 94.45, 119.845, 94.7, 0.2], ["K3_PWR", 1, 119.845, 94.7, 106.6, 94.7, 0.2], ["K3_PWR", 1, 106.6, 94.7, 103.7, 97.6, 0.2], ["K3_PWR", 2, 103.7, 97.6, 102.3, 99.0, 0.2], ["K3_PWR", 1, 102.3, 99.0, 100.8, 100.5, 0.2], ["K3_PWR", 1, 100.8, 100.5, 98.3, 100.5, 0.2], ["K3_PWR", 2, 98.3, 100.5, 97.3, 99.5, 0.2], ["K3_PWR", 2, 97.3, 99.5, 97.3, 99.2, 0.2], ["K3_PWR", 1, 97.3, 99.2, 97.3, 93.5, 0.2], ["K3_PWR", 2, 97.3, 93.5, 85.3, 81.5, 0.2], ["K3_PWR", 2, 85.3, 81.5, 85.3, 65.4, 0.2], ["K3_PWR", 2, 85.3, 65.4, 88.9, 61.8, 0.2], ["K3_PWR", 1, 88.9, 61.8, 91.9, 58.8, 0.2], ["K3_PWR", 1, 91.9, 58.8, 92.7, 58.8, 0.2], ["K3_PWR", 2, 92.7, 58.8, 93.2, 58.3, 0.2], ["K3_PWR", 2, 93.2, 58.3, 96.5, 58.3, 0.2], ["K3_PWR", 1, 96.5, 58.3, 97.7, 57.1, 0.2], ["K3_PWR", 1, 97.7, 57.1, 97.7, 52.2, 0.2], ["K3_PWR", 2, 97.7, 52.2, 97.6, 50.8, 0.2], ["K3_PWR", 1, 97.6, 50.8, 97.4, 51.0, 0.2], ["K3_PWR", 1, 97.4, 51.0, 94.8, 51.0, 0.2], ["K3_PWR", 1, 94.8, 51.0, 94.4, 50.6, 0.2], ["K4_VUP", 1, 67.75, 34.75, 67.9, 34.5, 0.2], ["K4_VUP", 1, 67.9, 34.5, 68.3415, 34.25, 0.2], ["K4_VUP", 1, 68.3415, 34.25, 79.05, 34.25, 0.2], ["K4_VUP", 2, 79.05, 34.25, 79.95, 33.35, 0.2], ["K4_VUP", 2, 79.95, 33.35, 80.55, 33.1, 0.2], ["K4_VUP", 1, 80.55, 33.1, 84.05, 36.6, 0.2], ["K4_VUP", 1, 84.05, 36.6, 89.05, 36.6, 0.2], ["K4_VUP", 1, 89.05, 36.6, 89.4, 36.25, 0.2], ["KEY_RCLK", 1, 93.1, 56.0, 93.4, 56.3, 0.2], ["KEY_RCLK", 1, 93.4, 56.3, 93.4, 62.1, 0.2], ["KEY_RCLK", 1, 93.4, 62.1, 90.9, 64.6, 0.2], ["KEY_RCLK", 1, 90.9, 64.6, 90.9, 65.8, 0.2], ["KEY_RCLK", 1, 90.9, 65.8, 91.3, 66.2, 0.2], ["KEY_RCLK", 1, 91.3, 66.2, 91.7, 66.2, 0.2], ["KEY_RCLK", 1, 91.7, 66.2, 92.2, 66.7, 0.2], ["KEY_RCLK", 2, 92.2, 66.7, 93.1, 67.6, 0.2], ["KEY_RCLK", 2, 93.1, 67.6, 93.1, 69.9, 0.2], ["KEY_RCLK", 1, 93.1, 69.9, 92.9, 70.1, 0.2], ["KEY_RCLK", 1, 92.9, 70.1, 92.9, 72.8, 0.2], ["KEY_SRCLK", 1, 94.4, 56.0, 94.4, 63.5, 0.2], ["KEY_SRCLK", 1, 94.4, 63.5, 98.7, 67.8, 0.2], ["KEY_SRCLK", 1, 98.7, 67.8, 98.7, 68.7, 0.2], ["KEY_SRCLK", 1, 98.7, 68.7, 98.4, 69.0, 0.2], ["KEY_SRCLK", 1, 98.4, 69.0, 98.0, 69.0, 0.2], ["KEY_SRCLK", 1, 98.0, 69.0, 94.2, 72.8, 0.2], ["POGO1_PWR", 1, 24.45, 62.5, 26.7, 62.5, 0.2], ["POGO1_PWR", 1, 26.7, 62.5, 26.9, 62.3, 0.2], ["POGO1_PWR", 1, 26.9, 62.3, 26.9, 60.2, 0.2], ["POGO1_PWR", 1, 26.9, 60.2, 27.15, 59.95, 0.2], ["POGO1_PWR", 1, 27.15, 59.95, 29.2, 59.95, 0.2], ["POGO1_PWR", 1, 29.2, 59.95, 30.45, 58.7, 0.2], ["POGO1_PWR", 1, 30.45, 58.7, 30.45, 28.35, 0.2], ["POGO1_PWR", 1, 30.45, 28.35, 31.3004, 27.5006, 0.2], ["SDA", 1, 80.329, 36.5, 80.329, 35.8112, 0.2], ["SDA", 1, 86.6, 28.7, 86.6, 30.075, 0.2], ["SDA", 1, 86.6, 30.075, 82.975, 33.7, 0.2], ["SDA", 1, 82.975, 33.7, 82.975, 34.625, 0.2], ["SDA", 1, 82.975, 34.625, 84.325, 35.975, 0.2], ["SDA", 2, 84.325, 35.975, 85.125, 36.775, 0.2], ["SDA", 2, 85.125, 36.775, 85.125, 39.9, 0.2], ["SDA", 2, 85.125, 39.9, 85.325, 40.1, 0.2], ["SDA", 1, 85.325, 40.1, 83.875, 41.55, 0.2], ["SDA", 1, 83.875, 41.55, 81.85, 41.55, 0.2], ["SDA", 1, 81.85, 41.55, 81.5974, 41.4406, 0.2], ["SDA", 1, 81.5974, 41.4406, 81.325, 41.15, 0.2], ["SDA", 2, 81.325, 41.15, 81.425, 41.05, 0.2], ["SDA", 2, 81.425, 41.05, 81.425, 37.95, 0.2], ["SDA", 2, 81.425, 37.95, 80.975, 37.5, 0.2], ["SDA", 2, 80.975, 37.5, 80.975, 37.325, 0.2], ["SDA", 2, 80.975, 37.325, 80.848, 37.0296, 0.2], ["SDA", 2, 80.848, 37.0296, 80.0, 36.225, 0.2], ["SDA", 1, 80.0, 36.225, 80.329, 35.8112, 0.2], ["VBUS_EN4", 1, 88.6359, 27.0942, 88.6, 25.5, 0.2], ["VBUS_EN4", 2, 88.6, 25.5, 88.6, 24.4, 0.2], ["VBUS_EN4", 2, 88.6, 24.4, 94.4, 18.6, 0.2], ["VBUS_EN4", 2, 94.4, 18.6, 99.5, 18.6, 0.2], ["VBUS_EN4", 2, 99.5, 18.6, 99.8, 18.3, 0.2], ["VBUS_EN4", 1, 99.8, 18.3, 100.3, 17.8, 0.2], ["VBUS_EN4", 1, 100.3, 17.8, 100.3, 14.2, 0.2], ["VBUS_EN4", 2, 100.3, 14.2, 100.3617, 13.3985, 0.2], ["VBUS_EN4", 2, 100.3617, 13.3985, 100.0464, 12.5464, 0.2], ["VBUS_EN4", 2, 100.0464, 12.5464, 99.0, 11.5, 0.2], ["VBUS_EN4", 2, 99.0, 11.5, 77.7, 11.5, 0.2], ["VBUS_EN4", 2, 77.7, 11.5, 76.7, 12.5, 0.2], ["VBUS_EN4", 2, 76.7, 12.5, 41.6, 12.5, 0.2], ["VBUS_EN4", 2, 41.6, 12.5, 31.4, 22.7, 0.2], ["VBUS_EN4", 1, 31.4, 22.7, 26.3, 27.8, 0.2], ["VBUS_EN4", 1, 26.3, 27.8, 26.3, 39.0, 0.2], ["VBUS_EN4", 1, 26.3, 39.0, 28.3, 41.0, 0.2], ["VBUS_EN4", 1, 28.3, 41.0, 28.3, 44.8, 0.2], ["VBUS_EN4", 2, 28.3, 44.8, 29.3, 45.8, 0.2], ["VBUS_EN4", 2, 29.3, 45.8, 29.3, 46.1, 0.2], ["VBUS_EN4", 1, 29.3, 46.1, 29.4, 56.8, 0.2], ["VBUS_EN4", 2, 29.4, 56.8, 30.5, 57.9, 0.2], ["VBUS_EN4", 2, 30.5, 57.9, 30.5, 61.0, 0.2], ["VBUS_EN4", 2, 30.5, 61.0, 30.7289, 61.2292, 0.2], ["VO1", 2, 13.8, 44.4, 15.1, 44.4, 0.3], ["VO1", 2, 15.1, 44.4, 15.45, 44.75, 0.3], ["VO1", 2, 15.45, 44.75, 15.781, 45.5946, 0.3], ["VO1", 2, 15.781, 45.5946, 15.7109, 47.4174, 0.3], ["VO1", 2, 15.7109, 47.4174, 15.9, 47.9, 0.3], ["VO1", 2, 15.9, 47.9, 16.1, 48.1, 0.3], ["VO1", 2, 16.1, 48.1, 17.6, 48.1, 0.3], ["VO1", 2, 17.6, 48.1, 17.9, 47.8, 0.3], ["VO1", 1, 17.9, 47.8, 18.1, 47.6, 0.3], ["VO2", 1, 51.4, 87.25, 51.4, 87.05, 0.3], ["VO2", 1, 51.4, 87.05, 51.2, 86.85, 0.3], ["VO2", 1, 51.2, 86.85, 50.45, 86.85, 0.3], ["VO2", 1, 50.45, 86.85, 46.775, 83.175, 0.3], ["VO2", 2, 46.775, 83.175, 42.875, 79.275, 0.3], ["VO2", 2, 42.875, 79.275, 42.875, 78.625, 0.3], ["VO2", 2, 42.875, 78.625, 43.225, 78.275, 0.3], ["VO2", 2, 43.225, 78.275, 48.975, 78.25, 0.3], ["VO3", 1, 139.775, 87.25, 139.775, 87.05, 0.3], ["VO3", 1, 139.775, 87.05, 139.575, 86.85, 0.3], ["VO3", 1, 139.575, 86.85, 139.25, 86.85, 0.3], ["VO3", 1, 139.25, 86.85, 138.45, 86.05, 0.3], ["VO3", 1, 138.45, 86.05, 138.45, 84.6, 0.3], ["VO3", 1, 138.45, 84.6, 137.425, 83.575, 0.3], ["VO3", 2, 137.425, 83.575, 137.275, 83.425, 0.3], ["VO3", 2, 137.275, 83.425, 137.275, 82.425, 0.3], ["VO3", 2, 137.275, 82.425, 139.3, 80.4, 0.3], ["VO3", 2, 139.3, 80.4, 139.3, 79.95, 0.3], ["VO3", 2, 139.3, 79.95, 139.1539, 79.6135, 0.3], ["VO3", 2, 139.1539, 79.6135, 137.775, 78.325, 0.3], ["VO3", 1, 137.775, 78.325, 137.775, 78.25, 0.3], ["VO4", 1, 44.45, 37.4, 41.55, 34.5, 0.3], ["VO4", 1, 41.55, 34.5, 37.5, 34.5, 0.3], ["VO4", 1, 37.5, 34.5, 34.75, 31.75, 0.3], ["VO4", 1, 34.75, 31.75, 34.75, 29.5, 0.3], ["VO4", 1, 34.75, 29.5, 36.2, 28.05, 0.3], ["VO4", 1, 36.2, 28.05, 36.2, 24.25, 0.3], ["VO4", 1, 36.2, 24.25, 41.9541, 18.5014, 0.3]], "vias": [["$10N732", 135.1, 75.5], ["$10N732", 133.85, 76.8], ["$10N732", 127.85, 73.35], ["$10N732", 127.85, 69.25], ["$12N878", 43.85, 39.65], ["$12N878", 49.45, 34.4], ["$12N878", 51.35, 34.4], ["$12N878", 65.3, 39.65], ["$12N878", 64.0, 41.85], ["$12N878", 60.1, 42.15], ["$17N154", 95.1, 59.5], ["$17N154", 90.0, 59.5], ["$17N154", 74.4, 49.5], ["$2N653", 25.7, 18.65], ["$2N653", 9.65, 31.15], ["$2N653", 8.85, 32.3], ["$2N653", 10.4, 33.85], ["$2N653", 11.75, 32.75], ["$2N653", 15.85, 30.0], ["$2N676", 20.375, 47.15], ["$2N676", 21.275, 46.05], ["$2N676", 28.95, 43.95], ["$2N676", 28.95, 40.7], ["$2N676", 17.7, 39.15], ["$2N698", 18.9, 44.4], ["$2N707", 31.2, 36.7], ["$2N707", 29.7, 37.6], ["$2N707", 35.4, 25.8], ["$2N707", 37.2999, 26.5506], ["$2N719", 32.2, 38.9], ["$2N719", 34.5, 34.7], ["$2N732", 28.2, 56.8], ["$2N732", 28.2, 58.2], ["$8N687", 49.1, 81.1], ["$8N687", 46.4, 79.0], ["+3V3", 131.5, 80.7], ["+3V3", 123.25, 71.6], ["+3V3", 125.15, 71.6], ["+3V3", 131.9, 75.15], ["+3V3", 134.225, 75.125], ["+3V3", 137.675, 75.125], ["+3V3", 137.1, 75.5], ["+3V3", 143.35, 77.1], ["+5V", 86.3, 68.2], ["+5V", 91.9, 65.2], ["+5V", 93.4, 63.7], ["+5V", 101.0, 63.7], ["EDL_EN4", 61.05, 69.8], ["EDL_EN4", 61.75, 59.8], ["EFUSE_EN1", 29.7, 41.2], ["EFUSE_EN1", 96.7, 13.0], ["EFUSE_EN3", 141.5, 82.525], ["EFUSE_EN3", 138.6, 76.075], ["EFUSE_EN3", 134.75, 76.85], ["EFUSE_EN3", 135.7, 82.95], ["EFUSE_EN3", 137.7, 84.825], ["EFUSE_EN3", 139.975, 88.325], ["EFUSE_EN3", 138.55, 92.425], ["EFUSE_EN3", 145.6, 84.5], ["EFUSE_EN3", 145.575, 80.775], ["EFUSE_EN3", 145.7, 81.4], ["EFUSE_EN3", 145.7, 85.9], ["EFUSE_EN3", 132.8, 92.8], ["EFUSE_EN3", 123.0, 96.1], ["EFUSE_EN3", 102.0, 100.4], ["EFUSE_EN3", 99.0, 101.2], ["EFUSE_EN3", 89.5, 91.4], ["EFUSE_EN3", 90.2, 75.7], ["EFUSE_EN3", 93.9, 72.0], ["EFUSE_EN3", 95.4, 70.5], ["EFUSE_EN3", 97.6, 70.5], ["EFUSE_EN3", 103.5, 67.6], ["EFUSE_EN3", 113.6, 73.0], ["EFUSE_EN3", 131.0, 78.1], ["EFUSE_EN3", 131.0, 78.9], ["EFUSE_EN3", 133.2, 75.4], ["EFUSE_FLT1", 24.1, 43.5], ["EFUSE_FLT1", 41.7, 43.3], ["EFUSE_FLT1", 43.8, 41.2], ["EFUSE_FLT1", 57.5, 39.7], ["EFUSE_FLT1", 72.6, 43.1], ["EFUSE_FLT1", 74.7, 45.3], ["EFUSE_PG3", 104.4, 65.8], ["EFUSE_PG3", 95.1, 62.5], ["EFUSE_PG3", 91.8, 62.5], ["INA_ALERT", 133.25, 49.85], ["INA_ALERT", 138.45, 49.85], ["INA_ALERT", 147.95, 59.75], ["INA_ALERT", 143.75, 75.15], ["INA_ALERT", 148.0, 74.8], ["INA_ALERT", 145.0, 87.7], ["INA_ALERT", 129.5, 95.0], ["INA_ALERT", 103.7, 99.7], ["INA_ALERT", 100.4, 99.7], ["INA_ALERT", 99.0, 99.8], ["INA_ALERT", 68.8, 87.5], ["INA_ALERT", 62.1, 80.8], ["INA_ALERT", 59.7, 78.4], ["INA_ALERT", 58.6, 77.3], ["K3_PWR", 103.7, 97.6], ["K3_PWR", 102.3, 99.0], ["K3_PWR", 98.3, 100.5], ["K3_PWR", 97.3, 99.2], ["K3_PWR", 97.3, 93.5], ["K3_PWR", 88.9, 61.8], ["K3_PWR", 92.7, 58.8], ["K3_PWR", 96.5, 58.3], ["K3_PWR", 97.7, 52.2], ["K3_PWR", 97.6, 50.8], ["K4_VUP", 79.05, 34.25], ["K4_VUP", 80.55, 33.1], ["KEY_RCLK", 92.2, 66.7], ["KEY_RCLK", 93.1, 69.9], ["SDA", 84.325, 35.975], ["SDA", 85.325, 40.1], ["SDA", 81.325, 41.15], ["SDA", 80.0, 36.225], ["VBUS_EN4", 88.6, 25.5], ["VBUS_EN4", 99.8, 18.3], ["VBUS_EN4", 100.3, 14.2], ["VBUS_EN4", 31.4, 22.7], ["VBUS_EN4", 28.3, 44.8], ["VBUS_EN4", 29.3, 46.1], ["VBUS_EN4", 29.4, 56.8], ["VO1", 13.8, 44.4], ["VO1", 17.9, 47.8], ["VO2", 46.775, 83.175], ["VO2", 48.975, 78.25], ["VO3", 137.425, 83.575], ["VO3", 137.775, 78.325]]} \ No newline at end of file +{"segs": [["$1N236", 1, 5.4991, 101.1098, 4.7, 100.3, 0.3], ["$1N236", 1, 4.7, 100.3, 4.7, 94.8, 0.3], ["$1N236", 1, 4.7, 94.8, 3.4341, 93.4999, 0.3], ["+12V", 1, 6.4998, 101.1098, 5.9995, 101.1098, 0.3], ["+12V", 1, 5.9995, 101.1098, 6.2, 100.9, 0.3], ["+12V", 1, 6.2, 100.9, 6.2, 100.0, 0.3], ["+12V", 1, 6.2, 100.0, 8.2, 97.9, 0.3], ["+12V", 1, 8.2, 97.9, 8.2, 94.9, 0.3], ["+12V", 1, 8.2, 94.9, 9.5656, 93.4999, 0.3], ["+3V3", 1, 95.3, 74.5, 95.4, 72.8, 0.279], ["EFUSE_FLT2", 1, 46.1, 82.7, 46.1, 83.55, 0.2], ["EFUSE_FLT2", 1, 46.1, 83.55, 46.6, 84.05, 0.2], ["EFUSE_FLT2", 2, 46.6, 84.05, 48.2, 85.65, 0.2], ["EFUSE_FLT2", 2, 48.2, 85.65, 55.25, 85.65, 0.2], ["EFUSE_FLT2", 2, 55.25, 85.65, 56.25, 84.65, 0.2], ["EFUSE_FLT2", 2, 56.25, 84.65, 67.8, 84.65, 0.2], ["EFUSE_FLT2", 2, 67.8, 84.65, 80.75, 71.7, 0.2], ["EFUSE_FLT2", 2, 80.75, 71.7, 80.75, 52.35, 0.2], ["EFUSE_FLT2", 2, 80.75, 52.35, 80.55, 52.15, 0.2], ["EFUSE_FLT2", 2, 80.55, 52.15, 80.55, 51.45, 0.2], ["EFUSE_FLT2", 2, 80.55, 51.45, 80.85, 51.15, 0.2], ["EFUSE_FLT2", 2, 80.85, 51.15, 81.35, 51.15, 0.2], ["EFUSE_FLT2", 2, 81.35, 51.15, 84.4, 48.1, 0.2], ["EFUSE_FLT2", 2, 84.4, 48.1, 84.4, 45.8, 0.2], ["EFUSE_FLT2", 1, 84.4, 45.8, 83.15, 44.55, 0.2], ["EFUSE_FLT2", 1, 83.15, 44.55, 80.9, 44.55, 0.2], ["EFUSE_FLT2", 1, 80.9, 44.55, 80.5, 44.15, 0.2], ["EFUSE_FLT2", 2, 80.5, 44.15, 79.2, 42.85, 0.2], ["EFUSE_FLT2", 1, 79.2, 42.85, 77.2, 42.8, 0.2], ["EFUSE_FLT2", 1, 77.2, 42.8, 76.9, 42.5, 0.2], ["EFUSE_FLT2", 1, 76.9, 42.5, 76.5, 42.5, 0.2], ["EFUSE_FLT2", 1, 76.5, 42.5, 75.9982, 42.722, 0.2], ["EFUSE_FLT2", 1, 75.9982, 42.722, 75.7, 43.05, 0.2], ["EFUSE_FLT2", 2, 75.7, 43.05, 75.2, 43.55, 0.2], ["EFUSE_FLT2", 2, 75.2, 43.55, 75.2, 44.25, 0.2], ["EFUSE_FLT2", 2, 75.2, 44.25, 75.0, 44.45, 0.2], ["EFUSE_FLT2", 1, 75.0, 44.45, 75.5, 45.4, 0.2], ["KEY_OE#", 1, 84.8259, 27.0942, 84.8, 29.9, 0.2], ["KEY_OE#", 2, 84.8, 29.9, 87.9, 33.0, 0.2], ["KEY_OE#", 2, 87.9, 33.0, 87.9, 40.1, 0.2], ["KEY_OE#", 1, 87.9, 40.1, 89.1, 41.3, 0.2], ["KEY_OE#", 1, 89.1, 41.3, 89.2, 42.8, 0.2], ["KEY_OE#", 2, 89.2, 42.8, 89.3, 57.6, 0.2], ["KEY_OE#", 2, 89.3, 57.6, 90.3, 58.6, 0.2], ["KEY_OE#", 1, 90.3, 58.6, 90.7, 59.0, 0.2], ["KEY_OE#", 1, 90.7, 59.0, 90.7, 61.8, 0.2], ["KEY_OE#", 2, 90.7, 61.8, 90.7, 63.7, 0.2], ["KEY_OE#", 1, 90.7, 63.7, 90.4, 64.0, 0.2], ["KEY_OE#", 1, 90.4, 64.0, 90.4, 71.7, 0.2], ["KEY_OE#", 1, 90.4, 71.7, 94.7, 76.0, 0.2], ["KEY_OE#", 1, 94.7, 76.0, 97.4, 76.0, 0.2], ["KEY_OE#", 1, 97.4, 76.0, 98.2402, 76.3664, 0.2], ["KEY_OE#", 1, 98.2402, 76.3664, 100.5, 78.8, 0.2], ["KEY_OE#", 2, 100.5, 78.8, 104.3, 78.8, 0.2], ["KEY_OE#", 2, 104.3, 78.8, 105.8, 77.3, 0.2], ["KEY_OE#", 2, 105.8, 77.3, 106.2, 77.3, 0.2], ["KEY_OE#", 2, 106.2, 77.3, 111.1, 72.4, 0.2], ["KEY_OE#", 2, 111.1, 72.4, 111.1, 71.6, 0.2], ["KEY_OE#", 1, 111.1, 71.6, 113.6341, 69.2407, 0.2], ["KEY_OE#", 1, 113.6341, 69.2407, 114.0, 68.4, 0.2], ["KEY_OE#", 1, 114.0, 68.4, 114.0, 66.4, 0.2], ["KEY_OE#", 2, 114.0, 66.4, 116.5708, 63.7692, 0.2], ["KEY_RCLK", 1, 92.4459, 27.0942, 92.45, 29.9, 0.2], ["KEY_RCLK", 1, 92.45, 29.9, 93.9, 31.35, 0.2], ["KEY_RCLK", 2, 93.9, 31.35, 93.9, 34.35, 0.2], ["KEY_RCLK", 1, 93.9, 34.35, 95.2, 35.65, 0.2], ["KEY_RCLK", 1, 95.2, 35.65, 95.2, 36.2, 0.2], ["KEY_RCLK", 2, 95.2, 36.2, 98.35, 39.35, 0.2], ["KEY_RCLK", 2, 98.35, 39.35, 98.35, 48.75, 0.2], ["KEY_RCLK", 1, 98.35, 48.75, 98.9, 49.3, 0.2], ["KEY_RCLK", 1, 98.9, 49.3, 98.9, 50.2, 0.2], ["KEY_RCLK", 1, 98.9, 50.2, 99.55, 50.85, 0.2], ["KEY_RCLK", 2, 99.55, 50.85, 99.55, 54.9, 0.2], ["KEY_RCLK", 2, 99.55, 54.9, 102.0232, 57.3732, 0.2], ["KEY_RCLK", 2, 102.0232, 57.3732, 102.4499, 57.544, 0.2], ["KEY_RCLK", 2, 102.4499, 57.544, 108.45, 57.4, 0.2], ["KEY_RCLK", 1, 108.45, 57.4, 109.55, 58.5, 0.2], ["KEY_RCLK", 1, 109.55, 58.5, 111.15, 58.5, 0.2], ["KEY_RCLK", 2, 111.15, 58.5, 112.75, 60.1, 0.2], ["KEY_RCLK", 2, 112.75, 60.1, 112.75, 62.45, 0.2], ["KEY_RCLK", 2, 112.75, 62.45, 114.0308, 63.7692, 0.2], ["KEY_SER", 1, 87.3659, 27.0942, 87.85, 27.6, 0.2], ["KEY_SER", 1, 87.85, 27.6, 87.8944, 28.0444, 0.2], ["KEY_SER", 1, 87.8944, 28.0444, 87.95, 28.125, 0.2], ["KEY_SER", 1, 87.95, 28.125, 88.0, 28.2059, 0.2], ["KEY_SER", 1, 88.0, 28.2059, 88.0, 32.15, 0.2], ["KEY_SER", 2, 88.0, 32.15, 88.35, 32.5, 0.2], ["KEY_SER", 2, 88.35, 32.5, 88.35, 39.3, 0.2], ["KEY_SER", 2, 88.35, 39.3, 88.55, 39.5, 0.2], ["KEY_SER", 1, 88.55, 39.5, 91.65, 42.6, 0.2], ["KEY_SER", 1, 91.65, 42.6, 91.65, 42.85, 0.2], ["KEY_SER", 2, 91.65, 42.85, 91.65, 46.55, 0.2], ["KEY_SER", 2, 91.65, 46.55, 97.4, 52.3, 0.2], ["KEY_SER", 1, 97.4, 52.3, 97.9, 52.8, 0.2], ["KEY_SER", 1, 97.9, 52.8, 101.95, 52.8, 0.2], ["KEY_SER", 1, 101.95, 52.8, 103.15, 54.0, 0.2], ["KEY_SER", 2, 103.15, 54.0, 105.7, 56.55, 0.2], ["KEY_SER", 2, 105.7, 56.55, 108.6, 56.55, 0.2], ["KEY_SER", 1, 108.6, 56.55, 109.9, 57.85, 0.2], ["KEY_SER", 2, 109.9, 57.85, 107.9893, 59.6738, 0.2], ["KEY_SER", 2, 107.9893, 59.6738, 107.7, 60.35, 0.2], ["KEY_SER", 2, 107.7, 60.35, 107.7, 62.5, 0.2], ["KEY_SER", 2, 107.7, 62.5, 108.9508, 63.7692, 0.2], ["KEY_SRCLK", 1, 88.6359, 27.0942, 88.65, 30.9, 0.2], ["KEY_SRCLK", 1, 88.65, 30.9, 94.55, 36.8, 0.2], ["KEY_SRCLK", 2, 94.55, 36.8, 94.55, 48.45, 0.2], ["KEY_SRCLK", 2, 94.55, 48.45, 98.25, 52.15, 0.2], ["KEY_SRCLK", 1, 98.25, 52.15, 102.25, 52.15, 0.2], ["KEY_SRCLK", 1, 102.25, 52.15, 109.35, 59.25, 0.2], ["KEY_SRCLK", 2, 109.35, 59.25, 110.2, 60.1, 0.2], ["KEY_SRCLK", 2, 110.2, 60.1, 110.2, 62.45, 0.2], ["KEY_SRCLK", 2, 110.2, 62.45, 111.4908, 63.7692, 0.2], ["VBUS_EN2", 2, 118.25, 62.9, 117.85, 62.5, 0.2], ["VBUS_EN2", 2, 117.85, 62.5, 117.85, 56.45, 0.2], ["VBUS_EN2", 2, 117.85, 56.45, 113.95, 52.55, 0.2], ["VBUS_EN2", 2, 113.95, 52.55, 104.85, 52.55, 0.2], ["VBUS_EN2", 2, 104.85, 52.55, 103.15, 50.85, 0.2], ["VBUS_EN2", 1, 103.15, 50.85, 100.05, 47.75, 0.2], ["VBUS_EN2", 1, 100.05, 47.75, 99.6, 47.75, 0.2], ["VBUS_EN2", 2, 99.6, 47.75, 99.6, 38.0, 0.2], ["VBUS_EN2", 2, 99.6, 38.0, 96.5, 34.9, 0.2], ["VBUS_EN2", 1, 96.5, 34.9, 91.65, 30.05, 0.2], ["VBUS_EN2", 1, 91.65, 30.05, 91.65, 27.8788, 0.2], ["VBUS_EN2", 1, 91.65, 27.8788, 91.4129, 27.3221, 0.2], ["VBUS_EN2", 1, 91.4129, 27.3221, 91.1759, 27.0942, 0.2], ["VBUS_EN5", 1, 112.75, 62.4, 112.75, 58.8, 0.2], ["VBUS_EN5", 1, 112.75, 58.8, 117.55, 54.0, 0.2], ["VBUS_EN5", 2, 117.55, 54.0, 117.95, 53.6, 0.2], ["VBUS_EN5", 2, 117.95, 53.6, 117.95, 41.75, 0.2], ["VBUS_EN5", 1, 117.95, 41.75, 119.8, 39.85, 0.2], ["VBUS_EN5", 2, 119.8, 39.85, 100.8, 20.85, 0.2], ["VBUS_EN5", 2, 100.8, 20.85, 97.05, 20.85, 0.2], ["VBUS_EN5", 2, 97.05, 20.85, 96.85, 20.65, 0.2], ["VBUS_EN5", 1, 96.85, 20.65, 96.7512, 20.734, 0.2]], "vias": [["EFUSE_FLT2", 46.6, 84.05], ["EFUSE_FLT2", 84.4, 45.8], ["EFUSE_FLT2", 80.5, 44.15], ["EFUSE_FLT2", 79.2, 42.85], ["EFUSE_FLT2", 75.7, 43.05], ["EFUSE_FLT2", 75.0, 44.45], ["KEY_OE#", 84.8, 29.9], ["KEY_OE#", 87.9, 40.1], ["KEY_OE#", 89.2, 42.8], ["KEY_OE#", 90.3, 58.6], ["KEY_OE#", 90.7, 61.8], ["KEY_OE#", 90.7, 63.7], ["KEY_OE#", 100.5, 78.8], ["KEY_OE#", 111.1, 71.6], ["KEY_OE#", 114.0, 66.4], ["KEY_RCLK", 93.9, 31.35], ["KEY_RCLK", 93.9, 34.35], ["KEY_RCLK", 95.2, 36.2], ["KEY_RCLK", 98.35, 48.75], ["KEY_RCLK", 99.55, 50.85], ["KEY_RCLK", 108.45, 57.4], ["KEY_RCLK", 111.15, 58.5], ["KEY_SER", 88.0, 32.15], ["KEY_SER", 88.55, 39.5], ["KEY_SER", 91.65, 42.85], ["KEY_SER", 97.4, 52.3], ["KEY_SER", 103.15, 54.0], ["KEY_SER", 108.6, 56.55], ["KEY_SER", 109.9, 57.85], ["KEY_SRCLK", 94.55, 36.8], ["KEY_SRCLK", 98.25, 52.15], ["KEY_SRCLK", 109.35, 59.25], ["VBUS_EN2", 103.15, 50.85], ["VBUS_EN2", 99.6, 47.75], ["VBUS_EN2", 96.5, 34.9], ["VBUS_EN5", 117.55, 54.0], ["VBUS_EN5", 117.95, 41.75], ["VBUS_EN5", 119.8, 39.85], ["VBUS_EN5", 96.85, 20.65]]} \ No newline at end of file diff --git a/.claude/_pcb2_route_geom.json b/.claude/_pcb2_route_geom.json index 6c6ec70..726d8c8 100644 --- a/.claude/_pcb2_route_geom.json +++ b/.claude/_pcb2_route_geom.json @@ -1 +1 @@ -{"pads": [["", "MH1", "GND", 12, 314.96, 314.96, 0, ["ELLIPSE", 236.2, 236.2]], ["", "MH2", "GND", 12, 8346.46, 314.96, 0, ["ELLIPSE", 236.2, 236.2]], ["", "MH3", "GND", 12, 275.59, 2362.2, 0, ["ELLIPSE", 236.2, 236.2]], ["", "MH4", "GND", 12, 8385.83, 1771.65, 0, ["ELLIPSE", 236.2, 236.2]], ["", "MH5", "GND", 12, 3015.75, 3129.92, 0, ["ELLIPSE", 236.2, 236.2]], ["", "MH6", "GND", 12, 5830.71, 3129.92, 0, ["ELLIPSE", 236.2, 236.2]], ["", "P1H1", "", 12, 704.33, 3360.63, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H2", "", 12, 2735.83, 3522.05, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H3", "", 12, 401.18, 3699.21, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H4", "", 12, 393.31000000000006, 3876.38, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H5", "", 12, 2735.83, 3962.99, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H6", "", 12, 2680.71, 4600.79, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P1H7", "", 12, 1161.02, 4880.31, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H1", "", 12, 3519.29, 3360.63, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H2", "", 12, 5550.789999999999, 3522.05, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H3", "", 12, 3216.14, 3699.21, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H4", "", 12, 3208.27, 3876.38, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H5", "", 12, 5550.789999999999, 3962.99, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H6", "", 12, 5495.67, 4600.79, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P2H7", "", 12, 3975.98, 4880.31, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H1", "", 12, 6334.25, 3360.63, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H2", "", 12, 8365.75, 3522.05, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H3", "", 12, 6031.1, 3699.21, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H4", "", 12, 6023.23, 3876.38, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H5", "", 12, 8365.75, 3962.99, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H6", "", 12, 8310.63, 4600.79, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P3H7", "", 12, 6790.94, 4880.31, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H1", "", 12, 3738.19, 1960.63, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H2", "", 12, 1706.69, 1799.21, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H3", "", 12, 4041.34, 1622.0499999999997, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H4", "", 12, 4049.21, 1444.88, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H5", "", 12, 1706.69, 1358.27, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H6", "", 12, 1761.81, 720.47, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P4H7", "", 12, 3281.5, 440.94, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H1", "", 12, 6553.15, 1960.63, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H2", "", 12, 4521.65, 1799.21, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H3", "", 12, 6856.3, 1622.0499999999997, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H4", "", 12, 6864.17, 1444.88, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H5", "", 12, 4521.65, 1358.27, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H6", "", 12, 4576.77, 720.47, 0, ["ELLIPSE", 98.4, 98.4]], ["", "P5H7", "", 12, 6096.459999999999, 440.94, 0, ["ELLIPSE", 98.4, 98.4]], ["C701", "2", "+5V", 2, 1617.7199999999998, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C701", "1", "GND", 2, 1696.46, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C702", "2", "+5V", 2, 4432.68, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C702", "1", "GND", 2, 4511.42, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C703", "2", "+5V", 2, 7247.64, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C703", "1", "GND", 2, 7326.38, 4002.3599999999997, 3.141592653589793, ["RECT", 55.5, 53.1, 0]], ["C704", "2", "+5V", 2, 2824.8, 1318.9, 0, ["RECT", 55.5, 53.1, 0]], ["C704", "1", "GND", 2, 2746.06, 1318.9, 0, ["RECT", 55.5, 53.1, 0]], ["C705", "2", "+5V", 2, 5639.76, 1318.9, 0, ["RECT", 55.5, 53.1, 0]], ["C705", "1", "GND", 2, 5561.0199999999995, 1318.9, 0, ["RECT", 55.5, 53.1, 0]], ["C711", "2", "GND", 2, 1305.9, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C711", "1", "VBUS1", 2, 1338.98, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C712", "2", "GND", 2, 4120.86, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C712", "1", "VBUS2", 2, 4153.94, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C713", "2", "GND", 2, 6935.82, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C713", "1", "VBUS3", 2, 6968.9, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C714", "2", "GND", 2, 3136.62, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C714", "1", "VBUS4", 2, 3103.54, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C715", "2", "GND", 2, 5951.58, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C715", "1", "VBUS5", 2, 5918.5, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C721", "2", "GND", 2, 1207.48, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C721", "1", "$20N304", 2, 1240.56, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C722", "2", "GND", 2, 4022.4400000000005, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C722", "1", "$20N314", 2, 4055.5200000000004, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C723", "2", "GND", 2, 6837.4, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C723", "1", "$20N324", 2, 6870.48, 4002.3599999999997, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C724", "2", "GND", 2, 3235.04, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C724", "1", "$20N334", 2, 3201.96, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C725", "2", "GND", 2, 6050, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C725", "1", "$20N344", 2, 6016.92, 1318.9, 0, ["RECT", 19.7, 21.3, 0]], ["C740", "2", "GND", 2, 3637, 2348.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C740", "1", "XTAL1", 2, 3670.08, 2348.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C741", "2", "GND", 2, 3814.96, 2176.37, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C741", "1", "XTAL2", 2, 3814.96, 2209.45, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C742", "2", "GND", 2, 3966.54, 2941.74, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C742", "1", "VDD18", 2, 3966.54, 2908.66, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C743", "2", "GND", 2, 3832.68, 2412.59, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C743", "1", "VDD18PLL", 2, 3832.68, 2445.67, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C744", "2", "GND", 2, 3761.81, 2412.59, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C744", "1", "+3V3_HUB", 2, 3761.81, 2445.67, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C745", "2", "GND", 2, 3937.01, 2307.08, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C745", "1", "+3V3_HUB", 2, 3937.01, 2340.16, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C746", "2", "GND", 2, 4080.71, 2412.59, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C746", "1", "+3V3_HUB", 2, 4080.71, 2445.67, -1.570796326794897, ["RECT", 19.7, 21.3, 0]], ["C747", "2", "GND", 2, 3472.4400000000005, 2831.5, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C747", "1", "+3V3_HUB", 2, 3472.4400000000005, 2798.42, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C748", "2", "GND", 2, 3641.73, 2819.69, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C748", "1", "+3V3_HUB", 2, 3641.73, 2786.61, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C749", "2", "GND", 2, 3907.48, 2941.74, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C749", "1", "+3V3_HUB", 2, 3907.48, 2908.66, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C750", "2", "GND", 2, 4201.58, 2498.03, 0, ["RECT", 19.7, 21.3, 0]], ["C750", "1", "+3V3_HUB", 2, 4168.5, 2498.03, 0, ["RECT", 19.7, 21.3, 0]], ["C751", "2", "GND", 2, 3818.9000000000005, 2925.2, 0, ["RECT", 55.5, 53.1, 0]], ["C751", "1", "+3V3_HUB", 2, 3740.1600000000003, 2925.2, 0, ["RECT", 55.5, 53.1, 0]], ["J23", "B8", "", 2, 8361.885, 2509.84, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A5", "$16N222", 2, 8361.885, 2490.1499999999996, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B7", "UP_DM", 2, 8361.885, 2470.47, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A6", "UP_DP", 2, 8361.885, 2450.78, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A7", "UP_DM", 2, 8361.885, 2431.1, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B6", "UP_DP", 2, 8361.885, 2411.41, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A8", "", 2, 8361.885, 2391.7400000000002, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B5", "$16N224", 2, 8361.885, 2372.04, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A1B12", "GND", 2, 8361.885, 2566.92, -1.570796326794897, ["POLYGON", [8387.473, 2555.112, "L", 8336.291, 2555.112, 8336.291, 2566.923, 8336.297, 2566.923, 8336.297, 2578.733, 8387.479, 2578.733, 8387.479, 2566.922, 8387.473, 2566.922, 8387.473, 2555.112]]], ["J23", "B1A12", "GND", 2, 8361.885, 2314.95, -1.570796326794897, ["POLYGON", [8336.291, 2326.767, "L", 8387.471, 2326.767, 8387.471, 2314.956, 8387.471, 2314.955, 8387.471, 2303.144, 8336.291, 2303.144, 8336.291, 2314.955, 8336.291, 2314.956, 8336.291, 2326.767]]], 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["RECT", 7.1, 18.9, 0]], ["J71", "2", "GND", 2, 936.6143, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "3", "", 2, 922.8348000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "4", "USB1_DMJ", 2, 922.8348000000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "5", "", 2, 909.0553, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "6", "USB1_DPJ", 2, 909.0553, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "7", "", 2, 895.2756999999999, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "8", "GND", 2, 895.2756999999999, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "9", "", 2, 881.4962, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "10", "", 2, 881.4962, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "11", "", 2, 867.7167, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "12", "GND", 2, 867.7167, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "13", "", 2, 853.9372000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "14", "THERM_1", 2, 853.9372000000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "15", "", 2, 840.1576, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "16", "GND", 2, 840.1576, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "17", "", 2, 826.3781, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "18", "", 2, 826.3781, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "19", "GND", 2, 812.5986, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "20", "", 2, 812.5986, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "21", "", 2, 798.8191, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "22", "CC1_1", 2, 798.8191, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "23", "GND", 2, 785.0395000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "24", "GND", 2, 785.0395000000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "25", "", 2, 771.26, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "26", "", 2, 771.26, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "27", "", 2, 757.4805000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "28", "", 2, 757.4805000000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "29", "GND", 2, 743.7009, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "30", "", 2, 743.7009, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "31", "", 2, 729.9214000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "32", "", 2, 729.9214000000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "33", "", 2, 716.1419000000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "34", "", 2, 716.1419000000001, 3606.2977, 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6483.857200000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "15", "", 2, 6470.0776000000005, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "16", "GND", 2, 6470.0776000000005, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "17", "", 2, 6456.2981, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "18", "", 2, 6456.2981, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "19", "GND", 2, 6442.518600000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "20", "", 2, 6442.518600000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "21", "", 2, 6428.739100000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "22", "CC1_3", 2, 6428.739100000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "23", "GND", 2, 6414.959500000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "24", "GND", 2, 6414.959500000001, 3606.2977, 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3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "47", "GND", 2, 6249.605200000001, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "48", "", 2, 6249.605200000001, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "49", "", 2, 6235.8257, 3689.7623, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "50", "", 2, 6235.8257, 3606.2977, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J73", "51", "VBUS3", 2, 6638.5815999999995, 3648.0299999999997, 3.141592653589793, ["RECT", 19.3, 29.9, 0]], ["J73", "52", "GND", 2, 6163.778400000001, 3648.0299999999997, 3.141592653589793, ["RECT", 19.3, 29.9, 0]], ["J74", "1", "GND", 2, 3505.9057000000003, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "2", "GND", 2, 3505.9057000000003, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "3", "", 2, 3519.6852, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "4", "USB4_DMJ", 2, 3519.6852, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "5", "", 2, 3533.4647, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "6", "USB4_DPJ", 2, 3533.4647, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "7", "", 2, 3547.2443000000003, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "8", "GND", 2, 3547.2443000000003, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "9", "", 2, 3561.0238000000004, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "10", "", 2, 3561.0238000000004, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "11", "", 2, 3574.8033000000005, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "12", "GND", 2, 3574.8033000000005, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "13", "", 2, 3588.5828, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "14", "THERM_4", 2, 3588.5828, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "15", "", 2, 3602.3624, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "16", "GND", 2, 3602.3624, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "17", "", 2, 3616.1419, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "18", "", 2, 3616.1419, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "19", "GND", 2, 3629.9214, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "20", "", 2, 3629.9214, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "21", "", 2, 3643.7009000000007, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "22", "CC1_4", 2, 3643.7009, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "23", "GND", 2, 3657.4805000000006, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "24", "GND", 2, 3657.4805000000006, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "25", "", 2, 3671.26, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "26", "", 2, 3671.26, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "27", "", 2, 3685.0395000000003, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "28", "", 2, 3685.0395000000003, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J74", "29", "GND", 2, 3698.8191000000006, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], 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["J75", "38", "", 2, 6568.897200000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "39", "", 2, 6582.676700000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "40", "", 2, 6582.676700000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "41", "GND", 2, 6596.456200000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "42", "", 2, 6596.456200000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "43", "", 2, 6610.235700000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "44", "", 2, 6610.235700000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "45", "", 2, 6624.015300000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "46", "", 2, 6624.015300000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "47", "GND", 2, 6637.794800000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "48", "", 2, 6637.794800000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "49", "", 2, 6651.574300000001, 1631.4977000000001, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "50", "", 2, 6651.574300000001, 1714.9623, 0, ["RECT", 7.1, 18.9, 0]], ["J75", "51", "VBUS5", 2, 6248.818400000001, 1673.23, 0, ["RECT", 19.3, 29.9, 0]], ["J75", "52", "GND", 2, 6723.6216, 1673.23, 0, ["RECT", 19.3, 29.9, 0]], ["R701", "2", "GND", 2, 1108.55, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R701", "1", "VBUS_EN1", 2, 1142.6299999999999, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R702", "2", "GND", 2, 3923.51, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R702", "1", "VBUS_EN2", 2, 3957.59, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R703", "2", "GND", 2, 6738.470000000001, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R703", "1", "VBUS_EN3", 2, 6772.55, 4002.3599999999997, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R704", "2", "GND", 2, 3333.97, 1318.9, 0, ["RECT", 22.3, 21.3, 0]], ["R704", "1", "VBUS_EN4", 2, 3299.89, 1318.9, 0, ["RECT", 22.3, 21.3, 0]], ["R705", "2", "GND", 2, 6148.93, 1318.9, 0, ["RECT", 22.3, 21.3, 0]], ["R705", "1", "VBUS_EN5", 2, 6114.850000000001, 1318.9, 0, ["RECT", 22.3, 21.3, 0]], ["R708", "2", "GND", 2, 3801.18, 2412.09, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R708", "1", "RBIAS", 2, 3801.18, 2446.17, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R709", "2", "VBUS_DET", 2, 4168, 2592.52, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R709", "1", "VBUS_UP", 2, 4202.08, 2592.52, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R710", "2", "GND", 2, 4168, 2545.28, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R710", "1", "VBUS_DET", 2, 4202.08, 2545.28, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R711", "2", "GND", 2, 4304.44, 2663.39, 0, ["RECT", 22.3, 21.3, 0]], ["R711", "1", "CFGSEL0", 2, 4270.36, 2663.39, 0, ["RECT", 22.3, 21.3, 0]], ["R712", "2", "GND", 2, 4202.08, 2639.76, 0, ["RECT", 22.3, 21.3, 0]], ["R712", "1", "CFGSEL1", 2, 4168, 2639.76, 0, ["RECT", 22.3, 21.3, 0]], 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"1", "NONREM1", 2, 4168, 2687.01, 0, ["RECT", 22.3, 21.3, 0]], ["R720", "2", "GND", 2, 4304.44, 2568.8999999999996, 0, ["RECT", 22.3, 21.3, 0]], ["R720", "1", "NONREM0", 2, 4270.36, 2568.8999999999996, 0, ["RECT", 22.3, 21.3, 0]], ["R721", "2", "UP_VBUS_DET", 2, 3132.57, 2421.26, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R721", "1", "VBUS_UP", 2, 3166.65, 2421.26, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R722", "2", "GND", 2, 3053.83, 2421.26, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R722", "1", "UP_VBUS_DET", 2, 3087.91, 2421.26, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R761", "2", "VBUS1", 2, 764.73, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R761", "1", "CC1_1", 2, 798.8099999999998, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R762", "2", "VBUS2", 2, 3579.69, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R762", "1", "CC1_2", 2, 3613.77, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R763", "2", "VBUS3", 2, 6394.650000000001, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R763", "1", "CC1_3", 2, 6428.73, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R764", "2", "VBUS4", 2, 3677.79, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R764", "1", "CC1_4", 2, 3643.71, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R765", "2", "VBUS5", 2, 6492.75, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R765", "1", "CC1_5", 2, 6458.670000000001, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R771", "2", "GND", 2, 663.6700000000001, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R771", "1", "THERM_1", 2, 697.7499999999999, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R772", "2", "GND", 2, 3478.63, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R772", "1", "THERM_2", 2, 3512.71, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R773", "2", "GND", 2, 6293.59, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R773", "1", "THERM_3", 2, 6327.669999999999, 3529.92, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R774", "2", "GND", 2, 3778.85, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R774", "1", "THERM_4", 2, 3744.7699999999995, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R775", "2", "GND", 2, 6593.8099999999995, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["R775", "1", "THERM_5", 2, 6559.7300000000005, 1791.34, 0, ["RECT", 22.3, 21.3, 0]], ["U24", "3", "VBUS_EN1", 2, 1426.7700000000002, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U24", "2", "GND", 2, 1426.7700000000002, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U24", "1", "+5V", 2, 1426.7700000000002, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U24", "6", "VBUS1", 2, 1533.0700000000002, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U24", "5", "VBUS1", 2, 1533.0700000000002, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U24", "4", "$20N304", 2, 1533.0700000000002, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "3", "VBUS_EN2", 2, 4241.73, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "2", "GND", 2, 4241.73, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "1", "+5V", 2, 4241.73, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "6", "VBUS2", 2, 4348.03, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "5", "VBUS2", 2, 4348.03, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U25", "4", "$20N314", 2, 4348.03, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "3", "VBUS_EN3", 2, 7056.69, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "2", "GND", 2, 7056.69, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "1", "+5V", 2, 7056.69, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "6", "VBUS3", 2, 7162.990000000001, 3964.96, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "5", "VBUS3", 2, 7162.990000000001, 4002.3599999999997, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U26", "4", "$20N324", 2, 7162.990000000001, 4039.76, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U27", "3", "VBUS_EN4", 2, 3015.75, 1281.5, 0, ["RECT", 43.3, 23.6, 0]], ["U27", "2", "GND", 2, 3015.75, 1318.9, 0, ["RECT", 43.3, 23.6, 0]], ["U27", "1", "+5V", 2, 3015.75, 1356.3000000000002, 0, ["RECT", 43.3, 23.6, 0]], ["U27", "6", "VBUS4", 2, 2909.45, 1356.3000000000002, 0, ["RECT", 43.3, 23.6, 0]], ["U27", "5", "VBUS4", 2, 2909.45, 1318.9, 0, ["RECT", 43.3, 23.6, 0]], ["U27", "4", "$20N334", 2, 2909.45, 1281.5, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "3", "VBUS_EN5", 2, 5830.710000000001, 1281.5, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "2", "GND", 2, 5830.710000000001, 1318.9, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "1", "+5V", 2, 5830.710000000001, 1356.3000000000002, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "6", "VBUS5", 2, 5724.41, 1356.3000000000002, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "5", "VBUS5", 2, 5724.41, 1318.9, 0, ["RECT", 43.3, 23.6, 0]], ["U28", "4", "$20N344", 2, 5724.41, 1281.5, 0, ["RECT", 43.3, 23.6, 0]], ["U32", "16", "", 2, 3761.8150000000005, 2824.803, 0, ["OVAL", 33.5, 11.8]], ["U32", "15", "", 2, 3761.8150000000005, 2805.1229999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "14", "", 2, 3761.8150000000005, 2785.433, 0, ["OVAL", 33.5, 11.8]], ["U32", "13", "GND", 2, 3761.8150000000005, 2765.7529999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "12", "USB5_DP", 2, 3761.8150000000005, 2746.0629999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "11", "USB5_DM", 2, 3761.8150000000005, 2726.383, 0, ["OVAL", 33.5, 11.8]], ["U32", "10", "+3V3_HUB", 2, 3761.8150000000005, 2706.6929999999998, 0, ["OVAL", 33.5, 11.8]], ["U32", "9", "USB4_DP", 2, 3761.8150000000005, 2687.013, 0, ["OVAL", 33.5, 11.8]], ["U32", "8", "USB4_DM", 2, 3761.8150000000005, 2667.3230000000003, 0, ["OVAL", 33.5, 11.8]], ["U32", "7", "USB3_DP", 2, 3761.8150000000005, 2647.643, 0, ["OVAL", 33.5, 11.8]], ["U32", "6", "USB3_DM", 2, 3761.8150000000005, 2627.953, 0, ["OVAL", 33.5, 11.8]], ["U32", "5", "+3V3_HUB", 2, 3761.8150000000005, 2608.2729999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "4", "USB2_DP", 2, 3761.8150000000005, 2588.5829999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "3", "USB2_DM", 2, 3761.8150000000005, 2568.903, 0, ["OVAL", 33.5, 11.8]], ["U32", "2", "USB1_DP", 2, 3761.8150000000005, 2549.2129999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "1", "USB1_DM", 2, 3761.8150000000005, 2529.533, 0, ["OVAL", 33.5, 11.8]], ["U32", "17", "", 2, 3789.375, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "18", "", 2, 3809.0550000000003, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "19", "GND", 2, 3828.745, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "20", "", 2, 3848.425, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "21", "", 2, 3868.1150000000002, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "22", "", 2, 3887.7950000000005, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "23", "", 2, 3907.4850000000006, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "24", "+3V3_HUB", 2, 3927.165, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "25", "VDD18", 2, 3946.8550000000005, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "26", "", 2, 3966.535, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "27", "", 2, 3986.225, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "28", "", 2, 4005.905, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "29", "", 2, 4025.5950000000003, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "30", "", 2, 4045.2750000000005, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "31", "", 2, 4064.965, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "32", "", 2, 4084.6450000000004, 2852.363, 0, ["OVAL", 11.8, 33.5]], ["U32", "33", "", 2, 4112.205, 2824.8129999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "34", "", 2, 4112.205, 2805.1229999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "35", "", 2, 4112.205, 2785.4429999999998, 0, ["OVAL", 33.5, 11.8]], ["U32", "36", "", 2, 4112.205, 2765.7529999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "37", "", 2, 4112.205, 2746.0730000000003, 0, ["OVAL", 33.5, 11.8]], ["U32", "38", "", 2, 4112.205, 2726.383, 0, ["OVAL", 33.5, 11.8]], ["U32", "39", "", 2, 4112.205, 2706.703, 0, ["OVAL", 33.5, 11.8]], ["U32", "40", "NONREM1", 2, 4112.205, 2687.013, 0, ["OVAL", 33.5, 11.8]], ["U32", "41", "CFGSEL0", 2, 4112.205, 2667.3329999999996, 0, ["OVAL", 33.5, 11.8]], ["U32", "42", "CFGSEL1", 2, 4112.205, 2647.643, 0, ["OVAL", 33.5, 11.8]], ["U32", "43", "HUB_RST", 2, 4112.205, 2627.9629999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "44", "VBUS_DET", 2, 4112.205, 2608.2729999999997, 0, ["OVAL", 33.5, 11.8]], ["U32", "45", "NONREM0", 2, 4112.205, 2588.593, 0, ["OVAL", 33.5, 11.8]], ["U32", "46", "+3V3_HUB", 2, 4112.205, 2568.903, 0, ["OVAL", 33.5, 11.8]], ["U32", "47", "", 2, 4112.205, 2549.223, 0, ["OVAL", 33.5, 11.8]], ["U32", "48", "", 2, 4112.205, 2529.533, 0, ["OVAL", 33.5, 11.8]], ["U32", "49", "", 2, 4084.6450000000004, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "50", "", 2, 4064.965, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "51", "", 2, 4045.2750000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "52", "+3V3_HUB", 2, 4025.5950000000003, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "53", "", 2, 4005.905, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "54", "PRTDIS6", 2, 3986.225, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "55", "", 2, 3966.535, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "56", "PRTDIS7", 2, 3946.8550000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "57", "+3V3_HUB", 2, 3927.165, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "58", "UP_DM", 2, 3907.4850000000006, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "59", "UP_DP", 2, 3887.7950000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "60", "XTAL2", 2, 3868.1150000000002, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "61", "XTAL1", 2, 3848.425, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "62", "VDD18PLL", 2, 3828.745, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "63", "RBIAS", 2, 3809.0550000000003, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "64", "+3V3_HUB", 2, 3789.375, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "65", "GND", 2, 3937.0150000000003, 2677.173, -1.5707963267948966, ["RECT", 189, 189, 0]], ["U51", "1", "USB1_DMJ", 2, 879.53, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "2", "GND", 2, 916.93, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "3", "USB1_DPJ", 2, 954.3299999999999, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "4", "USB1_DP", 2, 954.3299999999999, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "5", "VBUS1", 2, 916.93, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "6", "USB1_DM", 2, 879.53, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "1", "USB2_DMJ", 2, 3694.49, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "2", "GND", 2, 3731.8899999999994, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "3", "USB2_DPJ", 2, 3769.29, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "4", "USB2_DP", 2, 3769.29, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "5", "VBUS2", 2, 3731.8899999999994, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "6", "USB2_DM", 2, 3694.49, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "1", "USB3_DMJ", 2, 6509.450000000001, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "2", "GND", 2, 6546.85, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "3", "USB3_DPJ", 2, 6584.250000000001, 3516.1099999999997, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "4", "USB3_DP", 2, 6584.250000000001, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "5", "VBUS3", 2, 6546.85, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "6", "USB3_DM", 2, 6509.450000000001, 3425.63, 0, ["RECT", 20.9, 42.2, 0]], ["U54", "1", "USB4_DMJ", 2, 3562.9900000000002, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "2", "GND", 2, 3525.59, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "3", "USB4_DPJ", 2, 3488.19, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "4", "USB4_DP", 2, 3488.19, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "5", "VBUS4", 2, 3525.59, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "6", "USB4_DM", 2, 3562.9900000000002, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "1", "USB5_DMJ", 2, 6377.950000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "2", "GND", 2, 6340.550000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "3", "USB5_DPJ", 2, 6303.150000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "4", "USB5_DP", 2, 6303.150000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "5", "VBUS5", 2, 6340.550000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "6", "USB5_DM", 2, 6377.950000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["Y1", "1", "XTAL1", 2, 3728.34, 2348.425, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "2", "GND", 2, 3814.9600000000005, 2348.425, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "3", "XTAL2", 2, 3814.9600000000005, 2281.4950000000003, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "4", "GND", 2, 3728.34, 2281.4950000000003, 0, ["RECT", 55.1, 47.2, 0]], ["C736", "2", "+5V", 2, 3208.66, 2303.15, 0, ["RECT", 55.5, 53.1, 0]], ["C736", "1", "GND", 2, 3129.9199999999996, 2303.15, 0, ["RECT", 55.5, 53.1, 0]], ["C737", "2", "+3V3_HUB", 2, 3724.12, 2125.98, 0, ["RECT", 58.5, 68, 0]], ["C737", "1", "GND", 2, 3598.7200000000003, 2125.98, 0, ["RECT", 58.5, 68, 0]], ["C760", "2", "+3V3_HUB", 2, 2460.63, 2378.74, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C760", "1", "GND", 2, 2460.63, 2345.66, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["J31", "1", "VO1_P", 12, 1490.94, 2707.48, 0, ["RECT", 66.9, 66.9, 0]], ["J31", "2", "GND", 12, 1490.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "3", "VO1_P", 12, 1590.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "4", "GND", 12, 1590.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "5", "VO1_P", 12, 1690.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "6", "GND", 12, 1690.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "7", "+5V", 12, 1790.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "8", "GND", 12, 1790.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "9", "+5V", 12, 1890.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "10", "GND", 12, 1890.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "11", "POGO1_PWR", 12, 1990.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "12", "POGO4_PWR", 12, 1990.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "13", "POGO1_VUP", 12, 2090.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "14", "POGO4_VUP", 12, 2090.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "15", "POGO1_VDN", 12, 2190.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "16", "POGO4_VDN", 12, 2190.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "17", "EDL_EN1", 12, 2290.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "18", "EDL_EN4", 12, 2290.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "19", "VBUS_EN1", 12, 2390.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "20", "VBUS_EN4", 12, 2390.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "21", "SDA", 12, 2490.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "22", "+5V", 12, 2490.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "23", "SCL", 12, 2590.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "24", "+5V", 12, 2590.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "25", "GND", 12, 2690.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "26", "UP_VBUS_DET", 12, 2690.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "27", "GND", 12, 2790.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "28", "GND", 12, 2790.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "29", "GND", 12, 2890.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "30", "VO4_P", 12, 2890.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "31", "GND", 12, 2990.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "32", "VO4_P", 12, 2990.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "33", "GND", 12, 3090.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "34", "VO4_P", 12, 3090.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "35", "VO2_P", 12, 3190.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "36", "GND", 12, 3190.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "37", "VO2_P", 12, 3290.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "38", "GND", 12, 3290.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "39", "VO2_P", 12, 3390.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "40", "GND", 12, 3390.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "1", "+5V", 12, 5270.47, 2707.48, 0, ["RECT", 66.9, 66.9, 0]], ["J32", "2", "+5V", 12, 5270.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "3", "+5V", 12, 5370.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "4", "+5V", 12, 5370.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "5", "POGO2_PWR", 12, 5470.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "6", "VBUS_EN5", 12, 5470.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "7", "POGO2_VUP", 12, 5570.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "8", "EDL_EN5", 12, 5570.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "9", "POGO2_VDN", 12, 5670.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "10", "GND", 12, 5670.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "11", "EDL_EN2", 12, 5770.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "12", "GND", 12, 5770.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "13", "VBUS_EN2", 12, 5870.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "14", "GND", 12, 5870.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "15", "HUB_RST", 12, 5970.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "16", "GND", 12, 5970.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "17", "GND", 12, 6070.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "18", "VO5_P", 12, 6070.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "19", "GND", 12, 6170.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "20", "VO5_P", 12, 6170.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "21", "GND", 12, 6270.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "22", "VO5_P", 12, 6270.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "23", "POGO3_PWR", 12, 6370.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "24", "POGO5_PWR", 12, 6370.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "25", "POGO3_VUP", 12, 6470.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "26", "POGO5_VUP", 12, 6470.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "27", "POGO3_VDN", 12, 6570.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "28", "POGO5_VDN", 12, 6570.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "29", "VO3_P", 12, 6670.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "30", "GND", 12, 6670.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "31", "VO3_P", 12, 6770.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "32", "GND", 12, 6770.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "33", "VO3_P", 12, 6870.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "34", "GND", 12, 6870.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "35", "EDL_EN3", 12, 6970.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "36", "GND", 12, 6970.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "37", "VBUS_EN3", 12, 7070.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "38", "GND", 12, 7070.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "39", "+5V", 12, 7170.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "40", "+5V", 12, 7170.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["U31", "1", "GND", 2, 3561.807, 2472.44, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "2", "+3V3_HUB", 2, 3561.807, 2381.89, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "3", "+5V", 2, 3561.807, 2291.3399999999997, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "4", "+3V3_HUB", 2, 3327.952, 2381.89, 0, ["RECT", 92.1, 141.7, 0]], ["U34", "1", "SDA", 2, 2176.96, 2287.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "2", "SCL", 2, 2176.96, 2337.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "3", "", 2, 2176.96, 2387.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "4", "GND", 2, 2176.96, 2437.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "8", "+3V3_HUB", 2, 2389.96, 2287.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "7", "GND", 2, 2389.96, 2337.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "6", "GND", 2, 2389.96, 2387.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "5", "GND", 2, 2389.96, 2437.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["C802", "2", "VO1_P", 2, 2243.99, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C802", "1", "GND", 2, 2369.3900000000003, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C804", "2", "VO1_P", 2, 2066.8300000000004, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C804", "1", "GND", 2, 2192.2300000000005, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["J41", "1", "POGO1_PWR", 1, 2715.75, 4753.94, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J42", "1", "POGO1_VUP", 1, 2731.8899999999994, 4844.88, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J43", "1", "POGO1_VDN", 1, 2625.2, 4769.29, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J45", "1", "POGO2_PWR", 1, 5530.71, 4753.94, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J46", "1", "POGO2_VUP", 1, 5546.85, 4844.88, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J49", "1", "POGO3_PWR", 1, 8345.67, 4753.94, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["R741", "2", "EDL_EN1", 2, 1462.88, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R741", "1", "GND", 2, 1496.9600000000003, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["U42", "3", "", 2, 4084.2499999999995, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "2", "GND", 2, 4084.2499999999995, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "1", "$22N75", 2, 4084.2499999999995, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "6", "EDL_EN2", 2, 4190.549999999999, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "5", "+3V3_HUB", 2, 4190.549999999999, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "4", "$22N76", 2, 4190.549999999999, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["J63", "4", "GND", 2, 5884.44, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J63", "3", "GND", 2, 6130.519999999999, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J63", "2", "$23N76", 2, 5982.9299999999985, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J63", "1", "$23N75", 2, 6032.129999999999, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J56", "1", "GND", 1, 1687.8, 392.13, 0, ["ELLIPSE", 74.8, 74.8]], ["J59", "1", "POGO5_VDN", 1, 4632.28, 551.97, 0, ["ELLIPSE", 74.8, 74.8]], ["C765", "2", "+3V3_HUB", 2, 6089.37, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C765", "1", "GND", 2, 6056.29, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["R791", "2", "$21N88", 2, 1580.9899999999998, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R791", "1", "GND", 2, 1615.0700000000002, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C801", "2", "GND", 2, 1318.505, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C801", "1", "VO1_P", 2, 1657.0949999999998, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C803", "2", "VO1_P", 2, 2263.68, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C803", "1", "GND", 2, 2389.08, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C805", "2", "VO1_P", 2, 1869.98, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C805", "1", "GND", 2, 1995.38, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["R782", "2", "$22N69", 2, 4474.69, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R782", "1", "GND", 2, 4508.7699999999995, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R792", "2", "$22N70", 2, 4395.95, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R792", "1", "GND", 2, 4430.03, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C811", "2", "GND", 2, 4133.465, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C811", "1", "VO2_P", 2, 4472.055, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C812", "2", "VO2_P", 2, 5058.95, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C812", "1", "GND", 2, 5184.349999999999, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C813", "2", "VO2_P", 2, 5078.64, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C813", "1", "GND", 2, 5204.04, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C814", "2", "VO2_P", 2, 4881.79, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C814", "1", "GND", 2, 5007.19, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["J83", "1", "VO3_P", 2, 7688.5802, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "2", "GND", 2, 7609.8401, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "3", "$23N69", 2, 7531.0999, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "4", "$23N70", 2, 7452.3598, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["R783", "2", "$23N69", 2, 7289.650000000001, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R783", "1", "GND", 2, 7323.73, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R793", "2", "$23N70", 2, 7210.91, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R793", "1", "GND", 2, 7244.989999999999, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C821", "2", "GND", 2, 6948.425000000001, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C821", "1", "VO3_P", 2, 7287.015, 4581.1, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C822", "2", "VO3_P", 2, 7873.91, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C822", "1", "GND", 2, 7999.3099999999995, 4435.43, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C823", "2", "VO3_P", 2, 7893.6, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C823", "1", "GND", 2, 8019, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C763", "2", "+3V3_HUB", 2, 6798.03, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C763", "1", "GND", 2, 6831.11, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["J84", "1", "VO4_P", 2, 2383.8597999999997, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "2", "GND", 2, 2462.5998999999997, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "3", "$24N69", 2, 2541.3400999999994, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "4", "$24N70", 2, 2620.0802, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["R784", "2", "$24N69", 2, 2782.79, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R784", "1", "GND", 2, 2748.71, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R794", "2", "$24N70", 2, 2861.5299999999997, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R794", "1", "GND", 2, 2827.4499999999994, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["C831", "2", "GND", 2, 3124.015, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C831", "1", "VO4_P", 2, 2785.4249999999997, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C832", "2", "VO4_P", 2, 2198.53, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C832", "1", "GND", 2, 2073.13, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["R744", "2", "EDL_EN4", 2, 2979.64, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["R744", "1", "GND", 2, 2945.56, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["C764", "2", "+3V3_HUB", 2, 3274.41, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C764", "1", "GND", 2, 3241.33, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["J85", "1", "VO5_P", 2, 5198.8198, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "2", "GND", 2, 5277.5599, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "3", "$25N69", 2, 5356.3000999999995, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "4", "$25N70", 2, 5435.0401999999995, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["R785", "2", "$25N69", 2, 5597.75, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R785", "1", "GND", 2, 5563.670000000001, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R795", "2", "$25N70", 2, 5676.489999999999, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R795", "1", "GND", 2, 5642.41, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["C841", "2", "GND", 2, 5938.984999999999, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C841", "1", "VO5_P", 2, 5600.3949999999995, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C806", "2", "VO1_P", 2, 2132.67, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C806", "1", "GND", 2, 2165.75, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C815", "2", "VO2_P", 2, 4684.9400000000005, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C815", "1", "GND", 2, 4810.34, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C816", "2", "VO2_P", 2, 4947.63, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C816", "1", "GND", 2, 4980.71, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C824", "2", "VO3_P", 2, 7696.75, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C824", "1", "GND", 2, 7822.15, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C825", "2", "VO3_P", 2, 7499.9, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C825", "1", "GND", 2, 7625.299999999999, 4297.64, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C826", "2", "VO3_P", 2, 7762.59, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C826", "1", "GND", 2, 7795.67, 4435.43, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C833", "2", "VO4_P", 2, 2178.8399999999997, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C833", "1", "GND", 2, 2053.4399999999996, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C834", "2", "VO4_P", 2, 2375.69, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C834", "1", "GND", 2, 2250.2899999999995, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C835", "2", "VO4_P", 2, 2572.54, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C835", "1", "GND", 2, 2447.14, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C836", "2", "VO4_P", 2, 2309.85, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C836", "1", "GND", 2, 2276.77, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C842", "2", "VO5_P", 2, 5013.49, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C842", "1", "GND", 2, 4888.09, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C843", "2", "VO5_P", 2, 4993.8, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C843", "1", "GND", 2, 4868.400000000001, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C844", "2", "VO5_P", 2, 5190.65, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C844", "1", "GND", 2, 5065.25, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C845", "2", "VO5_P", 2, 5387.5, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C845", "1", "GND", 2, 5262.1, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["J60", "1", "GND", 1, 4502.76, 392.13, 0, ["ELLIPSE", 74.8, 74.8]], ["J44", "1", "GND", 1, 2754.72, 4929.13, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J47", "1", "POGO2_VDN", 1, 5440.16, 4769.29, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J50", "1", "POGO3_VUP", 1, 8361.81, 4844.88, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J53", "1", "POGO4_PWR", 1, 1726.77, 567.32, 0, ["ELLIPSE", 74.8, 74.8]], ["C846", "2", "VO5_P", 2, 5124.810000000001, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C846", "1", "GND", 2, 5091.7300000000005, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["J65", "4", "GND", 2, 7002.959999999999, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J65", "3", "GND", 2, 6756.88, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J65", "2", "$25N76", 2, 6904.47, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["J65", "1", "$25N75", 2, 6855.2699999999995, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["U41", "3", "", 2, 1269.29, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "2", "GND", 2, 1269.29, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "1", "$21N93", 2, 1269.29, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "6", "EDL_EN1", 2, 1375.59, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "5", "+3V3_HUB", 2, 1375.59, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "4", "$21N94", 2, 1375.59, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["J62", "4", "GND", 2, 3069.4800000000005, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J62", "3", "GND", 2, 3315.56, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J62", "2", "$22N76", 2, 3167.9700000000003, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J62", "1", "$22N75", 2, 3217.17, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J52", "1", "GND", 1, 8384.65, 4929.13, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J55", "1", "POGO4_VDN", 1, 1817.32, 551.97, 0, ["ELLIPSE", 74.8, 74.8]], ["J58", "1", "POGO5_VUP", 1, 4525.59, 476.38, 0, ["ELLIPSE", 74.8, 74.8]], ["R745", "2", "EDL_EN5", 2, 5794.6, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["R745", "1", "GND", 2, 5760.520000000001, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["J81", "1", "VO1_P", 2, 2058.6602000000003, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "2", "GND", 2, 1979.9200999999998, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "3", "$21N87", 2, 1901.1799, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "4", "$21N88", 2, 1822.4397999999999, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["R781", "2", "$21N87", 2, 1659.7299999999998, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R781", "1", "GND", 2, 1693.81, 4297.64, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C761", "2", "+3V3_HUB", 2, 1168.1100000000001, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C761", "1", "GND", 2, 1201.19, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["J82", "1", "VO2_P", 2, 4873.6202, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "2", "GND", 2, 4794.8801, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "3", "$22N69", 2, 4716.1399, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "4", "$22N70", 2, 4637.399800000001, 4435.43, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["R742", "2", "EDL_EN2", 2, 4277.84, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R742", "1", "GND", 2, 4311.92, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C762", "2", "+3V3_HUB", 2, 3983.07, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C762", "1", "GND", 2, 4016.15, 4199.21, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["U43", "3", "", 2, 6899.209999999999, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "2", "GND", 2, 6899.209999999999, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "1", "$23N75", 2, 6899.209999999999, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "6", "EDL_EN3", 2, 7005.51, 4161.8099999999995, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "5", "+3V3_HUB", 2, 7005.51, 4199.21, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "4", "$23N76", 2, 7005.51, 4236.61, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["R743", "2", "EDL_EN3", 2, 7092.800000000001, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R743", "1", "GND", 2, 7126.88, 4199.21, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["J64", "4", "GND", 2, 4188, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J64", "3", "GND", 2, 3941.92, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J64", "2", "$24N76", 2, 4089.5099999999998, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["J64", "1", "$24N75", 2, 4040.31, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["U44", "3", "", 2, 3173.2299999999996, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "2", "GND", 2, 3173.2299999999996, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "1", "$24N75", 2, 3173.2299999999996, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "6", "EDL_EN4", 2, 3066.93, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "5", "+3V3_HUB", 2, 3066.93, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "4", "$24N76", 2, 3066.93, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["J61", "4", "GND", 2, 254.51999999999998, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J61", "3", "GND", 2, 500.6, 3354.735, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J61", "2", "$21N94", 2, 353.01, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J61", "1", "$21N93", 2, 402.21000000000004, 3468.8849999999998, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J48", "1", "GND", 1, 5569.69, 4929.13, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J51", "1", "POGO3_VDN", 1, 8255.12, 4769.29, 3.141592653589793, ["ELLIPSE", 74.8, 74.8]], ["J54", "1", "POGO4_VUP", 1, 1710.63, 476.38, 0, ["ELLIPSE", 74.8, 74.8]], ["J57", "1", "POGO5_PWR", 1, 4541.73, 567.32, 0, ["ELLIPSE", 74.8, 74.8]], ["U45", "3", "", 2, 5988.1900000000005, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "2", "GND", 2, 5988.1900000000005, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "1", "$25N75", 2, 5988.1900000000005, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "6", "EDL_EN5", 2, 5881.889999999999, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "5", "+3V3_HUB", 2, 5881.889999999999, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "4", "$25N76", 2, 5881.889999999999, 1084.65, 0, ["RECT", 43.3, 23.6, 0]]], "vias": [["USB1_DPJ", 869.685, 3569.2914, 24], ["USB1_DPJ", 979.9213, 3553.5433000000003, 24], ["USB2_DPJ", 3684.6457, 3569.2914, 24], ["USB2_DPJ", 3794.8819, 3553.5433000000003, 24], ["USB3_DPJ", 6499.6063, 3569.2914, 24], ["USB3_DPJ", 6609.8426, 3553.5433000000003, 24], ["USB4_DPJ", 3572.8346999999994, 1751.9685, 24], ["USB4_DPJ", 3462.5984, 1767.7165, 24], ["USB5_DPJ", 6387.7953, 1751.9685, 24], ["USB5_DPJ", 6277.5591, 1767.7165, 24], ["USB4_DM", 3629.9213, 2675.1969, 24], ["USB4_DM", 3562.9921000000004, 1980.315, 24], ["USB4_DP", 3629.9213, 2710.6299, 24], ["USB4_DP", 3527.5590999999995, 1980.315, 24], ["USB5_DM", 4381.8898, 2425.1969, 24], ["USB5_DM", 4381.8898, 2330.7087, 24], ["USB5_DP", 4342.5197, 2425.1969, 24], ["USB5_DP", 4342.5197, 2330.7087, 24], ["UP_DP", 8419.2914, 2450.7874, 24], ["UP_DP", 8419.2914, 2389.7638, 24], ["UP_DM", 8454.7245, 2413.3858, 24], ["UP_DM", 8454.7245, 2488.189, 24], ["GND", 3858.2737, 2598.4344999999994, 24], ["GND", 3858.2737, 2637.8046, 24], ["GND", 3858.2737, 2677.1747, 24], ["GND", 3858.2737, 2716.5448000000006, 24], ["GND", 3858.2737, 2755.9149, 24], ["GND", 3897.6438, 2598.4344999999994, 24], ["GND", 3897.6438, 2637.8046, 24], ["GND", 3897.6438, 2677.1747, 24], ["GND", 3897.6438, 2716.5448000000006, 24], ["GND", 3897.6438, 2755.9149, 24], ["GND", 3937.0139, 2598.4344999999994, 24], ["GND", 3937.0139, 2637.8046, 24], ["GND", 3937.0139, 2677.1747, 24], ["GND", 3937.0139, 2716.5448000000006, 24], ["GND", 3937.0139, 2755.9149, 24], ["GND", 3976.384, 2598.4344999999994, 24], ["GND", 3976.384, 2637.8046, 24], ["GND", 3976.384, 2677.1747, 24], ["GND", 3976.384, 2716.5448000000006, 24], ["GND", 3976.384, 2755.9149, 24], ["GND", 4015.7541, 2598.4344999999994, 24], ["GND", 4015.7541, 2637.8046, 24], ["GND", 4015.7541, 2677.1747, 24], ["GND", 4015.7541, 2716.5448000000006, 24], ["GND", 4015.7541, 2755.9149, 24], ["GND", 5864.7551, 3315.364, 24], ["GND", 5864.7551, 3354.7341, 24], ["GND", 5864.7551, 3394.1042000000007, 24], ["GND", 5904.1252, 3315.364, 24], ["GND", 5904.1252, 3354.7341, 24], ["GND", 5904.1252, 3394.1042000000007, 24], ["GND", 6110.834, 3315.364, 24], ["GND", 6110.834, 3354.7341, 24], ["GND", 6110.834, 3394.1042000000007, 24], ["GND", 6150.2041, 3315.364, 24], ["GND", 6150.2041, 3354.7341, 24], ["GND", 6150.2041, 3394.1042000000007, 24], ["GND", 1259.4495, 4581.1009, 24], ["GND", 1298.8195999999998, 4581.1009, 24], ["GND", 1338.1897, 4581.1009, 24], ["GND", 1377.5598, 4581.1009, 24], ["GND", 4074.4115999999995, 4581.1009, 24], ["GND", 4113.7817, 4581.1009, 24], ["GND", 4153.1518, 4581.1009, 24], ["GND", 4192.5219, 4581.1009, 24], ["GND", 7609.8387999999995, 4376.3764, 24], ["GND", 7609.8387999999995, 4415.7465, 24], ["GND", 7609.8387999999995, 4455.1166, 24], ["GND", 7609.8387999999995, 4494.4867, 24], ["GND", 6889.3699, 4581.1009, 24], ["GND", 6928.74, 4581.1009, 24], ["GND", 6968.1101, 4581.1009, 24], ["GND", 7007.4802, 4581.1009, 24], ["GND", 2462.5998, 826.776, 24], ["GND", 2462.5998, 866.1460999999999, 24], ["GND", 2462.5998, 905.5162, 24], ["GND", 2462.5998, 944.8863, 24], ["GND", 3064.9582999999993, 740.1617999999999, 24], ["GND", 3104.3284, 740.1617999999999, 24], ["GND", 3143.6985, 740.1617999999999, 24], ["GND", 3183.0686000000005, 740.1617999999999, 24], ["GND", 5277.558, 826.776, 24], ["GND", 5277.558, 866.1460999999999, 24], ["GND", 5277.558, 905.5162, 24], ["GND", 5277.558, 944.8863, 24], ["GND", 5879.9284, 740.1617999999999, 24], ["GND", 5919.2985, 740.1617999999999, 24], ["GND", 5958.6686, 740.1617999999999, 24], ["GND", 5998.038699999999, 740.1617999999999, 24], ["GND", 6983.2754, 1927.1546, 24], ["GND", 6983.2754, 1966.5247, 24], ["GND", 6983.2754, 2005.8948, 24], ["GND", 7022.6455, 1927.1546, 24], ["GND", 7022.6455, 1966.5247, 24], ["GND", 7022.6455, 2005.8948, 24], ["GND", 6737.196599999999, 1927.1546, 24], ["GND", 6737.196599999999, 1966.5247, 24], ["GND", 6737.196599999999, 2005.8948, 24], ["GND", 6776.566700000001, 1927.1546, 24], ["GND", 6776.566700000001, 1966.5247, 24], ["GND", 6776.566700000001, 2005.8948, 24], ["GND", 3049.793, 3315.364, 24], ["GND", 3049.793, 3354.7341, 24], ["GND", 3049.793, 3394.1042000000007, 24], ["GND", 3089.1631, 3315.364, 24], ["GND", 3089.1631, 3354.7341, 24], ["GND", 3089.1631, 3394.1042000000007, 24], ["GND", 3295.8758, 3315.364, 24], ["GND", 3295.8758, 3354.7341, 24], ["GND", 3295.8758, 3394.1042000000007, 24], ["GND", 3335.2459, 3315.364, 24], ["GND", 3335.2459, 3354.7341, 24], ["GND", 3335.2459, 3394.1042000000007, 24], ["GND", 1979.9184, 4376.3764, 24], ["GND", 1979.9184, 4415.7465, 24], ["GND", 1979.9184, 4455.1166, 24], ["GND", 1979.9184, 4494.4867, 24], ["GND", 4794.8805, 4376.3764, 24], ["GND", 4794.8805, 4415.7465, 24], ["GND", 4794.8805, 4455.1166, 24], ["GND", 4794.8805, 4494.4867, 24], ["GND", 4168.3133, 1927.1546, 24], ["GND", 4168.3133, 1966.5247, 24], ["GND", 4168.3133, 2005.8948, 24], ["GND", 4207.6834, 1927.1546, 24], ["GND", 4207.6834, 1966.5247, 24], ["GND", 4207.6834, 2005.8948, 24], ["GND", 3922.2344, 1927.1546, 24], ["GND", 3922.2344, 1966.5247, 24], ["GND", 3922.2344, 2005.8948, 24], ["GND", 3961.6044999999995, 1927.1546, 24], ["GND", 3961.6044999999995, 1966.5247, 24], ["GND", 3961.6044999999995, 2005.8948, 24], ["GND", 234.8348, 3315.364, 24], ["GND", 234.8348, 3354.7341, 24], ["GND", 234.8348, 3394.1042000000007, 24], ["GND", 274.2049, 3315.364, 24], ["GND", 274.2049, 3354.7341, 24], ["GND", 274.2049, 3394.1042000000007, 24], ["GND", 480.9136, 3315.364, 24], ["GND", 480.9136, 3354.7341, 24], ["GND", 480.9136, 3394.1042000000007, 24], ["GND", 520.2837, 3315.364, 24], ["GND", 520.2837, 3354.7341, 24], ["GND", 520.2837, 3394.1042000000007, 24], ["GND", 1754.5513, 4002.3604, 24], ["GND", 4569.5096, 4002.3604, 24], ["GND", 7384.4717, 4002.3604, 24], ["GND", 2768.2905, 1372.5663, 24], ["GND", 5583.2488, 1372.5663, 24], ["GND", 1305.8983, 4036.5522, 24], ["GND", 4120.8605, 4036.5522, 24], ["GND", 6935.8187, 4036.5522, 24], ["GND", 3170.8116, 1318.8984, 24], ["GND", 5985.7737, 1318.8984, 24], ["GND", 1207.481, 4036.5522, 24], ["GND", 4022.4392, 4036.5522, 24], ["GND", 6837.4013, 4036.5522, 24], ["GND", 3266.6302, 1331.983, 24], ["GND", 6081.5884, 1331.983, 24], ["GND", 3849.1505, 2176.3713, 24], ["GND", 4000.7333, 2941.7417, 24], ["GND", 3862.4242, 2382.8469, 24], ["GND", 3727.6174, 2412.5919, 24], ["GND", 4114.9026, 2412.5919, 24], ["GND", 3485.5235, 2863.0906, 24], ["GND", 3641.7303, 2853.8823, 24], ["GND", 3873.2866999999997, 2941.7417, 24], ["GND", 4235.7728, 2498.0289, 24], ["GND", 3872.5677, 2902.9684, 24], ["GND", 1108.5518, 4037.4639, 24], ["GND", 3923.51, 4037.4639, 24], ["GND", 6738.468199999999, 4037.4639, 24], ["GND", 3369.0738, 1318.8984, 24], ["GND", 6184.031999999999, 1318.8984, 24], ["GND", 3863.5836, 2349.6875, 24], ["GND", 4304.4393, 2698.4947, 24], ["GND", 4237.1845, 2639.7613, 24], ["GND", 8211.3115, 2574.4749, 24], ["GND", 8211.3115, 2377.6244, 24], ["GND", 4237.1845, 2687.0093, 24], ["GND", 4304.4393, 2533.7955, 24], ["GND", 3053.8284, 2456.3646, 24], ["GND", 1471.1097, 4002.3604, 24], ["GND", 4286.0719, 4002.3604, 24], ["GND", 7101.0301, 4002.3604, 24], ["GND", 3060.0909, 1318.8984, 24], ["GND", 5875.053, 1318.8984, 24], ["GND", 3799.2567, 2765.7535, 24], ["GND", 916.9295999999999, 3472.8765, 24], ["GND", 3731.8917999999994, 3472.8765, 24], ["GND", 6546.85, 3472.8765, 24], ["GND", 3525.5885, 1848.3823000000002, 24], ["GND", 6340.5507, 1848.3823000000002, 24], ["GND", 3879.3905, 2321.7379, 24], ["GND", 3676.6394, 2302.9087, 24], ["GND", 3152.149, 2356.8188, 24], ["GND", 3663.254, 2125.9815, 24], ["GND", 2494.823, 2345.6587, 24], ["GND", 3493.9568, 2500.542, 24], ["GND", 2236.6467, 2437.1982, 24], ["GND", 2330.277, 2337.1981, 24], ["GND", 2330.277, 2387.1981, 24], ["GND", 2449.6468, 2437.1982, 24], ["GND", 2433.9266, 4435.4315, 24], ["GND", 2216.9262, 4357.2632, 24], ["GND", 1532.0649, 4199.2109, 24], ["GND", 4128.5915, 4199.2109, 24], ["GND", 1760.3762000000002, 392.1301, 24], ["GND", 6056.2907, 1156.2435, 24], ["GND", 1628.5052999999998, 4330.0715, 24], ["GND", 2453.6156, 4297.6401, 24], ["GND", 1935.756, 4322.3368, 24], ["GND", 4543.8736, 4297.6401, 24], ["GND", 4443.4635, 4330.0715, 24], ["GND", 5248.8848, 4435.4315, 24], ["GND", 5268.5738, 4297.6401, 24], ["GND", 5031.8884, 4357.2632, 24], ["GND", 7358.8318, 4297.6401, 24], ["GND", 7258.4217, 4330.0715, 24], ["GND", 8063.8469, 4435.4315, 24], ["GND", 8083.535899999999, 4297.6401, 24], ["GND", 6855.287200000001, 4223.3882, 24], ["GND", 2748.7100999999993, 1058.7221, 24], ["GND", 2827.4503, 1058.7221, 24], ["GND", 2137.6666, 885.8312, 24], ["GND", 2945.5606, 1157.1553, 24], ["GND", 3241.3285, 1156.2435, 24], ["GND", 5563.668399999999, 1058.7221, 24], ["GND", 5642.4086, 1058.7221, 24], ["GND", 2189.9264, 4459.6088, 24], ["GND", 4750.7181, 4322.3368, 24], ["GND", 5004.8886, 4459.6088, 24], ["GND", 7846.8466, 4357.2632, 24], ["GND", 7565.6763, 4322.3368, 24], ["GND", 7819.8468, 4459.6088, 24], ["GND", 2117.9736, 1023.6187, 24], ["GND", 2314.8241, 1023.6187, 24], ["GND", 2511.6746, 1023.6187, 24], ["GND", 2276.7689, 920.0229, 24], ["GND", 4952.6248, 885.8312, 24], ["GND", 4932.9358, 1023.6187, 24], ["GND", 5129.7863, 1023.6187, 24], ["GND", 5326.6368, 1023.6187, 24], ["GND", 4575.3344, 392.1301, 24], ["GND", 2827.2981, 4929.1286, 24], ["GND", 5091.7311, 920.0229, 24], ["GND", 1313.6293, 4199.2109, 24], ["GND", 8457.2263, 4929.1286, 24], ["GND", 5760.518899999999, 1157.1553, 24], ["GND", 1728.9154000000003, 4297.6401, 24], ["GND", 1225.3668, 4223.3882, 24], ["GND", 4347.0231, 4199.2109, 24], ["GND", 4040.3290000000006, 4223.3882, 24], ["GND", 6943.5497, 4199.2109, 24], ["GND", 7161.9853, 4199.2109, 24], ["GND", 3128.8888, 1122.0518, 24], ["GND", 5642.2642, 4929.1286, 24], ["GND", 5943.847, 1122.0518, 24], ["GND", 3646.8704, 2385.26, 24], ["GND", 4132.7809, 2503.3105, 24], ["GND", 3828.7462, 2814.9201, 24], ["VO1_P", 1657.0945000000002, 4632.2796, 24], ["VO1_P", 1657.0945000000002, 4529.9174, 24], ["VO1_P", 1708.5984000000003, 4632.6024, 24], ["VO1_P", 2291.2323, 4435.4292, 24], ["VO1_P", 2310.9252, 4297.6418, 24], ["VO1_P", 2114.0748, 4297.6418, 24], ["VO1_P", 1822.7361999999998, 4297.6418, 24], ["VO1_P", 2103.1417, 4435.4292, 24], ["VO1_P", 2099.0276, 4475.7953, 24], ["VO1_P", 2099.0276, 4395.063, 24], ["VO1_P", 2125.4725, 4502.2441, 24], ["VO2_P", 4472.0551, 4632.2796, 24], ["VO2_P", 4472.0551, 4529.9174, 24], ["VO2_P", 4523.5551, 4632.6024, 24], ["VO2_P", 5106.1929, 4435.4292, 24], ["VO2_P", 5125.885900000001, 4297.6418, 24], ["VO2_P", 4929.0355, 4297.6418, 24], ["VO2_P", 4637.6969, 4297.6418, 24], ["VO2_P", 4918.1024, 4435.4292, 24], ["VO2_P", 4913.9882, 4475.7953, 24], ["VO2_P", 4913.9882, 4395.063, 24], ["VO2_P", 4940.4331, 4502.2441, 24], ["VO3_P", 7287.0158, 4632.2796, 24], ["VO3_P", 7287.0158, 4529.9174, 24], ["VO3_P", 7338.5158, 4632.6024, 24], ["VO3_P", 7921.1536, 4435.4292, 24], ["VO3_P", 7940.8426, 4297.6418, 24], ["VO3_P", 7743.992200000001, 4297.6418, 24], ["VO3_P", 7452.6575, 4297.6418, 24], ["VO3_P", 7733.063, 4435.4292, 24], ["VO3_P", 7728.9449, 4475.7953, 24], ["VO3_P", 7728.9449, 4395.063, 24], ["VO3_P", 7755.3938, 4502.2441, 24], ["VO4_P", 2785.4252, 791.3425, 24], ["VO4_P", 2785.4252, 688.9803, 24], ["VO4_P", 2836.9252, 791.6614, 24], ["VO4_P", 2198.5315, 938.9803, 24], ["VO4_P", 2178.8386, 1076.7677, 24], ["VO4_P", 2375.689, 1076.7677, 24], ["VO4_P", 2619.7834999999995, 1023.6181, 24], ["VO4_P", 2339.378, 885.8307, 24], ["VO4_P", 2343.4921, 926.1969, 24], ["VO4_P", 2343.4921, 845.4646, 24], ["VO4_P", 2317.0473, 952.6417000000001, 24], ["VO5_P", 5600.3937, 791.3425, 24], ["VO5_P", 5600.3937, 688.9803, 24], ["VO5_P", 5651.8977, 791.6614, 24], ["VO5_P", 5013.4882, 938.9803, 24], ["VO5_P", 4993.7992, 1076.7677, 24], ["VO5_P", 5190.649599999999, 1076.7677, 24], ["VO5_P", 5434.7441, 1023.6181, 24], ["VO5_P", 5154.3386, 885.8307, 24], ["VO5_P", 5158.4528, 926.1969, 24], ["VO5_P", 5158.4528, 845.4646, 24], ["VO5_P", 5132.0079, 952.6417000000001, 24], ["GND", 3971.2018, 2307.08, 24], ["GND", 663.6696, 3565.0227, 24], ["GND", 3478.6318, 3565.0227, 24], ["GND", 6293.59, 3565.0227, 24], ["GND", 3813.952, 1791.3396, 24], ["GND", 6628.9141, 1791.3396, 24], ["GND", 8316.6103, 2566.9213, 24], ["GND", 8316.6064, 2314.9567, 24], ["GND", 936.6142, 3648.0315, 24], ["GND", 895.2756, 3648.0315, 24], ["GND", 840.1575, 3648.0315, 24], ["GND", 785.0394, 3648.0315, 24], ["GND", 936.6142, 3722.8346999999994, 24], ["GND", 785.0394, 3722.8346999999994, 24], ["GND", 743.7008000000001, 3722.8346999999994, 24], ["GND", 688.5827, 3722.8346999999994, 24], ["GND", 619.685, 3722.8346999999994, 24], ["GND", 491.7323, 3648.0315, 24], ["GND", 3751.5747999999994, 3648.0315, 24], ["GND", 3710.2362, 3648.0315, 24], ["GND", 3655.1181, 3648.0315, 24], ["GND", 3600, 3648.0315, 24], ["GND", 3751.5747999999994, 3722.8346999999994, 24], ["GND", 3600, 3722.8346999999994, 24], ["GND", 3558.6614, 3722.8346999999994, 24], ["GND", 3503.5433000000003, 3722.8346999999994, 24], ["GND", 3434.6457, 3722.8346999999994, 24], ["GND", 3306.6929, 3648.0315, 24], ["GND", 6566.5355, 3648.0315, 24], ["GND", 6525.1969, 3648.0315, 24], ["GND", 6470.0788, 3648.0315, 24], ["GND", 6414.9607, 3648.0315, 24], ["GND", 6566.5355, 3722.8346999999994, 24], ["GND", 6414.9607, 3722.8346999999994, 24], ["GND", 6373.6221000000005, 3722.8346999999994, 24], ["GND", 6318.504000000001, 3722.8346999999994, 24], ["GND", 6249.6063, 3722.8346999999994, 24], ["GND", 6121.6536, 3648.0315, 24], ["GND", 3505.9055, 1673.2284, 24], ["GND", 3547.2441, 1673.2284, 24], ["GND", 3602.3622, 1673.2284, 24], ["GND", 3657.4803, 1673.2284, 24], ["GND", 3505.9055, 1598.4251999999997, 24], ["GND", 3657.4803, 1598.4251999999997, 24], ["GND", 3698.8189, 1598.4251999999997, 24], ["GND", 3753.937, 1598.4251999999997, 24], ["GND", 3822.8346999999994, 1598.4251999999997, 24], ["GND", 3950.7874, 1673.2284, 24], ["GND", 6320.8662, 1673.2284, 24], ["GND", 6362.2048, 1673.2284, 24], ["GND", 6417.3229, 1673.2284, 24], ["GND", 6472.441, 1673.2284, 24], ["GND", 6320.8662, 1598.4251999999997, 24], ["GND", 6472.441, 1598.4251999999997, 24], ["GND", 6513.7796, 1598.4251999999997, 24], ["GND", 6568.8976999999995, 1598.4251999999997, 24], ["GND", 6637.7953, 1598.4251999999997, 24], ["GND", 6765.7481, 1673.2284, 24], ["THERM_1", 838.189, 3557.4803, 24], ["THERM_1", 697.7558999999999, 3557.4803, 24], ["THERM_2", 3653.1496000000006, 3557.4803, 24], ["THERM_2", 3512.7165999999997, 3557.4803, 24], ["THERM_3", 6468.1103, 3557.4803, 24], ["THERM_3", 6327.6772, 3557.4803, 24], ["THERM_4", 3604.3307, 1763.7795, 24], ["THERM_4", 3744.7638, 1763.7795, 24], ["THERM_5", 6419.2914, 1763.7795, 24], ["THERM_5", 6559.7245, 1763.7795, 24], ["VBUS_UP", 8311.0237, 2346.4567, 24], ["VBUS_UP", 8324.4843, 2535.4252, 24], ["VBUS_UP", 4228.3465, 2590.5512, 24], ["VBUS_UP", 3649.6063, 2275.5906, 24], ["XTAL1", 3746.063, 2371.063, 24], ["XTAL1", 3848.4252000000006, 2534.4488, 24], ["XTAL2", 3838.5827, 2299.2126, 24], ["XTAL2", 3996.063, 2539.3701, 24], ["CFGSEL0", 4263.7796, 2665.3543, 24], ["CFGSEL0", 4076.7717, 2669.2914, 24], ["NONREM0", 4269.6851, 2529.5276, 24], ["NONREM0", 4389.7638, 2549.2126, 24], ["NONREM0", 4389.7638, 2653.5433000000003, 24], ["NONREM0", 4072.8346999999994, 2598.4252000000006, 24], ["HUB_RST", 4053.1496000000006, 2722.441, 24], ["+3V3_HUB", 3559.0551, 2775.5906, 24], ["+3V3_HUB", 3472.441, 2775.5906, 24], ["+3V3_HUB", 3555.1181, 2427.1654, 24], ["+3V3_HUB", 3641.7322999999997, 2755.9055, 24], ["+3V3_HUB", 4171.2599, 2512.7953, 24], ["+3V3_HUB", 4314.9607, 2616.1417, 24], ["+3V3_HUB", 3633.8583, 2783.4646, 24], ["+3V3_HUB", 3740.1614, 2925.2008, 24], ["+3V3_HUB", 3905.5118, 2891.7322999999997, 24], ["+3V3_HUB", 4028.5433000000003, 2536.4173, 24], ["+3V3_HUB", 3934.0551, 2447.8347, 24], ["+3V3_HUB", 4076.7717, 2462.5984, 24], ["+3V3_HUB", 3988.189, 2338.5827, 24], ["+3V3_HUB", 3275.5906, 1114.1732, 24], ["+3V3_HUB", 3033.4685, 1122.0512, 24], ["+3V3_HUB", 3961.4095, 4199.2087, 24], ["+3V3_HUB", 4224.0118, 4199.2087, 24], ["+3V3_HUB", 1409.0512, 4199.2087, 24], ["+3V3_HUB", 1146.4488, 4199.2087, 24], ["+3V3_HUB", 6776.3701, 4199.2087, 24], ["+3V3_HUB", 7038.9725, 4199.2087, 24], ["EDL_EN1", 1437.0079, 4133.8583, 24], ["EDL_EN2", 5448.8189, 2937.0078999999996, 24], ["EDL_EN2", 4251.9685, 4133.8583, 24], ["EDL_EN3", 7011.8111, 4133.8583, 24], ["EDL_EN4", 3033.4685, 1159.4488, 24], ["EDL_EN5", 5570.8662, 2417.3229, 24], ["EDL_EN5", 5858.2678, 1161.4173, 24], ["EDL_EN5", 5812.9922, 1120.0787, 24], ["VBUS_EN2", 4303.1496, 4035.4331, 24], ["VBUS_EN2", 5795.2756, 2783.4646, 24], ["VBUS_EN4", 2996.063, 1283.4646, 24], ["VBUS_EN5", 5811.0237, 1283.4646, 24], ["VBUS_EN5", 5543.3071, 2511.811, 24], ["UP_VBUS_DET", 3090.5512, 2429.1339, 24], ["+5V", 7039.3701, 2763.7795, 24], ["+5V", 5704.7244, 2818.8977, 24], ["+5V", 5440.9449, 2783.4646, 24], ["+5V", 5401.5748, 2417.3229, 24], ["+5V", 5543.3071, 1472.441, 24], ["+5V", 5279.5276, 3015.7481, 24], ["+5V", 3649.6063, 2228.3465, 24], ["+5V", 3570.8662, 2224.4095, 24], ["+5V", 3561.8071, 2291.3386, 24], ["+5V", 3181.1024, 2318.8977, 24], ["+5V", 2417.3229, 2500, 24], ["+5V", 1492.1260000000002, 2500, 24], ["+5V", 1401.5748000000003, 3795.2756, 24], ["$20N304", 1255.9055, 4003.937, 24], ["$20N304", 1409.4488, 4074.8032000000003, 24], ["$20N314", 4070.8662, 4003.937, 24], ["$20N314", 4267.7166, 4074.8032000000003, 24], ["$20N324", 6893.700799999999, 4039.3701, 24], ["$20N324", 6984.252, 4094.4882, 24], ["$20N334", 3201.9607, 1341.3622, 24], ["$20N334", 2960.6299, 1275.5906, 24], ["$20N344", 6016.9213, 1341.3622, 24], ["$20N344", 5877.952800000001, 1255.9055, 24], ["$24N75", 3842.5197, 1665.3543, 24], ["$24N75", 3206.6929, 1159.4488, 24], ["$25N75", 6657.4804, 1665.3543, 24], ["$25N75", 6021.6496, 1159.4488, 24], ["$25N76", 6893.700799999999, 1854.3307, 24], ["$25N76", 5848.4292, 1084.6496, 24], ["VBUS1", 1362.2047, 3984.2520000000004, 24], ["VBUS1", 1366.1417000000001, 3736.2205, 24], ["VBUS1", 1464.5669, 3637.7953, 24], ["VBUS1", 1566.5315, 4002.3583, 24], ["VBUS1", 984.252, 3460.6299, 24], ["VBUS1", 916.9291, 3392.7205, 24], ["VBUS1", 745.7047, 3529.9213, 24], ["VBUS2", 4173.2284, 3976.378, 24], ["VBUS2", 4330.7087, 3964.567, 24], ["VBUS2", 3799.2126, 3460.6299, 24], ["VBUS2", 3731.8898, 3392.7205, 24], ["VBUS2", 3560.6654, 3529.9213, 24], ["VBUS3", 7039.3701, 3893.7008000000005, 24], ["VBUS3", 7196.452799999999, 4002.3583, 24], ["VBUS3", 6917.3229, 3901.5747999999994, 24], ["VBUS3", 6638.582699999999, 3621.2676999999994, 24], ["VBUS3", 6546.850400000001, 3392.7205, 24], ["VBUS3", 6375.626, 3529.9213, 24], ["VBUS4", 3086.6142, 1346.4567, 24], ["VBUS4", 2893.7008000000005, 1429.1338999999998, 24], ["VBUS4", 2822.8346999999994, 1413.3858, 24], ["VBUS4", 2875.9882, 1356.2992, 24], ["VBUS4", 3435.0394, 1698.8189, 24], ["VBUS4", 3525.5906, 1928.5394, 24], ["VBUS4", 3694.8819, 1793.3071, 24], ["VBUS5", 5775.5906, 1429.1338999999998, 24], ["VBUS5", 5704.7244, 1358.2677, 24], ["VBUS5", 6271.6536, 1862.2047, 24], ["VBUS5", 6340.5512, 1928.5394, 24], ["VBUS5", 6509.8426, 1793.3071, 24], ["POGO1_VDN", 2188.9764, 2913.3858, 24], ["POGO1_VDN", 2334.6457, 4133.8583, 24], ["POGO1_VDN", 2625.2008, 4769.2914, 24], ["POGO1_PWR", 1992.1260000000002, 3110.2362, 24], ["POGO1_PWR", 2307.0866, 4059.0551, 24], ["POGO1_PWR", 2715.7479999999996, 4753.941, 24], ["POGO1_VUP", 2090.5512, 3011.811, 24], ["POGO1_VUP", 2090.5512, 3165.3544, 24], ["POGO1_VUP", 2731.8898, 4844.8819, 24], ["POGO2_PWR", 5598.4252, 2838.5827, 24], ["POGO2_PWR", 5641.7323, 2881.8898, 24], ["POGO2_PWR", 5641.7323, 2937.0078999999996, 24], ["POGO2_PWR", 5641.7323, 4133.8583, 24], ["POGO2_PWR", 5530.7087, 4753.941, 24], ["POGO2_VDN", 5913.385900000001, 2783.4646, 24], ["POGO2_VDN", 5669.2914, 4059.0551, 24], ["POGO2_VDN", 5440.1615, 4769.2914, 24], ["POGO2_VUP", 5216.5355, 2661.4173, 24], ["POGO2_VUP", 5535.4331, 2818.8977, 24], ["POGO2_VUP", 5673.2284, 2862.2047, 24], ["POGO2_VUP", 5677.1654, 2937.0078999999996, 24], ["POGO2_VUP", 5669.2914, 4011.8111, 24], ["POGO2_VUP", 5586.6142, 4594.4882, 24], ["POGO3_VDN", 6984.252, 3448.8189, 24], ["POGO3_VDN", 7043.3071, 3507.874, 24], ["POGO3_PWR", 6956.693, 3374.0158, 24], ["POGO3_PWR", 7043.3071, 3460.6299, 24], ["POGO3_VUP", 6673.2284, 2854.3307, 24], ["POGO3_VUP", 7043.3071, 3204.7244, 24], ["POGO5_PWR", 6370.0788, 2417.3229, 24], ["POGO5_PWR", 5838.582699999999, 1854.3307, 24], ["POGO5_PWR", 5413.385900000001, 1429.1338999999998, 24], ["POGO5_VDN", 6448.8189, 2417.3229, 24], ["POGO5_VDN", 5874.015799999999, 1842.5197, 24], ["POGO5_VDN", 5448.8189, 1417.3228, 24], ["POGO5_VUP", 6397.6378, 2492.126, 24], ["POGO5_VUP", 5944.8819, 2035.4331, 24], ["POGO5_VUP", 5507.8741, 1566.9291, 24], ["SDA", 2318.8977, 2421.2599, 24], ["SCL", 2242.126, 2657.4803, 24], ["SCL", 2175.1969, 2354.3307, 24]], "lines": [["3114fd1435f7a6d8", "USB1_DPJ", 2, 909.0551, 3606.2991999999995, 909.0551, 3592.9134, 4.3307], ["c7ac9887a9d652fe", "USB1_DPJ", 2, 909.0551, 3592.9134, 901.7440999999999, 3582.1142, 4.3307], ["81f562e66d372d85", "USB1_DPJ", 2, 901.7440999999999, 3582.1142, 889.3701, 3577.1654, 7.874], ["f4a217da7612b10c", "USB1_DPJ", 2, 889.3701, 3577.1654, 869.685, 3569.2914, 11.0236], ["0edfe53fa732c2d2", "USB1_DPJ", 1, 869.685, 3569.2914, 979.9213, 3553.5433000000003, 11.0236], ["a59d22f6995e218a", "USB1_DPJ", 2, 979.9213, 3553.5433000000003, 954.3307, 3527.9528, 11.0236], ["8154a8b5a66f6a2c", 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["99a769ccd0721c6e", "UP_DP", 2, 3887.7953, 2380.7087, 3901.5747999999994, 2366.9291, 11.0236], ["8c51f39d8eedfe66", "UP_DP", 2, 3901.5747999999994, 2366.9291, 8070.8662, 2366.9291, 11.0236], ["da5890a955319586", "UP_DP", 2, 8070.8662, 2366.9291, 8115.3544, 2411.4173, 11.0236], ["13a43ef9ea72ea78", "UP_DP", 2, 8115.3544, 2411.4173, 8361.8898, 2411.4173, 11.0236], ["6f8fb395e226d125", "UP_DM", 2, 3907.4803, 2501.9685, 3907.4803, 2399.6063, 11.0236], ["429f82464387c5c3", "UP_DM", 2, 3907.4803, 2399.6063, 3921.2599, 2385.8268, 11.0236], ["f31d396620479b95", "UP_DM", 2, 3921.2599, 2385.8268, 8062.9922, 2385.8268, 11.0236], ["239d683915b8e7cd", "UP_DM", 2, 8062.9922, 2385.8268, 8108.2678, 2431.1024, 11.0236], ["95fdf66862b2a336", "UP_DM", 2, 8108.2678, 2431.1024, 8361.8898, 2431.1024, 11.0236], ["e9922b5c546b5d0b", "UP_DP", 2, 8361.8898, 2450.7874, 8419.2914, 2450.7874, 11.0236], ["dcb00e80f1f22c0c", "UP_DP", 1, 8419.2914, 2450.7874, 8419.2914, 2389.7638, 11.0236], ["7f847fa1a024b6b9", "UP_DP", 2, 8419.2914, 2389.7638, 8408.6812, 2406.437, 11.0236], ["273854ff3d1347e7", "UP_DP", 2, 8408.6812, 2406.437, 8399.6064, 2411.4173, 11.0236], ["939a54232593908a", "UP_DP", 2, 8361.8898, 2411.4173, 8399.6064, 2411.4173, 11.0236], ["f36793d1187b7a0d", "UP_DM", 2, 8405.5119, 2431.1024, 8361.8898, 2431.1024, 11.0236], ["09e68f894b265062", "UP_DM", 2, 8405.5119, 2431.1024, 8435.0394, 2413.3858, 11.0236], ["a32dd4b6cf73a077", "UP_DM", 2, 8435.0394, 2413.3858, 8454.7245, 2413.3858, 11.0236], ["e830e07e8982fd3b", "UP_DM", 1, 8454.7245, 2413.3858, 8454.7245, 2488.189, 11.0236], ["5245bff4cf7a5fbd", "UP_DM", 2, 8454.7245, 2488.189, 8435.0394, 2488.189, 11.0236], ["34a46b51c68b3059", "UP_DM", 2, 8435.0394, 2488.189, 8405.5119, 2470.4725, 11.0236], ["2c4ccf655a488b22", "UP_DM", 2, 8361.8898, 2470.4725, 8405.5119, 2470.4725, 11.0236], ["43df5eb07fd2d2d9", "GND", 2, 1722.2431000000001, 4002.3604, 1754.5513, 4002.3604, 11.811], ["f334c26ba313ddcc", "GND", 2, 4537.2013, 4002.3604, 4569.5096, 4002.3604, 11.811], ["846431bbb68b7cb0", "GND", 2, 7352.1634, 4002.3604, 7384.4717, 4002.3604, 11.811], ["983859920d045c6f", "GND", 2, 2768.2905, 1343.4791, 2768.2905, 1372.5663, 11.811], ["af41b15aa24be223", "GND", 2, 5583.2488, 1343.4791, 5583.2488, 1372.5663, 11.811], ["2d883c9144322ab3", "GND", 2, 1305.8983, 4011.0415000000003, 1305.8983, 4036.5522, 11.811], ["301fa91d54f3e73f", "GND", 2, 4120.8605, 4011.0415000000003, 4120.8605, 4036.5522, 11.811], ["bfb306a8e09d8f2a", "GND", 2, 6935.8187, 4011.0415000000003, 6935.8187, 4036.5522, 11.811], ["a91325a0f64c090f", "GND", 2, 3144.5017, 1318.8984, 3170.8116, 1318.8984, 11.811], ["5d5e17705be4c274", "GND", 2, 5959.463800000001, 1318.8984, 5985.7737, 1318.8984, 11.811], ["59852f0fc9ce4df0", "GND", 2, 1207.481, 4011.0415000000003, 1207.481, 4036.5522, 11.811], ["96b891c7b9a1e3c5", "GND", 2, 4022.4392, 4011.0415000000003, 4022.4392, 4036.5522, 11.811], ["63a31bf426b64e43", "GND", 2, 6837.4013, 4011.0415000000003, 6837.4013, 4036.5522, 11.811], ["7f0f7c8c377c5b86", "GND", 2, 3242.923, 1327.5794999999998, 3266.6302, 1331.983, 11.811], ["bd33d4d637cd1387", "GND", 2, 6057.8812, 1327.5794999999998, 6081.5884, 1331.983, 11.811], ["2e4bcb0642933e04", "GND", 2, 3823.6399, 2176.3713, 3849.1505, 2176.3713, 11.811], ["3039b3ce6706364a", "GND", 2, 3975.2226, 2941.7417, 4000.7333, 2941.7417, 11.811], ["f69ee87e4124fc88", "GND", 2, 3841.3603000000003, 2404.71, 3862.4242, 2382.8469, 11.811], ["6685f2c39852b343", "GND", 2, 3753.1280000000006, 2412.5919, 3727.6174, 2412.5919, 11.811], ["438303e56911f3cd", "GND", 2, 4089.392, 2412.5919, 4114.9026, 2412.5919, 11.811], ["0732b1bfd6658cb1", "GND", 2, 3481.12, 2839.3834000000006, 3485.5235, 2863.0906, 11.811], ["95628457e013a0a6", "GND", 2, 3641.7303, 2827.5724, 3641.7303, 2853.8823, 11.811], ["4bb1964315128926", "GND", 2, 3898.7973999999995, 2941.7417, 3873.2866999999997, 2941.7417, 11.811], ["639f7356819d343d", "GND", 2, 4209.4629, 2498.0289, 4235.7728, 2498.0289, 11.811], ["ba8a1c023a401fd3", "GND", 2, 3844.6812, 2902.9684, 3872.5677, 2902.9684, 11.811], ["925e186ca5fc9795", "GND", 2, 1108.5518, 4011.0415000000003, 1108.5518, 4037.4639, 11.811], ["8f8a1db7bd9119bc", "GND", 2, 3923.51, 4011.0415000000003, 3923.51, 4037.4639, 11.811], ["b4639464687ac75d", "GND", 2, 6738.468199999999, 4011.0415000000003, 6738.468199999999, 4037.4639, 11.811], ["c4935fd8a9780121", "GND", 2, 3343.1514000000006, 1318.8984, 3369.0738, 1318.8984, 11.811], ["a60f1c4667e868bb", "GND", 2, 6158.1096, 1318.8984, 6184.031999999999, 1318.8984, 11.811], ["df5e8c87459f6a00", "GND", 2, 3809.8603, 2402.9107, 3863.5836, 2349.6875, 11.811], ["8d8e5c20426c1107", "GND", 2, 4304.4393, 2672.0723, 4304.4393, 2698.4947, 11.811], ["a92d5a365666184e", "GND", 2, 4211.2621, 2639.7613, 4237.1845, 2639.7613, 11.811], ["9e49017ca113d981", "GND", 2, 8211.3115, 2548.0526, 8211.3115, 2574.4749, 11.811], ["c0246745d2d46361", "GND", 2, 8211.3115, 2351.2021, 8211.3115, 2377.6244, 11.811], ["de7143396744a162", "GND", 2, 4211.2621, 2687.0093, 4237.1845, 2687.0093, 11.811], ["5d139575f910e0f0", "GND", 2, 4304.4393, 2560.2179, 4304.4393, 2533.7955, 11.811], ["210f2cf408fa572b", "GND", 2, 3053.8284, 2429.9423, 3053.8284, 2456.3646, 11.811], ["b8d6c93028e8c19c", "GND", 2, 1446.4496, 4002.3604, 1471.1097, 4002.3604, 11.811], ["b55d326333ec7b7c", "GND", 2, 4261.4117, 4002.3604, 4286.0719, 4002.3604, 11.811], ["0ae28ebf218b9926", "GND", 2, 7076.369999999999, 4002.3604, 7101.0301, 4002.3604, 11.811], ["161091f5432e670f", "GND", 2, 3035.4308, 1318.8984, 3060.0909, 1318.8984, 11.811], ["391cbd8137949534", "GND", 2, 5850.392899999999, 1318.8984, 5875.053, 1318.8984, 11.811], ["57a8578fad13ba58", "GND", 2, 3776.5945999999994, 2765.7535, 3799.2567, 2765.7535, 11.811], ["18f7f9de46a10e92", "GND", 2, 916.9295999999999, 3496.9763000000003, 916.9295999999999, 3472.8765, 11.811], ["1a2e6daff27bf0fa", "GND", 2, 3731.8917999999994, 3496.9763000000003, 3731.8917999999994, 3472.8765, 11.811], ["3080a79a75f65dea", "GND", 2, 6546.85, 3496.9763000000003, 6546.85, 3472.8765, 11.811], ["b96d234db4392578", "GND", 2, 3525.5885, 1824.2824999999998, 3525.5885, 1848.3823000000002, 11.811], ["e15adf3b9bf0037e", "GND", 2, 6340.5507, 1824.2824999999998, 6340.5507, 1848.3823000000002, 11.811], ["586805d87f0d0812", "GND", 2, 3840.5395, 2326.7946, 3879.3905, 2321.7379, 11.811], ["e3ee6032080d6691", "GND", 2, 3702.7599, 2302.9087, 3676.6394, 2302.9087, 11.811], ["8de9f5e51e480f16", "GND", 2, 3152.149, 2327.7316, 3152.149, 2356.8188, 11.811], ["7db9223d1ffe4538", "GND", 2, 3626, 2125.9815, 3663.254, 2125.9815, 11.811], ["91bac59ce424f1b1", "GND", 2, 2469.3124, 2345.6587, 2494.823, 2345.6587, 11.811], ["e856fabeff25919e", "GND", 2, 3514.5728, 2492.1195, 3493.9568, 2500.542, 11.811], ["50d8739f164bd768", "GND", 2, 2213.3929, 2437.1982, 2236.6467, 2437.1982, 11.811], ["ee8fc87dbc6f3878", "GND", 2, 2353.5308, 2337.1981, 2330.277, 2337.1981, 11.811], ["a4473908e3a9030d", "GND", 2, 2353.5308, 2387.1981, 2330.277, 2387.1981, 11.811], ["c7ef56a789ad8133", "GND", 2, 2426.393, 2437.1982, 2449.6468, 2437.1982, 11.811], ["286b02b4d3c08fe4", "GND", 2, 2396.6726, 4435.4315, 2433.9266, 4435.4315, 11.811], ["6c521b5353b2dd07", "GND", 2, 2216.9262, 4329.6716, 2216.9262, 4357.2632, 11.811], ["5906e8ba0cc83e08", "GND", 2, 1506.1425, 4199.2109, 1532.0649, 4199.2109, 11.811], ["60b9464ee3bbb87b", "GND", 2, 4103.9313, 4199.2109, 4128.5915, 4199.2109, 11.811], ["fc4e760836932c03", "GND", 1, 1723.2312, 392.1301, 1760.3762000000002, 392.1301, 11.811], ["08ef77d5be6aa6ae", "GND", 2, 6056.2907, 1130.7329, 6056.2907, 1156.2435, 11.811], ["1a2665d4aeef7342", "GND", 2, 1624.2527999999998, 4306.3212, 1628.5052999999998, 4330.0715, 11.811], ["59c3fa07ff3a1c6f", "GND", 2, 2416.3615, 4297.6401, 2453.6156, 4297.6401, 11.811], ["1d50f4d098e33f6f", "GND", 2, 1968.0975, 4322.3368, 1935.756, 4322.3368, 11.811], ["554a25baa0acbfe6", "GND", 2, 4517.9513, 4297.6401, 4543.8736, 4297.6401, 11.811], ["4e5b8212f66c5d0b", "GND", 2, 4439.2111, 4306.3212, 4443.4635, 4330.0715, 11.811], ["99f683a5d91774c2", "GND", 2, 5211.630800000001, 4435.4315, 5248.8848, 4435.4315, 11.811], ["c3e5ffc767ed358d", "GND", 2, 5231.3198, 4297.6401, 5268.5738, 4297.6401, 11.811], ["357e51fbf2a65afd", "GND", 2, 5031.8884, 4329.6716, 5031.8884, 4357.2632, 11.811], ["953982e6bef6ce50", "GND", 2, 7332.9095, 4297.6401, 7358.8318, 4297.6401, 11.811], ["61a1da5845c0b2c1", "GND", 2, 7254.1693, 4306.3212, 7258.4217, 4330.0715, 11.811], ["df12010ff7c054cb", "GND", 2, 8026.5929, 4435.4315, 8063.8469, 4435.4315, 11.811], ["83c779d5e30071c5", "GND", 2, 8046.2819, 4297.6401, 8083.535899999999, 4297.6401, 11.811], ["9751b85f8c3b2b8d", "GND", 2, 6838.9919, 4207.892, 6855.287200000001, 4223.3882, 11.811], ["4ad4c078de81e01e", "GND", 2, 2748.7100999999993, 1032.2998, 2748.7100999999993, 1058.7221, 11.811], ["fcd96367dee8f574", "GND", 2, 2827.4503, 1032.2998, 2827.4503, 1058.7221, 11.811], ["a6910b0de2e3355d", "GND", 2, 2100.4126, 885.8312, 2137.6666, 885.8312, 11.811], ["c50ff69b0d83b7dc", "GND", 2, 2945.5606, 1130.7329, 2945.5606, 1157.1553, 11.811], ["884ba1d263c48c12", "GND", 2, 3241.3285, 1130.7329, 3241.3285, 1156.2435, 11.811], ["59af798ed4dce6e1", "GND", 2, 5563.668399999999, 1032.2998, 5563.668399999999, 1058.7221, 11.811], ["36337e3c747cffab", "GND", 2, 5642.4086, 1032.2998, 5642.4086, 1058.7221, 11.811], ["a3cfe220b15fea18", "GND", 2, 2173.6311, 4444.1126, 2189.9264, 4459.6088, 11.811], ["dafa6a678d189ca4", "GND", 2, 4783.0597, 4322.3368, 4750.7181, 4322.3368, 11.811], ["1a3664ae12044b96", "GND", 2, 4988.5932, 4444.1126, 5004.8886, 4459.6088, 11.811], ["8ca7026524e6446d", "GND", 2, 7846.8466, 4329.6716, 7846.8466, 4357.2632, 11.811], ["2db0bf98714e2c88", "GND", 2, 7598.0179, 4322.3368, 7565.6763, 4322.3368, 11.811], ["f3686544f8211b0c", "GND", 2, 7803.5515, 4444.1126, 7819.8468, 4459.6088, 11.811], ["00be9695c600ed4e", "GND", 2, 2080.7196, 1023.6187, 2117.9736, 1023.6187, 11.811], ["a6c862b81774af0a", "GND", 2, 2277.5701, 1023.6187, 2314.8241, 1023.6187, 11.811], ["65c45ca0c9d0beb9", "GND", 2, 2474.4206, 1023.6187, 2511.6746, 1023.6187, 11.811], ["101a5abb0c7cbd59", "GND", 2, 2276.7689, 894.5123, 2276.7689, 920.0229, 11.811], ["ea7f076ac6433927", "GND", 2, 4915.3708, 885.8312, 4952.6248, 885.8312, 11.811], ["b7b0c9a4cb9f0b5e", "GND", 2, 4895.6818, 1023.6187, 4932.9358, 1023.6187, 11.811], ["1690798a1540b94d", "GND", 2, 5092.5323, 1023.6187, 5129.7863, 1023.6187, 11.811], ["ab6a3356ecaa0f25", "GND", 2, 5289.382800000001, 1023.6187, 5326.6368, 1023.6187, 11.811], ["7108de8589e21117", "GND", 1, 4538.1895, 392.1301, 4575.3344, 392.1301, 11.811], ["9287471c3342dab8", "GND", 1, 2790.1531, 4929.1286, 2827.2981, 4929.1286, 11.811], ["6f5fc25e2e25f7fb", "GND", 2, 5091.7311, 894.5123, 5091.7311, 920.0229, 11.811], ["648ce9e9568ca71a", "GND", 2, 1288.9692, 4199.2109, 1313.6293, 4199.2109, 11.811], ["e4a559411e899ec4", "GND", 1, 8420.0813, 4929.1286, 8457.2263, 4929.1286, 11.811], ["4fcbc5cbe083b01c", "GND", 2, 5760.518899999999, 1130.7329, 5760.518899999999, 1157.1553, 11.811], ["174dfc3f295905f9", "GND", 2, 1702.993, 4297.6401, 1728.9154000000003, 4297.6401, 11.811], ["412445000d980928", "GND", 2, 1209.0715, 4207.892, 1225.3668, 4223.3882, 11.811], ["4e00acfaa52cde23", "GND", 2, 4321.1008, 4199.2109, 4347.0231, 4199.2109, 11.811], ["34b25311bfd5124c", "GND", 2, 4024.0337, 4207.892, 4040.3290000000006, 4223.3882, 11.811], ["d6dfc76ded89e1b5", "GND", 2, 6918.8896, 4199.2109, 6943.5497, 4199.2109, 11.811], ["76d5d32d3f67981b", "GND", 2, 7136.062899999999, 4199.2109, 7161.9853, 4199.2109, 11.811], ["9c685f2eb5284783", "GND", 2, 3153.5489, 1122.0518, 3128.8888, 1122.0518, 11.811], ["fb2527b6fc2e6c51", "GND", 1, 5605.1192, 4929.1286, 5642.2642, 4929.1286, 11.811], ["3d9f7820440cddcb", "GND", 2, 5968.5072, 1122.0518, 5943.847, 1122.0518, 11.811], ["0fa7159f5b51cfaf", "GND", 2, 3644.8839, 2357.1115, 3646.8704, 2385.26, 11.811], ["b753247f0ed644f8", "GND", 2, 4158.8172, 2536.5998, 4132.7809, 2503.3105, 5.9055], ["364881e15acf49e9", "GND", 2, 3828.7462, 2837.5822, 3828.7462, 2814.9201, 7.874], ["45463f96dcd4cb00", "VO1_P", 2, 1657.0945000000002, 4581.0985, 1657.0945000000002, 4632.2796, 39.3701], ["a1496edf74f99d34", "VO1_P", 2, 1657.0945000000002, 4581.0985, 1657.0945000000002, 4529.9174, 39.3701], ["a8c6eea0cbccbc54", "VO1_P", 2, 1657.0945000000002, 4581.0985, 1708.5984000000003, 4632.6024, 39.3701], ["23a3a9e6a0e4ae3b", "VO1_P", 2, 2243.9882, 4435.4292, 2291.2323, 4435.4292, 39.3701], ["1f3631b7a404ed3d", "VO1_P", 2, 2263.6811, 4297.6418, 2310.9252, 4297.6418, 39.3701], ["f2bbc87dbdf9aa54", "VO1_P", 2, 2066.8307, 4297.6418, 2114.0748, 4297.6418, 39.3701], ["4d9cf4bc6ce0e4a0", "VO1_P", 2, 1869.9803, 4297.6418, 1822.7361999999998, 4297.6418, 39.3701], ["3596aa5c3b66b5e4", "VO1_P", 2, 2126.7638, 4435.4292, 2103.1417, 4435.4292, 39.3701], ["775b313ab01607df", "VO1_P", 2, 2058.6614, 4435.4292, 2099.0276, 4475.7953, 39.3701], ["c621b61924080635", "VO1_P", 2, 2058.6614, 4435.4292, 2099.0276, 4395.063, 39.3701], ["15fd9220b383ec60", "VO1_P", 2, 2058.6614, 4435.4292, 2125.4725, 4502.2441, 39.3701], ["fd593cc210807230", "VO2_P", 2, 4472.0551, 4581.0985, 4472.0551, 4632.2796, 39.3701], ["56c0e20d42ed8fda", "VO2_P", 2, 4472.0551, 4581.0985, 4472.0551, 4529.9174, 39.3701], ["e9cf5bf548d6cb1e", "VO2_P", 2, 4472.0551, 4581.0985, 4523.5551, 4632.6024, 39.3701], ["9c64185127b8adb4", "VO2_P", 2, 5058.9489, 4435.4292, 5106.1929, 4435.4292, 39.3701], ["b6ac831ba821f843", "VO2_P", 2, 5078.6418, 4297.6418, 5125.885900000001, 4297.6418, 39.3701], ["55e2ac16ed24dbaa", "VO2_P", 2, 4881.7914, 4297.6418, 4929.0355, 4297.6418, 39.3701], ["f4f929eccd084f55", "VO2_P", 2, 4684.941, 4297.6418, 4637.6969, 4297.6418, 39.3701], ["7919f1d746bd42f2", "VO2_P", 2, 4941.7244, 4435.4292, 4918.1024, 4435.4292, 39.3701], ["e59783f2aad07bf8", "VO2_P", 2, 4873.6221, 4435.4292, 4913.9882, 4475.7953, 39.3701], ["4dc785b388621ee2", "VO2_P", 2, 4873.6221, 4435.4292, 4913.9882, 4395.063, 39.3701], ["372588ec0f11a010", "VO2_P", 2, 4873.6221, 4435.4292, 4940.4331, 4502.2441, 39.3701], ["9d36dafb3ba9ed5f", "VO3_P", 2, 7287.0158, 4581.0985, 7287.0158, 4632.2796, 39.3701], ["bb41dc7785d90d97", "VO3_P", 2, 7287.0158, 4581.0985, 7287.0158, 4529.9174, 39.3701], ["a37b2e0c7ed6248e", "VO3_P", 2, 7287.0158, 4581.0985, 7338.5158, 4632.6024, 39.3701], ["85b6c9360f8d9cef", "VO3_P", 2, 7873.9095, 4435.4292, 7921.1536, 4435.4292, 39.3701], ["6401970fc2f7f531", "VO3_P", 2, 7893.5985, 4297.6418, 7940.8426, 4297.6418, 39.3701], ["775f13ecb36344d8", "VO3_P", 2, 7696.7481, 4297.6418, 7743.992200000001, 4297.6418, 39.3701], ["18ef20040848eb38", "VO3_P", 2, 7499.901600000001, 4297.6418, 7452.6575, 4297.6418, 39.3701], ["9d3a80b6ffce2f5d", "VO3_P", 2, 7756.6851, 4435.4292, 7733.063, 4435.4292, 39.3701], ["e0eae5175a0d313c", "VO3_P", 2, 7688.5788, 4435.4292, 7728.9449, 4395.063, 39.3701], ["8c55bbeb73d4c6a4", "VO3_P", 2, 7688.5788, 4435.4292, 7755.3938, 4502.2441, 39.3701], ["28ff89d0a1e01143", "VO4_P", 2, 2785.4252, 740.1614, 2785.4252, 791.3425, 39.3701], ["d70bc7b8d39e771f", "VO4_P", 2, 2785.4252, 740.1614, 2785.4252, 688.9803, 39.3701], ["893a338046efc0d8", "VO4_P", 2, 2785.4252, 740.1614, 2836.9252, 791.6614, 39.3701], ["8d78a303dbcaabfd", "VO4_P", 2, 2198.5315, 885.8307, 2198.5315, 938.9803, 39.3701], ["1858a88e58fccf9d", "VO4_P", 2, 2178.8386, 1023.6181, 2178.8386, 1076.7677, 39.3701], ["c58ed7bb97a78f11", "VO4_P", 2, 2375.689, 1023.6181, 2375.689, 1076.7677, 39.3701], ["d14f9130a2b10ec8", "VO4_P", 2, 2572.5394, 1023.6181, 2619.7834999999995, 1023.6181, 39.3701], ["3155abb857458775", "VO4_P", 2, 2315.7559, 885.8307, 2339.378, 885.8307, 39.3701], ["dbf2ea9c66873db2", "VO4_P", 2, 2383.8583, 885.8307, 2343.4921, 845.4646, 39.3701], ["835c5845f97db7e7", "VO4_P", 2, 2383.8583, 885.8307, 2317.0473, 952.6417000000001, 39.3701], ["94f80215483f8c9c", "VO5_P", 2, 5600.3937, 740.1614, 5600.3937, 791.3425, 39.3701], ["829a53302d04965a", "VO5_P", 2, 5600.3937, 740.1614, 5600.3937, 688.9803, 39.3701], ["f58da464b093e748", "VO5_P", 2, 5600.3937, 740.1614, 5651.8977, 791.6614, 39.3701], ["f1cffba57358ef5f", "VO5_P", 2, 5013.4882, 885.8307, 5013.4882, 938.9803, 39.3701], ["b7254a17fe428a44", "VO5_P", 2, 4993.7992, 1023.6181, 4993.7992, 1076.7677, 39.3701], ["e2b24f7ab0b02d0a", "VO5_P", 2, 5190.649599999999, 1023.6181, 5190.649599999999, 1076.7677, 39.3701], ["3a29a446fb8f13bd", "VO5_P", 2, 5387.5, 1023.6181, 5434.7441, 1023.6181, 39.3701], ["3389e4da367fd4d8", "VO5_P", 2, 5130.7166, 885.8307, 5154.3386, 885.8307, 39.3701], ["e9e72ec76dab7a2e", "VO5_P", 2, 5198.8189, 885.8307, 5158.4528, 845.4646, 39.3701], ["b127942ec5713615", "VO5_P", 2, 5198.8189, 885.8307, 5132.0079, 952.6417000000001, 39.3701], ["4ed79778ddb7b9d9", "GND", 2, 3945.6911, 2307.08, 3971.2018, 2307.08, 11.811], ["763479e003bd9a47", "GND", 2, 663.6696, 3538.6003, 663.6696, 3565.0227, 11.811], ["2828b112fba1c45b", "GND", 2, 3478.6318, 3538.6003, 3478.6318, 3565.0227, 11.811], ["c590b2d3526a2cea", "GND", 2, 6293.59, 3538.6003, 6293.59, 3565.0227, 11.811], ["415b7cc0c409a7d2", "GND", 2, 3788.0296, 1791.3396, 3813.952, 1791.3396, 11.811], ["f6f9da5faab39be9", "GND", 2, 6602.9918, 1791.3396, 6628.9141, 1791.3396, 11.811], ["ba7b8d48bea69c05", "GND", 2, 8361.8859, 2566.9213, 8316.6103, 2566.9213, 15.748], ["972f96c48f6f6106", "GND", 2, 8361.8819, 2314.9567, 8316.6064, 2314.9567, 15.748], ["62e194a825775705", "GND", 2, 936.6142, 3606.2991999999995, 936.6142, 3629.5276000000003, 4.3307], ["9ec9b0ad24887b0e", "GND", 2, 936.6142, 3629.5276000000003, 936.6142, 3638.7796, 11.811], ["944b31032fffaced", "GND", 2, 936.6142, 3638.7796, 927.3622, 3648.0315, 11.811], ["345cce3f202e4f3a", "GND", 2, 895.2756, 3606.2991999999995, 895.2756, 3629.5276000000003, 4.3307], ["831b7964fe7e2e14", "GND", 2, 895.2756, 3629.5276000000003, 895.2756, 3648.0315, 11.811], ["ab90af9386d68638", "GND", 2, 927.3622, 3648.0315, 895.2756, 3648.0315, 11.811], ["39c697caa69ab926", "GND", 2, 867.7165, 3606.2991999999995, 867.7165, 3629.5276000000003, 4.3307], ["a8e8ec69a3f9b8d3", "GND", 2, 867.7165, 3629.5276000000003, 867.7165, 3648.0315, 11.811], ["64dd84fc93329d84", "GND", 2, 895.2756, 3648.0315, 867.7165, 3648.0315, 11.811], ["b850dbf85bc4e916", "GND", 2, 840.1575, 3606.2991999999995, 840.1575, 3629.5276000000003, 4.3307], ["0c62879bad36f43f", "GND", 2, 840.1575, 3629.5276000000003, 840.1575, 3648.0315, 11.811], ["073b932116562472", "GND", 2, 867.7165, 3648.0315, 840.1575, 3648.0315, 11.811], ["cbcebb0da781cc65", "GND", 2, 840.1575, 3648.0315, 785.0394, 3648.0315, 11.811], ["d358799aa9aa7947", "GND", 2, 785.0394, 3606.2991999999995, 785.0394, 3629.5276000000003, 4.3307], ["3918be0968c5aba3", "GND", 2, 785.0394, 3629.5276000000003, 785.0394, 3648.0315, 11.811], ["ea8e3d82b51c2970", "GND", 2, 936.6142, 3689.7638, 936.6142, 3712.9921999999997, 4.3307], ["d614ab076a14ecff", "GND", 2, 936.6142, 3712.9921999999997, 936.6142, 3717.9134, 11.811], ["4b9a961d03be63bc", "GND", 2, 936.6142, 3717.9134, 931.6929, 3722.8346999999994, 11.811], ["6c9713433b83b2df", "GND", 2, 812.5984, 3689.7638, 812.5984, 3712.9921999999997, 4.3307], ["d8b5400b04ee8eac", "GND", 2, 812.5984, 3712.9921999999997, 812.5984, 3722.8346999999994, 11.811], ["8e0d986487d4d3a8", "GND", 2, 931.6929, 3722.8346999999994, 812.5984, 3722.8346999999994, 11.811], ["d278d30c74fb5c6c", "GND", 2, 785.0394, 3689.7638, 785.0394, 3712.9921999999997, 4.3307], ["59dbc8e3dd54a08e", "GND", 2, 785.0394, 3712.9921999999997, 785.0394, 3722.8346999999994, 11.811], ["0a116a7fed4b58e4", "GND", 2, 812.5984, 3722.8346999999994, 785.0394, 3722.8346999999994, 11.811], ["e25031417f57ab55", "GND", 2, 743.7008000000001, 3689.7638, 743.7008000000001, 3712.9921999999997, 4.3307], ["02db9695a6e10be6", "GND", 2, 743.7008000000001, 3712.9921999999997, 743.7008000000001, 3722.8346999999994, 11.811], ["a2f59733334c0de8", "GND", 2, 785.0394, 3722.8346999999994, 743.7008000000001, 3722.8346999999994, 11.811], ["1844a988f003581d", "GND", 2, 688.5827, 3689.7638, 688.5827, 3712.9921999999997, 4.3307], ["02b49f4feb8d54b0", "GND", 2, 688.5827, 3712.9921999999997, 688.5827, 3722.8346999999994, 11.811], ["ff34936997b4b94a", "GND", 2, 743.7008000000001, 3722.8346999999994, 688.5827, 3722.8346999999994, 11.811], ["3c97bc707dd40b92", "GND", 2, 661.0236, 3689.7638, 661.0236, 3712.9921999999997, 4.3307], ["dac79d5d678ab372", "GND", 2, 661.0236, 3712.9921999999997, 661.0236, 3722.8346999999994, 11.811], ["babea650206530cb", "GND", 2, 688.5827, 3722.8346999999994, 661.0236, 3722.8346999999994, 11.811], ["7ffe41c648147c7b", "GND", 2, 661.0236, 3722.8346999999994, 619.685, 3722.8346999999994, 11.811], ["a01078b6c7d2b339", "GND", 2, 619.685, 3689.7638, 619.685, 3712.9921999999997, 4.3307], ["9fd3e4d50815c7f6", "GND", 2, 619.685, 3712.9921999999997, 619.685, 3722.8346999999994, 11.811], ["04f6a8c79ae5b9e3", "GND", 2, 533.8583, 3648.0315, 491.7323, 3648.0315, 11.811], ["5d3a64e609f3ce63", "GND", 2, 3751.5747999999994, 3606.2991999999995, 3751.5747999999994, 3629.5276000000003, 4.3307], ["ce64e1b308ae1ec2", "GND", 2, 3751.5747999999994, 3629.5276000000003, 3751.5747999999994, 3638.7796, 11.811], ["d811966efede9a4b", "GND", 2, 3751.5747999999994, 3638.7796, 3742.3229, 3648.0315, 11.811], ["132da0e54315edfb", "GND", 2, 3710.2362, 3606.2991999999995, 3710.2362, 3629.5276000000003, 4.3307], ["43143b2d761920a8", "GND", 2, 3710.2362, 3629.5276000000003, 3710.2362, 3648.0315, 11.811], ["d7a729893b40dc19", "GND", 2, 3742.3229, 3648.0315, 3710.2362, 3648.0315, 11.811], ["d4310e80f6367e23", "GND", 2, 3682.6772, 3606.2991999999995, 3682.6772, 3629.5276000000003, 4.3307], ["389b3d415fa41981", "GND", 2, 3682.6772, 3629.5276000000003, 3682.6772, 3648.0315, 11.811], ["7ce7ba956dda8a2c", "GND", 2, 3710.2362, 3648.0315, 3682.6772, 3648.0315, 11.811], ["5fe02fb87a995910", "GND", 2, 3655.1181, 3606.2991999999995, 3655.1181, 3629.5276000000003, 4.3307], ["f6d456c81812c6bf", "GND", 2, 3655.1181, 3629.5276000000003, 3655.1181, 3648.0315, 11.811], ["f44de1fd4dac6ec4", "GND", 2, 3682.6772, 3648.0315, 3655.1181, 3648.0315, 11.811], ["4ff2703c81ca412f", "GND", 2, 3655.1181, 3648.0315, 3600, 3648.0315, 11.811], ["59a05a3dea07d2e0", "GND", 2, 3600, 3606.2991999999995, 3600, 3629.5276000000003, 4.3307], ["b3f1753da52586cd", "GND", 2, 3600, 3629.5276000000003, 3600, 3648.0315, 11.811], ["24cb20915cffb799", "GND", 2, 3751.5747999999994, 3689.7638, 3751.5747999999994, 3712.9921999999997, 4.3307], ["aa0cc74a04fcfa9f", "GND", 2, 3751.5747999999994, 3712.9921999999997, 3751.5747999999994, 3717.9134, 11.811], ["7d233fb225d461db", "GND", 2, 3751.5747999999994, 3717.9134, 3746.6536, 3722.8346999999994, 11.811], ["8734e02e50898deb", "GND", 2, 3627.5590999999995, 3689.7638, 3627.5590999999995, 3712.9921999999997, 4.3307], ["5c3cf877ae1f7728", "GND", 2, 3627.5590999999995, 3712.9921999999997, 3627.5590999999995, 3722.8346999999994, 11.811], ["801d3e120cd38bdb", "GND", 2, 3746.6536, 3722.8346999999994, 3627.5590999999995, 3722.8346999999994, 11.811], ["89f33b6cd9da56b0", "GND", 2, 3600, 3689.7638, 3600, 3712.9921999999997, 4.3307], ["8a553f56164a81d6", "GND", 2, 3600, 3712.9921999999997, 3600, 3722.8346999999994, 11.811], ["3c2f47f081d953e2", "GND", 2, 3627.5590999999995, 3722.8346999999994, 3600, 3722.8346999999994, 11.811], ["a4957f6e89b9f875", "GND", 2, 3558.6614, 3689.7638, 3558.6614, 3712.9921999999997, 4.3307], ["942191dcc94f435e", "GND", 2, 3558.6614, 3712.9921999999997, 3558.6614, 3722.8346999999994, 11.811], ["f40683e1526f2cba", "GND", 2, 3600, 3722.8346999999994, 3558.6614, 3722.8346999999994, 11.811], ["a829b210ad7aa241", "GND", 2, 3503.5433000000003, 3689.7638, 3503.5433000000003, 3712.9921999999997, 4.3307], ["4704a15e136db62a", "GND", 2, 3503.5433000000003, 3712.9921999999997, 3503.5433000000003, 3722.8346999999994, 11.811], ["7706acc6278fd59f", "GND", 2, 3558.6614, 3722.8346999999994, 3503.5433000000003, 3722.8346999999994, 11.811], ["3f6f4c9d2276c634", "GND", 2, 3475.9843, 3689.7638, 3475.9843, 3712.9921999999997, 4.3307], ["cee9d95eb8c7559a", "GND", 2, 3475.9843, 3712.9921999999997, 3475.9843, 3722.8346999999994, 11.811], ["a8af9a6bfd2b0fc3", "GND", 2, 3503.5433000000003, 3722.8346999999994, 3475.9843, 3722.8346999999994, 11.811], ["0ac70f9b62a2e677", "GND", 2, 3475.9843, 3722.8346999999994, 3434.6457, 3722.8346999999994, 11.811], ["62e0231a56b0c098", "GND", 2, 3434.6457, 3689.7638, 3434.6457, 3712.9921999999997, 4.3307], ["2e1dc6c389547ec2", "GND", 2, 3434.6457, 3712.9921999999997, 3434.6457, 3722.8346999999994, 11.811], ["8f38574609a2a8b3", "GND", 2, 3348.8189, 3648.0315, 3306.6929, 3648.0315, 11.811], ["f47d1879f2f7a8e1", "GND", 2, 6566.5355, 3606.2991999999995, 6566.5355, 3629.5276000000003, 4.3307], ["0c8aa6d58abaa5a4", "GND", 2, 6566.5355, 3629.5276000000003, 6566.5355, 3638.7796, 11.811], ["9dcad3a3b6a6e78a", "GND", 2, 6566.5355, 3638.7796, 6557.2835, 3648.0315, 11.811], ["03941ffd036a46d4", "GND", 2, 6525.1969, 3606.2991999999995, 6525.1969, 3629.5276000000003, 4.3307], ["3ad10b9ad29e3ef4", "GND", 2, 6525.1969, 3629.5276000000003, 6525.1969, 3648.0315, 11.811], ["f1b0736bdc27bff8", "GND", 2, 6557.2835, 3648.0315, 6525.1969, 3648.0315, 11.811], ["9f8f8c7d20900faf", "GND", 2, 6497.6378, 3606.2991999999995, 6497.6378, 3629.5276000000003, 4.3307], ["fe8f136fb9e25173", "GND", 2, 6497.6378, 3629.5276000000003, 6497.6378, 3648.0315, 11.811], ["b505752ffefcb788", "GND", 2, 6525.1969, 3648.0315, 6497.6378, 3648.0315, 11.811], ["c946b1ca3d02656a", "GND", 2, 6470.0788, 3606.2991999999995, 6470.0788, 3629.5276000000003, 4.3307], ["9f1b45e765e313f9", "GND", 2, 6470.0788, 3629.5276000000003, 6470.0788, 3648.0315, 11.811], ["8d44ed8685127323", "GND", 2, 6497.6378, 3648.0315, 6470.0788, 3648.0315, 11.811], ["8407e68101c17f0c", "GND", 2, 6470.0788, 3648.0315, 6414.9607, 3648.0315, 11.811], ["97e75c8aa0493d8b", "GND", 2, 6414.9607, 3606.2991999999995, 6414.9607, 3629.5276000000003, 4.3307], ["b16a4ae3e5b084b7", "GND", 2, 6414.9607, 3629.5276000000003, 6414.9607, 3648.0315, 11.811], ["04b10264eee9a2cb", "GND", 2, 6566.5355, 3689.7638, 6566.5355, 3712.9921999999997, 4.3307], ["f50a7d58aee8e174", "GND", 2, 6566.5355, 3712.9921999999997, 6566.5355, 3717.9134, 11.811], ["616df58db3eaa129", "GND", 2, 6566.5355, 3717.9134, 6561.6142, 3722.8346999999994, 11.811], ["5c5f5ddf95e96e04", "GND", 2, 6442.519700000001, 3689.7638, 6442.519700000001, 3712.9921999999997, 4.3307], ["152ce223c03ec37a", "GND", 2, 6442.519700000001, 3712.9921999999997, 6442.519700000001, 3722.8346999999994, 11.811], ["0b5c9ce4e09dc4dd", "GND", 2, 6561.6142, 3722.8346999999994, 6442.519700000001, 3722.8346999999994, 11.811], ["77eadaee51e5829d", "GND", 2, 6414.9607, 3689.7638, 6414.9607, 3712.9921999999997, 4.3307], ["9f5467a12f641639", "GND", 2, 6414.9607, 3712.9921999999997, 6414.9607, 3722.8346999999994, 11.811], ["0558ec921211cb29", "GND", 2, 6442.519700000001, 3722.8346999999994, 6414.9607, 3722.8346999999994, 11.811], ["db8be3d017241b6a", "GND", 2, 6373.6221000000005, 3689.7638, 6373.6221000000005, 3712.9921999999997, 4.3307], ["7474987086042cd4", "GND", 2, 6373.6221000000005, 3712.9921999999997, 6373.6221000000005, 3722.8346999999994, 11.811], ["d97d31ac84425025", "GND", 2, 6414.9607, 3722.8346999999994, 6373.6221000000005, 3722.8346999999994, 11.811], ["c3ab0f71f1ee202e", "GND", 2, 6318.504000000001, 3689.7638, 6318.504000000001, 3712.9921999999997, 4.3307], ["dc49f5d60a111d23", "GND", 2, 6318.504000000001, 3712.9921999999997, 6318.504000000001, 3722.8346999999994, 11.811], ["8c8c2fc61714ee18", "GND", 2, 6373.6221000000005, 3722.8346999999994, 6318.504000000001, 3722.8346999999994, 11.811], ["a53d41ea97a0dcd4", "GND", 2, 6290.9449, 3689.7638, 6290.9449, 3712.9921999999997, 4.3307], ["5147e4d2863d8e34", "GND", 2, 6290.9449, 3712.9921999999997, 6290.9449, 3722.8346999999994, 11.811], ["c0d18eb4eecbe734", "GND", 2, 6318.504000000001, 3722.8346999999994, 6290.9449, 3722.8346999999994, 11.811], ["dd80dbb14dc34354", "GND", 2, 6290.9449, 3722.8346999999994, 6249.6063, 3722.8346999999994, 11.811], ["9e5c1fed7ab088c6", "GND", 2, 6249.6063, 3689.7638, 6249.6063, 3712.9921999999997, 4.3307], ["e47d0487288fb127", "GND", 2, 6249.6063, 3712.9921999999997, 6249.6063, 3722.8346999999994, 11.811], ["e4be53693fedbc9e", "GND", 2, 6163.7796, 3648.0315, 6121.6536, 3648.0315, 11.811], ["c4d7a4409289540f", "GND", 2, 3505.9055, 1714.9605999999999, 3505.9055, 1691.7323, 4.3307], ["9087602ca844df00", "GND", 2, 3505.9055, 1691.7323, 3505.9055, 1682.4803, 11.811], ["4d0200e8394a7848", "GND", 2, 3505.9055, 1682.4803, 3515.1575, 1673.2284, 11.811], ["a0874cd5df7a999d", "GND", 2, 3547.2441, 1714.9605999999999, 3547.2441, 1691.7323, 4.3307], ["94b6eb0e453220e9", "GND", 2, 3547.2441, 1691.7323, 3547.2441, 1673.2284, 11.811], ["1b80fff0206a2e40", "GND", 2, 3515.1575, 1673.2284, 3547.2441, 1673.2284, 11.811], ["6258df1876530528", "GND", 2, 3574.8032000000003, 1714.9605999999999, 3574.8032000000003, 1691.7323, 4.3307], ["ca7ab92f4907f8a5", "GND", 2, 3574.8032000000003, 1691.7323, 3574.8032000000003, 1673.2284, 11.811], ["edfe64f88acda958", "GND", 2, 3547.2441, 1673.2284, 3574.8032000000003, 1673.2284, 11.811], ["ea322e3c40ab87df", "GND", 2, 3602.3622, 1714.9605999999999, 3602.3622, 1691.7323, 4.3307], ["79c37aa11d4f9cb3", "GND", 2, 3602.3622, 1691.7323, 3602.3622, 1673.2284, 11.811], ["27e26202967a5019", "GND", 2, 3574.8032000000003, 1673.2284, 3602.3622, 1673.2284, 11.811], ["f22a8a31e1ee542f", "GND", 2, 3602.3622, 1673.2284, 3657.4803, 1673.2284, 11.811], ["a4198303b2fb51e1", "GND", 2, 3657.4803, 1714.9605999999999, 3657.4803, 1691.7323, 4.3307], ["76a08e8e3a4c3b29", "GND", 2, 3657.4803, 1691.7323, 3657.4803, 1673.2284, 11.811], ["54af56048716bee8", "GND", 2, 3505.9055, 1631.4960999999998, 3505.9055, 1608.2677, 4.3307], ["c493d32d0548dddc", "GND", 2, 3505.9055, 1608.2677, 3505.9055, 1603.3465, 11.811], ["c44816ea1724ebc9", "GND", 2, 3505.9055, 1603.3465, 3510.8268, 1598.4251999999997, 11.811], ["b62defb68f8ab4be", "GND", 2, 3629.9213, 1631.4960999999998, 3629.9213, 1608.2677, 4.3307], ["b328be7c5c6527f2", "GND", 2, 3629.9213, 1608.2677, 3629.9213, 1598.4251999999997, 11.811], ["86f2c4baa2b5497d", "GND", 2, 3510.8268, 1598.4251999999997, 3629.9213, 1598.4251999999997, 11.811], ["6edaf0712022d607", "GND", 2, 3657.4803, 1631.4960999999998, 3657.4803, 1608.2677, 4.3307], ["95a6ad73a4d5a26d", "GND", 2, 3657.4803, 1608.2677, 3657.4803, 1598.4251999999997, 11.811], ["08297216e68c3198", "GND", 2, 3629.9213, 1598.4251999999997, 3657.4803, 1598.4251999999997, 11.811], ["e3d4c76775ce8fed", "GND", 2, 3698.8189, 1631.4960999999998, 3698.8189, 1608.2677, 4.3307], ["1a0635778adb3ddb", "GND", 2, 3698.8189, 1608.2677, 3698.8189, 1598.4251999999997, 11.811], ["32679b3405b7c047", "GND", 2, 3657.4803, 1598.4251999999997, 3698.8189, 1598.4251999999997, 11.811], ["8bd83dbf95513b17", "GND", 2, 3753.937, 1631.4960999999998, 3753.937, 1608.2677, 4.3307], ["24b2c5125ca70bf0", "GND", 2, 3753.937, 1608.2677, 3753.937, 1598.4251999999997, 11.811], ["f0025c36636d1f52", "GND", 2, 3698.8189, 1598.4251999999997, 3753.937, 1598.4251999999997, 11.811], ["777ea022f21245d6", "GND", 2, 3781.4961, 1631.4960999999998, 3781.4961, 1608.2677, 4.3307], ["cd566bef11d872cd", "GND", 2, 3781.4961, 1608.2677, 3781.4961, 1598.4251999999997, 11.811], ["b24742819f47b84a", "GND", 2, 3753.937, 1598.4251999999997, 3781.4961, 1598.4251999999997, 11.811], ["8a07e8d5054de395", "GND", 2, 3781.4961, 1598.4251999999997, 3822.8346999999994, 1598.4251999999997, 11.811], ["f020dd46c9a7fb00", "GND", 2, 3822.8346999999994, 1631.4960999999998, 3822.8346999999994, 1608.2677, 4.3307], ["636dc6b57100d23a", "GND", 2, 3822.8346999999994, 1608.2677, 3822.8346999999994, 1598.4251999999997, 11.811], ["bca23e9e0df3a378", "GND", 2, 3908.6614, 1673.2284, 3950.7874, 1673.2284, 11.811], ["370ec68810f27343", "GND", 2, 6320.8662, 1714.9605999999999, 6320.8662, 1691.7323, 4.3307], ["177138fc0ee7bae5", "GND", 2, 6320.8662, 1691.7323, 6320.8662, 1682.4803, 11.811], ["73a98b7604d47528", "GND", 2, 6320.8662, 1682.4803, 6330.118199999999, 1673.2284, 11.811], ["df27ec93da7eab23", "GND", 2, 6362.2048, 1714.9605999999999, 6362.2048, 1691.7323, 4.3307], ["aa80b061bdd11d79", "GND", 2, 6362.2048, 1691.7323, 6362.2048, 1673.2284, 11.811], ["4525046d996469a7", "GND", 2, 6330.118199999999, 1673.2284, 6362.2048, 1673.2284, 11.811], ["4fad57534df26fa9", "GND", 2, 6389.7638, 1714.9605999999999, 6389.7638, 1691.7323, 4.3307], ["77430a411850ba06", "GND", 2, 6389.7638, 1691.7323, 6389.7638, 1673.2284, 11.811], ["16c2220944e21480", "GND", 2, 6362.2048, 1673.2284, 6389.7638, 1673.2284, 11.811], ["44ecf6d3df142ec7", "GND", 2, 6417.3229, 1714.9605999999999, 6417.3229, 1691.7323, 4.3307], ["185bd149a645fa0d", "GND", 2, 6417.3229, 1691.7323, 6417.3229, 1673.2284, 11.811], ["32419072dc0f8069", "GND", 2, 6389.7638, 1673.2284, 6417.3229, 1673.2284, 11.811], ["7ede465d266f8949", "GND", 2, 6417.3229, 1673.2284, 6472.441, 1673.2284, 11.811], ["7db88616d51d4b9a", "GND", 2, 6472.441, 1714.9605999999999, 6472.441, 1691.7323, 4.3307], ["5fd763014d5b19d9", "GND", 2, 6472.441, 1691.7323, 6472.441, 1673.2284, 11.811], ["55824a1c657ab01b", "GND", 2, 6320.8662, 1631.4960999999998, 6320.8662, 1608.2677, 4.3307], ["94cc3a2960a6d3f6", "GND", 2, 6320.8662, 1608.2677, 6320.8662, 1603.3465, 11.811], ["803dab5b8217666b", "GND", 2, 6320.8662, 1603.3465, 6325.7874, 1598.4251999999997, 11.811], ["a7d5281dc9cdc97b", "GND", 2, 6444.8819, 1631.4960999999998, 6444.8819, 1608.2677, 4.3307], ["485badc871363dca", "GND", 2, 6444.8819, 1608.2677, 6444.8819, 1598.4251999999997, 11.811], ["d2e9808c49223e2d", "GND", 2, 6325.7874, 1598.4251999999997, 6444.8819, 1598.4251999999997, 11.811], ["259a16d7230802d7", "GND", 2, 6472.441, 1631.4960999999998, 6472.441, 1608.2677, 4.3307], ["3da64fd60135943d", "GND", 2, 6472.441, 1608.2677, 6472.441, 1598.4251999999997, 11.811], ["6b52497885694047", "GND", 2, 6444.8819, 1598.4251999999997, 6472.441, 1598.4251999999997, 11.811], ["da6386a5129535e8", "GND", 2, 6513.7796, 1631.4960999999998, 6513.7796, 1608.2677, 4.3307], ["91fcc46894832b8b", "GND", 2, 6513.7796, 1608.2677, 6513.7796, 1598.4251999999997, 11.811], ["aa024f07a3889943", "GND", 2, 6472.441, 1598.4251999999997, 6513.7796, 1598.4251999999997, 11.811], ["76141a20d4d0ece9", "GND", 2, 6568.8976999999995, 1631.4960999999998, 6568.8976999999995, 1608.2677, 4.3307], ["91a52f142860b197", "GND", 2, 6568.8976999999995, 1608.2677, 6568.8976999999995, 1598.4251999999997, 11.811], ["625fb315feaee6db", "GND", 2, 6513.7796, 1598.4251999999997, 6568.8976999999995, 1598.4251999999997, 11.811], ["06b0a4ba214999b6", "GND", 2, 6596.4567, 1631.4960999999998, 6596.4567, 1608.2677, 4.3307], ["cdf7c5889b3ef57e", "GND", 2, 6596.4567, 1608.2677, 6596.4567, 1598.4251999999997, 11.811], ["20fe09d293831bae", "GND", 2, 6568.8976999999995, 1598.4251999999997, 6596.4567, 1598.4251999999997, 11.811], ["a4e81b5f84d9debf", "GND", 2, 6596.4567, 1598.4251999999997, 6637.7953, 1598.4251999999997, 11.811], ["fe310e007860a9a3", "GND", 2, 6637.7953, 1631.4960999999998, 6637.7953, 1608.2677, 4.3307], ["e9ef1dfc76bda6c2", "GND", 2, 6637.7953, 1608.2677, 6637.7953, 1598.4251999999997, 11.811], ["5f7e46c57c0ea4bd", "GND", 2, 6723.6221000000005, 1673.2284, 6765.7481, 1673.2284, 11.811], ["348e78f0c33b03ef", "THERM_1", 2, 853.9369999999999, 3606.2991999999995, 853.9369999999999, 3585.8268, 4.3307], ["67aa5568a308f20e", "THERM_1", 2, 853.9369999999999, 3585.8268, 838.189, 3570.0788000000002, 4.3307], ["3c85ce288b6e0237", "THERM_1", 2, 838.189, 3570.0788000000002, 838.189, 3557.4803, 7.874], ["ed550fc22b55b6d4", "THERM_1", 1, 838.189, 3557.4803, 697.7558999999999, 3557.4803, 7.874], ["2f8b557f419789f3", "THERM_1", 2, 697.7558999999999, 3557.4803, 697.7558999999999, 3533.8583, 7.874], ["cfb60b3fd0d87886", "THERM_1", 2, 697.748, 3529.9213, 720.7126, 3529.9213, 7.874], ["eae5520fba963e9d", "THERM_1", 2, 700.7874000000002, 3531.4961, 720.7126, 3529.9213, 7.874], ["58787a24f8986bad", "THERM_2", 2, 3668.8977, 3606.2991999999995, 3668.8977, 3585.8268, 4.3307], ["75e4b3015c0738e0", "THERM_2", 2, 3668.8977, 3585.8268, 3653.1496000000006, 3570.0788000000002, 4.3307], ["62468025c85d955e", "THERM_2", 2, 3653.1496000000006, 3570.0788000000002, 3653.1496000000006, 3557.4803, 7.874], ["4a57cb5e43064323", "THERM_2", 1, 3653.1496000000006, 3557.4803, 3512.7165999999997, 3557.4803, 7.874], ["914a8f5858c3e158", "THERM_2", 2, 3512.7165999999997, 3557.4803, 3512.7165999999997, 3533.8583, 7.874], ["ed0b53e87ed0d3b8", "THERM_2", 2, 3512.7087, 3529.9213, 3535.6693, 3529.9213, 7.874], ["8c577dc71e92cf84", "THERM_2", 2, 3515.7481, 3531.4961, 3535.6693, 3529.9213, 7.874], ["bfb3776983166a33", "THERM_3", 2, 6483.8583, 3606.2991999999995, 6483.8583, 3585.8268, 4.3307], ["ff11ff94d702f14d", "THERM_3", 2, 6483.8583, 3585.8268, 6468.1103, 3570.0788000000002, 4.3307], ["4278306d4f0cb49d", "THERM_3", 2, 6468.1103, 3570.0788000000002, 6468.1103, 3557.4803, 7.874], ["3b98f89e04011666", "THERM_3", 1, 6468.1103, 3557.4803, 6327.6772, 3557.4803, 7.874], ["63825d3359fb04d1", "THERM_3", 2, 6327.6772, 3557.4803, 6327.6772, 3533.8583, 7.874], ["7dde5cc2b574e85f", "THERM_3", 2, 6327.6693, 3529.9213, 6350.63, 3529.9213, 7.874], ["a6eeae5e79e72ffb", "THERM_3", 2, 6330.7087, 3531.4961, 6350.63, 3529.9213, 7.874], ["887c087ac5395cb8", "THERM_4", 2, 3588.5827, 1714.9605999999999, 3588.5827, 1735.4331, 4.3307], ["5fe3c84043cac55e", "THERM_4", 2, 3588.5827, 1735.4331, 3604.3307, 1751.1811, 4.3307], ["55a3306bc615297d", "THERM_4", 2, 3604.3307, 1751.1811, 3604.3307, 1763.7795, 7.874], ["5078396c2dcf0de5", "THERM_4", 1, 3604.3307, 1763.7795, 3744.7638, 1763.7795, 7.874], ["f94f521cd5d5d8bf", "THERM_4", 2, 3744.7638, 1763.7795, 3744.7638, 1787.4016000000001, 7.874], ["eb6564b81459402e", "THERM_4", 2, 3744.7717000000002, 1791.3386, 3721.8071, 1791.3386, 7.874], ["e2a8f20e8d7f4028", "THERM_4", 2, 3742.126, 1789.3701, 3721.8071, 1791.3386, 7.874], ["bda60d30fbd3baa7", "THERM_5", 2, 6403.5433, 1714.9605999999999, 6403.5433, 1735.4331, 4.3307], ["34005a6195691026", "THERM_5", 2, 6403.5433, 1735.4331, 6419.2914, 1751.1811, 4.3307], ["7665eb7abda641a9", "THERM_5", 2, 6419.2914, 1751.1811, 6419.2914, 1763.7795, 7.874], ["f82e2c76a142c45a", "THERM_5", 1, 6419.2914, 1763.7795, 6559.7245, 1763.7795, 7.874], ["08ac81b8e8ed0e10", "THERM_5", 2, 6559.7245, 1763.7795, 6559.7245, 1787.4016000000001, 7.874], ["8c53ee980c5c9134", "THERM_5", 2, 6559.7284, 1791.3386, 6536.7678, 1791.3386, 7.874], ["828fd8bb8e47bbec", "THERM_5", 2, 6557.0867, 1789.3701, 6536.7678, 1791.3386, 7.874], ["7b33b07b2f643f1b", "CC1_1", 2, 798.8189, 3606.2991999999995, 798.8189, 3583.0709, 4.3307], ["f412277ed7d01886", "CC1_1", 2, 798.8189, 3583.0709, 798.8189, 3533.8583, 7.874], ["8303d85bfec65f23", "CC1_1", 2, 798.811, 3529.9213, 821.7717, 3529.9213, 7.874], ["d76761adb3d1ee60", "CC1_1", 2, 799.2125999999998, 3531.4961, 821.7717, 3529.9213, 7.874], ["a318bf622e7452b9", "CC1_2", 2, 3613.7796, 3606.2991999999995, 3613.7796, 3583.0709, 4.3307], ["a36ef39be51d0094", "CC1_2", 2, 3613.7796, 3583.0709, 3613.7796, 3533.8583, 7.874], ["a481f4cca691adf1", "CC1_2", 2, 3613.7717, 3529.9213, 3636.7322999999997, 3529.9213, 7.874], ["f3baa9fa88be4806", "CC1_2", 2, 3614.1733, 3531.4961, 3636.7322999999997, 3529.9213, 7.874], ["efbf455064084410", "CC1_3", 2, 6428.7402, 3606.2991999999995, 6428.7402, 3583.0709, 4.3307], ["89ef922d899afef1", "CC1_3", 2, 6428.7402, 3583.0709, 6428.7402, 3533.8583, 7.874], ["aafef9054630fbd5", "CC1_3", 2, 6428.7284, 3529.9213, 6451.693, 3529.9213, 7.874], ["f0ed1eaa44937dc9", "CC1_3", 2, 6429.133899999999, 3531.4961, 6451.693, 3529.9213, 7.874], ["f9620d7e1832686b", "CC1_4", 2, 3643.7008000000005, 1714.9605999999999, 3643.7008000000005, 1738.189, 4.3307], ["d90a5719a7bac19a", "CC1_4", 2, 3643.7008000000005, 1738.189, 3643.7008000000005, 1787.4016000000001, 7.874], ["7d9d09f0f97b5cea", "CC1_4", 2, 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3740.1600000000003, 2925.2, 0, ["RECT", 55.5, 53.1, 0]], ["J23", "B8", "", 2, 8361.885, 2509.84, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A5", "$16N222", 2, 8361.885, 2490.1499999999996, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B7", "UP_DM", 2, 8361.885, 2470.47, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A6", "UP_DP", 2, 8361.885, 2450.78, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A7", "UP_DM", 2, 8361.885, 2431.1, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B6", "UP_DP", 2, 8361.885, 2411.41, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A8", "", 2, 8361.885, 2391.7400000000002, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "B5", "$16N224", 2, 8361.885, 2372.04, -1.570796326794897, ["RECT", 11.8, 51.2, 0]], ["J23", "A1B12", "GND", 2, 8361.885, 2566.92, -1.570796326794897, ["POLYGON", [8387.473, 2555.112, "L", 8336.291, 2555.112, 8336.291, 2566.923, 8336.297, 2566.923, 8336.297, 2578.733, 8387.479, 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822.8381, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "19", "GND", 2, 809.0586000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "20", "", 2, 809.0586000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "21", "", 2, 795.2791000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "22", "CC1_1", 2, 795.2791000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "23", "GND", 2, 781.4995, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "24", "GND", 2, 781.4995, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "25", "", 2, 767.72, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "26", "", 2, 767.72, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "27", "", 2, 753.9405, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "28", "", 2, 753.9405, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "29", "GND", 2, 740.1609000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "30", "", 2, 740.1609000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "31", "", 2, 726.3814000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "32", "", 2, 726.3814000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "33", "", 2, 712.6019000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "34", "", 2, 712.6019000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "35", "", 2, 698.8224000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "36", "", 2, 698.8224000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "37", "GND", 2, 685.0428, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "38", "", 2, 685.0428, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "39", "", 2, 671.2633000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "40", "", 2, 671.2633000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "41", "GND", 2, 657.4838000000001, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "42", "", 2, 657.4838000000001, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "43", "", 2, 643.7043, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "44", "", 2, 643.7043, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "45", "", 2, 629.9247, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "46", "", 2, 629.9247, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J71", "47", "GND", 2, 616.1452, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 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0]], ["J72", "6", "USB2_DPJ", 2, 3720.4753, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "7", "", 2, 3706.6956999999998, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "8", "GND", 2, 3706.6956999999998, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "9", "", 2, 3692.9161999999997, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "10", "", 2, 3692.9161999999997, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "11", "", 2, 3679.1366999999996, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "12", "GND", 2, 3679.1366999999996, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "13", "", 2, 3665.3571999999995, 3663.7823000000003, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "14", "THERM_2", 2, 3665.3571999999995, 3580.3177000000005, 3.141592653589793, ["RECT", 7.1, 18.9, 0]], ["J72", "15", "", 2, 3651.5776, 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4045.2750000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "52", "+3V3_HUB", 2, 4025.5950000000003, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "53", "", 2, 4005.905, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "54", "", 2, 3986.225, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "55", "", 2, 3966.535, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "56", "", 2, 3946.8550000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "57", "+3V3_HUB", 2, 3927.165, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "58", "UP_DM", 2, 3907.4850000000006, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "59", "UP_DP", 2, 3887.7950000000005, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "60", "XTAL2", 2, 3868.1150000000002, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "61", "XTAL1", 2, 3848.425, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "62", "VDD18PLL", 2, 3828.745, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "63", "RBIAS", 2, 3809.0550000000003, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "64", "+3V3_HUB", 2, 3789.375, 2501.973, 0, ["OVAL", 11.8, 33.5]], ["U32", "65", "GND", 2, 3937.0150000000003, 2677.173, -1.5707963267948966, ["RECT", 189, 189, 0]], ["U51", "1", "USB1_DMJ", 2, 875.99, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "2", "GND", 2, 913.39, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "3", "USB1_DPJ", 2, 950.79, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "4", "USB1_DP", 2, 950.79, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "5", "VBUS1", 2, 913.39, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U51", "6", "USB1_DM", 2, 875.99, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "1", "USB2_DMJ", 2, 3690.95, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "2", "GND", 2, 3728.35, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "3", "USB2_DPJ", 2, 3765.75, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "4", "USB2_DP", 2, 3765.75, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "5", "VBUS2", 2, 3728.35, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U52", "6", "USB2_DM", 2, 3690.95, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "1", "USB3_DMJ", 2, 6505.91, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "2", "GND", 2, 6543.31, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "3", "USB3_DPJ", 2, 6580.71, 3490.12, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "4", "USB3_DP", 2, 6580.71, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "5", "VBUS3", 2, 6543.31, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U53", "6", "USB3_DM", 2, 6505.91, 3399.64, 0, ["RECT", 20.9, 42.2, 0]], ["U54", "1", "USB4_DMJ", 2, 3562.9900000000002, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "2", "GND", 2, 3525.59, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "3", "USB4_DPJ", 2, 3488.19, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "4", "USB4_DP", 2, 3488.19, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "5", "VBUS4", 2, 3525.59, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U54", "6", "USB4_DM", 2, 3562.9900000000002, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "1", "USB5_DMJ", 2, 6377.950000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "2", "GND", 2, 6340.550000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "3", "USB5_DPJ", 2, 6303.150000000001, 1805.15, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "4", "USB5_DP", 2, 6303.150000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "5", "VBUS5", 2, 6340.550000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["U55", "6", "USB5_DM", 2, 6377.950000000001, 1895.63, 3.141592653589793, ["RECT", 20.9, 42.2, 0]], ["Y1", "1", "XTAL1", 2, 3728.34, 2348.425, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "2", "GND", 2, 3814.9600000000005, 2348.425, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "3", "XTAL2", 2, 3814.9600000000005, 2281.4950000000003, 0, ["RECT", 55.1, 47.2, 0]], ["Y1", "4", "GND", 2, 3728.34, 2281.4950000000003, 0, ["RECT", 55.1, 47.2, 0]], ["J84", "1", "VO4_P", 2, 2383.8597999999997, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "2", "GND", 2, 2462.5998999999997, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "3", "$24N121", 2, 2541.3400999999994, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J84", "4", "$24N122", 2, 2620.0802, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["C736", "2", "+5V", 2, 3208.66, 2303.15, 0, ["RECT", 55.5, 53.1, 0]], ["C736", "1", "GND", 2, 3129.9199999999996, 2303.15, 0, ["RECT", 55.5, 53.1, 0]], ["R784", "2", "$24N121", 2, 2782.79, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R784", "1", "GND", 2, 2748.71, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R743", "2", "EDL_EN3", 2, 7089.26, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R743", "1", "GND", 2, 7123.339999999999, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C760", "2", "+3V3_HUB", 2, 2460.63, 2378.74, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C760", "1", "GND", 2, 2460.63, 2345.66, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["Q405", "1", "$24N135", 2, 2253.9400000000005, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q405", "2", "GND", 2, 2253.9400000000005, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q405", "3", "POGO4_VDN", 2, 2175.2000000000003, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["C761", "2", "+3V3_HUB", 2, 1164.56, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C761", "1", "GND", 2, 1197.6399999999999, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C762", "2", "+3V3_HUB", 2, 3979.52, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C762", "1", "GND", 2, 4012.6, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["U21", "1", "K1_PWR", 2, 4411.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "2", "K1_VUP", 2, 4461.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "3", "K1_VDN", 2, 4511.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "4", "", 2, 4561.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "5", "EDL_EN5", 2, 4611.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "6", "EDL_EN3", 2, 4661.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "7", "EDL_EN2", 2, 4711.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "8", "GND", 2, 4761.61, 2725.8100000000004, 0, ["OVAL", 23.7, 77.6]], ["U21", "16", "+3V3_HUB", 2, 4411.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "15", "EDL_EN4", 2, 4461.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "14", "KEY_SER", 2, 4511.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "13", "KEY_OE#", 2, 4561.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "12", "KEY_RCLK", 2, 4611.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "11", "KEY_SRCLK", 2, 4661.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "10", "+3V3_HUB", 2, 4711.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["U21", "9", "SR_CAS", 2, 4761.61, 2510.4100000000003, 0, ["OVAL", 23.7, 77.6]], ["C833", "2", "VO4_P", 2, 2178.8399999999997, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C833", "1", "GND", 2, 2053.4399999999996, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C801", "2", "GND", 2, 1314.9550000000002, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C801", "1", "VO1_P", 2, 1653.545, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C834", "2", "VO4_P", 2, 2375.69, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C834", "1", "GND", 2, 2250.2899999999995, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C802", "2", "VO1_P", 2, 2240.45, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C802", "1", "GND", 2, 2365.85, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C835", "2", "VO4_P", 2, 2572.54, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C835", "1", "GND", 2, 2447.14, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C803", "2", "VO1_P", 2, 2260.1299999999997, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C803", "1", "GND", 2, 2385.5299999999997, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C836", "2", "VO4_P", 2, 2309.85, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C836", "1", "GND", 2, 2276.77, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C804", "2", "VO1_P", 2, 2063.28, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C804", "1", "GND", 2, 2188.6800000000003, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C805", "2", "VO1_P", 2, 1866.43, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C805", "1", "GND", 2, 1991.8300000000002, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["Q403", "1", "$24N125", 2, 1978.3500000000001, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q403", "2", "GND", 2, 1978.3500000000001, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q403", "3", "POGO4_PWR", 2, 1899.61, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["C806", "2", "VO1_P", 2, 2129.13, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C806", "1", "GND", 2, 2162.21, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["J64", "4", "GND", 2, 4188, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J64", "3", "GND", 2, 3941.92, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J64", "2", "$24N140", 2, 4089.5099999999998, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["J64", "1", "$24N139", 2, 4040.31, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["C811", "2", "GND", 2, 4129.915, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C811", "1", "VO2_P", 2, 4468.505, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["U44", "3", "", 2, 3173.2299999999996, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "2", "GND", 2, 3173.2299999999996, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "1", "$24N139", 2, 3173.2299999999996, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "6", "EDL_EN4", 2, 3066.93, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "5", "+3V3_HUB", 2, 3066.93, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U44", "4", "$24N140", 2, 3066.93, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["C812", "2", "VO2_P", 2, 5055.41, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C812", "1", "GND", 2, 5180.81, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["R744", "2", "EDL_EN4", 2, 2979.64, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["R744", "1", "GND", 2, 2945.56, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["C813", "2", "VO2_P", 2, 5075.1, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C813", "1", "GND", 2, 5200.5, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C764", "2", "+3V3_HUB", 2, 3274.41, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C764", "1", "GND", 2, 3241.33, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C814", "2", "VO2_P", 2, 4878.24, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C814", "1", "GND", 2, 5003.639999999999, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["J85", "1", "VO5_P", 2, 5198.8198, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "2", "GND", 2, 5277.5599, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "3", "$25N121", 2, 5356.3000999999995, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["J85", "4", "$25N122", 2, 5435.0401999999995, 885.8299999999999, 0, ["RECT", 43.3, 157.5, 0]], ["C815", "2", "VO2_P", 2, 4681.39, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C815", "1", "GND", 2, 4806.79, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["R785", "2", "$25N121", 2, 5597.75, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R785", "1", "GND", 2, 5563.670000000001, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["C816", "2", "VO2_P", 2, 4944.09, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C816", "1", "GND", 2, 4977.17, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C821", "2", "GND", 2, 6944.875000000001, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["C821", "1", "VO3_P", 2, 7283.465, 4555.12, 3.141592653589793, ["RECT", 169.3, 65, 0]], ["Q504", "1", "$25N130", 2, 4931.099999999999, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q504", "2", "GND", 2, 4931.099999999999, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q504", "3", "POGO5_VUP", 2, 4852.36, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["C822", "2", "VO3_P", 2, 7870.370000000001, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C822", "1", "GND", 2, 7995.77, 4409.45, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["R522", "2", "K5_VUP", 2, 4891.73, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R522", "1", "$25N130", 2, 4891.73, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["C823", "2", "VO3_P", 2, 7890.060000000001, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C823", "1", "GND", 2, 8015.460000000001, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["R523", "2", "GND", 2, 4891.73, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R523", "1", "$25N130", 2, 4891.73, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["C824", "2", "VO3_P", 2, 7693.21, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C824", "1", "GND", 2, 7818.61, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C825", "2", "VO3_P", 2, 7496.360000000001, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["C825", "1", "GND", 2, 7621.76, 4271.65, 3.141592653589793, ["RECT", 58.5, 68, 0]], ["Q505", "1", "$25N135", 2, 5068.9, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q505", "2", "GND", 2, 5068.9, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q505", "3", "POGO5_VDN", 2, 4990.16, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["C826", "2", "VO3_P", 2, 7759.049999999999, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C826", "1", "GND", 2, 7792.129999999999, 4409.45, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["U33", "1", "K2_VUP", 2, 7510.41, 2521.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "2", "K2_VDN", 2, 7510.41, 2571.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "3", "K2_PWR", 2, 7510.41, 2621.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "4", "K3_VDN", 2, 7510.41, 2671.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "5", "K3_VUP", 2, 7510.41, 2721.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "6", "K3_PWR", 2, 7510.41, 2771.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "7", "HUB_RST", 2, 7510.41, 2821.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "8", "GND", 2, 7510.41, 2871.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "16", "+3V3_HUB", 2, 7725.8099999999995, 2521.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "15", "EDL_EN1", 2, 7725.8099999999995, 2571.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "14", "SR_CAS2", 2, 7725.8099999999995, 2621.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "13", "KEY_OE#", 2, 7725.8099999999995, 2671.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "12", "KEY_RCLK", 2, 7725.8099999999995, 2721.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "11", "KEY_SRCLK", 2, 7725.8099999999995, 2771.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "10", "+3V3_HUB", 2, 7725.8099999999995, 2821.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["U33", "9", "", 2, 7725.8099999999995, 2871.85, 1.5707963267948966, ["OVAL", 23.7, 77.6]], ["C739", "2", "+3V3_HUB", 2, 7854.33, 2713.39, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["C739", "1", "GND", 2, 7854.33, 2680.31, 1.5707963267948966, ["RECT", 19.7, 21.3, 0]], ["R609", "2", "+3V3_HUB", 2, 4839.87, 2874.02, 0, ["RECT", 22.3, 21.3, 0]], ["R609", "1", "KEY_OE#", 2, 4805.79, 2874.02, 0, ["RECT", 22.3, 21.3, 0]], ["J31", "1", "VO1_P", 12, 1490.94, 2707.48, 0, ["RECT", 66.9, 66.9, 0]], ["J31", "2", "GND", 12, 1490.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "3", "VO1_P", 12, 1590.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "4", "GND", 12, 1590.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "5", "VO1_P", 12, 1690.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "6", "GND", 12, 1690.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "7", "+5V", 12, 1790.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "8", "GND", 12, 1790.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "9", "+5V", 12, 1890.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "10", "GND", 12, 1890.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "11", "GND", 12, 1990.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "12", "GND", 12, 1990.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "13", "GND", 12, 2090.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "14", "GND", 12, 2090.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "15", "GND", 12, 2190.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "16", "GND", 12, 2190.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "17", "GND", 12, 2290.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "18", "GND", 12, 2290.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "19", "VBUS_EN1", 12, 2390.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "20", "VBUS_EN4", 12, 2390.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "21", "SDA", 12, 2490.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "22", "+5V", 12, 2490.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "23", "SCL", 12, 2590.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "24", "+5V", 12, 2590.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "25", "GND", 12, 2690.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "26", "UP_VBUS_DET", 12, 2690.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "27", "GND", 12, 2790.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "28", "GND", 12, 2790.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "29", "GND", 12, 2890.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "30", "VO4_P", 12, 2890.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "31", "GND", 12, 2990.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "32", "VO4_P", 12, 2990.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "33", "GND", 12, 3090.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "34", "VO4_P", 12, 3090.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "35", "VO2_P", 12, 3190.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "36", "GND", 12, 3190.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "37", "VO2_P", 12, 3290.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "38", "GND", 12, 3290.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "39", "VO2_P", 12, 3390.94, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J31", "40", "GND", 12, 3390.94, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J63", "4", "GND", 2, 5880.900000000001, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J63", "3", "GND", 2, 6126.98, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J63", "2", "$23N140", 2, 5979.389999999999, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J63", "1", "$23N139", 2, 6028.59, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J32", "1", "+5V", 12, 5270.47, 2707.48, 0, ["RECT", 66.9, 66.9, 0]], ["J32", "2", "+5V", 12, 5270.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "3", "+5V", 12, 5370.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "4", "+5V", 12, 5370.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "5", "KEY_SER", 12, 5470.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "6", "VBUS_EN5", 12, 5470.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "7", "KEY_SRCLK", 12, 5570.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "8", "GND", 12, 5570.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "9", "KEY_RCLK", 12, 5670.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "10", "GND", 12, 5670.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "11", "KEY_OE#", 12, 5770.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "12", "GND", 12, 5770.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "13", "VBUS_EN2", 12, 5870.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "14", "GND", 12, 5870.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "15", "GND", 12, 5970.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "16", "GND", 12, 5970.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "17", "GND", 12, 6070.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "18", "VO5_P", 12, 6070.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "19", "GND", 12, 6170.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "20", "VO5_P", 12, 6170.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "21", "GND", 12, 6270.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "22", "VO5_P", 12, 6270.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "23", "GND", 12, 6370.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "24", "GND", 12, 6370.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "25", "GND", 12, 6470.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "26", "GND", 12, 6470.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "27", "GND", 12, 6570.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "28", "GND", 12, 6570.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "29", "VO3_P", 12, 6670.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "30", "GND", 12, 6670.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "31", "VO3_P", 12, 6770.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "32", "GND", 12, 6770.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "33", "VO3_P", 12, 6870.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "34", "GND", 12, 6870.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "35", "GND", 12, 6970.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "36", "GND", 12, 6970.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "37", "VBUS_EN3", 12, 7070.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "38", "GND", 12, 7070.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "39", "+5V", 12, 7170.47, 2707.48, 0, ["ELLIPSE", 66.9, 66.9]], ["J32", "40", "+5V", 12, 7170.47, 2607.48, 0, ["ELLIPSE", 66.9, 66.9]], ["R420", "2", "K4_PWR", 2, 1938.98, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R420", "1", "$24N125", 2, 1938.98, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R421", "2", "GND", 2, 1938.98, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R421", "1", "$24N125", 2, 1938.98, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["Q404", "1", "$24N130", 2, 2116.14, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q404", "2", "GND", 2, 2116.14, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q404", "3", "POGO4_VUP", 2, 2037.3999999999999, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["R795", "2", "$25N122", 2, 5676.489999999999, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R795", "1", "GND", 2, 5642.41, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["C841", "2", "GND", 2, 5938.984999999999, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C841", "1", "VO5_P", 2, 5600.3949999999995, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C842", "2", "VO5_P", 2, 5013.49, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C842", "1", "GND", 2, 4888.09, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C843", "2", "VO5_P", 2, 4993.8, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C843", "1", "GND", 2, 4868.400000000001, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["R524", "2", "K5_VDN", 2, 5029.53, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R524", "1", "$25N135", 2, 5029.53, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R525", "2", "GND", 2, 5029.53, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R525", "1", "$25N135", 2, 5029.53, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["J65", "4", "GND", 2, 7002.959999999999, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J65", "3", "GND", 2, 6756.88, 1966.525, 0, ["RECT", 82.7, 118.1, 0]], ["J65", "2", "$25N140", 2, 6904.47, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["J65", "1", "$25N139", 2, 6855.2699999999995, 1852.3749999999998, 0, ["RECT", 31.5, 63, 0]], ["R422", "2", "K4_VUP", 2, 2076.77, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R422", "1", "$24N130", 2, 2076.77, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["J61", "4", "GND", 2, 250.98, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J61", "3", "GND", 2, 497.06000000000006, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J61", "2", "$21N158", 2, 349.47, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J61", "1", "$21N157", 2, 398.6700000000001, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["C844", "2", "VO5_P", 2, 5190.65, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C844", "1", "GND", 2, 5065.25, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["J62", "4", "GND", 2, 3065.9400000000005, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J62", "3", "GND", 2, 3312.02, 3328.755, 3.141592653589793, ["RECT", 82.7, 118.1, 0]], ["J62", "2", "$22N140", 2, 3164.4300000000003, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["J62", "1", "$22N139", 2, 3213.63, 3442.9049999999997, 3.141592653589793, ["RECT", 31.5, 63, 0]], ["U45", "3", "", 2, 5988.1900000000005, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "2", "GND", 2, 5988.1900000000005, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "1", "$25N139", 2, 5988.1900000000005, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "6", "EDL_EN5", 2, 5881.889999999999, 1159.4499999999998, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "5", "+3V3_HUB", 2, 5881.889999999999, 1122.05, 0, ["RECT", 43.3, 23.6, 0]], ["U45", "4", "$25N140", 2, 5881.889999999999, 1084.65, 0, ["RECT", 43.3, 23.6, 0]], ["R794", "2", "$24N122", 2, 2861.5299999999997, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["R794", "1", "GND", 2, 2827.4499999999994, 1023.6199999999999, 0, ["RECT", 22.3, 21.3, 0]], ["J81", "1", "VO1_P", 2, 2055.1202000000003, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "2", "GND", 2, 1976.3800999999999, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "3", "$21N139", 2, 1897.6399000000001, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J81", "4", "$21N140", 2, 1818.8997999999997, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["R424", "2", "K4_VDN", 2, 2214.57, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R424", "1", "$24N135", 2, 2214.57, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["J82", "1", "VO2_P", 2, 4870.0802, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "2", "GND", 2, 4791.340099999999, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "3", "$22N121", 2, 4712.5999, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J82", "4", "$22N122", 2, 4633.8598, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["Q503", "1", "$25N125", 2, 4793.3099999999995, 490.15999999999997, 0, ["RECT", 39.4, 25.6, 0]], ["Q503", "2", "GND", 2, 4793.3099999999995, 415.35999999999996, 0, ["RECT", 39.4, 25.6, 0]], ["Q503", "3", "POGO5_PWR", 2, 4714.57, 452.76, 0, ["RECT", 39.4, 25.6, 0]], ["J83", "1", "VO3_P", 2, 7685.0401999999995, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "2", "GND", 2, 7606.3000999999995, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "3", "$23N121", 2, 7527.5599, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["J83", "4", "$23N122", 2, 7448.8198, 4409.45, 3.141592653589793, ["RECT", 43.3, 157.5, 0]], ["C604", "2", "+3V3_HUB", 2, 4622.84, 2874.02, 0, ["RECT", 19.7, 21.3, 0]], ["C604", "1", "GND", 2, 4589.76, 2874.02, 0, ["RECT", 19.7, 21.3, 0]], ["Q103", "1", "$21N143", 2, 2460.63, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q103", "2", "GND", 2, 2460.63, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q103", "3", "POGO1_PWR", 2, 2539.37, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q104", "1", "$21N148", 2, 2322.8299999999995, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q104", "2", "GND", 2, 2322.8299999999995, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q104", "3", "POGO1_VUP", 2, 2401.5699999999997, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q105", "1", "$21N153", 2, 2185.0399999999995, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q105", "2", "GND", 2, 2185.0399999999995, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q105", "3", "POGO1_VDN", 2, 2263.7799999999997, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q203", "1", "$22N125", 2, 5275.59, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q203", "2", "GND", 2, 5275.59, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q203", "3", "POGO2_PWR", 2, 5354.33, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q204", "1", "$22N130", 2, 5137.799999999999, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q204", "2", "GND", 2, 5137.799999999999, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q204", "3", "POGO2_VUP", 2, 5216.54, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q205", "1", "$22N135", 2, 5000, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q205", "2", "GND", 2, 5000, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q205", "3", "POGO2_VDN", 2, 5078.74, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q303", "1", "$23N125", 2, 8090.549999999999, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q303", "2", "GND", 2, 8090.549999999999, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q303", "3", "POGO3_PWR", 2, 8169.29, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q304", "1", "$23N130", 2, 7952.759999999999, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q304", "2", "GND", 2, 7952.759999999999, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q304", "3", "POGO3_VUP", 2, 8031.5, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q305", "1", "$23N135", 2, 7814.96, 4805.120000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q305", "2", "GND", 2, 7814.96, 4879.920000000001, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["Q305", "3", "POGO3_VDN", 2, 7893.7, 4842.52, 3.141592653589793, ["RECT", 39.4, 25.6, 0]], ["R120", "2", "K1_PWR", 2, 2500, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R120", "1", "$21N143", 2, 2500, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R121", "2", "GND", 2, 2500, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R121", "1", "$21N143", 2, 2500, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R122", "2", "K1_VUP", 2, 2362.2, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R122", "1", "$21N148", 2, 2362.2, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R123", "2", "GND", 2, 2362.2, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R123", "1", "$21N148", 2, 2362.2, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R124", "2", "K1_VDN", 2, 2224.41, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R124", "1", "$21N153", 2, 2224.41, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R125", "2", "GND", 2, 2224.41, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R125", "1", "$21N153", 2, 2224.41, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R220", "2", "K2_PWR", 2, 5314.96, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R220", "1", "$22N125", 2, 5314.96, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R221", "2", "GND", 2, 5314.96, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R221", "1", "$22N125", 2, 5314.96, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R222", "2", "K2_VUP", 2, 5177.17, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R222", "1", "$22N130", 2, 5177.17, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R223", "2", "GND", 2, 5177.17, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R223", "1", "$22N130", 2, 5177.17, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R224", "2", "K2_VDN", 2, 5039.37, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R224", "1", "$22N135", 2, 5039.37, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R225", "2", "GND", 2, 5039.37, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R225", "1", "$22N135", 2, 5039.37, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R320", "2", "K3_PWR", 2, 8129.92, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R320", "1", "$23N125", 2, 8129.92, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R321", "2", "GND", 2, 8129.92, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R321", "1", "$23N125", 2, 8129.92, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R322", "2", "K3_VUP", 2, 7992.129999999999, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R322", "1", "$23N130", 2, 7992.129999999999, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R323", "2", "GND", 2, 7992.129999999999, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R323", "1", "$23N130", 2, 7992.129999999999, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R324", "2", "K3_VDN", 2, 7854.33, 4687.68, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R324", "1", "$23N135", 2, 7854.33, 4721.76, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R325", "2", "GND", 2, 7854.33, 4589.26, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R325", "1", "$23N135", 2, 7854.33, 4623.34, -1.570796326794897, ["RECT", 22.3, 21.3, 0]], ["R741", "2", "EDL_EN1", 2, 1459.34, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R741", "1", "GND", 2, 1493.42, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C846", "2", "VO5_P", 2, 5124.810000000001, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["C846", "1", "GND", 2, 5091.7300000000005, 885.8299999999999, 0, ["RECT", 19.7, 21.3, 0]], ["R742", "2", "EDL_EN2", 2, 4274.3, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R742", "1", "GND", 2, 4308.38, 4173.23, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C765", "2", "+3V3_HUB", 2, 6089.37, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C765", "1", "GND", 2, 6056.29, 1122.05, 0, ["RECT", 19.7, 21.3, 0]], ["C831", "2", "GND", 2, 3124.015, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["C831", "1", "VO4_P", 2, 2785.4249999999997, 740.1599999999999, 0, ["RECT", 169.3, 65, 0]], ["R781", "2", "$21N139", 2, 1656.19, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R781", "1", "GND", 2, 1690.2700000000002, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R425", "2", "GND", 2, 2214.57, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R425", "1", "$24N135", 2, 2214.57, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R782", "2", "$22N121", 2, 4471.15, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R782", "1", "GND", 2, 4505.23, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R520", "2", "K5_PWR", 2, 4753.94, 607.5899999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R520", "1", "$25N125", 2, 4753.94, 573.5099999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R783", "2", "$23N121", 2, 7286.11, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R783", "1", "GND", 2, 7320.189999999999, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["U22", "1", "K4_PWR", 2, 5194.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "2", "K4_VUP", 2, 5144.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "3", "K4_VDN", 2, 5094.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "4", "", 2, 5044.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "5", "K5_VDN", 2, 4994.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "6", "K5_VUP", 2, 4944.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "7", "K5_PWR", 2, 4894.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "8", "GND", 2, 4844.69, 2510.4100000000003, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "16", "+3V3_HUB", 2, 5194.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "15", "", 2, 5144.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "14", "SR_CAS", 2, 5094.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "13", "KEY_OE#", 2, 5044.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "12", "KEY_RCLK", 2, 4994.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "11", "KEY_SRCLK", 2, 4944.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "10", "+3V3_HUB", 2, 4894.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["U22", "9", "SR_CAS2", 2, 4844.69, 2725.8100000000004, 3.141592653589793, ["OVAL", 23.7, 77.6]], ["C832", "2", "VO4_P", 2, 2198.53, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["C832", "1", "GND", 2, 2073.13, 885.8299999999999, 0, ["RECT", 58.5, 68, 0]], ["R791", "2", "$21N140", 2, 1577.45, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R791", "1", "GND", 2, 1611.5300000000002, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R792", "2", "$22N122", 2, 4392.41, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R792", "1", "GND", 2, 4426.49, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R521", "2", "GND", 2, 4753.94, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R521", "1", "$25N125", 2, 4753.94, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R793", "2", "$23N122", 2, 7207.370000000001, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["R793", "1", "GND", 2, 7241.45, 4271.65, 3.141592653589793, ["RECT", 22.3, 21.3, 0]], ["C605", "2", "+3V3_HUB", 2, 5055.91, 2874.02, 0, ["RECT", 19.7, 21.3, 0]], ["C605", "1", "GND", 2, 5022.83, 2874.02, 0, ["RECT", 19.7, 21.3, 0]], ["C763", "2", "+3V3_HUB", 2, 6794.480000000001, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["C763", "1", "GND", 2, 6827.560000000001, 4173.23, 3.141592653589793, ["RECT", 19.7, 21.3, 0]], ["U31", "1", "GND", 2, 3561.807, 2472.44, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "2", "+3V3_HUB", 2, 3561.807, 2381.89, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "3", "+5V", 2, 3561.807, 2291.3399999999997, 0, ["RECT", 98.4, 43.3, 0]], ["U31", "4", "+3V3_HUB", 2, 3327.952, 2381.89, 0, ["RECT", 92.1, 141.7, 0]], ["U43", "3", "", 2, 6895.669999999999, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "2", "GND", 2, 6895.669999999999, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "1", "$23N139", 2, 6895.669999999999, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "6", "EDL_EN3", 2, 7001.97, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "5", "+3V3_HUB", 2, 7001.97, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U43", "4", "$23N140", 2, 7001.97, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U34", "1", "SDA", 2, 2176.96, 2287.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "2", "SCL", 2, 2176.96, 2337.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "3", "", 2, 2176.96, 2387.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "4", "GND", 2, 2176.96, 2437.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "8", "+3V3_HUB", 2, 2389.96, 2287.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "7", "GND", 2, 2389.96, 2337.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "6", "GND", 2, 2389.96, 2387.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["U34", "5", "GND", 2, 2389.96, 2437.2, 1.5707963267948966, ["OVAL", 22.4, 76.8]], ["R423", "2", "GND", 2, 2076.77, 706.0199999999999, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["R423", "1", "$24N130", 2, 2076.77, 671.94, 1.5707963267948966, ["RECT", 22.3, 21.3, 0]], ["U41", "3", "", 2, 1265.7500000000002, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "2", "GND", 2, 1265.7500000000002, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "1", "$21N157", 2, 1265.7500000000002, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "6", "EDL_EN1", 2, 1372.0500000000002, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "5", "+3V3_HUB", 2, 1372.0500000000002, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U41", "4", "$21N158", 2, 1372.0500000000002, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["C845", "2", "VO5_P", 2, 5387.5, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["C845", "1", "GND", 2, 5262.1, 1023.6199999999999, 0, ["RECT", 58.5, 68, 0]], ["U42", "3", "", 2, 4080.7099999999996, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "2", "GND", 2, 4080.7099999999996, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "1", "$22N139", 2, 4080.7099999999996, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "6", "EDL_EN2", 2, 4187.009999999999, 4135.83, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "5", "+3V3_HUB", 2, 4187.009999999999, 4173.23, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["U42", "4", "$22N140", 2, 4187.009999999999, 4210.63, 3.141592653589793, ["RECT", 43.3, 23.6, 0]], ["R745", "2", "EDL_EN5", 2, 5794.6, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["R745", "1", "GND", 2, 5760.520000000001, 1122.05, 0, ["RECT", 22.3, 21.3, 0]], ["J41", "1", "POGO1_PWR", 1, 2648.82, 4796.85, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J42", "1", "POGO1_VUP", 1, 2700, 4749.21, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J43", "1", "POGO1_VDN", 1, 2697.24, 4852.76, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J44", "1", "GND", 1, 2753.94, 4803.54, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J45", "1", "POGO2_PWR", 1, 5463.779999999999, 4796.85, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J46", "1", "POGO2_VUP", 1, 5514.96, 4749.21, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J47", "1", "POGO2_VDN", 1, 5512.200000000001, 4852.76, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J48", "1", "GND", 1, 5568.9, 4803.54, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J49", "1", "POGO3_PWR", 1, 8278.74, 4796.85, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J50", "1", "POGO3_VUP", 1, 8329.92, 4749.21, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J51", "1", "POGO3_VDN", 1, 8327.17, 4852.76, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J52", "1", "GND", 1, 8383.86, 4803.54, 3.141592653589793, ["ELLIPSE", 59.1, 59.1]], ["J53", "1", "POGO4_PWR", 1, 1790.1600000000003, 498.43000000000006, 0, ["ELLIPSE", 59.1, 59.1]], ["J54", "1", "POGO4_VUP", 1, 1738.98, 546.06, 0, ["ELLIPSE", 59.1, 59.1]], ["J55", "1", "POGO4_VDN", 1, 1741.73, 442.52, 0, ["ELLIPSE", 59.1, 59.1]], ["J56", "1", "GND", 1, 1685.04, 491.73, 0, ["ELLIPSE", 59.1, 59.1]], ["J57", "1", "POGO5_PWR", 1, 4605.12, 498.43000000000006, 0, ["ELLIPSE", 59.1, 59.1]], ["J58", "1", "POGO5_VUP", 1, 4553.94, 546.06, 0, ["ELLIPSE", 59.1, 59.1]], ["J59", "1", "POGO5_VDN", 1, 4556.69, 442.52, 0, ["ELLIPSE", 59.1, 59.1]], ["J60", "1", "GND", 1, 4500, 491.73, 0, ["ELLIPSE", 59.1, 59.1]], ["C737", "1", "+3V3_HUB", 2, 3715.24, 2125.98, 3.141592653589793, ["RECT", 59.1, 53.5, 0]], ["C737", "2", "GND", 2, 3620.76, 2125.98, 3.141592653589793, ["RECT", 59.1, 53.5, 0]]], "vias": [["USB1_DPJ", 866.1417, 3543.3071, 24], ["USB1_DPJ", 976.3779999999999, 3527.5590999999995, 24], ["USB2_DPJ", 3681.1024, 3543.3071, 24], ["USB2_DPJ", 3791.3386, 3527.5590999999995, 24], ["USB3_DPJ", 6496.063, 3543.3071, 24], ["USB3_DPJ", 6606.2993, 3527.5590999999995, 24], ["USB4_DPJ", 3572.8346999999994, 1751.9685, 24], ["USB4_DPJ", 3462.5984, 1767.7165, 24], ["USB5_DPJ", 6387.7953, 1751.9685, 24], ["USB5_DPJ", 6277.5591, 1767.7165, 24], ["USB4_DM", 3629.9213, 2675.1969, 24], ["USB4_DM", 3562.9921000000004, 1980.315, 24], ["USB4_DP", 3629.9213, 2710.6299, 24], ["USB4_DP", 3527.5590999999995, 1980.315, 24], ["USB5_DM", 4381.8898, 2425.1969, 24], ["USB5_DM", 4381.8898, 2330.7087, 24], ["USB5_DP", 4342.5197, 2425.1969, 24], ["USB5_DP", 4342.5197, 2330.7087, 24], ["UP_DP", 8419.2914, 2450.7874, 24], ["UP_DP", 8419.2914, 2389.7638, 24], ["UP_DM", 8454.7245, 2413.3858, 24], ["UP_DM", 8454.7245, 2488.189, 24], ["VO1_P", 1653.5433, 4606.2992, 24], ["VO1_P", 1653.5433, 4503.937, 24], ["VO1_P", 1705.0473, 4606.6221, 24], ["VO1_P", 2287.6929, 4409.4488, 24], ["VO1_P", 2307.374, 4271.6496, 24], ["VO1_P", 2110.5236, 4271.6496, 24], ["VO1_P", 1913.6732000000002, 4271.6496, 24], ["VO1_P", 2099.6024, 4409.4488, 24], ["VO1_P", 2095.4882, 4449.815, 24], ["VO1_P", 2095.4882, 4369.0827, 24], ["VO1_P", 2121.9331, 4476.2638, 24], ["VO2_P", 4468.504, 4606.2992, 24], ["VO2_P", 4468.504, 4503.937, 24], ["VO2_P", 4520.0079, 4606.6221, 24], ["VO2_P", 5102.6536, 4409.4488, 24], ["VO2_P", 5122.3426, 4271.6496, 24], ["VO2_P", 4925.4843, 4271.6496, 24], ["VO2_P", 4728.6339, 4271.6496, 24], ["VO2_P", 4914.563, 4409.4488, 24], ["VO2_P", 4910.4449, 4449.815, 24], ["VO2_P", 4910.4449, 4369.0827, 24], ["VO2_P", 4936.8937, 4476.2638, 24], ["VO3_P", 7283.464599999999, 4606.2992, 24], ["VO3_P", 7283.464599999999, 4503.937, 24], ["VO3_P", 7334.9686, 4606.6221, 24], ["VO3_P", 7917.6142, 4409.4488, 24], ["VO3_P", 7937.3032, 4271.6496, 24], ["VO3_P", 7740.452800000001, 4271.6496, 24], ["VO3_P", 7543.6024, 4271.6496, 24], ["VO3_P", 7729.5237, 4409.4488, 24], ["VO3_P", 7725.4056, 4449.815, 24], ["VO3_P", 7725.4056, 4369.0827, 24], ["VO3_P", 7751.8544, 4476.2638, 24], ["VO4_P", 2785.4252, 791.3425, 24], ["VO4_P", 2785.4252, 688.9803, 24], ["VO4_P", 2836.9252, 791.6614, 24], ["VO4_P", 2151.2874, 885.8307, 24], ["VO4_P", 2131.5945, 1023.6181, 24], ["VO4_P", 2328.4449, 1023.6181, 24], ["VO4_P", 2619.7834999999995, 1023.6181, 24], ["VO4_P", 2339.378, 885.8307, 24], ["VO4_P", 2343.4921, 926.1969, 24], ["VO4_P", 2343.4921, 845.4646, 24], ["VO4_P", 2317.0473, 952.6417000000001, 24], ["VO5_P", 5600.3937, 791.3425, 24], ["VO5_P", 5600.3937, 688.9803, 24], ["VO5_P", 5651.8977, 791.6614, 24], ["VO5_P", 4966.2441, 885.8307, 24], ["VO5_P", 4946.5552, 1023.6181, 24], ["VO5_P", 5143.4055, 1023.6181, 24], ["VO5_P", 5434.7441, 1023.6181, 24], ["VO5_P", 5154.3386, 885.8307, 24], ["VO5_P", 5158.4528, 926.1969, 24], ["VO5_P", 5158.4528, 845.4646, 24], ["VO5_P", 5132.0079, 952.6417000000001, 24], ["GND", 3860.2422, 2600.4030000000002, 24], ["GND", 3860.2422, 2625.9935, 24], ["GND", 3860.2422, 2651.5841, 24], ["GND", 3860.2422, 2677.1747, 24], ["GND", 3860.2422, 2702.7652, 24], ["GND", 3860.2422, 2728.3558, 24], ["GND", 3860.2422, 2753.9464, 24], ["GND", 3885.8328, 2600.4030000000002, 24], ["GND", 3885.8328, 2625.9935, 24], ["GND", 3885.8328, 2651.5841, 24], ["GND", 3885.8328, 2677.1747, 24], ["GND", 3885.8328, 2702.7652, 24], ["GND", 3885.8328, 2728.3558, 24], ["GND", 3885.8328, 2753.9464, 24], ["GND", 3911.4233999999997, 2600.4030000000002, 24], ["GND", 3911.4233999999997, 2625.9935, 24], ["GND", 3911.4233999999997, 2651.5841, 24], ["GND", 3911.4233999999997, 2677.1747, 24], ["GND", 3911.4233999999997, 2702.7652, 24], ["GND", 3911.4233999999997, 2728.3558, 24], ["GND", 3911.4233999999997, 2753.9464, 24], ["GND", 3937.0139, 2600.4030000000002, 24], ["GND", 3937.0139, 2625.9935, 24], ["GND", 3937.0139, 2651.5841, 24], ["GND", 3937.0139, 2677.1747, 24], ["GND", 3937.0139, 2702.7652, 24], ["GND", 3937.0139, 2728.3558, 24], ["GND", 3937.0139, 2753.9464, 24], ["GND", 3962.6045, 2600.4030000000002, 24], ["GND", 3962.6045, 2625.9935, 24], ["GND", 3962.6045, 2651.5841, 24], ["GND", 3962.6045, 2677.1747, 24], ["GND", 3962.6045, 2702.7652, 24], ["GND", 3962.6045, 2728.3558, 24], ["GND", 3962.6045, 2753.9464, 24], ["GND", 3988.1951, 2600.4030000000002, 24], ["GND", 3988.1951, 2625.9935, 24], ["GND", 3988.1951, 2651.5841, 24], ["GND", 3988.1951, 2677.1747, 24], ["GND", 3988.1951, 2702.7652, 24], ["GND", 3988.1951, 2728.3558, 24], ["GND", 3988.1951, 2753.9464, 24], ["GND", 4013.7856, 2600.4030000000002, 24], ["GND", 4013.7856, 2625.9935, 24], ["GND", 4013.7856, 2651.5841, 24], ["GND", 4013.7856, 2677.1747, 24], ["GND", 4013.7856, 2702.7652, 24], ["GND", 4013.7856, 2728.3558, 24], ["GND", 4013.7856, 2753.9464, 24], ["GND", 2462.5998, 834.6501, 24], ["GND", 2462.5998, 860.2405999999999, 24], ["GND", 2462.5998, 885.8312, 24], ["GND", 2462.5998, 911.4218, 24], ["GND", 2462.5998, 937.0123, 24], ["GND", 1250.9771, 4542.3253, 24], ["GND", 1250.9771, 4567.9159, 24], ["GND", 1276.5676, 4542.3253, 24], ["GND", 1276.5676, 4567.9159, 24], ["GND", 1302.1582, 4542.3253, 24], ["GND", 1302.1582, 4567.9159, 24], ["GND", 1327.7487, 4542.3253, 24], ["GND", 1327.7487, 4567.9159, 24], ["GND", 1353.3393, 4542.3253, 24], ["GND", 1353.3393, 4567.9159, 24], ["GND", 1378.9299, 4542.3253, 24], ["GND", 1378.9299, 4567.9159, 24], ["GND", 4162.4078, 1928.1387999999997, 24], ["GND", 4162.4078, 1953.7294, 24], ["GND", 4162.4078, 1979.32, 24], ["GND", 4162.4078, 2004.9105, 24], ["GND", 4187.9983, 1928.1387999999997, 24], ["GND", 4187.9983, 1953.7294, 24], ["GND", 4187.9983, 1979.32, 24], ["GND", 4187.9983, 2004.9105, 24], ["GND", 4213.5889, 1928.1387999999997, 24], ["GND", 4213.5889, 1953.7294, 24], ["GND", 4213.5889, 1979.32, 24], ["GND", 4213.5889, 2004.9105, 24], ["GND", 3916.3288999999995, 1928.1387999999997, 24], ["GND", 3916.3288999999995, 1953.7294, 24], ["GND", 3916.3288999999995, 1979.32, 24], ["GND", 3916.3288999999995, 2004.9105, 24], ["GND", 3941.9195, 1928.1387999999997, 24], ["GND", 3941.9195, 1953.7294, 24], ["GND", 3941.9195, 1979.32, 24], ["GND", 3941.9195, 2004.9105, 24], ["GND", 3967.51, 1928.1387999999997, 24], ["GND", 3967.51, 1953.7294, 24], ["GND", 3967.51, 1979.32, 24], ["GND", 3967.51, 2004.9105, 24], ["GND", 4065.9392, 4542.3253, 24], ["GND", 4065.9392, 4567.9159, 24], ["GND", 4091.5297999999993, 4542.3253, 24], ["GND", 4091.5297999999993, 4567.9159, 24], ["GND", 4117.1203, 4542.3253, 24], ["GND", 4117.1203, 4567.9159, 24], ["GND", 4142.7109, 4542.3253, 24], ["GND", 4142.7109, 4567.9159, 24], ["GND", 4168.3015, 4542.3253, 24], ["GND", 4168.3015, 4567.9159, 24], ["GND", 4193.892, 4542.3253, 24], ["GND", 4193.892, 4567.9159, 24], ["GND", 5277.558, 834.6501, 24], ["GND", 5277.558, 860.2405999999999, 24], ["GND", 5277.558, 885.8312, 24], ["GND", 5277.558, 911.4218, 24], ["GND", 5277.558, 937.0123, 24], ["GND", 6880.8974, 4542.3253, 24], ["GND", 6880.8974, 4567.9159, 24], ["GND", 6906.488, 4542.3253, 24], ["GND", 6906.488, 4567.9159, 24], ["GND", 6932.0785, 4542.3253, 24], ["GND", 6932.0785, 4567.9159, 24], ["GND", 6957.669100000001, 4542.3253, 24], ["GND", 6957.669100000001, 4567.9159, 24], ["GND", 6983.2597, 4542.3253, 24], ["GND", 6983.2597, 4567.9159, 24], ["GND", 7008.850199999999, 4542.3253, 24], ["GND", 7008.850199999999, 4567.9159, 24], ["GND", 5855.3102, 3290.3679, 24], ["GND", 5855.3102, 3315.9585000000006, 24], ["GND", 5855.3102, 3341.549, 24], ["GND", 5855.3102, 3367.1396, 24], ["GND", 5880.9008, 3290.3679, 24], ["GND", 5880.9008, 3315.9585000000006, 24], ["GND", 5880.9008, 3341.549, 24], ["GND", 5880.9008, 3367.1396, 24], ["GND", 5906.4914, 3290.3679, 24], ["GND", 5906.4914, 3315.9585000000006, 24], ["GND", 5906.4914, 3341.549, 24], ["GND", 5906.4914, 3367.1396, 24], ["GND", 6101.3891, 3290.3679, 24], ["GND", 6101.3891, 3315.9585000000006, 24], ["GND", 6101.3891, 3341.549, 24], ["GND", 6101.3891, 3367.1396, 24], ["GND", 6126.9797, 3290.3679, 24], ["GND", 6126.9797, 3315.9585000000006, 24], ["GND", 6126.9797, 3341.549, 24], ["GND", 6126.9797, 3367.1396, 24], ["GND", 6152.570299999999, 3290.3679, 24], ["GND", 6152.570299999999, 3315.9585000000006, 24], ["GND", 6152.570299999999, 3341.549, 24], ["GND", 6152.570299999999, 3367.1396, 24], ["GND", 5875.007100000001, 727.3665, 24], ["GND", 5875.007100000001, 752.9571, 24], ["GND", 5900.5977, 727.3665, 24], ["GND", 5900.5977, 752.9571, 24], ["GND", 5926.188199999999, 727.3665, 24], ["GND", 5926.188199999999, 752.9571, 24], ["GND", 5951.7788, 727.3665, 24], ["GND", 5951.7788, 752.9571, 24], ["GND", 5977.3694, 727.3665, 24], ["GND", 5977.3694, 752.9571, 24], ["GND", 6002.9599, 727.3665, 24], ["GND", 6002.9599, 752.9571, 24], ["GND", 6977.3699, 1928.1387999999997, 24], ["GND", 6977.3699, 1953.7294, 24], ["GND", 6977.3699, 1979.32, 24], ["GND", 6977.3699, 2004.9105, 24], ["GND", 7002.9605, 1928.1387999999997, 24], ["GND", 7002.9605, 1953.7294, 24], ["GND", 7002.9605, 1979.32, 24], ["GND", 7002.9605, 2004.9105, 24], ["GND", 7028.5509999999995, 1928.1387999999997, 24], ["GND", 7028.5509999999995, 1953.7294, 24], ["GND", 7028.5509999999995, 1979.32, 24], ["GND", 7028.5509999999995, 2004.9105, 24], ["GND", 6731.291, 1928.1387999999997, 24], ["GND", 6731.291, 1953.7294, 24], ["GND", 6731.291, 1979.32, 24], ["GND", 6731.291, 2004.9105, 24], ["GND", 6756.881599999999, 1928.1387999999997, 24], ["GND", 6756.881599999999, 1953.7294, 24], ["GND", 6756.881599999999, 1979.32, 24], ["GND", 6756.881599999999, 2004.9105, 24], ["GND", 6782.4722, 1928.1387999999997, 24], ["GND", 6782.4722, 1953.7294, 24], ["GND", 6782.4722, 1979.32, 24], ["GND", 6782.4722, 2004.9105, 24], ["GND", 225.3899, 3290.3679, 24], ["GND", 225.3899, 3315.9585000000006, 24], ["GND", 225.3899, 3341.549, 24], ["GND", 225.3899, 3367.1396, 24], ["GND", 250.9805, 3290.3679, 24], ["GND", 250.9805, 3315.9585000000006, 24], ["GND", 250.9805, 3341.549, 24], ["GND", 250.9805, 3367.1396, 24], ["GND", 276.571, 3290.3679, 24], ["GND", 276.571, 3315.9585000000006, 24], ["GND", 276.571, 3341.549, 24], ["GND", 276.571, 3367.1396, 24], ["GND", 471.4688, 3290.3679, 24], ["GND", 471.4688, 3315.9585000000006, 24], ["GND", 471.4688, 3341.549, 24], ["GND", 471.4688, 3367.1396, 24], ["GND", 497.0593, 3290.3679, 24], ["GND", 497.0593, 3315.9585000000006, 24], ["GND", 497.0593, 3341.549, 24], ["GND", 497.0593, 3367.1396, 24], ["GND", 522.6499, 3290.3679, 24], ["GND", 522.6499, 3315.9585000000006, 24], ["GND", 522.6499, 3341.549, 24], ["GND", 522.6499, 3367.1396, 24], ["GND", 3040.3481, 3290.3679, 24], ["GND", 3040.3481, 3315.9585000000006, 24], ["GND", 3040.3481, 3341.549, 24], ["GND", 3040.3481, 3367.1396, 24], ["GND", 3065.9387000000006, 3290.3679, 24], ["GND", 3065.9387000000006, 3315.9585000000006, 24], ["GND", 3065.9387000000006, 3341.549, 24], ["GND", 3065.9387000000006, 3367.1396, 24], ["GND", 3091.5292, 3290.3679, 24], ["GND", 3091.5292, 3315.9585000000006, 24], ["GND", 3091.5292, 3341.549, 24], ["GND", 3091.5292, 3367.1396, 24], ["GND", 3286.4309, 3290.3679, 24], ["GND", 3286.4309, 3315.9585000000006, 24], ["GND", 3286.4309, 3341.549, 24], ["GND", 3286.4309, 3367.1396, 24], ["GND", 3312.0215, 3290.3679, 24], ["GND", 3312.0215, 3315.9585000000006, 24], ["GND", 3312.0215, 3341.549, 24], ["GND", 3312.0215, 3367.1396, 24], ["GND", 3337.612, 3290.3679, 24], ["GND", 3337.612, 3315.9585000000006, 24], ["GND", 3337.612, 3341.549, 24], ["GND", 3337.612, 3367.1396, 24], ["GND", 1976.379, 4358.2701, 24], ["GND", 1976.379, 4383.8606, 24], ["GND", 1976.379, 4409.4512, 24], ["GND", 1976.379, 4435.0418, 24], ["GND", 1976.379, 4460.6323, 24], ["GND", 4791.3412, 4358.2701, 24], ["GND", 4791.3412, 4383.8606, 24], ["GND", 4791.3412, 4409.4512, 24], ["GND", 4791.3412, 4435.0418, 24], ["GND", 4791.3412, 4460.6323, 24], ["GND", 7606.2994, 4358.2701, 24], ["GND", 7606.2994, 4383.8606, 24], ["GND", 7606.2994, 4409.4512, 24], ["GND", 7606.2994, 4435.0418, 24], ["GND", 7606.2994, 4460.6323, 24], ["GND", 3060.0371, 727.3665, 24], ["GND", 3060.0371, 752.9571, 24], ["GND", 3085.6277, 727.3665, 24], ["GND", 3085.6277, 752.9571, 24], ["GND", 3111.2181999999993, 727.3665, 24], ["GND", 3111.2181999999993, 752.9571, 24], ["GND", 3136.8088, 727.3665, 24], ["GND", 3136.8088, 752.9571, 24], ["GND", 3162.3993, 727.3665, 24], ["GND", 3162.3993, 752.9571, 24], ["GND", 3187.9899, 727.3665, 24], ["GND", 3187.9899, 752.9571, 24], ["GND", 1751.0002, 3976.3801000000003, 24], ["GND", 4565.9584, 3976.3801000000003, 24], ["GND", 7380.9205, 3976.3801000000003, 24], ["GND", 2768.2905, 1372.5663, 24], ["GND", 5583.2488, 1372.5663, 24], ["GND", 1302.359, 4010.5719, 24], ["GND", 4117.3211, 4010.5719, 24], ["GND", 6932.2793, 4010.5719, 24], ["GND", 3170.8116, 1318.8984, 24], ["GND", 5985.7737, 1318.8984, 24], ["GND", 1203.9298, 4010.5719, 24], ["GND", 4018.8918999999996, 4010.5719, 24], ["GND", 6833.8501, 4010.5719, 24], ["GND", 3266.6302, 1331.983, 24], ["GND", 6081.5884, 1331.983, 24], ["GND", 3849.1505, 2176.3713, 24], ["GND", 4000.7333, 2941.7417, 24], ["GND", 3862.4242, 2382.8469, 24], ["GND", 3727.6174, 2412.5919, 24], ["GND", 3971.2018, 2307.08, 24], ["GND", 4114.9026, 2412.5919, 24], ["GND", 3485.5235, 2863.0906, 24], ["GND", 3641.7303, 2853.8823, 24], ["GND", 3873.2866999999997, 2941.7417, 24], ["GND", 4235.7728, 2498.0289, 24], ["GND", 3872.5677, 2902.9684, 24], ["GND", 1105.0085, 4011.4836000000005, 24], ["GND", 3919.9706000000006, 4011.4836000000005, 24], ["GND", 6734.9288, 4011.4836000000005, 24], ["GND", 3369.0738, 1318.8984, 24], ["GND", 6184.031999999999, 1318.8984, 24], ["GND", 3863.5836, 2349.6875, 24], ["GND", 4304.4393, 2698.4947, 24], ["GND", 8211.3115, 2574.4749, 24], ["GND", 8211.3115, 2377.6244, 24], ["GND", 4237.1845, 2687.0093, 24], ["GND", 4304.4393, 2533.7955, 24], ["GND", 3053.8284, 2456.3646, 24], ["GND", 660.1303, 3539.0423999999994, 24], ["GND", 3475.0885, 3539.0423999999994, 24], ["GND", 6290.0506, 3539.0423999999994, 24], ["GND", 3813.952, 1791.3396, 24], ["GND", 6628.9141, 1791.3396, 24], ["GND", 1467.5704, 3976.3801000000003, 24], ["GND", 4282.5325, 3976.3801000000003, 24], ["GND", 7097.4907, 3976.3801000000003, 24], ["GND", 3060.0909, 1318.8984, 24], ["GND", 5875.053, 1318.8984, 24], ["GND", 913.3903, 3446.8883, 24], ["GND", 3728.3485, 3446.8883, 24], ["GND", 6543.3106, 3446.8883, 24], ["GND", 3525.5885, 1848.3823000000002, 24], ["GND", 6340.5507, 1848.3823000000002, 24], ["GND", 3879.3905, 2321.7379, 24], ["GND", 3676.6394, 2302.9087, 24], ["GND", 3152.149, 2356.8188, 24], ["GND", 2748.7100999999993, 1058.7221, 24], ["GND", 3663.254, 2125.9815, 24], ["GND", 7158.442, 4173.2306, 24], ["GND", 2494.823, 2345.6587, 24], ["GND", 2297.1167, 415.35849999999994, 24], ["GND", 1221.8157, 4197.4078, 24], ["GND", 4036.7778, 4197.4078, 24], ["GND", 4804.2146, 2768.4143, 24], ["GND", 2099.0716, 1069.2522, 24], ["GND", 2295.9221, 1069.2522, 24], ["GND", 2430.3872, 4409.4512, 24], ["GND", 2511.6746, 1023.6187, 24], ["GND", 2450.0644, 4271.6519, 24], ["GND", 2276.7689, 920.0229, 24], ["GND", 2213.375, 4331.275, 24], ["GND", 1946.1983, 4226.0184, 24], ["GND", 2021.5299, 415.35849999999994, 24], ["GND", 2186.3871, 4433.6284, 24], ["GND", 3128.8888, 1122.0518, 24], ["GND", 5245.3454, 4409.4512, 24], ["GND", 2945.5606, 1157.1553, 24], ["GND", 5265.0344, 4271.6519, 24], ["GND", 3241.3285, 1156.2435, 24], ["GND", 5028.3372, 4331.275, 24], ["GND", 4761.1565, 4226.0184, 24], ["GND", 5563.668399999999, 1058.7221, 24], ["GND", 5001.3453, 4433.6284, 24], ["GND", 4974.2796, 415.35849999999994, 24], ["GND", 8060.303599999999, 4409.4512, 24], ["GND", 8079.996499999999, 4271.6519, 24], ["GND", 4926.8345, 706.0201, 24], ["GND", 7843.3072, 4331.275, 24], ["GND", 7576.1265, 4226.0184, 24], ["GND", 5112.0789, 415.35849999999994, 24], ["GND", 7816.3074, 4433.6284, 24], ["GND", 7570.6632, 2871.8519000000006, 24], ["GND", 7888.5228, 2680.3085, 24], ["GND", 1974.0848, 706.0201, 24], ["GND", 2159.3174, 415.35849999999994, 24], ["GND", 5642.4086, 1058.7221, 24], ["GND", 4933.7228, 931.4647, 24], ["GND", 4914.0338, 1069.2522, 24], ["GND", 5064.6338, 706.0201, 24], ["GND", 5110.8843, 1069.2522, 24], ["GND", 5943.847, 1122.0518, 24], ["GND", 2827.4503, 1058.7221, 24], ["GND", 4836.4882, 415.35849999999994, 24], ["GND", 4589.7584, 2908.213, 24], ["GND", 2503.8097, 4879.92, 24], ["GND", 2366.0104, 4879.92, 24], ["GND", 2228.219, 4879.92, 24], ["GND", 5318.767900000001, 4879.92, 24], ["GND", 5180.976499999999, 4879.92, 24], ["GND", 5043.1772, 4879.92, 24], ["GND", 8133.730100000001, 4879.92, 24], ["GND", 7995.938699999999, 4879.92, 24], ["GND", 7858.1394, 4879.92, 24], ["GND", 2535.1048, 4589.2584, 24], ["GND", 2397.3016, 4589.2584, 24], ["GND", 2259.5141, 4589.2584, 24], ["GND", 5350.063, 4589.2584, 24], ["GND", 5212.2716, 4589.2584, 24], ["GND", 5074.4723, 4589.2584, 24], ["GND", 8165.0252, 4589.2584, 24], ["GND", 8027.2338, 4589.2584, 24], ["GND", 7889.434499999999, 4589.2584, 24], ["GND", 1528.5216, 4173.2306, 24], ["GND", 5091.7311, 920.0229, 24], ["GND", 4343.4838, 4173.2306, 24], ["GND", 6056.2907, 1156.2435, 24], ["GND", 1725.3721, 4271.6519, 24], ["GND", 2249.6716, 706.0201, 24], ["GND", 4540.3343, 4271.6519, 24], ["GND", 7355.2925, 4271.6519, 24], ["GND", 4844.6916, 2570.6645, 24], ["GND", 2118.7645, 931.4647, 24], ["GND", 1624.962, 4304.0833, 24], ["GND", 4439.9241, 4304.0833, 24], ["GND", 4789.0431, 706.0201, 24], ["GND", 7254.8823, 4304.0833, 24], ["GND", 5022.8295, 2908.213, 24], ["GND", 6851.736, 4197.4078, 24], ["GND", 3493.9568, 2500.542, 24], ["GND", 6940.0103, 4173.2306, 24], ["GND", 2236.6467, 2437.1982, 24], ["GND", 2330.277, 2337.1981, 24], ["GND", 2330.277, 2387.1981, 24], ["GND", 2449.6468, 2437.1982, 24], ["GND", 2111.8723, 706.0201, 24], ["GND", 1310.09, 4173.2306, 24], ["GND", 5326.6368, 1023.6187, 24], ["GND", 4125.0521, 4173.2306, 24], ["GND", 5760.518899999999, 1157.1553, 24], ["GND", 2815.4125, 4803.542, 24], ["GND", 5630.3746, 4803.542, 24], ["GND", 8445.3328, 4803.542, 24], ["GND", 1685.0403000000001, 553.2026, 24], ["GND", 4499.9985, 553.2026, 24], ["GND", 3646.8704, 2385.26, 24], ["GND", 8315.645, 2579.3091, 24], ["GND", 8314.7442, 2306.6376, 24], ["GND", 4132.7809, 2503.3105, 24], ["GND", 3828.7462, 2814.9201, 24], ["GND", 933.0709, 3622.0473, 24], ["GND", 891.7323, 3622.0473, 24], ["GND", 836.6142, 3622.0473, 24], ["GND", 781.4961, 3622.0473, 24], ["GND", 933.0709, 3696.8503999999994, 24], ["GND", 781.4961, 3696.8503999999994, 24], ["GND", 740.1575, 3696.8503999999994, 24], ["GND", 685.0394, 3696.8503999999994, 24], ["GND", 616.1417, 3696.8503999999994, 24], ["GND", 488.18899999999996, 3622.0473, 24], ["GND", 3748.0315, 3622.0473, 24], ["GND", 3706.6929, 3622.0473, 24], ["GND", 3651.5747999999994, 3622.0473, 24], ["GND", 3596.4566999999997, 3622.0473, 24], ["GND", 3748.0315, 3696.8503999999994, 24], ["GND", 3596.4566999999997, 3696.8503999999994, 24], ["GND", 3555.1181, 3696.8503999999994, 24], ["GND", 3500, 3696.8503999999994, 24], ["GND", 3431.1024, 3696.8503999999994, 24], ["GND", 3303.1496000000006, 3622.0473, 24], ["GND", 6562.9922, 3622.0473, 24], ["GND", 6521.6536, 3622.0473, 24], ["GND", 6466.5355, 3622.0473, 24], ["GND", 6411.4174, 3622.0473, 24], ["GND", 6562.9922, 3696.8503999999994, 24], ["GND", 6411.4174, 3696.8503999999994, 24], ["GND", 6370.0788, 3696.8503999999994, 24], ["GND", 6314.9607, 3696.8503999999994, 24], ["GND", 6246.063, 3696.8503999999994, 24], ["GND", 6118.1103, 3622.0473, 24], ["GND", 3505.9055, 1673.2284, 24], ["GND", 3547.2441, 1673.2284, 24], ["GND", 3602.3622, 1673.2284, 24], ["GND", 3657.4803, 1673.2284, 24], ["GND", 3505.9055, 1598.4251999999997, 24], ["GND", 3657.4803, 1598.4251999999997, 24], ["GND", 3698.8189, 1598.4251999999997, 24], ["GND", 3753.937, 1598.4251999999997, 24], ["GND", 3822.8346999999994, 1598.4251999999997, 24], ["GND", 3950.7874, 1673.2284, 24], ["GND", 6320.8662, 1673.2284, 24], ["GND", 6362.2048, 1673.2284, 24], ["GND", 6417.3229, 1673.2284, 24], ["GND", 6472.441, 1673.2284, 24], ["GND", 6320.8662, 1598.4251999999997, 24], ["GND", 6472.441, 1598.4251999999997, 24], ["GND", 6513.7796, 1598.4251999999997, 24], ["GND", 6568.8976999999995, 1598.4251999999997, 24], ["GND", 6637.7953, 1598.4251999999997, 24], ["GND", 6765.7481, 1673.2284, 24], ["THERM_1", 828.3465, 3531.4961, 24], ["THERM_1", 694.2125999999998, 3519.6851000000006, 24], ["THERM_2", 3643.3071, 3531.4961, 24], ["THERM_2", 3509.1733, 3519.6851000000006, 24], ["THERM_3", 6458.2678, 3531.4961, 24], ["THERM_3", 6324.133899999999, 3519.6851000000006, 24], ["THERM_4", 3610.6299, 1763.7795, 24], ["THERM_4", 3744.7638, 1775.5906, 24], ["THERM_5", 6425.5906, 1763.7795, 24], ["THERM_5", 6559.7245, 1775.5906, 24], ["HUB_RST", 4267.7166, 2618.1102999999994, 24], ["HUB_RST", 7437.0079, 2763.7795, 24], ["VBUS_UP", 8295.2756, 2381.8898, 24], ["VBUS_UP", 8303.1497, 2460.6299, 24], ["VBUS_UP", 4220.4725, 2578.7402, 24], ["VBUS_UP", 3649.6063, 2281.4961, 24], ["VBUS_UP", 3494.0945, 2421.2599, 24], ["VBUS_UP", 3189.6103, 2421.2599, 24], ["XTAL1", 3703.7402, 2502.9528, 24], ["XTAL1", 3848.4252000000006, 2534.4488, 24], ["XTAL2", 3460.6299, 2502.9528, 24], ["XTAL2", 3799.2126, 2799.2126, 24], ["CFGSEL0", 4263.7796, 2704.7244, 24], ["CFGSEL0", 4072.8346999999994, 2702.7559, 24], ["NONREM0", 4271.6536, 2503.937, 24], ["NONREM0", 4386.9803, 2577.5866, 24], ["NONREM0", 4389.7638, 2795.2756, 24], ["NONREM0", 4070.8662, 2637.7953, 24], ["+3V3_HUB", 3559.0551, 2755.9055, 24], ["+3V3_HUB", 3483.8544, 2775.5906, 24], ["+3V3_HUB", 3555.1181, 2427.1654, 24], ["+3V3_HUB", 3641.7284, 2771.2559, 24], ["+3V3_HUB", 4171.2599, 2512.7953, 24], ["+3V3_HUB", 4309.7048, 2616.1417, 24], ["+3V3_HUB", 3460.6299, 2925.1969, 24], ["+3V3_HUB", 3740.1614, 2925.2008, 24], ["+3V3_HUB", 3907.4803, 2889.3662, 24], ["+3V3_HUB", 3771.6536, 2500, 24], ["+3V3_HUB", 3927.1654, 2534.4488, 24], ["+3V3_HUB", 3746.4055, 2442.4173, 24], ["+3V3_HUB", 4008.7676999999994, 2414.7087, 24], ["+3V3_HUB", 4125.9843, 2442.9134, 24], ["+3V3_HUB", 3973.8306999999995, 2339.374, 24], ["+3V3_HUB", 4421.2599, 2586.6142, 24], ["+3V3_HUB", 4425.1969, 2496.063, 24], ["+3V3_HUB", 4694.4607, 2496.063, 24], ["+3V3_HUB", 3724.4095000000007, 2212.5984, 24], ["+3V3_HUB", 4881.8898, 2874.0158, 24], ["+3V3_HUB", 5077.5709, 2874.0197, 24], ["+3V3_HUB", 5181.1024, 2866.1418, 24], ["+3V3_HUB", 4644.5, 2874.0197, 24], ["+3V3_HUB", 3327.3622, 2385.8268, 24], ["+3V3_HUB", 2461.6142, 2396.0669, 24], ["+3V3_HUB", 2440.9449, 2299.2126, 24], ["+3V3_HUB", 3675.1969, 1877.9528, 24], ["+3V3_HUB", 3399.6063, 1858.2677, 24], ["+3V3_HUB", 3255.8424999999997, 1090.5512, 24], ["+3V3_HUB", 3033.4685, 1122.0512, 24], ["+3V3_HUB", 3980.315, 3059.0551, 24], ["+3V3_HUB", 3980.315, 3944.8819, 24], ["+3V3_HUB", 3956.6929, 4011.8111, 24], ["+3V3_HUB", 3960.6299, 4141.7323, 24], ["+3V3_HUB", 4220.4725, 4169.2914, 24], ["+3V3_HUB", 5204.7244, 2574.8032000000003, 24], ["+3V3_HUB", 5413.385900000001, 2555.1181, 24], ["+3V3_HUB", 5425.1969, 2437.0079, 24], ["+3V3_HUB", 5511.8111, 2318.8977, 24], ["+3V3_HUB", 5511.8111, 2114.1732, 24], ["+3V3_HUB", 5511.8111, 2035.4331, 24], ["+3V3_HUB", 5531.4961, 1122.0473, 24], ["+3V3_HUB", 5848.4292, 1122.0512, 24], ["+3V3_HUB", 6110.633900000001, 1106.2992, 24], ["+3V3_HUB", 1405.5117999999998, 2578.7402, 24], ["+3V3_HUB", 1405.5117999999998, 3901.5747999999994, 24], ["+3V3_HUB", 1405.5117999999998, 4169.2914, 24], ["+3V3_HUB", 1142.315, 4157.4803, 24], ["+3V3_HUB", 6688.9764, 2893.7008000000005, 24], ["+3V3_HUB", 6811.027599999999, 4141.7323, 24], ["+3V3_HUB", 7035.4331, 4169.2914, 24], ["+3V3_HUB", 7776.004000000001, 2831.2008000000005, 24], ["K1_PWR", 4397.6378, 2850.3937, 24], ["K1_PWR", 2562.9921000000004, 2909.4488, 24], ["K1_VUP", 4460.63, 2937.0078999999996, 24], ["K1_VUP", 4460.63, 3023.6221, 24], ["K1_VUP", 4460.63, 3822.8346999999994, 24], ["K1_VUP", 2480.2087, 3862.2047, 24], ["K1_VDN", 4511.7874, 2917.3229, 24], ["K1_VDN", 4594.4882, 3035.4331, 24], ["K1_VDN", 4574.8032, 4673.2284, 24], ["K1_VDN", 2224.4095, 4670.8662, 24], ["K2_PWR", 7389.7638, 4673.2284, 24], ["K2_PWR", 5314.9607, 4670.8662, 24], ["K2_VUP", 7381.8898, 3842.5197, 24], ["K2_VUP", 5295.2756, 3862.2047, 24], ["K2_VDN", 7457.4843, 2559.8465, 24], ["K2_VDN", 6629.9213, 2555.1181, 24], ["K2_VDN", 6590.5512, 4559.0551, 24], ["K2_VDN", 5122.0473, 4559.0551, 24], ["K3_PWR", 7470.5, 2787.4016, 24], ["K3_PWR", 8106.2796, 2807.0866, 24], ["K3_VUP", 7610.236299999999, 4212.5985, 24], ["K3_VUP", 7964.566999999999, 4468.504, 24], ["K3_VDN", 7627.952800000001, 4181.1024, 24], ["K3_VDN", 7826.7717, 4474.4095, 24], ["K4_PWR", 1945.3071, 622.0472, 24], ["K4_PWR", 4311.0237, 631.8898, 24], ["K4_PWR", 4316.9292, 2303.1496, 24], ["K4_PWR", 5192.9133999999995, 2417.3229, 24], ["K4_VUP", 2115.4567, 649.6063000000001, 24], ["K4_VUP", 4283.4646, 669.2913, 24], ["K4_VUP", 4285.8268, 2275.5906, 24], ["K4_VUP", 5061.0237, 2275.5906, 24], ["K4_VUP", 5070.8662, 2338.5827, 24], ["K4_VUP", 5145.6693, 2417.3229, 24], ["K4_VDN", 2299.2126, 807.0866, 24], ["K4_VDN", 4255.9055, 838.5827, 24], ["K4_VDN", 4255.9055, 2228.3465, 24], ["K4_VDN", 5023.6221, 2248.0315, 24], ["K4_VDN", 5035.4331, 2338.5827, 24], ["K4_VDN", 5094.4882, 2417.3229, 24], ["K5_PWR", 4818.8977, 2035.4331, 24], ["K5_PWR", 4893.7008, 2114.1732, 24], ["K5_PWR", 4893.7008, 2338.5827, 24], ["K5_PWR", 4893.7008, 2417.3229, 24], ["K5_VUP", 4846.4567, 826.7717, 24], ["K5_VUP", 4791.3386, 846.4567, 24], ["K5_VUP", 4791.3386, 1988.189, 24], ["K5_VUP", 4944.8819, 2114.1732, 24], ["K5_VUP", 4944.8819, 2338.5827, 24], ["K5_VUP", 4944.8819, 2417.3229, 24], ["K5_VDN", 5003.937, 826.7717, 24], ["K5_VDN", 4996.063, 1082.6772, 24], ["K5_VDN", 4996.063, 2035.4331, 24], ["K5_VDN", 4996.063, 2114.1732, 24], ["K5_VDN", 4996.063, 2338.5827, 24], ["K5_VDN", 4996.063, 2417.3229, 24], ["KEY_SER", 4527.5591, 2529.5276, 24], ["KEY_SER", 5517.7166, 2549.2126, 24], ["KEY_SRCLK", 4681.1024, 2629.9213, 24], ["KEY_SRCLK", 4925.1969, 2629.9213, 24], ["KEY_SRCLK", 4962.5985, 2755.9055, 24], ["KEY_SRCLK", 7362.2048, 2781.4961, 24], ["KEY_SRCLK", 7364.566999999999, 2728.3465, 24], ["KEY_SRCLK", 7767.7166, 2759.8425, 24], ["KEY_OE#", 4580.7087, 2576.7717, 24], ["KEY_OE#", 4811.0237, 2576.7717, 24], ["KEY_OE#", 5003.937, 2840.5512, 24], ["KEY_OE#", 4800.2008, 2840.5512, 24], ["KEY_OE#", 5750, 2830.7087, 24], ["KEY_OE#", 5818.8976999999995, 2547.2441, 24], ["KEY_OE#", 7661.4174, 2547.2441, 24], ["SR_CAS", 4779.5276, 2500, 24], ["SR_CAS", 5299.2126, 2500, 24], ["SR_CAS2", 7760.299299999999, 2633.8583, 24], ["SR_CAS2", 7228.3465, 2653.5433000000003, 24], ["SR_CAS2", 7208.6615, 2937.0078999999996, 24], ["SR_CAS2", 4921.2599, 2917.3229, 24], ["SR_CAS2", 4917.3229, 2791.3386, 24], ["SR_CAS2", 4843.6024, 2783.8819000000003, 24], ["EDL_EN1", 7759.1457, 2586.6142, 24], ["EDL_EN1", 7636.641799999999, 2589.3977, 24], ["EDL_EN1", 7647.6378, 4114.1733, 24], ["EDL_EN1", 1436.7992, 4133.8583, 24], ["EDL_EN2", 4706.8977, 2942.437, 24], ["EDL_EN2", 4629.9213, 3035.4331, 24], ["EDL_EN2", 4629.9213, 4066.9292, 24], ["EDL_EN2", 4240.1575, 4086.6142, 24], ["EDL_EN3", 6964.566999999999, 4039.3701, 24], ["EDL_EN3", 6659.448899999999, 4037.4016, 24], ["EDL_EN3", 6657.5512, 2984.2520000000004, 24], ["EDL_EN3", 4685.0394, 2909.4488, 24], ["EDL_EN4", 4460.63, 2417.3229, 24], ["EDL_EN4", 4417.3229, 2338.5827, 24], ["EDL_EN4", 4397.6378, 2114.1732, 24], ["EDL_EN4", 3858.2677000000003, 2094.4882, 24], ["EDL_EN4", 3838.5827, 1185.0394, 24], ["EDL_EN4", 3034.4528, 1172.2441, 24], ["EDL_EN5", 4627.5512, 2811.0235999999995, 24], ["EDL_EN5", 4960.63, 2816.5906, 24], ["EDL_EN5", 5067.5237, 2909.4488, 24], ["EDL_EN5", 5700.7874, 2909.4488, 24], ["EDL_EN5", 5720.4725, 2417.3229, 24], ["EDL_EN5", 5791.3386, 2338.5827, 24], ["EDL_EN5", 5791.3386, 2114.1732, 24], ["EDL_EN5", 5791.3386, 2035.4331, 24], ["VBUS_EN1", 1181.1024, 4039.3701, 24], ["VBUS_EN1", 1358.9921, 4039.3701, 24], ["VBUS_EN1", 1440.9449, 4011.8111, 24], ["VBUS_EN1", 2389.7835, 3992.126, 24], ["VBUS_EN2", 3950.2244, 3934.2205000000004, 24], ["VBUS_EN2", 4204.7244, 4007.874, 24], ["VBUS_EN2", 6212.5985, 3984.2520000000004, 24], ["VBUS_EN2", 6232.2835, 3015.7481, 24], ["VBUS_EN2", 6559.055200000001, 2996.063, 24], ["VBUS_EN2", 6539.3701, 2830.7087, 24], ["VBUS_EN2", 5889.7638, 2830.7087, 24], ["VBUS_EN3", 6788.1497, 3980.315, 24], ["VBUS_EN3", 7019.685099999999, 4007.874, 24], ["VBUS_EN3", 7070.8623, 3891.7322999999997, 24], ["VBUS_EN4", 3279.5276000000003, 1283.311, 24], ["VBUS_EN4", 3049.2126, 1281.5, 24], ["VBUS_EN4", 2956.6929, 2500, 24], ["VBUS_EN5", 6094.4882, 1283.311, 24], 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["7df4f846be6f8108", "GND", 2, 4533.6501, 3976.3801000000003, 4565.9584, 3976.3801000000003, 11.811], ["4fb14c13c7ea0563", "GND", 2, 7348.6122, 3976.3801000000003, 7380.9205, 3976.3801000000003, 11.811], ["0b2d6408a3cab4a7", "GND", 2, 2768.2905, 1343.4791, 2768.2905, 1372.5663, 11.811], ["86cd385f177b11b3", "GND", 2, 5583.2488, 1343.4791, 5583.2488, 1372.5663, 11.811], ["e8b08620c83722ee", "GND", 2, 1302.359, 3985.0612, 1302.359, 4010.5719, 11.811], ["b52fa88a9d928830", "GND", 2, 4117.3211, 3985.0612, 4117.3211, 4010.5719, 11.811], ["d79962073ad8b551", "GND", 2, 6932.2793, 3985.0612, 6932.2793, 4010.5719, 11.811], ["dccfcf54082b5a8e", "GND", 2, 3144.5017, 1318.8984, 3170.8116, 1318.8984, 11.811], ["d54de69455799b4d", "GND", 2, 5959.463800000001, 1318.8984, 5985.7737, 1318.8984, 11.811], ["ecb6ff72cba310fb", "GND", 2, 1203.9298, 3985.0612, 1203.9298, 4010.5719, 11.811], ["346eaa8d5fc4b8e5", "GND", 2, 4018.8918999999996, 3985.0612, 4018.8918999999996, 4010.5719, 11.811], ["b4db2bdb883d31dc", "GND", 2, 6833.8501, 3985.0612, 6833.8501, 4010.5719, 11.811], ["05b72f6b3e19e182", "GND", 2, 3242.923, 1327.5794999999998, 3266.6302, 1331.983, 11.811], ["297956b985c44082", "GND", 2, 6057.8812, 1327.5794999999998, 6081.5884, 1331.983, 11.811], ["4ec00289f40ca91d", "GND", 2, 3823.6399, 2176.3713, 3849.1505, 2176.3713, 11.811], ["fa8c4e50dd25e24f", "GND", 2, 3975.2226, 2941.7417, 4000.7333, 2941.7417, 11.811], ["1559152cb05683e1", "GND", 2, 3841.3603000000003, 2404.71, 3862.4242, 2382.8469, 11.811], ["0cf809e7253c3fff", "GND", 2, 3753.1280000000006, 2412.5919, 3727.6174, 2412.5919, 11.811], ["108eaeef00b86b46", "GND", 2, 3945.6911, 2307.08, 3971.2018, 2307.08, 11.811], ["63d4ad99a2ebf3ba", "GND", 2, 4089.392, 2412.5919, 4114.9026, 2412.5919, 11.811], ["48b25ea18420781e", "GND", 2, 3481.12, 2839.3834000000006, 3485.5235, 2863.0906, 11.811], ["8ad6db704a488cff", "GND", 2, 3641.7303, 2827.5724, 3641.7303, 2853.8823, 11.811], ["118ea3d7e82fe05e", "GND", 2, 3898.7973999999995, 2941.7417, 3873.2866999999997, 2941.7417, 11.811], ["8c3286cfcaa3a922", "GND", 2, 4209.4629, 2498.0289, 4235.7728, 2498.0289, 11.811], ["d8b18fbe731f3383", "GND", 2, 3844.6812, 2902.9684, 3872.5677, 2902.9684, 11.811], ["f03a60b952c60770", "GND", 2, 1105.0085, 3985.0612, 1105.0085, 4011.4836000000005, 11.811], ["18d068d1397dc006", "GND", 2, 3919.9706000000006, 3985.0612, 3919.9706000000006, 4011.4836000000005, 11.811], ["0034168d1f0d4473", "GND", 2, 6734.9288, 3985.0612, 6734.9288, 4011.4836000000005, 11.811], ["ea0f3231d8f6c048", "GND", 2, 3343.1514000000006, 1318.8984, 3369.0738, 1318.8984, 11.811], ["14e86f2c167dadb3", "GND", 2, 6158.1096, 1318.8984, 6184.031999999999, 1318.8984, 11.811], ["b313eef34ef39b27", "GND", 2, 3809.8603, 2402.9107, 3863.5836, 2349.6875, 11.811], ["8a2d6ee2078a7f2a", "GND", 2, 4304.4393, 2672.0723, 4304.4393, 2698.4947, 11.811], ["44f7ca1018c738f7", "GND", 2, 8211.3115, 2548.0526, 8211.3115, 2574.4749, 11.811], ["45c8f5e7298c8ad4", "GND", 2, 8211.3115, 2351.2021, 8211.3115, 2377.6244, 11.811], ["62fefe118336ec9b", "GND", 2, 4211.2621, 2687.0093, 4237.1845, 2687.0093, 11.811], ["0ab9cbd9b2cbc54b", "GND", 2, 4304.4393, 2560.2179, 4304.4393, 2533.7955, 11.811], ["7305a49aec8b8ee5", "GND", 2, 3053.8284, 2429.9423, 3053.8284, 2456.3646, 11.811], ["067136ab178e2fac", "GND", 2, 660.1303, 3512.62, 660.1303, 3539.0423999999994, 11.811], ["1d0c20e8515cb457", "GND", 2, 3475.0885, 3512.62, 3475.0885, 3539.0423999999994, 11.811], ["184b02715b7e0593", "GND", 2, 6290.0506, 3512.62, 6290.0506, 3539.0423999999994, 11.811], ["f8bd9b6b356e4527", "GND", 2, 3788.0296, 1791.3396, 3813.952, 1791.3396, 11.811], ["dc25065c6abf5b44", "GND", 2, 6602.9918, 1791.3396, 6628.9141, 1791.3396, 11.811], ["bfd3b89a9852c125", "GND", 2, 1442.9102, 3976.3801000000003, 1467.5704, 3976.3801000000003, 11.811], ["5d5ad93569deaaaf", "GND", 2, 4257.8724, 3976.3801000000003, 4282.5325, 3976.3801000000003, 11.811], ["a1920c02d3d75bc6", "GND", 2, 7072.830599999999, 3976.3801000000003, 7097.4907, 3976.3801000000003, 11.811], ["b7cfb376f0132b06", "GND", 2, 3035.4308, 1318.8984, 3060.0909, 1318.8984, 11.811], ["7c3f873dea1b459b", "GND", 2, 5850.392899999999, 1318.8984, 5875.053, 1318.8984, 11.811], ["94d4a744a3885725", "GND", 2, 913.3903, 3470.9881, 913.3903, 3446.8883, 11.811], ["5cefd160d658a182", "GND", 2, 3728.3485, 3470.9881, 3728.3485, 3446.8883, 11.811], ["f345ac6a6e2993ed", "GND", 2, 6543.3106, 3470.9881, 6543.3106, 3446.8883, 11.811], ["27a8b6fa1bd08f44", "GND", 2, 3525.5885, 1824.2824999999998, 3525.5885, 1848.3823000000002, 11.811], ["af93fdac5c104659", "GND", 2, 6340.5507, 1824.2824999999998, 6340.5507, 1848.3823000000002, 11.811], ["e53d993aabb80a8e", "GND", 2, 3840.5395, 2326.7946, 3879.3905, 2321.7379, 11.811], ["814f25dc369adb56", "GND", 2, 3702.7599, 2302.9087, 3676.6394, 2302.9087, 11.811], ["18b1cfc1dac9f6a2", "GND", 2, 3152.149, 2327.7316, 3152.149, 2356.8188, 11.811], ["35418ee92e85858a", "GND", 2, 2748.7100999999993, 1032.2998, 2748.7100999999993, 1058.7221, 11.811], ["6c7c86d1defbecb3", "GND", 2, 3626, 2125.9815, 3663.254, 2125.9815, 11.811], ["3595aa1f976125d2", "GND", 2, 7132.5196, 4173.2306, 7158.442, 4173.2306, 11.811], ["256805f45331e815", "GND", 2, 2469.3124, 2345.6587, 2494.823, 2345.6587, 11.811], ["819e0688fd09a9b2", "GND", 2, 2271.6705, 415.35849999999994, 2297.1167, 415.35849999999994, 11.811], ["1b685e7acae9ea79", "GND", 2, 1205.5203, 4181.9117, 1221.8157, 4197.4078, 11.811], ["1f4b8082471d4b4f", "GND", 2, 4020.4825, 4181.9117, 4036.7778, 4197.4078, 11.811], ["3dce789ea9473ce0", "GND", 2, 4771.4908, 2762.6393, 4804.2146, 2768.4143, 11.811], ["d86c1d08da830ed8", "GND", 2, 2080.7196, 1055.6502, 2099.0716, 1069.2522, 11.811], ["9692e6d5b80be4b8", "GND", 2, 2277.5701, 1055.6502, 2295.9221, 1069.2522, 11.811], ["4d45508e1716e737", "GND", 2, 2393.1332, 4409.4512, 2430.3872, 4409.4512, 11.811], ["f460846385bd25aa", "GND", 2, 2474.4206, 1023.6187, 2511.6746, 1023.6187, 11.811], ["803d6aee5328864f", "GND", 2, 2412.8104, 4271.6519, 2450.0644, 4271.6519, 11.811], ["45042728b711db07", "GND", 2, 2276.7689, 894.5123, 2276.7689, 920.0229, 11.811], ["ffbe89450a83c98e", "GND", 2, 2213.375, 4303.6834, 2213.375, 4331.275, 11.811], ["f08c80e36ed45a93", "GND", 2, 1964.5503000000003, 4239.6204, 1946.1983, 4226.0184, 11.811], ["7fec29ad9d6e3f33", "GND", 2, 1996.0838, 415.35849999999994, 2021.5299, 415.35849999999994, 11.811], ["e4d3b671030a2ba0", "GND", 2, 2170.0917, 4418.1323, 2186.3871, 4433.6284, 11.811], ["54cb3a1fe4dbb560", "GND", 2, 3153.5489, 1122.0518, 3128.8888, 1122.0518, 11.811], ["10311250bf56bcda", "GND", 2, 5208.091400000001, 4409.4512, 5245.3454, 4409.4512, 11.811], ["e6a3843d60e09074", "GND", 2, 2945.5606, 1130.7329, 2945.5606, 1157.1553, 11.811], ["0b4f52b306a29048", "GND", 2, 5227.7804, 4271.6519, 5265.0344, 4271.6519, 11.811], ["c88e0b0a1e8cf80e", "GND", 2, 3241.3285, 1130.7329, 3241.3285, 1156.2435, 11.811], ["781a24e3c929eba6", "GND", 2, 5028.3372, 4303.6834, 5028.3372, 4331.275, 11.811], ["f7a1e1028d9a57cf", "GND", 2, 4779.5085, 4239.6204, 4761.1565, 4226.0184, 11.811], ["0007d2bc77abbb7f", "GND", 2, 5563.668399999999, 1032.2998, 5563.668399999999, 1058.7221, 11.811], ["d383496f10928176", "GND", 2, 4985.0499, 4418.1323, 5001.3453, 4433.6284, 11.811], ["8aac09b8f16b1681", "GND", 2, 4948.8334, 415.35849999999994, 4974.2796, 415.35849999999994, 11.811], ["8b118e20359bf8ec", "GND", 2, 8023.0496, 4409.4512, 8060.303599999999, 4409.4512, 11.811], ["394693e9071f246d", "GND", 2, 8042.7425, 4271.6519, 8079.996499999999, 4271.6519, 11.811], ["55a17b4b238d8fba", "GND", 2, 4900.4121, 706.0201, 4926.8345, 706.0201, 11.811], ["152556b733fd53a6", "GND", 2, 7843.3072, 4303.6834, 7843.3072, 4331.275, 11.811], ["96f6fbf6f62050ea", "GND", 2, 7594.4785, 4239.6204, 7576.1265, 4226.0184, 11.811], ["f76718982c0bda1e", "GND", 2, 5086.6327, 415.35849999999994, 5112.0789, 415.35849999999994, 11.811], ["c7fa7d10669a6fcc", "GND", 2, 7800.0121, 4418.1323, 7816.3074, 4433.6284, 11.811], ["d22b3cc0266dd503", "GND", 2, 7547.240300000001, 2871.8519000000006, 7570.6632, 2871.8519000000006, 11.811], ["df29b84a245a3b1c", "GND", 2, 7863.0121, 2680.3085, 7888.5228, 2680.3085, 11.811], ["4beca07cfdfa3165", "GND", 2, 1947.6625, 706.0201, 1974.0848, 706.0201, 11.811], ["3772611a4ffd4043", "GND", 2, 2133.8712, 415.35849999999994, 2159.3174, 415.35849999999994, 11.811], ["bc876558f54cdce5", "GND", 2, 5642.4086, 1032.2998, 5642.4086, 1058.7221, 11.811], ["2cf39c8f498c81ec", "GND", 2, 4915.3708, 917.8627, 4933.7228, 931.4647, 11.811], ["fb1821985d632dcb", "GND", 2, 4895.6818, 1055.6502, 4914.0338, 1069.2522, 11.811], ["1fe8d3c44e919f8b", "GND", 2, 5038.2114, 706.0201, 5064.6338, 706.0201, 11.811], ["cba649781778a78d", "GND", 2, 5092.5323, 1055.6502, 5110.8843, 1069.2522, 11.811], ["b69c982621a01675", "GND", 2, 5968.5072, 1122.0518, 5943.847, 1122.0518, 11.811], ["54f1faf582d95526", "GND", 2, 2827.4503, 1032.2998, 2827.4503, 1058.7221, 11.811], ["ea209e48bbf493bc", "GND", 2, 4811.042, 415.35849999999994, 4836.4882, 415.35849999999994, 11.811], ["cbd4b934836f123f", "GND", 2, 4589.7584, 2882.7023, 4589.7584, 2908.213, 11.811], ["84c3d15e5fece14c", "GND", 2, 2478.3635, 4879.92, 2503.8097, 4879.92, 11.811], ["4a9a10ee8d40605c", "GND", 2, 2340.5643, 4879.92, 2366.0104, 4879.92, 11.811], ["014c9df7b18123ee", "GND", 2, 2202.7728, 4879.92, 2228.219, 4879.92, 11.811], ["fca91834a5f2b49d", "GND", 2, 5293.3218, 4879.92, 5318.767900000001, 4879.92, 11.811], ["aa3865f4372607e0", "GND", 2, 5155.5303, 4879.92, 5180.976499999999, 4879.92, 11.811], ["52f129cc269a4594", "GND", 2, 5017.7311, 4879.92, 5043.1772, 4879.92, 11.811], ["0a2ed79036536678", "GND", 2, 8108.2839, 4879.92, 8133.730100000001, 4879.92, 11.811], ["3f4a7a95602cefcd", "GND", 2, 7970.4925, 4879.92, 7995.938699999999, 4879.92, 11.811], ["dc19b7d41f873541", "GND", 2, 7832.6932, 4879.92, 7858.1394, 4879.92, 11.811], ["dc167b9b374d338d", "GND", 2, 2508.6825, 4589.2584, 2535.1048, 4589.2584, 11.811], ["c7e1fcd726e0ead1", "GND", 2, 2370.8792, 4589.2584, 2397.3016, 4589.2584, 11.811], ["4d824a5c38a0796d", "GND", 2, 2233.0918, 4589.2584, 2259.5141, 4589.2584, 11.811], ["3aefee0883abe7a5", "GND", 2, 5323.6407, 4589.2584, 5350.063, 4589.2584, 11.811], ["34ebe58670e6f3e8", "GND", 2, 5185.8493, 4589.2584, 5212.2716, 4589.2584, 11.811], ["f4e8da43df210123", "GND", 2, 5048.05, 4589.2584, 5074.4723, 4589.2584, 11.811], ["d436f50f1efbe28c", "GND", 2, 8138.6028, 4589.2584, 8165.0252, 4589.2584, 11.811], ["a17731058d247f21", "GND", 2, 8000.8114000000005, 4589.2584, 8027.2338, 4589.2584, 11.811], ["6ab47b0e3d5f2005", "GND", 2, 7863.0121, 4589.2584, 7889.434499999999, 4589.2584, 11.811], ["4dbe557dc7985fe3", "GND", 2, 1502.5992, 4173.2306, 1528.5216, 4173.2306, 11.811], ["e1163876623478ee", "GND", 2, 5091.7311, 894.5123, 5091.7311, 920.0229, 11.811], ["1b2907a4ed19d429", "GND", 2, 4317.5614, 4173.2306, 4343.4838, 4173.2306, 11.811], ["469dc321704dc18a", "GND", 2, 6056.2907, 1130.7329, 6056.2907, 1156.2435, 11.811], ["ff5da687f9348dc9", "GND", 2, 1699.4497, 4271.6519, 1725.3721, 4271.6519, 11.811], ["bf624ed2bce2511f", "GND", 2, 2223.2492, 706.0201, 2249.6716, 706.0201, 11.811], ["1c8a9a283883fe6a", "GND", 2, 4514.4119, 4271.6519, 4540.3343, 4271.6519, 11.811], ["f320fd72fdd05565", "GND", 2, 7329.3701, 4271.6519, 7355.2925, 4271.6519, 11.811], ["1199331849e55ac4", "GND", 2, 4844.6916, 2547.2415, 4844.6916, 2570.6645, 11.811], ["498a9c082407a05d", "GND", 2, 2100.4126, 917.8627, 2118.7645, 931.4647, 11.811], ["4602d964982ba457", "GND", 2, 1620.7095, 4280.333, 1624.962, 4304.0833, 11.811], ["2f26ef1d3798ab2a", "GND", 2, 4435.6717, 4280.333, 4439.9241, 4304.0833, 11.811], ["4df8f74d8255a7f6", "GND", 2, 4762.6207, 706.0201, 4789.0431, 706.0201, 11.811], ["d2182d92a080bac7", "GND", 2, 7250.6299, 4280.333, 7254.8823, 4304.0833, 11.811], ["a93c6ceed04c12cc", "GND", 2, 5022.8295, 2882.7023, 5022.8295, 2908.213, 11.811], ["941ffa4bb5f6b031", "GND", 2, 6835.4407, 4181.9117, 6851.736, 4197.4078, 11.811], ["7f68773417eaac9d", "GND", 2, 3514.5728, 2492.1195, 3493.9568, 2500.542, 11.811], ["627e16cabb624966", "GND", 2, 6915.350200000001, 4173.2306, 6940.0103, 4173.2306, 11.811], ["e6730ccb7003e212", "GND", 2, 2213.3929, 2437.1982, 2236.6467, 2437.1982, 11.811], ["4abd7fcbebdd8a35", "GND", 2, 2353.5308, 2337.1981, 2330.277, 2337.1981, 11.811], ["7682e6aeacb762df", "GND", 2, 2353.5308, 2387.1981, 2330.277, 2387.1981, 11.811], ["2adb6813f488cc5a", "GND", 2, 2426.393, 2437.1982, 2449.6468, 2437.1982, 11.811], ["27e8b26827c97fe8", "GND", 2, 2085.4499, 706.0201, 2111.8723, 706.0201, 11.811], ["c53135161b955b02", "GND", 2, 1285.4298, 4173.2306, 1310.09, 4173.2306, 11.811], ["befe0ae1a0a3dcc4", "GND", 2, 5289.382800000001, 1023.6187, 5326.6368, 1023.6187, 11.811], ["e6861bc111650aa4", "GND", 2, 4100.392, 4173.2306, 4125.0521, 4173.2306, 11.811], ["3bcf9e0b7493b34c", "GND", 2, 5760.518899999999, 1130.7329, 5760.518899999999, 1157.1553, 11.811], ["b4df1edfdf1fa53a", "GND", 1, 2781.5192, 4803.542, 2815.4125, 4803.542, 11.811], ["4f38a9815d4a7a1a", "GND", 1, 5596.481400000001, 4803.542, 5630.3746, 4803.542, 11.811], ["ecc043bfff7181cd", "GND", 1, 8411.4396, 4803.542, 8445.3328, 4803.542, 11.811], ["190239663e3f3064", "GND", 1, 1685.0403000000001, 519.3093, 1685.0403000000001, 553.2026, 11.811], ["56774660ffe88ef1", "GND", 1, 4499.9985, 519.3093, 4499.9985, 553.2026, 11.811], ["381edc10465929bb", "GND", 2, 3644.8839, 2357.1115, 3646.8704, 2385.26, 11.811], ["4e66a09fee67dd9e", "GND", 2, 8352.0444, 2579.3091, 8315.645, 2579.3091, 11.811], ["252757cc0cab31a7", "GND", 2, 8352.0434, 2306.6376, 8314.7442, 2306.6376, 11.811], ["a453a3fc66bc536b", "GND", 2, 4158.8172, 2536.5998, 4132.7809, 2503.3105, 5.9055], ["2c56909adb6a8c43", "GND", 2, 3828.7462, 2837.5822, 3828.7462, 2814.9201, 7.874], ["e147f72dc48db54c", "GND", 2, 933.0709, 3580.315, 933.0709, 3603.5433000000003, 4.3307], ["7a540be3b62ac1f3", "GND", 2, 933.0709, 3603.5433000000003, 933.0709, 3612.7953, 11.811], ["2dcf28a2ea50d591", "GND", 2, 933.0709, 3612.7953, 923.8189, 3622.0473, 11.811], ["bd253af5ea51055f", "GND", 2, 891.7323, 3580.315, 891.7323, 3603.5433000000003, 4.3307], ["468fc4d4a33db5dd", "GND", 2, 891.7323, 3603.5433000000003, 891.7323, 3622.0473, 11.811], ["8adf2ccb2996ee5a", "GND", 2, 923.8189, 3622.0473, 891.7323, 3622.0473, 11.811], ["229a4b7241170f90", "GND", 2, 864.1732, 3580.315, 864.1732, 3603.5433000000003, 4.3307], ["77944fcb12de2cf4", "GND", 2, 864.1732, 3603.5433000000003, 864.1732, 3622.0473, 11.811], ["d02f3dffbb1fc9b6", "GND", 2, 891.7323, 3622.0473, 864.1732, 3622.0473, 11.811], ["83c1e2f0430773f5", "GND", 2, 836.6142, 3580.315, 836.6142, 3603.5433000000003, 4.3307], ["952b8a75e0d4f7e7", "GND", 2, 836.6142, 3603.5433000000003, 836.6142, 3622.0473, 11.811], ["50509dc0b60bcbff", "GND", 2, 864.1732, 3622.0473, 836.6142, 3622.0473, 11.811], ["e05fa6c8c19ae368", "GND", 2, 836.6142, 3622.0473, 781.4961, 3622.0473, 11.811], ["4df50b0d6a54a073", "GND", 2, 781.4961, 3580.315, 781.4961, 3603.5433000000003, 4.3307], ["1f67290c10fd0b58", "GND", 2, 781.4961, 3603.5433000000003, 781.4961, 3622.0473, 11.811], ["28bdf7e229b31596", "GND", 2, 933.0709, 3663.7796, 933.0709, 3687.0078999999996, 4.3307], ["fdafd10b31f0bdad", "GND", 2, 933.0709, 3687.0078999999996, 933.0709, 3691.9292, 11.811], ["8f9c7787e868631f", "GND", 2, 933.0709, 3691.9292, 928.1496, 3696.8503999999994, 11.811], ["77e33ee9188d17bb", "GND", 2, 809.0551, 3663.7796, 809.0551, 3687.0078999999996, 4.3307], ["4a24fe2d0567fd5f", "GND", 2, 809.0551, 3687.0078999999996, 809.0551, 3696.8503999999994, 11.811], ["dd19d7b571b7a76c", "GND", 2, 928.1496, 3696.8503999999994, 809.0551, 3696.8503999999994, 11.811], ["d25be44936d42f65", "GND", 2, 781.4961, 3663.7796, 781.4961, 3687.0078999999996, 4.3307], ["c26eb4c7efccdd11", "GND", 2, 781.4961, 3687.0078999999996, 781.4961, 3696.8503999999994, 11.811], ["dce94d8db5dc57df", "GND", 2, 809.0551, 3696.8503999999994, 781.4961, 3696.8503999999994, 11.811], ["af32e755b75e06bd", "GND", 2, 740.1575, 3663.7796, 740.1575, 3687.0078999999996, 4.3307], ["526b8c64c9150084", "GND", 2, 740.1575, 3687.0078999999996, 740.1575, 3696.8503999999994, 11.811], ["aa5fea22772882bd", "GND", 2, 781.4961, 3696.8503999999994, 740.1575, 3696.8503999999994, 11.811], ["101b048b4a7c52eb", "GND", 2, 685.0394, 3663.7796, 685.0394, 3687.0078999999996, 4.3307], ["60aeaa41a1777503", "GND", 2, 685.0394, 3687.0078999999996, 685.0394, 3696.8503999999994, 11.811], ["8c7b22a423a3d4cc", "GND", 2, 740.1575, 3696.8503999999994, 685.0394, 3696.8503999999994, 11.811], ["11f546b63b4f9d9d", "GND", 2, 657.4802999999999, 3663.7796, 657.4802999999999, 3687.0078999999996, 4.3307], ["23b60b5b49bf3d14", "GND", 2, 657.4802999999999, 3687.0078999999996, 657.4802999999999, 3696.8503999999994, 11.811], ["3e04f2ab50c463e6", "GND", 2, 685.0394, 3696.8503999999994, 657.4802999999999, 3696.8503999999994, 11.811], ["1aed64a2e359622a", "GND", 2, 657.4802999999999, 3696.8503999999994, 616.1417, 3696.8503999999994, 11.811], ["9ad449eb917cac68", "GND", 2, 616.1417, 3663.7796, 616.1417, 3687.0078999999996, 4.3307], ["b6d0f7af6f2df76a", "GND", 2, 616.1417, 3687.0078999999996, 616.1417, 3696.8503999999994, 11.811], ["6ac23cd202109763", "GND", 2, 530.315, 3622.0473, 488.18899999999996, 3622.0473, 11.811], ["797f595d091cfb8e", "GND", 2, 3748.0315, 3580.315, 3748.0315, 3603.5433000000003, 4.3307], ["677202d3d72a6192", "GND", 2, 3748.0315, 3603.5433000000003, 3748.0315, 3612.7953, 11.811], ["8ed94f8d436d2c3b", "GND", 2, 3748.0315, 3612.7953, 3738.7796, 3622.0473, 11.811], ["c083d94c2ea102e5", "GND", 2, 3706.6929, 3580.315, 3706.6929, 3603.5433000000003, 4.3307], ["8be3ab7523241b72", "GND", 2, 3706.6929, 3603.5433000000003, 3706.6929, 3622.0473, 11.811], ["7716cdc17787ea0d", "GND", 2, 3738.7796, 3622.0473, 3706.6929, 3622.0473, 11.811], ["61e260edbf722820", "GND", 2, 3679.1339, 3580.315, 3679.1339, 3603.5433000000003, 4.3307], ["0d466df230cd2c9e", "GND", 2, 3679.1339, 3603.5433000000003, 3679.1339, 3622.0473, 11.811], ["40921cf3fb9ef4b3", "GND", 2, 3706.6929, 3622.0473, 3679.1339, 3622.0473, 11.811], ["e69e4d278c83391c", "GND", 2, 3651.5747999999994, 3580.315, 3651.5747999999994, 3603.5433000000003, 4.3307], ["1727cbe3e3a118d7", "GND", 2, 3651.5747999999994, 3603.5433000000003, 3651.5747999999994, 3622.0473, 11.811], ["bd6c74f48777dd11", "GND", 2, 3679.1339, 3622.0473, 3651.5747999999994, 3622.0473, 11.811], ["f2f2715d0679ab9a", "GND", 2, 3651.5747999999994, 3622.0473, 3596.4566999999997, 3622.0473, 11.811], ["1df8d13e11ce9588", "GND", 2, 3596.4566999999997, 3580.315, 3596.4566999999997, 3603.5433000000003, 4.3307], ["634af639139b61f4", "GND", 2, 3596.4566999999997, 3603.5433000000003, 3596.4566999999997, 3622.0473, 11.811], ["530595812099ba8e", "GND", 2, 3748.0315, 3663.7796, 3748.0315, 3687.0078999999996, 4.3307], ["0713677c0343016e", "GND", 2, 3748.0315, 3687.0078999999996, 3748.0315, 3691.9292, 11.811], ["823539c965a1ac0b", "GND", 2, 3748.0315, 3691.9292, 3743.1102999999994, 3696.8503999999994, 11.811], ["3181d7a8027a3a22", "GND", 2, 3624.0158, 3663.7796, 3624.0158, 3687.0078999999996, 4.3307], ["ee177c8fc52e1649", "GND", 2, 3624.0158, 3687.0078999999996, 3624.0158, 3696.8503999999994, 11.811], ["9435f5900e261efc", "GND", 2, 3743.1102999999994, 3696.8503999999994, 3624.0158, 3696.8503999999994, 11.811], ["876b7610b4eaf62e", "GND", 2, 3596.4566999999997, 3663.7796, 3596.4566999999997, 3687.0078999999996, 4.3307], ["267f937f33fc7454", "GND", 2, 3596.4566999999997, 3687.0078999999996, 3596.4566999999997, 3696.8503999999994, 11.811], ["d4564205ab6f0485", "GND", 2, 3624.0158, 3696.8503999999994, 3596.4566999999997, 3696.8503999999994, 11.811], ["091e5626710e6bcc", "GND", 2, 3555.1181, 3663.7796, 3555.1181, 3687.0078999999996, 4.3307], ["aca9540126171fec", "GND", 2, 3555.1181, 3687.0078999999996, 3555.1181, 3696.8503999999994, 11.811], ["b8ee0564370a2393", "GND", 2, 3596.4566999999997, 3696.8503999999994, 3555.1181, 3696.8503999999994, 11.811], ["d2c01bf350c72616", "GND", 2, 3500, 3663.7796, 3500, 3687.0078999999996, 4.3307], ["e2e4b3727a42335f", "GND", 2, 3500, 3687.0078999999996, 3500, 3696.8503999999994, 11.811], ["47ecda9cc78cae1c", "GND", 2, 3555.1181, 3696.8503999999994, 3500, 3696.8503999999994, 11.811], ["e9f8aaae4cd5adcf", "GND", 2, 3472.441, 3663.7796, 3472.441, 3687.0078999999996, 4.3307], ["cb03f936df30b3b5", "GND", 2, 3472.441, 3687.0078999999996, 3472.441, 3696.8503999999994, 11.811], ["c901aa91deaff2cf", "GND", 2, 3500, 3696.8503999999994, 3472.441, 3696.8503999999994, 11.811], ["4b595f37a5ce75e2", "GND", 2, 3472.441, 3696.8503999999994, 3431.1024, 3696.8503999999994, 11.811], ["af5a1299b823d261", "GND", 2, 3431.1024, 3663.7796, 3431.1024, 3687.0078999999996, 4.3307], ["3b8d9e057ba4ca00", "GND", 2, 3431.1024, 3687.0078999999996, 3431.1024, 3696.8503999999994, 11.811], ["53b32c971eda315a", "GND", 2, 3345.2756, 3622.0473, 3303.1496000000006, 3622.0473, 11.811], ["91bdfb2da4cccbe9", "GND", 2, 6562.9922, 3580.315, 6562.9922, 3603.5433000000003, 4.3307], ["b2be911d8b699439", "GND", 2, 6562.9922, 3603.5433000000003, 6562.9922, 3612.7953, 11.811], ["cfdd927bc22a4928", "GND", 2, 6562.9922, 3612.7953, 6553.7402, 3622.0473, 11.811], ["c02327b7950c8229", "GND", 2, 6521.6536, 3580.315, 6521.6536, 3603.5433000000003, 4.3307], ["ea87c8f9e8d7dbc9", "GND", 2, 6521.6536, 3603.5433000000003, 6521.6536, 3622.0473, 11.811], ["bd7c276b4a523acb", "GND", 2, 6553.7402, 3622.0473, 6521.6536, 3622.0473, 11.811], ["30dc8343ae3ff3ad", "GND", 2, 6494.0945, 3580.315, 6494.0945, 3603.5433000000003, 4.3307], ["118d1ca447dd361b", "GND", 2, 6494.0945, 3603.5433000000003, 6494.0945, 3622.0473, 11.811], ["2a1e1a1cc566f91e", "GND", 2, 6521.6536, 3622.0473, 6494.0945, 3622.0473, 11.811], ["0724c3b54f9d2e98", "GND", 2, 6466.5355, 3580.315, 6466.5355, 3603.5433000000003, 4.3307], ["d56c1f3fb447d01f", "GND", 2, 6466.5355, 3603.5433000000003, 6466.5355, 3622.0473, 11.811], ["5f1ee4b96f14628b", "GND", 2, 6494.0945, 3622.0473, 6466.5355, 3622.0473, 11.811], ["85e594bec3662663", "GND", 2, 6466.5355, 3622.0473, 6411.4174, 3622.0473, 11.811], ["66c4540579ec9152", "GND", 2, 6411.4174, 3580.315, 6411.4174, 3603.5433000000003, 4.3307], ["27782ec1c9cd5f27", "GND", 2, 6411.4174, 3603.5433000000003, 6411.4174, 3622.0473, 11.811], ["9d1cc40a74c0ce8a", "GND", 2, 6562.9922, 3663.7796, 6562.9922, 3687.0078999999996, 4.3307], ["64fd5c9b300903d8", "GND", 2, 6562.9922, 3687.0078999999996, 6562.9922, 3691.9292, 11.811], ["f6a94c130379c654", "GND", 2, 6562.9922, 3691.9292, 6558.070900000001, 3696.8503999999994, 11.811], ["dbd833f21c6badba", "GND", 2, 6438.9764, 3663.7796, 6438.9764, 3687.0078999999996, 4.3307], ["bd28699827b48aa0", "GND", 2, 6438.9764, 3687.0078999999996, 6438.9764, 3696.8503999999994, 11.811], ["10d094f2d80d3885", "GND", 2, 6558.070900000001, 3696.8503999999994, 6438.9764, 3696.8503999999994, 11.811], ["7656f34860ed47a2", "GND", 2, 6411.4174, 3663.7796, 6411.4174, 3687.0078999999996, 4.3307], ["3accbf9776c7df28", "GND", 2, 6411.4174, 3687.0078999999996, 6411.4174, 3696.8503999999994, 11.811], ["2b492c9f1b931060", "GND", 2, 6438.9764, 3696.8503999999994, 6411.4174, 3696.8503999999994, 11.811], ["073e67f88a051de5", "GND", 2, 6370.0788, 3663.7796, 6370.0788, 3687.0078999999996, 4.3307], ["0e6e0d31caeede57", "GND", 2, 6370.0788, 3687.0078999999996, 6370.0788, 3696.8503999999994, 11.811], ["9cfbb7f7fcbc55a9", "GND", 2, 6411.4174, 3696.8503999999994, 6370.0788, 3696.8503999999994, 11.811], ["9f0937b2af2aff64", "GND", 2, 6314.9607, 3663.7796, 6314.9607, 3687.0078999999996, 4.3307], ["ced07e95f9baa22f", "GND", 2, 6314.9607, 3687.0078999999996, 6314.9607, 3696.8503999999994, 11.811], ["1fe1673aa38805ef", "GND", 2, 6370.0788, 3696.8503999999994, 6314.9607, 3696.8503999999994, 11.811], ["ad10e62706db1027", "GND", 2, 6287.401600000001, 3663.7796, 6287.401600000001, 3687.0078999999996, 4.3307], ["eb81535f32b42267", "GND", 2, 6287.401600000001, 3687.0078999999996, 6287.401600000001, 3696.8503999999994, 11.811], ["dbce2d964b0d4efa", "GND", 2, 6314.9607, 3696.8503999999994, 6287.401600000001, 3696.8503999999994, 11.811], ["e7f6a591152a4292", "GND", 2, 6287.401600000001, 3696.8503999999994, 6246.063, 3696.8503999999994, 11.811], ["d79db664fadb9198", "GND", 2, 6246.063, 3663.7796, 6246.063, 3687.0078999999996, 4.3307], ["9830cbf3efd1633d", "GND", 2, 6246.063, 3687.0078999999996, 6246.063, 3696.8503999999994, 11.811], ["878395586e0b34ff", "GND", 2, 6160.236299999999, 3622.0473, 6118.1103, 3622.0473, 11.811], ["62ffc63b895d9d30", "GND", 2, 3505.9055, 1714.9605999999999, 3505.9055, 1691.7323, 4.3307], ["ffb292d16d82cf7b", "GND", 2, 3505.9055, 1691.7323, 3505.9055, 1682.4803, 11.811], ["488527623cd3eb5d", "GND", 2, 3505.9055, 1682.4803, 3515.1575, 1673.2284, 11.811], ["4be17d3f337152a7", "GND", 2, 3547.2441, 1714.9605999999999, 3547.2441, 1691.7323, 4.3307], ["1c527ce948f5707c", "GND", 2, 3547.2441, 1691.7323, 3547.2441, 1673.2284, 11.811], ["76bcc99c4553a598", "GND", 2, 3515.1575, 1673.2284, 3547.2441, 1673.2284, 11.811], ["c1e97f94b448ce7e", "GND", 2, 3574.8032000000003, 1714.9605999999999, 3574.8032000000003, 1691.7323, 4.3307], ["7690bac2c418ad7c", "GND", 2, 3574.8032000000003, 1691.7323, 3574.8032000000003, 1673.2284, 11.811], ["eda3d180a0773486", "GND", 2, 3547.2441, 1673.2284, 3574.8032000000003, 1673.2284, 11.811], ["69d2d3ab9213ba63", "GND", 2, 3602.3622, 1714.9605999999999, 3602.3622, 1691.7323, 4.3307], ["ad076cdfb227c35f", "GND", 2, 3602.3622, 1691.7323, 3602.3622, 1673.2284, 11.811], ["12e201f3d9e7dc4e", "GND", 2, 3574.8032000000003, 1673.2284, 3602.3622, 1673.2284, 11.811], ["b9bf8257dde8d303", "GND", 2, 3602.3622, 1673.2284, 3657.4803, 1673.2284, 11.811], ["84010e6f11ddfa0f", "GND", 2, 3657.4803, 1714.9605999999999, 3657.4803, 1691.7323, 4.3307], ["27c8a2f12f735e55", "GND", 2, 3657.4803, 1691.7323, 3657.4803, 1673.2284, 11.811], ["2c4e97d8d9288496", "GND", 2, 3505.9055, 1631.4960999999998, 3505.9055, 1608.2677, 4.3307], ["9128776dc5a8ad60", "GND", 2, 3505.9055, 1608.2677, 3505.9055, 1603.3465, 11.811], ["93d7ec2a8002f96a", "GND", 2, 3505.9055, 1603.3465, 3510.8268, 1598.4251999999997, 11.811], ["28e5dac87858bc35", "GND", 2, 3629.9213, 1631.4960999999998, 3629.9213, 1608.2677, 4.3307], ["1dffe7189e155efc", "GND", 2, 3629.9213, 1608.2677, 3629.9213, 1598.4251999999997, 11.811], ["8987c5a501363225", "GND", 2, 3510.8268, 1598.4251999999997, 3629.9213, 1598.4251999999997, 11.811], ["1358eef826a6ba18", "GND", 2, 3657.4803, 1631.4960999999998, 3657.4803, 1608.2677, 4.3307], ["b04faaffc2c97574", "GND", 2, 3657.4803, 1608.2677, 3657.4803, 1598.4251999999997, 11.811], ["d000d93a8ffad173", "GND", 2, 3629.9213, 1598.4251999999997, 3657.4803, 1598.4251999999997, 11.811], ["1ab1c46455743abc", "GND", 2, 3698.8189, 1631.4960999999998, 3698.8189, 1608.2677, 4.3307], ["b24788566e8107a2", "GND", 2, 3698.8189, 1608.2677, 3698.8189, 1598.4251999999997, 11.811], ["fbd4b6d6c4bb8fcb", "GND", 2, 3657.4803, 1598.4251999999997, 3698.8189, 1598.4251999999997, 11.811], ["bfaf09b40f04921e", "GND", 2, 3753.937, 1631.4960999999998, 3753.937, 1608.2677, 4.3307], ["abbbf120563ba1f0", "GND", 2, 3753.937, 1608.2677, 3753.937, 1598.4251999999997, 11.811], ["679708d1a03abef7", "GND", 2, 3698.8189, 1598.4251999999997, 3753.937, 1598.4251999999997, 11.811], ["bb82205aebe708c6", "GND", 2, 3781.4961, 1631.4960999999998, 3781.4961, 1608.2677, 4.3307], ["48bc0eddd00953db", "GND", 2, 3781.4961, 1608.2677, 3781.4961, 1598.4251999999997, 11.811], ["0fbdfd0480ab165d", "GND", 2, 3753.937, 1598.4251999999997, 3781.4961, 1598.4251999999997, 11.811], ["c8b5aceaa38ea1d1", "GND", 2, 3781.4961, 1598.4251999999997, 3822.8346999999994, 1598.4251999999997, 11.811], ["51aa98361876f5b0", "GND", 2, 3822.8346999999994, 1631.4960999999998, 3822.8346999999994, 1608.2677, 4.3307], ["2c827e92bf70d7e0", "GND", 2, 3822.8346999999994, 1608.2677, 3822.8346999999994, 1598.4251999999997, 11.811], ["363d8aaadc8d3f79", "GND", 2, 3908.6614, 1673.2284, 3950.7874, 1673.2284, 11.811], ["02bec6b5d70d61ee", "GND", 2, 6320.8662, 1714.9605999999999, 6320.8662, 1691.7323, 4.3307], ["1a4b38c588ae64f9", "GND", 2, 6320.8662, 1691.7323, 6320.8662, 1682.4803, 11.811], ["c0944491b4a88465", "GND", 2, 6320.8662, 1682.4803, 6330.118199999999, 1673.2284, 11.811], ["bf08d73a6a517313", "GND", 2, 6362.2048, 1714.9605999999999, 6362.2048, 1691.7323, 4.3307], ["f750db3809f2c069", "GND", 2, 6362.2048, 1691.7323, 6362.2048, 1673.2284, 11.811], ["1906cc7b2ef975c5", "GND", 2, 6330.118199999999, 1673.2284, 6362.2048, 1673.2284, 11.811], ["11281730025964aa", "GND", 2, 6389.7638, 1714.9605999999999, 6389.7638, 1691.7323, 4.3307], ["585bec1667d8210a", "GND", 2, 6389.7638, 1691.7323, 6389.7638, 1673.2284, 11.811], ["4802926c054f70be", "GND", 2, 6362.2048, 1673.2284, 6389.7638, 1673.2284, 11.811], ["d96bc1efa06c5785", "GND", 2, 6417.3229, 1714.9605999999999, 6417.3229, 1691.7323, 4.3307], ["7491e89cefc559d0", "GND", 2, 6417.3229, 1691.7323, 6417.3229, 1673.2284, 11.811], ["88a69246cedf01d2", "GND", 2, 6389.7638, 1673.2284, 6417.3229, 1673.2284, 11.811], ["0ea4a2cd30384104", "GND", 2, 6417.3229, 1673.2284, 6472.441, 1673.2284, 11.811], ["8b91f8f8c8d80d50", "GND", 2, 6472.441, 1714.9605999999999, 6472.441, 1691.7323, 4.3307], ["f3867c5c7e6fc0ed", "GND", 2, 6472.441, 1691.7323, 6472.441, 1673.2284, 11.811], ["374e16a843742d31", "GND", 2, 6320.8662, 1631.4960999999998, 6320.8662, 1608.2677, 4.3307], ["98d8901027561345", "GND", 2, 6320.8662, 1608.2677, 6320.8662, 1603.3465, 11.811], ["5f4d7cf573e28273", "GND", 2, 6320.8662, 1603.3465, 6325.7874, 1598.4251999999997, 11.811], ["93fdc4beee0cbf1f", "GND", 2, 6444.8819, 1631.4960999999998, 6444.8819, 1608.2677, 4.3307], ["96c7f5a34393d081", "GND", 2, 6444.8819, 1608.2677, 6444.8819, 1598.4251999999997, 11.811], ["2299e63bdf9f83c9", "GND", 2, 6325.7874, 1598.4251999999997, 6444.8819, 1598.4251999999997, 11.811], ["a8b8352f3ee22ce7", "GND", 2, 6472.441, 1631.4960999999998, 6472.441, 1608.2677, 4.3307], ["5aea0b0a8241f64f", "GND", 2, 6472.441, 1608.2677, 6472.441, 1598.4251999999997, 11.811], ["9363a14f33070508", "GND", 2, 6444.8819, 1598.4251999999997, 6472.441, 1598.4251999999997, 11.811], ["30e8325e6deae14a", "GND", 2, 6513.7796, 1631.4960999999998, 6513.7796, 1608.2677, 4.3307], ["85ce300c209f6ee8", "GND", 2, 6513.7796, 1608.2677, 6513.7796, 1598.4251999999997, 11.811], ["699952a90ffdf614", "GND", 2, 6472.441, 1598.4251999999997, 6513.7796, 1598.4251999999997, 11.811], ["b7104ce0688a157f", "GND", 2, 6568.8976999999995, 1631.4960999999998, 6568.8976999999995, 1608.2677, 4.3307], ["6fdc8ecf347489c3", "GND", 2, 6568.8976999999995, 1608.2677, 6568.8976999999995, 1598.4251999999997, 11.811], ["d1b97bc30359817d", "GND", 2, 6513.7796, 1598.4251999999997, 6568.8976999999995, 1598.4251999999997, 11.811], ["e66c978a56e03601", "GND", 2, 6596.4567, 1631.4960999999998, 6596.4567, 1608.2677, 4.3307], ["472ec8f7189e47ce", "GND", 2, 6596.4567, 1608.2677, 6596.4567, 1598.4251999999997, 11.811], ["c3b29cac96f32f8d", "GND", 2, 6568.8976999999995, 1598.4251999999997, 6596.4567, 1598.4251999999997, 11.811], ["af9711624bbd1112", "GND", 2, 6596.4567, 1598.4251999999997, 6637.7953, 1598.4251999999997, 11.811], ["f280eb77713d84ac", "GND", 2, 6637.7953, 1631.4960999999998, 6637.7953, 1608.2677, 4.3307], ["39f949b51102c56a", "GND", 2, 6637.7953, 1608.2677, 6637.7953, 1598.4251999999997, 11.811], ["962eda12bffdb716", "GND", 2, 6723.6221000000005, 1673.2284, 6765.7481, 1673.2284, 11.811], ["4be0b3c20ec7bb1d", "THERM_1", 2, 850.3936999999999, 3580.315, 850.3936999999999, 3559.8425, 4.3307], ["aac7b2a1ac5baa41", "THERM_1", 2, 850.3936999999999, 3559.8425, 834.6457, 3544.0945, 4.3307], ["46c9986e11afa6d8", "THERM_1", 2, 834.6457, 3544.0945, 834.6457, 3537.7953, 7.874], ["9bd0dd464cd97d68", "THERM_1", 2, 834.6457, 3537.7953, 828.3465, 3531.4961, 7.874], ["41c9742721b2e355", "THERM_1", 1, 828.3465, 3531.4961, 706.0236, 3531.4961, 7.874], ["81c88dc4c093153d", "THERM_1", 1, 706.0236, 3531.4961, 694.2125999999998, 3519.6851000000006, 7.874], ["099cf8e397f2e1e6", "THERM_1", 2, 694.2125999999998, 3519.6851000000006, 694.2125999999998, 3507.874, 7.874], ["7cc2d5bb5c64b638", "THERM_1", 2, 694.2087000000001, 3503.941, 717.1693, 3503.941, 7.874], ["d1edab137eb4f16a", "THERM_1", 2, 696.8504, 3507.874, 717.1693, 3503.941, 7.874], ["dd85f83bd0230e0a", "THERM_2", 2, 3665.3544, 3580.315, 3665.3544, 3559.8425, 4.3307], ["2ee9c8c961cd5100", "THERM_2", 2, 3665.3544, 3559.8425, 3649.6063, 3544.0945, 4.3307], ["54461bfda7d84534", "THERM_2", 2, 3649.6063, 3544.0945, 3649.6063, 3537.7953, 7.874], ["56c5dd15817f5367", "THERM_2", 2, 3649.6063, 3537.7953, 3643.3071, 3531.4961, 7.874], ["95c3f8238d977849", "THERM_2", 1, 3643.3071, 3531.4961, 3520.9843, 3531.4961, 7.874], ["cbe50c124bf60a15", "THERM_2", 1, 3520.9843, 3531.4961, 3509.1733, 3519.6851000000006, 7.874], ["7a85554792afc64e", "THERM_2", 2, 3509.1733, 3519.6851000000006, 3509.1733, 3507.874, 7.874], ["d34385984f9b6606", "THERM_2", 2, 3509.1692999999996, 3503.941, 3532.1299, 3503.941, 7.874], ["93c7764315dda425", "THERM_2", 2, 3511.811, 3507.874, 3532.1299, 3503.941, 7.874], ["a1260b4f83a6e4b9", "THERM_3", 2, 6480.315, 3580.315, 6480.315, 3559.8425, 4.3307], ["c72d90ff41cdd55f", "THERM_3", 2, 6480.315, 3559.8425, 6464.566999999999, 3544.0945, 4.3307], ["930f1406fb4181f5", "THERM_3", 2, 6464.566999999999, 3544.0945, 6464.566999999999, 3537.7953, 7.874], ["e377f9bb7a719be7", "THERM_3", 2, 6464.566999999999, 3537.7953, 6458.2678, 3531.4961, 7.874], ["d425a82478dab242", "THERM_3", 1, 6458.2678, 3531.4961, 6335.9449, 3531.4961, 7.874], ["7a196dbe420c9975", "THERM_3", 1, 6335.9449, 3531.4961, 6324.133899999999, 3519.6851000000006, 7.874], ["8dd23e843c40afcb", "THERM_3", 2, 6324.133899999999, 3519.6851000000006, 6324.133899999999, 3507.874, 7.874], ["1fa52bc899a349c3", "THERM_3", 2, 6324.13, 3503.941, 6347.0906, 3503.941, 7.874], ["d08b8b6276253789", "THERM_3", 2, 6326.7717, 3507.874, 6347.0906, 3503.941, 7.874], ["2ad4679983e40bb1", "THERM_4", 2, 3588.5827, 1714.9605999999999, 3588.5827, 1735.4331, 4.3307], ["09301e2dcf75f6fd", "THERM_4", 2, 3588.5827, 1735.4331, 3604.3307, 1751.1811, 4.3307], ["47abd3f869a55f4d", "THERM_4", 2, 3604.3307, 1751.1811, 3604.3307, 1757.4803, 7.874], ["1b263547317c8850", "THERM_4", 2, 3604.3307, 1757.4803, 3610.6299, 1763.7795, 7.874], ["e7bfd8bdc0369f2b", "THERM_4", 1, 3610.6299, 1763.7795, 3732.9528, 1763.7795, 7.874], ["1cd8b81d1dd1b09e", "THERM_4", 1, 3732.9528, 1763.7795, 3744.7638, 1775.5906, 7.874], ["50efe9f6953a10e5", "THERM_4", 2, 3744.7638, 1775.5906, 3744.7638, 1787.4016000000001, 7.874], ["a0cd44a7dfe07955", "THERM_4", 2, 3744.7717000000002, 1791.3386, 3721.8071, 1791.3386, 7.874], ["a235eecc3ff56bc5", "THERM_4", 2, 3742.126, 1789.3701, 3721.8071, 1791.3386, 7.874], ["572b25a37f1d4469", "THERM_5", 2, 6403.5433, 1714.9605999999999, 6403.5433, 1735.4331, 4.3307], ["48cae0014edeb354", "THERM_5", 2, 6403.5433, 1735.4331, 6419.2914, 1751.1811, 4.3307], ["8f3b96d9e65c1e65", "THERM_5", 2, 6419.2914, 1751.1811, 6419.2914, 1757.4803, 7.874], ["63afcc997541e6ef", "THERM_5", 2, 6419.2914, 1757.4803, 6425.5906, 1763.7795, 7.874], ["9cbb76b17c694814", "THERM_5", 1, 6425.5906, 1763.7795, 6547.9133999999995, 1763.7795, 7.874], ["2db741c88c3b5af4", "THERM_5", 1, 6547.9133999999995, 1763.7795, 6559.7245, 1775.5906, 7.874], ["6110d45e8ce36df2", "THERM_5", 2, 6559.7245, 1775.5906, 6559.7245, 1787.4016000000001, 7.874], ["74ad46129bc72343", "THERM_5", 2, 6559.7284, 1791.3386, 6536.7678, 1791.3386, 7.874], ["590900ed265c0547", "THERM_5", 2, 6557.0867, 1789.3701, 6536.7678, 1791.3386, 7.874], ["1a6decb0cd193c23", "CC1_1", 2, 795.2756, 3580.315, 795.2756, 3557.0866, 4.3307], ["cdbfcfccdf674560", "CC1_1", 2, 795.2756, 3557.0866, 795.2756, 3507.874, 7.874], ["ad8e2d1bc7e7641b", "CC1_1", 2, 795.2717, 3503.941, 818.2322999999999, 3503.941, 7.874], ["fdd487cf53181a53", "CC1_2", 2, 3610.2362, 3580.315, 3610.2362, 3557.0866, 4.3307], ["299446fc5a72225f", "CC1_2", 2, 3610.2362, 3557.0866, 3610.2362, 3507.874, 7.874], ["561a8fa175dca4b4", "CC1_2", 2, 3610.2284, 3503.941, 3633.1929, 3503.941, 7.874], ["ed7792f776e11010", "CC1_3", 2, 6425.1969, 3580.315, 6425.1969, 3557.0866, 4.3307], ["26cde10e6c2f04ab", "CC1_3", 2, 6425.1969, 3557.0866, 6425.1969, 3507.874, 7.874], ["4341929245b209e0", "CC1_3", 2, 6425.189, 3503.941, 6448.149599999999, 3503.941, 7.874], ["25fd2450b6e583bc", "CC1_4", 2, 3643.7008000000005, 1714.9605999999999, 3643.7008000000005, 1738.189, 4.3307], ["acfa2e6ee3e4ab4f", "CC1_4", 2, 3643.7008000000005, 1738.189, 3643.7008000000005, 1787.4016000000001, 7.874], ["f47762118fa84fcf", "CC1_4", 2, 3643.7087, 1791.3386, 3620.7481, 1791.3386, 7.874], ["d854f6968d1e24b4", "CC1_4", 2, 3641.7322999999997, 1787.4016000000001, 3620.7481, 1791.3386, 7.874], ["540cf627129ede33", "CC1_5", 2, 6458.6615, 1714.9605999999999, 6458.6615, 1738.189, 4.3307], ["f6bff8d54ec9635e", "CC1_5", 2, 6458.6615, 1738.189, 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["2dfe90417eb033aa", "K4_VUP", 1, 5070.8662, 2338.5827, 5133.8583, 2401.5748, 7.874], ["41d3e1f845a401ed", "K4_VUP", 1, 5133.8583, 2401.5748, 5139.7638, 2401.5748, 7.874], ["0ed13b2cae50e622", "K4_VUP", 1, 5139.7638, 2401.5748, 5145.6693, 2407.4803, 7.874], ["6ee7b159f425a2a6", "K4_VUP", 1, 5145.6693, 2407.4803, 5145.6693, 2417.3229, 7.874], ["02baf567409bffe7", "K4_VUP", 2, 5145.6693, 2417.3229, 5144.689, 2459.7992, 7.874], ["d0db724b753cb533", "K4_VDN", 2, 2214.5709, 607.5906, 2214.5709, 630.5512, 7.874], ["a0e1be29cdd77ef3", "K4_VDN", 2, 2214.5709, 630.5512, 2219.4921, 630.2362, 7.874], ["a3bf45480f075d49", "K4_VDN", 2, 2219.4921, 630.2362, 2227.8937, 633.4055, 7.874], ["52988c748b303856", "K4_VDN", 2, 2227.8937, 633.4055, 2279.5276, 685.0394, 7.874], ["267e657a18abfc2b", "K4_VDN", 2, 2279.5276, 685.0394, 2279.5276, 787.4016, 7.874], ["ee7c88d5056f4ba3", "K4_VDN", 2, 2279.5276, 787.4016, 2299.2126, 807.0866, 7.874], ["1a0367770c33ac2c", "K4_VDN", 1, 2299.2126, 807.0866, 2755.9055, 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["234c0f64ef6b2c16", "K5_VUP", 2, 4878.9331, 636.1417, 4866.1418, 655.6929, 7.874], ["f347fc8768de8951", "K5_VUP", 2, 4866.1418, 655.6929, 4866.1418, 807.0866, 7.874], ["85fe7ea4e0433532", "K5_VUP", 2, 4866.1418, 807.0866, 4846.4567, 826.7717, 7.874], ["f4365685df387cbd", "K5_VUP", 1, 4846.4567, 826.7717, 4811.0237, 826.7717, 7.874], ["51a4307c7c68f915", "K5_VUP", 1, 4811.0237, 826.7717, 4791.3386, 846.4567, 7.874], ["8372e787ccf5e3c7", "K5_VUP", 2, 4791.3386, 846.4567, 4791.3386, 1988.189, 7.874], ["9decdfee5c3445d5", "K5_VUP", 1, 4791.3386, 1988.189, 4811.0237, 2007.8739999999998, 7.874], ["7ecd551ee756b8fb", "K5_VUP", 1, 4811.0237, 2007.8739999999998, 4838.5827, 2007.8739999999998, 7.874], ["51964f22cfaeaeeb", "K5_VUP", 1, 4838.5827, 2007.8739999999998, 4944.8819, 2114.1732, 7.874], ["faacda4f34f6dd86", "K5_VUP", 2, 4944.8819, 2114.1732, 4944.8819, 2338.5827, 7.874], ["8614663a4ecb7cd8", "K5_VUP", 1, 4944.8819, 2338.5827, 4944.8819, 2417.3229, 7.874], ["4557f37227a7737a", "K5_VUP", 2, 4944.8819, 2417.3229, 4944.689, 2510.4095, 7.874], ["f4e4f771b7a962c2", "K5_VDN", 2, 5029.5315, 607.5906, 5029.5315, 630.5512, 7.874], ["53df709bedffb33d", "K5_VDN", 2, 4994.689, 2510.4095, 4994.689, 2459.7992, 7.874], ["0318ec9628670e8f", "K5_VDN", 2, 5029.5315, 630.5512, 5022.6418, 630.2362, 7.874], ["c14c24eb8dd22314", "K5_VDN", 2, 5022.6418, 630.2362, 5010.8701, 634.7992, 7.874], ["11700e3c93062a95", "K5_VDN", 2, 5010.8701, 634.7992, 5003.937, 641.7323, 7.874], ["550a42f7b77bb13e", "K5_VDN", 2, 5003.937, 641.7323, 5003.937, 826.7717, 7.874], ["a38db5c072c24bcc", "K5_VDN", 1, 5003.937, 826.7717, 4996.063, 834.6457, 7.874], ["6bf5295130025561", "K5_VDN", 1, 4996.063, 834.6457, 4996.063, 1082.6772, 7.874], ["876c8ef0857e51fd", "K5_VDN", 2, 4996.063, 1082.6772, 4996.063, 2035.4331, 7.874], ["973aaba1ccb5c1a0", "K5_VDN", 1, 4996.063, 2035.4331, 4996.063, 2114.1732, 7.874], ["0cab819fa38754fb", "K5_VDN", 2, 4996.063, 2114.1732, 4996.063, 2338.5827, 7.874], ["abe55bf1910249c6", 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3437.0078999999996, 1791.3386, 3437.0078999999996, 1909.4488, 19.685], ["ea076b45b7d9ecda", "VBUS4", 2, 3437.0078999999996, 1909.4488, 3456.6929, 1929, 19.685], ["1e5e028eafa43d3a", "VBUS4", 1, 3456.6929, 1929, 3525.5906, 1928.5394, 19.685], ["10eb04a9efb7cda4", "VBUS4", 1, 3435.0394, 1793.3071, 3446.8503999999994, 1799.2126000000003, 19.685], ["c79ad33cd0be0734", "VBUS4", 1, 3446.8503999999994, 1799.2126000000003, 3690.8268, 1799.2126000000003, 19.685], ["173919266d299b80", "VBUS4", 1, 3690.8268, 1799.2126000000003, 3695.8465, 1795.2756, 19.685], ["be05de96801b2d09", "VBUS4", 2, 3695.8465, 1795.2756, 3696.8150000000005, 1791.3386, 19.685], ["d567664e24a348cd", "VBUS5", 2, 5918.5, 1318.9015999999997, 5918.5, 1341.3622, 19.685], ["6d66b56ddc3ab70f", "VBUS5", 2, 6248.8189, 1673.2284, 6248.8189, 1699.9921, 19.3], ["c87fd263fabc05a9", "VBUS5", 2, 6492.7481, 1791.3386, 6511.7756, 1791.3386, 19.685], ["b9e0f5c3bbafdbf7", "VBUS5", 2, 5724.4095, 1356.2992, 5690.948900000001, 1356.2992, 19.685], ["cbfc0ee5ef9ebae2", "VBUS5", 2, 5724.4095, 1318.9015999999997, 5690.948900000001, 1318.9015999999997, 19.685], ["3ad4f97ef3c49def", "VBUS5", 2, 6340.5512, 1895.6299, 6340.5512, 1928.5394, 19.685], ["770b143cd652de09", "VBUS5", 2, 5918.5, 1341.3622, 5917.763800000001, 1374.0197, 19.685], ["613306987f6a2130", "VBUS5", 2, 5917.763800000001, 1374.0197, 5897.6378, 1393.7008, 19.685], ["3f7febb2e2b50fb5", "VBUS5", 1, 5897.6378, 1393.7008, 5711.641799999999, 1393.7008, 19.685], ["7629a36e6043eb24", "VBUS5", 2, 5711.641799999999, 1393.7008, 5691.9292, 1375, 19.685], ["6ebfa1f8b6e6b400", "VBUS5", 2, 5691.9292, 1375, 5690.948900000001, 1356.2992, 19.685], ["b9e260cf3c3d20e6", "VBUS5", 2, 5692.9133999999995, 1350.3937, 5690.948900000001, 1318.9015999999997, 19.685], ["2a2411c7daf6150e", "VBUS5", 1, 5897.6378, 1393.7008, 5925.1969, 1401.5748000000003, 19.685], ["e8a3db661fbaa4f8", "VBUS5", 1, 5925.1969, 1401.5748000000003, 6228.3465, 1401.5748000000003, 19.685], ["d5a0769449a0fa29", "VBUS5", 1, 6228.3465, 1401.5748000000003, 6248.0827, 1421.2599, 19.685], ["5a0b9e6b3e8bef27", "VBUS5", 2, 6248.0827, 1421.2599, 6248.748299999999, 1673.2302, 19.685], ["d7d22fdf89126695", "VBUS5", 2, 6248.748299999999, 1673.2302, 6248.8189, 1699.9921, 19.685], ["7e8658393c760e85", "VBUS5", 2, 6240.1575, 1700.7873999999997, 6240.1575, 1909.4488, 19.685], ["d3778d160d5ca0dd", "VBUS5", 2, 6240.1575, 1909.4488, 6259.8426, 1929.0158, 19.685], ["dd16863b102b399d", "VBUS5", 1, 6259.8426, 1929.0158, 6340.5512, 1928.5394, 19.685], ["54b6d277ca1bd499", "VBUS5", 1, 6344.4882, 1917.3228, 6492.126, 1917.3228, 19.685], ["bef131431d6c6f3b", "VBUS5", 1, 6492.126, 1917.3228, 6511.8071, 1897.6378, 19.685], ["74408068a976123a", "VBUS5", 2, 6511.8071, 1897.6378, 6511.7756, 1791.3386, 19.685], ["4a68fe02e361e4c3", "POGO1_PWR", 2, 2539.3701, 4842.5197, 2539.3701, 4814.9607, 7.874], ["89e1ba4a2f68fae2", "POGO1_PWR", 2, 2539.3701, 4814.9607, 2559.0512, 4795.5591, 7.874], ["1a7dcf0fd2fbfb55", "POGO1_PWR", 1, 2559.0512, 4795.5591, 2648.8189, 4796.8504, 7.874], ["321e3714569c9a25", "POGO1_VUP", 2, 2401.5709, 4842.5197, 2401.5748, 4767.7166, 7.874], ["7ff0e7b881aa2e44", "POGO1_VUP", 2, 2401.5748, 4767.7166, 2421.2599, 4748.1103, 7.874], ["d7c67c46146ba383", "POGO1_VUP", 1, 2421.2599, 4748.1103, 2700, 4749.2087, 7.874], ["abcc26294a580d94", "POGO1_VDN", 2, 2263.7795, 4842.5197, 2291.3386, 4846.4567, 7.874], ["3a736abf065ea0e8", "POGO1_VDN", 1, 2291.3386, 4846.4567, 2688.9764000000005, 4846.4567, 7.874], ["9fa31897eebb12d9", "POGO1_VDN", 1, 2688.9764000000005, 4846.4567, 2697.2402, 4852.7599, 7.874], ["a5527e6c5e09ab9d", "POGO2_PWR", 2, 5354.3307, 4842.5197, 5354.3307, 4814.9607, 7.874], ["870444097dd85cf4", "POGO2_PWR", 2, 5354.3307, 4814.9607, 5374.0118, 4795.5591, 7.874], ["0026f29e96aef6e7", "POGO2_PWR", 1, 5374.0118, 4795.5591, 5463.7796, 4796.8504, 7.874], ["c12a4d46393ee5af", "POGO2_VUP", 2, 5216.5394, 4842.5197, 5216.5355, 4767.7166, 7.874], ["7bc24e31e83d32e9", "POGO2_VUP", 2, 5216.5355, 4767.7166, 5236.2205, 4748.1103, 7.874], ["0f2274eb51b718a5", "POGO2_VUP", 1, 5236.2205, 4748.1103, 5514.9607, 4749.2087, 7.874], ["996d9eb65b123ad2", "POGO2_VDN", 2, 5078.7402, 4842.5197, 5106.2992, 4846.4567, 7.874], ["909e835889617d94", "POGO2_VDN", 1, 5106.2992, 4846.4567, 5503.937, 4846.4567, 7.874], ["4ca04f638d3925d5", "POGO2_VDN", 1, 5503.937, 4846.4567, 5512.2008, 4852.7599, 7.874], ["10945735aef53372", "POGO3_PWR", 2, 8169.2914, 4842.5197, 8169.2914, 4814.9607, 7.874], ["257546e8cfd7aa39", "POGO3_PWR", 2, 8169.2914, 4814.9607, 8188.9725, 4795.5591, 7.874], ["debb077e3e7f3aa4", "POGO3_PWR", 1, 8188.9725, 4795.5591, 8278.7402, 4796.8504, 7.874], ["ec83bdd36c5c806e", "POGO3_VUP", 2, 8031.500100000001, 4842.5197, 8031.4961, 4767.7166, 7.874], ["15598d0a7199fe99", "POGO3_VUP", 2, 8031.4961, 4767.7166, 8051.1812, 4748.1103, 7.874], ["8d59990f6fa7cb24", "POGO3_VUP", 1, 8051.1812, 4748.1103, 8329.9213, 4749.2087, 7.874], ["5345c430564aab09", "POGO3_VDN", 2, 7893.700799999999, 4842.5197, 7921.2599, 4846.4567, 7.874], ["6b923496b609274b", "POGO3_VDN", 1, 7921.2599, 4846.4567, 8318.8977, 4846.4567, 7.874], ["e62f2931a7f3d6c9", "POGO3_VDN", 1, 8318.8977, 4846.4567, 8327.1693, 4852.7599, 7.874], ["da0fa5ea72459b82", "POGO4_PWR", 2, 1899.6102, 452.7598, 1900.7559, 480.3307, 7.874], ["b769af46ccd291fd", "POGO4_PWR", 2, 1900.7559, 480.3307, 1881.8898, 499.7244, 7.874], ["24a04a861d3933f1", "POGO4_PWR", 1, 1881.8898, 499.7244, 1790.1614, 498.42910000000006, 7.874], ["126668dbf1ca6f2c", "POGO4_VUP", 2, 2037.4016000000001, 452.7598, 2035.8425, 527.563, 7.874], ["1f6109e6328b5bb0", "POGO4_VUP", 2, 2035.8425, 527.563, 2015.748, 547.1654, 7.874], ["8c5ad23101b51f64", "POGO4_VUP", 1, 2015.748, 547.1654, 1738.9803000000002, 546.0591, 7.874], ["65190043e9f14373", "POGO4_VDN", 2, 2175.2008, 452.7598, 2149.6063, 452.7559, 7.874], ["b62c288dfa3b4344", "POGO4_VDN", 1, 2149.6063, 452.7559, 1751.9685, 452.7559, 7.874], ["dc87b2e007099fde", "POGO4_VDN", 1, 1751.9685, 452.7559, 1741.7284, 442.5197, 7.874], ["793be9cdfffd16ea", "POGO5_PWR", 2, 4714.5709, 452.7598, 4715.7166, 480.3307, 7.874], ["2acef6d82c8da89f", "POGO5_PWR", 2, 4715.7166, 480.3307, 4696.8504, 499.7244, 7.874], ["f3c83ef351ff71b5", "POGO5_PWR", 1, 4696.8504, 499.7244, 4605.1181, 498.42910000000006, 7.874], ["fe9d7864632986f8", "POGO5_VUP", 2, 4852.3583, 452.7598, 4850.8032, 527.563, 7.874], ["c6e0ca30a010c772", "POGO5_VUP", 2, 4850.8032, 527.563, 4830.7087, 547.1654, 7.874], ["53ac6cba6268c3c4", "POGO5_VUP", 1, 4830.7087, 547.1654, 4553.941, 546.0591, 7.874], ["23ebc3a0e4013ff5", "POGO5_VDN", 2, 4990.1615, 452.7598, 4964.567, 452.7559, 7.874], ["fe8bc60d260349ea", "POGO5_VDN", 1, 4964.567, 452.7559, 4566.9292, 452.7559, 7.874], ["dacfa3a730baa609", "POGO5_VDN", 1, 4566.9292, 452.7559, 4556.689, 442.5197, 7.874], ["a9714f140ffa0ee9", "SDA", 2, 2176.9606, 2287.2008, 2126.748, 2287.2008, 7.874], ["ae4410be0096724a", "SDA", 1, 2490.941, 2707.4803, 2440.9449, 2657.4803, 7.874], ["8ec1ecebc074bb41", "SDA", 1, 2440.9449, 2657.4803, 2153.5433, 2657.4803, 7.874], ["d5a24a9f3818d16b", "SDA", 1, 2153.5433, 2657.4803, 2141.7323, 2645.6693, 7.874], ["3b6e7ab4c56cf303", "SDA", 1, 2141.7323, 2645.6693, 2141.7323, 2562.9921000000004, 7.874], ["a3c567236ece2bc4", "SDA", 1, 2141.7323, 2562.9921000000004, 2106.2992, 2527.5591, 7.874], ["998d3337da4997b0", "SDA", 1, 2106.2992, 2527.5591, 2106.2992, 2500, 7.874], ["42f5ea4d081a7ad1", "SDA", 2, 2106.2992, 2500, 2106.2992, 2307.0866, 7.874], ["fb0bf48b6e679fed", "SDA", 2, 2106.2992, 2307.0866, 2126.748, 2287.2008, 7.874], ["23e8fca212282c9d", "SCL", 2, 2176.9606, 2337.2008, 2126.748, 2337.2008, 7.874], ["35ab389ce897cb3a", "SCL", 2, 2590.941, 2707.4803, 2541.3386, 2657.4803, 7.874], ["2aad33159eccc475", "SCL", 2, 2541.3386, 2657.4803, 2045.2756, 2657.4803, 7.874], ["f30ab09108d1b782", "SCL", 2, 2045.2756, 2657.4803, 2041.3386, 2653.5433000000003, 7.874], ["f9fd23eeebb07c98", "SCL", 1, 2041.3386, 2653.5433000000003, 2041.3386, 2568.8977, 7.874], ["462257e6bc99b7aa", "SCL", 1, 2041.3386, 2568.8977, 2072.8347, 2537.4016, 7.874], ["369920f6ece3d33a", "SCL", 1, 2072.8347, 2537.4016, 2072.8347, 2501.9685, 7.874], ["f8dd7b72eb6ac82e", "SCL", 2, 2072.8347, 2501.9685, 2072.8347, 2356.2992, 7.874], ["102d5c865a0b673c", "SCL", 1, 2072.8347, 2356.2992, 2092.5197, 2336.6142, 7.874], ["bdec022d5e2fcffe", "SCL", 1, 2092.5197, 2336.6142, 2131.8898, 2336.6142, 7.874], ["a306c1cfa2f1c432", "SCL", 2, 2131.8898, 2336.6142, 2126.748, 2337.2008, 7.874], ["d0346a2c5ab93e02", "KEY_RCLK", 2, 7725.8111, 2721.8503999999994, 7776.4213, 2721.8503999999994, 7.874], ["a2843f92f9555eb2", "KEY_RCLK", 2, 4611.6103, 2459.7992, 4611.6103, 2510.4095, 7.874], ["86e560c469405641", "KEY_RCLK", 2, 4611.6103, 2510.4095, 4610.4213, 2586.6142, 7.874], ["6ef215ff05c970c6", "KEY_RCLK", 2, 4610.4213, 2586.6142, 4629.9174, 2605.8819, 7.874], ["fbfd81234b19ed3a", "KEY_RCLK", 1, 4629.9174, 2605.8819, 4795.2756, 2602.3622, 7.874], ["b1c82545f9b094fc", "KEY_RCLK", 1, 4795.2756, 2602.3622, 4976.3819, 2605.9134, 7.874], ["5f80c21d3f0b796d", "KEY_RCLK", 1, 4976.3819, 2605.9134, 4995.9055, 2625.9843, 7.874], ["7c342e23700385e0", "KEY_RCLK", 2, 4995.9055, 2625.9843, 4994.689, 2725.8109999999997, 7.874], ["db8b399115b1d66b", "KEY_RCLK", 2, 4994.689, 2725.8109999999997, 4994.689, 2776.4213, 7.874], ["1d93b1d4eafb12bc", "KEY_RCLK", 2, 4998.0315, 2777.5590999999995, 4998.0315, 2789.3701, 7.874], ["5b871287ea6d8f0f", "KEY_RCLK", 1, 4998.0315, 2789.3701, 5009.8426, 2801.1811, 7.874], ["b97160036e547e9f", "KEY_RCLK", 1, 5009.8426, 2801.1811, 5651.5748, 2801.1811, 7.874], ["20e50d3313e38117", "KEY_RCLK", 2, 5651.5748, 2801.1811, 5671.0945, 2781.4961, 7.874], ["510a0c2f1e943e71", "KEY_RCLK", 2, 5671.0945, 2781.4961, 5670.468499999999, 2707.4803, 7.874], ["e3491ceb9fc9a9b6", "KEY_RCLK", 1, 5651.5748, 2801.1811, 5681.1024, 2803.1496000000006, 7.874], ["961e07cf176387f1", "KEY_RCLK", 1, 5681.1024, 2803.1496000000006, 7311.0237, 2803.1496000000006, 7.874], ["c39246ec5a0e4c6e", "KEY_RCLK", 2, 7311.0237, 2803.1496000000006, 7330.7087, 2783.4646, 7.874], ["e52bf2cf6aa125e2", "KEY_RCLK", 2, 7330.7087, 2783.4646, 7330.7087, 2720.4725, 7.874], ["e83b3b0a50cd2848", "KEY_RCLK", 1, 7330.7087, 2720.4725, 7350.3937, 2700.7874, 7.874], ["24b7ebf5a824a09c", "KEY_RCLK", 1, 7350.3937, 2700.7874, 7759.8426, 2700.7874, 7.874], ["c131040d3114ff51", "KEY_RCLK", 1, 7759.8426, 2700.7874, 7767.7166, 2708.6614, 7.874], ["fb6f213d20229a22", "KEY_RCLK", 2, 7767.7166, 2708.6614, 7776.4213, 2721.8503999999994, 7.874], ["b47a8204074c21f6", "PRTDIS7", 2, 3986.2205, 2446.1693, 4008.6811, 2446.1693, 7.874]]} \ No newline at end of file diff --git a/.claude/_pcb2_sig_routes.json b/.claude/_pcb2_sig_routes.json index c49638f..5b10716 100644 --- a/.claude/_pcb2_sig_routes.json +++ b/.claude/_pcb2_sig_routes.json @@ -1 +1 @@ -{"GND": [[23.79, 91.6, 2, 0.11], [23.79, 92.19, 2, 0.3], [23.79, 92.425, 2, 0.3], [23.555, 92.66, 2, 0.3], [19.94, 92.66, 2, 0.3]], "GND#2": [[22.74, 91.6, 2, 0.11], [22.74, 92.19, 2, 0.3], [22.74, 92.66, 2, 0.3]], "GND#3": [[22.04, 91.6, 2, 0.11], [22.04, 92.19, 2, 0.3], [22.04, 92.66, 2, 0.3]], "GND#4": [[21.34, 91.6, 2, 0.11], [21.34, 92.19, 2, 0.3], [21.34, 92.66, 2, 0.3]], "GND#5": [[19.94, 91.6, 2, 0.11], [19.94, 92.19, 2, 0.3], [19.94, 92.66, 2, 0.3]], "GND#6": [[23.79, 92.66, 2, 0.3], [23.79, 92.66, 1, 0.3], [23.79, 92.66, 1, 0.3]], "GND#7": [[22.74, 92.66, 2, 0.3], [22.74, 92.66, 1, 0.3], [22.74, 92.66, 1, 0.3]], "GND#8": [[21.34, 92.66, 2, 0.3], [21.34, 92.66, 1, 0.3], [21.34, 92.66, 1, 0.3]], "GND#9": [[19.94, 92.66, 2, 0.3], [19.94, 92.66, 1, 0.3], [19.94, 92.66, 1, 0.3]], "GND#10": [[23.79, 93.72, 2, 0.11], [23.79, 94.31, 2, 0.3], [23.79, 94.435, 2, 0.3], [23.665, 94.56, 2, 0.3], [15.74, 94.56, 2, 0.3]], "GND#11": [[20.64, 93.72, 2, 0.11], [20.64, 94.31, 2, 0.3], [20.64, 94.56, 2, 0.3]], "GND#12": [[19.94, 93.72, 2, 0.11], [19.94, 94.31, 2, 0.3], [19.94, 94.56, 2, 0.3]], "GND#13": [[18.89, 93.72, 2, 0.11], [18.89, 94.31, 2, 0.3], [18.89, 94.56, 2, 0.3]], "GND#14": [[17.49, 93.72, 2, 0.11], [17.49, 94.31, 2, 0.3], [17.49, 94.56, 2, 0.3]], "GND#15": [[16.79, 93.72, 2, 0.11], [16.79, 94.31, 2, 0.3], [16.79, 94.56, 2, 0.3]], "GND#16": [[15.74, 93.72, 2, 0.11], [15.74, 94.31, 2, 0.3], [15.74, 94.56, 2, 0.3]], "GND#17": [[23.79, 94.56, 2, 0.3], [23.79, 94.56, 1, 0.3], [23.79, 94.56, 1, 0.3]], "GND#18": [[19.94, 94.56, 2, 0.3], [19.94, 94.56, 1, 0.3], [19.94, 94.56, 1, 0.3]], "GND#19": [[18.89, 94.56, 2, 0.3], [18.89, 94.56, 1, 0.3], [18.89, 94.56, 1, 0.3]], "GND#20": [[17.49, 94.56, 2, 0.3], [17.49, 94.56, 1, 0.3], [17.49, 94.56, 1, 0.3]], "GND#21": [[15.74, 94.56, 2, 0.3], [15.74, 94.56, 1, 0.3], [15.74, 94.56, 1, 0.3]], "GND#22": [[13.56, 92.66, 2, 0.3], [12.49, 92.66, 2, 0.3], [12.49, 92.66, 1, 0.3], [12.49, 92.66, 1, 0.3]], "GND#23": [[95.29, 91.6, 2, 0.11], [95.29, 92.19, 2, 0.3], [95.29, 92.425, 2, 0.3], [95.055, 92.66, 2, 0.3], [91.44, 92.66, 2, 0.3]], "GND#24": [[94.24, 91.6, 2, 0.11], [94.24, 92.19, 2, 0.3], [94.24, 92.66, 2, 0.3]], "GND#25": [[93.54, 91.6, 2, 0.11], [93.54, 92.19, 2, 0.3], [93.54, 92.66, 2, 0.3]], "GND#26": [[92.84, 91.6, 2, 0.11], [92.84, 92.19, 2, 0.3], [92.84, 92.66, 2, 0.3]], "GND#27": [[91.44, 91.6, 2, 0.11], [91.44, 92.19, 2, 0.3], [91.44, 92.66, 2, 0.3]], "GND#28": [[95.29, 92.66, 2, 0.3], [95.29, 92.66, 1, 0.3], [95.29, 92.66, 1, 0.3]], "GND#29": [[94.24, 92.66, 2, 0.3], [94.24, 92.66, 1, 0.3], [94.24, 92.66, 1, 0.3]], "GND#30": [[92.84, 92.66, 2, 0.3], [92.84, 92.66, 1, 0.3], [92.84, 92.66, 1, 0.3]], "GND#31": [[91.44, 92.66, 2, 0.3], [91.44, 92.66, 1, 0.3], [91.44, 92.66, 1, 0.3]], "GND#32": [[95.29, 93.72, 2, 0.11], [95.29, 94.31, 2, 0.3], [95.29, 94.435, 2, 0.3], [95.165, 94.56, 2, 0.3], [87.24, 94.56, 2, 0.3]], "GND#33": [[92.14, 93.72, 2, 0.11], [92.14, 94.31, 2, 0.3], [92.14, 94.56, 2, 0.3]], "GND#34": [[91.44, 93.72, 2, 0.11], [91.44, 94.31, 2, 0.3], [91.44, 94.56, 2, 0.3]], "GND#35": [[90.39, 93.72, 2, 0.11], [90.39, 94.31, 2, 0.3], [90.39, 94.56, 2, 0.3]], "GND#36": [[88.99, 93.72, 2, 0.11], [88.99, 94.31, 2, 0.3], [88.99, 94.56, 2, 0.3]], "GND#37": [[88.29, 93.72, 2, 0.11], [88.29, 94.31, 2, 0.3], [88.29, 94.56, 2, 0.3]], "GND#38": [[87.24, 93.72, 2, 0.11], [87.24, 94.31, 2, 0.3], [87.24, 94.56, 2, 0.3]], "GND#39": [[95.29, 94.56, 2, 0.3], [95.29, 94.56, 1, 0.3], [95.29, 94.56, 1, 0.3]], "GND#40": [[91.44, 94.56, 2, 0.3], [91.44, 94.56, 1, 0.3], [91.44, 94.56, 1, 0.3]], "GND#41": [[90.39, 94.56, 2, 0.3], [90.39, 94.56, 1, 0.3], [90.39, 94.56, 1, 0.3]], "GND#42": [[88.99, 94.56, 2, 0.3], [88.99, 94.56, 1, 0.3], [88.99, 94.56, 1, 0.3]], "GND#43": [[87.24, 94.56, 2, 0.3], [87.24, 94.56, 1, 0.3], [87.24, 94.56, 1, 0.3]], "GND#44": [[85.06, 92.66, 2, 0.3], [83.99, 92.66, 2, 0.3], [83.99, 92.66, 1, 0.3], [83.99, 92.66, 1, 0.3]], "GND#45": [[166.79, 91.6, 2, 0.11], [166.79, 92.19, 2, 0.3], [166.79, 92.425, 2, 0.3], [166.555, 92.66, 2, 0.3], [162.94, 92.66, 2, 0.3]], "GND#46": [[165.74, 91.6, 2, 0.11], [165.74, 92.19, 2, 0.3], [165.74, 92.66, 2, 0.3]], "GND#47": [[165.04, 91.6, 2, 0.11], [165.04, 92.19, 2, 0.3], [165.04, 92.66, 2, 0.3]], "GND#48": [[164.34, 91.6, 2, 0.11], [164.34, 92.19, 2, 0.3], [164.34, 92.66, 2, 0.3]], "GND#49": [[162.94, 91.6, 2, 0.11], [162.94, 92.19, 2, 0.3], [162.94, 92.66, 2, 0.3]], "GND#50": [[166.79, 92.66, 2, 0.3], [166.79, 92.66, 1, 0.3], [166.79, 92.66, 1, 0.3]], "GND#51": [[165.74, 92.66, 2, 0.3], [165.74, 92.66, 1, 0.3], [165.74, 92.66, 1, 0.3]], "GND#52": [[164.34, 92.66, 2, 0.3], [164.34, 92.66, 1, 0.3], [164.34, 92.66, 1, 0.3]], "GND#53": [[162.94, 92.66, 2, 0.3], [162.94, 92.66, 1, 0.3], [162.94, 92.66, 1, 0.3]], "GND#54": [[166.79, 93.72, 2, 0.11], [166.79, 94.31, 2, 0.3], [166.79, 94.435, 2, 0.3], [166.665, 94.56, 2, 0.3], [158.74, 94.56, 2, 0.3]], "GND#55": [[163.64, 93.72, 2, 0.11], [163.64, 94.31, 2, 0.3], [163.64, 94.56, 2, 0.3]], "GND#56": [[162.94, 93.72, 2, 0.11], [162.94, 94.31, 2, 0.3], [162.94, 94.56, 2, 0.3]], "GND#57": [[161.89, 93.72, 2, 0.11], [161.89, 94.31, 2, 0.3], [161.89, 94.56, 2, 0.3]], "GND#58": [[160.49, 93.72, 2, 0.11], [160.49, 94.31, 2, 0.3], [160.49, 94.56, 2, 0.3]], "GND#59": [[159.79, 93.72, 2, 0.11], [159.79, 94.31, 2, 0.3], [159.79, 94.56, 2, 0.3]], "GND#60": [[158.74, 93.72, 2, 0.11], [158.74, 94.31, 2, 0.3], [158.74, 94.56, 2, 0.3]], "GND#61": [[166.79, 94.56, 2, 0.3], [166.79, 94.56, 1, 0.3], [166.79, 94.56, 1, 0.3]], "GND#62": [[162.94, 94.56, 2, 0.3], [162.94, 94.56, 1, 0.3], [162.94, 94.56, 1, 0.3]], "GND#63": [[161.89, 94.56, 2, 0.3], [161.89, 94.56, 1, 0.3], [161.89, 94.56, 1, 0.3]], "GND#64": [[160.49, 94.56, 2, 0.3], [160.49, 94.56, 1, 0.3], [160.49, 94.56, 1, 0.3]], "GND#65": [[158.74, 94.56, 2, 0.3], [158.74, 94.56, 1, 0.3], [158.74, 94.56, 1, 0.3]], "GND#66": [[156.56, 92.66, 2, 0.3], [155.49, 92.66, 2, 0.3], [155.49, 92.66, 1, 0.3], [155.49, 92.66, 1, 0.3]], "GND#67": [[89.05, 43.56, 2, 0.11], [89.05, 42.97, 2, 0.3], [89.05, 42.735, 2, 0.3], [89.285, 42.5, 2, 0.3], [92.9, 42.5, 2, 0.3]], "GND#68": [[90.1, 43.56, 2, 0.11], [90.1, 42.97, 2, 0.3], [90.1, 42.5, 2, 0.3]], "GND#69": [[90.8, 43.56, 2, 0.11], [90.8, 42.97, 2, 0.3], [90.8, 42.5, 2, 0.3]], "GND#70": [[91.5, 43.56, 2, 0.11], [91.5, 42.97, 2, 0.3], [91.5, 42.5, 2, 0.3]], "GND#71": [[92.9, 43.56, 2, 0.11], [92.9, 42.97, 2, 0.3], [92.9, 42.5, 2, 0.3]], "GND#72": [[89.05, 42.5, 2, 0.3], [89.05, 42.5, 1, 0.3], [89.05, 42.5, 1, 0.3]], "GND#73": [[90.1, 42.5, 2, 0.3], [90.1, 42.5, 1, 0.3], [90.1, 42.5, 1, 0.3]], "GND#74": [[91.5, 42.5, 2, 0.3], [91.5, 42.5, 1, 0.3], [91.5, 42.5, 1, 0.3]], "GND#75": [[92.9, 42.5, 2, 0.3], [92.9, 42.5, 1, 0.3], [92.9, 42.5, 1, 0.3]], "GND#76": [[89.05, 41.44, 2, 0.11], [89.05, 40.85, 2, 0.3], [89.05, 40.725, 2, 0.3], [89.175, 40.6, 2, 0.3], [97.1, 40.6, 2, 0.3]], "GND#77": [[92.2, 41.44, 2, 0.11], [92.2, 40.85, 2, 0.3], [92.2, 40.6, 2, 0.3]], "GND#78": [[92.9, 41.44, 2, 0.11], [92.9, 40.85, 2, 0.3], [92.9, 40.6, 2, 0.3]], "GND#79": [[93.95, 41.44, 2, 0.11], [93.95, 40.85, 2, 0.3], [93.95, 40.6, 2, 0.3]], "GND#80": [[95.35, 41.44, 2, 0.11], [95.35, 40.85, 2, 0.3], [95.35, 40.6, 2, 0.3]], "GND#81": [[96.05, 41.44, 2, 0.11], [96.05, 40.85, 2, 0.3], [96.05, 40.6, 2, 0.3]], "GND#82": [[97.1, 41.44, 2, 0.11], [97.1, 40.85, 2, 0.3], [97.1, 40.6, 2, 0.3]], "GND#83": [[89.05, 40.6, 2, 0.3], [89.05, 40.6, 1, 0.3], [89.05, 40.6, 1, 0.3]], "GND#84": [[92.9, 40.6, 2, 0.3], [92.9, 40.6, 1, 0.3], [92.9, 40.6, 1, 0.3]], "GND#85": [[93.95, 40.6, 2, 0.3], [93.95, 40.6, 1, 0.3], [93.95, 40.6, 1, 0.3]], "GND#86": [[95.35, 40.6, 2, 0.3], [95.35, 40.6, 1, 0.3], [95.35, 40.6, 1, 0.3]], "GND#87": [[97.1, 40.6, 2, 0.3], [97.1, 40.6, 1, 0.3], [97.1, 40.6, 1, 0.3]], "GND#88": [[99.28, 42.5, 2, 0.3], [100.35, 42.5, 2, 0.3], [100.35, 42.5, 1, 0.3], [100.35, 42.5, 1, 0.3]], "GND#89": [[160.55, 43.56, 2, 0.11], [160.55, 42.97, 2, 0.3], [160.55, 42.735, 2, 0.3], [160.785, 42.5, 2, 0.3], [164.4, 42.5, 2, 0.3]], "GND#90": [[161.6, 43.56, 2, 0.11], [161.6, 42.97, 2, 0.3], [161.6, 42.5, 2, 0.3]], "GND#91": [[162.3, 43.56, 2, 0.11], [162.3, 42.97, 2, 0.3], [162.3, 42.5, 2, 0.3]], "GND#92": [[163.0, 43.56, 2, 0.11], [163.0, 42.97, 2, 0.3], [163.0, 42.5, 2, 0.3]], "GND#93": [[164.4, 43.56, 2, 0.11], [164.4, 42.97, 2, 0.3], [164.4, 42.5, 2, 0.3]], "GND#94": [[160.55, 42.5, 2, 0.3], [160.55, 42.5, 1, 0.3], [160.55, 42.5, 1, 0.3]], "GND#95": [[161.6, 42.5, 2, 0.3], [161.6, 42.5, 1, 0.3], [161.6, 42.5, 1, 0.3]], "GND#96": [[163.0, 42.5, 2, 0.3], [163.0, 42.5, 1, 0.3], [163.0, 42.5, 1, 0.3]], "GND#97": [[164.4, 42.5, 2, 0.3], [164.4, 42.5, 1, 0.3], [164.4, 42.5, 1, 0.3]], "GND#98": [[160.55, 41.44, 2, 0.11], [160.55, 40.85, 2, 0.3], [160.55, 40.725, 2, 0.3], [160.675, 40.6, 2, 0.3], [168.6, 40.6, 2, 0.3]], "GND#99": [[163.7, 41.44, 2, 0.11], [163.7, 40.85, 2, 0.3], [163.7, 40.6, 2, 0.3]], "GND#100": [[164.4, 41.44, 2, 0.11], [164.4, 40.85, 2, 0.3], [164.4, 40.6, 2, 0.3]], "GND#101": [[165.45, 41.44, 2, 0.11], [165.45, 40.85, 2, 0.3], [165.45, 40.6, 2, 0.3]], "GND#102": [[166.85, 41.44, 2, 0.11], [166.85, 40.85, 2, 0.3], [166.85, 40.6, 2, 0.3]], "GND#103": [[167.55, 41.44, 2, 0.11], [167.55, 40.85, 2, 0.3], [167.55, 40.6, 2, 0.3]], "GND#104": [[168.6, 41.44, 2, 0.11], [168.6, 40.85, 2, 0.3], [168.6, 40.6, 2, 0.3]], "GND#105": [[160.55, 40.6, 2, 0.3], [160.55, 40.6, 1, 0.3], [160.55, 40.6, 1, 0.3]], "GND#106": [[164.4, 40.6, 2, 0.3], [164.4, 40.6, 1, 0.3], [164.4, 40.6, 1, 0.3]], "GND#107": [[165.45, 40.6, 2, 0.3], [165.45, 40.6, 1, 0.3], [165.45, 40.6, 1, 0.3]], "GND#108": [[166.85, 40.6, 2, 0.3], [166.85, 40.6, 1, 0.3], [166.85, 40.6, 1, 0.3]], "GND#109": [[168.6, 40.6, 2, 0.3], [168.6, 40.6, 1, 0.3], [168.6, 40.6, 1, 0.3]], "GND#110": [[170.78, 42.5, 2, 0.3], [171.85, 42.5, 2, 0.3], [171.85, 42.5, 1, 0.3], [171.85, 42.5, 1, 0.3]], "THERM_1": [[21.69, 91.6, 2, 0.11], [21.69, 91.08, 2, 0.11], [21.29, 90.68, 2, 0.2], [21.29, 90.36, 2, 0.2], [21.29, 90.36, 1, 0.2], [17.723, 90.36, 1, 0.2], [17.723, 90.36, 2, 0.2], [17.723, 89.76, 2, 0.2]], "THERM_1#2": [[17.7228, 89.66, 2, 0.2], [18.3061, 89.66, 2, 0.2]], "THERM_1#3": [[17.8, 89.7, 2, 0.2], [18.3061, 89.66, 2, 0.2]], "THERM_2": [[93.19, 91.6, 2, 0.11], [93.19, 91.08, 2, 0.11], [92.79, 90.68, 2, 0.2], [92.79, 90.36, 2, 0.2], [92.79, 90.36, 1, 0.2], [89.223, 90.36, 1, 0.2], [89.223, 90.36, 2, 0.2], [89.223, 89.76, 2, 0.2]], "THERM_2#2": [[89.2228, 89.66, 2, 0.2], [89.806, 89.66, 2, 0.2]], "THERM_2#3": [[89.3, 89.7, 2, 0.2], [89.806, 89.66, 2, 0.2]], "THERM_3": [[164.69, 91.6, 2, 0.11], [164.69, 91.08, 2, 0.11], [164.29, 90.68, 2, 0.2], [164.29, 90.36, 2, 0.2], [164.29, 90.36, 1, 0.2], [160.723, 90.36, 1, 0.2], [160.723, 90.36, 2, 0.2], [160.723, 89.76, 2, 0.2]], "THERM_3#2": [[160.7228, 89.66, 2, 0.2], [161.306, 89.66, 2, 0.2]], "THERM_3#3": [[160.8, 89.7, 2, 0.2], [161.306, 89.66, 2, 0.2]], "THERM_4": [[91.15, 43.56, 2, 0.11], [91.15, 44.08, 2, 0.11], [91.55, 44.48, 2, 0.2], [91.55, 44.8, 2, 0.2], [91.55, 44.8, 1, 0.2], [95.117, 44.8, 1, 0.2], [95.117, 44.8, 2, 0.2], [95.117, 45.4, 2, 0.2]], "THERM_4#2": [[95.1172, 45.5, 2, 0.2], [94.5339, 45.5, 2, 0.2]], "THERM_4#3": [[95.05, 45.45, 2, 0.2], [94.5339, 45.5, 2, 0.2]], "THERM_5": [[162.65, 43.56, 2, 0.11], [162.65, 44.08, 2, 0.11], [163.05, 44.48, 2, 0.2], [163.05, 44.8, 2, 0.2], [163.05, 44.8, 1, 0.2], [166.617, 44.8, 1, 0.2], [166.617, 44.8, 2, 0.2], [166.617, 45.4, 2, 0.2]], "THERM_5#2": [[166.6171, 45.5, 2, 0.2], [166.0339, 45.5, 2, 0.2]], "THERM_5#3": [[166.55, 45.45, 2, 0.2], [166.0339, 45.5, 2, 0.2]], "CC1_1": [[20.29, 91.6, 2, 0.11], [20.29, 91.01, 2, 0.2], [20.29, 89.76, 2, 0.2]], "CC1_1#2": [[20.2898, 89.66, 2, 0.2], [20.873, 89.66, 2, 0.2]], "CC1_1#3": [[20.3, 89.7, 2, 0.2], [20.873, 89.66, 2, 0.2]], "CC1_2": [[91.79, 91.6, 2, 0.11], [91.79, 91.01, 2, 0.2], [91.79, 89.76, 2, 0.2]], "CC1_2#2": [[91.7898, 89.66, 2, 0.2], [92.373, 89.66, 2, 0.2]], "CC1_2#3": [[91.8, 89.7, 2, 0.2], [92.373, 89.66, 2, 0.2]], "CC1_3": [[163.29, 91.6, 2, 0.11], [163.29, 91.01, 2, 0.2], [163.29, 89.76, 2, 0.2]], "CC1_3#2": [[163.2897, 89.66, 2, 0.2], [163.873, 89.66, 2, 0.2]], "CC1_3#3": [[163.3, 89.7, 2, 0.2], [163.873, 89.66, 2, 0.2]], "CC1_4": [[92.55, 43.56, 2, 0.11], [92.55, 44.15, 2, 0.2], [92.55, 45.4, 2, 0.2]], "CC1_4#2": [[92.5502, 45.5, 2, 0.2], [91.967, 45.5, 2, 0.2]], "CC1_4#3": [[92.5, 45.4, 2, 0.2], [91.967, 45.5, 2, 0.2]], "CC1_5": [[164.05, 43.56, 2, 0.11], [164.05, 44.15, 2, 0.2], [164.05, 45.4, 2, 0.2]], "CC1_5#2": [[164.0502, 45.5, 2, 0.2], [163.467, 45.5, 2, 0.2]], "CC1_5#3": [[164.0, 45.4, 2, 0.2], [163.467, 45.5, 2, 0.2]], "VBUS_UP": [[212.3918, 59.5997, 2, 0.2], [211.4418, 59.5997, 2, 0.2]], "VBUS_UP#2": [[212.3919, 64.3998, 2, 0.2], [211.4419, 64.3998, 2, 0.2]], "VBUS_UP#3": [[106.7328, 65.85, 2, 0.2], [107.316, 65.85, 2, 0.2]], "VBUS_UP#4": [[80.4329, 61.5, 2, 0.2], [81.0161, 61.5, 2, 0.2]], "VBUS_UP#5": [[211.4418, 59.5997, 2, 0.2], [211.1, 59.6, 2, 0.2], [211.1, 59.6, 1, 0.2], [211.4, 59.9, 1, 0.2], [211.4419, 64.3998, 1, 0.2], [211.4419, 64.3998, 2, 0.2], [211.4419, 64.3998, 2, 0.2]], "VBUS_UP#6": [[211.2, 64.5, 1, 0.2], [112.7, 64.5, 1, 0.2], [110.0, 67.2, 1, 0.2], [108.9, 67.2, 1, 0.2], [107.4, 65.8, 1, 0.2], [107.4, 65.8, 2, 0.2], [107.316, 65.85, 2, 0.2]], "VBUS_UP#7": [[107.1, 65.8, 1, 0.2], [106.6, 65.3, 1, 0.2], [101.4, 65.3, 1, 0.2], [93.9, 57.8, 1, 0.2], [92.7, 57.8, 1, 0.2], [92.7, 57.8, 2, 0.2], [92.1, 57.2, 2, 0.2], [84.1, 57.2, 2, 0.2], [82.9, 58.4, 2, 0.2], [82.9, 59.6, 2, 0.2], [81.0161, 61.5, 2, 0.2]], "RBIAS": [[96.55, 62.1327, 2, 0.2], [96.55, 62.7159, 2, 0.2]], "RBIAS#2": [[96.75, 63.5501, 2, 0.2], [96.75, 62.8247, 2, 0.2]], "RBIAS#3": [[96.55, 62.7159, 2, 0.2], [96.75, 62.8247, 2, 0.2]], "VDD18": [[100.7501, 73.88, 2, 0.2], [100.7501, 73.3298, 2, 0.2]], "VDD18#2": [[100.2501, 72.45, 2, 0.2], [100.2501, 73.1755, 2, 0.2]], "VDD18#3": [[100.7501, 73.3298, 2, 0.2], [100.2501, 73.1755, 2, 0.2]], "VDD18PLL": [[97.3501, 62.12, 2, 0.2], [97.3501, 62.6702, 2, 0.2]], "VDD18PLL#2": [[97.2501, 63.5501, 2, 0.2], [97.2501, 62.8247, 2, 0.2]], "VDD18PLL#3": [[97.3501, 62.6702, 2, 0.15], [97.2501, 62.8247, 2, 0.15]], "XTAL1": [[93.22, 59.6501, 2, 0.2], [93.7702, 59.6501, 2, 0.2]], "XTAL1#2": [[97.75, 63.5501, 2, 0.2], [97.75, 62.8247, 2, 0.2]], "XTAL1#3": [[93.7702, 59.6501, 2, 0.2], [94.6998, 59.65, 2, 0.2]], "XTAL1#4": [[95.15, 60.225, 2, 0.15], [95.15, 60.225, 1, 0.15], [95.3, 60.375, 1, 0.15], [95.3, 61.925, 1, 0.15], [97.75, 64.375, 1, 0.15], [97.75, 64.375, 2, 0.15], [97.75, 62.8247, 2, 0.15]], "XTAL2": [[96.9, 56.12, 2, 0.2], [96.9, 56.6702, 2, 0.2]], "XTAL2#2": [[98.2501, 63.5501, 2, 0.2], [98.2501, 62.8247, 2, 0.2]], "XTAL2#3": [[96.9, 56.6702, 2, 0.2], [96.9, 57.95, 2, 0.2]], "XTAL2#4": [[97.5, 58.4, 2, 0.15], [97.5, 58.4, 1, 0.15], [97.5, 60.775, 1, 0.15], [101.225, 64.5, 1, 0.15], [101.5, 64.5, 1, 0.15], [101.5, 64.5, 2, 0.15], [98.7, 64.5, 2, 0.15], [98.3, 64.1, 2, 0.15], [98.2501, 62.8247, 2, 0.15]], "CFGSEL0": [[108.4671, 67.6501, 2, 0.2], [107.8839, 67.6501, 2, 0.2]], "CFGSEL0#2": [[104.45, 67.7503, 2, 0.2], [105.1755, 67.7503, 2, 0.2]], "CFGSEL0#3": [[107.8839, 67.6501, 2, 0.2], [108.3, 67.7, 2, 0.2], [108.3, 67.7, 1, 0.2], [108.3, 68.55, 1, 0.2], [107.95, 68.9, 1, 0.2], [104.65, 68.9, 1, 0.2], [103.55, 67.8, 1, 0.2], [103.55, 67.8, 2, 0.2], [105.1755, 67.7503, 2, 0.2]], "CFGSEL1": [[105.8672, 67.0499, 2, 0.2], [105.464, 67.0499, 2, 0.2]], "CFGSEL1#2": [[104.45, 67.2501, 2, 0.2], [105.1755, 67.2501, 2, 0.2]], "CFGSEL1#3": [[105.464, 67.0499, 2, 0.2], [105.1755, 67.2501, 2, 0.2]], "NONREM0": [[108.4671, 65.2501, 2, 0.2], [107.8839, 65.2501, 2, 0.2]], "NONREM0#2": [[104.45, 65.7503, 2, 0.2], [103.7246, 65.7503, 2, 0.2]], "NONREM0#3": [[107.8839, 65.2501, 2, 0.2], [108.45, 64.7, 2, 0.2], [108.45, 64.25, 2, 0.2], [108.45, 64.25, 1, 0.2], [108.8522, 64.7984, 1, 0.2], [109.25, 65.0, 1, 0.2], [111.25, 65.0, 1, 0.2], [111.5, 64.75, 1, 0.2], [111.5, 64.75, 2, 0.2], [111.5, 67.4, 2, 0.2], [111.5, 67.4, 1, 0.2], [109.55, 69.35, 1, 0.2], [104.1, 69.35, 1, 0.2], [102.9, 68.15, 1, 0.2], [102.9, 66.55, 1, 0.2], [103.45, 66.0, 1, 0.2], [103.45, 66.0, 2, 0.2], [103.7246, 65.7503, 2, 0.2]], "NONREM1": [[105.8672, 68.2501, 2, 0.2], [105.284, 68.2501, 2, 0.2]], "NONREM1#2": [[104.45, 68.2501, 2, 0.2], [105.1755, 68.2501, 2, 0.2]], "NONREM1#3": [[105.284, 68.2501, 2, 0.2], [105.1755, 68.2501, 2, 0.2]], "PRTDIS6": [[102.4499, 62.1327, 2, 0.2], [102.4499, 62.7159, 2, 0.2]], "PRTDIS6#2": [[101.2501, 63.5501, 2, 0.2], [101.2501, 62.8247, 2, 0.2]], "PRTDIS6#3": [[102.4499, 62.7159, 2, 0.2], [101.2501, 62.8247, 2, 0.2]], "PRTDIS7": [[101.25, 62.1327, 2, 0.2], [101.8205, 62.1327, 2, 0.2]], "PRTDIS7#2": [[100.2501, 63.5501, 2, 0.2], [100.2501, 62.8247, 2, 0.2]], "PRTDIS7#3": [[101.8205, 62.1327, 2, 0.2], [101.3603, 62.1163, 2, 0.2], [100.5925, 62.4429, 2, 0.2], [100.2501, 62.8247, 2, 0.2]], "HUB_RST": [[104.45, 66.75, 2, 0.15], [105.19, 66.75, 2, 0.15], [105.49, 66.45, 2, 0.15], [108.467, 66.45, 2, 0.15]], "HUB_RST#2": [[108.4671, 66.45, 2, 0.2], [107.8839, 66.45, 2, 0.2]], "HUB_RST#3": [[107.8839, 66.45, 2, 0.2]], "HUB_RST#4": [[104.4, 66.75, 2, 0.2], [103.65, 66.75, 2, 0.2], [103.0768, 67.3232, 2, 0.2], [102.9076, 67.7499, 2, 0.2], [102.95, 69.15, 2, 0.2], [102.95, 69.15, 1, 0.2], [103.8, 70.0, 1, 0.2], [150.4, 70.0, 1, 0.2], [151.6499, 68.77, 1, 0.2]], "+3V3_HUB": [[95.55, 66.25, 2, 0.28], [90.75, 66.25, 2, 0.28], [90.4, 66.6, 2, 0.28], [90.4, 70.5, 2, 0.28], [90.4, 70.5, 1, 0.28], [88.2, 70.5, 1, 0.28], [88.2, 70.5, 2, 0.28], [88.2, 71.0799, 2, 0.28]], "+3V3_HUB#2": [[95.55, 68.75, 2, 0.28], [93.3, 68.75, 2, 0.28], [92.95, 69.1, 2, 0.28], [92.95, 69.55, 2, 0.28], [92.5, 70.0, 2, 0.28], [92.4999, 70.7799, 2, 0.28]], "+3V3_HUB#3": [[90.3, 61.0, 2, 0.28], [90.3, 61.65, 2, 0.28], [90.3, 61.65, 1, 0.28], [90.4592, 69.9837, 1, 0.28], [90.9552, 70.3678, 1, 0.28], [92.5, 70.0, 1, 0.28], [92.5, 70.0, 2, 0.28], [92.4999, 70.7799, 2, 0.28]], "+3V3_HUB#4": [[102.25, 63.55, 2, 0.24], [102.25, 64.125, 2, 0.24], [103.375, 65.25, 2, 0.24], [104.45, 65.25, 2, 0.24]], "+3V3_HUB#5": [[105.95, 63.45, 2, 0.35], [105.95, 63.825, 2, 0.35], [105.95, 63.825, 1, 0.35], [106.275, 64.15, 1, 0.35], [107.3, 64.15, 1, 0.35], [109.6, 66.45, 1, 0.35], [109.6, 66.45, 2, 0.35], [109.333, 66.45, 2, 0.35]], "+3V3_HUB#6": [[95.55, 62.12, 2, 0.35], [95.55, 62.6702, 2, 0.35]], "+3V3_HUB#7": [[100.0001, 59.4401, 2, 0.35], [100.5706, 59.4401, 2, 0.35]], "+3V3_HUB#8": [[103.65, 62.12, 2, 0.35], [103.65, 62.6702, 2, 0.35]], "+3V3_HUB#9": [[88.2, 71.0799, 2, 0.35], [88.2, 70.5297, 2, 0.35]], "+3V3_HUB#10": [[92.4999, 70.7799, 2, 0.35], [92.4999, 70.2297, 2, 0.35]], "+3V3_HUB#11": [[99.25, 73.88, 2, 0.35], [99.25, 73.3298, 2, 0.35]], "+3V3_HUB#12": [[102.4499, 61.2671, 2, 0.35], [102.9204, 61.2671, 2, 0.35]], "+3V3_HUB#13": [[101.25, 61.2671, 2, 0.35], [101.8205, 61.2671, 2, 0.35]], "+3V3_HUB#14": [[109.3328, 66.45, 2, 0.35], [109.736, 66.45, 2, 0.35]], "+3V3_HUB#15": [[99.75, 72.45, 2, 0.2997199999999998], [99.75, 73.1755, 2, 0.2997199999999998]], "+3V3_HUB#16": [[104.45, 65.2501, 2, 0.2997199999999998], [105.1755, 65.2501, 2, 0.2997199999999998]], "+3V3_HUB#17": [[99.75, 63.5501, 2, 0.2997199999999998], [99.75, 62.8247, 2, 0.2997199999999998]], "+3V3_HUB#18": [[96.2501, 63.5501, 2, 0.2997199999999998], [95.8003, 63.5501, 2, 0.2997199999999998]], "+3V3_HUB#19": [[62.5, 60.42, 2, 0.35], [62.5, 60.9702, 2, 0.35]], "+3V3_HUB#20": [[60.705, 58.0949, 2, 0.35], [61.9803, 58.0949, 2, 0.35]], "+3V3_HUB#21": [[106.44, 106.6599, 2, 0.35], [107.2899, 106.6599, 2, 0.35]], "+3V3_HUB#22": [[154.67, 28.5001, 2, 0.35], [155.2202, 28.5001, 2, 0.35]], "+3V3_HUB#23": [[172.67, 106.6599, 2, 0.35], [172.1198, 106.6599, 2, 0.35]], "+3V3_HUB#24": [[83.17, 28.5001, 2, 0.35], [83.7202, 28.5001, 2, 0.35]], "+3V3_HUB#25": [[34.94, 106.6599, 2, 0.35], [35.7899, 106.6599, 2, 0.35]], "+3V3_HUB#26": [[29.67, 106.6599, 2, 0.35], [29.1198, 106.6599, 2, 0.35]], "+3V3_HUB#27": [[101.17, 106.6599, 2, 0.35], [100.6198, 106.6599, 2, 0.35]], "+3V3_HUB#28": [[177.94, 106.6599, 2, 0.35], [178.7899, 106.6599, 2, 0.35]], "+3V3_HUB#29": [[77.9, 28.5001, 2, 0.35], [77.0501, 28.5001, 2, 0.35]], "+3V3_HUB#30": [[149.4, 28.5001, 2, 0.35], [148.5501, 28.5001, 2, 0.35]], "+3V3_HUB#31": [[88.2, 70.5297, 2, 0.35]], "+3V3_HUB#32": [[90.7, 70.5, 1, 0.35], [90.9, 70.7, 1, 0.35], [92.3, 70.7, 1, 0.35], [92.3, 70.7, 2, 0.35], [92.4, 70.7, 2, 0.35]], "+3V3_HUB#33": [[90.4, 70.2, 1, 0.35]], "+3V3_HUB#34": [[92.4999, 70.2297, 2, 0.35]], "+3V3_HUB#35": [[92.3, 71.0, 1, 0.35], [93.3, 72.0, 1, 0.35], [93.3, 72.6, 1, 0.35], [95.0001, 74.3001, 1, 0.35], [95.0001, 74.3001, 2, 0.35], [95.0001, 74.3001, 2, 0.35]], "+3V3_HUB#36": [[95.3, 74.25, 1, 0.35], [96.6, 72.95, 1, 0.35], [98.7, 72.95, 1, 0.35], [99.2, 73.45, 1, 0.35], [99.2, 73.45, 2, 0.35], [99.25, 73.3298, 2, 0.35]], "+3V3_HUB#37": [[99.475, 73.325, 2, 0.35], [99.75, 73.1755, 2, 0.35]], "+3V3_HUB#38": [[90.6, 61.7, 2, 0.35], [93.9, 61.7, 2, 0.35], [95.8003, 63.5501, 2, 0.35]], "+3V3_HUB#39": [[95.3, 62.9, 2, 0.35], [95.55, 62.6702, 2, 0.35]], "+3V3_HUB#40": [[95.675, 66.25, 2, 0.245], [96.45, 66.25, 2, 0.245], [97.45, 65.25, 2, 0.245], [101.725, 65.25, 2, 0.245], [102.15, 64.825, 2, 0.245], [102.325, 64.425, 2, 0.245], [102.325, 64.425, 1, 0.245], [100.125, 62.175, 1, 0.245], [99.925, 62.175, 1, 0.245], [99.925, 62.175, 2, 0.245], [99.75, 62.8247, 2, 0.245]], "+3V3_HUB#41": [[100.1, 62.0, 2, 0.35], [100.8, 61.3, 2, 0.35], [101.8205, 61.2671, 2, 0.35]], "+3V3_HUB#42": [[101.9, 61.3, 2, 0.35], [102.9204, 61.2671, 2, 0.35]], "+3V3_HUB#43": [[102.1, 64.0, 1, 0.35], [103.55, 62.55, 1, 0.35], [103.55, 62.55, 2, 0.35], [103.65, 62.6702, 2, 0.35]], "+3V3_HUB#44": [[100.0, 61.9, 1, 0.35], [101.3, 60.6, 1, 0.35], [101.3, 59.4, 1, 0.35], [101.3, 59.4, 2, 0.35], [100.5706, 59.4401, 2, 0.35]], "+3V3_HUB#45": [[102.4, 64.4, 2, 0.35]], "+3V3_HUB#46": [[104.55, 65.25, 2, 0.245], [105.1755, 65.2501, 2, 0.245]], "+3V3_HUB#47": [[103.8, 62.6, 2, 0.35], [105.2, 62.6, 2, 0.35], [105.9, 63.3, 2, 0.35]], "+3V3_HUB#48": [[109.736, 66.45, 2, 0.35]], "+3V3_HUB#49": [[101.5, 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106.6599, 2, 0.35]], "+3V3_HUB#56": [[100.6, 105.8, 1, 0.35], [106.4, 105.8, 1, 0.35], [107.2899, 106.6599, 1, 0.35], [107.2899, 106.6599, 2, 0.35], [107.2899, 106.6599, 2, 0.35]], "+3V3_HUB#57": [[100.4, 105.8, 1, 0.35], [36.7, 105.8, 1, 0.35], [35.7899, 106.6599, 1, 0.35], [35.7899, 106.6599, 2, 0.35], [35.7899, 106.6599, 2, 0.35]], "+3V3_HUB#58": [[35.5, 106.6, 1, 0.35], [34.7, 105.8, 1, 0.35], [30.0, 105.8, 1, 0.35], [29.1198, 106.6599, 1, 0.35], [29.1198, 106.6599, 2, 0.35], [29.1198, 106.6599, 2, 0.35]], "+3V3_HUB#59": [[101.8, 57.8, 2, 0.15], [107.8, 51.8, 2, 0.15], [120.8, 51.8, 2, 0.15], [141.0, 31.6, 2, 0.15], [145.1, 31.6, 2, 0.15], [145.9447, 31.2378, 2, 0.15], [148.5501, 28.5001, 2, 0.15]], "+3V3_HUB#60": [[147.7, 29.6, 2, 0.35], [148.4, 30.3, 2, 0.35], [154.2, 30.3, 2, 0.35], [154.7, 29.8, 2, 0.35], [154.7, 29.3607, 2, 0.35], [154.9601, 28.75, 2, 0.35], [155.2202, 28.5001, 2, 0.35]], "+3V3_HUB#61": [[107.4, 106.4, 1, 0.35], [108.0, 105.8, 1, 0.35], [170.9, 105.8, 1, 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89.66, 2, 0.5]], "VBUS4": [[78.8299, 33.5001, 2, 0.5], [78.8299, 34.0706, 2, 0.5]], "VBUS4#2": [[87.22, 42.5, 2, 0.4902199999999997], [87.22, 43.1798, 2, 0.4902199999999997]], "VBUS4#3": [[93.4159, 45.5, 2, 0.5], [93.8991, 45.5, 2, 0.5]], "VBUS4#4": [[73.9, 34.45, 2, 0.5], [73.0501, 34.45, 2, 0.5]], "VBUS4#5": [[73.9, 33.5001, 2, 0.5], [73.0501, 33.5001, 2, 0.5]], "VBUS4#6": [[89.55, 48.149, 2, 0.5], [89.55, 48.9849, 2, 0.5]], "VBUS4#7": [[78.8299, 34.0706, 2, 0.5], [78.4, 34.2, 2, 0.5], [78.4, 34.2, 1, 0.5], [78.2, 34.4, 1, 0.5], [75.4, 34.4, 1, 0.5], [73.5, 36.3, 1, 0.5], [73.5, 36.3, 2, 0.5], [72.1, 36.3, 2, 0.5], [71.7, 35.9, 2, 0.5], [71.7, 35.9, 1, 0.5], [73.0501, 34.45, 1, 0.5], [73.0501, 34.45, 2, 0.5], [73.0501, 34.45, 2, 0.5]], "VBUS4#8": [[73.1, 34.2, 2, 0.5], [73.0501, 33.5001, 2, 0.5]], "VBUS4#9": [[78.55, 34.45, 1, 0.5], [87.25, 43.15, 1, 0.5], [87.25, 43.15, 2, 0.5], [87.22, 43.1798, 2, 0.5]], "VBUS4#10": [[87.1, 43.4, 1, 0.5], [87.0161, 46.0003, 1, 0.5], [87.3581, 46.849, 1, 0.5], [89.55, 48.9849, 1, 0.5], [89.55, 48.9849, 2, 0.5], [89.55, 48.9849, 2, 0.5]], "VBUS4#11": [[89.85, 48.95, 1, 0.5], [93.25, 45.55, 1, 0.5], [93.85, 45.55, 1, 0.5], [93.85, 45.55, 2, 0.5], [93.8991, 45.5, 2, 0.5]], "VBUS5": [[150.3299, 33.5001, 2, 0.5], [150.3299, 34.0706, 2, 0.5]], "VBUS5#2": [[158.72, 42.5, 2, 0.4902199999999997], [158.72, 43.1798, 2, 0.4902199999999997]], "VBUS5#3": [[164.9158, 45.5, 2, 0.5], [165.3991, 45.5, 2, 0.5]], "VBUS5#4": [[145.4, 34.45, 2, 0.5], [144.5501, 34.45, 2, 0.5]], "VBUS5#5": [[145.4, 33.5001, 2, 0.5], [144.5501, 33.5001, 2, 0.5]], "VBUS5#6": [[161.05, 48.149, 2, 0.5], [161.05, 48.9849, 2, 0.5]], "VBUS5#7": [[150.3299, 34.0706, 2, 0.5], [150.3, 34.4, 2, 0.5], [148.4, 36.3, 2, 0.5], [146.7, 36.3, 2, 0.5], [146.7, 36.3, 1, 0.5], [144.9, 34.5, 1, 0.5], [144.9, 34.5, 2, 0.5], [144.5501, 34.45, 2, 0.5]], "VBUS5#8": [[144.6, 34.3, 2, 0.5], [144.5501, 33.5001, 2, 0.5]], "VBUS5#9": [[150.2, 34.8, 2, 0.5], [158.72, 43.1798, 2, 0.5]], "VBUS5#10": [[158.5, 43.4, 2, 0.5], [158.5, 46.5, 2, 0.5], [159.3, 47.3, 2, 0.5], [159.3, 47.3, 1, 0.5], [161.05, 48.9849, 1, 0.5], [161.05, 48.9849, 2, 0.5], [161.05, 48.9849, 2, 0.5]], "VBUS5#11": [[161.35, 48.95, 1, 0.5], [164.75, 45.55, 1, 0.5], [165.35, 45.55, 1, 0.5], [165.35, 45.55, 2, 0.5], [165.3991, 45.5, 2, 0.5]], "POGO1_VDN": [[55.6499, 68.77, 2, 0.2], [55.6, 74.0, 2, 0.2], [55.6, 74.0, 1, 0.2], [59.3, 77.7, 1, 0.2], [59.3, 105.0, 1, 0.2], [59.3, 105.0, 2, 0.2], [63.0, 108.7, 2, 0.2], [63.0, 117.4, 2, 0.2], [66.6801, 121.14, 2, 0.2], [66.6801, 121.14, 1, 0.2], [66.6801, 121.14, 1, 0.2]], "POGO1_PWR": [[50.5699, 68.77, 2, 0.2], [50.6, 79.0, 2, 0.2], [50.6, 79.0, 1, 0.2], [58.6, 87.0, 1, 0.2], [58.6, 103.1, 1, 0.2], [58.6, 103.1, 2, 0.2], [63.5, 108.0, 2, 0.2], [63.5, 115.0, 2, 0.2], [63.861, 115.8459, 2, 0.2], [68.98, 120.7501, 2, 0.2], [68.98, 120.7501, 1, 0.2], [68.98, 120.7501, 1, 0.2]], "POGO1_VUP": [[53.1099, 68.77, 2, 0.2], [53.1, 76.5, 2, 0.2], [53.1, 76.5, 1, 0.2], [53.1, 80.4, 1, 0.2], [53.1, 80.4, 2, 0.2], [64.0, 91.3, 2, 0.2], [64.0, 109.5, 2, 0.2], [69.8, 115.3, 2, 0.2], [69.8, 122.4272, 2, 0.2], [69.595, 122.88, 2, 0.2], [69.39, 123.06, 2, 0.2], [69.39, 123.06, 1, 0.2], [69.39, 123.06, 1, 0.2]], "POGO2_PWR": [[138.9499, 68.77, 2, 0.2], [142.2, 72.1, 2, 0.2], [142.2, 72.1, 1, 0.2], [143.3, 73.2, 1, 0.2], [143.3, 73.2, 2, 0.2], [143.3, 74.6, 2, 0.2], [143.3, 74.6, 1, 0.2], [143.3, 105.0, 1, 0.2], [143.3, 105.0, 2, 0.2], [143.3, 118.0, 2, 0.2], [140.48, 120.7501, 2, 0.2], [140.48, 120.7501, 1, 0.2], [140.48, 120.7501, 1, 0.2]], "POGO2_VDN": [[144.0299, 68.77, 2, 0.2], [144.9464, 67.8535, 2, 0.2], [145.7999, 67.5098, 2, 0.2], [150.1001, 67.5941, 2, 0.2], [150.4, 67.9, 2, 0.2], [150.4, 70.5, 2, 0.2], [150.2, 70.7, 2, 0.2], [150.2, 70.7, 1, 0.2], [144.7, 76.2, 1, 0.2], [144.7, 102.4, 1, 0.2], [144.0, 103.1, 1, 0.2], [144.0, 103.1, 2, 0.2], [142.6, 104.5, 2, 0.2], [142.6, 117.1, 2, 0.2], [141.2, 118.5, 2, 0.2], [140.8, 118.5, 2, 0.2], [138.1801, 121.14, 2, 0.2], [138.1801, 121.14, 1, 0.2], [138.1801, 121.14, 1, 0.2]], "POGO2_VUP": [[141.4899, 68.77, 1, 0.2], [140.2, 67.5, 1, 0.2], [132.5, 67.6, 1, 0.2], [132.5, 67.6, 2, 0.2], [132.5, 69.8, 2, 0.2], [134.3, 71.6, 2, 0.2], [140.6, 71.6, 2, 0.2], [140.6, 71.6, 1, 0.2], [140.8, 71.4, 1, 0.2], [142.8, 71.4, 1, 0.2], [144.1, 72.7, 1, 0.2], [144.1, 72.7, 2, 0.2], [144.2, 74.6, 2, 0.2], [144.2, 74.6, 1, 0.2], [144.0, 74.8, 1, 0.2], [144.0, 101.9, 1, 0.2], [144.0, 101.9, 2, 0.2], [141.9, 104.0, 2, 0.2], [141.9, 116.7, 2, 0.2], [141.9, 116.7, 1, 0.2], [141.9, 121.6, 1, 0.2], [141.5376, 122.4445, 1, 0.2], [140.89, 123.06, 1, 0.2]], "POGO3_VDN": [[166.8899, 68.77, 1, 0.2], [177.4, 79.3, 1, 0.2], [177.4, 87.6, 1, 0.2], [177.4, 87.6, 2, 0.2], [178.9, 89.1, 2, 0.2], [178.9, 89.1, 1, 0.2], [201.9, 112.1, 1, 0.2], [201.9, 113.3, 1, 0.2], [209.68, 121.14, 1, 0.2]], "POGO3_PWR": [[161.8099, 68.77, 1, 0.2], [176.7, 83.7, 1, 0.2], [176.7, 85.7, 1, 0.2], [176.7, 85.7, 2, 0.2], [178.9, 87.9, 2, 0.2], [178.9, 87.9, 1, 0.2], [211.98, 120.7501, 1, 0.2]], "POGO3_VUP": [[164.3499, 68.77, 1, 0.2], [168.0, 72.5, 1, 0.2], [169.5, 72.5, 1, 0.2], [169.5, 72.5, 2, 0.2], [178.4, 81.4, 2, 0.2], [178.9, 81.4, 2, 0.2], [178.9, 81.4, 1, 0.2], [213.4, 115.9, 1, 0.2], [213.4, 121.6, 1, 0.2], [213.0376, 122.4445, 1, 0.2], [212.39, 123.06, 1, 0.2]], "POGO4_PWR": [[50.5699, 66.23, 1, 0.2], [50.5997, 21.4, 1, 0.2], [50.2398, 20.5532, 1, 0.2], [43.86, 14.4099, 1, 0.2]], "POGO4_VDN": [[55.6499, 66.23, 1, 0.2], [54.6, 65.2, 1, 0.2], [54.6, 24.0, 1, 0.2], [53.6, 23.0, 1, 0.2], [53.6, 21.4, 1, 0.2], [46.1599, 14.02, 1, 0.2]], "POGO4_VUP": [[53.1099, 66.23, 1, 0.2], [52.159, 67.152, 1, 0.2], [51.3004, 67.48, 1, 0.2], [49.5998, 67.412, 1, 0.2], [49.3, 67.1, 1, 0.2], [49.3, 26.1, 1, 0.2], [42.5, 19.3, 1, 0.2], [42.5, 13.1, 1, 0.2], [43.45, 12.1001, 1, 0.2]], "POGO5_PWR": [[161.8099, 66.23, 2, 0.2], [161.8, 61.4, 2, 0.2], [161.8, 61.4, 1, 0.2], [148.3, 47.9, 1, 0.2], [148.3, 47.1, 1, 0.2], [148.3, 47.1, 2, 0.2], [137.5, 36.3, 2, 0.2], [137.5, 36.3, 1, 0.2], [115.3599, 14.4099, 1, 0.2]], "POGO5_VDN": [[166.8899, 66.23, 2, 0.2], [163.8, 63.1, 2, 0.2], [163.8, 61.4, 2, 0.2], [163.8, 61.4, 1, 0.2], [149.2, 46.8, 1, 0.2], [149.2, 46.8, 2, 0.2], [138.4, 36.0, 2, 0.2], [138.4, 36.0, 1, 0.2], [137.7, 35.6, 1, 0.2], [125.1, 23.0, 1, 0.2], [125.1, 21.4, 1, 0.2], [117.6599, 14.02, 1, 0.2]], "POGO5_VUP": [[164.3499, 66.23, 2, 0.2], [162.5, 64.4, 2, 0.2], [162.5, 63.3, 2, 0.2], [162.5, 63.3, 1, 0.2], [151.0, 51.7, 1, 0.2], [151.0, 51.7, 2, 0.2], [139.9, 40.6, 2, 0.2], [139.9, 39.8, 2, 0.2], [139.9, 39.8, 1, 0.2], [139.9, 36.3, 1, 0.2], [138.7, 35.1, 1, 0.2], [138.2, 35.1, 1, 0.2], [128.6, 25.5, 1, 0.2], [128.6, 22.3, 1, 0.2], [118.9, 12.6, 1, 0.2], [115.7363, 12.6, 1, 0.2], [115.175, 12.35, 1, 0.2], [114.95, 12.1001, 1, 0.2]], "SDA": [[55.2948, 58.0949, 2, 0.2], [54.0194, 58.0949, 2, 0.2]], "SDA#2": [[63.2699, 68.77, 1, 0.2], [62.0, 67.5, 1, 0.2], [59.7498, 67.41, 1, 0.2], [59.5, 67.15, 1, 0.2], [59.5, 62.1, 1, 0.2], [58.9, 61.5, 1, 0.2], [58.9, 61.5, 2, 0.2], [58.5, 61.1, 2, 0.2], [58.5, 60.6, 2, 0.2], [56.6, 58.7, 2, 0.2], [55.0193, 58.7, 2, 0.2], [54.3097, 58.3975, 2, 0.2], [54.0194, 58.0949, 2, 0.2]], "SCL": [[55.2948, 59.3649, 2, 0.2], [54.0194, 59.3649, 2, 0.2]], "SCL#2": [[65.8099, 68.77, 2, 0.2], [64.6, 67.55, 2, 0.2], [56.95, 67.5, 2, 0.2], [56.95, 67.5, 1, 0.2], [56.95, 63.0, 1, 0.2], [55.25, 61.3, 1, 0.2], [55.25, 59.8, 1, 0.2], [55.25, 59.8, 2, 0.2], [55.025, 59.575, 2, 0.2], [54.4819, 59.3561, 2, 0.2], [54.0194, 59.3649, 2, 0.2]]} \ No newline at end of file +{"$16N235": [[95.5501, 71.2501, 2, 0.2], [94.8247, 71.2501, 2, 0.2], [95.5501, 71.2501, 2, 0.2]], "$16N237": [[96.2501, 72.45, 2, 0.2], [96.2501, 73.1755, 2, 0.2], [96.2501, 72.45, 2, 0.2]], "$16N239": [[103.2501, 72.45, 2, 0.2], [103.2501, 72.9955, 2, 0.2], [103.2501, 72.45, 2, 0.2]], "$16N241": [[104.45, 71.7503, 2, 0.2], [104.9955, 71.7503, 2, 0.2]], "$16N241\u00002": [[105.632, 72.3908, 2, 0.2], [105.632, 72.974, 2, 0.2]], "$16N241\u00003": [[104.9955, 71.7503, 2, 0.2], [105.0, 72.3, 2, 0.2], [105.632, 72.974, 2, 0.2]], "$16N243": [[103.75, 63.5501, 2, 0.2], [104.1998, 63.5501, 2, 0.2], [103.75, 63.5501, 2, 0.2]], "$16N245": [[104.45, 64.2501, 2, 0.2], [104.9955, 64.2501, 2, 0.2], [104.45, 64.2501, 2, 0.2]], "$16N247": [[104.45, 64.7503, 2, 0.2], [105.1755, 64.7503, 2, 0.2], [104.45, 64.7503, 2, 0.2]], "$16N247\u00002": [[107.0678, 62.145, 2, 0.2], [107.651, 62.145, 2, 0.2], [107.0678, 62.145, 2, 0.2]], "$16N249": [[103.2501, 63.5501, 2, 0.2], [103.2501, 63.0047, 2, 0.2], [103.2501, 63.5501, 2, 0.2]], "$16N251": [[102.75, 63.5501, 2, 0.2], [102.75, 63.0047, 2, 0.2], [102.75, 63.5501, 2, 0.2]], "$16N253": [[104.45, 71.2501, 2, 0.2], [104.9955, 71.2501, 2, 0.2]], "$16N253\u00002": [[105.676, 70.6548, 2, 0.2], [106.2465, 70.6548, 2, 0.2]], "$16N253\u00003": [[104.9955, 71.2501, 2, 0.2], [103.85, 71.25, 2, 0.2], [103.45, 70.85, 2, 0.2], [103.45, 70.36, 2, 0.2], [103.51, 70.3024, 2, 0.2], [103.51, 70.3024, 1, 0.2], [107.2, 70.448, 1, 0.2], [107.25, 70.4, 1, 0.2], [107.25, 70.35, 1, 0.2], [107.25, 70.35, 2, 0.2], [106.95, 70.65, 2, 0.2], [106.2465, 70.6548, 2, 0.2]]} \ No newline at end of file diff --git a/.claude/_refresh_geo.py b/.claude/_refresh_geo.py index 4ec1c55..a58d016 100644 --- a/.claude/_refresh_geo.py +++ b/.claude/_refresh_geo.py @@ -1,31 +1,31 @@ -# -*- coding: utf-8 -*- -u"""刷新 `_pcb2_pads_full.json` / `_pcb2_vias.json`（inner1_* 三个校核脚本的输入）。""" -import json, os, sys -HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) -from eda import run -JS = u""" -await eda.dmt_EditorControl.openDocument('f126ffb29c92f9b2'); -await new Promise(r=>setTimeout(r,1800)); -const name = {}; -for (const c of await eda.pcb_PrimitiveComponent.getAll()) - name[c.getState_PrimitiveId()] = c.getState_Designator(); -const ids = Object.keys(name).sort((a,b)=>b.length-a.length); -const pads = []; -for (const p of await eda.pcb_PrimitivePad.getAll()) { - const pid = p.getState_PrimitiveId(); let hit=''; - for (const id of ids) if (pid.length>id.length && pid.indexOf(id)===0){hit=name[id];break;} - pads.push([hit, p.getState_PadNumber(), p.getState_Net(), p.getState_Layer(), - p.getState_X(), p.getState_Y(), p.getState_Pad(), p.getState_Hole()]); -} -const vias = []; -for (const o of await eda.pcb_PrimitiveVia.getAll()) - vias.push([o.getState_Net(), o.getState_X(), o.getState_Y(), o.getState_Diameter(), o.getState_HoleDiameter()]); -return {pads: pads, vias: vias}; -""" -r = run(JS, timeout=300) -if not r.get('success'): - sys.exit(u'失败: ' + json.dumps(r, ensure_ascii=False)[:400]) -d = r['result'] -json.dump(d['pads'], open(os.path.join(HERE, '_pcb2_pads_full.json'), 'w', encoding='utf-8'), ensure_ascii=False) -json.dump(d['vias'], open(os.path.join(HERE, '_pcb2_vias.json'), 'w', encoding='utf-8'), ensure_ascii=False) -print(u'焊盘 %d / 过孔 %d' % (len(d['pads']), len(d['vias']))) +# -*- coding: utf-8 -*- +u"""刷新 `_pcb2_pads_full.json` / `_pcb2_vias.json`（inner1_* 三个校核脚本的输入）。""" +import json, os, sys +HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) +from eda import run +JS = u""" +await eda.dmt_EditorControl.openDocument('942ed1560d81c1e7'); +await new Promise(r=>setTimeout(r,1800)); +const name = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) + name[c.getState_PrimitiveId()] = c.getState_Designator(); +const ids = Object.keys(name).sort((a,b)=>b.length-a.length); +const pads = []; +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const pid = p.getState_PrimitiveId(); let hit=''; + for (const id of ids) if (pid.length>id.length && pid.indexOf(id)===0){hit=name[id];break;} + pads.push([hit, p.getState_PadNumber(), p.getState_Net(), p.getState_Layer(), + p.getState_X(), p.getState_Y(), p.getState_Pad(), p.getState_Hole()]); +} +const vias = []; +for (const o of await eda.pcb_PrimitiveVia.getAll()) + vias.push([o.getState_Net(), o.getState_X(), o.getState_Y(), o.getState_Diameter(), o.getState_HoleDiameter()]); +return {pads: pads, vias: vias}; +""" +r = run(JS, timeout=300) +if not r.get('success'): + sys.exit(u'失败: ' + json.dumps(r, ensure_ascii=False)[:400]) +d = r['result'] +json.dump(d['pads'], open(os.path.join(HERE, '_pcb2_pads_full.json'), 'w', encoding='utf-8'), ensure_ascii=False) +json.dump(d['vias'], open(os.path.join(HERE, '_pcb2_vias.json'), 'w', encoding='utf-8'), ensure_ascii=False) +print(u'焊盘 %d / 过孔 %d' % (len(d['pads']), len(d['vias']))) diff --git a/.claude/_tmp_probe.js b/.claude/_tmp_probe.js deleted file mode 100644 index d2a8ec7..0000000 --- a/.claude/_tmp_probe.js +++ /dev/null @@ -1,23 +0,0 @@ -await eda.dmt_EditorControl.openDocument('7e9415a16a909c51'); -await new Promise(r => setTimeout(r, 1200)); -const M = 39.3701; -const R = (x0,y0,x1,y1) => [x0*M,y0*M,'L',x1*M,y0*M,x1*M,y1*M,x0*M,y1*M]; -const tries = [ - ['rect-L3-+12V', '+12V', 16, R(100,20,120,30)], - ['rect-L3-$net', '$1N223', 16, R(100,35,120,45)], - ['rect-L4-VO1_P', 'VO1_P', 2, R(100,50,120,60)], -]; -const out = []; -for (const [name, net, layer, src] of tries) { - const row = {name}; - try { - const poly = await eda.pcb_MathPolygon.createComplexPolygon([src]); - row.poly = !!poly; - const pour = await eda.pcb_PrimitivePour.create(net, layer, poly, 'solid', false, name, 3, 10); - row.pour = !!pour; - if (pour) await eda.pcb_PrimitivePour.delete(pour.primitiveId); - } catch (e) { row.err = String(e).slice(0, 140); } - out.push(row); -} -out.nPourNow = (await eda.pcb_PrimitivePour.getAll()).length; -return out; diff --git a/.claude/_tmp_probe2.js b/.claude/_tmp_probe2.js deleted file mode 100644 index d747e6d..0000000 --- a/.claude/_tmp_probe2.js +++ /dev/null @@ -1,25 +0,0 @@ -await eda.dmt_EditorControl.openDocument('7e9415a16a909c51'); -await new Promise(r => setTimeout(r, 1200)); -const M = 39.3701; -const R = (x0,y0,x1,y1) => [x0*M,y0*M,'L',x1*M,y0*M,x1*M,y1*M,x0*M,y1*M]; -const Rc= (x0,y0,x1,y1) => [x0*M,y0*M,'L',x1*M,y0*M,x1*M,y1*M,x0*M,y1*M,x0*M,y0*M]; // 显式闭合 -const Rr= (x0,y0,x1,y1) => ['R',x0*M,y0*M,x1*M,y1*M,0,0]; // R 矩形模式 -const cases = [ - ['L15-rect', 'GND', 15, R(100,20,120,30)], - ['L16-rect-close','+12V',16, Rc(100,35,120,45)], - ['L16-Rmode', '+12V',16, Rr(100,50,120,60)], - ['L1-rect', '+12V', 1, R(100,65,120,75)], -]; -const out = []; -for (const [name, net, layer, src] of cases) { - const row = {name}; - try { - const poly = await eda.pcb_MathPolygon.createComplexPolygon([src]); - row.poly = !!poly; - const pour = await eda.pcb_PrimitivePour.create(net, layer, poly, 'solid', false, name, 3, 10); - row.pour = !!pour; - if (pour) await eda.pcb_PrimitivePour.delete(pour.primitiveId); - } catch (e) { row.err = String(e).slice(0, 90); } - out.push(row); -} -return out; diff --git a/.claude/c4_site.py b/.claude/c4_site.py index 7ee5f95..2046873 100644 --- a/.claude/c4_site.py +++ b/.claude/c4_site.py @@ -3,7 +3,8 @@ u"""载板 C4-SITE1 ~ C4-SITE5：每台手机一页。 一页里三块： 【A】电池排线 4 焊盘直焊座 J8n（P+/P−/TEMP/ID，2026-09-06 取代 TP8n1/2）+ TEMP 10k / ID 68k + §6.3 电容组（六颗） - 【B】四根侧键顶针（PWR / VUP / VDN + J604 三键公共地） + 【B】四根侧键顶针（PWR / VUP / VDN + J604 三键公共地）+ 三颗按键 MOS（2N7002 + 1k 栅阻 + 100k 下拉） + —— 2026-09-06 随 74HC595 从下板 P2 搬来（§26.23），位号沿用 Q%d03~05 / R%d20~25 【C】EDL：1.25mm 2P 座 + TS5A3157 模拟开关 + 100k 下拉 + 去耦 用法: /c/Python314/python .claude/c4_site.py [--push] [--only N] @@ -50,6 +51,8 @@ P = { 'CONN2P': '6461e6e5749d421bb997627984866425', # C225104 A1251WV-S-2P 'SW': '5acafd8eb5a641fcaf05190902930635', # C353034 TS5A3157DBVR 'R100K': 'acc294b6661948399f609b41c77ed19f', # C25741 100k 0402 + 'NMOS': 'f8007837564a4f1fa0e6b57b81dccb0d', # C8545 2N7002（按键 MOS，从下板搬来） + 'R1K': '65abbad5fa864933b552e0f016ece0db', # C11702 1k 0402（栅极串阻） } # ---- 版面常量 ---- @@ -63,9 +66,14 @@ J8 = (225, 630) # 排线直焊座：符号 4 脚朝**左**（实 COL = {'1': 100, '2': 130, '3': 170, '4': 190} R78, R79 = (170, 575), (190, 575) # TEMP / ID 电阻（竖放），下端直接落在 GND 母线上 -POGO_X = [220, 320, 420, 520] # 【B】四根顶针的元件中心 -Y_POGO = 380 -POGO_PORT_Y = [330, 300, 270, 240] +# 【B】三个按键列（PWR / VUP / VDN），每列：顶针在上、按键 MOS 在下、K 端口从最底下进来。 +# 列内相对顶针中心 x_p：MOS (x_p-25, 360) → G(x_p-45,360) S(x_p-15,340) D(x_p-15,380)； +# 栅阻 R%20/22/24 (x_p-45, 330) 竖放；下拉 R%21/23/25 (x_p-75, 330) 竖放； +# K 端口 (x_p-45, 250)；POGO 端口挂在漏极竖线旁的横支线末端 (x_p+5, 410)（给 PCB 网络起名）。 +# 列距 120：一列占 x_p-85 ~ x_p+85（POGO 标签），最东一列的标签 515 < 【C】那根 x=530 的竖线。 +KEY_X = [190, 310, 430] +GND_POGO_X = 80 # 第四根顶针（J604 公共地） +Y_POGO = 440 J6, U4 = (660, 400), (880, 400) # 【C】 R74, C76 = (975, 370), (1060, 370) @@ -88,6 +96,9 @@ def names(n): 'j8': 'J8%d' % n, 'r78': 'R78%d' % n, 'r79': 'R79%d' % n, 'pogo': ['J%d' % (41 + (n - 1) * 4 + i) for i in range(4)], 'j6': 'J6%d' % n, 'u4': 'U4%d' % n, 'r74': 'R74%d' % n, 'c76': 'C76%d' % n, + 'q': ['Q%d0%d' % (n, k) for k in (3, 4, 5)], # PWR / VUP / VDN + 'rg': ['R%d2%d' % (n, k) for k in (0, 2, 4)], # 1k 栅阻 + 'rp': ['R%d2%d' % (n, k) for k in (1, 3, 5)], # 100k 下拉 } @@ -102,8 +113,12 @@ def placement(n): # 和 skill §6 那张表相反 —— 所以传 90。下面 EXPECT 会再断言一次。 rot = 90 if key == 'C2200U' else 270 out.append([d['caps'][i], P[key], CAP_X[i], Y_CAP, rot, LIB_POGO if key == 'C2200U' else LIB]) - for i, x in enumerate(POGO_X): + for i, x in enumerate(KEY_X): out.append([d['pogo'][i], P['POGO'], x, Y_POGO, 0, LIB_POGO]) + out.append([d['q'][i], P['NMOS'], x - 25, 360, 0, LIB]) + out.append([d['rg'][i], P['R1K'], x - 45, 330, 90, LIB]) + out.append([d['rp'][i], P['R100K'], x - 75, 330, 90, LIB]) + out.append([d['pogo'][3], P['POGO'], GND_POGO_X, Y_POGO, 0, LIB_POGO]) out += [[d['j6'], P['CONN2P'], J6[0], J6[1], 0, LIB], [d['u4'], P['SW'], U4[0], U4[1], 0, LIB], [d['r74'], P['R100K'], R74[0], R74[1], 270, LIB], @@ -153,16 +168,41 @@ def wiring(n, pins): w(top[0], top[1], top[0], Y_VO) w(bot[0], bot[1], bot[0], Y_GND) - # ---------- 【B】侧键顶针 ---------- - labels = ['POGO%d_PWR' % n, 'POGO%d_VUP' % n, 'POGO%d_VDN' % n, None] - for i in range(4): + # ---------- 【B】侧键顶针 + 按键 MOS ---------- + for i, key in enumerate(('PWR', 'VUP', 'VDN')): px, py = pins[d['pogo'][i]]['1'] - yy = POGO_PORT_Y[i] - w(px, py, px, yy) - if labels[i]: - PT.append(['BI', labels[i], px, yy, 180]) - else: - F.append(['Ground', 'GND', px, yy, 0]) + q = pins[d['q'][i]] + g, sr, dr = q['1'], q['2'], q['3'] # 2N7002：1=G 2=S 3=D（下面 build_page 里断言过） + assert px == dr[0] == sr[0] and dr[1] < py, (d['q'][i], q, px, py) + # 漏极 -> 顶针一根直线；POGO 端口挂在旁边一根 20 长的横支线末端（给 PCB 网络起名）。 + # ⚠️ 不能把端口放在直线的中点：两段共线导线会被 EasyEDA 合并成一段，端口就落在中段 = + # 真断线（skill §8a-2，2026-09-06 第一版就是这么被 port_audit 抓到 15 处的）。 + mid = dr[1] + 30 + w(dr[0], dr[1], px, py) + w(dr[0], mid, dr[0] + 20, mid) + PT.append(['BI', 'POGO%d_%s' % (n, key), dr[0] + 20, mid, 0]) + # 源极 -> 地 + w(sr[0], sr[1], sr[0], 300) + F.append(['Ground', 'GND', sr[0], 300, 0]) + # 栅极 <- 1k <- K 端口（从底下进来） + rg = pins[d['rg'][i]] + gt = max(rg.values(), key=lambda v: v[1]) + gb = min(rg.values(), key=lambda v: v[1]) + assert gt[0] == g[0] and gt[1] < g[1], (d['rg'][i], rg, g) + w(g[0], g[1], gt[0], gt[1]) + w(gb[0], gb[1], gb[0], 250) + PT.append(['IN', 'K%d_%s' % (n, key), gb[0], 250, 180]) + # 栅极 100k 下拉（复位期间 / 排针没插时不误按） + rp = pins[d['rp'][i]] + pt = max(rp.values(), key=lambda v: v[1]) + pb = min(rp.values(), key=lambda v: v[1]) + assert pt[0] < g[0] and pt[1] < g[1], (d['rp'][i], rp, g) + w(g[0], g[1], pt[0], g[1], pt[0], pt[1]) + w(pb[0], pb[1], pb[0], 300) + F.append(['Ground', 'GND', pb[0], 300, 0]) + px, py = pins[d['pogo'][3]]['1'] # J604 三键公共地 + w(px, py, px, 400) + F.append(['Ground', 'GND', px, 400, 0]) # ---------- 【C】EDL ---------- j, u = pins[d['j6']], pins[d['u4']] @@ -205,11 +245,11 @@ def wiring(n, pins): % names(n)['j8'], 10), (45, 772, u' %s 10k 代替保护板上的 NTC（模拟 25 °C），%s 68k 照抄保护板上的 ID 电阻，都对 P−。' % (names(n)['r78'], names(n)['r79']), 10), - (45, 470, u'【B】四根顶针顶主板反面的 J601~J604（§13.3）。J604 是三键公共地，', 10), - (45, 454, u' 直接接本路的电源返回地。驱动 MOS 在下板，这里只有顶针。', 10), - (45, 438, u'顶针 = YTC1P-2510-01（立创 C5221288）：自由高 3.5 / 行程 0.8 / 压到底 2.7 mm。', 10), - (45, 422, u' 配 3.0mm 立柱 → 压缩 0.5mm（62% 行程，约 62g），屏蔽罩净空 1.6mm。', 10), - (45, 406, u' 冠径只有 Ø0.9 球头，±1mm 落点公差靠首件实测校正（§22.3c / §22.3e）。', 10), + (45, 522, u'【B】四根顶针顶主板反面的 J601~J604（§13.3），J604 是三键公共地，直接接本路的电源返回地。按键 = MOS 把触点对地短接（主板上已串 1k）。', 10), + (45, 508, u' %s 2N7002 由 C6-KEYS 的 74HC595 驱动（K%d_PWR/VUP/VDN），栅极 1k 串阻 + 100k 下拉：复位期间 / 排针没插时不会误按（2026-09-06 从下板搬来，§26.23）。' + % ('/'.join(names(n)['q']), n), 10), + (45, 494, u' 顶针 YTC1P-2510-01（C5221288）：自由高 3.5 / 行程 0.8 / 压到底 2.7 mm；配 3.0mm 立柱压缩 0.5mm（62% 行程，约 62g），屏蔽罩净空 1.6mm。', 10), + (45, 480, u' 冠径只有 Ø0.9 球头，±1mm 落点公差靠首件实测校正（§22.3c / §22.3e）。', 10), (45, 205, u'【C】%s 是 1.25mm 2P 座，两根线焊到主板正面的 TP1204 / TP1205（§22.4）。' % names(n)['j6'], 10), (45, 189, u' %s 导通即短接两点 → 手机进 9008。串了 1.8k，短路电流只有 1mA。' @@ -332,6 +372,10 @@ return k; for k, v in want.items(): if got.get(k, '').upper().replace('VCC', 'V+') != v: bad.append(u'%s.%s 引脚名期望 %s 实测 %s' % (d['u4'], k, v, got.get(k))) + for qd in d['q']: + q = pins[qd] + if not (sorted(q) == ['1', '2', '3'] and q['1'][0] < q['2'][0] == q['3'][0] and q['2'][1] < q['1'][1] < q['3'][1]): + bad.append(u'%s 2N7002 引脚应是 1=G(左) 2=S(右下) 3=D(右上)，实测 %s' % (qd, q)) if bad: raise SystemExit(pname + u' 引脚核对失败：\n ' + '\n '.join(bad)) diff --git a/.claude/drc_read.py b/.claude/drc_read.py index 2d39fc9..aea8f32 100644 --- a/.claude/drc_read.py +++ b/.claude/drc_read.py @@ -43,7 +43,14 @@ sys.path.insert(0, HERE) from eda import run # 默认下板；载板加参数：/c/Python314/python .claude/drc_read.py --pcb2 -PCB = 'f126ffb29c92f9b2' if '--pcb2' in sys.argv else '7e9415a16a909c51' +# 2026-09-08：加 `--blade` / `--base` 跑 R2 的两块板（UUID 从 .claude/r2/r2-uuids.json 取） +if '--blade' in sys.argv or '--base' in sys.argv: + import json as _j, io as _io, os as _os + _u = _j.load(_io.open(_os.path.join(_os.path.dirname(_os.path.abspath(__file__)), + 'r2', 'r2-uuids.json'), encoding='utf-8')) + PCB = _u['boards']['BASE' if '--base' in sys.argv else 'BLADE']['pcb']['uuid'] +else: + PCB = '942ed1560d81c1e7' if '--pcb2' in sys.argv else '7e9415a16a909c51' JS_TREE = u""" await eda.dmt_EditorControl.openDocument('%s'); diff --git a/.claude/dump_pads.py b/.claude/dump_pads.py index 2140d2d..9f3606f 100644 --- a/.claude/dump_pads.py +++ b/.claude/dump_pads.py @@ -38,7 +38,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -# 默认下板；载板用 `python .claude/dump_pads.py f126ffb29c92f9b2 pcb2-copper.json` +# 默认下板；载板用 `python .claude/dump_pads.py 942ed1560d81c1e7 pcb2-copper.json` PCB = sys.argv[1] if len(sys.argv) > 1 else '7e9415a16a909c51' MIL = 39.3701 OUT = os.path.join(HERE, sys.argv[2] if len(sys.argv) > 2 else 'pcb-copper.json') diff --git a/.claude/eda-parts.json b/.claude/eda-parts.json index ce6fb6f..95926b9 100644 --- a/.claude/eda-parts.json +++ b/.claude/eda-parts.json @@ -1,6 +1,6 @@ { "_note": "EasyEDA 器件与工程 UUID 缓存。新会话直接用，不必重新 lib_Device.search。role 里带 ⚠️ 的是踩过的坑。P2 单路取值见设计文档 §16.2。⚠️ 作废：C25907(5.23k)、C25743(107k) 已被 C407675(5.49k)、C25755(150k) 取代，不要再用。 ⚠️ Board3(自制转接板) 已删除，改走方案 D：载板上放 BM24-50DS 座 + 原厂排线。 ⚠️ BM24 座子已改用个人库自建封装版 771dbf00…（见 parts.BM24-HRS-PIN），立创原件 C424561 的封装编号是错的。", - "_generated": "2026-09-05 夜：板对板连接器换件实施完毕 —— 下板 C55020601 公头 / 载板 C5307344 母座（对插 13.0mm、双双插装、公母同一套 IDC 奇偶式编号）。P5-BTB / C1-CONN 两页已重生成，载板 PCB 已重摆/重扇/重铺。", + "_generated": "2026-09-08：R2 底板 M3 新增 4 个器件（TCA9548APWR / NCP18XH103F03RB / PCIE-064-02-F-D-TH 插槽 / 1x5 排针），引脚坐标均为空页实测。", "library_uuid": "0819f05c4eef4c71ace90d822a990e87", "project": { "uuid": "1e5745f4caff4b15a921694d2fd912e4", @@ -107,7 +107,7 @@ "uuid": "9b2474b02bb94569a00ded395421ea45", "lib": "0819f05c4eef4c71ace90d822a990e87", "fp": "R0402", - "role": "R 4.7k 0402 — ⚠️ 曾误当 eFuse ILIM 用；TPS25940 的 R_ILIM 合法范围是 16.9~150k，4.7k 非法。现无用途" + "role": "R 4.7k 0402 — R2 刀片的 I²C 上拉（B2-CTRL 的 R40/R41，挂本槽 mux 分支）。⚠️ 曾误当 eFuse ILIM 用，那是非法的（合法范围 16.9~150k）" }, "C2653873": { "name": "TPS25940ARVCR", @@ -526,16 +526,6 @@ "lcsc": "C424561", "role": "J71~J75 实际用的就是这一条（2026-09-04 自建）。焊盘按 **Hirose 奇偶行编号**：奇数 1,3,5..49 在 +Y 排、偶数 2,4,6..50 在 −Y 排，1 脚在 −X 端；pin51 = 1/2 脚那端的电源触点(x=−6.03)，pin52 = 49/50 脚那端(x=+6.03)。几何来自 Hirose 官方样本反算，生成脚本 .claude/fp_bm24.py。⚠ 「哪一排是奇数排」还没有实证（§13.5 的 §MIRROR），打样前必须做那一次实测。" }, - "POGO-D1.9": { - "name": "YTC1P-2510-01 D1.9", - "uuid": "1c8e0ea1e66142a8860d6812b1dbe356", - "lib": "543725e8f0454017a5691e7e570aeef6", - "lib_note": "个人库", - "fp": "POGO-SMD1P_D1.9", - "fp_uuid": "2cbabda783f34133b4fe450e98f282bc", - "lcsc": "C5221288", - "role": "J41~J60 侧键顶针，**实际用的就是这一条**。立创原封装 SMD-1_BD2.0-H3.6 焊盘 Ø2.5，而小米8 四个侧键触点最近的一对（J601↔J604）只隔 2.217 mm → 焊盘会叠在一起把音量+ 永久短路。自建封装缩到 Ø1.9（净间距 0.317 mm）。法兰本来就只有 Ø2.0。见设计文档 §25.3。" - }, "C55020601": { "name": "AZ-PZ2.54-V11-2*20P", "uuid": "c0ab04240dc64fca8d6203d15f8a8a68", @@ -575,6 +565,123 @@ "lib": "0819f05c4eef4c71ace90d822a990e87", "fp": "R0402", "role": "R 68k 0402 — R79n 电池 ID 电阻（实测原保护板 ≈68k 对 P−）" + }, + "MI8-KEY-PAD": { + "name": "MI8-KEY-PAD D1.5", + "uuid": "1c8e0ea1e66142a8860d6812b1dbe356", + "lib": "543725e8f0454017a5691e7e570aeef6", + "lib_note": "个人库", + "fp": "PAD-D1.5_MI8-KEY", + "fp_uuid": "e106d85830014c088c1fba82f91a26f6", + "sym_uuid": "f524af799aa247f2b91e8f56171fa171", + "lcsc": "", + "role": "J41~J60 侧键触点盘。**2026-09-06 方案改**：顶针取消，改成和中框一样的焊盘 —— 螺丝把主板压在载板上（1 mm 间隙），主板自己的弹片直接压在这个裸铜盘上。器件 uuid 没变（就是原来那颗顶针器件改的），所以**原理图一个字没动**，符号也没换。封装 Ø1.5：四触点实测最小间距 1.78 mm，净距 0.28。⚠️ 旧的 POGO-SMD1P_D1.9 是按「最近一对 2.217 mm」缩的，在真实 1.78 下是负净距。⚠️ 器件属性里的 BOM 字段（Add into BOM=yes / C5221288 / YIYUAN）**API 改不动**，要在客户端手工改成不进 BOM 并清掉料号，否则会照着买 20 颗用不上的顶针。⚠️ 工艺：这是接触盘，**钢网开口 0（不上锡膏）**，表面处理走 ENIG。" + }, + "C15127": { + "name": "AO3401A_C15127", + "uuid": "be56508f80684877b262e15e4d50e175", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "SOT-23_L2.9-W1.3-P1.90-LS2.4-BR", + "role": "Q7 P-MOS 高边开关（风扇 FAN_12V_SW）。Vgs 绝对最大 ±12V ⇒ 必须配 DZ3 钳位。⚠ 封装名和 AO3400A 那颗不一样（SOT-23_ 不是 SOT-23-3_），H_FP 要单独加一条" + }, + "C2891776": { + "name": "BZT52C8V2", + "uuid": "46e19a04908e4d7f9d40ab2982f52315", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "SOD-123_L2.7-W1.6-LS3.7-RD-1", + "role": "DZ3 8.2V/500mW 稳压管，钳 Q7 的负 Vgs。K 接源极、A 接栅极；create(rot=90) 才是 K 上 A 下" + }, + "C25756": { + "name": "0402WGF1502TCE", + "uuid": "6d104587f1cd4b509c6a5fb272570507", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "R0402", + "role": "R 15k 0402 1% — 两路 TACH 接收的栅极串阻（10k 会让高电平不够）" + }, + "C2847671": { + "name": "2510-4A", + "uuid": "04ed497706104166a1f88dbf2d16083e", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "CONN-TH_4P-P2.54_CAX_2510-4A", + "role": "J26/J27 四线风扇座（直针 1x4P 2.54）。1=GND 2=FAN_12V_SW 3=TACH 4=PWM，与旧 3 针针序不同。塑壳 11.5mm，下板上只有两个上角和 y 68~92 放得下" + }, + "C116575": { + "name": "T491A226K010AT", + "uuid": "950f101b742e488fa85dafd0c53e49eb", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "CASE-A_3216", + "role": "C737 AMS1117-3.3 输出 22uF/10V **固态钽**（手册 §Stability 要求，陶瓷不算数）。⚠ **1 脚是正极**（rot 0 时在上），装配时钽的条纹 = 正极，别按铝电解的习惯" + }, + "PCIE-X4-EDGE-64P": { + "name": "PCIE-X4-EDGE-64P", + "uuid": "787309ccc49040b1b6383a339fd8c405", + "lib": "543725e8f0454017a5691e7e570aeef6", + "lib_note": "个人库，不是系统库 —— 放元件时 libraryUuid 要用这个", + "symbol": "1083524aa7614bde8c2394b7d1fe5bf3", + "role": "R2 刀片 J1：PCI-E x4 金手指（板边本身，不采购）。符号借自系统库 PCIE-064-02-F-D-TH，脚号 A1~A32 在左列（自上而下，pitch 10）、B1~B32 在右列，与 PCIe CEM 命名一一对应。⛔ 封装还没建（64 个板边焊盘，1.0 mm 间距，正反两面），属 M4 —— ✅ **T3 已定（2026-09-08）：做斜边 20°/1.0 mm，金手指区电镀硬金（不是 ENIG），板厚必须 1.6 mm**，所以现在可以开画。⚠ 斜边会吃掉手指前端约 1.0 mm 的镀层 ⇒ 金手指长度按 PCIe CEM 画，别自己缩短。" + }, + "C310990": { + "name": "F1206HC12A0TM", + "uuid": "507cd700b60b451caa0f3237e41baf6d", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "1206", + "role": "下板 / R2 底板 F1：12A 贴片保险丝（35V，分断 150A）。整机最坏 9.99A（设计文档 §22.6），⚠ 与刀片上那颗 F1（2A 慢断，T7 还是 10A 占位件 C310989）不是一回事，别搞混。" + }, + "C2570006": { + "name": "RHC2512FT2R00", + "uuid": "3c25870a08a64dc7b809655f380d8ce9", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "2512", + "role": "R9A~R9E：2Ω 2W 2512，5 颗串联 = 10Ω/10W 母线泄放电阻。高 0.8mm —— 原来的立式水泥电阻站起来超高度预算，才拆成 5 颗贴片。" + }, + "C9900017043": { + "name": "DC-005-5.5*2.5", + "uuid": "66ed565d4c984ace901de00bbc83af82", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "DC-005", + "role": "J1 圆形 DC 电源座（2026-09-08 用户拍板换掉 XT30PW-M，不降载）。脚 1 = 中心极正 → 保险丝；脚 2/3 = 负极静/动触点，两个都接地并联降接触电阻。⚠ 家族额定 2~5A 而整机最坏 9.99A —— 已知风险、用户明确接受，发热点在插头内芯与弹片的接触面，板上加铜救不了。" + }, + "C130026": { + "name": "TCA9548APWR", + "uuid": "98a0404e89ff4ecdb0427f14520ce65a", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "TSSOP-24_L7.8-W4.4-P0.65-LS6.4-BL", + "role": "U35 TCA9548A 8 通道 I²C 多路器（R2 底板，D8：一槽一路）。实测引脚（rot 0，相对中心）：左列自上而下 1 A0(-50,+55) 2 A1(+45) 3 RESET#(+35) 4 SD0(+25) 5 SC0(+15) 6 SD1(+5) 7 SC1(-5) 8 SD2(-15) 9 SC2(-25) 10 SD3(-35) 11 SC3(-45) 12 GND(-55)；右列自下而上 13 SD4(+50,-55) 14 SC4(-45) 15 SD5(-35) 16 SC5(-25) 17 SD6(-15) 18 SC6(-5) 19 SD7(+5) 20 SC7(+15) 21 A2(+25) 22 SCL(+35) 23 SDA(+45) 24 VCC(+55)。⚠ SD/SC 成对，通道 n 的 SDn/SCn 脚号相邻但**SD 在前 SC 在后**，别按 SCL/SDA 的习惯顺序接反。" + }, + "C13564": { + "name": "NCP18XH103F03RB", + "uuid": "26d83c83abc7457cb451b4cf76e659b1", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "R0603", + "role": "RT601/RT602 NTC 10k B=3380K 0603（R1 P3-CONTROL 原件，R2 挪到 A6-FAN）。两脚件，rot 0 时 1 在左(-20,0)、2 在右(+20,0)，无极性。" + }, + "C4597619": { + "name": "PCIE-064-02-F-D-TH", + "uuid": "3ea1a15bda65451a97a33a1549965ce3", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "插件 P=1mm（SAMTEC）", + "role": "J34~J38：R2 底板的 5 个 PCI-E x4 插槽。**符号与刀片 J1（PCIE-X4-EDGE-64P）同源**，脚号 A1~A32 在左列（-35，自上而下 pitch 10，A1 在 +155）、B1~B32 在右列（+35，同 y）。⛔ **T8 风险**：这是 SAMTEC 的贵料，客户端 lib_Device.search 够不着立创全库里那些几毛钱的PC 标准 PCI-E 4X 插槽（同 T7）。下单前必须换成便宜的同针位插槽并核对封装。" + }, + "C50951": { + "name": "2.54mm 1*5P 直排针", + "uuid": "e2ae8b0c17dd425aa2f9a1952b667332", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "HDR-TH_5P-P2.54", + "role": "J33 应急 UART 口（D13 的保命口：GND/TXD0/RXD0/EN/IO0）。rot 0 实测引脚全部朝左：1(-20,+20) 2(-20,+10) 3(-20,0) 4(-20,-10) 5(-20,-20)。位号前缀是 P?，放件后要显式 setState_Designator(\"J33\")。" + }, + "C19188869": { + "name": "PCIE-64P11L", + "uuid": "568ba50f7a8e4226aed9ac603b235162", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "PCIE-SMD_PCIE-64P11L", + "role": "J34~J38：R2 底板的 5 个 PCI-E x4 插槽（SOFNG 硕方，PCIE 64PIN 镀金加强 **贴片立式**）。2026-09-08 取代 SAMTEC PCIE-064-02-F-D-TH（C4597619）结掉 T8 —— 用户要 PC 标准便宜料。⚠ **脚号与刀片金手指不一样**：本符号的**脚号是 1~64**（脚名才是 A1~A32/B1~B32），而刀片 PCIE-X4-EDGE-64P 的脚号直接就是 A1~A32/B1~B32。换算：A(n) → 脚号 n，B(n) → 脚号 32+n。引脚**相对坐标与 Samtec 那颗完全一致**（A 排 x=-35、B 排 x=+35，y = 155-10*(n-1)），所以版图一个字没动。⚠ 还多一根 **65 脚 = 外壳/屏蔽，在 (0,+175)**（符号顶端正中），本项目接 GND。⛔ **贴片立式**：保持力只靠焊盘剪切，不如原来那颗直插 —— 五片刀片各驮一块手机主板，M4 布板时要给刀片加固定件（梳齿/压条），不能只靠插槽。" + }, + "C310998": { + "name": "F1206SB2000V063TM", + "uuid": "256f75e322a94be48a90613406f07457", + "lib": "0819f05c4eef4c71ace90d822a990e87", + "fp": "1206", + "role": "刀片 B1-POWER 的 F1：**2A 慢断**贴片保险丝（AEM，SB = Slow Blow），1206 / 63V / 分断 50A / 熔断 I²t = 0.63 A²s。2026-09-08 结掉 T7，取代同封装的 10A 占位件 C310989（F1206HC10A0TM）。⚠ **封装 uuid 与占位件不同**（bceff889… vs 66116fae…，10A/150A 分断那颗焊盘更大），刀片 PCB 还没布（M4），所以无影响；原理图侧的导线是按读回引脚坐标算的，自动跟随。⚠ 刀片满载约 1.45 A（16 W 手机 ÷ 92% ÷ 12 V）= 额定的 73%，正压在保险丝「连续 ≤75%」的降额线上，机箱内 40~50 ℃ 还要再降 ——要更大裕量就换 F1206SB2500V032TM（C310999，2.5A/32V/I²t 0.9）。⚠ 别和底板那两颗混：底板 F1 是 C310990 F1206HC12A0TM（12A，整机 9.99 A）。" } }, "schematic_boards": { @@ -586,7 +693,7 @@ }, "Board2": { "schematic": "302e115180aaa8fc", - "pcb": "f126ffb29c92f9b2", + "pcb": "942ed1560d81c1e7", "board": "c6594605c7cbe2b3", "role": "上板 载板(carrier)", "pages": { @@ -600,7 +707,8 @@ "C4-SITE5": "e58ef2c0a55e744a", "C5-J1401A": "967543b084075b4b", "C5-J1401B": "63413775cfc3aafc", - "C5-AUX": "b1ffbaef65ef82c9" + "C5-AUX": "b1ffbaef65ef82c9", + "C6-KEYS": "f44d1c8b0ad64fad" } } } diff --git a/.claude/mi8_mech.json b/.claude/mi8_mech.json index 1a4c95e..a8ae0c9 100644 --- a/.claude/mi8_mech.json +++ b/.claude/mi8_mech.json @@ -1,35 +1,35 @@ { "frame": "顶视，板左下角原点，mm", - "board_w": 67.09, - "board_h": 44.66, + "board_w": 44.0, + "board_h": 67.0, "holes": { "H1": [ - 54.2, - 42.3 + 1.4, + 9.9 ], "H2": [ - 2.6, - 38.2 + 0.7, + 27.3 ], "H3": [ - 61.9, - 33.7 + 1.7, + 38.7 ], "H4": [ - 62.1, - 29.2 + 41.9, + 1.9 ], "H5": [ - 2.6, - 27.0 + 57.4, + 41.2 ], "H6": [ - 4.0, - 10.8 + 64.6, + 28.1 ], "H7": [ - 42.6, - 3.7 + 64.8, + 32.4 ] }, "contacts_up": { @@ -71,5 +71,28 @@ 2.73, 4.38 ] - } + }, + "hole_d": 2.0, + "_source": "2026-09-06 测量底板扫描件反算（pcb2_measure_read.py，基准点单应，±0.5mm）。板长 67 = 裸板；描的轮廓 70.3 含 SIM 卡托伸出的 3.3mm（卡托在 u 大的那一端）", + "side_key_contacts": { + "PWR": [ + 4.72, + 5.16 + ], + "VUP": [ + 3.42, + 6.37 + ], + "VDN": [ + 3.49, + 3.74 + ], + "GND": [ + 2.05, + 4.99 + ] + }, + "_side_key_note": "2026-09-06 实测：中框金焊盘 + 7 孔配准反算，残差 0.57mm。菱形 相邻1.87/对角2.65，焊盘 Φ1.35。簇心 (3.42,5.07)，用户卡尺「H1 孔心到簇心 5mm」判死（另一条 2.88 的解已弃）。身份两条独立描述印证：GND 离短板边最近、PWR 与之正对、VDN 离长板边最近、VUP 次之。", + "frame_boss_to_pad_mm": 1.0, + "_frame_boss_note": "2026-09-06 用户实测：中框螺柱支撑面到侧键金焊盘面 1 mm = 载板面到主板贴合面该有的间隙" } \ No newline at end of file diff --git a/.claude/p5_btb.py b/.claude/p5_btb.py index 84703a2..35d73be 100644 --- a/.claude/p5_btb.py +++ b/.claude/p5_btb.py @@ -56,14 +56,23 @@ HDR = 'c0ab04240dc64fca8d6203d15f8a8a68' # C55020601 AZ-PZ2.54-V11-2*20P # 不是为了电流（2.8 A / 10 = 0.28 A/针），是为了**让它就近落地、 # 不必在 Inner1 上拉一条横贯全板的脊**（§25.10） # · GND 从 33 针减到 **26 针**，20 A 回流 = 0.77 A/针，仍很宽裕 +# ## 2026-09-06 第三版：74HC595 + 15 颗按键 MOS 整窝挪到载板（§26.23） +# +# 跨排针的不再是 15 条 `POGO*` + 5 条 `EDL_EN*` + `HUB_RST`（21 针）， +# 而是移位链的 4 根线 `KEY_SER` / `KEY_SRCLK` / `KEY_RCLK` / `KEY_OE#`。 +# 净腾 17 针，全部补成 GND（回流从 26 针加到 43 针）。 +# 4 根 KEY_* 放在 **J25 北排 3~6 行**（载板 x 139~147）：595 摆在载板走廊中段 +# （J31 与 J32 之间，x 110~133），从 J32 西端出线最近；下板这头 ESP32 在 (88,18)， +# U21/U22 腾出来之后 x 88~97 / y 35~55 整片是空的，四根线北上到 J25 西端没有障碍。 +# `POGO*` / `EDL_EN*` / `HUB_RST` 从此是**载板内部网络**。 J24 = [ ('VO1_P', 'GND'), ('VO1_P', 'GND'), ('VO1_P', 'GND'), # 1~3 -> site1(北) ('+5V', 'GND'), ('+5V', 'GND'), # 4~5 -> C701/U24(北) - ('POGO1_PWR', 'POGO4_PWR'), # 6~10 北=CH1 信号 - ('POGO1_VUP', 'POGO4_VUP'), # 南=CH4 信号 - ('POGO1_VDN', 'POGO4_VDN'), - ('EDL_EN1', 'EDL_EN4'), - ('VBUS_EN1', 'VBUS_EN4'), + ('GND', 'GND'), # 6~9 原 POGO1/POGO4/EDL_EN1/EDL_EN4， + ('GND', 'GND'), # 2026-09-06 随 595 上载板腾空 -> GND + ('GND', 'GND'), + ('GND', 'GND'), + ('VBUS_EN1', 'VBUS_EN4'), # 10 ('SDA', '+5V'), ('SCL', '+5V'), # 11~12 南=U27/C704(南) ('GND', 'UP_VBUS_DET'), # 13 R722 在底层 y62.2 ('GND', 'GND'), # 14 @@ -72,18 +81,16 @@ J24 = [ ] J25 = [ ('+5V', '+5V'), ('+5V', '+5V'), # 1~2 北->C702/U25 南->U28/C705 - ('POGO2_PWR', 'VBUS_EN5'), # 3~4 南=CH5 的两个使能 - ('POGO2_VUP', 'EDL_EN5'), # （U28/U45 就在 x133~136） - ('POGO2_VDN', 'GND'), - ('EDL_EN2', 'GND'), - ('VBUS_EN2', 'GND'), - ('HUB_RST', 'GND'), # 8 + ('KEY_SER', 'VBUS_EN5'), # 3~6 北=74HC595 移位链 4 根（原 POGO2_* / EDL_EN2） + ('KEY_SRCLK', 'GND'), # 南=CH5 的 VBUS 使能（原 EDL_EN5 -> GND） + ('KEY_RCLK', 'GND'), + ('KEY_OE#', 'GND'), + ('VBUS_EN2', 'GND'), # 7 + ('GND', 'GND'), # 8 原 HUB_RST -> 载板内部 ('GND', 'VO5_P'), ('GND', 'VO5_P'), ('GND', 'VO5_P'), # 9~11 -> site5(南) - ('POGO3_PWR', 'POGO5_PWR'), # 12~14 北=CH3 南=CH5 顶针 - ('POGO3_VUP', 'POGO5_VUP'), - ('POGO3_VDN', 'POGO5_VDN'), + ('GND', 'GND'), ('GND', 'GND'), ('GND', 'GND'), # 12~14 原 POGO3_* / POGO5_* -> GND ('VO3_P', 'GND'), ('VO3_P', 'GND'), ('VO3_P', 'GND'), # 15~17 -> site3(北) - ('EDL_EN3', 'GND'), ('VBUS_EN3', 'GND'), # 18~19 + ('GND', 'GND'), ('VBUS_EN3', 'GND'), # 18~19 原 EDL_EN3 -> GND ('+5V', '+5V'), # 20 -> C703/U26(北) ] @@ -166,7 +173,7 @@ def plan(): (60, 698, u'⚠ 北排喂北边的站、南排喂南边的站，一路都不许跨行 —— 4A 的电源面穿不过排母的地针行（缝里只剩 0.44mm 铜）。', 10), (60, 215, u'每路 VOn_P 用 3 针并联（4A / 3 = 1.33A 每针，母座额定 2.5A 每针），正对面 3 针地做本路回流（§15.4）。', 10), (60, 195, u'+5V 用 10 针、分散在两颗排母的南北四处：不是为了电流（0.28A 每针），是为了就近落地，免得在 Inner1 上拉一条横贯全板的脊。', 10), - (60, 175, u'合计 54 个信号 + 26 个地（20A 回流 = 0.77A 每针）。', 10), + (60, 175, u'合计 37 个信号 + 43 个地（2026-09-06 起：74HC595 + 按键 MOS 整窝在载板，跨板只剩 KEY_SER/SRCLK/RCLK/OE# 四根，§26.23）。', 10), (60, 155, u'对插高度 = 2.5 + 10.5 = 13.0mm（塑料对塑料定位），满足 §22.3d 的净空要求。', 10), (60, 135, u'⚠ 下板 C2/C3 罐高必须 <= 11.5mm，且 C2~C6 压在 J24 位置上、PCB 上要挪开（§22.3f）。', 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-50.03, 70.9, 70.9, "VO5_P"], ["22", 50.03, 49.97, 70.9, 70.9, "GND"], ["23", 150.03, -50.03, 70.9, 70.9, "GND"], ["24", 150.03, 49.97, 70.9, 70.9, "GND"], ["25", 250.03, -50.03, 70.9, 70.9, "GND"], ["26", 250.03, 49.97, 70.9, 70.9, "GND"], ["27", 350.03, -50.03, 70.9, 70.9, "GND"], ["28", 350.03, 49.97, 70.9, 70.9, "GND"], ["29", 450.03, -50.03, 70.9, 70.9, "GND"], ["30", 450.03, 49.97, 70.9, 70.9, "VO3_P"], ["31", 550.03, -50.03, 70.9, 70.9, "GND"], ["32", 550.03, 49.97, 70.9, 70.9, "VO3_P"], ["33", 650.03, -50.03, 70.9, 70.9, "GND"], ["34", 650.03, 49.97, 70.9, 70.9, "VO3_P"], ["35", 750.03, -50.03, 70.9, 70.9, "GND"], ["36", 750.03, 49.97, 70.9, 70.9, "GND"], ["37", 850.03, -50.03, 70.9, 70.9, "GND"], ["38", 850.03, 49.97, 70.9, 70.9, "VBUS_EN3"], ["39", 950.03, -50.03, 70.9, 70.9, "+5V"], ["40", 950.03, 49.97, 70.9, 70.9, "+5V"]]}, {"d": "DZ3", "x": 3917.32, "y": 4724.41, "rot": 0, "lay": 1, "fp": "SOD-123_L2.7-W1.6-LS3.7-RD-1", "n": 2, "bb": [-90.52000000000007, -18.710000000000218, 90.58000000000001, 18.68999999999978], "pads": [["2", 66.98, -0.01, 47.2, 37.4, "$17N208"], ["1", -66.92, -0.01, 47.2, 37.4, "+12V"]]}, {"d": "J26", "x": -940.94, "y": 4527.56, "rot": 0, "lay": 1, "fp": "CONN-TH_4P-P2.54_CAX_2510-4A", "n": 4, "bb": [-181.46000000000004, -31.460000000000036, 181.54000000000008, 31.539999999999964], "pads": [["1", -149.96, 0.04, 63, 63, "GND"], ["2", -49.96, 0.04, 63, 63, "FAN_12V_SW"], ["3", 50.04, 0.04, 63, 63, "FAN_IN_TACH_RAW"], ["4", 150.04, 0.04, 63, 63, "FAN_PWM_L"]]}, {"d": "J27", "x": 7240.16, "y": 4527.56, "rot": 0, "lay": 1, "fp": "CONN-TH_4P-P2.54_CAX_2510-4A", "n": 4, "bb": [-181.46000000000004, -31.460000000000036, 181.53999999999996, 31.539999999999964], "pads": [["1", -149.96, 0.04, 63, 63, "GND"], ["2", -49.96, 0.04, 63, 63, "FAN_12V_SW"], ["3", 50.04, 0.04, 63, 63, "FAN_OUT_TACH_RAW"], ["4", 150.04, 0.04, 63, 63, "FAN_PWM_L"]]}, {"d": "Q7", "x": 3740.16, "y": 4724.41, "rot": 0, "lay": 1, "fp": "SOT-23_L2.9-W1.3-P1.90-LS2.4-BR", "n": 3, "bb": [-64.95999999999977, -53.159999999999854, 64.94000000000024, 53.14000000000033], "pads": [["2", 45.24, 37.39, 39.4, 31.5, "+12V"], ["3", -45.26, -0.01, 39.4, 31.5, "FAN_12V_SW"], ["1", 45.24, -37.41, 39.4, 31.5, "$17N208"]]}, {"d": "Q8", "x": 3740.16, "y": 4566.93, "rot": 0, "lay": 1, "fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR", "n": 3, "bb": [-59.059999999999675, -50.23000000000029, 59.04000000000015, 50.16999999999989], "pads": [["1", 39.34, -37.43, 39.4, 25.6, "$17N212"], ["2", 39.34, 37.37, 39.4, 25.6, "GND"], ["3", -39.36, -0.03, 39.4, 25.6, "$17N210"]]}, {"d": "Q9", "x": -1023.6199999999997, "y": 4094.49, "rot": 0, "lay": 1, "fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR", "n": 3, "bb": [-59.08000000000034, -50.18999999999987, 59.11999999999962, 50.20999999999985], "pads": [["1", 39.42, -37.39, 39.4, 25.6, "$17N226"], ["2", 39.42, 37.41, 39.4, 25.6, "GND"], ["3", -39.38, 0.01, 39.4, 25.6, "FAN_TACH_IN"]]}, {"d": "Q10", "x": 7125.98, "y": 4094.49, "rot": 0, "lay": 1, "fp": "SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR", "n": 3, "bb": [-59.0799999999992, -50.18999999999987, 59.120000000000076, 50.20999999999985], "pads": [["1", 39.42, -37.39, 39.4, 25.6, "$17N233"], ["2", 39.42, 37.41, 39.4, 25.6, "GND"], ["3", -39.38, 0.01, 39.4, 25.6, "FAN_TACH_OUT"]]}, {"d": "R746", "x": 3582.68, "y": 4724.41, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.229999999999926, -10.660000000000219, 28.16999999999998, 10.639999999999782], "pads": [["2", 17.02, -0.01, 22.3, 21.3, "+12V"], ["1", -17.08, -0.01, 22.3, 21.3, "$17N208"]]}, {"d": "R747", "x": 3582.68, "y": 4566.93, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.229999999999926, -10.680000000000655, 28.16999999999998, 10.619999999999346], "pads": [["2", 17.02, -0.03, 22.3, 21.3, "$17N208"], ["1", -17.08, -0.03, 22.3, 21.3, "$17N210"]]}, {"d": "R748", "x": 3917.32, "y": 4566.93, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.16999999999998, -10.680000000000655, 28.229999999999926, 10.619999999999346], "pads": [["2", 17.08, -0.03, 22.3, 21.3, "$17N212"], ["1", -17.02, -0.03, 22.3, 21.3, "FAN_EN"]]}, {"d": "R749", "x": 4055.12, "y": 4566.93, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.16999999999998, -10.680000000000655, 28.229999999999926, 10.619999999999346], "pads": [["2", 17.08, -0.03, 22.3, 21.3, "$17N212"], ["1", -17.02, -0.03, 22.3, 21.3, "GND"]]}, {"d": "R750", "x": -1023.6200000000002, "y": 4251.97, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.229999999999812, -10.620000000000255, 28.170000000000208, 10.679999999999746], "pads": [["2", 17.02, 0.03, 22.3, 21.3, "FAN_12V_SW"], ["1", -17.08, 0.03, 22.3, 21.3, "FAN_IN_TACH_RAW"]]}, {"d": "R751", "x": -826.7699999999996, "y": 4251.97, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.180000000000312, -10.620000000000255, 28.219999999999594, 10.679999999999746], "pads": [["2", 17.07, 0.03, 22.3, 21.3, "FAN_IN_TACH_RAW"], ["1", -17.03, 0.03, 22.3, 21.3, "$17N226"]]}, {"d": "R752", "x": -826.7699999999996, "y": 4094.49, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.180000000000312, -10.639999999999782, 28.219999999999594, 10.660000000000219], "pads": [["2", 17.07, 0.01, 22.3, 21.3, "$17N226"], ["1", -17.03, 0.01, 22.3, 21.3, "GND"]]}, {"d": "R753", "x": -1023.6199999999997, "y": 3937.01, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.23000000000038, -10.660000000000219, 28.16999999999964, 10.639999999999782], "pads": [["2", 17.02, -0.01, 22.3, 21.3, "+3V3"], ["1", -17.08, -0.01, 22.3, 21.3, "FAN_TACH_IN"]]}, {"d": "R754", "x": 7125.98, "y": 4251.97, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.229999999999926, -10.620000000000255, 28.170000000000435, 10.679999999999746], "pads": [["2", 17.02, 0.03, 22.3, 21.3, "FAN_12V_SW"], ["1", -17.08, 0.03, 22.3, 21.3, "FAN_OUT_TACH_RAW"]]}, {"d": "R755", "x": 7322.83, "y": 4251.97, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.179999999999744, -10.620000000000255, 28.219999999999708, 10.679999999999746], "pads": [["2", 17.07, 0.03, 22.3, 21.3, "FAN_OUT_TACH_RAW"], ["1", -17.03, 0.03, 22.3, 21.3, "$17N233"]]}, {"d": "R756", "x": 7322.83, "y": 4094.49, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.179999999999744, -10.639999999999782, 28.219999999999708, 10.660000000000219], "pads": [["2", 17.07, 0.01, 22.3, 21.3, "$17N233"], ["1", -17.03, 0.01, 22.3, 21.3, "GND"]]}, {"d": "R757", "x": 7125.98, "y": 3937.01, "rot": 0, "lay": 1, "fp": "R0402", "n": 2, "bb": [-28.229999999999926, -10.660000000000219, 28.170000000000435, 10.639999999999782], "pads": [["2", 17.02, -0.01, 22.3, 21.3, "+3V3"], ["1", -17.08, -0.01, 22.3, 21.3, "FAN_TACH_OUT"]]}, {"d": "J1", "x": 9448.818959999999, "y": 1574.80316, "rot": 0, "lay": 1, "fp": "DC-IN-TH_DC-005-2", "n": 3, "bb": [-149.61895999999797, -124.00315999999998, 149.58104000000094, 167.29684000000003], "pads": [["3", 19.681, -92.503, 141.7, 63, "GND"], ["2", -118.119, 92.497, 63, 149.6, "GND"], ["1", 118.081, 92.497, 63, 149.6, "$1N223"]]}] \ No newline at end of file diff --git a/.claude/pcb1_env.py b/.claude/pcb1_env.py index bbd2913..49b898a 100644 --- a/.claude/pcb1_env.py +++ b/.claude/pcb1_env.py @@ -25,7 +25,9 @@ from eda import run DX, DY = 30.0, 5.0 # 下板原点在载板坐标里的位置 GAP = 13.0 # 两板净空 MARGIN = 1.0 # 装配余量 -BW, BH = 160.0, 125.0 +# 2026-09-07：跟 pcb1_place 一起改成真板框（220x135，左下角 (-30,-5)）。 +BX0, BY0, BX1, BY1 = -30.0, -5.0, 190.0, 130.0 +BW, BH = BX1 - BX0, BY1 - BY0 LANE_H = 1.0 # 排线（0.2 厚）+ 走线余量，按 1 mm 算 @@ -37,7 +39,7 @@ def shift(x0, y0, x1, y1): def clip(r): u"""裁到下板板框内；完全在框外返回 None。""" x0 = max(r[0], 0.0); y0 = max(r[1], 0.0) - x1 = min(r[2], BW); y1 = min(r[3], BH) + x1 = min(r[2], BX1); y1 = min(r[3], BY1) if x1 <= x0 or y1 <= y0: return None return [round(x0, 2), round(y0, 2), round(x1, 2), round(y1, 2)] @@ -54,7 +56,7 @@ def header_anchors(): pads = json.load(io.open(os.path.join(HERE, 'pcb2-header-pads.json'), encoding='utf-8'))['pads'] nets = {} r = run(""" -await eda.dmt_EditorControl.openDocument('f126ffb29c92f9b2'); +await eda.dmt_EditorControl.openDocument('942ed1560d81c1e7'); await new Promise(r=>setTimeout(r,2000)); const out = {}; for (const c of await eda.pcb_PrimitiveComponent.getAll()) { @@ -116,7 +118,7 @@ def build(): data = { 'frame': u'下板 PCB1 坐标系 mm，原点左下角，Y 向上。下板坐标 = 载板坐标 − (30,5)。' u'hmax = 该矩形内下板元件允许的最大高度 = 13(净空) − h(载板底面元件) − 1(余量)', - 'gap': GAP, 'board': [BW, BH], + 'gap': GAP, 'board': [BW, BH], 'board_rect': [BX0, BY0, BX1, BY1], 'anchors': anchors, 'zones': zones, 'lanes': lanes, 'slots': slots, } out = os.path.join(HERE, 'pcb1-env.json') diff --git a/.claude/pcb1_escape_audit.py b/.claude/pcb1_escape_audit.py index e33032f..8a99258 100644 --- a/.claude/pcb1_escape_audit.py +++ b/.claude/pcb1_escape_audit.py @@ -156,11 +156,18 @@ def main(): pours = R.pour_rects() obstacles = R.obstacles_of(pads, vias, lines, pours) js = R.jobs(pads, want, skip=() if want else R.SKIP) + # ⚠️ 2026-09-06 起 `route_sig` 把出线段也下发了 —— 布不通的焊盘在板上是 + # 「一个焊盘 + 一小截自己的出线段」，不再是光焊盘。只认光焊盘会报「0 个」。 + # 出线段全长 ≤ 1.2 mm、没有过孔的碎片，一样当孤立焊盘审。 need = set() for net, frags in js: for fr in frags: - if len(fr['pads']) == 1 and not fr['vias'] and not fr['lines']: - need.add(fr['pads'][0]['tag']) + if len(fr['pads']) != 1 or fr['vias']: + continue + q = fr['pads'][0] + if all(max(math.hypot(l['x0'] - q['x'], l['y0'] - q['y']), + math.hypot(l['x1'] - q['x'], l['y1'] - q['y'])) <= 1.2 for l in fr['lines']): + need.add(q['tag']) order = [n for n, _f in js] stubs, alts = R.plan_stubs(order, pads, obstacles, need) audit.stubs = stubs diff --git a/.claude/pcb1_i2c_l3.py b/.claude/pcb1_i2c_l3.py index b430932..c1e7165 100644 --- a/.claude/pcb1_i2c_l3.py +++ b/.claude/pcb1_i2c_l3.py @@ -70,7 +70,10 @@ E = RS.E # 引擎（polish / _l_shapes / board_mask 从这 #: **但 2026-09-06 试着加进来没跑通**：它板上的铜整片都在顶层、且集中在控制块那一带， #: 六条连线里有四条报「L2 源0 / L16 源0」—— 主碎片周围一个合法孔位都没有，扎不下去。 #: 要挪它得先把控制块那一带的顶层拆开，不是改这一行的事。 -NETS = ('SCL', 'SDA') +NETS = ('SCL', 'SDA', 'BUCK_PG') +# ── 侧键模拟线 POGO3_PWR / POGO3_VDN / POGO4_VDN / POGO5_PWR / POGO5_VUP（第二十六轮加） +# 2026-09-06 随 74HC595 + 按键 MOS 整窝挪到载板（§26.23）之后，下板上不再有 POGO* 网络， +# 已从候选表拿掉；它们在 Inner2 上的铜由 pcb_prune_nets.py 一并清掉了。 L_TOP, L_BOT, L3 = 1, 2, 16 LAYS = (L_TOP, L_BOT, L3) @@ -108,6 +111,14 @@ CLUSTERS = { 'U12': (121.5, 45.5, 129.5, 52.5), # CH5 INA226 'U13': (3.0, 90.5, 11.0, 100.0), # 输入侧 INA226 'J24': (30.0, 60.5, 38.5, 67.0), # 排针（通孔针，L3 上直接落脚） + # 五路 Buck 控制器：`BUCK_PG` 在 U*.14 上。**不划框的话整条出线短线也被拆掉**， + # 而那几个脚在 0.5 mm 脚距的 QFN 上，`entry_stub` 重建不回来 ⇒ 整个网络断成 6 片 + # （2026-09-06 实测，连通性保险当场拦下）。框只罩住芯片本体 + 0.6 mm。 + 'U1': (14.4, 25.1, 19.2, 29.9), + 'U2': (48.7, 95.6, 53.5, 100.4), + 'U3': (137.1, 95.6, 141.9, 100.4), + 'U4': (46.1, 25.1, 50.9, 29.9), + 'U5': (125.6, 25.1, 130.4, 29.9), } @@ -964,6 +975,8 @@ def main(): pads, vias, lines = NL.geom(refresh) print(u'板上：焊盘 %d / 过孔 %d / 走线 %d' % (len(pads), len(vias), len(lines))) + # ⚠️ 只拆**这一轮要动的**网络（`--net` 限定时尤其重要） + globals()['NETS'] = tuple(nets) keep_l, drop_l, keep_v, drop_v = split_old(pads, vias, lines) dlen = sum(math.hypot(lines[i]['x1'] - lines[i]['x0'], lines[i]['y1'] - lines[i]['y0']) for i in drop_l) @@ -1016,7 +1029,48 @@ def main(): if worse: # ⚠️ 这条保险是必需的：本脚本会把这些网络在簇框外的铜**全部拆掉**重来。 # 拆得动、重连不上的话，板子会比动手之前更差，而净距校核照样全绿。 - sys.exit(u'⛔ %s 的连通性变差了 —— 不下发' % ' / '.join(worse)) + # + # 但**不要因此把整轮毙掉** —— `NETS` 是一张「候选表」，里面难免有挪不动的 + # （2026-09-06 实测 `BUCK_PG`：五个分支要去板子四角，而 L3 上 y<34 往东 + # 只剩 x115~116 那条 1.0 mm 缝，`+12V` 把别的通道全占了）。 + # 把变差的那几个**踢出去重算一遍**，剩下的照常下发。 + print(u' → %s 挪进内层会变差，踢出候选表重算一轮' % ' / '.join(worse)) + keep = [n for n in nets if n not in worse] + if not keep: + sys.exit(u'⛔ 候选表里一个都留不下 —— 不下发') + # ⚠️ **拆除清单必须跟着重算**。第一版只换了 `run_plan` 的网络表， + # 而 `drop_l/drop_v` 还是按完整候选表算的 ⇒ `--push` 会把被踢掉那个网络的 + # 铜删掉、又不给它重布，板子直接变差（净距校核照样全绿）。 + globals()['NETS'] = tuple(keep) + keep_l, drop_l, keep_v, drop_v = split_old(pads, vias, lines) + vlines, vvias = virtual(pads, vias, lines, drop_l, drop_v) + print(u' 重算后要拆：%d 段 / %d 孔（%d 个网络）' + % (len(drop_l), len(drop_v), len(keep))) + del BLOCK[:] + routes = run_plan(pads, vvias, vlines, keep) + routes = chamfer(routes, pads, vvias, vlines) + msgs, _r = plane_report(routes, pads_raw, obs_board) + for m in msgs: + print(u' ⚠️ ' + m) + if msgs: + sys.exit(u'⛔ 重算之后仍有孤岛 —— 不下发') + summarize(routes) + bad = verify(routes, pads, vvias, vlines) + for b in bad[:20]: + print(u' ✗ ' + b) + if bad: + sys.exit(u'⛔ 重算之后校核不过 —— 不下发') + nets = keep + worse2 = [] + for net, n, det in connectivity(routes, pads, vvias, vlines): + was = len(frags(net, pads, vias, lines)) + print(u' 连通性 %s：%d 个碎片 %s%s' + % (net, n, det if n > 1 else u'✅', + u'' if n <= was else u' ⛔ 仍然变差')) + if n > was and net in keep: + worse2.append(net) + if worse2: + sys.exit(u'⛔ %s 重算之后仍然变差 —— 不下发' % ' / '.join(worse2)) if not push: print(u'\n（只算不下发。要下发加 --push）') return diff --git a/.claude/pcb1_import.py b/.claude/pcb1_import.py index a4bf6f6..7761592 100644 --- a/.claude/pcb1_import.py +++ b/.claude/pcb1_import.py @@ -1,191 +1,200 @@ -# -*- coding: utf-8 -*- -u"""下板 PCB1「从原理图导入变更」。 - -用法: - python .claude/pcb1_import.py --bom 逐页重抓原理图 BOM，存 _p1_sch_bom.json（对账的基准） - python .claude/pcb1_import.py --probe 只开对话框、把全部变更行读出来存 _p1_import_rows.json - python .claude/pcb1_import.py --apply 读完之后真的点「应用修改」（先自动取消勾选「包含设计规则」） - python .claude/pcb1_import.py --verify 拿 PCB 上的元件表和 _p1_sch_bom.json 对账 - -⚠️ **改过原理图就要先 `--bom` 再 `--verify`**，否则是拿新 PCB 和旧原理图对账 —— - 刚改的那几个位号会被报成「PCB 有原理图没有」，而真正的错混在里面看不出来。 - （2026-09-06 之前 `_p1_sch_bom.json` 在仓库里根本没有生产者，只能手工维护。） - -⚠️ skill §9o：整页重画过的页（P5-BTB / P6-FAN-EDL）元件 UUID 全是新的， - EasyEDA 会把 PCB 上**将被删掉的**元件复用成新元件（改封装 + 改位号）， - 所以导入后必须跑 --verify 核对「位号 ↔ 封装」是不是和原理图一致。 -""" -import io, json, os, re, sys, time -HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) -from eda import run - -PCB = '7e9415a16a909c51' - -HELPERS = u""" -const sleep = ms => new Promise(r => setTimeout(r, ms)); -const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; -const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const p=propsOf(t); if(p&&typeof p.onClick==='function'){p.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; -const nat = b => { const o={bubbles:true,cancelable:true,view:window,button:0}; - for (const t of ['pointerdown','mousedown','pointerup','mouseup','click']) - b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o)); }; -const leaf = (txt) => { for (const el of document.querySelectorAll('*')) if (el.children.length===0 && (el.textContent||'').trim()===txt && el.offsetParent!==null) return el; return null; }; -""" - -JS_PROBE = HELPERS + u""" -await eda.dmt_EditorControl.openDocument('%s'); -await sleep(1800); -const out = {}; -fire(leaf('设计')); await sleep(900); -out.opened = fire(leaf('从原理图导入变更')); -await sleep(9000); -let sc = null; -for (const el of document.querySelectorAll('div')) - if (el.scrollHeight > el.clientHeight + 20 && /移除元件|增加元件|修改/.test(el.innerText || '')) - if (!sc || el.innerText.length < sc.innerText.length) sc = el; -const seq = []; -if (sc) { - sc.scrollTop = 0; await sleep(400); - let last = -1; - for (let i = 0; i < 200; i++) { - seq.push({top: sc.scrollTop, txt: sc.innerText}); - if (sc.scrollTop === last) break; - last = sc.scrollTop; - if (sc.scrollTop + sc.clientHeight >= sc.scrollHeight - 2) break; - sc.scrollTop += Math.max(40, sc.clientHeight / 2); - await sleep(260); - } -} -out.seq = seq; -out.buttons = [...document.querySelectorAll('button')].filter(b => b.offsetParent !== null).map(b => (b.innerText||'').trim()).filter(Boolean); -return out; -""" % PCB - -JS_APPLY = HELPERS + u""" -const out = {}; -let ruleBox = null, ruleTxt = null; -for (const el of document.querySelectorAll('*')) { - if (el.children.length === 0 && /设计规则/.test((el.textContent||'').trim()) && el.offsetParent !== null) { - ruleTxt = (el.textContent||'').trim(); - let r = el; - for (let i = 0; i < 6 && r; i++) { const cb = r.querySelector && r.querySelector('input[type=checkbox]'); if (cb) { ruleBox = cb; break; } r = r.parentElement; } - break; - } -} -out.ruleTxt = ruleTxt; out.ruleChecked = ruleBox ? ruleBox.checked : null; -if (ruleBox && ruleBox.checked) { nat(ruleBox); await sleep(500); out.ruleAfter = ruleBox.checked; } -const btn = [...document.querySelectorAll('button')].find(b => b.offsetParent !== null && (b.innerText||'').trim() === '应用修改'); -if (!btn) return Object.assign(out, {err: 'no 应用修改'}); -nat(btn); -await sleep(15000); -for (const b of document.querySelectorAll('button')) if (b.offsetParent !== null && /^(确定|确认|是)$/.test((b.innerText||'').trim())) { nat(b); await sleep(4000); out.confirmed = (b.innerText||'').trim(); } -await sleep(4000); -const comps = await eda.pcb_PrimitiveComponent.getAll(); -out.n = comps.length; -out.buttons = [...document.querySelectorAll('button')].filter(b => b.offsetParent !== null).map(b => (b.innerText||'').trim()).filter(Boolean).slice(0,20); -return out; -""" - -JS_DUMP = u""" -// ⚠️ skill §9l：每段会读/改文档的 JS 都要自己 openDocument。 -// 少了这一行，紧跟在 --bom（最后停在某张原理图上）之后跑 --verify， -// `pcb_PrimitiveComponent.getAll()` 在原理图文档上直接抛 -// `Cannot read properties of null (reading 'map')` —— 报错信息完全指不到根因。 -await eda.dmt_EditorControl.openDocument('7e9415a16a909c51'); -await new Promise(r => setTimeout(r, 1800)); -const cs = await eda.pcb_PrimitiveComponent.getAll(); -const out = []; -for (const c of cs) out.push({d: c.designator, x: c.x, y: c.y, rot: c.rotation, lay: c.layer, - fp: (c.footprint && c.footprint.name) ? c.footprint.name : (c.footprint || null)}); -return out; -""" - -JS_BOM = u""" -const sleep = ms => new Promise(r => setTimeout(r, ms)); -await eda.dmt_EditorControl.openDocument('%s'); -await sleep(1300); -const cur = String((await eda.dmt_Schematic.getCurrentSchematicPageInfo()).name || ''); -if (cur.toUpperCase() !== '%s') return {err: 'openDocument 打到了 ' + cur}; -const list = []; -for (const c of await eda.sch_PrimitiveComponent.getAll()) { - if (c.getState_ComponentType() !== 'part') continue; - let fp = null; - try { const f = c.getState_Footprint(); if (f) fp = {name: String(f.name || f)}; } catch (e) {} - list.push({d: String(c.getState_Designator ? c.getState_Designator() : ''), - uuid: c.getState_PrimitiveId(), fp: fp}); -} -return {list: list}; -""" - - -def refresh_bom(): - u"""逐页重抓原理图 BOM。 - - ⚠️ **一页一个请求**，不要一次抓 11 页 —— `eda.py` 把返回值截到 20000 字符再打印， - 整本 BOM 装不下，截断之后 `json.load` 直接炸在中间（2026-09-06 踩过）。 - """ - pages = json.load(io.open(os.path.join(HERE, 'eda-parts.json'), encoding='utf-8'))['pages'] - bom, bad = {}, [] - for name, uuid in pages.items(): - r = run(JS_BOM % (uuid, name.upper()), timeout=300) - if not r.get('success'): - bad.append(u'%s: %s' % (name, json.dumps(r, ensure_ascii=False)[:160])) - continue - res = r['result'] - if res.get('err'): - bad.append(u'%s: %s' % (name, res['err'])) - continue - bom[name] = res['list'] - print(u' %-12s %3d 件' % (name, len(res['list']))) - if bad: - print(u'❌ 这几页没抓到，**没有写缓存**：') - for b in bad: - print(u' · ' + b) - sys.exit(1) - io.open(os.path.join(HERE, '_p1_sch_bom.json'), 'w', encoding='utf-8').write( - json.dumps(bom, ensure_ascii=False)) - print(u'已写 _p1_sch_bom.json：%d 页 / %d 件' % (len(bom), sum(len(v) for v in bom.values()))) - - -def dump(): - r = run(JS_DUMP, timeout=300) - if not r.get('success'): sys.exit(json.dumps(r, ensure_ascii=False)[:600]) - return r['result'] - -def verify(): - cs = dump() - io.open(os.path.join(HERE, '_pcb1_comps.json'), 'w', encoding='utf-8').write(json.dumps(cs, ensure_ascii=False)) - bom = json.load(io.open(os.path.join(HERE, '_p1_sch_bom.json'), encoding='utf-8')) - sch = {} - for pg, v in bom.items(): - for c in v: - d = c.get('d') - if d and re.match(r'^[A-Za-z]+\d', d): - sch[d] = ((c.get('fp') or {}).get('name'), pg) - pcb = {c['d']: c for c in cs} - miss = sorted(set(sch) - set(pcb)); extra = sorted(set(pcb) - set(sch)) - bad = [(d, pcb[d]['fp'], sch[d][0]) for d in sorted(set(sch) & set(pcb)) if pcb[d]['fp'] != sch[d][0]] - print(u'PCB %d 件 / 原理图 %d 件' % (len(cs), len(sch))) - print(u'原理图有 PCB 没有 %d: %s' % (len(miss), miss[:40])) - print(u'PCB 有原理图没有 %d: %s' % (len(extra), extra[:40])) - print(u'封装对不上 %d:' % len(bad)) - for t in bad[:40]: print(u' %s PCB=%s SCH=%s' % t) - return not (miss or extra or bad) - -if __name__ == '__main__': - a = sys.argv[1] if len(sys.argv) > 1 else '--verify' - if a == '--bom': - refresh_bom() - elif a == '--probe': - r = run(JS_PROBE, timeout=400) - if not r.get('success'): sys.exit(json.dumps(r, ensure_ascii=False)[:800]) - res = r['result'] - io.open(os.path.join(HERE, '_p1_import_rows.json'), 'w', encoding='utf-8').write(json.dumps(res, ensure_ascii=False, indent=1)) - print(u'opened=%s 快照 %d 屏' % (res.get('opened'), len(res.get('seq') or []))) - print(res.get('buttons')) - elif a == '--apply': - r = run(JS_APPLY, timeout=400) - print(json.dumps(r, ensure_ascii=False)[:1200]) - elif a == '--verify': - sys.exit(0 if verify() else 1) - else: - sys.exit(__doc__) +# -*- coding: utf-8 -*- +u"""下板 PCB1「从原理图导入变更」。 + +用法: + python .claude/pcb1_import.py --bom 逐页重抓原理图 BOM，存 _p1_sch_bom.json（对账的基准） + python .claude/pcb1_import.py --probe 只开对话框、把全部变更行读出来存 _p1_import_rows.json + python .claude/pcb1_import.py --apply 读完之后真的点「应用修改」（先自动取消勾选「包含设计规则」） + python .claude/pcb1_import.py --verify 拿 PCB 上的元件表和 _p1_sch_bom.json 对账 + +⚠️ **改过原理图就要先 `--bom` 再 `--verify`**，否则是拿新 PCB 和旧原理图对账 —— + 刚改的那几个位号会被报成「PCB 有原理图没有」，而真正的错混在里面看不出来。 + （2026-09-06 之前 `_p1_sch_bom.json` 在仓库里根本没有生产者，只能手工维护。） + +⚠️ skill §9o：整页重画过的页（P5-BTB / P6-FAN-EDL）元件 UUID 全是新的， + EasyEDA 会把 PCB 上**将被删掉的**元件复用成新元件（改封装 + 改位号）， + 所以导入后必须跑 --verify 核对「位号 ↔ 封装」是不是和原理图一致。 +""" +import io, json, os, re, sys, time +HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) +from eda import run + +PCB = '7e9415a16a909c51' +# 2026-09-06：加 `--board2` 就对载板 PCB2 做同一套事（BOM / 对话框 / 对账），产出文件带 _p2_ 前缀 +BOARD2 = '--board2' in sys.argv +if BOARD2: + PCB = '942ed1560d81c1e7' + sys.argv = [a for a in sys.argv if a != '--board2'] +BOM_FILE = '_p2_sch_bom.json' if BOARD2 else '_p1_sch_bom.json' +COMPS_FILE = '_pcb2_comps.json' if BOARD2 else '_pcb1_comps.json' +ROWS_FILE = '_p2_import_rows.json' if BOARD2 else '_p1_import_rows.json' + +HELPERS = u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const p=propsOf(t); if(p&&typeof p.onClick==='function'){p.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +const nat = b => { const o={bubbles:true,cancelable:true,view:window,button:0}; + for (const t of ['pointerdown','mousedown','pointerup','mouseup','click']) + b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o)); }; +const leaf = (txt) => { for (const el of document.querySelectorAll('*')) if (el.children.length===0 && (el.textContent||'').trim()===txt && el.offsetParent!==null) return el; return null; }; +""" + +JS_PROBE = HELPERS + u""" +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(1800); +const out = {}; +fire(leaf('设计')); await sleep(900); +out.opened = fire(leaf('从原理图导入变更')); +await sleep(9000); +let sc = null; +for (const el of document.querySelectorAll('div')) + if (el.scrollHeight > el.clientHeight + 20 && /移除元件|增加元件|修改/.test(el.innerText || '')) + if (!sc || el.innerText.length < sc.innerText.length) sc = el; +const seq = []; +if (sc) { + sc.scrollTop = 0; await sleep(400); + let last = -1; + for (let i = 0; i < 200; i++) { + seq.push({top: sc.scrollTop, txt: sc.innerText}); + if (sc.scrollTop === last) break; + last = sc.scrollTop; + if (sc.scrollTop + sc.clientHeight >= sc.scrollHeight - 2) break; + sc.scrollTop += Math.max(40, sc.clientHeight / 2); + await sleep(260); + } +} +out.seq = seq; +out.buttons = [...document.querySelectorAll('button')].filter(b => b.offsetParent !== null).map(b => (b.innerText||'').trim()).filter(Boolean); +return out; +""" % PCB + +JS_APPLY = HELPERS + u""" +const out = {}; +let ruleBox = null, ruleTxt = null; +for (const el of document.querySelectorAll('*')) { + if (el.children.length === 0 && /设计规则/.test((el.textContent||'').trim()) && el.offsetParent !== null) { + ruleTxt = (el.textContent||'').trim(); + let r = el; + for (let i = 0; i < 6 && r; i++) { const cb = r.querySelector && r.querySelector('input[type=checkbox]'); if (cb) { ruleBox = cb; break; } r = r.parentElement; } + break; + } +} +out.ruleTxt = ruleTxt; out.ruleChecked = ruleBox ? ruleBox.checked : null; +if (ruleBox && ruleBox.checked) { nat(ruleBox); await sleep(500); out.ruleAfter = ruleBox.checked; } +const btn = [...document.querySelectorAll('button')].find(b => b.offsetParent !== null && (b.innerText||'').trim() === '应用修改'); +if (!btn) return Object.assign(out, {err: 'no 应用修改'}); +nat(btn); +await sleep(15000); +for (const b of document.querySelectorAll('button')) if (b.offsetParent !== null && /^(确定|确认|是)$/.test((b.innerText||'').trim())) { nat(b); await sleep(4000); out.confirmed = (b.innerText||'').trim(); } +await sleep(4000); +const comps = await eda.pcb_PrimitiveComponent.getAll(); +out.n = comps.length; +out.buttons = [...document.querySelectorAll('button')].filter(b => b.offsetParent !== null).map(b => (b.innerText||'').trim()).filter(Boolean).slice(0,20); +return out; +""" + +JS_DUMP = u""" +// ⚠️ skill §9l：每段会读/改文档的 JS 都要自己 openDocument。 +// 少了这一行，紧跟在 --bom（最后停在某张原理图上）之后跑 --verify， +// `pcb_PrimitiveComponent.getAll()` 在原理图文档上直接抛 +// `Cannot read properties of null (reading 'map')` —— 报错信息完全指不到根因。 +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 1800)); +const cs = await eda.pcb_PrimitiveComponent.getAll(); +const out = []; +for (const c of cs) out.push({d: c.designator, x: c.x, y: c.y, rot: c.rotation, lay: c.layer, + fp: (c.footprint && c.footprint.name) ? c.footprint.name : (c.footprint || null)}); +return out; +""" % PCB + +JS_BOM = u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(1300); +const cur = String((await eda.dmt_Schematic.getCurrentSchematicPageInfo()).name || ''); +if (cur.toUpperCase() !== '%s') return {err: 'openDocument 打到了 ' + cur}; +const list = []; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + if (c.getState_ComponentType() !== 'part') continue; + let fp = null; + try { const f = c.getState_Footprint(); if (f) fp = {name: String(f.name || f)}; } catch (e) {} + list.push({d: String(c.getState_Designator ? c.getState_Designator() : ''), + uuid: c.getState_PrimitiveId(), fp: fp}); +} +return {list: list}; +""" + + +def refresh_bom(): + u"""逐页重抓原理图 BOM。 + + ⚠️ **一页一个请求**，不要一次抓 11 页 —— `eda.py` 把返回值截到 20000 字符再打印， + 整本 BOM 装不下，截断之后 `json.load` 直接炸在中间（2026-09-06 踩过）。 + """ + ep = json.load(io.open(os.path.join(HERE, 'eda-parts.json'), encoding='utf-8')) + pages = ep['schematic_boards']['Board2']['pages'] if BOARD2 else ep['pages'] + bom, bad = {}, [] + for name, uuid in pages.items(): + r = run(JS_BOM % (uuid, name.upper()), timeout=300) + if not r.get('success'): + bad.append(u'%s: %s' % (name, json.dumps(r, ensure_ascii=False)[:160])) + continue + res = r['result'] + if res.get('err'): + bad.append(u'%s: %s' % (name, res['err'])) + continue + bom[name] = res['list'] + print(u' %-12s %3d 件' % (name, len(res['list']))) + if bad: + print(u'❌ 这几页没抓到，**没有写缓存**：') + for b in bad: + print(u' · ' + b) + sys.exit(1) + io.open(os.path.join(HERE, BOM_FILE), 'w', encoding='utf-8').write( + json.dumps(bom, ensure_ascii=False)) + print(u'已写 ' + BOM_FILE + u'：%d 页 / %d 件' % (len(bom), sum(len(v) for v in bom.values()))) + + +def dump(): + r = run(JS_DUMP, timeout=300) + if not r.get('success'): sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + return r['result'] + +def verify(): + cs = dump() + io.open(os.path.join(HERE, COMPS_FILE), 'w', encoding='utf-8').write(json.dumps(cs, ensure_ascii=False)) + bom = json.load(io.open(os.path.join(HERE, BOM_FILE), encoding='utf-8')) + sch = {} + for pg, v in bom.items(): + for c in v: + d = c.get('d') + if d and re.match(r'^[A-Za-z]+\d', d): + sch[d] = ((c.get('fp') or {}).get('name'), pg) + pcb = {c['d']: c for c in cs} + miss = sorted(set(sch) - set(pcb)); extra = sorted(set(pcb) - set(sch)) + bad = [(d, pcb[d]['fp'], sch[d][0]) for d in sorted(set(sch) & set(pcb)) if pcb[d]['fp'] != sch[d][0]] + print(u'PCB %d 件 / 原理图 %d 件' % (len(cs), len(sch))) + print(u'原理图有 PCB 没有 %d: %s' % (len(miss), miss[:40])) + print(u'PCB 有原理图没有 %d: %s' % (len(extra), extra[:40])) + print(u'封装对不上 %d:' % len(bad)) + for t in bad[:40]: print(u' %s PCB=%s SCH=%s' % t) + return not (miss or extra or bad) + +if __name__ == '__main__': + a = sys.argv[1] if len(sys.argv) > 1 else '--verify' + if a == '--bom': + refresh_bom() + elif a == '--probe': + r = run(JS_PROBE, timeout=400) + if not r.get('success'): sys.exit(json.dumps(r, ensure_ascii=False)[:800]) + res = r['result'] + io.open(os.path.join(HERE, ROWS_FILE), 'w', encoding='utf-8').write(json.dumps(res, ensure_ascii=False, indent=1)) + print(u'opened=%s 快照 %d 屏' % (res.get('opened'), len(res.get('seq') or []))) + print(res.get('buttons')) + elif a == '--apply': + r = run(JS_APPLY, timeout=400) + print(json.dumps(r, ensure_ascii=False)[:1200]) + elif a == '--verify': + sys.exit(0 if verify() else 1) + else: + sys.exit(__doc__) diff --git a/.claude/pcb1_netlist.py b/.claude/pcb1_netlist.py index 60717ab..4eaa4a2 100644 --- a/.claude/pcb1_netlist.py +++ b/.claude/pcb1_netlist.py @@ -1,307 +1,313 @@ -# -*- coding: utf-8 -*- -u"""下板 PCB1：按**实测铜**算全板每个网络的连通性，列出还欠哪些连接。 - - /c/Python314/python .claude/pcb1_netlist.py # 全板汇总 - /c/Python314/python .claude/pcb1_netlist.py --net +5V # 只看这几个网络 - /c/Python314/python .claude/pcb1_netlist.py --todo # 只列还没连通的，按「要拉几条」排序 - /c/Python314/python .claude/pcb1_netlist.py --refresh # 重抓板上快照（改过板就要加） - /c/Python314/python .claude/pcb1_netlist.py --json out.json # 把待布线任务写成文件 - -## 为什么不看 DRC 的「连接性错误」 - -那一支是按**对象**列的（一个没连上的焊盘可能报好几条），还分页、还要 reload 才准， -数字（594）说明不了「还剩几条线要拉」。这里把焊盘 / 过孔 / 走线 / **实测铺铜** -当成图的节点，两两相触连边，数连通域 —— 一个网络 k 个连通域就是**还差 k−1 条线**。 - -## 铺铜怎么进这张图（关键） - -铺铜不是一个矩形，它是一堆环、还带反焊盘的洞，而且**一个铺铜对象可能铺出好几块**。 -所以照 `pcb1_pour.verify()` 的老办法：把同 (网络, 层) 的环光栅化成 0.25 mm 的布尔格、 -连通域标号，**每一个连通域各算一个节点**。落脚判据和那里一致： -过孔 / 通孔焊盘落在格子里就算连上；贴片焊盘只在本层（Top/Bottom）算。 - -⚠️ 走线**不**算落进铺铜（异网铺铜会被挖开，同网铺铜和走线重叠才算）， - 这里按「走线中点/端点落在本网铺铜格子里」判，偏保守一点没关系 —— - 保守的方向是「多报几条要拉的线」，不是「少报」。 -""" -import io -import json -import math -import os -import sys - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) - -import pcb1_pour as PO # noqa: E402 - -G = PO.G -EPS = 1e-6 -LAYNAME = {1: 'Top', 2: 'Bottom', 15: 'Inner1', 16: 'Inner2'} - - -# ══════════════════ 几何：点/段/矩形 ══════════════════ -def seg_pt(x0, y0, x1, y1, px, py): - dx, dy = x1 - x0, y1 - y0 - d2 = dx * dx + dy * dy - t = 0.0 if d2 < EPS else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / d2)) - return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) - - -def seg_seg(a0, a1, b0, b1): - def cross(o, a, b): - return (a[0] - o[0]) * (b[1] - o[1]) - (a[1] - o[1]) * (b[0] - o[0]) - d1, d2 = cross(b0, b1, a0), cross(b0, b1, a1) - d3, d4 = cross(a0, a1, b0), cross(a0, a1, b1) - if ((d1 > 0) != (d2 > 0)) and ((d3 > 0) != (d4 > 0)): - return 0.0 - return min(seg_pt(a0[0], a0[1], a1[0], a1[1], b0[0], b0[1]), - seg_pt(a0[0], a0[1], a1[0], a1[1], b1[0], b1[1]), - seg_pt(b0[0], b0[1], b1[0], b1[1], a0[0], a0[1]), - seg_pt(b0[0], b0[1], b1[0], b1[1], a1[0], a1[1])) - - -def seg_rect(p0, p1, cx, cy, hw, hh): - u"""线段到轴对齐矩形的距离（重叠返回 0）。""" - corners = [(cx - hw, cy - hh), (cx + hw, cy - hh), (cx + hw, cy + hh), (cx - hw, cy + hh)] - for p in (p0, p1): - if abs(p[0] - cx) <= hw + EPS and abs(p[1] - cy) <= hh + EPS: - return 0.0 - best = 1e9 - for k in range(4): - best = min(best, seg_seg(p0, p1, corners[k], corners[(k + 1) % 4])) - return best - - -# ══════════════════ 读板 ══════════════════ -def geom(refresh=False): - u"""返回 (pads, vias, lines)，全部 mm。 - - pads: dict(net,x,y,hw,hh,th,ref,num,plane) plane = 元件所在层（1/2） - vias: dict(net,x,y,r) - lines: dict(net,lay,x0,y0,x1,y1,w) - """ - snap = PO.snapshot(refresh) - raw, _n, _nb = PO.load_pads(False) - pads = [] - for net, x, y, hx, hy, th, tag, plane in raw: - ref, _, num = tag.rpartition('.') - pads.append(dict(net=net, x=x, y=y, hw=hx, hh=hy, th=th, - ref=ref, num=num, plane=plane, tag=tag)) - vias = [dict(net=n or '', x=x, y=y, r=(od or 0.61) / 2.0) - for n, x, y, od in snap.get('via', ())] - lines = [dict(net=n or '', lay=lay, x0=x0, y0=y0, x1=x1, y1=y1, w=w or 0.2) - for n, lay, x0, y0, x1, y1, w in snap.get('line', ())] - return pads, vias, lines - - -def pour_grids(refresh=False): - u"""同 (网络, 层) 的实测铺铜 -> 一个 `Grid`（已经标好连通域）。""" - if refresh or not os.path.exists(PO.FILLS): - d = PO.call(PO.JS_FILLS, timeout=900) - io.open(PO.FILLS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) - else: - d = json.load(io.open(PO.FILLS, encoding='utf-8')) - rings = {} - for e in d['pours']: - rings.setdefault((e['net'], e['layer']), []).extend(e['rings']) - return {k: PO._grid_from_cells(k[0], k[1], PO._cells_from_rings(v)) - for k, v in rings.items()} - - -def layers_of_pad(p): - return (1, 2, 15, 16) if p['th'] else (p['plane'],) - - -# ══════════════════ 连通性 ══════════════════ -class DSU(object): - def __init__(self, n): - self.p = list(range(n)) - - def find(self, i): - while self.p[i] != i: - self.p[i] = self.p[self.p[i]] - i = self.p[i] - return i - - def union(self, a, b): - a, b = self.find(a), self.find(b) - if a != b: - self.p[a] = b - - -def analyze(net, pads, vias, lines, pgrids): - u"""返回 (items, groups)。items 是 (kind, layers:set, obj, label)。""" - items = [] - for p in pads: - if p['net'] == net: - items.append(('pad', set(layers_of_pad(p)), p, p['tag'])) - for v in vias: - if v['net'] == net: - items.append(('via', set((1, 2, 15, 16)), v, u'过孔(%.2f,%.2f)' % (v['x'], v['y']))) - for l in lines: - if l['net'] == net: - items.append(('line', set((l['lay'],)), l, u'')) - # 铺铜：每个连通域一个节点 - pour_nodes = [] - for (pnet, lay), g in pgrids.items(): - if pnet != net: - continue - for cid, npx in g.sizes.items(): - pour_nodes.append((lay, g, cid)) - items.append(('pour', set((lay,)), (lay, g, cid), - u'%s 铺铜 %.0fmm²' % (LAYNAME[lay], npx * G * G))) - n = len(items) - dsu = DSU(n) - - def in_pour(node, x, y, hw, hh, lay): - u"""焊盘 / 过孔 / 线段的**外框**有没有碰到这一块铺铜。 - - ⚠️ 不能只测中心那一格：EasyEDA 回读的环里，**同网通孔焊盘的位置是一个洞** - （铜直连时那个洞正好等于焊盘轮廓，焊盘自己把它填上）。按中心格判， - J22.2 / J22.3 / J24.1 这三个明明坐在整块 GND 平面里的通孔脚会被判成孤立 - —— 2026-09-06 实测就是这么被骗过一次。 - 判据照 `pcb1_pour.Grid.hit()`：**外框覆盖到的格子里有一格属于这一块**。 - """ - play, g, cid = node - if play != lay: - return False - i0, i1 = int((x - hw) / G), int((x + hw) / G) + 1 - j0, j1 = int((y - hh) / G), int((y + hh) / G) + 1 - for j in range(max(0, j0), min(g.ny, j1 + 1)): - for i in range(max(0, i0), min(g.nx, i1 + 1)): - if g.lab[j][i] == cid: - return True - return False - - def touch(a, b): - ka, la, oa, _ = a - kb, lb, ob, _ = b - common = la & lb - if not common: - return False - if ka == 'pour' or kb == 'pour': - if ka != 'pour': - a, b = b, a - ka, la, oa, _x = a - kb, lb, ob, _y = b - lay = oa[0] - if kb == 'pad': - # 贴片焊盘只在自己那一层算落脚；通孔焊盘哪一层都算 - if not (ob['th'] or ob['plane'] == lay): - return False - return in_pour(oa, ob['x'], ob['y'], ob['hw'], ob['hh'], lay) - if kb == 'via': - return in_pour(oa, ob['x'], ob['y'], ob['r'], ob['r'], lay) - if kb == 'line': - if ob['lay'] != lay: - return False - n_ = max(2, int(math.hypot(ob['x1'] - ob['x0'], ob['y1'] - ob['y0']) / 0.2) + 1) - h_ = ob['w'] / 2.0 - for s in range(n_ + 1): - t = s / float(n_) - if in_pour(oa, ob['x0'] + t * (ob['x1'] - ob['x0']), - ob['y0'] + t * (ob['y1'] - ob['y0']), h_, h_, lay): - return True - return False - return False # pour-pour：同层不同连通域，本来就不通 - if ka == 'line' and kb == 'line': - return seg_seg((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), - (ob['x0'], ob['y0']), (ob['x1'], ob['y1'])) \ - <= (oa['w'] + ob['w']) / 2 + EPS - if ka == 'line' and kb == 'pad': - return seg_rect((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), - ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['w'] / 2 + EPS - if ka == 'line' and kb == 'via': - return seg_pt(oa['x0'], oa['y0'], oa['x1'], oa['y1'], - ob['x'], ob['y']) <= oa['w'] / 2 + ob['r'] + EPS - if ka == 'via' and kb == 'via': - return math.hypot(oa['x'] - ob['x'], oa['y'] - ob['y']) <= oa['r'] + ob['r'] + EPS - if ka == 'via' and kb == 'pad': - return abs(oa['x'] - ob['x']) <= ob['hw'] + oa['r'] + EPS \ - and abs(oa['y'] - ob['y']) <= ob['hh'] + oa['r'] + EPS - if ka == 'pad' and kb == 'pad': - return (abs(oa['x'] - ob['x']) <= oa['hw'] + ob['hw'] + EPS - and abs(oa['y'] - ob['y']) <= oa['hh'] + ob['hh'] + EPS) - return touch(b, a) - - for i in range(n): - for j in range(i + 1, n): - if touch(items[i], items[j]): - dsu.union(i, j) - groups = {} - for i in range(n): - groups.setdefault(dsu.find(i), []).append(i) - return items, list(groups.values()) - - -def main(): - argv = sys.argv[1:] - refresh = '--refresh' in argv - todo_only = '--todo' in argv - want = [] - if '--net' in argv: - want = [a for a in argv[argv.index('--net') + 1:] if not a.startswith('--')] - outjson = None - if '--json' in argv: - outjson = argv[argv.index('--json') + 1] - - pads, vias, lines = geom(refresh) - pgrids = pour_grids(refresh) - print(u'板上：%d 焊盘 / %d 过孔 / %d 走线 / %d 组铺铜' - % (len(pads), len(vias), len(lines), len(pgrids))) - - nets = {} - for p in pads: - if p['net']: - nets.setdefault(p['net'], 0) - nets[p['net']] += 1 - todo, done, single = [], 0, 0 - tasks = [] - for net in sorted(nets): - if want and net not in want: - continue - if nets[net] < 2: - single += 1 - continue - items, groups = analyze(net, pads, vias, lines, pgrids) - # 只含走线的碎片不算「要连的点」（它一定挂在别的东西上，否则是垃圾线） - real = [g for g in groups - if any(items[i][0] != 'line' for i in g)] - if len(real) <= 1: - done += 1 - continue - frags = [] - for g in sorted(real, key=lambda g: -len(g)): - labs = [items[i][3] for i in g if items[i][3]] - pts = [] - for i in g: - k, _l, o, _lab = items[i] - if k == 'pad': - pts.append((o['x'], o['y'], sorted(layers_of_pad(o)), o['tag'])) - elif k == 'via': - pts.append((o['x'], o['y'], [1, 2, 15, 16], 'via')) - frags.append(dict(n=len(g), labels=labs, pts=pts)) - todo.append((len(real) - 1, net, nets[net], frags)) - tasks.append(dict(net=net, npads=nets[net], need=len(real) - 1, frags=frags)) - - todo.sort(key=lambda t: (-t[0], t[1])) - print(u'\n---- 还没连通的网络：%d 个，共欠 %d 条连接 ----' - % (len(todo), sum(t[0] for t in todo))) - for need, net, npads, frags in todo: - print(u' %-14s %3d 焊盘 %2d 个碎片 -> 还差 %2d 条' % (net, npads, len(frags), need)) - if not todo_only: - for f in frags[:8]: - labs = f['labels'][:10] - print(u' [%2d] %s%s' % (f['n'], u' '.join(labs), - u' …' if len(f['labels']) > 10 else u'')) - print(u'\n已连通 %d 个网络 / 单焊盘网络 %d 个' % (done, single)) - if outjson: - io.open(outjson, 'w', encoding='utf-8').write( - json.dumps(tasks, ensure_ascii=False, indent=1)) - print(u'待布线任务已写到 %s' % outjson) - return 0 - - -if __name__ == '__main__': - sys.exit(main()) +# -*- coding: utf-8 -*- +u"""下板 PCB1：按**实测铜**算全板每个网络的连通性，列出还欠哪些连接。 + + /c/Python314/python .claude/pcb1_netlist.py # 全板汇总 + /c/Python314/python .claude/pcb1_netlist.py --net +5V # 只看这几个网络 + /c/Python314/python .claude/pcb1_netlist.py --todo # 只列还没连通的，按「要拉几条」排序 + /c/Python314/python .claude/pcb1_netlist.py --refresh # 重抓板上快照（改过板就要加） + /c/Python314/python .claude/pcb1_netlist.py --json out.json # 把待布线任务写成文件 + +## 为什么不看 DRC 的「连接性错误」 + +那一支是按**对象**列的（一个没连上的焊盘可能报好几条），还分页、还要 reload 才准， +数字（594）说明不了「还剩几条线要拉」。这里把焊盘 / 过孔 / 走线 / **实测铺铜** +当成图的节点，两两相触连边，数连通域 —— 一个网络 k 个连通域就是**还差 k−1 条线**。 + +## 铺铜怎么进这张图（关键） + +铺铜不是一个矩形，它是一堆环、还带反焊盘的洞，而且**一个铺铜对象可能铺出好几块**。 +所以照 `pcb1_pour.verify()` 的老办法：把同 (网络, 层) 的环光栅化成 0.25 mm 的布尔格、 +连通域标号，**每一个连通域各算一个节点**。落脚判据和那里一致： +过孔 / 通孔焊盘落在格子里就算连上；贴片焊盘只在本层（Top/Bottom）算。 + +⚠️ 走线**不**算落进铺铜（异网铺铜会被挖开，同网铺铜和走线重叠才算）， + 这里按「走线中点/端点落在本网铺铜格子里」判，偏保守一点没关系 —— + 保守的方向是「多报几条要拉的线」，不是「少报」。 +""" +import io +import json +import math +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) + +import pcb1_pour as PO # noqa: E402 + +G = PO.G +EPS = 1e-6 +LAYNAME = {1: 'Top', 2: 'Bottom', 15: 'Inner1', 16: 'Inner2'} + + +# ══════════════════ 几何：点/段/矩形 ══════════════════ +def seg_pt(x0, y0, x1, y1, px, py): + dx, dy = x1 - x0, y1 - y0 + d2 = dx * dx + dy * dy + t = 0.0 if d2 < EPS else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / d2)) + return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + + +def seg_seg(a0, a1, b0, b1): + def cross(o, a, b): + return (a[0] - o[0]) * (b[1] - o[1]) - (a[1] - o[1]) * (b[0] - o[0]) + d1, d2 = cross(b0, b1, a0), cross(b0, b1, a1) + d3, d4 = cross(a0, a1, b0), cross(a0, a1, b1) + if ((d1 > 0) != (d2 > 0)) and ((d3 > 0) != (d4 > 0)): + return 0.0 + return min(seg_pt(a0[0], a0[1], a1[0], a1[1], b0[0], b0[1]), + seg_pt(a0[0], a0[1], a1[0], a1[1], b1[0], b1[1]), + seg_pt(b0[0], b0[1], b1[0], b1[1], a0[0], a0[1]), + seg_pt(b0[0], b0[1], b1[0], b1[1], a1[0], a1[1])) + + +def seg_rect(p0, p1, cx, cy, hw, hh): + u"""线段到轴对齐矩形的距离（重叠返回 0）。""" + corners = [(cx - hw, cy - hh), (cx + hw, cy - hh), (cx + hw, cy + hh), (cx - hw, cy + hh)] + for p in (p0, p1): + if abs(p[0] - cx) <= hw + EPS and abs(p[1] - cy) <= hh + EPS: + return 0.0 + best = 1e9 + for k in range(4): + best = min(best, seg_seg(p0, p1, corners[k], corners[(k + 1) % 4])) + return best + + +# ══════════════════ 读板 ══════════════════ +def geom(refresh=False): + u"""返回 (pads, vias, lines)，全部 mm。 + + pads: dict(net,x,y,hw,hh,th,ref,num,plane) plane = 元件所在层（1/2） + vias: dict(net,x,y,r) + lines: dict(net,lay,x0,y0,x1,y1,w) + """ + snap = PO.snapshot(refresh) + raw, _n, _nb = PO.load_pads(False) + pads = [] + for net, x, y, hx, hy, th, tag, plane in raw: + ref, _, num = tag.rpartition('.') + pads.append(dict(net=net, x=x, y=y, hw=hx, hh=hy, th=th, + ref=ref, num=num, plane=plane, tag=tag)) + vias = [dict(net=n or '', x=x, y=y, r=(od or 0.61) / 2.0) + for n, x, y, od in snap.get('via', ())] + lines = [dict(net=n or '', lay=lay, x0=x0, y0=y0, x1=x1, y1=y1, w=w or 0.2) + for n, lay, x0, y0, x1, y1, w in snap.get('line', ())] + return pads, vias, lines + + +def pour_grids(refresh=False): + u"""同 (网络, 层) 的实测铺铜 -> 一个 `Grid`（已经标好连通域）。""" + if refresh or not os.path.exists(PO.FILLS): + d = PO.call(PO.JS_FILLS, timeout=900) + io.open(PO.FILLS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) + else: + d = json.load(io.open(PO.FILLS, encoding='utf-8')) + rings = {} + for e in d['pours']: + rings.setdefault((e['net'], e['layer']), []).extend(e['rings']) + return {k: PO._grid_from_cells(k[0], k[1], PO._cells_from_rings(v)) + for k, v in rings.items()} + + +def layers_of_pad(p): + return (1, 2, 15, 16) if p['th'] else (p['plane'],) + + +# ══════════════════ 连通性 ══════════════════ +class DSU(object): + def __init__(self, n): + self.p = list(range(n)) + + def find(self, i): + while self.p[i] != i: + self.p[i] = self.p[self.p[i]] + i = self.p[i] + return i + + def union(self, a, b): + a, b = self.find(a), self.find(b) + if a != b: + self.p[a] = b + + +def analyze(net, pads, vias, lines, pgrids): + u"""返回 (items, groups)。items 是 (kind, layers:set, obj, label)。""" + items = [] + for p in pads: + if p['net'] == net: + items.append(('pad', set(layers_of_pad(p)), p, p['tag'])) + for v in vias: + if v['net'] == net: + items.append(('via', set((1, 2, 15, 16)), v, u'过孔(%.2f,%.2f)' % (v['x'], v['y']))) + for l in lines: + if l['net'] == net: + items.append(('line', set((l['lay'],)), l, u'')) + # 铺铜：每个连通域一个节点 + pour_nodes = [] + for (pnet, lay), g in pgrids.items(): + if pnet != net: + continue + for cid, npx in g.sizes.items(): + pour_nodes.append((lay, g, cid)) + items.append(('pour', set((lay,)), (lay, g, cid), + u'%s 铺铜 %.0fmm²' % (LAYNAME[lay], npx * G * G))) + n = len(items) + dsu = DSU(n) + + def in_pour(node, x, y, hw, hh, lay): + u"""焊盘 / 过孔 / 线段的**外框**有没有碰到这一块铺铜。 + + ⚠️ 不能只测中心那一格：EasyEDA 回读的环里，**同网通孔焊盘的位置是一个洞** + （铜直连时那个洞正好等于焊盘轮廓，焊盘自己把它填上）。按中心格判， + J22.2 / J22.3 / J24.1 这三个明明坐在整块 GND 平面里的通孔脚会被判成孤立 + —— 2026-09-06 实测就是这么被骗过一次。 + 判据照 `pcb1_pour.Grid.hit()`：**外框覆盖到的格子里有一格属于这一块**。 + """ + play, g, cid = node + if play != lay: + return False + # ⚠️ 必须走 pcb1_pour 的 gi/gj —— 板框左下角是 (−30, −5)，不是 (0, 0)。 + # 2026-09-08 踩过：pcb1_pour 把 BW/BH 从假板框 160×125 改成真板框 220×135 + # 并加了 BX0/BY0 之后，这里还在 `int(x / G)`，坐标整体偏了 30 mm —— + # 表现是「靠平面连通的网络（+12V/GND/+3V3/VOn_P）忽然全部碎成几十片」， + # 而 pcb1_pour --verify 回读的实测铺铜完全健康。**两边对不上时信实测那一边。** + # 更贵的是 pcb1_orphan_cu 走的就是这套栅格，据此误删过 12 个好过孔。 + i0, i1 = PO.gi(x - hw), PO.gi(x + hw) + 1 + j0, j1 = PO.gj(y - hh), PO.gj(y + hh) + 1 + for j in range(max(0, j0), min(g.ny, j1 + 1)): + for i in range(max(0, i0), min(g.nx, i1 + 1)): + if g.lab[j][i] == cid: + return True + return False + + def touch(a, b): + ka, la, oa, _ = a + kb, lb, ob, _ = b + common = la & lb + if not common: + return False + if ka == 'pour' or kb == 'pour': + if ka != 'pour': + a, b = b, a + ka, la, oa, _x = a + kb, lb, ob, _y = b + lay = oa[0] + if kb == 'pad': + # 贴片焊盘只在自己那一层算落脚；通孔焊盘哪一层都算 + if not (ob['th'] or ob['plane'] == lay): + return False + return in_pour(oa, ob['x'], ob['y'], ob['hw'], ob['hh'], lay) + if kb == 'via': + return in_pour(oa, ob['x'], ob['y'], ob['r'], ob['r'], lay) + if kb == 'line': + if ob['lay'] != lay: + return False + n_ = max(2, int(math.hypot(ob['x1'] - ob['x0'], ob['y1'] - ob['y0']) / 0.2) + 1) + h_ = ob['w'] / 2.0 + for s in range(n_ + 1): + t = s / float(n_) + if in_pour(oa, ob['x0'] + t * (ob['x1'] - ob['x0']), + ob['y0'] + t * (ob['y1'] - ob['y0']), h_, h_, lay): + return True + return False + return False # pour-pour：同层不同连通域，本来就不通 + if ka == 'line' and kb == 'line': + return seg_seg((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), + (ob['x0'], ob['y0']), (ob['x1'], ob['y1'])) \ + <= (oa['w'] + ob['w']) / 2 + EPS + if ka == 'line' and kb == 'pad': + return seg_rect((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), + ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['w'] / 2 + EPS + if ka == 'line' and kb == 'via': + return seg_pt(oa['x0'], oa['y0'], oa['x1'], oa['y1'], + ob['x'], ob['y']) <= oa['w'] / 2 + ob['r'] + EPS + if ka == 'via' and kb == 'via': + return math.hypot(oa['x'] - ob['x'], oa['y'] - ob['y']) <= oa['r'] + ob['r'] + EPS + if ka == 'via' and kb == 'pad': + return abs(oa['x'] - ob['x']) <= ob['hw'] + oa['r'] + EPS \ + and abs(oa['y'] - ob['y']) <= ob['hh'] + oa['r'] + EPS + if ka == 'pad' and kb == 'pad': + return (abs(oa['x'] - ob['x']) <= oa['hw'] + ob['hw'] + EPS + and abs(oa['y'] - ob['y']) <= oa['hh'] + ob['hh'] + EPS) + return touch(b, a) + + for i in range(n): + for j in range(i + 1, n): + if touch(items[i], items[j]): + dsu.union(i, j) + groups = {} + for i in range(n): + groups.setdefault(dsu.find(i), []).append(i) + return items, list(groups.values()) + + +def main(): + argv = sys.argv[1:] + refresh = '--refresh' in argv + todo_only = '--todo' in argv + want = [] + if '--net' in argv: + want = [a for a in argv[argv.index('--net') + 1:] if not a.startswith('--')] + outjson = None + if '--json' in argv: + outjson = argv[argv.index('--json') + 1] + + pads, vias, lines = geom(refresh) + pgrids = pour_grids(refresh) + print(u'板上：%d 焊盘 / %d 过孔 / %d 走线 / %d 组铺铜' + % (len(pads), len(vias), len(lines), len(pgrids))) + + nets = {} + for p in pads: + if p['net']: + nets.setdefault(p['net'], 0) + nets[p['net']] += 1 + todo, done, single = [], 0, 0 + tasks = [] + for net in sorted(nets): + if want and net not in want: + continue + if nets[net] < 2: + single += 1 + continue + items, groups = analyze(net, pads, vias, lines, pgrids) + # 只含走线的碎片不算「要连的点」（它一定挂在别的东西上，否则是垃圾线） + real = [g for g in groups + if any(items[i][0] != 'line' for i in g)] + if len(real) <= 1: + done += 1 + continue + frags = [] + for g in sorted(real, key=lambda g: -len(g)): + labs = [items[i][3] for i in g if items[i][3]] + pts = [] + for i in g: + k, _l, o, _lab = items[i] + if k == 'pad': + pts.append((o['x'], o['y'], sorted(layers_of_pad(o)), o['tag'])) + elif k == 'via': + pts.append((o['x'], o['y'], [1, 2, 15, 16], 'via')) + frags.append(dict(n=len(g), labels=labs, pts=pts)) + todo.append((len(real) - 1, net, nets[net], frags)) + tasks.append(dict(net=net, npads=nets[net], need=len(real) - 1, frags=frags)) + + todo.sort(key=lambda t: (-t[0], t[1])) + print(u'\n---- 还没连通的网络：%d 个，共欠 %d 条连接 ----' + % (len(todo), sum(t[0] for t in todo))) + for need, net, npads, frags in todo: + print(u' %-14s %3d 焊盘 %2d 个碎片 -> 还差 %2d 条' % (net, npads, len(frags), need)) + if not todo_only: + for f in frags[:8]: + labs = f['labels'][:10] + print(u' [%2d] %s%s' % (f['n'], u' '.join(labs), + u' …' if len(f['labels']) > 10 else u'')) + print(u'\n已连通 %d 个网络 / 单焊盘网络 %d 个' % (done, single)) + if outjson: + io.open(outjson, 'w', encoding='utf-8').write( + json.dumps(tasks, ensure_ascii=False, indent=1)) + print(u'待布线任务已写到 %s' % outjson) + return 0 + + +if __name__ == '__main__': + sys.exit(main()) diff --git a/.claude/pcb1_place.py b/.claude/pcb1_place.py index 61986a1..afa89c5 100644 --- a/.claude/pcb1_place.py +++ b/.claude/pcb1_place.py @@ -43,9 +43,20 @@ from eda import run PCB = '7e9415a16a909c51' MIL = 39.3700787401575 -BW, BH = 160.0, 125.0 +# ⚠️⚠️ 2026-09-07 修正：这两个数从 2026-09-06「两板尺寸取大对齐」那一轮起就过期了 —— +# 板上实测的板框是 **220 x 135、左下角 (-30,-5)**（`pcb1_outline.py` 就是这么画的， +# 回读多段线 x -1181.1~7480.3 mil / y -196.9~5118.1 mil 逐条对上）。 +# 旧值 (0,0,160,125) 是真板框的**子集**，所以越框检查一直是「偏严但不错」—— +# 代价是**左右各 30 mm、上下各 6 mm 的板面从来没进过摆位视野**。 +# 板边元件（风扇座、电源座、调试口）按旧值挑位置会挑到板子中间去。 +BX0, BY0, BX1, BY1 = -30.0, -5.0, 190.0, 130.0 # 真板框，mm +BW, BH = BX1 - BX0, BY1 - BY0 # 220 x 135 CORNER_R = 5.0 -MH = [(5.0, 5.0), (BW - 5.0, 5.0), (5.0, BH - 5.0), (BW - 5.0, BH - 5.0)] +# 2026-09-06 用户指令「两板尺寸取大对齐、四角定位孔对齐」：板框改成和载板一样的 220×135， +# **坐标原点不动**（下板坐标 = 载板坐标 − (30,5)，pcb1_env.py 那条约定不变），板框画到 (−30,−5)~(190,130)。 +# 定位孔 = 载板 `pcb2_place.MH` 减 (30,5)：四角 + 两侧中点。载板中跨那两个 (46.6,74.5)/(118.1,74.5) +# 落在下板 CH2 功率级 / 布好的线上，不打。板框与孔由 `pcb_place.py --outline` 下发（同一张表）。 +MH = [(-22.0, 3.0), (182.0, 3.0), (-26.0, 126.0), (186.0, 126.0), (-23.0, 55.0), (183.0, 40.0)] MH_HOLE, MH_PAD, MH_KEEPOUT = 3.2, 6.0, 6.5 PARTS = {c['d']: c for c in json.load(io.open(os.path.join(HERE, 'pcb1-parts.json'), encoding='utf-8'))} @@ -63,8 +74,18 @@ FP_BODY = { # 上面这几条当年是拿放大截图量出来的，六条全部对得上（误差 ≤0.31）。 # ⇒ 新加板边连接器时先跑 `fp_body.py --scan <关键词>`，别再猜 ±4.5。 # ── 2026-09-06 换件：J1 → XT30PW-M，J26~J30 → 2510-3A 直针座 ── - 'CONN-TH_XT30PW-M': (-6.65, -7.98, 6.65, 5.97), # 12V XT30 公头（90°板装） - 'CONN-TH_2510-3A': (-3.81, -2.88, 3.81, 2.93), # 风扇 3P **直针**座 + 'CONN-TH_XT30PW-M': (-6.65, -7.98, 6.65, 5.97), # 12V XT30 公头（已换掉，见下一条） + # ── 2026-09-08 换件：J1 → 圆形 DC 电源座 DC-005-5.5*2.5（用户拍板，不降载）── + # ⚠️ 这个数不是量截图量出来的，是 `pcb_Primitive.getPrimitivesBBox([pid])` 直接读的 + # （把件建在板外 (200,0) rot 0 读完再删）。**它含丝印/装配层，比塑壳本体大一圈** —— + # 同法读 XT30 得 14.85 x 13.55，而本体表里是 13.30 x 13.95，x 方向多 0.90。 + # 偏大的方向是安全的（净距检查偏严），本体真值待打样时拿实物量（§12 待确认项）。 + # 本体几乎全在 −X 侧、三个脚挤在 +X 端 ⇒ **桶口朝 −X**，朝西板边用 rot 0，不用转。 + 'DC-IN-TH_DC-005-2': (-10.68, -7.16, 3.92, 3.22), # 圆形 DC 座 5.5x2.5 + 'CONN-TH_2510-3A': (-3.81, -2.88, 3.81, 2.93), # 风扇 3P **直针**座（已换掉，见下一条） + # ── 2026-09-07 FAN-R2：五个 3 针风扇座 → 两个 4 针（一进一出，山洋 9G0612P4S001）── + 'CONN-TH_4P-P2.54_CAX_2510-4A': (-5.08, -2.79, 5.08, 3.01), # 风扇 4P 直针座（fp_body --scan 读出） + 'SOD-123_L2.7-W1.6-LS3.7-RD-1': (-1.93, -0.85, 1.93, 0.85), # DZ3 BZT52C8V2；本体比焊盘框宽 0.4 # 下面两条是换下来的，留着当对照（**别再用**）： 'CONN-TH_P5.08_KF128-5.08-2P': (-5.20, -5.20, 5.20, 5.20), # 旧 12V 螺钉端子 # ⚠️ KF2510-3A 是**弯针**座：焊盘一排，塑壳整个往 +Y 伸 11.7 mm，开口在远端。 @@ -113,8 +134,13 @@ H_FP = { # ⚠️⚠️ 换成立式**省的是板面、付的是高度**：直针座塑壳竖起来。 # `3D Model Transform` 只给 XY，**Z 读不出来** —— 下面两个数是按同系列 # 常规值取的保守估计，**打样前必须拿实物量**（§12 待确认项）。 - 'CONN-TH_XT30PW-M': 11.0, # XT30 90° 板装公头，本体躺着 - 'CONN-TH_2510-3A': 9.0, # 2510 直针座，塑壳竖立 + 'CONN-TH_XT30PW-M': 11.0, # XT30 90° 板装公头，本体躺着（已换掉） + 'DC-IN-TH_DC-005-2': 11.0, # 圆形 DC 座：同系列常规值，**打样前拿实物量** + # 放在西条（x −29~−1）上，那一条 hmax = 99（载板底面没东西），所以这个数目前不吃紧 + 'CONN-TH_2510-3A': 9.0, # 2510 直针座，塑壳竖立（3P，已换掉） + 'CONN-TH_4P-P2.54_CAX_2510-4A': 11.5, # 2510 直针 4P：厂家属性 Z-Height of the Board = 11.5 + 'SOT-23_L2.9-W1.3-P1.90-LS2.4-BR': 1.2, # Q7 AO3401A（和另一个 SOT-23-3 同高，封装名不同） + 'SOD-123_L2.7-W1.6-LS3.7-RD-1': 1.2, # DZ3 BZT52C8V2 # 排针本身就是对插件，不参与高度核算 'HDR-TH_40P-P2.54_AZ-PZ2.54-V11-2X20P': None, } @@ -238,12 +264,7 @@ CH1 = [ # 放电联锁 ('Q%01', 13.8, 35.5, 0), ('R%18', 16.4, 35.5, 0), ('Q%02', 13.8, 39.5, 0), ('R%19', 17.8, 40.0, 90), - # 按键驱动（远离 SW） - ('Q%03', 24.0, 12.0, 0), ('Q%04', 28.0, 12.0, 0), - ('Q%05', 24.0, 16.0, 0), ('R%20', 28.0, 16.0, 0), - ('R%21', 24.0, 19.5, 0), ('R%22', 28.0, 19.5, 0), - ('R%23', 24.0, 22.5, 0), ('R%24', 28.0, 22.5, 0), - ('R%25', 24.0, 25.5, 0), + # 按键驱动 Q%03~05 / R%20~25：2026-09-06 随 74HC595 整窝挪到载板（§26.23），这一片空出来了 ] @@ -294,7 +315,20 @@ put('J25', 128.0, 62.5, 0) # **原来 F1 那个位置 (14.5,71.5) 正好被吃掉**。 # 而东边的墙是硬的：北排 CH2 从 **x 29.6** 起，D1(SMB) 再往东就撞上去。 # ⇒ J1 东边只剩 15 mm 给 F1/Q1/D1/DZ1/C1/R1 六件，一行排不下（要 15+ mm），改**两行**。 -put('J1', 8.5, 72.0, 270) # 12V XT30 公头，插口朝左板边（rot 270） +# 2026-09-08 ⛔ **硬缺陷修复**：J1 原来在 x=8.5（本体 x 0.5~14.7）—— +# 那是按**过期的假板框 160×125**挑的“西板边”。真板框西边在 x=−30， +# 于是这个 **90° 板装** XT30 的插口缩在板内 30.5 mm，上方 13 mm 处还压着载板 +# —— **插头根本插不进去**。不是优化问题，是板子能不能用的问题。 +# → 整个输入首级（J1/F1/Q1/D1 + Q1 的栅极卫星 DZ1/C1/R1）西移 30 mm。 +# 西条 x −29~−1 整条 hmax = 99（载板底面没东西），高件随便放。 +# 代价：加权 HPWL +1~3%（源头离负载远了）—— 这是板子可装配的必要代价。 +# 2026-09-08 换成圆形 DC 电源座（用户拍板：DC-005 5.5x2.5，**不降载**，接受插座超额定）。 +# ⚠️ 整机 12V 最坏 9.99 A（§22.6），而 DC-005 家族额定 2~5 A —— 这是全板唯一一处 +# 明知超额定还要装的地方，发热在**插头内芯与插座弹片的接触面**，板上加铜救不了。 +# 板端能做的只有一件：pin2 / pin3 两个负极触点**都接地并联**，接触电阻减半（见 p1_dcjack.py）。 +# 桶口朝 −X ⇒ **rot 0**（XT30 那颗要 rot 270，别照抄）。本体 x −10.68~+3.92 相对中心， +# 放 x=−18.8 时本体 x −29.48~−14.88，离真西板边 (−30) 0.52 mm，和原来 XT30 的 0.5 一致。 +put('J1', -18.8, 72.0, 0) # 12V 圆形 DC 座，桶口朝**真**西板边（本体 x −29.5~−14.9） # ⚠⚠ **v11 的两行排法把 8 A 链卡死了**（2026-09-06 第二十三轮重排）。 # XT30 rot 270 之后 **GND 在北针 (13.5,74.5)、VIN 在南针 (13.5,69.5)**， # 而 F1 卵在 (17.5,74.5) 卧着放 ⇒ VIN_RAW 要从南针绕到 GND 盘东侧再北上， @@ -304,12 +338,12 @@ put('J1', 8.5, 72.0, 270) # 12V XT30 公头，插口朝左板边（rot 270 # ② D1 挪到东边空列 ⇒ J1.2 → F1.1 一片 6.5 × 7.9 mm 的铜，不再有颈； # ③ C4/C5/C6 一起东移 ⇒ 腾出 y 78.85~83.5 那条 4.65 mm 的 VIN_SW 西行干道 # （干道北提是因为 J1 的机械脚 J1.4 在 (3.5,77.5)，占到 y 78.6）。 -put('F1', 17.5, 74.5, 90) # 立着放：F1.1(VIN_RAW) 在南、F1.2(VIN_FUSED) 在北 -put('Q1', 24.0, 74.5, 270) # SOP-8 P-MOS 防反接 -put('D1', 31.0, 74.5, 270) # SMBJ13A TVS（挪出 VIN_RAW 通道，贴在漏极铜东缘） -put('DZ1', 22.0, 68.0, 0) # 栅极钳位 -put('C1', 25.5, 68.0, 0) -put('R1', 28.0, 71.5, 0) +put('F1', -12.5, 74.5, 90) # 立着放：F1.1(VIN_RAW) 在南、F1.2(VIN_FUSED) 在北 +put('Q1', -6.0, 74.5, 270) # SOP-8 P-MOS 防反接 +put('D1', 1.0, 74.5, 270) # SMBJ13A TVS（挪出 VIN_RAW 通道，贴在漏极铜东缘） +put('DZ1', -8.0, 68.0, 0) # 栅极钳位 +put('C1', -4.5, 68.0, 0) +put('R1', -2.0, 71.5, 0) put('C2', 6.5, 84.5, 0) # 470µF/25V put('C3', 16.0, 84.5, 0) # C4/C5/C6：rot 180 让 $1N236 那一脚朝西迎着漏极铜，GND 脚朝东好打过孔 @@ -360,28 +394,73 @@ put('R707', 60.0, 71.5, 180) put('L3', 70.5, 78.0, 0) put('C734', 77.5, 78.0, 90) put('C735', 80.0, 78.0, 90) -# 第三片 595（EDL_EN1~5）+ 风扇低边驱动 -put('U33', 92.0, 71.0, 0) +# ── 风扇 FAN-R2（2026-09-07）：两只 4 线 PWM 风扇，一进一出 ────────────── +# 旧的「低边切回流 + 5 个 3 针座 + TACH 分压」整块作废：R730~R732、J28~J30 已删。 +# 现在是「高边默认关电 + 独立 PWM 开漏 + 两路独立测速接收」，见设计文档 §22.6。 +# ⚠️ 摆位约束不只是「元件之间不重叠」：这一块北中区 y 64~100 底下压着已布好的 +# +12V / +3V3 / GND 铜和过孔，而 `pcb1_route_sig --ripup` **只拆自己画过的信号线**， +# 拆不掉电源铜。第一版把新件摆进 y 66~88 直接刷出 65 条间距错误。 +# ⇒ 新件整体上移到 **y 104~121 那条空带**（J28 删掉之后腾出来的）， +# 留用件 Q6 / R733 / R734 原地不动（它们原来的位置本来就是干净的）。 +# 【A】高边电源开关：+12V --Q7(P-MOS)--> FAN_12V_SW，MCU 高阻时默认断电 +put('R746', 91.0, 120.0, 0) # 100k 栅极拉回源极 +put('Q7', 95.0, 120.0, 0) # AO3401A +put('DZ3', 99.5, 120.0, 0) # BZT52C8V2 钳位负 Vgs（Q7 的 Vgs 绝对最大 ±12V） +put('C738', 105.0, 120.0, 0) # 22uF/25V，开关后母线本地储能 +put('D2', 111.5, 120.0, 0) # SS34：K 接 FAN_12V_SW、A 接 GND（负向钳位，不再是续流） +put('R747', 91.0, 116.0, 0) # 1k 栅极串阻 -> Q8 漏极 +put('Q8', 95.0, 116.0, 0) # AO3400A 拉低 Q7 栅极 +put('R748', 99.5, 116.0, 0) # 1k FAN_EN(IO5) -> Q8 栅极 +put('R749', 103.0, 116.0, 0) # 100k Q8 栅极下拉 = 复位默认断电 +# 【B】两路独立测速接收（10k 上拉到 FAN_12V_SW -> 15k/10k 分压 -> N-MOS -> 3V3 上拉） +# 2026-09-08：**跟着各自的风扇座走到真板边**。 +# 链路是 J2n.TACH → R75x(上拉到 FAN_12V_SW) → 分压 → Q(N-MOS) → FAN_TACH_xx(3V3 逻辑)。 +# `FAN_IN_TACH_RAW` / `FAN_OUT_TACH_RAW` 是**座子到分压器**的本地网络： +# 接收电路留在中间的话，这两个网络要横跨大半块板（121 / 104 mm）； +# 挪到座子旁边只剩几毫米。代价是 `FAN_TACH_IN/OUT`（已经是 3.3 V 逻辑、 +# 经 N-MOS 整形过）各长约 16 mm —— 净赚一百多毫米，而且换掉的是**未整形的 +# 12 V 摆幅裸信号**，抗扰上也是对的。 +put('R750', -26.0, 108.0, 0) # 进风：贴着西板边的 J26 +put('R751', -21.0, 108.0, 0) +put('Q9', -26.0, 104.0, 0) +put('R752', -21.0, 104.0, 0) +put('R753', -26.0, 100.0, 0) +put('R754', 181.0, 108.0, 0) # 排风：贴着东板边的 J27 +put('R755', 186.0, 108.0, 0) +put('Q10', 181.0, 104.0, 0) +put('R756', 186.0, 104.0, 0) +put('R757', 181.0, 100.0, 0) +# 【C】PWM 低边开漏：Q6 / R733 / R734 保持 2026-09-06 的原位（现在只拉风扇 PWM 脚） put('Q6', 102.0, 69.5, 0) -put('D2', 108.5, 69.5, 0) -put('C738', 102.0, 74.0, 0) -put('C739', 107.0, 74.0, 0) -put('R730', 98.0, 78.0, 0) -put('R731', 101.5, 78.0, 0) -put('R732', 105.0, 78.0, 0) -put('R733', 98.0, 80.5, 0) +put('R733', 98.0, 80.5, 0) put('R734', 101.5, 80.5, 0) -# 风扇座：4 个侧吸 + 1 个顶排，全部放板边（§22.6） -put('J26', 5.0, 16.0, 0) # 左板边（南） -put('J27', 5.0, 30.0, 0) -put('J29', 154.9, 16.0, 0) # 右板边（南） -put('J30', 154.9, 30.0, 0) -put('J28', 100.0, 112.7, 0) # 顶板边一侧；弯针塑壳往 +Y 伸 11.7，壳顶顶到 y 124.4 +# 风扇座：一进一出，分列**真**左右板边（顶排风孔取消，见 THERMAL_TWO_FAN） +# ⚠️ 4P 座比 3P 宽 2.54 ⇒ 半宽 3.81 → 5.08。本体 (-5.08,-2.79)-(5.08,3.01)，rot 0。 +# +# 2026-09-08 挪位：原来在 (6.3,121) / (151,121) —— 那是按**过期的假板框 160×125** 挑的 +# 「两个上角」，在真板框 220×135 / 左下角 (−30,−5) 里其实都在**板子中间**， +# 风扇线缆没法横着出去（直针座是垂直插拔，板边的意义就在于让线缆走得掉）。 +# +# 当年退到「上角」的理由是：4P 座塑壳 11.5 mm（厂家 Z-Height），而下板 hmax 由 +# **载板底面元件**的投影压出来（pcb1-env.json zones），假板框上 hmax >= 11.5 的 +# 板边只有 y 68~92 一段，还被输入链占满。**真板框下这个约束消失**： +# 左条 x −30~0 整条 hmax 无限制，右条 x 160~190 有 84% 无限制。 +# 实扫（`_fanpos2.py`）：西边 y 2~49 与 61~120、东边 y 2~34 与 67~120 都可用。 +# +# ⚠️ 压降复核（原注释担心的那一条）：`FAN_12V_SW` 总共 2×0.67 A，但 Q7 居中、 +# 两支**各只走 0.67 A**。0.8 mm 线宽下 R = ρL/(Wt)： +# 西支 125 mm → 0.077 Ω → 51 mV；东支 95 mm → 0.058 Ω → 39 mV +# 都远在 FAN_CIRCUIT 那 0.2 V 预算之内。当年算的 0.26 V 是「单条 196 mm 走全电流」， +# 分成两支之后不成立。⇒ **这条线要按 0.8 mm 下发，别当普通信号走 0.20。** +put('J26', -23.9, 115.0, 0) # 真西板边 = 进风（本体 x −29.0~−18.8，离板框 1.0） +put('J27', 183.9, 115.0, 0) # 真东板边 = 排风（本体 x 178.8~189.0） # ══════════════════ 【S-M】P3 / P3B 控制块 ══════════════════ # 南中块 x 69.5~119.5 / y 0.5~59 put('U20', 88.0, 18.2, 180) # ESP32-S3：天线端转到 −Y 朝下板边 -put('J22', 154.4, 52.0, 90) # 调试 USB-C，rot 90 = 开口朝 +X 右板边 +# 2026-09-08 ⛔ 同一类硬缺陷：J22 原来在 x=154.4（本体到 159.6）= 假板框的东边， +# 真板框东边在 x=190，于是 USB-C 开口缩在板内 30.4 mm，线插不进去。 +put('J22', 184.4, 52.0, 90) # 调试 USB-C，rot 90 = 开口朝**真**东板边（本体到 189.6） # （下板边放不下：C841 罐的 1.5 mm 禁区压到 y 8.4） put('RT601', 70.8, 36.0, 90) # 电感区测温：贴着 CH4 的电感那一排 put('RT602', 70.8, 26.0, 90) # MOS 区测温 @@ -413,8 +492,7 @@ put('RT602', 70.8, 26.0, 90) # MOS 区测温 DECAP = [ ('C602', 'U20', '2', 3.0), # 100 nF 0402，ESP32 高频去耦 —— 先占位 ('C601', 'U20', '2', 8.0), # 22 µF 1206，ESP32 储能 - ('C604', 'U21', '10', 3.0), # 74HC595 #1 VCC - ('C605', 'U22', '10', 3.0), # 74HC595 #2 VCC + # C604 / C605（74HC595 去耦）2026-09-06 随 595 挪到载板 ('C606', 'U23', '24', 3.0), # PCA9555 VDD ('C607', 'U6', '15', 3.0), # DAC63204 #1 VDD ('C610', 'U7', '15', 3.0), # DAC63204 #2 VDD @@ -457,8 +535,7 @@ def affine(pagelist, x0, y0, w, h): # 给走线留通道），结果钉在下面这张表里。附属的 22 个 R/C 不再跟着仿射走， # 改成 `SAT` 表逐个贴到**它真正的对端引脚**旁边。 CTRL = { - 'U21': (92.25, 52.37), - 'U22': (92.84, 38.01), + # U21 (92.25,52.37) / U22 (92.84,38.01) 2026-09-06 挪到载板（§26.23）—— x 88~97 / y 35~55 空出来 'U23': (76.50, 49.63), 'U6': (79.58, 38.01), 'U7': (109.57, 34.71), @@ -489,7 +566,6 @@ SAT = [ ('R608', 'U23', '1', 6.0, u'IOEXP_INT# 上拉'), ('R606', 'U23', '9', 6.0, u'BUCK_PG 上拉'), ('R607', 'U23', '10', 6.0, u'INA_ALERT 上拉'), - ('R609', 'U21', '13', 7.0, u'KEY_OE# 上拉（三片 595 共用）'), ('C608', 'U6', '13', 4.0, u'DAC #1 内部基准/输出滤波'), ('C609', 'U6', '16', 4.0, u'DAC #1'), ('R614', 'U6', '16', 5.0, u'DAC #1'), @@ -586,7 +662,7 @@ def _fits(des, cx, cy, rot, clear=0.3): u"""摆在这里会不会撞人 / 越框 / 压定位孔 / 超高。""" b = box(des, rot) ab = (cx + b[0], cy + b[1], cx + b[2], cy + b[3]) - if ab[0] < 0.4 or ab[2] > BW - 0.4 or ab[1] < 0.4 or ab[3] > BH - 0.4: + if ab[0] < BX0 + 0.4 or ab[2] > BX1 - 0.4 or ab[1] < BY0 + 0.4 or ab[3] > BY1 - 0.4: return False r = MH_KEEPOUT / 2.0 for hx, hy in MH: @@ -756,7 +832,7 @@ def check(): for d in sorted(POS): x0, y0, x1, y1 = abs_box(d) m = 0.4 - if x0 < m or x1 > BW - m or y0 < m or y1 > BH - m: + if x0 < BX0 + m or x1 > BX1 - m or y0 < BY0 + m or y1 > BY1 - m: errs.append(u'越出板框: %-6s 框 %.2f..%.2f / %.2f..%.2f' % (d, x0, x1, y0, y1)) r = MH_KEEPOUT / 2.0 @@ -840,6 +916,53 @@ def mate_report(): % (p, v[2], v[0], v[3], u'✔' if v[2] == v[3] else u'✘')) +# ══════════ 出线道加宽（2026-09-06 第二十六轮，用户拍板）══════════ +#: **「够净距」不等于「出得去线」。** `pad_clearance_errs` 判的是焊盘净距 ≥ 0.20， +#: 而一根 0.2 mm 的线要从两个焊盘中间出去，需要 0.20 + 0.20 + 0.20 = **0.60**。 +#: U6 / U7（WQFN-16 3×3，四边出脚）周围的卫星件正好卡在 **0.31 ~ 0.38** —— +#: 本地六项全过、DRC 也没有间距错误，可 `pcb1_escape_audit` 报「被围死」、 +#: 布线器报「几何上就出不去」，`SCL`(U6.6) / `$6N532`(U6.16) / `$6N547`(U7.16) +#: 三个网络因此永远布不通。这里把堵住出线道的六颗按**背离芯片**的方向各挪 0.30 mm。 +#: +#: ⚠️ 挪完 `C607` / `R617` 会分别压到 `SDA` / `SCL` 的换层孔（净距 0.029 / 0.113）—— +#: 那两个孔是 `pcb1_i2c_l3.py` 每轮重算的，**挪件之后必须重跑它**，孔会自己让开。 +#: +#: ⚠️ §26.22b：门槛不是 0.60 而是 **0.741**（CLR + 半线宽 + 栅格量化余量 QERR，两侧各 0.3707）。 +#: 0.30 挪出来的 0.612/0.615/0.676 理论上塞得下、0.1 栅格上塞不下 ⇒ 2026-09-06 第二十八轮 +#: 改成 **0.50（东列 0.45）**，三个方向都 ≥ 0.80。板上现在（`_pcb1_place_now.json`）是按 0.30 摆的， +#: 再挪 0.20 / 0.15 会压到的铜见 `.claude/_pcb1_unrouted_report.md` §A（VDAC4 孔、SDA 线+孔， +#: 以及 10 段要按新位置重做的扇出短线）。 +#: ⚠️⚠️ **这一手救不了 `U6.16` / `U7.16`**（`pcb1_ch_reroute.py` 本地实测：挪完照样「几何上就出不去」）—— +#: 它们被 C609 / C612 的 GND 脚 + GND 扇出孔从西边、C607 / C610 从北边、U6.15 的 +3V3 出线段从东边 +#: 三面围死，北挪 C607 只是把北墙推远，西墙东墙不动。真正的解法是下面的 `SAT_FLIP`。 +ESCAPE_NUDGE = { + 'R615': (0.0, -0.50), # U6 南排（U6.5 / U6.6=SCL） 0.312 -> 0.812 + 'C607': (0.0, +0.50), # U6 北排（U6.13/15/16） 0.315 -> 0.815 + 'C608': (+0.45, 0.0), # U6 东列（VDAC2 / VDAC4） 0.376 -> 0.826 + 'R617': (0.0, -0.50), # U7 南排（U7.5 / U7.6） 0.315 -> 0.815 + 'C610': (0.0, +0.50), # U7 北排（U7.13/15/16） 0.312 -> 0.812 + 'C611': (+0.45, 0.0), # U7 东列（VDAC3 / VDAC5） 0.376 -> 0.826 +} +for _d, (_dx, _dy) in sorted(ESCAPE_NUDGE.items()): + if _d in POS: + _x, _y, _r = POS[_d] + POS[_d] = (round(_x + _dx, 3), round(_y + _dy, 3), _r) + +# ══════════ VREF 电容转 180°（2026-09-06 第二十八轮，A 类唯一真正的几何解）══════════ +#: `C609` / `C612` 是 DAC63204 的 VREF 电容（pin 16），`place_sats()` 把它们竖着（rot 90）贴在 +#: U6.16 / U7.16 的西北角：**GND 脚在南（离引脚近）、VREF 脚在北（离引脚远）**， +#: GND 扇出孔又打在 GND 脚正南 —— 于是 U6.16 往西北去找 VREF 脚的那条道被自家 GND 孔 + GND 短线堵死。 +#: 转 180°（rot 90 -> 270）之后 VREF 脚朝南正对 U6.16（0.8 mm），GND 脚朝北。 +#: `pcb1_ch_reroute.py --win 73,32,87,47 --nets '$6N532' --move C609:0:0:180 --drop-via 78.03,39.61` +#: 本地实测：`$6N532` 3.6 mm 一次布通、净距 0；U7 同理。下发时要删 2 段扇出短线 + 补 1 个 GND 孔 +#: （见 `_pcb1_unrouted_report.md` §A）。 +SAT_FLIP = {'C609': 180, 'C612': 180} +for _d, _dr in sorted(SAT_FLIP.items()): + if _d in POS: + _x, _y, _r = POS[_d] + POS[_d] = (_x, _y, (_r + _dr) % 360) + + def summary(): ext = ch_extent() print(u'母版局部包围盒 x %.2f~%.2f y %.2f~%.2f（%.1f x %.1f）' diff --git a/.claude/pcb1_pour.py b/.claude/pcb1_pour.py index e5d6a30..e8c0d5d 100644 --- a/.claude/pcb1_pour.py +++ b/.claude/pcb1_pour.py @@ -71,6 +71,11 @@ J24 焊盘 x 6.97~57.03、J25 x 102.97~153.03，两排 y 61.2 / 63.8，Ø1.8 焊 **南边要 5.6 A**（CH1 + CH4 + CH5 各 1.6 A，加左右四个风扇约 0.4+0.4 A）。 分法：**中桥喂 CH1 + CH4 + 左风扇 = 3.6 A，右通道喂 CH5 + 右风扇 = 2.0 A。** + +> ⚠️ 2026-09-07 FAN-R2：五个 3 针风扇座删成两个 4 针，而且挪到了**北边两个上角**， +> 供电也从 `+12V` 改成 Q7 开关之后的 `FAN_12V_SW`。所以**南边现在只有 4.8 A** +> （中桥 3.2 / 右通道 1.6），风扇那 1.34 A 全部走北带经 Q7。上面两个 3.6 / 2.0 的 +> 判据没改，现在只是更保守，不用重算。 左通道不用 —— 它的北端要从 J1 (6.0,74) 和 C2.1 (4.8,82) 两个通孔旁边挤过去， 只剩 2.8 mm、带 2.06 A，够不上一路通道的量，而且那一片正好在 8 A 输入链的顶层大铜下面， 留成 GND 底填**比塞一条 12V 细带有用得多**。 @@ -135,7 +140,15 @@ VIN_RAW, VIN_FUSED, VIN_SW = AUTO['VIN_RAW'], AUTO['VIN_FUSED'], AUTO['VIN_SW'] CHAIN = ((VIN_RAW, 'VIN_RAW'), (VIN_FUSED, 'VIN_FUSED'), (VIN_SW, 'VIN_SW')) MIL = 39.3700787401575 -BW, BH = 160.0, 125.0 +# ⚠️⚠️ 2026-09-08：这里原来写的是 `BW, BH = 160.0, 125.0`，栅格从 (0,0) 起索引 —— +# 那是**过期的假板框**，和 `pcb1_place.py` 当年那条是同一个病（它已在第三十轮改掉）。 +# 真板框是 **220 × 135、左下角 (−30, −5)**（`pcb1_outline.py` 就是这么画的）。 +# 后果：**本地校核看不见 x<0 / y<0 那两条边**，落在那里的铜一律算成 0 —— +# 板上的铜不受影响（多边形是原样下发给 EasyEDA 的、由它去填）， +# 但**任何摆到负坐标的东西，断面/连通性校核都会静悄悄地给出 0**。 +# 第三十四轮把输入首级西移到 x −17~2 之后当场撞上：三块顶层铜全报「碎成 0 块」。 +BX0, BY0 = -30.0, -5.0 # 板框左下角 +BW, BH = 220.0, 135.0 # 板框尺寸 INSET = 0.5 # 铜面离板边 CLEAR = 0.2 # 安全间距（pcb1_rules.MIN_CLEARANCE） @@ -167,6 +180,24 @@ def rect(x0, y0, x1, y1): return [(x0, y0), (x1, y0), (x1, y1), (x0, y1)] +# ── 毫米 ↔ 栅格：**一律走这四个函数，不要再写 int(x / G)** ────────────── +# 板框左下角不是 (0,0)，直接除 G 会把负坐标截成 0（见上面 BX0/BY0 那段）。 +def gi(x): + return int((x - BX0) / G) + + +def gj(y): + return int((y - BY0) / G) + + +def gx(i): + return BX0 + (i + 0.5) * G + + +def gy(j): + return BY0 + (j + 0.5) * G + + CORNER_R = 5.0 @@ -179,10 +210,10 @@ def board_poly(inset=INSET, seg=6): """ r = CORNER_R - inset pts = [] - for cx, cy, a0 in ((BW - CORNER_R, CORNER_R, -90.0), - (BW - CORNER_R, BH - CORNER_R, 0.0), - (CORNER_R, BH - CORNER_R, 90.0), - (CORNER_R, CORNER_R, 180.0)): + for cx, cy, a0 in ((BX0 + BW - CORNER_R, BY0 + CORNER_R, -90.0), + (BX0 + BW - CORNER_R, BY0 + BH - CORNER_R, 0.0), + (BX0 + CORNER_R, BY0 + BH - CORNER_R, 90.0), + (BX0 + CORNER_R, BY0 + CORNER_R, 180.0)): for k in range(seg + 1): a = math.radians(a0 + 90.0 * k / seg) pts.append((cx + r * math.cos(a), cy + r * math.sin(a))) @@ -201,12 +232,18 @@ REGIONS = [ # 载板 `pcb2_pour.py` 文件头第 4 条）。 # ⇒ 把中桥并进南西、右通道并进南东、风扇指并进北带，凑成三个 L / T 形多边形， # 每块各自含 J28.1 / J26.1+J27.1 / J29.1+J30.1，**不依赖扇出就活得下来**。 + # ⚠️⚠️ **2026-09-07 FAN-R2 之后上面这句不再成立**：J28/J29/J30 删了，J26/J27 挪到两个上角 + # 而且 pin2 已经从 `+12V` 改成开关后的 `FAN_12V_SW`（经 Q7）—— + # 三块 +12V 里**一个风扇座的通孔焊盘都不剩了**，现在靠 `pcb_fanout` 打的过孔活着 + # （实测三块各填出 1 段，没被当孤岛删）。⇒ **重铺之前必须先扇出**， + # 否则会退回「边框还在、nPoured=0」那个状态。整板重布时把这三块各自含一个本网 + # 通孔焊盘的条件重新落实一次，别再依赖扇出的运气。 dict(net='+12V', layer=L_PWR, name='12V-N', poly=[ # 北大块 y 88~124.5 通板 + 风扇指下伸到 y 66.5，**挖掉 U13 那一角**（Kelvin 脚，§10.4） (0.5, 88.0), (96.5, 88.0), (96.5, 66.5), (112.0, 66.5), (112.0, 88.0), (159.5, 88.0), (159.5, 124.5), (0.5, 124.5), (0.5, 102.4), (12.5, 102.4), (12.5, 95.6), (0.5, 95.6)], - note=u'北带（CH2/CH3 的 Cin、U19、U29、J28）+ 风扇指（R730/C738/D2）；' + note=u'北带（CH2/CH3 的 Cin、U19、U29；FAN-R2 之后还含 Q7 源极 = 风扇 1.34 A 的入口）+ 风扇指（现已空载）；' u'**源 Rs6.2 的焊盘是 (8.93~10.21, 91.77~95.23)** —— U13 那个缺口原来写成 y 93.0~101.5，' u'正好把 Rs6.2 的中心咬掉，扇出于是把这颗 8 A 源判成「不在铜面里」一个过孔都没打（2026-09-06 抓到）。' u'缺口收成 y 95.6~102.4，只罩住 U13 十个脚(96.08~101.92)与 C11'), @@ -225,11 +262,11 @@ REGIONS = [ # 把 +12V 推到 72.6，缝就没了；离 3V3-SE 还有 0.4，够。 (0.5, 9.0), (72.6, 9.0), (72.6, 88.0), (61.5, 88.0), (61.5, 40.7), (54.0, 40.7), (54.0, 34.0), (0.5, 34.0)], - note=u'CH1 + CH4 的 Cin、J26/J27 左风扇；中桥穿中间通道下来，喂 3.6 A'), + note=u'CH1 + CH4 的 Cin（FAN-R2 之后南边没有风扇了）；中桥穿中间通道下来，喂 3.2 A，校核仍按 3.6 A 卡'), dict(net='+12V', layer=L_PWR, name='12V-SE+RC', poly=[ # 南东块 + 右通道：L 形。J22 只有两个无网络的壳体通孔在 x=151.9，不挡 x≥153.5 (116.0, 9.0), (159.5, 9.0), (159.5, 88.0), (153.5, 88.0), (153.5, 34.0), (116.0, 34.0)], - note=u'CH5 的 Cin、J29/J30 右风扇；右通道接回北带，喂 2.0 A'), + note=u'CH5 的 Cin（FAN-R2 之后南边没有风扇了）；右通道接回北带，喂 1.6 A，校核仍按 2.0 A 卡'), # ── +3V3：南部两块，各自从北边的源单独引底层干线（见文件头「绕不过去的结论」）── dict(net='+3V3', layer=L_PWR, name='3V3-SW', poly=rect(0.8, 41.0, 58.5, 58.5), @@ -273,19 +310,36 @@ REGIONS = [ # ⚠️ 顶层和内层挡路的东西不一样（Grid 的表）：这一片里 J1/C2/C3 的通孔、 # D1/C4/C5/C6/R1 的 GND 贴片焊盘、以及扇出给它们打的 9 个 GND 过孔 + 短线， # **每一样都要躲**。下面每一条边界后面括号里写的就是它躲的那个东西。 + # ⚠️⚠️ 2026-09-08 第三十四轮**整段重画**：输入首级（J1/F1/Q1/D1 + 栅极卫星）西移了 30 mm + # （J1 换圆形 DC 座并挪到真西板边）。旧的那一版坐标写在 x 11.9~22.5， + # 那一片现在**一个本网焊盘都没有** —— 铺出来是孤岛、会被整块删掉， + # 而断面校核量到的是空气（报 0.00 mm）。这是本文件第二次踩同一条， + # 第一次是第二十三轮（注释还在下面 CUTS 里）。⇒ **摆位一改就要回来重画这三块。** + # + # 新链路是**单向**的，比旧版顺：J1(−18.8) → F1(−12.5) → Q1(−6) → D1(1) → 东北去 C2/C3/Rs6。 + # 旧版是 J1 一路向东到 Q1、再折回西边找 Rs6，多绕了一圈。 dict(net=VIN_RAW, layer=L_TOP, name='VINRAW-TOP', - poly=[(11.9, 65.4), (19.6, 65.4), (19.6, 73.08), (18.58, 73.08), - (18.58, 73.78), (15.0, 73.78), (15.0, 73.0), (11.9, 73.0)], - note=u'J1.2(13.5,69.5) → F1.1(17.5,73.06)。F1 竖着放之后这一段是一片 7.7×7.7 的大铜；' - u'西北那个阶梯是躲 J1.1 的 GND 通孔(Φ2.5, 净距后 r=1.45)，' - u'东边 19.6 躲 Q1.4 栅极脚(20.215)与 DZ1.1(19.890)，' - u'北边两段台阶各给 VINFUSED 让 0.2'), + poly=[(-17.0, 70.7), (-11.5, 70.7), (-11.5, 73.80), + (-13.65, 73.80), (-13.65, 76.5), (-17.0, 76.5)], + note=u'J1.1(−15.80,74.35，中心正极，通孔盘 1.6×3.8) → F1.1(−12.50,73.06)。' + u'南边 70.7 躲 J1.3 的 GND 通孔盘(顶 70.450)；' + u'东边 −11.5 刚好盖住 F1.1(东 −11.637)，离 Q1 源极三脚(西 −9.786) 还有 1.7；' + u'x −13.65 那级台阶是躲 F1.2(西 −13.364, 南 75.350) —— 台阶以东只铺到 73.80，' + u'盖住 F1.1(顶 73.651) 并给 VIN_FUSED 让 0.30。' + u'**载流断面在 J1.1 与 F1.1 之间**（x≈−14.2），那里是满高 5.8 mm；' + u'台阶以东那 3.10 mm 不走穿过电流，F1.1 就是终点。' + u'⚠️ 两块的**竖直边**也要拉开：VINRAW 东界 −11.5 与 VINFUSED 的台阶 −11.15 ' + u'差 0.35 —— 第一版这两条边只隔 0.20（正好压在下限上），是校核报出来的'), dict(net=VIN_FUSED, layer=L_TOP, name='VINFUSED-TOP', - poly=[(16.4, 74.0), (18.8, 74.0), (18.8, 73.3), (22.5, 73.3), - (22.5, 78.5), (16.4, 78.5)], - note=u'F1.2(17.5,75.95) → Q1.1~3(源极三脚, x 20.2~22.2)。' - u'南边两段：西半 74.0 躲 F1.1(顶 73.651)，东半 73.3 躲 Q1.4(顶 72.882) ' - u'并盖住 Q1.3(底 73.578)；北边 78.5 给 VIN_SW 西行干道让 0.35'), + poly=[(-13.4, 74.10), (-11.15, 74.10), (-11.15, 73.3), + (-7.5, 73.3), (-7.5, 77.8), (-13.4, 77.8)], + note=u'F1.2(−12.50,75.95) → Q1.1~3(源极三脚, x −9.786~−7.751)。' + u'南边两段：西半 74.10 同时躲 F1.1(顶 73.651) 和 VINRAW 的台阶(顶 73.80，让 0.30)，' + u'东半 73.3 躲 Q1.4 栅极脚(顶 72.882) 并盖住 Q1.3(底 73.578)；' + u'东边 −7.5 离 Q1 漏极四脚(西 −4.250) 还有 3.25。' + u'断面在 F1.2 与源极之间（x≈−10.7）= 4.5 mm。' + u'⚠️ DZ1.1/C1.1 这两个栅极钳位件同属本网但在 y≈68，**不进这块铜** ——' + u'µA 级，交给 pcb1_route_sig 拉一条细线'), # ⚠ `VIN_SW` 必须是**一个铺铜对象**，不能拆成几块靠互相重叠连起来。 # 同层同网两块铜重叠时，低优先级那块会被高优先级那块裁掉 —— 裁的时候 @@ -294,16 +348,17 @@ REGIONS = [ # ⇒ 宁可手写 18 个点。下面的 `rects` 是这 18 个点该等于的矩形并集， # `report()` 里逐格对照，写错一个点当场就报（check_poly_rects）。 dict(net=VIN_SW, layer=L_TOP, name='VINSW-TOP', - poly=[(25.6, 72.1), (29.68, 72.1), (29.68, 73.45), (32.3, 73.45), - (32.3, 78.85), (30.47, 78.85), (30.47, 86.47), (28.6, 86.47), + poly=[(-4.45, 72.10), (-0.30, 72.10), (-0.30, 73.40), (2.40, 73.40), + (2.40, 78.85), (30.46, 78.85), (30.46, 86.47), (28.6, 86.47), (28.6, 83.49), (16.72, 83.49), (16.72, 85.5), (12.5, 85.5), (12.5, 83.49), (6.65, 83.49), (6.65, 87.0), (5.3, 87.0), - (5.3, 95.25), (1.5, 95.25), (1.5, 78.85), (25.6, 78.85)], - rects=[(25.6, 72.1, 29.68, 78.85), # Q1 漏极四脚（南边 72.1 躲 R1 的 GND 过孔 26.675,71.5） - (25.6, 73.45, 32.3, 78.85), # D1.1 TVS（南边 73.45 躲 D1.2 的 GND 盘顶 73.163 与它 6 个扇出孔） - (28.6, 78.85, 30.47, 86.47), # C4.2/C5.2/C6.2 去耦（东边 30.47 躲 C6.1 的 GND 盘 30.670） - (1.5, 78.85, 28.6, 83.49), # ★ 8 A 西行干道，y 净宽 4.64 mm； - # 南边 78.85 躲 J1 的机械脚 J1.4(顶 78.401)，北边 83.49 躲 C2/C3 的四个通孔(底 83.700) + (5.3, 95.25), (1.5, 95.25), (1.5, 83.49), (-4.45, 83.49)], + rects=[(-4.45, 72.10, -0.30, 78.85), # Q1 漏极四脚（x −4.250~−2.215）。南边 72.10 躲 R1 两脚(顶 71.772)，留 0.328 + (-0.30, 73.40, 2.40, 78.85), # D1.1 TVS(−0.096~2.096, 75.838~77.885)。 + # 南边抬到 73.40 是躲 D1.2 的 GND 盘(顶 73.163) 和它正下方 6 个扇出孔 + (-4.45, 78.85, 28.6, 83.49), # ★ 8 A 干道，y 净宽 4.64 mm。**西端由 1.5 延到 −4.45**： + # 旧版西端卡在 1.5 是因为老 J1 的机械脚 J1.4(顶 78.401) 顶着，那颗件已经挪走 + (28.6, 78.85, 30.46, 86.47), # C4.2/C5.2/C6.2 去耦（东边 30.46 躲 C6.1 的 GND 盘 30.670） (12.5, 83.49, 16.72, 85.5), # C3.1 口袋（东边 16.72 躲 C3.2 GND 通孔 16.950） (1.5, 83.49, 6.65, 87.0), # C2.1 口袋（净宽 5.15 mm） (1.5, 87.0, 5.3, 95.25)], # 北柱到 Rs6.1（净宽 **3.8 mm** = 8.5 A） @@ -312,8 +367,11 @@ REGIONS = [ # 顶到 y 95.4 —— 离 U13.2 只剩 0.379 mm，`pcb1_escape_audit` 报「被围死」。 # 收窄之后 U13 南边是一整片 x 5.5~14 / y 91.6~96 的空地。 # （Rs6.2 那两根往西甩的 1 mm 扇出短线也一起没了 —— 见 pcb_fanout.FORCE_ARRAY） - note=u'**8 A 主干**：Q1 漏极 → 北上 → 西行干道 → C3.1/C2.1 → 北柱 → Rs6.1，一路无过孔；' - u'东边挂 D1(TVS) 与 C4/C5/C6 去耦。干道比 v10 北提了 2.8 mm —— XT30 的机械脚占到 y 78.4'), + note=u'**8 A 主干**：Q1 漏极(−3.2) → 东经 D1 → 北上 → **东行**干道 → C2.1/C3.1 → 北柱 → Rs6.1，' + u'一路无过孔；东端挂 C4/C5/C6 去耦。' + u'⚠️ 第三十四轮之后干道是**东行**不是西行 —— 源头 Q1 从 x 24 挪到了 x −6，' + u'而 C2/C3/Rs6/C4~C6 一颗没动，于是电流方向整个翻过来了。' + u'旧注释「干道比 v10 北提 2.8 mm 躲 XT30 机械脚」已作废：那颗 XT30 已经不在这块板上'), ] # ── 断面校核：每一条都是「这里必须能过多少安」────────────────────────── @@ -332,7 +390,9 @@ CUTS = [ (u'南西块 → CH1', '+12V', L_PWR, 'x', 33.0, (9.0, 34.0), 2.0), (u'南西块 → CH4+CH1', '+12V', L_PWR, 'x', 61.0, (9.0, 34.0), 3.6), (u'南东块 → CH5', '+12V', L_PWR, 'x', 140.0, (9.0, 34.0), 1.6), - (u'风扇指 @接北带', '+12V', L_PWR, 'y', 87.0, (94.0, 114.0), 1.0), + # FAN-R2 之后风扇指下面已经没有 +12V 负载（风扇改吃开关后的 FAN_12V_SW）。 + # 这一条留着当**几何回归**：北带往南这一指还在，断面别被后来的布线啃掉。 + (u'风扇指 @接北带(现空载)', '+12V', L_PWR, 'y', 87.0, (94.0, 114.0), 1.0), (u'北大块 @Rs6 东出', '+12V', L_PWR, 'x', 20.0, (86.0, 124.5), 8.0), (u'3V3 南西块', '+3V3', L_PWR, 'x', 33.0, (41.0, 58.5), 0.5), (u'3V3 南东块 @控制块', '+3V3', L_PWR, 'x', 95.0, (9.0, 58.5), 0.5), @@ -341,10 +401,14 @@ CUTS = [ # 8 A 输入链（顶层 1 oz）。J1 → F1 → Q1 → D1/C4~C6 → C3/C2 → Rs6，分叉之前全程 8 A。 # ⚠ 这一排坐标跟着摆位走，**摆位一改就要重定**：2026-09-06 第二十三轮把 # F1 竖过来、D1 与 C4/C5/C6 挪到东列之后，旧的 `x=10` 那一刀量到的是空气（报 0.00 mm）。 - (u'RAW J1→F1 颈', VIN_RAW, L_TOP, 'y', 73.4, (14.0, 20.0), 8.0), - (u'RAW J1.2 东出', VIN_RAW, L_TOP, 'x', 15.5, (64.0, 76.0), 8.0), - (u'FUSED F1.2→Q1 源极', VIN_FUSED, L_TOP, 'x', 19.5, (72.0, 80.0), 8.0), - (u'SW Q1 漏极北出', VIN_SW, L_TOP, 'y', 77.5, (24.0, 34.0), 8.0), + # 2026-09-08：输入首级西移 30 mm，下面前四条**全部重定**。 + # ⚠️ 断面要卡在「电流真正流过的那一段」，不是随便找个地方量： + # VIN_RAW 的载流段是 J1.1 与 F1.1 **之间**（x≈−14.2）；台阶以东那 3.15 mm + # 是 F1.1 的落脚区、不走穿过电流，在那里量会得到一个偏严且没意义的数。 + (u'RAW J1.1→F1.1', VIN_RAW, L_TOP, 'x', -14.2, (68.0, 79.0), 8.0), + (u'FUSED F1.2→Q1 源极', VIN_FUSED, L_TOP, 'x', -10.7, (70.0, 80.0), 8.0), + (u'SW Q1 漏极东出', VIN_SW, L_TOP, 'x', -1.5, (69.0, 81.0), 8.0), + (u'SW 过 D1 北上', VIN_SW, L_TOP, 'x', 2.0, (70.0, 86.0), 8.0), (u'SW 干道 @x24 东端', VIN_SW, L_TOP, 'x', 24.0, (74.0, 86.0), 8.0), (u'SW 干道 @x12', VIN_SW, L_TOP, 'x', 12.0, (74.0, 86.0), 8.0), (u'SW 干道拐北 @y84', VIN_SW, L_TOP, 'y', 84.0, (0.5, 12.0), 8.0), @@ -373,7 +437,6 @@ ROUTED_PADS = { 'U12.9': u'Kelvin（IN−）：单独引线到 Rs501.1 的焊盘，不进 VO5_P 小岛', 'C11.1': u'陪 U13 一起挖出去，走顶层到 L2 输出', 'U13.6': u'INA226 的 VS+，陪 U13 一起挖出去（C11 就在旁边）', - 'C739.1': u'孤零零落在风扇指里，走 11 mm 顶层线到 U33.10', # U23 西侧那两颗（v11 控制块退火重排之后落到 x 71.9~72.4）： # 那一条 x 是 `12V-SW+BR`(东界 72.6) 与 `3V3-SE`(西界 73.0) 中间的 0.4 mm 缝， # 两块内层平面谁都够不着。**贴片焊盘对内层透明，所以不是错误**，走顶层短线即可： @@ -385,12 +448,24 @@ ROUTED_PADS = { u'不能从大铜面上随便找个点接', 'DZ1.1': u'Q1 栅极钳位齐纳的上端，µA 级；夹在 F1.1 与 Q1.4 之间只有 3.1 mm，走细线', 'C1.1': u'Q1 栅极 RC 的上端，µA 级；同 DZ1.1', + # 2026-09-08 第三十四轮：两路 TACH 接收跟着风扇座搬到了东西**板边** + # （R753 在 x −25.6、R757 在 x 181，都在 y≈100），离 `3V3-SW`/`3V3-SE` 两块内层 + # 平面各有 80~100 mm。**不要为这两颗把平面拉过去** —— 10 kΩ 上拉到 3.3 V + # 只有 **0.33 mA**，外层 0.2 mm 线绰绰有余，而拉一条 100 mm 的内层电源面 + # 会把 Inner2 的分割搅乱。它们是「接收电路在信号源头整形」那条设计决定的代价。 + 'R753.2': u'进风 TACH 的 3.3V 上拉（10k, 0.33 mA），随风扇座在西板边；走顶层细线', + 'R757.2': u'排风 TACH 的 3.3V 上拉（10k, 0.33 mA），随风扇座在东板边；走顶层细线', } # 整块「有意不进平面」的区域（位号前缀 → 说明） ROUTED_BLOCKS = [ ((14.0, 100.0, 30.0, 124.0), u'北左辅助 Buck 那一窝：12V 与 3V3 在 16×24 mm 里交错，整窝走顶层'), ((36.0, 70.0, 58.0, 84.0), u'CH2 的 +3V3（5 个，50 mA）：沿 y≈84 走顶层到中间那块'), ((126.0, 70.0, 146.0, 84.0), u'CH3 的 +3V3（5 个，50 mA）：同上'), + # `R518.1`(CH5 的 +3V3)：2026-09-06 第二十六轮起不再落在 Inner2 的 +3V3 上 —— + # 它本来就是「短线 + 扇出孔」那一类，只是以前**碰巧**还压着平面所以没被点名。 + # 实测通路：R518.1 → 顶层 0.66 mm → +3V3 扇出孔 (134.575, 51.000) → 平面， + # `pcb1_netlist` 里 +3V3 整网连通（不在「还差」名单里）。框只罩这一颗。 + ((135.0, 50.4, 136.0, 51.6), u'CH5 的 R518.1：顶层 0.66 mm 短线到 (134.575,51.000) 的 +3V3 扇出孔'), ] @@ -531,6 +606,16 @@ def inside(poly, x, y): # ══════════════════ 栅格化 + 校核 ══════════════════ G = 0.25 # 栅格（mm）。0.25 下 45 mm 的通道是 180 格，够细 +#: 浮铜检查的**最小面积**（mm²）。小于它的当栅格碎屑放过，只打印不判红。 +#: +#: ⚠️ 这不是"把检查关小声点"，是给它一个说得出理由的下限：布线一多， +#: 过孔的反焊盘之间必然夹出 0.25×0.25（**正好一个栅格**）这种碎屑 —— +#: 2026-09-06 第二十五轮实测两粒：Inner1 (68.9,74.6) 0.06 mm²、Inner2 (138.5,75.2) 0.19 mm²， +#: 都比一个过孔盘还小，电气上没有意义，而且嘉立创铺铜自己也会按死铜阈值清掉。 +#: 门槛定在 1.0 mm²（1×1 mm）：这一轮真正抓到的两条 —— 南沿那条 **1312.8 mm²** 的 +#: GND 底填、`3V3-SW` 里那块 **7.2 mm²** 的孤岛 —— 都远在门槛之上，一条都不会漏。 +MIN_FLOAT_AREA = 1.0 + class Grid(object): u"""某一层上某个网络的铜：先按区域填，再挖异网的反焊盘 / 过孔 / 走线。 @@ -554,11 +639,11 @@ class Grid(object): for r in regions: xs = [p[0] for p in r['poly']] ys = [p[1] for p in r['poly']] - i0, i1 = int(min(xs) / G), int(max(xs) / G) + 1 - j0, j1 = int(min(ys) / G), int(max(ys) / G) + 1 + i0, i1 = gi(min(xs)), gi(max(xs)) + 1 + j0, j1 = gj(min(ys)), gj(max(ys)) + 1 for j in range(max(0, j0), min(self.ny, j1)): for i in range(max(0, i0), min(self.nx, i1)): - if not self.c[j][i] and inside(r['poly'], (i + .5) * G, (j + .5) * G): + if not self.c[j][i] and inside(r['poly'], gx(i), gy(j)): self.c[j][i] = True # 反焊盘：异网焊盘（内层只算通孔，外层连贴片一起算） self.carved = 0 @@ -580,21 +665,21 @@ class Grid(object): # 天线禁铺（全层） for j in range(self.ny): for i in range(self.nx): - if self.c[j][i] and ANT[0] <= (i + .5) * G <= ANT[2] \ - and ANT[1] <= (j + .5) * G <= ANT[3]: + if self.c[j][i] and ANT[0] <= gx(i) <= ANT[2] \ + and ANT[1] <= gy(j) <= ANT[3]: self.c[j][i] = False self.label() def _carve(self, x0, y0, x1, y1): u"""挖掉一个矩形（已经把净距算进去了）。返回有没有真挖到东西。""" hit = False - for j in range(max(0, int(y0 / G)), min(self.ny, int(y1 / G) + 1)): - yc = (j + .5) * G + for j in range(max(0, gj(y0)), min(self.ny, gj(y1) + 1)): + yc = gy(j) if not (y0 <= yc <= y1): continue row = self.c[j] - for i in range(max(0, int(x0 / G)), min(self.nx, int(x1 / G) + 1)): - if row[i] and x0 <= (i + .5) * G <= x1: + for i in range(max(0, gi(x0)), min(self.nx, gi(x1) + 1)): + if row[i] and x0 <= gx(i) <= x1: row[i] = False hit = True return hit @@ -628,15 +713,15 @@ class Grid(object): u"""沿一条线量本网铜的总宽与最长连续段（mm）。""" tot = run_max = run = 0 if axis == 'y': - j = int(coord / G) - for i in range(int(span[0] / G), int(span[1] / G) + 1): + j = gj(coord) + for i in range(gi(span[0]), gi(span[1]) + 1): v = 0 <= i < self.nx and 0 <= j < self.ny and self.c[j][i] tot += 1 if v else 0 run = run + 1 if v else 0 run_max = max(run_max, run) else: - i = int(coord / G) - for j in range(int(span[0] / G), int(span[1] / G) + 1): + i = gi(coord) + for j in range(gj(span[0]), gj(span[1]) + 1): v = 0 <= i < self.nx and 0 <= j < self.ny and self.c[j][i] tot += 1 if v else 0 run = run + 1 if v else 0 @@ -645,8 +730,8 @@ class Grid(object): def hit(self, x, y, hx, hy): u"""这个焊盘有没有落在本网主连通域上（焊盘框内任一格）。""" - i0, i1 = int((x - hx) / G), int((x + hx) / G) + 1 - j0, j1 = int((y - hy) / G), int((y + hy) / G) + 1 + i0, i1 = gi(x - hx), gi(x + hx) + 1 + j0, j1 = gj(y - hy), gj(y + hy) + 1 for j in range(max(0, j0), min(self.ny, j1 + 1)): for i in range(max(0, i0), min(self.nx, i1 + 1)): if self.lab[j][i]: @@ -1004,7 +1089,9 @@ def ascii_map_top(pads, obs=()): 看不出「是被 GND 扇出孔啃的还是被自己的边界切的」。 """ g = 0.5 - x0, x1, y0, y1 = 1.0, 31.0, 65.0, 95.0 + # 2026-09-08：窗口跟着输入首级西移 —— 旧值 (1,31,65,95) 现在只剩右半条链。 + # 链路实际占 x −17~30.5 / y 70~95.3，取 0.5 mm/格 一行 96 字，够宽。 + x0, x1, y0, y1 = -18.0, 32.0, 69.0, 96.0 sym = [(VIN_RAW, 'R'), (VIN_FUSED, 'F'), (VIN_SW, 'S')] grids = [(s, Grid(net, L_TOP, [r for r in REGIONS if r['layer'] == L_TOP and r['net'] == net], @@ -1029,7 +1116,7 @@ def ascii_map_top(pads, obs=()): x = x0 + (i + .5) * g ch = '.' for s, gr in grids: - ii, jj = int(x / G), int(y / G) + ii, jj = gi(x), gj(y) if 0 <= ii < gr.nx and 0 <= jj < gr.ny and gr.c[jj][ii]: ch = s break @@ -1058,10 +1145,10 @@ def ascii_map(pads, obs=()): for j in range(ny - 1, -1, -1): row = '' for i in range(nx): - x, y = (i + .5) * g, (j + .5) * g + x, y = BX0 + (i + .5) * g, BY0 + (j + .5) * g ch = ' ' for net, gr in grids: - ii, jj = int(x / G), int(y / G) + ii, jj = gi(x), gj(y) if 0 <= ii < gr.nx and 0 <= jj < gr.ny and gr.c[jj][ii]: ch = sym[net] break @@ -1214,10 +1301,10 @@ def _cells_from_rings(rings): xs_ = pts[0::2] ys_ = pts[1::2] n = len(xs_) - j0 = max(0, int(min(ys_) / G)) - j1 = min(ny - 1, int(max(ys_) / G) + 1) + j0 = max(0, gj(min(ys_))) + j1 = min(ny - 1, gj(max(ys_)) + 1) for j in range(j0, j1 + 1): - y = (j + 0.5) * G + y = gy(j) cr = [] for k in range(n): y1, y2 = ys_[k], ys_[(k + 1) % n] @@ -1227,10 +1314,10 @@ def _cells_from_rings(rings): cr.sort() row = acc[j] for a in range(0, len(cr) - 1, 2): - ia = max(0, int(cr[a] / G)) - ib = min(nx - 1, int(cr[a + 1] / G)) + ia = max(0, gi(cr[a])) + ib = min(nx - 1, gi(cr[a + 1])) for i in range(ia, ib + 1): - xc = (i + 0.5) * G + xc = gx(i) if cr[a] <= xc <= cr[a + 1]: row[i] ^= 1 return [[bool(v) for v in r] for r in acc] @@ -1317,16 +1404,22 @@ def verify(refresh=True): g = G_[k] live = set() for x, y in anchors.get(k, ()): - i, j = int(x / G), int(y / G) + i, j = gi(x), gj(y) if 0 <= i < g.nx and 0 <= j < g.ny and g.lab[j][i]: live.add(g.lab[j][i]) dead = [(cid, n) for cid, n in g.sizes.items() if cid not in live] + big = [(c, n) for c, n in dead if n * G * G >= MIN_FLOAT_AREA] + dust = [(c, n) for c, n in dead if n * G * G < MIN_FLOAT_AREA] lay = {1: 'Top', 2: 'Bottom', 15: 'Inner1', 16: 'Inner2'}[k[1]] - chk(not dead, + if dust: + print(u' （%s %s 另有 %d 粒 < %.1f mm² 的碎屑，按 MIN_FLOAT_AREA 放过：%s mm²）' + % (lay, k[0], len(dust), MIN_FLOAT_AREA, + ' '.join('%.2f' % (n * G * G) for _c, n in sorted(dust, key=lambda t: -t[1])[:6]))) + chk(not big, u'%s %s 的 %d 块碎片各自都有本网焊盘/过孔落脚' % (lay, k[0], g.ncomp), u'%s %s 有 %d 块**浮铜**（没有任何本网落脚点）：%s mm²' - % (lay, k[0], len(dead), - ' '.join('%.1f' % (n * G * G) for _c, n in sorted(dead, key=lambda t: -t[1])[:6]))) + % (lay, k[0], len(big), + ' '.join('%.1f' % (n * G * G) for _c, n in sorted(big, key=lambda t: -t[1])[:6]))) grid_checks(G_, pads, chk) return bad diff --git a/.claude/pcb1_rules.py b/.claude/pcb1_rules.py index dac6970..eb55525 100644 --- a/.claude/pcb1_rules.py +++ b/.claude/pcb1_rules.py @@ -1,611 +1,622 @@ -# -*- coding: utf-8 -*- -u"""下板 PCB1 设计规则 + D± 差分对（2026-09-06，两板拆分之后重写）。 - -取代**单板时代**的 `pcb_rules.py`（那一份留在原地作历史，别再拿来下发 —— -它建 7 对差分、给 `+5V` 挂 `PWR12V`，两条在拆板之后都已经不对）。 - -做法和载板的 `pcb2_rules.py` 一模一样，**两个坑、两条陷阱全部照抄**， -那两份文件头是唯一的说明书，改规则前先读： - - · `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装 - · `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状**， - 两者不能混用（混了会被静默吃掉） - · 下发之后**别再去 GUI 换「配置」下拉框**，换一次整套重置、网络指派全部悬空 - · 写进去的 mm 会被换算成 mil 再换回来，`0.2` 回读是 `0.19999959999999997`， - 任何几何比较都留 1e-4 容差 - -## 和载板不同的四处 - -1. **差分对只剩 1 对**：`DEBUG`（`USB_DP` / `USB_DM`，J22 调试口 → U20 ESP32-S3）。 - 五路下行 D±、上行 `UP_*` 和五段 `*J` 在 2026-09-04 拆板时**整体搬到载板**， - 下板上这些网络已经不存在了 —— 建不上的对不是「没建上」，是本来就不该有。 - `strokeWidthMin` 保持 **0.20**（不像载板降到 0.10）：这一对两端是 USB-C 和模组， - 路上没有 0.35 mm 间距的连接器要钻。 - -2. **层角色是载板的镜像**：下板 **Inner1(L2) = 完整地平面 / Inner2(L3) = 分割电源面** - （§10.1）。D± 走**顶层、以 Inner1 为参考**，所以 W 0.28 / S 0.18 这一组几何 - 与载板完全同源（嘉立创四层 1.6 mm 标准叠层上下对称，L1-L2 与 L3-L4 都是 0.2104 mm）。 - -3. **线宽分五档**（载板三档）。多出来的两档是下板独有的东西： - - | 规则 | 默认 | 网络 | 依据 | - |---|---|---|---| - | `PWR12V` | 2.0 | `+12V` + 8 A 输入链三段 | §10.1：8 A 走 2.0 mm 温升 35 °C ⇒ **总干必须走灌铜**，2.0 只给分支 | - | `SWNODE` | 2.0 | 五路 Buck 的 SW 节点 | §10.1 表：4 A 的 SW 铜箔给 2.0 mm（温升 10.4 °C）| - | `PWR4A` | 1.5 | `VOn` / `VOn_F` / `VOn_P` | 每路 4 A（IPC-2221 外层 1 oz，ΔT≈16.7 °C）| - | `PWR5V` | 1.2 | `+5V` + U30 的 SW | §9.4 最坏 2.8 A（1.2 mm 可载 3.6 A）| - | `PWR1A` | 0.6 | `+3V3`、`SW3V3` | §9.3 辅助 Buck 按 0.5 A 设计 | - - **`SWNODE` 为什么和 `PWR4A` 分开、而且 max 卡在 4.0**：SW 是开关节点， - 铜越宽 I²R 越小但 dV/dt 的辐射面积越大（§10.2-2「压到刚好够载流」）。 - `PWR4A` 的 max 6.0 是给灌铜出线用的，SW 不该享受那个上限。 - - 最小值一律 0.15~0.3，理由同载板 §10.1：规则是**按网络**生效的， - `+12V` 上挂着 R104 那种 0402 分压抽头（焊盘才 0.57 mm 宽）， - 卡大线宽会让几十个焊盘扇不出去、刷出一屏假 DRC。 - **载流靠灌铜保证，不靠 DRC。** - -4. ⭐ **四条 4 A / 8 A 的干路是自动命名网（`$2N699` 一类）， - 这里按「位号 + 引脚」当场反查，不写死网名。** - - 拆板那次导入变更之后，同一个节点的自动网名从 `$2N687` 变成了 `$2N699`。 - 写死网名的后果是**静默失效**：`overwriteNetRules` 只改它认得的行， - 认不出的名字**既不报错也不留痕**，DRC 照样干干净净， - 而板上那条 4 A 干路的线宽规则已经悬空了。 - ⇒ 事实来源是 `pcb1-parts.json` 里每个焊盘带的 `net`， - `resolve_auto()` 拿 (位号, 引脚号) 反查，并**逐条断言**： - 查出来的必须是 `$` 开头的自动网、必须互不重复、 - 而且必须同时出现在这条链路的另一端（eFuse / Buck 的对应脚上）。 - 对不上就直接退出，不下发。 - -用法: /c/Python314/python .claude/pcb1_rules.py [--push | --check] - -⚠️ 跑之前先跑过 `pcb1_parts_dump.py`（导入变更之后必跑）， - 否则反查用的是旧网名 —— 这正是上面第 4 条要防的那件事。 -""" -import io -import json -import os -import sys - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -from eda import run - -PCB = '7e9415a16a909c51' # PCB1（下板） -PARTS = os.path.join(HERE, 'pcb1-parts.json') - -# ── 线宽规则（mm）────────────────────────────────────────────────────── -TRACK_RULES = { - 'PWR12V': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.3, 'strokeWidthMax': 10.0}, - 'SWNODE': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.3, 'strokeWidthMax': 4.0}, - 'PWR4A': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.3, 'strokeWidthMax': 6.0}, - 'PWR5V': {'strokeWidthDefault': 1.2, 'strokeWidthMin': 0.3, 'strokeWidthMax': 6.0}, - 'PWR1A': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.15, 'strokeWidthMax': 3.0}, -} - -# ── 有名字的网络 → 线宽规则 ──────────────────────────────────────────── -NET_TRACK = {} -for _n in range(1, 6): - NET_TRACK['VO%d' % _n] = 'PWR4A' # Buck 输出 → eFuse 输入 - NET_TRACK['VO%d_P' % _n] = 'PWR4A' # 分流之后 → 排针 → 载板 -NET_TRACK['+12V'] = 'PWR12V' -NET_TRACK['+5V'] = 'PWR5V' -NET_TRACK['+3V3'] = 'PWR1A' -NET_TRACK['SW3V3'] = 'PWR1A' # U19 SW → L2，0.5 A - -# ── 自动命名网 → 线宽规则（按「位号.引脚」反查，见文件头第 4 条）────── -# 值是 (探针, 校核端)：两端查出来的必须是同一个网，否则说明位号/引脚写错了。 -AUTO_TRACK = {} -for _n, _u in zip(range(1, 6), (1, 2, 3, 4, 5)): - _c = _n * 100 + 1 - # SW 节点：Buck 的 SW 脚 → 电感。TPS54622(VQFN-14) 的 SW 是 pin 11/12。 - AUTO_TRACK['SW%d' % _n] = ('SWNODE', ('L%d' % _c, '1'), ('U%d' % _u, '11')) - # VOn_F：eFuse 输出 → PGTH 分压 / INA226 VIN+ → 分流电阻上游。 - # TPS25940(WQFN-20) 的 OUT 是 pin 4~8，Rs*01 的上游脚是 pin 2。 - AUTO_TRACK['VO%d_F' % _n] = ('PWR4A', ('Rs%d' % _c, '2'), ('U%d' % (13 + _n), '5')) -# 8 A 输入链（§10.2b）：J1 → F1 → Q1 → C2/C3/D1 → Rs6。分叉之前全程 8 A。 -AUTO_TRACK['VIN_RAW'] = ('PWR12V', ('J1', '2'), ('F1', '1')) -AUTO_TRACK['VIN_FUSED'] = ('PWR12V', ('F1', '2'), ('Q1', '1')) -AUTO_TRACK['VIN_SW'] = ('PWR12V', ('Rs6', '1'), ('C2', '1')) -# 第二路辅助 Buck 的 SW（§9.4，12V→5V，最坏 2.8 A） -AUTO_TRACK['SW5V'] = ('PWR5V', ('L3', '1'), ('U30', '2')) -# 母线泄放链（2026-09-06 R9 拆成 5 × 2Ω 2512）：Q3 漏极 → R9A → … → R9E → GND。 -# 13.3 V 全压加在 10 Ω 上是 **1.33 A**，默认线宽扛不住；`PWR1A`(0.6 mm) 外层 1 oz -# 可带 2.16 A（ΔT 20 °C），够。四个串联节点全是自动命名网，同样按位号反查。 -for _i, (_a, _b) in enumerate(zip('ABCD', 'BCDE')): - AUTO_TRACK['BLEED%d' % (_i + 1)] = ('PWR1A', ('R9%s' % _a, '2'), ('R9%s' % _b, '1')) -AUTO_TRACK['BLEED0'] = ('PWR1A', ('Q3', '5'), ('R9A', '1')) - -# ── 铺铜的焊盘连接方式（Plane / Copper Zone）──────────────────────────── -# 默认 `connectMode = 0` 是十字花（辐条 0.254 mm）。给「有通孔焊盘、且电流大」的 -# 网络单独挂一条**全连接**，理由和载板 §25.11 那次一样：不是怕十字花烧 -# （单条辐条 0.254 mm 长、两端焊在大铜面上，8 A 下 ΔT ≈ 0.3 K，实算见 pcb2_rules.py）， -# 而是**铺完之后铜面几何要量得准** —— 十字花时铜面多边形把自己的焊盘挖空， -# 断面测量会读到一个 0.3 mm 的假瓶颈，真瓶颈和度量假象分不出来。 -# -# 内层铺铜的全连接**没有手焊代价**（焊接热走的是外层），所以这里比载板放得开一点。 -# 三类进来： -# · `VOn_P` 每路 3 个通孔焊盘（J24/J25 的排针针脚），一路 4 A 全从这三针进铜面； -# · `+5V` 10 个通孔焊盘（J24 四针 + J25 六针），最坏 2.8 A； -# · 8 A 输入链三段（`$1N223` / `$1N227` / `$1N236`）—— J1 端子和 C2/C3 两颗直插 -# 电解都在这上面，**这才是全板电流最大的通孔焊盘**。 -# 不进来的两个，理由都不是「忘了」： -# · `GND` ~38 个通孔焊盘、同时贴 Inner1 与 Inner2，留十字花（同载板的取舍）； -# · `+3V3` / `VOn` 一个通孔焊盘都没有（全是贴片），connectMode 对它们是空操作。 -PLANE_RULE = 'PLANE-DIRECT' -PLANE_CONNECT_DIRECT = 1 # 0 = 十字花（默认）, 1 = 全连接 -PLANE_NETS = ['VO%d_P' % _n for _n in range(1, 6)] + ['+5V'] -PLANE_AUTO = ['VIN_RAW', 'VIN_FUSED', 'VIN_SW'] # 键，取自 AUTO_TRACK - -# ── 差分对几何（mm）── 与载板同一组数，理由见文件头第 2 条 ───────────── -# ⚠️ 长度容差 5.0 mm（2026-09-04 用户拍板）：USB 2.0 HS 的对内偏斜预算按 100 ps -# 算、FR4 上约 15 mm；5 mm ≈ 30 ps 仍有大余量。卡 0.5 mm 会逼出没必要的蛇形线。 -DIFF = {'strokeWidthDefault': 0.28, 'strokeWidthMin': 0.20, 'strokeWidthMax': 0.60, - 'differentailPairSpacingDefault': 0.18, 'differentailPairSpacingMin': 0.15, - 'differentailPairLenTolerMax': 5.0} - -# 对内 0.28/0.18 是设计意图，但 DP/DM 是两个网络，通用 0.2 mm 净距规则不认「这是一对」， -# 在换层过孔处会误判。建一条 0.15 只挂在这一对自己的两个网络之间。 -PAIR_RULE = 'USBPAIR' -PAIR_CLEARANCE = 0.15 -PAIRS = [('DEBUG', 'USB_DP', 'USB_DM')] - -MIN_CLEARANCE = 0.2 - -OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" - "await new Promise(r=>setTimeout(r,1500));" % PCB) - - -def call(body, timeout=240): - r = run(OPEN + body, timeout=timeout) - if not r.get('success'): - print(u'失败:', json.dumps(r, ensure_ascii=False)[:600]) - sys.exit(1) - return r['result'] - - -# ── 自动命名网的反查 ────────────────────────────────────────────────── -def resolve_auto(): - u"""从 `pcb1-parts.json` 按 (位号, 引脚号) 查出当前的自动网名，并逐条断言。 - - 返回 {逻辑名: 网名}。任何一条对不上就直接 `sys.exit` —— 这是**下发前的闸门**， - 宁可不下发，也不要留一批悬空的指派（悬空是静默的，DRC 看不出来）。 - """ - if not os.path.exists(PARTS): - sys.exit(u'没有 %s —— 先跑 pcb1_parts_dump.py' % PARTS) - parts = json.load(io.open(PARTS, encoding='utf-8')) - pin = {} - for p in parts: - for pad in p['pads']: - pin[(p['d'], str(pad[0]))] = pad[5] - - out, bad, seen = {}, [], {} - for key, (rule, probe, cross) in sorted(AUTO_TRACK.items()): - if probe not in pin: - bad.append(u'%s: 板上没有 %s.%s' % (key, probe[0], probe[1])) - continue - if cross not in pin: - bad.append(u'%s: 板上没有校核端 %s.%s' % (key, cross[0], cross[1])) - continue - net, other = pin[probe], pin[cross] - if not net or not net.startswith('$'): - bad.append(u'%s: %s.%s 上是 “%s”，不是自动命名网 —— 探针写错了' - % (key, probe[0], probe[1], net)) - continue - if net != other: - bad.append(u'%s: %s.%s = %s，但校核端 %s.%s = %s —— 两端不是同一个网' - % (key, probe[0], probe[1], net, cross[0], cross[1], other)) - continue - if net in seen: - bad.append(u'%s 和 %s 查到同一个网 %s —— 探针重复了' - % (key, seen[net], net)) - continue - seen[net] = key - out[key] = net - - if bad: - print(u' [!!] 自动命名网反查失败，**没有下发任何东西**：') - for b in bad: - print(u' · ' + b) - print(u' 多半是 pcb1-parts.json 过期了（导入变更之后要重跑 pcb1_parts_dump.py），') - print(u' 也可能是原理图改了拓扑 —— 两种情况都要人看一眼，不能自动放过。') - sys.exit(1) - return out - - -def net_track_full(auto): - u"""有名字的 + 反查出来的，合成最终的「网络 → 线宽规则」表。""" - t = dict(NET_TRACK) - for key, net in auto.items(): - t[net] = AUTO_TRACK[key][0] - return t - - -def plane_nets_full(auto): - return list(PLANE_NETS) + [auto[k] for k in PLANE_AUTO] - - -CAP_JS = u""" -const D = eda.pcb_Drc; -const cur = await D.getCurrentRuleConfiguration(); -const c = JSON.parse(JSON.stringify(cur.config)); // 嵌套形状，原样送回 -const multi = (await D.getRuleConfiguration( - 'JLCPCB Capability(Multiple Layers Board)')).config; // 平形状，只当数据源 -const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s; -const PLANERULE = %s, PLANEMODE = %s; - -const setTrack = (e, mn, df, mx) => { - for (const k of Object.keys(e.form.data)) - Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx}); -}; -const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing']; - -// ── 1) 多层板能力集：三个放宽值 + 两条内层条目 ── -setTrack(T['copperThickness1oz'], 0.102, 0.254, 2.54); -if (!T['copperThickness0.5oz']) { - const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); - e.editName = 'copperThickness0.5oz'; e.isSetDefault = false; - setTrack(e, 0.089, 0.254, 2.54); - T['copperThickness0.5oz'] = e; -} -Object.assign(c['Physics']['Via Size']['viaSize'].form, - {viaOuterdiameterMin: 0.3, viaInnerdiameterMin: 0.2}); -if (!SS['copperThicknessInner0.5oz']) { - const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); - e.editName = 'copperThicknessInner0.5oz'; e.isSetDefault = false; - const src = multi['Spacing']['Safe Spacing']['copperThicknessInner0.5oz'].table; - for (const k of Object.keys(e.tables)) - e.tables[k].content = JSON.parse(JSON.stringify(src)); - SS['copperThicknessInner0.5oz'] = e; -} - -// ── 2) 功率线宽规则 ── -for (const name of Object.keys(TRACKS)) { - const f = TRACKS[name]; - const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); - e.editName = name; e.isSetDefault = false; e.unit = 'mm'; - setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax); - T[name] = e; -} - -// ── 3) 差分对几何 ── -const dp = c['Physics']['Differential Pair']['differentialPair'].form; -for (const k of Object.keys(dp.strokeWidthTables.data)) - Object.assign(dp.strokeWidthTables.data[k], - {minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault, - maxValue: DW.strokeWidthMax}); -for (const k of Object.keys(dp.diffPairSpacingTables.data)) - Object.assign(dp.diffPairSpacingTables.data[k], - {minValue: DW.differentailPairSpacingMin, - defaultValue: DW.differentailPairSpacingDefault}); -dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax; - -// ── 3b) 差分对对内间距条目（只给 net-by-net 用，不设为默认）── -if (!SS[PAIRRULE]) { - const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); - e.editName = PAIRRULE; e.isSetDefault = false; - for (const tk of Object.keys(e.tables || {})) - for (const row of (e.tables[tk].content || [])) - for (let i = 0; i < row.length; i++) - if (typeof row[i] === 'number') row[i] = PAIRC; - SS[PAIRRULE] = e; -} - -// ── 4) 安全间距全表抬到下限 ── -let bumped = 0; -for (const key of Object.keys(SS)) - if (key !== PAIRRULE) - for (const tk of Object.keys(SS[key].tables || {})) - for (const row of (SS[key].tables[tk].content || [])) - for (let i = 0; i < row.length; i++) - if (typeof row[i] === 'number' && row[i] < MINC) { row[i] = MINC; bumped++; } - -// ── 5) 铺铜焊盘连接方式：给大电流网络单独开一条「全连接」条目 ── -const CZ = c['Plane']['Copper Zone']; -if (!CZ[PLANERULE]) { - const e = JSON.parse(JSON.stringify(CZ['copperRegion'])); - e.editName = PLANERULE; e.isSetDefault = false; - CZ[PLANERULE] = e; -} -for (const m of ['singleLayerPadModel', 'multiLayerPadModel']) - for (const k of Object.keys(CZ[PLANERULE].form[m].data)) - CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE; - -const ok = await D.overwriteCurrentRuleConfiguration(c); // ⚠️ 传本体 -return {ok: ok === true, bumped: bumped, name: cur.name, - track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)}; -""" - - -def push_config(): - r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE, - json.dumps(PAIR_RULE), PAIR_CLEARANCE, - json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT)) - if not r.get('ok'): - print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效') - sys.exit(1) - print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track'])) - print(u' 安全间距抬高 %d 格，间距条目 %s' % (r['bumped'], ' '.join(r['spacing']))) - print(u' 铺铜连接方式条目 %s' % ' '.join(r['plane'])) - print(u' 配置名现在是 “%s”' % r['name']) - - -def caveat(n): - print(u'') - print(u'──── 两条必须记住的事 ────') - print(u'⚠️ 别去 GUI 的 设计 → 设计规则… 里换“配置”下拉框。') - print(u' 换一下整套重置，五条线宽规则全被冲掉，') - print(u' %d 个网络的指派立刻悬空（DRC 不报错，线宽也就不生效）。' % n) - print(u'⚠️ 再从原理图导入一次变更之后，自动命名网可能改名。') - print(u' 顺序是：pcb1_import --apply → pcb1_parts_dump → **pcb1_rules --push**。') - print(u' 少跑中间那一步，反查用的就是旧网名，指派会静默落空。') - - -def _nums(o): - if isinstance(o, bool): - return [] - if isinstance(o, (int, float)): - return [float(o)] - if isinstance(o, dict): - return [v for x in o.values() for v in _nums(x)] - if isinstance(o, list): - return [v for x in o for v in _nums(x)] - return [] - - -def _find(o, key_sub): - if isinstance(o, dict): - for k, v in o.items(): - if key_sub.lower() in str(k).lower() and isinstance(v, (int, float)) \ - and not isinstance(v, bool): - return float(v) - for v in o.values(): - r = _find(v, key_sub) - if r is not None: - return r - elif isinstance(o, list): - for v in o: - r = _find(v, key_sub) - if r is not None: - return r - return None - - -AUDIT_JS = """ -await new Promise(r=>setTimeout(r,1500)); -const c = await eda.pcb_Drc.getCurrentRuleConfiguration(); -const rules = await eda.pcb_Drc.getNetRules(); -const nbn = await eda.pcb_Drc.getNetByNetRules(); -return { - cfgName: c && c.name, - layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(), - track: Object.keys(c.config.Physics['Track']), - cap: { - track1oz: c.config.Physics['Track']['copperThickness1oz'], - via: c.config.Physics['Via Size']['viaSize'], - half: !!c.config.Physics['Track']['copperThickness0.5oz'], - inner: !!c.config.Spacing['Safe Spacing']['copperThicknessInner0.5oz'], - }, - diff: c.config.Physics['Differential Pair'], - spacing: c.config.Spacing['Safe Spacing'], - pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(), - assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default') - .map(r => [r.name, r['Track']]).sort(), - planeEntries: Object.keys(c.config['Plane']['Copper Zone']), - planeMode: ((((c.config['Plane']['Copper Zone'][%s] || {}).form || {}) - .multiLayerPadModel || {}).data || {})['1'], - planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default') - .map(r => [r.name, r['Copper Zone']]).sort(), - nbn: ((nbn && nbn['Safe Spacing']) || []).length, -}; -""" - - -def audit(auto): - track = net_track_full(auto) - planes = plane_nets_full(auto) - r = call(AUDIT_JS % json.dumps(PLANE_RULE)) - bad = [] - - def chk(cond, good, msg): - print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg)) - if not cond: - bad.append(msg) - - print(u'──── 审计 ────') - chk(r['layers'] == 4, u'铜层数 4', u'铜层数是 %s，应为 4' % r['layers']) - - cap = r['cap'] - tmin = _find(cap['track1oz'], 'minValue') - if tmin is None: - tmin = _find(cap['track1oz'], 'strokeWidthMin') - vout = _find(cap['via'], 'viaOuterdiameterMin') - vin = _find(cap['via'], 'viaInnerdiameterMin') - okcap = (tmin is not None and abs(tmin - 0.102) < 5e-4 - and vout is not None and abs(vout - 0.3) < 5e-4 - and vin is not None and abs(vin - 0.2) < 5e-4 - and cap['half'] and cap['inner']) - chk(okcap, - u'四层板能力集已就位（最小线宽 %.3f / 过孔 %.2f-%.2f，含 0.5oz 内层条目）' - % (tmin or -1, vout or -1, vin or -1), - u'还是两层板能力集：最小线宽 %.3f（应 0.102）/ 过孔 %.2f-%.2f（应 0.30-0.20）' - u' / 0.5oz 线宽条目 %s / 内层间距条目 %s' - % (tmin if tmin is not None else -1, vout if vout is not None else -1, - vin if vin is not None else -1, - u'有' if cap['half'] else u'无', u'有' if cap['inner'] else u'无')) - print(u' （配置名 “%s”）' % r['cfgName']) - - for name in sorted(TRACK_RULES): - chk(name in r['track'], u'线宽规则 %s 存在' % name, - u'线宽规则 %s **不存在** —— 有 %d 个网络指着它，现在是悬空的' - % (name, sum(1 for _, t in r['assigned'] if t == name))) - - w = _find(r['diff'], 'strokeWidthDefault') - if w is None: - w = _find(r['diff'], 'defaultValue') - sp = _find(r['diff'], 'PairSpacingDefault') - if sp is None: - d2 = (r['diff'] or {}).get('differentialPair', {}).get('form', {}) \ - .get('diffPairSpacingTables') - sp = _find(d2, 'defaultValue') - chk(w is not None and abs(w - DIFF['strokeWidthDefault']) < 5e-3 - and sp is not None and abs(sp - DIFF['differentailPairSpacingDefault']) < 5e-3, - u'差分对几何 W %.3f / S %.3f mm' % (w or -1, sp or -1), - u'差分对几何是 W %.3f / S %.3f，应为 W %.2f / S %.2f mm' - % (w if w is not None else -1, sp if sp is not None else -1, - DIFF['strokeWidthDefault'], DIFF['differentailPairSpacingDefault'])) - - # ⚠️ 容差留 1e-4：mm→mil→mm 往返，0.2 回读是 0.19999959999999997 - vals = [v for v in _nums(r['spacing']) if 0 < v < 10] - mn = min(vals) if vals else -1 - chk(mn >= PAIR_CLEARANCE - 1e-4, - u'安全间距下限 %.4f mm（对内那条 %.2f）' % (mn, PAIR_CLEARANCE), - u'安全间距下限只有 %.4f mm' % mn) - others = [v for k in r['spacing'] if k != PAIR_RULE - for v in _nums(r['spacing'][k]) if 0 < v < 10] - mno = min(others) if others else -1 - chk(mno >= MIN_CLEARANCE - 1e-4, u'非差分对间距下限 %.4f mm' % mno, - u'非差分对间距下限只有 %.4f mm，应抬到 %.2f mm' % (mno, MIN_CLEARANCE)) - - want = sorted(n for n, _, _ in PAIRS) - chk(r['pairs'] == want, u'差分对 %d 对: %s' % (len(r['pairs']), ' '.join(r['pairs'])), - u'差分对对不上：有 %s，应为 %s' % (r['pairs'], want)) - - pm = r.get('planeMode') or {} - chk(PLANE_RULE in (r.get('planeEntries') or []) - and pm.get('connectMode') == PLANE_CONNECT_DIRECT, - u'铺铜连接方式条目 %s 在（connectMode=%s 全连接）' % (PLANE_RULE, pm.get('connectMode')), - u'没有 %s 条目或 connectMode 不是 %d —— 大电流通孔焊盘会退回十字花' - % (PLANE_RULE, PLANE_CONNECT_DIRECT)) - pa = r.get('planeAssigned') or [] - chk(sorted(n for n, _ in pa) == sorted(planes) - and all(v == PLANE_RULE for _, v in pa), - u'铺铜全连接指派 %d 个网络' % len(pa), - u'铺铜全连接指派是 %s，应为 %s 全挂 %s' % (pa, planes, PLANE_RULE)) - - got = dict(r['assigned']) - missing = [(n, t) for n, t in sorted(track.items()) if got.get(n) != t] - chk(not missing and len(got) == len(track), - u'线宽指派 %d 个网络（含 %d 个自动命名网）' % (len(got), len(auto)), - u'线宽指派对不上：板上 %d 个 / 应 %d 个；缺或错的 %s' - % (len(got), len(track), missing[:8])) - - chk(r['nbn'] == len(PAIRS), u'对内间距规则 %d 条' % r['nbn'], - u'对内间距规则 %d 条，应为 %d' % (r['nbn'], len(PAIRS))) - - if bad: - caveat(len(track)) - return not bad - - -def main(): - auto = resolve_auto() - track = net_track_full(auto) - planes = plane_nets_full(auto) - - print(u'下板 PCB1 规则：线宽 %d 条（%s），安全间距下限 %.2f mm，四层板能力集' - % (len(TRACK_RULES), ' '.join(sorted(TRACK_RULES)), MIN_CLEARANCE)) - print(u'差分对：W %.2f / S %.2f / 线长容差 %.1f mm，共 %d 对（%s）' - % (DIFF['strokeWidthDefault'], DIFF['differentailPairSpacingDefault'], - DIFF['differentailPairLenTolerMax'], len(PAIRS), - ' '.join(n for n, _, _ in PAIRS))) - print(u'自动命名网反查（事实来源 pcb1-parts.json）：') - for key in sorted(auto): - rule, probe, cross = AUTO_TRACK[key] - print(u' %-10s = %-9s -> %-7s (%s.%s / 校核 %s.%s)' - % (key, auto[key], rule, probe[0], probe[1], cross[0], cross[1])) - print(u'线宽指派共 %d 个网络；铺铜全连接 %d 个（%s）' - % (len(track), len(planes), ' '.join(planes))) - - if '--check' in sys.argv: - sys.exit(0 if audit(auto) else 1) - if '--push' not in sys.argv: - print(u'（未加 --push，没有下发；--check 审计当前状态）') - return - - push_config() - - n = call(""" -const P = %s; -let k = 0; -for (const d of await eda.pcb_Drc.getAllDifferentialPairs()) - await eda.pcb_Drc.deleteDifferentialPair(d.name); -for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; } -return k; -""" % json.dumps(PAIRS)) - print(u' 差分对 %d / %d 对' % (n, len(PAIRS))) - if n != len(PAIRS): - print(u' [!!] 有对没建上 —— 多半是网络名在这块板上不存在') - - # ⚠️ `getNetRules()` 回来的是**整张表**，`overwriteNetRules` 整表覆盖 —— - # 线宽（Track）和铺铜连接方式（Copper Zone）必须在**同一次读改写**里做完， - # 分两次写的话后一次会拿着旧快照把前一次冲掉。 - n = call(""" -const T = %s, PN = %s, PR = %s; -const pset = new Set(PN); -const rules = await eda.pcb_Drc.getNetRules(); -let k = 0, p = 0; -const seen = []; -for (const r of rules) { - if (r.type !== 'net') continue; - if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); } - if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; } -} -await eda.pcb_Drc.overwriteNetRules(rules); -return {track: k, plane: p, seen: seen}; -""" % (json.dumps(track, ensure_ascii=False), - json.dumps(planes, ensure_ascii=False), json.dumps(PLANE_RULE))) - print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(track))) - if n['track'] != len(track): - miss = sorted(set(track) - set(n['seen'])) - print(u' [!!] 板上找不到这些网络：%s' % ' '.join(miss)) - print(u' 悬空的指派 DRC 不报错 —— 先查 pcb1-parts.json 是不是过期了') - print(u' 铺铜全连接指派 %d / %d 个网络（%s）' - % (n['plane'], len(planes), ' '.join(planes))) - if n['plane'] != len(planes): - print(u' [!!] 有网络没指派上 —— 没指派 = 退回十字花，大电流铜面几何就量不准了') - - # ⚠️ overwriteNetByNetRules 是整表覆盖，先读回再合并。 - # ⚠️ 还要**清掉自己的陈迹**：单板时代 `pcb_rules.py` 在这里留下了 7 条 - # （USB1~5 / UPSTREAM / DEBUG）。那 6 对的网络已经随 Hub 搬去载板、板上不存在了， - # 只加不删的话表里会一直挂着 6 条指向空网络的规则。判据是「rule 名是我们的 - # USBPAIR、但不在本轮 PAIRS 里」—— 别人建的条目一律不动。 - n = call(""" -const PAIRS = %s, RULE = %s; -const cur = await eda.pcb_Drc.getNetByNetRules(); -const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : []; -const key = e => [e.net1.name, e.net2.name].sort().join('|'); -const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|'))); -const list = []; -let dropped = 0; -for (const e of old) { - if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; } // 自己的陈迹 - list.push(e); -} -const have = new Set(list.map(key)); -let k = 0; -for (const [name, dp, dm] of PAIRS) { - const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm}, - rule: RULE, copperRuleName: null, planeRuleName: null}; - if (have.has(key(e))) continue; - list.push(e); k++; -} -const ok = await eda.pcb_Drc.overwriteNetByNetRules( - {'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []}); -const back = await eda.pcb_Drc.getNetByNetRules(); -return {added: k, dropped: dropped, ok: ok === true, - now: (back['Safe Spacing'] || []).length}; -""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE))) - print(u' 对内间距规则：新增 %d 条 / 清掉过期 %d 条，现共 %d 条（%s = %.2f mm）' - % (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE)) - if n['now'] != len(PAIRS): - print(u' [!!] 应为 %d 条' % len(PAIRS)) - - call("await eda.pcb_Document.save(); return 1;") - print(u' 已保存') - caveat(len(track)) - - -if __name__ == '__main__': - main() +# -*- coding: utf-8 -*- +u"""下板 PCB1 设计规则 + D± 差分对（2026-09-06，两板拆分之后重写）。 + +取代**单板时代**的 `pcb_rules.py`（那一份留在原地作历史，别再拿来下发 —— +它建 7 对差分、给 `+5V` 挂 `PWR12V`，两条在拆板之后都已经不对）。 + +做法和载板的 `pcb2_rules.py` 一模一样，**两个坑、两条陷阱全部照抄**， +那两份文件头是唯一的说明书，改规则前先读： + + · `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装 + · `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状**， + 两者不能混用（混了会被静默吃掉） + · 下发之后**别再去 GUI 换「配置」下拉框**，换一次整套重置、网络指派全部悬空 + · 写进去的 mm 会被换算成 mil 再换回来，`0.2` 回读是 `0.19999959999999997`， + 任何几何比较都留 1e-4 容差 + +## 和载板不同的四处 + +1. **差分对只剩 1 对**：`DEBUG`（`USB_DP` / `USB_DM`，J22 调试口 → U20 ESP32-S3）。 + 五路下行 D±、上行 `UP_*` 和五段 `*J` 在 2026-09-04 拆板时**整体搬到载板**， + 下板上这些网络已经不存在了 —— 建不上的对不是「没建上」，是本来就不该有。 + `strokeWidthMin` 保持 **0.20**（不像载板降到 0.10）：这一对两端是 USB-C 和模组， + 路上没有 0.35 mm 间距的连接器要钻。 + +2. **层角色是载板的镜像**：下板 **Inner1(L2) = 完整地平面 / Inner2(L3) = 分割电源面** + （§10.1）。D± 走**顶层、以 Inner1 为参考**，所以 W 0.28 / S 0.18 这一组几何 + 与载板完全同源（嘉立创四层 1.6 mm 标准叠层上下对称，L1-L2 与 L3-L4 都是 0.2104 mm）。 + +3. **线宽分五档**（载板三档）。多出来的两档是下板独有的东西： + + | 规则 | 默认 | 网络 | 依据 | + |---|---|---|---| + | `PWR12V` | 2.0 | `+12V` + 8 A 输入链三段 | §10.1：8 A 走 2.0 mm 温升 35 °C ⇒ **总干必须走灌铜**，2.0 只给分支 | + | `SWNODE` | 2.0 | 五路 Buck 的 SW 节点 | §10.1 表：4 A 的 SW 铜箔给 2.0 mm（温升 10.4 °C）| + | `PWR4A` | 1.5 | `VOn` / `VOn_F` / `VOn_P` | 每路 4 A（IPC-2221 外层 1 oz，ΔT≈16.7 °C）| + | `PWR5V` | 1.2 | `+5V` + U30 的 SW | §9.4 最坏 2.8 A（1.2 mm 可载 3.6 A）| + | `PWR1A` | 0.6 | `+3V3`、`SW3V3` | §9.3 辅助 Buck 按 0.5 A 设计 | + + **`SWNODE` 为什么和 `PWR4A` 分开、而且 max 卡在 4.0**：SW 是开关节点， + 铜越宽 I²R 越小但 dV/dt 的辐射面积越大（§10.2-2「压到刚好够载流」）。 + `PWR4A` 的 max 6.0 是给灌铜出线用的，SW 不该享受那个上限。 + + 最小值一律 0.15~0.3，理由同载板 §10.1：规则是**按网络**生效的， + `+12V` 上挂着 R104 那种 0402 分压抽头（焊盘才 0.57 mm 宽）， + 卡大线宽会让几十个焊盘扇不出去、刷出一屏假 DRC。 + **载流靠灌铜保证，不靠 DRC。** + +4. ⭐ **四条 4 A / 8 A 的干路是自动命名网（`$2N699` 一类）， + 这里按「位号 + 引脚」当场反查，不写死网名。** + + 拆板那次导入变更之后，同一个节点的自动网名从 `$2N687` 变成了 `$2N699`。 + 写死网名的后果是**静默失效**：`overwriteNetRules` 只改它认得的行， + 认不出的名字**既不报错也不留痕**，DRC 照样干干净净， + 而板上那条 4 A 干路的线宽规则已经悬空了。 + ⇒ 事实来源是 `pcb1-parts.json` 里每个焊盘带的 `net`， + `resolve_auto()` 拿 (位号, 引脚号) 反查，并**逐条断言**： + 查出来的必须是 `$` 开头的自动网、必须互不重复、 + 而且必须同时出现在这条链路的另一端（eFuse / Buck 的对应脚上）。 + 对不上就直接退出，不下发。 + +用法: /c/Python314/python .claude/pcb1_rules.py [--push | --check] + +⚠️ 跑之前先跑过 `pcb1_parts_dump.py`（导入变更之后必跑）， + 否则反查用的是旧网名 —— 这正是上面第 4 条要防的那件事。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from eda import run + +PCB = '7e9415a16a909c51' # PCB1（下板） +PARTS = os.path.join(HERE, 'pcb1-parts.json') + +# ── 线宽规则（mm）────────────────────────────────────────────────────── +TRACK_RULES = { + 'PWR12V': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.3, 'strokeWidthMax': 10.0}, + 'SWNODE': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.3, 'strokeWidthMax': 4.0}, + 'PWR4A': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.3, 'strokeWidthMax': 6.0}, + 'PWR5V': {'strokeWidthDefault': 1.2, 'strokeWidthMin': 0.3, 'strokeWidthMax': 6.0}, + 'PWR1A': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.15, 'strokeWidthMax': 3.0}, + 'FAN12V': {'strokeWidthDefault': 0.8, 'strokeWidthMin': 0.3, 'strokeWidthMax': 3.0}, +} + +# ── 有名字的网络 → 线宽规则 ──────────────────────────────────────────── +NET_TRACK = {} +for _n in range(1, 6): + NET_TRACK['VO%d' % _n] = 'PWR4A' # Buck 输出 → eFuse 输入 + NET_TRACK['VO%d_P' % _n] = 'PWR4A' # 分流之后 → 排针 → 载板 +NET_TRACK['+12V'] = 'PWR12V' +NET_TRACK['+5V'] = 'PWR5V' +NET_TRACK['+3V3'] = 'PWR1A' +NET_TRACK['SW3V3'] = 'PWR1A' # U19 SW → L2，0.5 A +# 2026-09-08 第三十三轮：风扇高边开关的下游母线。Q7 居中、东西两支**各只走 0.67 A** +# （FAN-R2 两把风扇 2 x 0.67 A），0.8 mm 外层 1 oz 下西支 125 mm -> 51 mV、东支 95 mm -> 39 mV， +# 在 `FAN_CIRCUIT` 的 0.2 V 预算之内。**默认信号线 0.20 mm 扛不住** —— +# 0.20 mm 下同样两支是 204 / 155 mV，单是西支就吃掉全部预算。 +# ⚠️ 早年注释里担心的 0.26 V 是「一条 196 mm 走全电流 1.33 A」的算法， +# J26/J27 分到东西两板边、Q7 居中之后不成立。 +NET_TRACK['FAN_12V_SW'] = 'FAN12V' + +# ── 自动命名网 → 线宽规则（按「位号.引脚」反查，见文件头第 4 条）────── +# 值是 (探针, 校核端)：两端查出来的必须是同一个网，否则说明位号/引脚写错了。 +AUTO_TRACK = {} +for _n, _u in zip(range(1, 6), (1, 2, 3, 4, 5)): + _c = _n * 100 + 1 + # SW 节点：Buck 的 SW 脚 → 电感。TPS54622(VQFN-14) 的 SW 是 pin 11/12。 + AUTO_TRACK['SW%d' % _n] = ('SWNODE', ('L%d' % _c, '1'), ('U%d' % _u, '11')) + # VOn_F：eFuse 输出 → PGTH 分压 / INA226 VIN+ → 分流电阻上游。 + # TPS25940(WQFN-20) 的 OUT 是 pin 4~8，Rs*01 的上游脚是 pin 2。 + AUTO_TRACK['VO%d_F' % _n] = ('PWR4A', ('Rs%d' % _c, '2'), ('U%d' % (13 + _n), '5')) +# 8 A 输入链（§10.2b）：J1 → F1 → Q1 → C2/C3/D1 → Rs6。分叉之前全程 8 A。 +# ⚠️ 2026-09-08 J1 换成圆形 DC 座之后**正极从 pin2 挪到了 pin1** +# （XT30：1=`−` / 2=`+`；DC-005：1=中心正极 / 2、3=两个负极触点）。 +# 探针写错时这里是硬失败（"J1.2 上是 GND，不是自动命名网"），不会静默放过 —— 这是对的。 +AUTO_TRACK['VIN_RAW'] = ('PWR12V', ('J1', '1'), ('F1', '1')) +AUTO_TRACK['VIN_FUSED'] = ('PWR12V', ('F1', '2'), ('Q1', '1')) +AUTO_TRACK['VIN_SW'] = ('PWR12V', ('Rs6', '1'), ('C2', '1')) +# 第二路辅助 Buck 的 SW（§9.4，12V→5V，最坏 2.8 A） +AUTO_TRACK['SW5V'] = ('PWR5V', ('L3', '1'), ('U30', '2')) +# 母线泄放链（2026-09-06 R9 拆成 5 × 2Ω 2512）：Q3 漏极 → R9A → … → R9E → GND。 +# 13.3 V 全压加在 10 Ω 上是 **1.33 A**，默认线宽扛不住；`PWR1A`(0.6 mm) 外层 1 oz +# 可带 2.16 A（ΔT 20 °C），够。四个串联节点全是自动命名网，同样按位号反查。 +for _i, (_a, _b) in enumerate(zip('ABCD', 'BCDE')): + AUTO_TRACK['BLEED%d' % (_i + 1)] = ('PWR1A', ('R9%s' % _a, '2'), ('R9%s' % _b, '1')) +AUTO_TRACK['BLEED0'] = ('PWR1A', ('Q3', '5'), ('R9A', '1')) + +# ── 铺铜的焊盘连接方式（Plane / Copper Zone）──────────────────────────── +# 默认 `connectMode = 0` 是十字花（辐条 0.254 mm）。给「有通孔焊盘、且电流大」的 +# 网络单独挂一条**全连接**，理由和载板 §25.11 那次一样：不是怕十字花烧 +# （单条辐条 0.254 mm 长、两端焊在大铜面上，8 A 下 ΔT ≈ 0.3 K，实算见 pcb2_rules.py）， +# 而是**铺完之后铜面几何要量得准** —— 十字花时铜面多边形把自己的焊盘挖空， +# 断面测量会读到一个 0.3 mm 的假瓶颈，真瓶颈和度量假象分不出来。 +# +# 内层铺铜的全连接**没有手焊代价**（焊接热走的是外层），所以这里比载板放得开一点。 +# 三类进来： +# · `VOn_P` 每路 3 个通孔焊盘（J24/J25 的排针针脚），一路 4 A 全从这三针进铜面； +# · `+5V` 10 个通孔焊盘（J24 四针 + J25 六针），最坏 2.8 A； +# · 8 A 输入链三段（`$1N223` / `$1N227` / `$1N236`）—— J1 端子和 C2/C3 两颗直插 +# 电解都在这上面，**这才是全板电流最大的通孔焊盘**。 +# 不进来的两个，理由都不是「忘了」： +# · `GND` ~38 个通孔焊盘、同时贴 Inner1 与 Inner2，留十字花（同载板的取舍）； +# · `+3V3` / `VOn` 一个通孔焊盘都没有（全是贴片），connectMode 对它们是空操作。 +PLANE_RULE = 'PLANE-DIRECT' +PLANE_CONNECT_DIRECT = 1 # 0 = 十字花（默认）, 1 = 全连接 +PLANE_NETS = ['VO%d_P' % _n for _n in range(1, 6)] + ['+5V'] +PLANE_AUTO = ['VIN_RAW', 'VIN_FUSED', 'VIN_SW'] # 键，取自 AUTO_TRACK + +# ── 差分对几何（mm）── 与载板同一组数，理由见文件头第 2 条 ───────────── +# ⚠️ 长度容差 5.0 mm（2026-09-04 用户拍板）：USB 2.0 HS 的对内偏斜预算按 100 ps +# 算、FR4 上约 15 mm；5 mm ≈ 30 ps 仍有大余量。卡 0.5 mm 会逼出没必要的蛇形线。 +DIFF = {'strokeWidthDefault': 0.28, 'strokeWidthMin': 0.20, 'strokeWidthMax': 0.60, + 'differentailPairSpacingDefault': 0.18, 'differentailPairSpacingMin': 0.15, + 'differentailPairLenTolerMax': 5.0} + +# 对内 0.28/0.18 是设计意图，但 DP/DM 是两个网络，通用 0.2 mm 净距规则不认「这是一对」， +# 在换层过孔处会误判。建一条 0.15 只挂在这一对自己的两个网络之间。 +PAIR_RULE = 'USBPAIR' +PAIR_CLEARANCE = 0.15 +PAIRS = [('DEBUG', 'USB_DP', 'USB_DM')] + +MIN_CLEARANCE = 0.2 + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,1500));" % PCB) + + +def call(body, timeout=240): + r = run(OPEN + body, timeout=timeout) + if not r.get('success'): + print(u'失败:', json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +# ── 自动命名网的反查 ────────────────────────────────────────────────── +def resolve_auto(): + u"""从 `pcb1-parts.json` 按 (位号, 引脚号) 查出当前的自动网名，并逐条断言。 + + 返回 {逻辑名: 网名}。任何一条对不上就直接 `sys.exit` —— 这是**下发前的闸门**， + 宁可不下发，也不要留一批悬空的指派（悬空是静默的，DRC 看不出来）。 + """ + if not os.path.exists(PARTS): + sys.exit(u'没有 %s —— 先跑 pcb1_parts_dump.py' % PARTS) + parts = json.load(io.open(PARTS, encoding='utf-8')) + pin = {} + for p in parts: + for pad in p['pads']: + pin[(p['d'], str(pad[0]))] = pad[5] + + out, bad, seen = {}, [], {} + for key, (rule, probe, cross) in sorted(AUTO_TRACK.items()): + if probe not in pin: + bad.append(u'%s: 板上没有 %s.%s' % (key, probe[0], probe[1])) + continue + if cross not in pin: + bad.append(u'%s: 板上没有校核端 %s.%s' % (key, cross[0], cross[1])) + continue + net, other = pin[probe], pin[cross] + if not net or not net.startswith('$'): + bad.append(u'%s: %s.%s 上是 “%s”，不是自动命名网 —— 探针写错了' + % (key, probe[0], probe[1], net)) + continue + if net != other: + bad.append(u'%s: %s.%s = %s，但校核端 %s.%s = %s —— 两端不是同一个网' + % (key, probe[0], probe[1], net, cross[0], cross[1], other)) + continue + if net in seen: + bad.append(u'%s 和 %s 查到同一个网 %s —— 探针重复了' + % (key, seen[net], net)) + continue + seen[net] = key + out[key] = net + + if bad: + print(u' [!!] 自动命名网反查失败，**没有下发任何东西**：') + for b in bad: + print(u' · ' + b) + print(u' 多半是 pcb1-parts.json 过期了（导入变更之后要重跑 pcb1_parts_dump.py），') + print(u' 也可能是原理图改了拓扑 —— 两种情况都要人看一眼，不能自动放过。') + sys.exit(1) + return out + + +def net_track_full(auto): + u"""有名字的 + 反查出来的，合成最终的「网络 → 线宽规则」表。""" + t = dict(NET_TRACK) + for key, net in auto.items(): + t[net] = AUTO_TRACK[key][0] + return t + + +def plane_nets_full(auto): + return list(PLANE_NETS) + [auto[k] for k in PLANE_AUTO] + + +CAP_JS = u""" +const D = eda.pcb_Drc; +const cur = await D.getCurrentRuleConfiguration(); +const c = JSON.parse(JSON.stringify(cur.config)); // 嵌套形状，原样送回 +const multi = (await D.getRuleConfiguration( + 'JLCPCB Capability(Multiple Layers Board)')).config; // 平形状，只当数据源 +const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s; +const PLANERULE = %s, PLANEMODE = %s; + +const setTrack = (e, mn, df, mx) => { + for (const k of Object.keys(e.form.data)) + Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx}); +}; +const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing']; + +// ── 1) 多层板能力集：三个放宽值 + 两条内层条目 ── +setTrack(T['copperThickness1oz'], 0.102, 0.254, 2.54); +if (!T['copperThickness0.5oz']) { + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = 'copperThickness0.5oz'; e.isSetDefault = false; + setTrack(e, 0.089, 0.254, 2.54); + T['copperThickness0.5oz'] = e; +} +Object.assign(c['Physics']['Via Size']['viaSize'].form, + {viaOuterdiameterMin: 0.3, viaInnerdiameterMin: 0.2}); +if (!SS['copperThicknessInner0.5oz']) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = 'copperThicknessInner0.5oz'; e.isSetDefault = false; + const src = multi['Spacing']['Safe Spacing']['copperThicknessInner0.5oz'].table; + for (const k of Object.keys(e.tables)) + e.tables[k].content = JSON.parse(JSON.stringify(src)); + SS['copperThicknessInner0.5oz'] = e; +} + +// ── 2) 功率线宽规则 ── +for (const name of Object.keys(TRACKS)) { + const f = TRACKS[name]; + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = name; e.isSetDefault = false; e.unit = 'mm'; + setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax); + T[name] = e; +} + +// ── 3) 差分对几何 ── +const dp = c['Physics']['Differential Pair']['differentialPair'].form; +for (const k of Object.keys(dp.strokeWidthTables.data)) + Object.assign(dp.strokeWidthTables.data[k], + {minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault, + maxValue: DW.strokeWidthMax}); +for (const k of Object.keys(dp.diffPairSpacingTables.data)) + Object.assign(dp.diffPairSpacingTables.data[k], + {minValue: DW.differentailPairSpacingMin, + defaultValue: DW.differentailPairSpacingDefault}); +dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax; + +// ── 3b) 差分对对内间距条目（只给 net-by-net 用，不设为默认）── +if (!SS[PAIRRULE]) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = PAIRRULE; e.isSetDefault = false; + for (const tk of Object.keys(e.tables || {})) + for (const row of (e.tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number') row[i] = PAIRC; + SS[PAIRRULE] = e; +} + +// ── 4) 安全间距全表抬到下限 ── +let bumped = 0; +for (const key of Object.keys(SS)) + if (key !== PAIRRULE) + for (const tk of Object.keys(SS[key].tables || {})) + for (const row of (SS[key].tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number' && row[i] < MINC) { row[i] = MINC; bumped++; } + +// ── 5) 铺铜焊盘连接方式：给大电流网络单独开一条「全连接」条目 ── +const CZ = c['Plane']['Copper Zone']; +if (!CZ[PLANERULE]) { + const e = JSON.parse(JSON.stringify(CZ['copperRegion'])); + e.editName = PLANERULE; e.isSetDefault = false; + CZ[PLANERULE] = e; +} +for (const m of ['singleLayerPadModel', 'multiLayerPadModel']) + for (const k of Object.keys(CZ[PLANERULE].form[m].data)) + CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE; + +const ok = await D.overwriteCurrentRuleConfiguration(c); // ⚠️ 传本体 +return {ok: ok === true, bumped: bumped, name: cur.name, + track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)}; +""" + + +def push_config(): + r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE, + json.dumps(PAIR_RULE), PAIR_CLEARANCE, + json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT)) + if not r.get('ok'): + print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效') + sys.exit(1) + print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track'])) + print(u' 安全间距抬高 %d 格，间距条目 %s' % (r['bumped'], ' '.join(r['spacing']))) + print(u' 铺铜连接方式条目 %s' % ' '.join(r['plane'])) + print(u' 配置名现在是 “%s”' % r['name']) + + +def caveat(n): + print(u'') + print(u'──── 两条必须记住的事 ────') + print(u'⚠️ 别去 GUI 的 设计 → 设计规则… 里换“配置”下拉框。') + print(u' 换一下整套重置，五条线宽规则全被冲掉，') + print(u' %d 个网络的指派立刻悬空（DRC 不报错，线宽也就不生效）。' % n) + print(u'⚠️ 再从原理图导入一次变更之后，自动命名网可能改名。') + print(u' 顺序是：pcb1_import --apply → pcb1_parts_dump → **pcb1_rules --push**。') + print(u' 少跑中间那一步，反查用的就是旧网名，指派会静默落空。') + + +def _nums(o): + if isinstance(o, bool): + return [] + if isinstance(o, (int, float)): + return [float(o)] + if isinstance(o, dict): + return [v for x in o.values() for v in _nums(x)] + if isinstance(o, list): + return [v for x in o for v in _nums(x)] + return [] + + +def _find(o, key_sub): + if isinstance(o, dict): + for k, v in o.items(): + if key_sub.lower() in str(k).lower() and isinstance(v, (int, float)) \ + and not isinstance(v, bool): + return float(v) + for v in o.values(): + r = _find(v, key_sub) + if r is not None: + return r + elif isinstance(o, list): + for v in o: + r = _find(v, key_sub) + if r is not None: + return r + return None + + +AUDIT_JS = """ +await new Promise(r=>setTimeout(r,1500)); +const c = await eda.pcb_Drc.getCurrentRuleConfiguration(); +const rules = await eda.pcb_Drc.getNetRules(); +const nbn = await eda.pcb_Drc.getNetByNetRules(); +return { + cfgName: c && c.name, + layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(), + track: Object.keys(c.config.Physics['Track']), + cap: { + track1oz: c.config.Physics['Track']['copperThickness1oz'], + via: c.config.Physics['Via Size']['viaSize'], + half: !!c.config.Physics['Track']['copperThickness0.5oz'], + inner: !!c.config.Spacing['Safe Spacing']['copperThicknessInner0.5oz'], + }, + diff: c.config.Physics['Differential Pair'], + spacing: c.config.Spacing['Safe Spacing'], + pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(), + assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default') + .map(r => [r.name, r['Track']]).sort(), + planeEntries: Object.keys(c.config['Plane']['Copper Zone']), + planeMode: ((((c.config['Plane']['Copper Zone'][%s] || {}).form || {}) + .multiLayerPadModel || {}).data || {})['1'], + planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default') + .map(r => [r.name, r['Copper Zone']]).sort(), + nbn: ((nbn && nbn['Safe Spacing']) || []).length, +}; +""" + + +def audit(auto): + track = net_track_full(auto) + planes = plane_nets_full(auto) + r = call(AUDIT_JS % json.dumps(PLANE_RULE)) + bad = [] + + def chk(cond, good, msg): + print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg)) + if not cond: + bad.append(msg) + + print(u'──── 审计 ────') + chk(r['layers'] == 4, u'铜层数 4', u'铜层数是 %s，应为 4' % r['layers']) + + cap = r['cap'] + tmin = _find(cap['track1oz'], 'minValue') + if tmin is None: + tmin = _find(cap['track1oz'], 'strokeWidthMin') + vout = _find(cap['via'], 'viaOuterdiameterMin') + vin = _find(cap['via'], 'viaInnerdiameterMin') + okcap = (tmin is not None and abs(tmin - 0.102) < 5e-4 + and vout is not None and abs(vout - 0.3) < 5e-4 + and vin is not None and abs(vin - 0.2) < 5e-4 + and cap['half'] and cap['inner']) + chk(okcap, + u'四层板能力集已就位（最小线宽 %.3f / 过孔 %.2f-%.2f，含 0.5oz 内层条目）' + % (tmin or -1, vout or -1, vin or -1), + u'还是两层板能力集：最小线宽 %.3f（应 0.102）/ 过孔 %.2f-%.2f（应 0.30-0.20）' + u' / 0.5oz 线宽条目 %s / 内层间距条目 %s' + % (tmin if tmin is not None else -1, vout if vout is not None else -1, + vin if vin is not None else -1, + u'有' if cap['half'] else u'无', u'有' if cap['inner'] else u'无')) + print(u' （配置名 “%s”）' % r['cfgName']) + + for name in sorted(TRACK_RULES): + chk(name in r['track'], u'线宽规则 %s 存在' % name, + u'线宽规则 %s **不存在** —— 有 %d 个网络指着它，现在是悬空的' + % (name, sum(1 for _, t in r['assigned'] if t == name))) + + w = _find(r['diff'], 'strokeWidthDefault') + if w is None: + w = _find(r['diff'], 'defaultValue') + sp = _find(r['diff'], 'PairSpacingDefault') + if sp is None: + d2 = (r['diff'] or {}).get('differentialPair', {}).get('form', {}) \ + .get('diffPairSpacingTables') + sp = _find(d2, 'defaultValue') + chk(w is not None and abs(w - DIFF['strokeWidthDefault']) < 5e-3 + and sp is not None and abs(sp - DIFF['differentailPairSpacingDefault']) < 5e-3, + u'差分对几何 W %.3f / S %.3f mm' % (w or -1, sp or -1), + u'差分对几何是 W %.3f / S %.3f，应为 W %.2f / S %.2f mm' + % (w if w is not None else -1, sp if sp is not None else -1, + DIFF['strokeWidthDefault'], DIFF['differentailPairSpacingDefault'])) + + # ⚠️ 容差留 1e-4：mm→mil→mm 往返，0.2 回读是 0.19999959999999997 + vals = [v for v in _nums(r['spacing']) if 0 < v < 10] + mn = min(vals) if vals else -1 + chk(mn >= PAIR_CLEARANCE - 1e-4, + u'安全间距下限 %.4f mm（对内那条 %.2f）' % (mn, PAIR_CLEARANCE), + u'安全间距下限只有 %.4f mm' % mn) + others = [v for k in r['spacing'] if k != PAIR_RULE + for v in _nums(r['spacing'][k]) if 0 < v < 10] + mno = min(others) if others else -1 + chk(mno >= MIN_CLEARANCE - 1e-4, u'非差分对间距下限 %.4f mm' % mno, + u'非差分对间距下限只有 %.4f mm，应抬到 %.2f mm' % (mno, MIN_CLEARANCE)) + + want = sorted(n for n, _, _ in PAIRS) + chk(r['pairs'] == want, u'差分对 %d 对: %s' % (len(r['pairs']), ' '.join(r['pairs'])), + u'差分对对不上：有 %s，应为 %s' % (r['pairs'], want)) + + pm = r.get('planeMode') or {} + chk(PLANE_RULE in (r.get('planeEntries') or []) + and pm.get('connectMode') == PLANE_CONNECT_DIRECT, + u'铺铜连接方式条目 %s 在（connectMode=%s 全连接）' % (PLANE_RULE, pm.get('connectMode')), + u'没有 %s 条目或 connectMode 不是 %d —— 大电流通孔焊盘会退回十字花' + % (PLANE_RULE, PLANE_CONNECT_DIRECT)) + pa = r.get('planeAssigned') or [] + chk(sorted(n for n, _ in pa) == sorted(planes) + and all(v == PLANE_RULE for _, v in pa), + u'铺铜全连接指派 %d 个网络' % len(pa), + u'铺铜全连接指派是 %s，应为 %s 全挂 %s' % (pa, planes, PLANE_RULE)) + + got = dict(r['assigned']) + missing = [(n, t) for n, t in sorted(track.items()) if got.get(n) != t] + chk(not missing and len(got) == len(track), + u'线宽指派 %d 个网络（含 %d 个自动命名网）' % (len(got), len(auto)), + u'线宽指派对不上：板上 %d 个 / 应 %d 个；缺或错的 %s' + % (len(got), len(track), missing[:8])) + + chk(r['nbn'] == len(PAIRS), u'对内间距规则 %d 条' % r['nbn'], + u'对内间距规则 %d 条，应为 %d' % (r['nbn'], len(PAIRS))) + + if bad: + caveat(len(track)) + return not bad + + +def main(): + auto = resolve_auto() + track = net_track_full(auto) + planes = plane_nets_full(auto) + + print(u'下板 PCB1 规则：线宽 %d 条（%s），安全间距下限 %.2f mm，四层板能力集' + % (len(TRACK_RULES), ' '.join(sorted(TRACK_RULES)), MIN_CLEARANCE)) + print(u'差分对：W %.2f / S %.2f / 线长容差 %.1f mm，共 %d 对（%s）' + % (DIFF['strokeWidthDefault'], DIFF['differentailPairSpacingDefault'], + DIFF['differentailPairLenTolerMax'], len(PAIRS), + ' '.join(n for n, _, _ in PAIRS))) + print(u'自动命名网反查（事实来源 pcb1-parts.json）：') + for key in sorted(auto): + rule, probe, cross = AUTO_TRACK[key] + print(u' %-10s = %-9s -> %-7s (%s.%s / 校核 %s.%s)' + % (key, auto[key], rule, probe[0], probe[1], cross[0], cross[1])) + print(u'线宽指派共 %d 个网络；铺铜全连接 %d 个（%s）' + % (len(track), len(planes), ' '.join(planes))) + + if '--check' in sys.argv: + sys.exit(0 if audit(auto) else 1) + if '--push' not in sys.argv: + print(u'（未加 --push，没有下发；--check 审计当前状态）') + return + + push_config() + + n = call(""" +const P = %s; +let k = 0; +for (const d of await eda.pcb_Drc.getAllDifferentialPairs()) + await eda.pcb_Drc.deleteDifferentialPair(d.name); +for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; } +return k; +""" % json.dumps(PAIRS)) + print(u' 差分对 %d / %d 对' % (n, len(PAIRS))) + if n != len(PAIRS): + print(u' [!!] 有对没建上 —— 多半是网络名在这块板上不存在') + + # ⚠️ `getNetRules()` 回来的是**整张表**，`overwriteNetRules` 整表覆盖 —— + # 线宽（Track）和铺铜连接方式（Copper Zone）必须在**同一次读改写**里做完， + # 分两次写的话后一次会拿着旧快照把前一次冲掉。 + n = call(""" +const T = %s, PN = %s, PR = %s; +const pset = new Set(PN); +const rules = await eda.pcb_Drc.getNetRules(); +let k = 0, p = 0; +const seen = []; +for (const r of rules) { + if (r.type !== 'net') continue; + if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); } + if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; } +} +await eda.pcb_Drc.overwriteNetRules(rules); +return {track: k, plane: p, seen: seen}; +""" % (json.dumps(track, ensure_ascii=False), + json.dumps(planes, ensure_ascii=False), json.dumps(PLANE_RULE))) + print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(track))) + if n['track'] != len(track): + miss = sorted(set(track) - set(n['seen'])) + print(u' [!!] 板上找不到这些网络：%s' % ' '.join(miss)) + print(u' 悬空的指派 DRC 不报错 —— 先查 pcb1-parts.json 是不是过期了') + print(u' 铺铜全连接指派 %d / %d 个网络（%s）' + % (n['plane'], len(planes), ' '.join(planes))) + if n['plane'] != len(planes): + print(u' [!!] 有网络没指派上 —— 没指派 = 退回十字花，大电流铜面几何就量不准了') + + # ⚠️ overwriteNetByNetRules 是整表覆盖，先读回再合并。 + # ⚠️ 还要**清掉自己的陈迹**：单板时代 `pcb_rules.py` 在这里留下了 7 条 + # （USB1~5 / UPSTREAM / DEBUG）。那 6 对的网络已经随 Hub 搬去载板、板上不存在了， + # 只加不删的话表里会一直挂着 6 条指向空网络的规则。判据是「rule 名是我们的 + # USBPAIR、但不在本轮 PAIRS 里」—— 别人建的条目一律不动。 + n = call(""" +const PAIRS = %s, RULE = %s; +const cur = await eda.pcb_Drc.getNetByNetRules(); +const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : []; +const key = e => [e.net1.name, e.net2.name].sort().join('|'); +const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|'))); +const list = []; +let dropped = 0; +for (const e of old) { + if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; } // 自己的陈迹 + list.push(e); +} +const have = new Set(list.map(key)); +let k = 0; +for (const [name, dp, dm] of PAIRS) { + const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm}, + rule: RULE, copperRuleName: null, planeRuleName: null}; + if (have.has(key(e))) continue; + list.push(e); k++; +} +const ok = await eda.pcb_Drc.overwriteNetByNetRules( + {'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []}); +const back = await eda.pcb_Drc.getNetByNetRules(); +return {added: k, dropped: dropped, ok: ok === true, + now: (back['Safe Spacing'] || []).length}; +""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE))) + print(u' 对内间距规则：新增 %d 条 / 清掉过期 %d 条，现共 %d 条（%s = %.2f mm）' + % (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE)) + if n['now'] != len(PAIRS): + print(u' [!!] 应为 %d 条' % len(PAIRS)) + + call("await eda.pcb_Document.save(); return 1;") + print(u' 已保存') + caveat(len(track)) + + +if __name__ == '__main__': + main() diff --git a/.claude/pcb2-bottom-heights.json b/.claude/pcb2-bottom-heights.json index e577a3a..4cb05da 100644 --- a/.claude/pcb2-bottom-heights.json +++ b/.claude/pcb2-bottom-heights.json @@ -1,28 +1,44 @@ { "frame": "载板坐标系 mm，h = 元件离载板底面的高度；两板净空 13 mm ⇒ 下板同一 (x,y) 上元件高 ≤ 13 − h − 1", "parts": [ + { + "ref": "C604", + "x0": 116.33, + "y0": 72.73, + "x1": 117.67, + "y1": 73.27, + "h": 1.7 + }, + { + "ref": "C605", + "x0": 127.33, + "y0": 72.73, + "x1": 128.67, + "y1": 73.27, + "h": 1.7 + }, { "ref": "C701", - "x0": 40.39, - "y0": 100.99, - "x1": 43.79, - "y1": 102.34, + "x0": 40.3, + "y0": 100.33, + "x1": 43.7, + "y1": 101.67, "h": 1.7 }, { "ref": "C702", - "x0": 111.88, - "y0": 100.99, - "x1": 115.3, - "y1": 102.34, + "x0": 111.79, + "y0": 100.33, + "x1": 115.21, + "y1": 101.67, "h": 1.7 }, { "ref": "C703", - "x0": 183.39, - "y0": 100.99, - "x1": 186.79, - "y1": 102.34, + "x0": 183.3, + "y0": 100.33, + "x1": 186.7, + "y1": 101.67, "h": 1.7 }, { @@ -35,34 +51,34 @@ }, { "ref": "C705", - "x0": 140.55, + "x0": 140.54, "y0": 32.83, - "x1": 143.95, + "x1": 143.96, "y1": 34.17, "h": 1.7 }, { "ref": "C711", - "x0": 32.92, - "y0": 101.39, - "x1": 34.26, - "y1": 101.93, + "x0": 32.83, + "y0": 100.73, + "x1": 34.17, + "y1": 101.27, "h": 1.7 }, { "ref": "C712", - "x0": 104.42, - "y0": 101.39, - "x1": 105.76, - "y1": 101.93, + "x0": 104.33, + "y0": 100.73, + "x1": 105.67, + "y1": 101.27, "h": 1.7 }, { "ref": "C713", - "x0": 175.92, - "y0": 101.39, - "x1": 177.26, - "y1": 101.93, + "x0": 175.83, + "y0": 100.73, + "x1": 177.17, + "y1": 101.27, "h": 1.7 }, { @@ -83,26 +99,26 @@ }, { "ref": "C721", - "x0": 30.42, - "y0": 101.39, - "x1": 31.76, - "y1": 101.93, + "x0": 30.33, + "y0": 100.73, + "x1": 31.67, + "y1": 101.27, "h": 1.7 }, { "ref": "C722", - "x0": 101.92, - "y0": 101.39, - "x1": 103.26, - "y1": 101.93, + "x0": 101.83, + "y0": 100.73, + "x1": 103.17, + "y1": 101.27, "h": 1.7 }, { "ref": "C723", - "x0": 173.42, - "y0": 101.39, - "x1": 174.76, - "y1": 101.93, + "x0": 173.33, + "y0": 100.73, + "x1": 174.67, + "y1": 101.27, "h": 1.7 }, { @@ -131,10 +147,18 @@ }, { "ref": "C737", - "x0": 90.66, - "y0": 53.14, - "x1": 95.34, - "y1": 54.86, + "x0": 91.22, + "y0": 53.32, + "x1": 95.12, + "y1": 54.68, + "h": 1.8 + }, + { + "ref": "C739", + "x0": 199.23, + "y0": 67.83, + "x1": 199.77, + "y1": 69.17, "h": 1.7 }, { @@ -243,26 +267,26 @@ }, { "ref": "C761", - "x0": 29.42, - "y0": 106.39, - "x1": 30.76, - "y1": 106.93, + "x0": 29.33, + "y0": 105.73, + "x1": 30.67, + "y1": 106.27, "h": 1.7 }, { "ref": "C762", - "x0": 100.92, - "y0": 106.39, - "x1": 102.26, - "y1": 106.93, + "x0": 100.83, + "y0": 105.73, + "x1": 102.17, + "y1": 106.27, "h": 1.7 }, { "ref": "C763", - "x0": 172.42, - "y0": 106.39, - "x1": 173.76, - "y1": 106.93, + "x0": 172.33, + "y0": 105.73, + "x1": 173.67, + "y1": 106.27, "h": 1.7 }, { @@ -283,146 +307,146 @@ }, { "ref": "C801", - "x0": 31.34, - "y0": 110.96, - "x1": 44.24, - "y1": 121.76, + "x0": 31.25, + "y0": 110.3, + "x1": 44.15, + "y1": 121.1, "h": 10.5 }, { "ref": "C802", - "x0": 56.25, - "y0": 111.8, - "x1": 60.93, - "y1": 113.52, + "x0": 56.17, + "y0": 111.14, + "x1": 60.84, + "y1": 112.86, "h": 1.7 }, { "ref": "C803", - "x0": 56.75, - "y0": 108.3, - "x1": 61.43, - "y1": 110.02, + "x0": 56.66, + "y0": 107.64, + "x1": 61.33, + "y1": 109.36, "h": 1.7 }, { "ref": "C804", - "x0": 51.75, - "y0": 108.3, - "x1": 56.42, - "y1": 110.02, + "x0": 51.66, + "y0": 107.64, + "x1": 56.34, + "y1": 109.36, "h": 1.7 }, { "ref": "C805", - "x0": 46.75, - "y0": 108.3, - "x1": 51.43, - "y1": 110.02, + "x0": 46.66, + "y0": 107.64, + "x1": 51.33, + "y1": 109.36, "h": 1.7 }, { "ref": "C806", - "x0": 53.92, - "y0": 112.39, - "x1": 55.26, - "y1": 112.93, + "x0": 53.83, + "y0": 111.73, + "x1": 55.17, + "y1": 112.27, "h": 1.7 }, { "ref": "C811", - "x0": 102.84, - "y0": 110.96, - "x1": 115.74, - "y1": 121.76, + "x0": 102.75, + "y0": 110.3, + "x1": 115.65, + "y1": 121.1, "h": 10.5 }, { "ref": "C812", - "x0": 127.75, - "y0": 111.8, - "x1": 132.42, - "y1": 113.52, + "x0": 127.66, + "y0": 111.14, + "x1": 132.34, + "y1": 112.86, "h": 1.7 }, { "ref": "C813", - "x0": 128.25, - "y0": 108.3, - "x1": 132.93, - "y1": 110.02, + "x0": 128.16, + "y0": 107.64, + "x1": 132.84, + "y1": 109.36, "h": 1.7 }, { "ref": "C814", - "x0": 123.25, - "y0": 108.3, - "x1": 127.92, - "y1": 110.02, + "x0": 123.16, + "y0": 107.64, + "x1": 127.83, + "y1": 109.36, "h": 1.7 }, { "ref": "C815", - "x0": 118.25, - "y0": 108.3, - "x1": 122.92, - "y1": 110.02, + "x0": 118.16, + "y0": 107.64, + "x1": 122.84, + "y1": 109.36, "h": 1.7 }, { "ref": "C816", - "x0": 125.42, - "y0": 112.39, - "x1": 126.76, - "y1": 112.93, + "x0": 125.33, + "y0": 111.73, + "x1": 126.67, + "y1": 112.27, "h": 1.7 }, { "ref": "C821", - "x0": 174.34, - "y0": 110.96, - "x1": 187.24, - "y1": 121.76, + "x0": 174.25, + "y0": 110.3, + "x1": 187.15, + "y1": 121.1, "h": 10.5 }, { "ref": "C822", - "x0": 199.25, - "y0": 111.8, - "x1": 203.92, - "y1": 113.52, + "x0": 199.17, + "y0": 111.14, + "x1": 203.84, + "y1": 112.86, "h": 1.7 }, { "ref": "C823", - "x0": 199.75, - "y0": 108.3, - "x1": 204.43, - "y1": 110.02, + "x0": 199.67, + "y0": 107.64, + "x1": 204.34, + "y1": 109.36, "h": 1.7 }, { "ref": "C824", - "x0": 194.75, - "y0": 108.3, - "x1": 199.43, - "y1": 110.02, + "x0": 194.66, + "y0": 107.64, + "x1": 199.34, + "y1": 109.36, "h": 1.7 }, { "ref": "C825", - "x0": 189.75, - "y0": 108.3, - "x1": 194.42, - "y1": 110.02, + "x0": 189.67, + "y0": 107.64, + "x1": 194.34, + "y1": 109.36, "h": 1.7 }, { "ref": "C826", - "x0": 196.92, - "y0": 112.39, - "x1": 198.26, - "y1": 112.93, + "x0": 196.83, + "y0": 111.73, + "x1": 198.17, + "y1": 112.27, "h": 1.7 }, { @@ -435,17 +459,17 @@ }, { "ref": "C832", - "x0": 51.92, + "x0": 51.91, "y0": 21.64, - "x1": 56.59, + "x1": 56.58, "y1": 23.36, "h": 1.7 }, { "ref": "C833", - "x0": 51.42, + "x0": 51.41, "y0": 25.14, - "x1": 56.09, + "x1": 56.08, "y1": 26.86, "h": 1.7 }, @@ -453,7 +477,7 @@ "ref": "C834", "x0": 56.41, "y0": 25.14, - "x1": 61.08, + "x1": 61.09, "y1": 26.86, "h": 1.7 }, @@ -461,7 +485,7 @@ "ref": "C835", "x0": 61.41, "y0": 25.14, - "x1": 66.09, + "x1": 66.08, "y1": 26.86, "h": 1.7 }, @@ -491,7 +515,7 @@ }, { "ref": "C843", - "x0": 122.92, + "x0": 122.91, "y0": 25.14, "x1": 127.59, "y1": 26.86, @@ -509,7 +533,7 @@ "ref": "C845", "x0": 132.91, "y0": 25.14, - "x1": 137.58, + "x1": 137.59, "y1": 26.86, "h": 1.7 }, @@ -547,33 +571,33 @@ }, { "ref": "J61", - "x0": 5.42, - "y0": 83.71, - "x1": 13.76, - "y1": 88.91, + "x0": 5.33, + "y0": 83.05, + "x1": 13.68, + "y1": 88.25, "h": 3.6 }, { "ref": "J62", - "x0": 76.92, - "y0": 83.71, - "x1": 85.27, - "y1": 88.91, + "x0": 76.82, + "y0": 83.05, + "x1": 85.17, + "y1": 88.25, "h": 3.6 }, { "ref": "J63", - "x0": 148.41, - "y0": 83.71, - "x1": 156.76, - "y1": 88.91, + "x0": 148.32, + "y0": 83.05, + "x1": 156.68, + "y1": 88.25, "h": 3.6 }, { "ref": "J64", - "x0": 99.08, + "x0": 99.07, "y0": 46.25, - "x1": 107.42, + "x1": 107.43, "y1": 51.45, "h": 3.6 }, @@ -581,72 +605,72 @@ "ref": "J65", "x0": 170.58, "y0": 46.25, - "x1": 178.92, + "x1": 178.93, "y1": 51.45, "h": 3.6 }, { "ref": "J71", - "x0": 13.31, - "y0": 91.36, - "x1": 25.87, - "y1": 93.96, + "x0": 13.22, + "y0": 90.7, + "x1": 25.77, + "y1": 93.3, "h": 1.0 }, { "ref": "J72", - "x0": 84.82, - "y0": 91.36, - "x1": 97.37, - "y1": 93.96, + "x0": 84.73, + "y0": 90.7, + "x1": 97.28, + "y1": 93.3, "h": 1.0 }, { "ref": "J73", - "x0": 156.31, - "y0": 91.36, - "x1": 168.86, - "y1": 93.96, + "x0": 156.22, + "y0": 90.7, + "x1": 168.77, + "y1": 93.3, "h": 1.0 }, { "ref": "J74", - "x0": 86.97, + "x0": 86.98, "y0": 41.2, - "x1": 99.52, + "x1": 99.53, "y1": 43.8, "h": 1.0 }, { "ref": "J75", - "x0": 158.48, + "x0": 158.47, "y0": 41.2, - "x1": 171.03, + "x1": 171.02, "y1": 43.8, "h": 1.0 }, { "ref": "J81", - "x0": 45.74, - "y0": 110.66, - "x1": 52.84, - "y1": 114.66, + "x0": 45.65, + "y0": 110.0, + "x1": 52.75, + "y1": 114.0, "h": 0.5 }, { "ref": "J82", - "x0": 117.24, - "y0": 110.66, - "x1": 124.34, - "y1": 114.66, + "x0": 117.15, + "y0": 110.0, + "x1": 124.25, + "y1": 114.0, "h": 0.5 }, { "ref": "J83", - "x0": 188.74, - "y0": 110.66, - "x1": 195.84, - "y1": 114.66, + "x0": 188.65, + "y0": 110.0, + "x1": 195.75, + "y1": 114.0, "h": 0.5 }, { @@ -665,28 +689,396 @@ "y1": 24.5, "h": 0.5 }, + { + "ref": "Q103", + "x0": 62.0, + "y0": 121.72, + "x1": 65.0, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q104", + "x0": 58.5, + "y0": 121.72, + "x1": 61.5, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q105", + "x0": 55.0, + "y0": 121.72, + "x1": 58.0, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q203", + "x0": 133.5, + "y0": 121.72, + "x1": 136.5, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q204", + "x0": 130.0, + "y0": 121.72, + "x1": 133.0, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q205", + "x0": 126.5, + "y0": 121.72, + "x1": 129.5, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q303", + "x0": 205.0, + "y0": 121.72, + "x1": 208.0, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q304", + "x0": 201.5, + "y0": 121.72, + "x1": 204.5, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q305", + "x0": 198.0, + "y0": 121.72, + "x1": 201.0, + "y1": 124.27, + "h": 2.0 + }, + { + "ref": "Q403", + "x0": 47.75, + "y0": 10.23, + "x1": 50.75, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "Q404", + "x0": 51.25, + "y0": 10.23, + "x1": 54.25, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "Q405", + "x0": 54.75, + "y0": 10.23, + "x1": 57.75, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "Q503", + "x0": 119.25, + "y0": 10.23, + "x1": 122.25, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "Q504", + "x0": 122.75, + "y0": 10.23, + "x1": 125.75, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "Q505", + "x0": 126.25, + "y0": 10.23, + "x1": 129.25, + "y1": 12.78, + "h": 2.0 + }, + { + "ref": "R120", + "x0": 63.23, + "y0": 118.78, + "x1": 63.77, + "y1": 120.22, + "h": 0.5 + }, + { + "ref": "R121", + "x0": 63.23, + "y0": 116.28, + "x1": 63.77, + "y1": 117.72, + "h": 0.5 + }, + { + "ref": "R122", + "x0": 59.73, + "y0": 118.78, + "x1": 60.27, + "y1": 120.22, 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4222.400000000001]}, {"d": "U34", "x": 2283.46, "y": 2362.2, "rot": 90, "n": 8, "bb": [2197.26, 2217.3399999999997, 2369.66, 2507.14]}, {"d": "R423", "x": 2076.77, "y": 688.98, "rot": 90, "n": 2, "bb": [2048.54, 678.3600000000002, 2104.94, 699.6600000000002]}, {"d": "U41", "x": 1318.9, "y": 4173.23, "rot": 180, "n": 6, "bb": [1244.0500000000002, 4124, 1393.6500000000003, 4222.400000000001]}, {"d": "C845", "x": 5324.8, "y": 1023.6199999999999, "rot": 0, "n": 2, "bb": [5232.85, 989.6399999999998, 5416.75, 1057.6399999999999]}, {"d": "U42", "x": 4133.86, "y": 4173.23, "rot": 180, "n": 6, "bb": [4059.0699999999993, 4124, 4208.669999999999, 4222.400000000001]}, {"d": "R745", "x": 5777.560000000001, "y": 1122.05, "rot": 0, "n": 2, "bb": [5749.35, 1111.35, 5805.75, 1132.65]}, {"d": "J41", "x": 2648.82, "y": 4796.85, "rot": 180, "n": 1, "bb": [2619.29, 4767.250000000001, 2678.3900000000003, 4826.350000000001]}, {"d": "J42", "x": 2700, "y": 4749.21, "rot": 180, "n": 1, "bb": [2670.45, 4719.67, 2729.55, 4778.77]}, {"d": "J43", "x": 2697.24, "y": 4852.76, "rot": 180, "n": 1, "bb": [2667.7299999999996, 4823.17, 2726.83, 4882.27]}, {"d": "J44", "x": 2753.94, "y": 4803.54, "rot": 180, "n": 1, "bb": [2724.43, 4774.03, 2783.53, 4833.13]}, {"d": "J45", "x": 5463.779999999999, "y": 4796.85, "rot": 180, "n": 1, "bb": [5434.209999999997, 4767.250000000001, 5493.309999999998, 4826.350000000001]}, {"d": "J46", "x": 5514.96, "y": 4749.21, "rot": 180, "n": 1, "bb": [5485.37, 4719.67, 5544.47, 4778.77]}, {"d": "J47", "x": 5512.200000000001, "y": 4852.76, "rot": 180, "n": 1, "bb": [5482.6500000000015, 4823.17, 5541.750000000002, 4882.27]}, {"d": "J48", "x": 5568.9, "y": 4803.54, "rot": 180, "n": 1, "bb": [5539.349999999999, 4774.03, 5598.45, 4833.13]}, {"d": "J49", "x": 8278.74, "y": 4796.85, "rot": 180, "n": 1, "bb": [8249.23, 4767.250000000001, 8308.329999999998, 4826.350000000001]}, {"d": "J50", "x": 8329.92, "y": 4749.21, "rot": 180, "n": 1, "bb": [8300.390000000001, 4719.67, 8359.49, 4778.77]}, {"d": "J51", "x": 8327.17, "y": 4852.76, "rot": 180, "n": 1, "bb": [8297.59, 4823.17, 8356.689999999999, 4882.27]}, {"d": "J52", "x": 8383.86, "y": 4803.54, "rot": 180, "n": 1, "bb": [8354.270000000002, 4774.03, 8413.37, 4833.13]}, {"d": "J53", "x": 1790.1600000000003, "y": 498.43000000000006, "rot": 0, "n": 1, "bb": [1760.65, 468.84999999999997, 1819.75, 527.9499999999999]}, {"d": "J54", "x": 1738.98, "y": 546.06, "rot": 0, "n": 1, "bb": [1709.45, 516.5500000000001, 1768.55, 575.65]}, {"d": "J55", "x": 1741.73, "y": 442.52, "rot": 0, "n": 1, "bb": [1712.15, 412.95, 1771.25, 472.05]}, {"d": "J56", "x": 1685.04, "y": 491.73, "rot": 0, "n": 1, "bb": [1655.45, 462.15, 1714.55, 521.25]}, {"d": "J57", "x": 4605.12, "y": 498.43000000000006, "rot": 0, "n": 1, "bb": [4575.55, 468.84999999999997, 4634.650000000001, 527.9499999999999]}, {"d": "J58", "x": 4553.94, "y": 546.06, "rot": 0, "n": 1, "bb": [4524.349999999999, 516.5500000000001, 4583.45, 575.65]}, {"d": "J59", "x": 4556.69, "y": 442.52, "rot": 0, "n": 1, "bb": [4527.15, 412.95, 4586.25, 472.05]}, {"d": "J60", "x": 4500, "y": 491.73, "rot": 0, "n": 1, "bb": [4470.45, 462.15, 4529.55, 521.25]}, {"d": "C737", "x": 3668, "y": 2125.98, "rot": 180, "n": 2, "bb": [3591.25, 2099.25, 3744.75, 2152.75]}, {"d": "R900", "x": 4045.276, "y": 2305.118, "rot": 0, "n": 2, "bb": [4017.0499999999997, 2294.486, 4073.4500000000003, 2315.786]}, {"d": "R901", "x": 4055.9450000000006, "y": 2339.134, "rot": 0, "n": 2, "bb": [4027.75, 2328.518, 4084.15, 2349.818]}, {"d": "R902", "x": 4198.228, "y": 2446.654, "rot": 0, "n": 2, "bb": [4170.05, 2435.958, 4226.45, 2457.2580000000003]}, {"d": "R903", "x": 4158.74, "y": 2832.992, "rot": 90, "n": 2, "bb": [4130.598, 2822.302, 4186.897999999999, 2843.6020000000003]}, {"d": "R904", "x": 4073.15, "y": 2898.898, "rot": 0, "n": 2, "bb": [4044.95, 2888.246, 4101.349999999999, 2909.5460000000003]}] \ No newline at end of file diff --git a/.claude/pcb2_clear.py b/.claude/pcb2_clear.py index 8e8becc..e46a81f 100644 --- a/.claude/pcb2_clear.py +++ b/.claude/pcb2_clear.py @@ -27,7 +27,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' +PCB = '942ed1560d81c1e7' MIL = 39.3700787401575 COPPER = (1, 15, 16, 2) diff --git a/.claude/pcb2_del_box.py b/.claude/pcb2_del_box.py index 191c216..1b2e8ac 100644 --- a/.claude/pcb2_del_box.py +++ b/.claude/pcb2_del_box.py @@ -1,94 +1,94 @@ -# -*- coding: utf-8 -*- -u"""删掉指定矩形框里的**某个网络**的走线与过孔（板坐标或站内坐标）。 - - /c/Python314/python .claude/pcb2_del_box.py GND --site 54.9 36.8 56.5 37.5 - /c/Python314/python .claude/pcb2_del_box.py GND --board 100 60 102 62 - 加 `--push` 才真删，不加只列出来。 - -## 为什么需要它 - -板上的铜是好几个脚本各画各的（`pcb2_dp_long` / `pcb2_fanout` / `pcb2_vo_vias` / `pcb2_route_sig`）， -每个脚本的 `--push` 只删**自己上一轮**画的东西。挪了一个元件之后， -它那颗扇出孔就成了没人认领的孤儿 —— 谁的删除逻辑都不管，DRC 只报一条 -「过孔没连上任何东西」，很容易被当成噪声放过去。 - -## 判据 - -- **完全落在框里**才删（导线两端都在框内、过孔中心在框内）。半进半出的一律不动， - 免得把一条长线截断一半留在板上 —— 那比不删还糟。 -- `--site` 是站内坐标，会自动展开到五个手机位（`pcb2_place.to_board`，4/5 站镜像）。 -""" -import json -import os -import sys - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -from eda import run -from pcb2_place import SITES, to_board - -PCB = 'f126ffb29c92f9b2' -MIL = 39.3700787401575 - - -def boxes_from_argv(): - if '--site' in sys.argv: - i = sys.argv.index('--site') - u0, v0, u1, v1 = [float(v) for v in sys.argv[i + 1:i + 5]] - out = [] - for n in SITES: - ax, ay, _ = to_board(n, u0, v0) - bx, by, _ = to_board(n, u1, v1) - out.append((min(ax, bx), min(ay, by), max(ax, bx), max(ay, by))) - return out - i = sys.argv.index('--board') - x0, y0, x1, y1 = [float(v) for v in sys.argv[i + 1:i + 5]] - return [(min(x0, x1), min(y0, y1), max(x0, x1), max(y0, y1))] - - -JS = u""" -await eda.dmt_EditorControl.openDocument('%s'); -await new Promise(r => setTimeout(r, 1500)); -const M = 39.3700787401575, q = v => Math.round(v / M * 1e4) / 1e4; -const NET = %s, B = %s, DO = %s; -const inB = (x, y) => B.some(b => x >= b[0] && x <= b[2] && y >= b[1] && y <= b[3]); -const lines = [], vias = []; -for (const l of await eda.pcb_PrimitiveLine.getAll()) { - if ((l.net || '') !== NET) continue; - if (l.layer !== 1 && l.layer !== 2) continue; - if (inB(q(l.startX), q(l.startY)) && inB(q(l.endX), q(l.endY))) - lines.push([l.primitiveId, q(l.startX), q(l.startY), q(l.endX), q(l.endY), l.layer]); -} -for (const v of await eda.pcb_PrimitiveVia.getAll()) { - if ((v.net || '') !== NET) continue; - if (inB(q(v.x), q(v.y))) vias.push([v.primitiveId, q(v.x), q(v.y)]); -} -if (DO) { - if (lines.length) await eda.pcb_PrimitiveLine.delete(lines.map(l => l[0])); - if (vias.length) await eda.pcb_PrimitiveVia.delete(vias.map(v => v[0])); - await eda.pcb_Document.save(); -} -return {lines: lines.map(l => l.slice(1)), vias: vias.map(v => v.slice(1)), did: DO}; -""" - - -def main(): - net = sys.argv[1] - boxes = boxes_from_argv() - do = '--push' in sys.argv - r = run(JS % (PCB, json.dumps(net), json.dumps(boxes), 'true' if do else 'false'), - timeout=600) - if not r.get('success'): - sys.exit(u'失败: ' + json.dumps(r, ensure_ascii=False)[:400]) - x = r['result'] - print(u'%s：%d 个框里有 %s 的导线 %d 条 / 过孔 %d 个' - % (u'已删' if do else u'（预览，加 --push 才删）', len(boxes), net, - len(x['lines']), len(x['vias']))) - for l in x['lines'][:20]: - print(u' 线 L%d (%.3f, %.3f) -> (%.3f, %.3f)' % (l[4], l[0], l[1], l[2], l[3])) - for v in x['vias'][:20]: - print(u' 孔 (%.3f, %.3f)' % (v[0], v[1])) - - -if __name__ == '__main__': - main() +# -*- coding: utf-8 -*- +u"""删掉指定矩形框里的**某个网络**的走线与过孔（板坐标或站内坐标）。 + + /c/Python314/python .claude/pcb2_del_box.py GND --site 54.9 36.8 56.5 37.5 + /c/Python314/python .claude/pcb2_del_box.py GND --board 100 60 102 62 + 加 `--push` 才真删，不加只列出来。 + +## 为什么需要它 + +板上的铜是好几个脚本各画各的（`pcb2_dp_long` / `pcb2_fanout` / `pcb2_vo_vias` / `pcb2_route_sig`）， +每个脚本的 `--push` 只删**自己上一轮**画的东西。挪了一个元件之后， +它那颗扇出孔就成了没人认领的孤儿 —— 谁的删除逻辑都不管，DRC 只报一条 +「过孔没连上任何东西」，很容易被当成噪声放过去。 + +## 判据 + +- **完全落在框里**才删（导线两端都在框内、过孔中心在框内）。半进半出的一律不动， + 免得把一条长线截断一半留在板上 —— 那比不删还糟。 +- `--site` 是站内坐标，会自动展开到五个手机位（`pcb2_place.to_board`，4/5 站镜像）。 +""" +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from eda import run +from pcb2_place import SITES, to_board + +PCB = '942ed1560d81c1e7' +MIL = 39.3700787401575 + + +def boxes_from_argv(): + if '--site' in sys.argv: + i = sys.argv.index('--site') + u0, v0, u1, v1 = [float(v) for v in sys.argv[i + 1:i + 5]] + out = [] + for n in SITES: + ax, ay, _ = to_board(n, u0, v0) + bx, by, _ = to_board(n, u1, v1) + out.append((min(ax, bx), min(ay, by), max(ax, bx), max(ay, by))) + return out + i = sys.argv.index('--board') + x0, y0, x1, y1 = [float(v) for v in sys.argv[i + 1:i + 5]] + return [(min(x0, x1), min(y0, y1), max(x0, x1), max(y0, y1))] + + +JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 1500)); +const M = 39.3700787401575, q = v => Math.round(v / M * 1e4) / 1e4; +const NET = %s, B = %s, DO = %s; +const inB = (x, y) => B.some(b => x >= b[0] && x <= b[2] && y >= b[1] && y <= b[3]); +const lines = [], vias = []; +for (const l of await eda.pcb_PrimitiveLine.getAll()) { + if ((l.net || '') !== NET) continue; + if (l.layer !== 1 && l.layer !== 2) continue; + if (inB(q(l.startX), q(l.startY)) && inB(q(l.endX), q(l.endY))) + lines.push([l.primitiveId, q(l.startX), q(l.startY), q(l.endX), q(l.endY), l.layer]); +} +for (const v of await eda.pcb_PrimitiveVia.getAll()) { + if ((v.net || '') !== NET) continue; + if (inB(q(v.x), q(v.y))) vias.push([v.primitiveId, q(v.x), q(v.y)]); +} +if (DO) { + if (lines.length) await eda.pcb_PrimitiveLine.delete(lines.map(l => l[0])); + if (vias.length) await eda.pcb_PrimitiveVia.delete(vias.map(v => v[0])); + await eda.pcb_Document.save(); +} +return {lines: lines.map(l => l.slice(1)), vias: vias.map(v => v.slice(1)), did: DO}; +""" + + +def main(): + net = sys.argv[1] + boxes = boxes_from_argv() + do = '--push' in sys.argv + r = run(JS % (PCB, json.dumps(net), json.dumps(boxes), 'true' if do else 'false'), + timeout=600) + if not r.get('success'): + sys.exit(u'失败: ' + json.dumps(r, ensure_ascii=False)[:400]) + x = r['result'] + print(u'%s：%d 个框里有 %s 的导线 %d 条 / 过孔 %d 个' + % (u'已删' if do else u'（预览，加 --push 才删）', len(boxes), net, + len(x['lines']), len(x['vias']))) + for l in x['lines'][:20]: + print(u' 线 L%d (%.3f, %.3f) -> (%.3f, %.3f)' % (l[4], l[0], l[1], l[2], l[3])) + for v in x['vias'][:20]: + print(u' 孔 (%.3f, %.3f)' % (v[0], v[1])) + + +if __name__ == '__main__': + main() diff --git a/.claude/pcb2_dp_long.py b/.claude/pcb2_dp_long.py index a596636..452d5d9 100644 --- a/.claude/pcb2_dp_long.py +++ b/.claude/pcb2_dp_long.py @@ -1,245 +1,247 @@ -# -*- coding: utf-8 -*- -u"""六对**长差分**（USB1~5 的 U32↔U5n + UPSTREAM 的 U32↔J23）+ Hub 西缘被 D± 夹住的两条 +3V3 车道。 - -**v5 版（2026-09-06，载板全部底层、接口边朝板边）。** v3 版存档在 `obsolete/pcb2_dp_long_v3_2026-09-06.py`。 -被 `pcb2_route_dp.py` import；校核 / 下发都用那个脚本，这里只放坐标。 - -## 出发点：U32 西缘的 12 条车道 - -U32（QFN-64，**底层**，中心 (100, 68)）的 D± 全在**西缘 x 95.55**，0.5 脚距、南→北： - - 1DM 64.25 | 1DP 64.75 | 2DM 65.25 | 2DP 65.75 | pin5 +3V3 66.25 | - 3DM 66.75 | 3DP 67.25 | 4DM 67.75 | 4DP 68.25 | pin10 +3V3 68.75 | - 5DM 69.25 | 5DP 69.75 | pin13 GND 70.25 | 14~16 NC - -目的地却是四面八方：1→西北远处 (U51 22/24, 87)、2→正北 (U52 94/96, 87)、3→东北 (U53 165/167, 87)、 -4→西南 (U54 88.6/90.5, 48)、5→东南 (U55 160/162, 48)、UP→正东 (J23 212, 61~62)。 - -### 定下来的走法（理由都在代码注释里） - -| 车道 | 层 | 走法 | -|---|---|---| -| pair 1 | 底 | 直着西行 y 64.25/64.75 到 x 22.34/22.82，北上进 U51 | -| pair 2 | 底 | 西行到 89.27/89.75 北上，y 80 处 45° 斜到 93.84/95.74 进 U52 | -| pin 5 | 底→顶 | 西行到 90.4，跟着 pair 3 北上到 70.5 打孔翻顶层，西去 (88.2, 70.5) 再下来进 C747 | -| pair 3 | 底 | 西行到 91.05/91.53 北上，y 76.50/76.98 东行，过了 pair 5 之后压到 75.40/75.88 从 MH 焊盘下面钻过去，x 165 北上 | -| pair 4 | **顶** | 西行到 x 92.2 打孔上顶层（DM 67.95 / DP 68.85），沿 x 91.5/91.98 南下到 y 52，斜到 (89.6/90.5, 50.3) 下来进 U54 | -| pin 10 | 底 | 西行到 92.95，跟着 pair 5 北上，斜到 (92.5, 70.0) 进 C748；(92.5, 70.0) 上有一个孔接顶层 +3V3 干线 | -| pair 5 | 底 | 西行到 93.47/93.95 北上，y 75.50/75.98 东行到 110.30/110.78 南下，**y 59.2~61.6 翻顶层跨过 UP**，y 52.5/52.98 东行，x 160.1/162 南下进 U55 | -| UP | 底 | 南缘 pin58/59 从 C743/C745 之间的竖井下到 60.12/60.60，一路东行，x 205 抬到 61.25/61.75 进 J23 B6/A7 | -| +3V3 干线 | 顶 | U31 pin2 旁 (90.3, 61.65) 打孔上顶层，北上到 (90.4, 70.5)（与 pin5 的孔汇合），东去 (92.5, 70.0) 下来进 C748 | - -### 三条关键约束 - -1. **0.5 脚距的车道之间打不了孔**：孔要离两边车道各 0.645，所以只有当邻居车道都拐走之后才能打。 - 北边的先拐（pair 5 → pin 10 → pair 4 打孔 → pair 3 → pin 5 → pair 2），像剥洋葱。 - pair 4 的两个孔卡在 DP3 的横车道（y 67.25，要求孔心 ≥ 67.895）和 pin10 北上车道（x 92.95，要求孔心 x ≤ 92.305）之间， - 所以 DP4 得先在 x 93.1→92.5 抬到 68.85 再打孔，两孔上下错 0.9。 -2. **顶层只走 Inner1 是 GND 的地方**：Hub 周围 x ≥ 87（VO4 岛东界已从 89 收到 87）、y < 75.5（VO2 的 Hub 北横带以南）是一整片 GND； - pair 4 全程、pair 5 跨 UP 的那 2.4 mm、+3V3 干线都在这片里。pair 5 的跨越点 x 110~111.5 也在 VO4/VO5 之间的 GND 窗口里。 -3. **平行 45° 斜段要保持 0.48 间距**：两根线各自的拐点不能同 x/同 y，第一拐**内侧**那根要早拐 0.2 - （0.48·(√2−1)），否则斜段上的垂直间距只剩 0.34。文件里所有成对斜段都按这个写。 - -### 每个站点最后一段 - -U5n 朝 Hub 那排的 DP/DM 相距 1.9 mm，车道并排 0.48 到最后 1.4 mm 再用 45° 分开， -分开的那根一律是**转弯时的外侧**，所以到站不用交叉 —— 五对都核过了 -（转弯规则：向右拐时左边那根变成外侧，连拐两次回到原样）。 -""" -import math - -L_TOP, L_BOT = 1, 2 -W = 0.28 - - -def chamfer(pts, r=0.35): - u"""把折线的拐点切成 45°。换层点（相邻两点层不同）不切。 - - ⚠ 点的 layer/width 语义是「从这一点到下一点」，所以在拐点 b 处插入的 - b1 用**前一段**的层/宽（它承担斜切段），b2 用 b 自己的。 - """ - if len(pts) < 3: - return list(pts) - out = [pts[0]] - for i in range(1, len(pts) - 1): - a, b, c = pts[i - 1], pts[i], pts[i + 1] - if a[2] != b[2] or b[2] != c[2]: # 拐点两侧不同层 -> 这是过孔点 - out.append(b) - continue - ax, ay = b[0] - a[0], b[1] - a[1] - cx, cy = c[0] - b[0], c[1] - b[1] - la, lc = math.hypot(ax, ay), math.hypot(cx, cy) - if la < 1e-9 or lc < 1e-9: - out.append(b) - continue - # 共线就不用切；**已经是 45° 的拐（正 + 斜）也不切** —— 再切一刀会变成两个 22.5°， - # 而且切出来的那一小段会向内侧挪 0.1 mm，实测把 DP4 的抬升段切进了 pin10 车道的净距圈（0.125）。 - dot = max(-1.0, min(1.0, (ax * cx + ay * cy) / (la * lc))) - if math.degrees(math.acos(dot)) <= 46.0: - out.append(b) - continue - d = min(r, la / 2.0, lc / 2.0) - out.append((round(b[0] - ax / la * d, 4), round(b[1] - ay / la * d, 4), a[2], a[3])) - out.append((round(b[0] + cx / lc * d, 4), round(b[1] + cy / lc * d, 4), b[2], b[3])) - out.append(pts[-1]) - return out - - -def P(*pts): - u"""(x, y[, layer[, width]]) -> 规范化四元组；层/宽省略时沿用上一点。""" - out, lay, w = [], L_BOT, W - for t in pts: - x, y = t[0], t[1] - lay = t[2] if len(t) > 2 else lay - w = t[3] if len(t) > 3 else w - out.append((round(x, 4), round(y, 4), lay, w)) - return out - - -PAD_X = 95.55 # U32 西缘焊盘中心（焊盘 x 95.125~95.975，hh 0.15） -# 0.28 的线直着从 0.5 脚距的焊盘出来，两边净距 0.21，不用让位。 - -# ══════════ pair 1 → U51（西北远处）══════════ -# 直着西行：y 64.25/64.75 从 x 95.55 到 x 22~23 一路无障碍（U31 pin1 顶 63.35、J31 底排焊盘底 65.38、 -# R721/R722 顶 61.77、U34 顶 ~62）。西行时 DM 在南 = 左侧，右拐北上后左侧变西 ⇒ DM 走西车道 22.34（正对 U51.6）， -# DP 在 22.82，到 y 84.3 再 45° 分到 24.24 进 U51.4。 -SITE1 = { - 'USB1_DM': [(PAD_X, 64.25), (22.34, 64.25), (22.34, 86.475)], - 'USB1_DP': [(PAD_X, 64.75), (22.82, 64.75), (22.82, 84.30), (24.24, 85.72), (24.24, 86.475)], -} - -# ══════════ pair 2 → U52（正北）══════════ -# 西行到 x 89.27/89.75 右拐北上（DM 西）。北上车道左边是 J31 最东一列焊盘（x ≤ 86.98），右边是 pin5 的北上车道 90.4。 -# 一直到 y 80 才 45° 斜向东北 —— 必须过了 pair 3 / pair 5 东行车道（y ≤ 76.97）之后才能往东挪， -# 而且要绕开 site2 的定位孔 H1 (89.39, 85.36)。斜段直接斜到各自焊盘正下方：DM 到 93.84、DP 一口气到 95.74。 -# 内侧（DP，东）早拐 0.2 保持斜段 0.48 间距。 -SITE2 = { - 'USB2_DM': [(PAD_X, 65.25), (89.27, 65.25), (89.27, 80.00), (93.84, 84.57), (93.84, 86.475)], - 'USB2_DP': [(PAD_X, 65.75), (89.75, 65.75), (89.75, 79.80), (95.74, 85.79), (95.74, 86.475)], -} - -# ══════════ pair 3 → U53（东北）══════════ -# 西行到 91.05/91.53 右拐北上（DM 西），再右拐东行（西车道变北车道 ⇒ DM 76.98 / DP 76.50）， -# 这一段在 pair 5 东行车道（75.50/75.98）的北边；pair 5 在 x 110.78 南下之后，pair 3 在 x 112 压到 75.40/75.88 —— -# 因为 MH (148.1, 79.5) 的 Ø6 焊盘底在 76.5，北车道上沿必须 ≤ 76.16。 -# 到 x 165 左拐北上：北车道（DM）是内侧变西 ⇒ DM 165.34 正对 U53.6，DP 在 165.82 到 y 84.6 再分到 167.24。 -# 下压的斜段：第一拐向右（东→东南），内侧是南车道 DP，早拐 0.2。 -SITE3 = { - 'USB3_DM': [(PAD_X, 66.75), (91.05, 66.75), (91.05, 76.98), (112.00, 76.98), (113.10, 75.88), - (165.34, 75.88), (165.34, 86.475)], - 'USB3_DP': [(PAD_X, 67.25), (91.53, 67.25), (91.53, 76.50), (111.80, 76.50), (112.90, 75.40), - (165.82, 75.40), (165.82, 84.60), (167.24, 86.02), (167.24, 86.475)], -} - -# ══════════ pair 4 → U54（西南）—— 全程顶层 ══════════ -# 它北边是 pin10（要跟 pair 5 北上）、南边是 pair 3（北上）、pair 2、pair 1 全都横在西边 —— 底层无路， -# 一出焊盘就打孔上顶层。两个孔：DM4 (92.2, 67.95)（离 DP3 横车道 67.39 有 0.255）、DP4 (92.2, 68.85)（上下错 0.9）， -# DP4 先在 x 93.1→92.5 斜抬到 68.85 再西行到孔，避开 DM4 的孔（孔顶 68.255 vs 车道底 68.11 才 0.055）。 -# 顶层：DP 西车道 91.5 / DM 91.98 南下到 y 52，45° 斜到 (89.6, 50.3) / (90.5, 50.3) 打孔回底层， -# 进 U54.4 (88.6, 48.149) / U54.6 (90.5, 48.149)。DM 的孔正对焊盘、直下；DP 的孔再斜 1 mm 到 88.6。 -# 顶层这一段底下 Inner1：x ≥ 87 全是 GND（VO4 岛东界 87、site4 岛 x ≤ 84.75、VO2 从 y 75.5 起）。 -SITE4 = { - 'USB4_DM': [(PAD_X, 67.75), (92.60, 67.75), (92.40, 67.95), (92.20, 67.95), - (92.20, 67.95, L_TOP), (91.98, 67.73), (91.98, 52.00), (90.50, 50.52), (90.50, 50.30), - (90.50, 50.30, L_BOT), (90.50, 48.685)], - 'USB4_DP': [(PAD_X, 68.25), (93.10, 68.25), (92.50, 68.85), (92.20, 68.85), - (92.20, 68.85, L_TOP), (91.50, 68.85), (91.50, 52.50), (89.60, 50.60), (89.60, 50.30), - (89.60, 50.30, L_BOT), (88.60, 49.30), (88.60, 48.685)], -} - -# ══════════ pair 5 → U55（东南）—— 绕 Hub 北边走 ══════════ -# 最北的一对，出来就右拐北上（DM 西 93.47 / DP 东 93.95；DP 的东沿离 C751 焊盘 94.295 只剩 0.205， -# 再东一点 pin13 的 GND 就打不了孔了 —— 给它留的孔位是 (94.6, 71.4)）。 -# 北上到 75.50/75.98（C751 顶 74.974，DP 拐角的 45° 切角离它 0.24）右拐东行（DM 北），到 x 110.30/110.78 右拐南下（南车道 DP 是内侧变西 ⇒ DP 110.30）。 -# 南下时 x 110.3 离 R711/R716/R720 的东沿 109.62 有 0.54、离 J64 焊盘 107.43 有 2.7。 -# **y 59.2~61.6 翻到顶层跨过 UP 的两根横线**（60.12/60.60）：DP 的孔在 110.30，DM 的孔错到 111.3（两孔 1.0）。 -# 到 y 52.5/52.98 左拐东行（东车道 DM 是内侧变北 ⇒ DM 52.98），DP 在 x 160.10 南下进 U55.4，DM 到 162.00 进 U55.6。 -SITE5 = { - 'USB5_DM': [(PAD_X, 69.25), (93.47, 69.25), (93.47, 75.98), (110.78, 75.98), - (110.78, 62.60), (111.30, 62.08), (111.30, 61.60), - (111.30, 61.60, L_TOP), (111.30, 59.20), - (111.30, 59.20, L_BOT), (111.30, 58.72), (110.78, 58.20), - (110.78, 52.98), (162.00, 52.98), (162.00, 48.685)], - 'USB5_DP': [(PAD_X, 69.75), (93.95, 69.75), (93.95, 75.50), (110.30, 75.50), - (110.30, 61.60), - (110.30, 61.60, L_TOP), (110.30, 59.20), - (110.30, 59.20, L_BOT), (110.30, 52.50), (160.10, 52.50), (160.10, 48.685)], -} - -# ══════════ UPSTREAM → J23（U32 南缘 → 板子正东）══════════ -# pin59 UP_DP (98.75, 63.55) / pin58 UP_DM (99.25, 63.55) 直着南下，从 C743（x ≤ 97.62）与 C745（x ≥ 99.78）之间的 -# 竖井下到 y 60.12/60.60（那排 0402 的焊盘底 60.98），一路东行到 x 205 —— 中间 y 60~61 从 x 99 到 208 全空。 -# J23（底层 rot 270）：B6 UP_DP 61.25 / A7 UP_DM 61.75 / A6 UP_DP 62.25 / B7 UP_DM 62.75，B5 CC2 在 60.25、A8 空脚 60.75。 -# 车道压在 60.17 会把 B5 的 CC2 走线堵死（R718 在 59.5），所以 x 205 就抬到 61.25/61.75 平着进 B6/A7。 -# 抬升是左拐再右拐，第一拐内侧是北车道 DM ⇒ DM 早拐 0.2。 -UP = { - 'UP_DP': [(98.75, 63.55), (98.75, 60.12), (205.00, 60.12), (206.13, 61.25), (212.392, 61.25)], - 'UP_DM': [(99.25, 63.55), (99.25, 60.60), (204.80, 60.60), (205.95, 61.75), (212.392, 61.75)], -} - -# ══════════ J23 的 A6↔B6 / A7↔B7 短接（USB-C 正反插的一对重复脚）══════════ -# 几何照抄 v3（那一版过了 DRC），只是 J23 翻到底层之后网络对调：61.25↔62.25 这一对现在是 UP_DP（B6/A6）， -# 61.75↔62.75 是 UP_DM（A7/B7）；出线在底层，跨越段翻到**顶层**。 -# ⚠ 表贴焊盘只到 x=213.04，过孔要离它 0.505 ⇒ 最西只能放到 213.55；出线前 0.65 mm 必须平着走（阵列上方起坡会蹭隔壁脚）。 -# 另一根的 61.75 横线离 (213.85, 62.25) 那个孔只有 0.165 —— 这是同一对的两根（UP_DP vs UP_DM），按对内 0.15 判。 -J23_TIE = { - 'UP_DP#2': [(212.392, 62.25, L_BOT, W), (213.85, 62.25), (213.85, 62.25, L_TOP), - (213.85, 60.70), (213.85, 60.70, L_BOT), (213.50, 61.25), - (213.20, 61.25), (212.392, 61.25)], - 'UP_DM#2': [(212.392, 61.75, L_BOT, W), (213.20, 61.75), (213.50, 61.75), - (214.25, 61.30), (214.75, 61.30), (214.75, 61.30, L_TOP), - (214.75, 63.20), (214.75, 63.20, L_BOT), (214.25, 63.20), - (213.50, 62.75), (213.20, 62.75), (212.392, 62.75)], -} - - -# ══════════ Hub 西缘 pin5 / pin10 的 +3V3（被 D± 夹住，只能在这里一起画）══════════ -# 后面的信号布线器（pcb2_route_sig.py）把这些线当**已有障碍**，别删。 -# pin5 (66.25) 夹在 DP2 (65.75) 与 DM3 (66.75) 之间：西行到 90.4（pair 3 拐走之后）跟着北上，到 (90.4, 70.5) 打孔翻顶层 -# —— 孔离 DP2 车道 89.75 / DM3 车道 91.05 各 0.65。顶层西去 (88.2, 70.5) 再下来进 C747（底层 rot 90，x 88.2， -# 在 J31 最东列 86.98 与 DM2 车道 89.27 之间）。(88.2, 70.5) 的孔离 VO2 岛东界 87.3 有 0.9，反焊盘不碰岛。 -# pin10 (68.75) 夹在 DP4 (68.25) 与 DM5 (69.25) 之间：西行到 92.95 跟着 pair 5 北上（离 DM5 车道 0.24、离 pair 4 的孔 0.305）， -# y 69.55 起 45° 斜到 (92.5, 70.0)，直进 C748（底层 rot 90，x 92.5，夹在 DP3 车道 91.53 与 DM5 车道 93.47 中间）。 -# +3V3 干线：U31 pin2（+3V3 输出，(90.47, 60.5) 焊盘 y ≤ 61.05）旁 (90.3, 61.65) 打孔上顶层，沿 x 90.3 北上 -# （pair 4 的顶层车道在 91.5 以东），到 (90.4, 70.5) 与 pin5 的孔汇合，再东去 (92.5, 70.0) 打孔下来进 C748。 -# 顶层这三段底下 Inner1 都是 GND（x 87.3~100.5、y 65.15~75.5 之间没有任何岛）。 -# 电容的哪个焊盘是 +3V3 由 build() 从障碍表里查，不写死。 -V_P5, V_P5W = (90.40, 70.50), (88.20, 70.50) -V_P10 = (92.50, 70.00) -V_TRUNK = (90.30, 61.65) - - -def _pad(pads, ref, net): - for p in pads: - if p['ref'] == ref and p['net'] == net: - return (p['x'], p['y']) - raise SystemExit(u'障碍表里找不到 %s 的 %s 焊盘（先 --dump）' % (ref, net)) - - -def power_lanes(pads): - c747 = _pad(pads, 'C747', '+3V3_HUB') - c748 = _pad(pads, 'C748', '+3V3_HUB') - for p in pads: # 干线起点必须真的落在 U31 pin2（+3V3 输出）里 - if p['ref'] == 'U31' and p['num'] == '2': - assert abs(p['x'] - 90.47) < 0.05 and abs(p['y'] - 60.5) < 0.05, u'U31 pin2 挪了，改 V_TRUNK' - return { - '+3V3_HUB#p5': [(PAD_X, 66.25), (90.40, 66.25), (V_P5[0], V_P5[1]), - (V_P5[0], V_P5[1], L_TOP), (V_P5W[0], V_P5W[1]), - (V_P5W[0], V_P5W[1], L_BOT), (c747[0], c747[1])], - '+3V3_HUB#p10': [(PAD_X, 68.75), (92.95, 68.75), (92.95, 69.55), (V_P10[0], V_P10[1]), - (c748[0], c748[1])], - '+3V3_HUB#trunk': [(90.30, 61.00), (V_TRUNK[0], V_TRUNK[1]), - (V_TRUNK[0], V_TRUNK[1], L_TOP), (90.30, 70.40), (V_P5[0], V_P5[1]), - (V_P10[0], V_P10[1]), (V_P10[0], V_P10[1], L_BOT), (c748[0], c748[1])], - } - - -def build(pads=None): - out = {} - for grp in (SITE1, SITE2, SITE3, SITE4, SITE5, UP, J23_TIE): - for net, pts in grp.items(): - out[net] = chamfer(P(*pts)) - if pads is not None: - for net, pts in power_lanes(pads).items(): - out[net] = chamfer(P(*pts)) - return out +# -*- coding: utf-8 -*- +u"""六对**长差分**（USB1~5 的 U32↔U5n + UPSTREAM 的 U32↔J23）+ Hub 西缘被 D± 夹住的两条 +3V3 车道。 + +**v5 版（2026-09-06，载板全部底层、接口边朝板边）。** v3 版存档在 `obsolete/pcb2_dp_long_v3_2026-09-06.py`。 +被 `pcb2_route_dp.py` import；校核 / 下发都用那个脚本，这里只放坐标。 + +## 出发点：U32 西缘的 12 条车道 + +U32（QFN-64，**底层**，中心 (100, 68)）的 D± 全在**西缘 x 95.55**，0.5 脚距、南→北： + + 1DM 64.25 | 1DP 64.75 | 2DM 65.25 | 2DP 65.75 | pin5 +3V3 66.25 | + 3DM 66.75 | 3DP 67.25 | 4DM 67.75 | 4DP 68.25 | pin10 +3V3 68.75 | + 5DM 69.25 | 5DP 69.75 | pin13 GND 70.25 | 14~16 NC + +目的地却是四面八方：1→西北远处 (U51 22/24, 87)、2→正北 (U52 94/96, 87)、3→东北 (U53 165/167, 87)、 +4→西南 (U54 88.6/90.5, 48)、5→东南 (U55 160/162, 48)、UP→正东 (J23 212, 61~62)。 + +### 定下来的走法（理由都在代码注释里） + +| 车道 | 层 | 走法 | +|---|---|---| +| pair 1 | 底 | 直着西行 y 64.25/64.75 到 x 22.34/22.82，北上进 U51 | +| pair 2 | 底 | 西行到 89.27/89.75 北上，y 80 处 45° 斜到 93.84/95.74 进 U52 | +| pin 5 | 底→顶 | 西行到 90.4，跟着 pair 3 北上到 70.5 打孔翻顶层，西去 (88.2, 70.5) 再下来进 C747 | +| pair 3 | 底 | 西行到 91.05/91.53 北上，y 76.50/76.98 东行，过了 pair 5 之后压到 75.40/75.88 从 MH 焊盘下面钻过去，x 165 北上 | +| pair 4 | **顶** | 西行到 x 92.2 打孔上顶层（DM 67.95 / DP 68.85），沿 x 91.5/91.98 南下到 y 52，斜到 (89.6/90.5, 50.3) 下来进 U54 | +| pin 10 | 底 | 西行到 92.95，跟着 pair 5 北上，斜到 (92.5, 70.0) 进 C748；(92.5, 70.0) 上有一个孔接顶层 +3V3 干线 | +| pair 5 | 底 | 西行到 93.47/93.95 北上，y 75.50/75.98 东行到 110.30/110.78 南下，**y 59.2~61.6 翻顶层跨过 UP**，y 52.5/52.98 东行，x 160.1/162 南下进 U55 | +| UP | 底 | 南缘 pin58/59 从 C743/C745 之间的竖井下到 60.12/60.60，一路东行，x 205 抬到 61.25/61.75 进 J23 B6/A7 | +| +3V3 干线 | 顶 | U31 pin2 旁 (90.3, 61.65) 打孔上顶层，北上到 (90.4, 70.5)（与 pin5 的孔汇合），东去 (92.5, 70.0) 下来进 C748 | + +### 三条关键约束 + +1. **0.5 脚距的车道之间打不了孔**：孔要离两边车道各 0.645，所以只有当邻居车道都拐走之后才能打。 + 北边的先拐（pair 5 → pin 10 → pair 4 打孔 → pair 3 → pin 5 → pair 2），像剥洋葱。 + pair 4 的两个孔卡在 DP3 的横车道（y 67.25，要求孔心 ≥ 67.895）和 pin10 北上车道（x 92.95，要求孔心 x ≤ 92.305）之间， + 所以 DP4 得先在 x 93.1→92.5 抬到 68.85 再打孔，两孔上下错 0.9。 +2. **顶层只走 Inner1 是 GND 的地方**：Hub 周围 x ≥ 87（VO4 岛东界已从 89 收到 87）、y < 75.5（VO2 的 Hub 北横带以南）是一整片 GND； + pair 4 全程、pair 5 跨 UP 的那 2.4 mm、+3V3 干线都在这片里。pair 5 的跨越点 x 110~111.5 也在 VO4/VO5 之间的 GND 窗口里。 +3. **平行 45° 斜段要保持 0.48 间距**：两根线各自的拐点不能同 x/同 y，第一拐**内侧**那根要早拐 0.2 + （0.48·(√2−1)），否则斜段上的垂直间距只剩 0.34。文件里所有成对斜段都按这个写。 + +### 每个站点最后一段 + +U5n 朝 Hub 那排的 DP/DM 相距 1.9 mm，车道并排 0.48 到最后 1.4 mm 再用 45° 分开， +分开的那根一律是**转弯时的外侧**，所以到站不用交叉 —— 五对都核过了 +（转弯规则：向右拐时左边那根变成外侧，连拐两次回到原样）。 +""" +import math +import sys as _s, os as _o; _s.path.insert(0, _o.path.dirname(_o.path.abspath(__file__))) +KSEP = chr(0) # 路径 key 的分隔符，与 pcb2_route_dp.KSEP 同值（不能 import：route_dp --dump 会反过来 import 本模块，循环） + +L_TOP, L_BOT = 1, 2 +W = 0.28 + + +def chamfer(pts, r=0.35): + u"""把折线的拐点切成 45°。换层点（相邻两点层不同）不切。 + + ⚠ 点的 layer/width 语义是「从这一点到下一点」，所以在拐点 b 处插入的 + b1 用**前一段**的层/宽（它承担斜切段），b2 用 b 自己的。 + """ + if len(pts) < 3: + return list(pts) + out = [pts[0]] + for i in range(1, len(pts) - 1): + a, b, c = pts[i - 1], pts[i], pts[i + 1] + if a[2] != b[2] or b[2] != c[2]: # 拐点两侧不同层 -> 这是过孔点 + out.append(b) + continue + ax, ay = b[0] - a[0], b[1] - a[1] + cx, cy = c[0] - b[0], c[1] - b[1] + la, lc = math.hypot(ax, ay), math.hypot(cx, cy) + if la < 1e-9 or lc < 1e-9: + out.append(b) + continue + # 共线就不用切；**已经是 45° 的拐（正 + 斜）也不切** —— 再切一刀会变成两个 22.5°， + # 而且切出来的那一小段会向内侧挪 0.1 mm，实测把 DP4 的抬升段切进了 pin10 车道的净距圈（0.125）。 + dot = max(-1.0, min(1.0, (ax * cx + ay * cy) / (la * lc))) + if math.degrees(math.acos(dot)) <= 46.0: + out.append(b) + continue + d = min(r, la / 2.0, lc / 2.0) + out.append((round(b[0] - ax / la * d, 4), round(b[1] - ay / la * d, 4), a[2], a[3])) + out.append((round(b[0] + cx / lc * d, 4), round(b[1] + cy / lc * d, 4), b[2], b[3])) + out.append(pts[-1]) + return out + + +def P(*pts): + u"""(x, y[, layer[, width]]) -> 规范化四元组；层/宽省略时沿用上一点。""" + out, lay, w = [], L_BOT, W + for t in pts: + x, y = t[0], t[1] + lay = t[2] if len(t) > 2 else lay + w = t[3] if len(t) > 3 else w + out.append((round(x, 4), round(y, 4), lay, w)) + return out + + +PAD_X = 95.55 # U32 西缘焊盘中心（焊盘 x 95.125~95.975，hh 0.15） +# 0.28 的线直着从 0.5 脚距的焊盘出来，两边净距 0.21，不用让位。 + +# ══════════ pair 1 → U51（西北远处）══════════ +# 直着西行：y 64.25/64.75 从 x 95.55 到 x 22~23 一路无障碍（U31 pin1 顶 63.35、J31 底排焊盘底 65.38、 +# R721/R722 顶 61.77、U34 顶 ~62）。西行时 DM 在南 = 左侧，右拐北上后左侧变西 ⇒ DM 走西车道 22.34（正对 U51.6）， +# DP 在 22.82，到 y 84.3 再 45° 分到 24.24 进 U51.4。 +SITE1 = { + 'USB1_DM': [(PAD_X, 64.25), (22.34, 64.25), (22.34, 86.475)], + 'USB1_DP': [(PAD_X, 64.75), (22.82, 64.75), (22.82, 84.30), (24.24, 85.72), (24.24, 86.475)], +} + +# ══════════ pair 2 → U52（正北）══════════ +# 西行到 x 89.27/89.75 右拐北上（DM 西）。北上车道左边是 J31 最东一列焊盘（x ≤ 86.98），右边是 pin5 的北上车道 90.4。 +# 一直到 y 80 才 45° 斜向东北 —— 必须过了 pair 3 / pair 5 东行车道（y ≤ 76.97）之后才能往东挪， +# 而且要绕开 site2 的定位孔 H1 (89.39, 85.36)。斜段直接斜到各自焊盘正下方：DM 到 93.84、DP 一口气到 95.74。 +# 内侧（DP，东）早拐 0.2 保持斜段 0.48 间距。 +SITE2 = { + 'USB2_DM': [(PAD_X, 65.25), (89.27, 65.25), (89.27, 80.00), (93.84, 84.57), (93.84, 86.475)], + 'USB2_DP': [(PAD_X, 65.75), (89.75, 65.75), (89.75, 79.80), (95.74, 85.79), (95.74, 86.475)], +} + +# ══════════ pair 3 → U53（东北）══════════ +# 西行到 91.05/91.53 右拐北上（DM 西），再右拐东行（西车道变北车道 ⇒ DM 76.98 / DP 76.50）， +# 这一段在 pair 5 东行车道（75.50/75.98）的北边；pair 5 在 x 110.78 南下之后，pair 3 在 x 112 压到 75.40/75.88 —— +# 因为 MH (148.1, 79.5) 的 Ø6 焊盘底在 76.5，北车道上沿必须 ≤ 76.16。 +# 到 x 165 左拐北上：北车道（DM）是内侧变西 ⇒ DM 165.34 正对 U53.6，DP 在 165.82 到 y 84.6 再分到 167.24。 +# 下压的斜段：第一拐向右（东→东南），内侧是南车道 DP，早拐 0.2。 +SITE3 = { + 'USB3_DM': [(PAD_X, 66.75), (91.05, 66.75), (91.05, 76.98), (112.00, 76.98), (113.10, 75.88), + (165.34, 75.88), (165.34, 86.475)], + 'USB3_DP': [(PAD_X, 67.25), (91.53, 67.25), (91.53, 76.50), (111.80, 76.50), (112.90, 75.40), + (165.82, 75.40), (165.82, 84.60), (167.24, 86.02), (167.24, 86.475)], +} + +# ══════════ pair 4 → U54（西南）—— 全程顶层 ══════════ +# 它北边是 pin10（要跟 pair 5 北上）、南边是 pair 3（北上）、pair 2、pair 1 全都横在西边 —— 底层无路， +# 一出焊盘就打孔上顶层。两个孔：DM4 (92.2, 67.95)（离 DP3 横车道 67.39 有 0.255）、DP4 (92.2, 68.85)（上下错 0.9）， +# DP4 先在 x 93.1→92.5 斜抬到 68.85 再西行到孔，避开 DM4 的孔（孔顶 68.255 vs 车道底 68.11 才 0.055）。 +# 顶层：DP 西车道 91.5 / DM 91.98 南下到 y 52，45° 斜到 (89.6, 50.3) / (90.5, 50.3) 打孔回底层， +# 进 U54.4 (88.6, 48.149) / U54.6 (90.5, 48.149)。DM 的孔正对焊盘、直下；DP 的孔再斜 1 mm 到 88.6。 +# 顶层这一段底下 Inner1：x ≥ 87 全是 GND（VO4 岛东界 87、site4 岛 x ≤ 84.75、VO2 从 y 75.5 起）。 +SITE4 = { + 'USB4_DM': [(PAD_X, 67.75), (92.60, 67.75), (92.40, 67.95), (92.20, 67.95), + (92.20, 67.95, L_TOP), (91.98, 67.73), (91.98, 52.00), (90.50, 50.52), (90.50, 50.30), + (90.50, 50.30, L_BOT), (90.50, 48.685)], + 'USB4_DP': [(PAD_X, 68.25), (93.10, 68.25), (92.50, 68.85), (92.20, 68.85), + (92.20, 68.85, L_TOP), (91.50, 68.85), (91.50, 52.50), (89.60, 50.60), (89.60, 50.30), + (89.60, 50.30, L_BOT), (88.60, 49.30), (88.60, 48.685)], +} + +# ══════════ pair 5 → U55（东南）—— 绕 Hub 北边走 ══════════ +# 最北的一对，出来就右拐北上（DM 西 93.47 / DP 东 93.95；DP 的东沿离 C751 焊盘 94.295 只剩 0.205， +# 再东一点 pin13 的 GND 就打不了孔了 —— 给它留的孔位是 (94.6, 71.4)）。 +# 北上到 75.50/75.98（C751 顶 74.974，DP 拐角的 45° 切角离它 0.24）右拐东行（DM 北），到 x 110.30/110.78 右拐南下（南车道 DP 是内侧变西 ⇒ DP 110.30）。 +# 南下时 x 110.3 离 R711/R716/R720 的东沿 109.62 有 0.54、离 J64 焊盘 107.43 有 2.7。 +# **y 59.2~61.6 翻到顶层跨过 UP 的两根横线**（60.12/60.60）：DP 的孔在 110.30，DM 的孔错到 111.3（两孔 1.0）。 +# 到 y 52.5/52.98 左拐东行（东车道 DM 是内侧变北 ⇒ DM 52.98），DP 在 x 160.10 南下进 U55.4，DM 到 162.00 进 U55.6。 +SITE5 = { + 'USB5_DM': [(PAD_X, 69.25), (93.47, 69.25), (93.47, 75.98), (110.78, 75.98), + (110.78, 62.60), (111.30, 62.08), (111.30, 61.60), + (111.30, 61.60, L_TOP), (111.30, 59.20), + (111.30, 59.20, L_BOT), (111.30, 58.72), (110.78, 58.20), + (110.78, 52.98), (162.00, 52.98), (162.00, 48.685)], + 'USB5_DP': [(PAD_X, 69.75), (93.95, 69.75), (93.95, 75.50), (110.30, 75.50), + (110.30, 61.60), + (110.30, 61.60, L_TOP), (110.30, 59.20), + (110.30, 59.20, L_BOT), (110.30, 52.50), (160.10, 52.50), (160.10, 48.685)], +} + +# ══════════ UPSTREAM → J23（U32 南缘 → 板子正东）══════════ +# pin59 UP_DP (98.75, 63.55) / pin58 UP_DM (99.25, 63.55) 直着南下，从 C743（x ≤ 97.62）与 C745（x ≥ 99.78）之间的 +# 竖井下到 y 60.12/60.60（那排 0402 的焊盘底 60.98），一路东行到 x 205 —— 中间 y 60~61 从 x 99 到 208 全空。 +# J23（底层 rot 270）：B6 UP_DP 61.25 / A7 UP_DM 61.75 / A6 UP_DP 62.25 / B7 UP_DM 62.75，B5 CC2 在 60.25、A8 空脚 60.75。 +# 车道压在 60.17 会把 B5 的 CC2 走线堵死（R718 在 59.5），所以 x 205 就抬到 61.25/61.75 平着进 B6/A7。 +# 抬升是左拐再右拐，第一拐内侧是北车道 DM ⇒ DM 早拐 0.2。 +UP = { + 'UP_DP': [(98.75, 63.55), (98.75, 60.12), (205.00, 60.12), (206.13, 61.25), (212.392, 61.25)], + 'UP_DM': [(99.25, 63.55), (99.25, 60.60), (204.80, 60.60), (205.95, 61.75), (212.392, 61.75)], +} + +# ══════════ J23 的 A6↔B6 / A7↔B7 短接（USB-C 正反插的一对重复脚）══════════ +# 几何照抄 v3（那一版过了 DRC），只是 J23 翻到底层之后网络对调：61.25↔62.25 这一对现在是 UP_DP（B6/A6）， +# 61.75↔62.75 是 UP_DM（A7/B7）；出线在底层，跨越段翻到**顶层**。 +# ⚠ 表贴焊盘只到 x=213.04，过孔要离它 0.505 ⇒ 最西只能放到 213.55；出线前 0.65 mm 必须平着走（阵列上方起坡会蹭隔壁脚）。 +# 另一根的 61.75 横线离 (213.85, 62.25) 那个孔只有 0.165 —— 这是同一对的两根（UP_DP vs UP_DM），按对内 0.15 判。 +J23_TIE = { + 'UP_DP' + KSEP + '2': [(212.392, 62.25, L_BOT, W), (213.85, 62.25), (213.85, 62.25, L_TOP), + (213.85, 60.70), (213.85, 60.70, L_BOT), (213.50, 61.25), + (213.20, 61.25), (212.392, 61.25)], + 'UP_DM' + KSEP + '2': [(212.392, 61.75, L_BOT, W), (213.20, 61.75), (213.50, 61.75), + (214.25, 61.30), (214.75, 61.30), (214.75, 61.30, L_TOP), + (214.75, 63.20), (214.75, 63.20, L_BOT), (214.25, 63.20), + (213.50, 62.75), (213.20, 62.75), (212.392, 62.75)], +} + + +# ══════════ Hub 西缘 pin5 / pin10 的 +3V3（被 D± 夹住，只能在这里一起画）══════════ +# 后面的信号布线器（pcb2_route_sig.py）把这些线当**已有障碍**，别删。 +# pin5 (66.25) 夹在 DP2 (65.75) 与 DM3 (66.75) 之间：西行到 90.4（pair 3 拐走之后）跟着北上，到 (90.4, 70.5) 打孔翻顶层 +# —— 孔离 DP2 车道 89.75 / DM3 车道 91.05 各 0.65。顶层西去 (88.2, 70.5) 再下来进 C747（底层 rot 90，x 88.2， +# 在 J31 最东列 86.98 与 DM2 车道 89.27 之间）。(88.2, 70.5) 的孔离 VO2 岛东界 87.3 有 0.9，反焊盘不碰岛。 +# pin10 (68.75) 夹在 DP4 (68.25) 与 DM5 (69.25) 之间：西行到 92.95 跟着 pair 5 北上（离 DM5 车道 0.24、离 pair 4 的孔 0.305）， +# y 69.55 起 45° 斜到 (92.5, 70.0)，直进 C748（底层 rot 90，x 92.5，夹在 DP3 车道 91.53 与 DM5 车道 93.47 中间）。 +# +3V3 干线：U31 pin2（+3V3 输出，(90.47, 60.5) 焊盘 y ≤ 61.05）旁 (90.3, 61.65) 打孔上顶层，沿 x 90.3 北上 +# （pair 4 的顶层车道在 91.5 以东），到 (90.4, 70.5) 与 pin5 的孔汇合，再东去 (92.5, 70.0) 打孔下来进 C748。 +# 顶层这三段底下 Inner1 都是 GND（x 87.3~100.5、y 65.15~75.5 之间没有任何岛）。 +# 电容的哪个焊盘是 +3V3 由 build() 从障碍表里查，不写死。 +V_P5, V_P5W = (90.40, 70.50), (88.20, 70.50) +V_P10 = (92.50, 70.00) +V_TRUNK = (90.30, 61.65) + + +def _pad(pads, ref, net): + for p in pads: + if p['ref'] == ref and p['net'] == net: + return (p['x'], p['y']) + raise SystemExit(u'障碍表里找不到 %s 的 %s 焊盘（先 --dump）' % (ref, net)) + + +def power_lanes(pads): + c747 = _pad(pads, 'C747', '+3V3_HUB') + c748 = _pad(pads, 'C748', '+3V3_HUB') + for p in pads: # 干线起点必须真的落在 U31 pin2（+3V3 输出）里 + if p['ref'] == 'U31' and p['num'] == '2': + assert abs(p['x'] - 90.47) < 0.05 and abs(p['y'] - 60.5) < 0.05, u'U31 pin2 挪了，改 V_TRUNK' + return { + '+3V3_HUB' + KSEP + 'p5': [(PAD_X, 66.25), (90.40, 66.25), (V_P5[0], V_P5[1]), + (V_P5[0], V_P5[1], L_TOP), (V_P5W[0], V_P5W[1]), + (V_P5W[0], V_P5W[1], L_BOT), (c747[0], c747[1])], + '+3V3_HUB' + KSEP + 'p10': [(PAD_X, 68.75), (92.95, 68.75), (92.95, 69.55), (V_P10[0], V_P10[1]), + (c748[0], c748[1])], + '+3V3_HUB' + KSEP + 'trunk': [(90.30, 61.00), (V_TRUNK[0], V_TRUNK[1]), + (V_TRUNK[0], V_TRUNK[1], L_TOP), (90.30, 70.40), (V_P5[0], V_P5[1]), + (V_P10[0], V_P10[1]), (V_P10[0], V_P10[1], L_BOT), (c748[0], c748[1])], + } + + +def build(pads=None): + out = {} + for grp in (SITE1, SITE2, SITE3, SITE4, SITE5, UP, J23_TIE): + for net, pts in grp.items(): + out[net] = chamfer(P(*pts)) + if pads is not None: + for net, pts in power_lanes(pads).items(): + out[net] = chamfer(P(*pts)) + return out diff --git a/.claude/pcb2_fanout.py b/.claude/pcb2_fanout.py index bb00dea..a1c64cb 100644 --- a/.claude/pcb2_fanout.py +++ b/.claude/pcb2_fanout.py @@ -1,7 +1,7 @@ # -*- coding: utf-8 -*- u"""载板 PCB2-CARRIER 的扇出 —— 复用下板 `pcb_fanout.py` 的规划器，只换掉板子相关的常量。 - /c/Python314/python .claude/dump_pads.py f126ffb29c92f9b2 pcb2-copper.json # 1. 抓障碍表 + /c/Python314/python .claude/dump_pads.py 942ed1560d81c1e7 pcb2-copper.json # 1. 抓障碍表 /c/Python314/python .claude/pcb2_fanout.py # 2. 只规划 /c/Python314/python .claude/pcb2_fanout.py --push # 3. 下发 @@ -47,7 +47,7 @@ F = importlib.util.module_from_spec(_spec) _spec.loader.exec_module(F) # ── 换掉板子相关的常量 ──────────────────────────────────────────────── -F.PCB = 'f126ffb29c92f9b2' # PCB2-CARRIER +F.PCB = '942ed1560d81c1e7' # PCB2-CARRIER F.SRC = os.path.join(HERE, 'pcb2-copper.json') F.BOARD = (0.0, 0.0, 220.0, 135.0) F.R_CORNER = 5.0 @@ -168,7 +168,7 @@ def clean2(): def main(): if not os.path.exists(F.SRC): sys.exit(u'先抓障碍表：/c/Python314/python .claude/dump_pads.py ' - u'f126ffb29c92f9b2 pcb2-copper.json') + u'942ed1560d81c1e7 pcb2-copper.json') print(u'载板扇出：板框 %.0f × %.0f，元件面 %s，GND -> layer %d' % (F.BOARD[2], F.BOARD[3], F.FANOUT_LAYERS, F.TARGET['GND'])) if SKIP_HDR: diff --git a/.claude/pcb2_gnd_patch.py b/.claude/pcb2_gnd_patch.py index e781eff..70d7aa2 100644 --- a/.claude/pcb2_gnd_patch.py +++ b/.claude/pcb2_gnd_patch.py @@ -1,255 +1,274 @@ -# -*- coding: utf-8 -*- -u"""补上 §25.8 遗留的**悬空 GND 焊盘** —— 自己找出来，自己打孔。 - - /c/Python314/python .claude/pcb2_route_dp.py --dump # 1. 先刷障碍表 - /c/Python314/python .claude/pcb2_gnd_patch.py # 2. 找悬空 + 选孔位 + 净距校核 - /c/Python314/python .claude/pcb2_gnd_patch.py --check # 只问「现在板上还有没有悬空的」 - /c/Python314/python .claude/pcb2_gnd_patch.py --push # 3. 下发（**只加不删**） - /c/Python314/python .claude/pcb2_pour.py --push # 4. 必须重铺 - -## 「悬空」是自己算的，不是抄 DRC - -把 GND 网络的**焊盘 / 过孔 / 导线**当图，两两相触连边（判据同 `pcb2_net_conn.py`）， -一个连通域里只要有**一个过孔或一个通孔焊盘**，它就落到 Inner1/Inner2 的地平面上 = 连通。 -**一个都没有的连通域就是悬空的** —— 那是纯顶层/底层的一小块孤铜。 - -⇒ 这个判据是幂等的：补完孔再跑一次，找到 0 个。 - -## 和 `pcb2_fanout.py` 的分工 - -`pcb_fanout` 是**批量**扇出（210 个孔），它对每个焊盘只试固定的几个方位， -挤不下就跳过 —— §25.8 里剩下的这几个就是被它跳过的。 -这里换成和 `pcb2_vo_vias.py` 同一套搜索：8 个方向 × 距离 × 线宽阶梯，逐个试到过为止。 - -## 下发**不能**用 `pcb2_route_dp.push()` - -那个函数会先把 net 上**所有**线和过孔删掉再重画 —— 对 GND 就是把 210 个扇出孔 -连同 BM24 的两条梳子全部抹掉。这里自己写一段只动**本脚本自己那几个对象**的 JS。 - -## ⚠️ 幂等靠 `_pcb2_gnd_patch.json` 这份「我上次画了啥」的清单 - -GND 上有两百多个别人的过孔，没法按网络整网重画，所以本脚本把自己下发的 -过孔/导线坐标记在 `_pcb2_gnd_patch.json` 里，下次 `--push` 先按坐标删掉它们再重画。 - -**不记账的代价实测过一次**：改完选点逻辑直接再 `--push`，板上就多出一对 -旧坐标的过孔（425 而不是 423），而且新画的短线被 EasyEDA 并进了旧的粗线里 —— -DRC 照样报错，看上去像"改了没生效"。 -""" -import json -import math -import os -import sys - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -import pcb2_route_dp as R -from pcb2_vo_vias import holes, local, place - -NET = 'GND' -STATE = os.path.join(HERE, '_pcb2_gnd_patch.json') -W_STEPS = [0.40, 0.30, 0.25, 0.20] # GND 没有专门的线宽规则，扇出历来用 0.30 -EPS = 1e-6 - - -def clusters(pads, vias, lines): - u"""GND 的连通域；返回**悬空的**那些（域里一个过孔/通孔焊盘都没有）。""" - items = [] - for p in pads: - if p['net'] == NET: - items.append(('pad', set((1, 2)) if p['lay'] == 12 else set((p['lay'],)), p)) - for v in vias: - if v['net'] == NET: - items.append(('via', set((1, 2)), v)) - for l in lines: - if l['net'] == NET: - items.append(('line', set((l['lay'],)), l)) - n = len(items) - par = list(range(n)) - - def find(i): - while par[i] != i: - par[i] = par[par[i]] - i = par[i] - return i - - def touch(a, b): - (ka, la, oa), (kb, lb, ob) = a, b - if not (la & lb): - return False - if ka == 'line' and kb == 'line': - return R.seg_seg((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), - (ob['x0'], ob['y0']), (ob['x1'], ob['y1'])) <= (oa['w'] + ob['w']) / 2 + EPS - if ka == 'line' and kb == 'pad': - return R.seg_rect((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), - ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['w'] / 2 + EPS - if ka == 'line' and kb == 'via': - return R.seg_pt(oa['x0'], oa['y0'], oa['x1'], oa['y1'], - ob['x'], ob['y']) <= oa['w'] / 2 + ob['r'] + EPS - if ka == 'via' and kb == 'via': - return math.hypot(oa['x'] - ob['x'], oa['y'] - ob['y']) <= oa['r'] + ob['r'] + EPS - if ka == 'via' and kb == 'pad': - return R.seg_rect((oa['x'], oa['y']), (oa['x'], oa['y']), - ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['r'] + EPS - if ka == 'pad' and kb == 'pad': - return False - return touch(b, a) - - for i in range(n): - for j in range(i + 1, n): - if touch(items[i], items[j]): - a, b = find(i), find(j) - if a != b: - par[a] = b - comp = {} - for i in range(n): - comp.setdefault(find(i), []).append(i) - out = [] - for _k, idx in comp.items(): - if any(items[i][0] == 'via' or (items[i][0] == 'pad' and items[i][2]['lay'] == 12) - for i in idx): - continue - out.append([items[i] for i in idx]) - return out - - -JS_ADD = u""" -await eda.dmt_EditorControl.openDocument('%s'); -await new Promise(r=>setTimeout(r,1800)); -const SEGS = %s, VIAS = %s, MIL = %f, OLD = %s; -// 先按坐标删掉**上一次本脚本画的**那几个（清单在 _pcb2_gnd_patch.json） -const hit = (x, y) => OLD.some(t => Math.hypot(x/MIL - t[0], y/MIL - t[1]) < 0.02); -let dv = 0, dl = 0; -for (const v of await eda.pcb_PrimitiveVia.getAll()) - if (v.getState_Net() === 'GND' && hit(v.getState_X(), v.getState_Y())) { - await eda.pcb_PrimitiveVia.delete(v.getState_PrimitiveId()); dv++; - } -for (const l of await eda.pcb_PrimitiveLine.getAll()) - if (l.getState_Net() === 'GND' - && (hit(l.getState_StartX(), l.getState_StartY()) || hit(l.getState_EndX(), l.getState_EndY()))) { - await eda.pcb_PrimitiveLine.delete(l.getState_PrimitiveId()); dl++; - } -let nl = 0, nv = 0; -for (const [net, lay, x0, y0, x1, y1, w] of SEGS) { - await eda.pcb_PrimitiveLine.create(net, lay, x0*MIL, y0*MIL, x1*MIL, y1*MIL, w*MIL); nl++; -} -for (const [net, x, y] of VIAS) { - await eda.pcb_PrimitiveVia.create(net, x*MIL, y*MIL, %f*MIL, %f*MIL); nv++; -} -await eda.pcb_Document.save(); -await new Promise(r=>setTimeout(r,1500)); -return {lines: nl, vias: nv, delVia: dv, delLine: dl, - totVia: (await eda.pcb_PrimitiveVia.getAll()).length}; -""" - - -def load_state(): - u"""上一轮本脚本下发的坐标（过孔中心 + 每段线的两端）。""" - try: - return json.load(open(STATE, encoding='utf-8')) - except Exception: - return [] - - -def drop_mine(pads, vias, lines): - u"""算之前先把**自己上一轮的产物**从障碍表里摘掉 —— 否则悬空焊盘已经不悬空了， - 脚本会以为没活干（而实际上那几个对象马上就要被删掉重画）。""" - old = load_state() - - def mine(x, y): - return any(math.hypot(x - a, y - b) < 0.02 for a, b in old) - vias = [v for v in vias if not mine(v['x'], v['y'])] - lines = [l for l in lines - if not (mine(l['x0'], l['y0']) or mine(l['x1'], l['y1'])) or l['net'] != NET] - return pads, vias, lines - - -def push_add(routes): - u"""**只 create、不 delete** —— GND 上有 210 个扇出孔和 BM24 的梳子，一删就完。""" - segs, vias = [], [] - for key, path in routes.items(): - net = R.netof(key) - s, v = R.expand(path) - for x0, y0, x1, y1, lay, w in s: - segs.append([net, lay, x0, y0, x1, y1, w]) - for x, y in v: - vias.append([net, x, y]) - old = load_state() - r = R.run(JS_ADD % (R.PCB, json.dumps(segs), json.dumps(vias), R.MIL, - json.dumps(old), R.VIA_H, R.VIA_D), timeout=600) - if not r.get('success'): - sys.exit(u'下发失败: ' + json.dumps(r, ensure_ascii=False)[:500]) - d = r['result'] - pts = [[v[1], v[2]] for v in vias] - pts += [[s_[2], s_[3]] for s_ in segs] + [[s_[4], s_[5]] for s_ in segs] - json.dump(pts, open(STATE, 'w', encoding='utf-8')) - print(u'下发完成：先删掉自己上一轮的 %d 孔 / %d 线，再画 %d 线 / %d 孔，板上过孔共 %d 个' - % (d['delVia'], d['delLine'], d['lines'], d['vias'], d['totVia'])) - - -def main(): - if '--check' in sys.argv: - # ⚠️ 不摘自己上一轮的产物 —— 这一支回答的是「板子现在还有没有悬空 GND」， - # 默认那一支回答的是「要画成什么样」（所以必须先摘掉自己画的再算）。 - left = clusters(*R.geom()) - print(u'板上还悬空的 GND 连通域 %d 个' % len(left)) - for cl in left: - print(u' %s' % ' + '.join('%s.%s' % (o['ref'], o['num']) - for k, _l, o in cl if k == 'pad')) - sys.exit(1 if left else 0) - pads, vias, lines = drop_mine(*R.geom()) - floats = clusters(pads, vias, lines) - print(u'悬空的 GND 连通域 %d 个:' % len(floats)) - if not floats: - print(u' 没有 —— 不用补。') - return - - hl = holes(pads) - routes, mine, mvias, fail = {}, [], [], 0 - for k, cl in enumerate(floats): - cands = [o for kind, _l, o in cl if kind == 'pad'] - desc = ' + '.join('%s.%s' % (o['ref'], o['num']) for o in cands) - best = None - for pad in cands: # 域里哪个焊盘都行，取第一个打得下孔的 - lp, lv, ll, lh = local(pads, vias, lines, pad['x'], pad['y'], hl) - lay = R.L_TOP if pad['lay'] == 1 else R.L_BOT - got = place(pad, lay, W_STEPS, lp, lv, ll, lh, mine, mvias) - if got: - best = (pad, lay) + got - break - if not best: - print(u' [!!] %-28s 找不到能落孔的位置' % desc) - fail += 1 - continue - pad, lay, w, segs, (vx, vy) = best - other = R.L_BOT if lay == R.L_TOP else R.L_TOP - pts = [(segs[0][1], segs[0][2], lay, w)] + [(x1, y1, lay, w) for _l, _a, _b, x1, y1, _w in segs] - routes[u'%s#patch%d' % (NET, k)] = pts + [(vx, vy, other, w), (vx, vy, other, w)] - for l_, x0, y0, x1, y1, w_ in segs: - mine.append((NET, l_, x0, y0, x1, y1, w_)) - mvias.append((NET, vx, vy)) - print(u' %-28s 从 %s.%s 出，过孔 (%8.3f,%8.3f) %d 段 线宽 %.2f' - % (desc, pad['ref'], pad['num'], vx, vy, len(segs), w)) - - segs = sum(len(R.expand(p)[0]) for p in routes.values()) - nv = sum(len(R.expand(p)[1]) for p in routes.values()) - print(u'') - print(u'%d/%d 个域搞定：%d 段导线 / %d 个过孔' % (len(routes), len(floats), segs, nv)) - if nv != len(routes): - sys.exit(u'!! 过孔数和域数对不上 —— expand() 又把末端过孔吞了') - n_sharp = len(R.sharp_corners(routes)) - print(u'直角拐点 %d（拐弯只许 45°，应当是 0）' % n_sharp) - print(u'') - print(u'净距校核（一般 %.2f mm）:' % R.CLR) - bad = R.check(routes, pads, vias, lines) - if not bad: - print(u' 全部通过 ✔') - - if '--push' in sys.argv: - if bad or fail or n_sharp: - sys.exit(u'\n!! 有未解决的问题，不下发。') - push_add(routes) - print(u'下一步必须重铺：/c/Python314/python .claude/pcb2_pour.py --push') - - -if __name__ == '__main__': - main() +# -*- coding: utf-8 -*- +u"""补上 §25.8 遗留的**悬空 GND 焊盘** —— 自己找出来，自己打孔。 + + /c/Python314/python .claude/pcb2_route_dp.py --dump # 1. 先刷障碍表 + /c/Python314/python .claude/pcb2_gnd_patch.py # 2. 找悬空 + 选孔位 + 净距校核 + /c/Python314/python .claude/pcb2_gnd_patch.py --check # 只问「现在板上还有没有悬空的」 + /c/Python314/python .claude/pcb2_gnd_patch.py --push # 3. 下发（**只加不删**） + /c/Python314/python .claude/pcb2_pour.py --push # 4. 必须重铺 + +## 「悬空」是自己算的，不是抄 DRC + +把 GND 网络的**焊盘 / 过孔 / 导线**当图，两两相触连边（判据同 `pcb2_net_conn.py`）， +一个连通域里只要有**一个过孔或一个通孔焊盘**，它就落到 Inner1/Inner2 的地平面上 = 连通。 +**一个都没有的连通域就是悬空的** —— 那是纯顶层/底层的一小块孤铜。 + +⇒ 这个判据是幂等的：补完孔再跑一次，找到 0 个。 + +## 和 `pcb2_fanout.py` 的分工 + +`pcb_fanout` 是**批量**扇出（210 个孔），它对每个焊盘只试固定的几个方位， +挤不下就跳过 —— §25.8 里剩下的这几个就是被它跳过的。 +这里换成和 `pcb2_vo_vias.py` 同一套搜索：8 个方向 × 距离 × 线宽阶梯，逐个试到过为止。 + +## 下发**不能**用 `pcb2_route_dp.push()` + +那个函数会先把 net 上**所有**线和过孔删掉再重画 —— 对 GND 就是把 210 个扇出孔 +连同 BM24 的两条梳子全部抹掉。这里自己写一段只动**本脚本自己那几个对象**的 JS。 + +## ⚠️ 幂等靠 `_pcb2_gnd_patch.json` 这份「我上次画了啥」的清单 + +GND 上有两百多个别人的过孔，没法按网络整网重画，所以本脚本把自己下发的 +过孔/导线坐标记在 `_pcb2_gnd_patch.json` 里，下次 `--push` 先按坐标删掉它们再重画。 + +**不记账的代价实测过一次**：改完选点逻辑直接再 `--push`，板上就多出一对 +旧坐标的过孔（425 而不是 423），而且新画的短线被 EasyEDA 并进了旧的粗线里 —— +DRC 照样报错，看上去像"改了没生效"。 +""" +import json +import math +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +import pcb2_route_dp as R +from pcb2_vo_vias import holes, local, place + +NET = 'GND' +STATE = os.path.join(HERE, '_pcb2_gnd_patch.json') +W_STEPS = [0.40, 0.30, 0.25, 0.20] # GND 没有专门的线宽规则，扇出历来用 0.30 +EPS = 1e-6 + + +def clusters(pads, vias, lines): + u"""GND 的连通域；返回**悬空的**那些（域里一个过孔/通孔焊盘都没有）。""" + items = [] + for p in pads: + if p['net'] == NET: + items.append(('pad', set((1, 2)) if p['lay'] == 12 else set((p['lay'],)), p)) + for v in vias: + if v['net'] == NET: + items.append(('via', set((1, 2)), v)) + for l in lines: + if l['net'] == NET: + items.append(('line', set((l['lay'],)), l)) + n = len(items) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + def touch(a, b): + (ka, la, oa), (kb, lb, ob) = a, b + if not (la & lb): + return False + if ka == 'line' and kb == 'line': + return R.seg_seg((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), + (ob['x0'], ob['y0']), (ob['x1'], ob['y1'])) <= (oa['w'] + ob['w']) / 2 + EPS + if ka == 'line' and kb == 'pad': + return R.seg_rect((oa['x0'], oa['y0']), (oa['x1'], oa['y1']), + ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['w'] / 2 + EPS + if ka == 'line' and kb == 'via': + return R.seg_pt(oa['x0'], oa['y0'], oa['x1'], oa['y1'], + ob['x'], ob['y']) <= oa['w'] / 2 + ob['r'] + EPS + if ka == 'via' and kb == 'via': + return math.hypot(oa['x'] - ob['x'], oa['y'] - ob['y']) <= oa['r'] + ob['r'] + EPS + if ka == 'via' and kb == 'pad': + return R.seg_rect((oa['x'], oa['y']), (oa['x'], oa['y']), + ob['x'], ob['y'], ob['hw'], ob['hh']) <= oa['r'] + EPS + if ka == 'pad' and kb == 'pad': + return False + return touch(b, a) + + # 2026-09-07：包围盒预筛。原来纯两两比对，第三十轮 GND 件数上去之后跑了 20 多分钟没出来。 + # 每件算一个外扩 EPS 的包围盒，先按 x 排序，只比 x 区间相交的对。 + def _bb(it): + k, _, o = it + if k == 'line': + r = o['w'] / 2.0 + return (min(o['x0'], o['x1']) - r, min(o['y0'], o['y1']) - r, + max(o['x0'], o['x1']) + r, max(o['y0'], o['y1']) + r) + if k == 'via': + return (o['x'] - o['r'], o['y'] - o['r'], o['x'] + o['r'], o['y'] + o['r']) + return (o['x'] - o['hw'], o['y'] - o['hh'], o['x'] + o['hw'], o['y'] + o['hh']) + bbs = [_bb(it) for it in items] + order = sorted(range(n), key=lambda i: bbs[i][0]) + for oi, i in enumerate(order): + bi = bbs[i] + for j in order[oi + 1:]: + bj = bbs[j] + if bj[0] > bi[2] + EPS: + break + if bj[1] > bi[3] + EPS or bj[3] < bi[1] - EPS: + continue + if touch(items[i], items[j]): + a, b = find(i), find(j) + if a != b: + par[a] = b + comp = {} + for i in range(n): + comp.setdefault(find(i), []).append(i) + out = [] + for _k, idx in comp.items(): + if any(items[i][0] == 'via' or (items[i][0] == 'pad' and items[i][2]['lay'] == 12) + for i in idx): + continue + out.append([items[i] for i in idx]) + return out + + +JS_ADD = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,1800)); +const SEGS = %s, VIAS = %s, MIL = %f, OLD = %s; +// 先按坐标删掉**上一次本脚本画的**那几个（清单在 _pcb2_gnd_patch.json） +const hit = (x, y) => OLD.some(t => Math.hypot(x/MIL - t[0], y/MIL - t[1]) < 0.02); +let dv = 0, dl = 0; +for (const v of await eda.pcb_PrimitiveVia.getAll()) + if (v.getState_Net() === 'GND' && hit(v.getState_X(), v.getState_Y())) { + await eda.pcb_PrimitiveVia.delete(v.getState_PrimitiveId()); dv++; + } +for (const l of await eda.pcb_PrimitiveLine.getAll()) + if (l.getState_Net() === 'GND' + && (hit(l.getState_StartX(), l.getState_StartY()) || hit(l.getState_EndX(), l.getState_EndY()))) { + await eda.pcb_PrimitiveLine.delete(l.getState_PrimitiveId()); dl++; + } +let nl = 0, nv = 0; +for (const [net, lay, x0, y0, x1, y1, w] of SEGS) { + await eda.pcb_PrimitiveLine.create(net, lay, x0*MIL, y0*MIL, x1*MIL, y1*MIL, w*MIL); nl++; +} +for (const [net, x, y] of VIAS) { + await eda.pcb_PrimitiveVia.create(net, x*MIL, y*MIL, %f*MIL, %f*MIL); nv++; +} +await eda.pcb_Document.save(); +await new Promise(r=>setTimeout(r,1500)); +return {lines: nl, vias: nv, delVia: dv, delLine: dl, + totVia: (await eda.pcb_PrimitiveVia.getAll()).length}; +""" + + +def load_state(): + u"""上一轮本脚本下发的坐标（过孔中心 + 每段线的两端）。""" + try: + return json.load(open(STATE, encoding='utf-8')) + except Exception: + return [] + + +def drop_mine(pads, vias, lines): + u"""算之前先把**自己上一轮的产物**从障碍表里摘掉 —— 否则悬空焊盘已经不悬空了， + 脚本会以为没活干（而实际上那几个对象马上就要被删掉重画）。""" + old = load_state() + + def mine(x, y): + return any(math.hypot(x - a, y - b) < 0.02 for a, b in old) + vias = [v for v in vias if not mine(v['x'], v['y'])] + lines = [l for l in lines + if not (mine(l['x0'], l['y0']) or mine(l['x1'], l['y1'])) or l['net'] != NET] + return pads, vias, lines + + +def push_add(routes): + u"""**只 create、不 delete** —— GND 上有 210 个扇出孔和 BM24 的梳子，一删就完。""" + segs, vias = [], [] + for key, path in routes.items(): + net = R.netof(key) + s, v = R.expand(path) + for x0, y0, x1, y1, lay, w in s: + segs.append([net, lay, x0, y0, x1, y1, w]) + for x, y in v: + vias.append([net, x, y]) + old = load_state() + r = R.run(JS_ADD % (R.PCB, json.dumps(segs), json.dumps(vias), R.MIL, + json.dumps(old), R.VIA_H, R.VIA_D), timeout=600) + if not r.get('success'): + sys.exit(u'下发失败: ' + json.dumps(r, ensure_ascii=False)[:500]) + d = r['result'] + pts = [[v[1], v[2]] for v in vias] + pts += [[s_[2], s_[3]] for s_ in segs] + [[s_[4], s_[5]] for s_ in segs] + json.dump(pts, open(STATE, 'w', encoding='utf-8')) + print(u'下发完成：先删掉自己上一轮的 %d 孔 / %d 线，再画 %d 线 / %d 孔，板上过孔共 %d 个' + % (d['delVia'], d['delLine'], d['lines'], d['vias'], d['totVia'])) + + +def main(): + if '--check' in sys.argv: + # ⚠️ 不摘自己上一轮的产物 —— 这一支回答的是「板子现在还有没有悬空 GND」， + # 默认那一支回答的是「要画成什么样」（所以必须先摘掉自己画的再算）。 + left = clusters(*R.geom()) + print(u'板上还悬空的 GND 连通域 %d 个' % len(left)) + for cl in left: + print(u' %s' % ' + '.join('%s.%s' % (o['ref'], o['num']) + for k, _l, o in cl if k == 'pad')) + sys.exit(1 if left else 0) + pads, vias, lines = drop_mine(*R.geom()) + floats = clusters(pads, vias, lines) + print(u'悬空的 GND 连通域 %d 个:' % len(floats)) + if not floats: + print(u' 没有 —— 不用补。') + return + + hl = holes(pads) + routes, mine, mvias, fail = {}, [], [], 0 + for k, cl in enumerate(floats): + cands = [o for kind, _l, o in cl if kind == 'pad'] + desc = ' + '.join('%s.%s' % (o['ref'], o['num']) for o in cands) + best = None + for pad in cands: # 域里哪个焊盘都行，取第一个打得下孔的 + lp, lv, ll, lh = local(pads, vias, lines, pad['x'], pad['y'], hl) + lay = R.L_TOP if pad['lay'] == 1 else R.L_BOT + got = place(pad, lay, W_STEPS, lp, lv, ll, lh, mine, mvias) + if got: + best = (pad, lay) + got + break + if not best: + print(u' [!!] %-28s 找不到能落孔的位置' % desc) + fail += 1 + continue + pad, lay, w, segs, (vx, vy) = best + other = R.L_BOT if lay == R.L_TOP else R.L_TOP + pts = [(segs[0][1], segs[0][2], lay, w)] + [(x1, y1, lay, w) for _l, _a, _b, x1, y1, _w in segs] + routes[u'%s%spatch%d' % (NET, R.KSEP, k)] = pts + [(vx, vy, other, w), (vx, vy, other, w)] + for l_, x0, y0, x1, y1, w_ in segs: + mine.append((NET, l_, x0, y0, x1, y1, w_)) + mvias.append((NET, vx, vy)) + print(u' %-28s 从 %s.%s 出，过孔 (%8.3f,%8.3f) %d 段 线宽 %.2f' + % (desc, pad['ref'], pad['num'], vx, vy, len(segs), w)) + + segs = sum(len(R.expand(p)[0]) for p in routes.values()) + nv = sum(len(R.expand(p)[1]) for p in routes.values()) + print(u'') + print(u'%d/%d 个域搞定：%d 段导线 / %d 个过孔' % (len(routes), len(floats), segs, nv)) + if nv != len(routes): + sys.exit(u'!! 过孔数和域数对不上 —— expand() 又把末端过孔吞了') + n_sharp = len(R.sharp_corners(routes)) + print(u'直角拐点 %d（拐弯只许 45°，应当是 0）' % n_sharp) + print(u'') + print(u'净距校核（一般 %.2f mm）:' % R.CLR) + bad = R.check(routes, pads, vias, lines) + if not bad: + print(u' 全部通过 ✔') + + if '--push' in sys.argv: + if bad or fail or n_sharp: + sys.exit(u'\n!! 有未解决的问题，不下发。') + push_add(routes) + print(u'下一步必须重铺：/c/Python314/python .claude/pcb2_pour.py --push') + + +if __name__ == '__main__': + main() diff --git a/.claude/pcb2_parts_dump.py b/.claude/pcb2_parts_dump.py index 78c6c6a..2d94aaf 100644 --- a/.claude/pcb2_parts_dump.py +++ b/.claude/pcb2_parts_dump.py @@ -12,7 +12,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' # PCB2-CARRIER +PCB = '942ed1560d81c1e7' # PCB2-CARRIER OUT = os.path.join(HERE, 'pcb2-parts.json') JS = u""" diff --git a/.claude/pcb2_place.py b/.claude/pcb2_place.py index 6a9474e..0e1eb11 100644 --- a/.claude/pcb2_place.py +++ b/.claude/pcb2_place.py @@ -79,28 +79,95 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' # PCB2-CARRIER +PCB = '942ed1560d81c1e7' # PCB2-CARRIER MIL = 39.3700787401575 BW, BH = 220.0, 135.0 # 板框 mm CORNER_R = 5.0 # 载板自己的 M3 安装孔（来历见 obsolete/pcb2_place_topside_2026-09-06.py 文件头，位置没动）。 MH = [(8.0, 8.0), (212.0, 8.0), (7.0, 60.0), (213.0, 45.0), - (76.6, 79.5), (148.1, 79.5)] # v3：中跨孔随上排下移 0.6（焊盘顶 82.5 < 83.0） + (76.6, 79.5), (148.1, 79.5), # v3：中跨孔随上排下移 0.6（焊盘顶 82.5 < 83.0） + # 2026-09-06 用户指令「两板尺寸取大对齐、四角定位孔对齐」：下板改成同样的 220×135、 + # 四角孔与本板重合。底部两角本来就有 (8,8)/(212,8)；顶部两角被上排主板（y ≤ 127.66）和 + # 尾插槽（site1 x 8.09~27.09，见 SLOTS 注释）夹住，只剩板角 4×4 那一块： + # 孔心 (4,131)/(216,131)，焊盘 Ø6 → 离板边 1.0、离主板边 0.34（主板架在 3 mm 立柱上，螺钉头 ≤ 2）、离槽 1.09。 + (4.0, 131.0), (216.0, 131.0)] MH_HOLE, MH_PAD = 3.2, 6.0 MH_KEEP = 3.5 # 底层元件离 M3 孔中心的最小距离（螺钉头 Ø6） # ---- 小米8 主板（顶视，板左下角原点，mm）---- -PW, PH = 67.09, 44.66 -HOLES = {'H1': (54.2, 42.3), 'H2': (2.6, 38.2), 'H3': (61.9, 33.7), 'H4': (62.1, 29.2), - 'H5': (2.6, 27.0), 'H6': (4.0, 10.8), 'H7': (42.6, 3.7)} -HOLE_D = 2.5 # 载板上的定位孔，NPTH -HOLE_KEEP = 2.8 # 底层元件离定位孔中心的最小距离（M2.5 尼龙螺钉头 Ø4.5 + 余量） +# 2026-09-06 实测替换（旧值的 7 孔是**从照片认的**，最大错 4.8 mm）。 +# 新值来源：测量底板（四基准点 Φ6，圆心矩形 160x110）上描轮廓 + 每孔戳一点 -> 扫描 -> +# `pcb2_measure_read.py` 单应反算。**再拿真主板平板扫描件做了一次独立复核**： +# 用这 7 个孔去套扫描件上的孔，**7/7 命中、平均残差 0.38 mm**（`_fit.png`）。 +# ⚠️ 编号整体重排过，别拿旧 H 号对新 H 号。 +# ⚠️ 板长 67 = **裸板**。用户描轮廓时 SIM 卡托还插着，卡托在 u 大的那一端伸出约 3.3 mm， +# 所以描出来是 70.3。他早先给的 u 值是拿 66 / 70.3 混着换算的，才有那 3~4 mm 的怪差。 +PW, PH = 67.0, 44.0 +HOLES = {'H1': (1.4, 9.9), 'H2': (0.7, 27.3), 'H3': (1.7, 38.7), 'H4': (41.9, 1.9), + 'H5': (57.4, 41.2), 'H6': (64.6, 28.1), 'H7': (64.8, 32.4)} +HOLE_D = 1.8 # 载板上的定位孔，NPTH。2026-09-06 用户卡尺：**主板孔 Φ2.0** + # （先前口头的 Φ1.5 作废）。Φ2.0 是手机自己的过孔 ⇒ 配 **M1.6 尼龙立柱** + # （M2 螺杆 Φ2.0 塞 Φ2.0 没余量，不选）；载板这侧是螺钉过孔，取 M1.6 的通孔 Φ1.8。 + # 原来整套按 Φ2.5 / M2.5 做的，是错的。 +HOLE_KEEP = 2.2 # 底层元件离定位孔中心的最小距离（M1.6 尼龙螺钉头 Ø3.2 + 余量） +# 2026-09-07：**H5 不打**。J61~J65（EDL 座）离 P*H5 只有 0.92（要 2.2），二选一里「不打 H5」代价为零： +# 每台还有 6 颗螺钉，H5 在 u 大 / v 大那个角（离侧键触点最远的角），那里没有需要压紧的东西。 +# 模型里 HOLES 保留 7 个（它是实测数据），只在下发孔 / 螺钉头避让时跳过这里列的。 +SKIP_HOLES = {'H5'} -# 侧键触点（§22.3b，已折算成顶视投影）。顶针顺序 = c4_site.py 的 pogo[0..3] -POGO_XY = [(3.11, 6.91), (2.70, 4.60), (5.41, 6.52), (2.12, 2.46)] +# 侧键触点。旧值（§22.3b 那四个点）是从照片认的，**内部排布是错的**，见下。 +# +# ---- 已经问清楚的（可信）---- +# 触点是 **4 个 Φ1.35 的圆盘，排成菱形**：相邻 1.87 mm、对角 2.65 mm。 +# 来源：中框（配合件）上那四个金色焊盘的平板扫描，边界干净，k-means 分开后直接量。 +# ⚠️ **顶针本体直径必须 < 1.87 mm**，常规 Φ2 以上的排不下 —— 选型硬约束。 +# +# ---- 位置：**中框螺柱配准**那一版（已被卡尺判定为正确）---- +# 2026-09-06：用户卡尺实测 **H1 孔心到四触点菱形中心 = 5 mm**，判死了两条路之争： +# 中框配准版 (3.42, 5.07) -> 离 H1 5.24 mm ✔ 采信 +# 红漆配准版 (0.81, 7.08) -> 离 H1 2.88 mm �’ 弃 +# 红漆那条当时的论据是「同图内量到最近孔 2.7 mm，不经配准也不吃手性」，**论据是错的**： +# 那个「最近的孔」是环形滤波器几百个候选里的一个，多半是过孔/焊盘误报，不是真孔。 +# ⚠️ 教训：环形滤波器在这块板上误报率极高，**任何"离最近的孔多少"都不能直接用**， +# 必须先确认那个候选真的是 7 孔之一。 +# 旁证：中框版四个点全在板内（红漆版算出 GND 在板边外 0.5 mm，与用户「GND 离短板边最近」矛盾）， +# 而且和旧 §22.3b 的簇心 (3.34, 5.12) 只差 0.1 mm —— 旧数据的**簇心本来就是对的，错的是内部排布**。 +# 下面四个坐标直接取中框配准的实测值（不是理想菱形），残差 0.57 mm。 +POGO_XY = [(4.72, 5.16), # PWR 电源 u+ + (3.42, 6.37), # VUP 音量+ v+ + (3.49, 3.74), # VDN 音量- v- + (2.05, 4.99)] # GND u- POGO_TAG = ['J603 PWR', 'J601 VUP', 'J602 VDN', 'J604 GND'] +# ---- 2026-09-06 用户改方案：**顶针取消，改成和中框一样的焊盘** ---- +# 装配方式跟着改：不再靠顶针弹力，而是**用螺丝把主板压在载板上**， +# 由主板自己的侧键弹片直接压在载板的焊盘上 —— 完全复刻中框的接触方式。 +# 好处：顶针那个「本体必须 < 1.87 mm」的硬卡点直接消失（现有 POGO-SMD1P_D1.9 的 Ø1.9 +# 在真实 1.78 mm 最小间距下是负净距，正是那 20 条重叠的来源）。 +# +# 焊盘定径：四点实测最小间距 **1.78 mm**（不是理想菱形的 1.87）⇒ +# 净距 0.20 -> 最大 Ø1.58 · 净距 0.25 -> Ø1.53 · 净距 0.30 -> Ø1.48 +# 中框原盘 Ø1.35。取 **Ø1.5**：净距 0.28（好做），容许位置误差 0.50 mm。 +POGO_PAD_D = 1.5 +# ⚠️ **位置不确定度 ±0.6 mm 已经吃掉全部余量**（Ø1.5 只容许 0.50）。 +# 打样前必须把触点位置收到 ±0.3：办法是「**一次装夹**」—— +# 主板放测量底板上，先戳 7 个孔、再把弹片涂红盖印，孔和触点落进同一套基准圆，一次量完。 +# ⚠️ **立柱高度 3.0 -> 1.0 mm**：2026-09-06 用户实测中框「螺柱支撑面 到 金焊盘面 = 1 mm」， +# 这就是载板面到主板贴合面该有的间隙。原来是 3.0 mm 立柱 + 顶针压缩 0.5，整套作废。 +# ✅ **不用挖空**：2026-09-06 用户实测「贴合面上元件全都低于 1 mm」（屏蔽罩、SIM 卡座都算过）， +# 所以载板**保持平板**，1.0 mm 间隙直接成立。曾担心的「挖空会和底层 BAND 那组元件打架」不存在了。 +# ✅ 排线反而更宽裕（绕边下落 5 -> 3 mm）： +# 尾插 2.9 + 3 + 2.9 + 1.6 + 34.1 ≈ 44.5 ≤ 50（原 46.5） +# 电池 4.6 + 3 + ... ≈ 29.6 ≤ 35（原 31.6） +# ⇒ §25.16 那串长度核算只会更松，不用改路径。 +# ⚠️ **1 mm 立柱不好买**：M1.6 尼龙立柱通常从 3 mm 起。可行做法是 +# 「螺钉从上穿过手机孔 + 1 mm 尼龙垫片 + 穿过载板 Φ1.8 孔 + 底面尼龙螺母」。垫片可叠。 +# ⚠️ 顶角那两个 M3 孔（4,131)/(216,131) 的旧注释写着「主板架在 3 mm 立柱上，螺钉头 ≤ 2」—— +# 现在只剩 1 mm，那两个孔真要补的话螺钉头必须 ≤ 1 或者挪开。（它们本来就没打到板上。） +POGO_STANDOFF_H = 1.0 + + # ---- 五个手机位：本体左下角 + 旋转（0 = 接口边朝下，180 = 接口边朝上；to_board 里 rot 180 是绕本体中心转，位置矩形不变）---- # v3（2026-09-06 用户拍板）：穿线槽挪到**主板投影外侧、靠板边**那一条，排线（按 6 cm 算） # 跨过主板正面到远端边、下穿、再折回底面。上排下移 / 下排上移各 2.5 mm，让板边那条留出 @@ -132,7 +199,9 @@ SLOTS = { # 2026-09-06 v4c（用户拍板）：尾插槽挪到**和电池槽同一条线**（接口边外侧 v −4.2~−1.2），排线翻过接口边直接下穿， # 不再从主板反面 3.0 mm 的缝里钻。背面到 J7n 变长 5.6，J7n 从 v 37 收到 **v 35**： # 2.86 + 绕边 5 + 到槽心 2.7 + 穿板 1.6 + 背面 37.7 ≈ 49.9 ≤ 50 ✔（实长 55）。 - 'tail': (45.0, 65.0, -4.2, -1.2), # 尾插排线：接口边外侧，与电池槽同线，正对 J1401 (u 47.5~59.7) + # 2026-09-06 顶角 M3 孔 (4,131)：site1 rot 180 下槽的 x = 72.09 − u，u=65 → x 7.09 会压到 Ø6 焊盘（边 7.0）。 + # 东端 65 → 64（x 8.09，离焊盘 1.09）。排线 18 宽盖 u 44.6~62.6，64 端还余 1.4。 + 'tail': (45.0, 64.0, -4.2, -1.2), # 尾插排线：接口边外侧，与电池槽同线，正对 J1401 (u 47.5~59.7) } # 排线在背面占的车道（本体坐标）。**车道里不放任何元件**（排线要平贴着走到插头 / 焊盘，0402 也别放）： # 尾插排线 u 44.6~62.6，v 4.4 ~ J7n 北沿（EDL 组 / VBUS 组因此整体西移到 u ≤ 44）； @@ -195,6 +264,19 @@ BAND = { 'r76': (52.233, 38.0, 0), # R76n 56k CC1→VBUS，pin1 (51.800) = J7n.22 正北 'r77': (54.8, 38.0, 0), # R77n 100k，pin1 (54.367) 收 THERM 'j6': (62.5, 41.0, 0), # J6n EDL 1.25mm 2P，J7n 东北、H1 keep-out 东侧；EDL 飞线随尾插排线穿槽走背面 ~40 mm + # ── 按键 MOS 三列（2026-09-06 随 74HC595 从下板搬来，§26.23）：顶针（顶层，u 2.1~5.4 / v 2.5~7）背面那片空地。 + # 列距 3.5；SOT-23 框 ±1.5×±1.27，0402 框 ±0.72×±0.27（竖放 ±0.27×±0.72）。 + # 东沿 15.5+1.5 = 17.0 < 电池排线车道 18.8；离 H6 (4,10.8) 最近的是 R%21 (8.5,10)：4.6 > 2.8； + # 漏极→顶针焊盘要换层（顶针是顶层单面焊盘），过孔由布线器自己打。 + 'q3': (8.5, 4.0, 0), # Q%03 PWR + 'q4': (12.0, 4.0, 0), # Q%04 VUP + 'q5': (15.5, 4.0, 0), # Q%05 VDN + 'r20': (8.5, 7.5, 90), # R%20 1k 栅阻 + 'r22': (12.0, 7.5, 90), + 'r24': (15.5, 7.5, 90), + 'r21': (8.5, 10.0, 90), # R%21 100k 栅极下拉 + 'r23': (12.0, 10.0, 90), + 'r25': (15.5, 10.0, 90), } # SMD 罐体 keep-out（相对元件原点）：10.3 见方 + 单边 0.25 CAN_BODY = (-5.4, -5.4, 5.4, 5.4) @@ -211,6 +293,9 @@ def desig(n): 'j7': 'J7%d' % n, 'u5': 'U5%d' % n, 'r76': 'R76%d' % n, 'r77': 'R77%d' % n, 'u2': 'U%d' % (23 + n), 'c70': 'C70%d' % n, 'c71': 'C71%d' % n, 'c72': 'C72%d' % n, 'r70': 'R70%d' % n, + 'q3': 'Q%d03' % n, 'q4': 'Q%d04' % n, 'q5': 'Q%d05' % n, + 'r20': 'R%d20' % n, 'r21': 'R%d21' % n, 'r22': 'R%d22' % n, + 'r23': 'R%d23' % n, 'r24': 'R%d24' % n, 'r25': 'R%d25' % n, } @@ -246,7 +331,23 @@ GLOBAL = { # v3 布线：U31 组挪到 J31 东端**南**侧（走廊北带 y 70~80 留给差分对上顶层北上） 'U31': (87.5, 60.5, 0), # 底边 57.65 让开 CH4 电池槽（y ≤ 56.36 + 0.5）；USB1 车道改走 y 64.0/64.46 'C736': (80.5, 58.5, 0), # +5V 输入 0805（U31 西侧） - 'C737': (93.0, 54.0, 0), # +3V3 输出 1206，Hub 晶振窝西南、CH4 电池槽东侧 + # ── 2026-09-07：U32 的 PRT_SWP1~5 五个 strap 脚的 100k 下拉（R900~R904，见 §21.6a）── + # BOOST/GANG_EN/SWP6-7 那五颗用户拍板不装（采到 1 也无功能后果）。 + # ⚠️ 第一版把十颗全摆在 U32 北边 y=79 那一排（那一片唯一的整块空地）， + # `pcb2_route_sig` **10 条只布通 3 条** —— 南边(49/50/51)、西边(15/17)、东南(47/48) + # 那七个脚要绕过整颗 QFN 和一圈去耦，绕不出去。改成**每颗贴着自己的引脚**。 + # 坐标是 `pcb2_strap_place.py` 按布线器的障碍表搜出来的（以引脚为心一圈圈往外找， + # 判据：两个焊盘离异网铜 >= 0.20 且不落进任何已有元件的本体投影）。改摆位请重跑它。 + 'R904': (103.458, 73.632, 0), # U32.31 PRT_SWP5，离脚 1.2 mm + 'R903': (105.632, 71.958, 90), # U32.33 PRT_SWP4，离脚 1.2 mm + 'R902': (106.635, 62.145, 0), # U32.47 PRT_SWP3，离脚 3.4 mm + 'R901': (103.021, 59.414, 0), # U32.49 PRT_SWP2，离脚 4.2 mm + 'R900': (102.750, 58.550, 0), # U32.51 PRT_SWP1，离脚 5.0 mm + # 2026-09-07：C737 由 1206 陶瓷换成 KEMET T491A226K010AT 固态钽（AMS1117 手册 §Stability + # 要求的 22uF 固态钽）。钽是极性件且 1 脚 = 正极，而板上 +3V3_HUB 的铜在东、GND 在西， + # 所以必须 rot 180；再东移 0.17 mm，让 1 脚（+3V3_HUB）西沿离那颗 GND 过孔 0.265 mm。 + # 改这两个数之前先读 §26.25：0.17 是算出来的净距，不是随手摆的。 + 'C737': (93.17, 54.0, 180), # +3V3 输出，CASE-A_3216 固态钽 # LM75BD 测温 + 100nF（SCL/SDA 在 J31.21/23 = x 63.3/65.8，北排；走线从排母针缝里穿到南边） # v2 第二版：挪到 J31 **南**边（走廊北带 y 70~76 要留给差分高速路）。CH4 行 B 只剩 U54(48.3)/R764/R774，这里是空的。 # v3 布线：J31 **南**边（USB1 那对在底层 y 62.9/63.6 从排母南边一路西行，U34 顶边 62.2） @@ -255,6 +356,30 @@ GLOBAL = { # 上游 VBUS 分压 -> UP_VBUS_DET -> J31 pin36 (81.049, 65.100)，跟着高阻端走 'R721': (80.0, 61.5, 180), # pin1 = VBUS_UP（v3：让开 U31 与 USB1 车道） 'R722': (78.0, 61.5, 180), # pin1 = UP_VBUS_DET, pin2 = GND + # ── 三片 74HC595（2026-09-06 从下板搬来，§26.23）。SOIC-16 框 9.5 × 7.44（rot 90 后 7.44 宽 × 9.5 高）。 + # 走廊中段 x 113~132 里能用的其实只有 **y 60.8~75.26 那条带**：UP_DP/UP_DM（底层 y 60.1/60.6）从 x 99 一路横穿到 205， + # 下面 y 52.5/53.0 是 USB5，上面 y 75.4/77.0 是 USB3（第一版只查了端点落在框里的线，把 UP 这对漏了， + # U21 rot 0 摆在 y 58.5 直接压在 UP 上；再上一版 rot 90 面对面缝 1.56，16 个脚的出线口互相堵死）。 + # U21 (117,66.5) / U22 (128,66.5) rot 90：x 113.28~120.72 / 124.28~131.72（缝 3.56，出线段各 1.3 还剩 1 mm）， + # y 61.75~71.25：离 UP_DM 线边 60.74 有 1.0，离 USB3_DP 线边 75.26 有 4.0；离 USB5 竖段 111.44 有 1.84、离 J32 焊盘边 133.0 有 1.28。 + # U33 单独放 **J32 东侧**（x 183~208 / y 52~86 只有 UP 那对在 y 60.1/60.6 横穿）：(193.5,68.5) rot 90 → y 63.75~73.25，离 UP_DM 3.0。 + # 四根控制线从 J32 北排 3~6 行（x 138.95~146.57）进来，正好夹在两处中间。 + # 2026-09-07 第三十轮：rot 90 的两片各 8 个西排脚全从 x 113~114 / 124 那两条竖缝出线，8 个网络布不通 + # （EDL_EN2/3/5、K5_VDN 等，§26.23 落地末尾）。改成 **rot 0 / 180：引脚排朝南北**，16 根脚沿 9 mm 宽的边出线： + # 北带 y 70.23~75.26（5 mm，C604/R609/C605 在 y 73）、南带 y 60.74~62.77（2 mm，够打一排换层孔到顶层）。 + # 底层 rot 0：脚 1~8（K/EDL 输出）在**北**排、9~16（控制/+3V3）在南排；rot 180 反过来。 + # U21 rot 0：K1 去 site1（西北）、EDL_EN2/3 去 site2/3（北），输出朝北顺路；控制脚南排沿 y≈63 东行去 J32。 + # U22 rot 180：K4/K5 去 site4/5（南），输出朝南，从南带换层到顶层跨过 UP 差分；控制脚北排。 + # U21 (116.5,66.5)：焊盘 x 111.56~121.44，离 USB5 竖段线边 111.4 有 0.5（≥0.2）； + # U22 (127.5,66.5)：焊盘 x 122.56~132.44，离 J32.1 盘边 ~133.1 有 0.6；两片焊盘之间 1.1。 + 'U21': (116.5, 66.5, 0), + 'U22': (127.5, 66.5, 180), + 'U33': (193.5, 68.5, 90), + # 去耦 / OE# 上拉都放两片北边那条带（y 72.73~73.27，离芯片上沿 71.25 有 1.5、离 USB3_DP 有 2.0） + 'C604': (117.0, 73.0, 0), + 'C605': (128.0, 73.0, 0), + 'R609': (122.5, 73.0, 0), + 'C739': (199.5, 68.5, 90), } HDR = {'J31': (62.0, 67.5, 0), 'J32': (158.0, 67.5, 0)} HUB_CENTER = (100.0, 68.0) # v1 是 (110, 67)：西移 10 让开 CH2 行 A / CH5 行 B，北移 1 让 C741 离开 CH4 电池槽 @@ -416,9 +541,20 @@ def check(pos): errs.append(u'越框: %s @ (%.1f, %.1f)' % (d, pos[d][0], pos[d][1])) # 同层重叠 + # 侧键触点盘（J41~J60）是 Ø1.5 的圆盘、盘心距最小 1.78 ⇒ 净距 0.28。 + # 包围盒判会把菱形里相邻的两个盘报成重叠（dx 1.30 < 1.50），所以这一组按**圆**判： + # 盘心距 >= POGO_PAD_D + 0.20（DRC 净距）。 + pogo = set() + for n in SITES: + pogo |= set(desig(n)['pogo']) for i in range(len(items)): for j in range(i + 1, len(items)): a, b_ = items[i], items[j] + if a in pogo and b_ in pogo: + dd = math.hypot(pos[a][0] - pos[b_][0], pos[a][1] - pos[b_][1]) + if dd < POGO_PAD_D + 0.20: + errs.append(u'触点盘太近: %s x %s 盘心距 %.2f（要 >= %.2f）' % (a, b_, dd, POGO_PAD_D + 0.20)) + continue shared = set(layers(a, pos[a][3])) & set(layers(b_, pos[b_][3])) for L in sorted(shared): if _overlap(abs_box(a, L), abs_box(b_, L)): @@ -474,6 +610,8 @@ def check(pos): b = abs_box(d, 2) for n in SITES: for hn, (u_, v_) in HOLES.items(): + if hn in SKIP_HOLES: + continue hx, hy, _ = to_board(n, u_, v_) dd = _dist_box_pt(b, hx, hy) if dd < HOLE_KEEP: @@ -641,11 +779,13 @@ return k; def mech_items(): - u"""35 个手机定位孔（NPTH）+ 5 个手机位的丝印外框与标签。""" + u"""手机定位孔（NPTH，7 孔模型减去 SKIP_HOLES ⇒ 30 个）+ 5 个手机位的丝印外框与标签。""" holes, lines, texts = [], [], [] for n in SITES: x0, y0, rho = SITES[n] for hn, (u, v) in HOLES.items(): + if hn in SKIP_HOLES: # 2026-09-07：H5 不打（push_mech 会先删掉板上全部 P*H* 再建） + continue x, y, _ = to_board(n, u, v) holes.append(['P%d%s' % (n, hn), round(x * MIL, 2), round(y * MIL, 2)]) c = [(x0, y0), (x0 + PW, y0), (x0 + PW, y0 + PH), (x0, y0 + PH)] @@ -791,6 +931,7 @@ return out; HEIGHT = { 'J31': 8.5, 'J32': 8.5, # 直插排母本体（C5307344） 'J23': 3.2, 'U31': 1.8, 'U32': 0.9, 'Y1': 1.2, 'U34': 1.6, + 'C737': 1.8, # KEMET A 壳 EIA-3216-18，最大高 1.8（不是 1206 的 1.7） } @@ -850,8 +991,15 @@ if __name__ == '__main__': print(' ', e) if len(errs) > 40: print(u' ...还有 %d 条' % (len(errs) - 40)) - sys.exit(1) - print(u'本地检查通过：无重叠、无越框、没人压槽、顶层只有顶针、底层件避开了螺钉头') + # --force：只下发 --mech / --outline（孔、槽、丝印）时，元件级的报错不该挡路 —— + # 那些是「元件 vs 孔」「元件 vs 元件」，和要写的机械图元本身无关。 + # ⚠️ 但 --push（重摆元件）绝不允许 force，摆错了会连着布线一起烂。 + if '--force' in sys.argv and '--push' not in sys.argv: + print(u'--force：以上按警告处理，继续下发机械图元（元件没动）') + else: + sys.exit(1) + else: + print(u'本地检查通过：无重叠、无越框、没人压槽、顶层只有顶针、底层件避开了螺钉头') if '--layers' in sys.argv: push_layers() if '--clean-copper' in sys.argv: diff --git a/.claude/pcb2_pour.py b/.claude/pcb2_pour.py index be9e4cb..fd29d23 100644 --- a/.claude/pcb2_pour.py +++ b/.claude/pcb2_pour.py @@ -108,7 +108,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' # PCB2-CARRIER +PCB = '942ed1560d81c1e7' # PCB2-CARRIER MIL = 39.3700787401575 L_TOP, L_PWR, L_GND, L_BOT = 1, 15, 16, 2 # ⚠ 载板：Inner1=电源 / Inner2=地 @@ -441,7 +441,9 @@ def main(): r = call(JS_REBUILD) if r.get('err'): sys.exit(u'!! 打不开铺铜管理器: ' + r['err']) - for i in range(60): + # 2026-09-07：正常一次填充 7 块 < 30 s；卡在 0/7 超过 ~90 s 就是客户端卡住了（§9k）， + # 再等到 4 分钟也不会好，早点退出去重载。 + for i in range(22): time.sleep(4) n = call(JS_POLL, timeout=40)['poured'] print(u' 填充 %d / %d' % (n, len(ps))) diff --git a/.claude/pcb2_reload.py b/.claude/pcb2_reload.py index 129118e..8c3daed 100644 --- a/.claude/pcb2_reload.py +++ b/.claude/pcb2_reload.py @@ -1,37 +1,76 @@ -# -*- coding: utf-8 -*- -u"""重载 EasyEDA 客户端页面（skill §9k/§9s）：关对话框 → 删铺铜边框 → 存盘 → reload → 等 windowId 变掉。""" -import json, os, sys, time, urllib.request -HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) -from eda import run, port -JS = u""" -const sleep = ms => new Promise(r => setTimeout(r, ms)); -const nat = b => { const o={bubbles:true,cancelable:true,view:window,button:0}; - for (const t of ['pointerdown','mousedown','pointerup','mouseup','click']) - b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o)); }; -for (const b of document.querySelectorAll('button')) - if ((b.innerText||'').trim()==='取消' && b.offsetParent!==null) { nat(b); await sleep(800); } -await eda.dmt_EditorControl.openDocument('f126ffb29c92f9b2'); -await sleep(1200); -let n = 0; -for (const o of await eda.pcb_PrimitivePour.getAll()) { await eda.pcb_PrimitivePour.delete(o.primitiveId); n++; } -await eda.pcb_Document.save(); -await sleep(1500); -window.onbeforeunload = null; -setTimeout(() => location.reload(true), 300); -return {deletedPours: n}; -""" -def wid(): - try: - with urllib.request.urlopen('http://127.0.0.1:%d/health' % port(), timeout=3) as r: - return json.loads(r.read()).get('activeWindowId') - except Exception: - return None -w0 = wid() -r = run(JS, timeout=60) -print(u'重载前 windowId %s，删铺铜边框 %s' % (w0, (r.get('result') or {}).get('deletedPours'))) -for i in range(30): - time.sleep(5) - w = wid() - if w and w != w0: - print(u'已重载，新 windowId %s（%d s）' % (w, (i + 1) * 5)); time.sleep(10); sys.exit(0) -sys.exit(u'!! 150 s 内 windowId 没变，重载没成功') +# -*- coding: utf-8 -*- +u"""重载 EasyEDA 客户端页面（skill §9k/§9s）：关对话框 → 删铺铜边框 → 存盘 → reload → 等 windowId 变掉。""" +import json, os, sys, time, urllib.request +HERE = os.path.dirname(os.path.abspath(__file__)); sys.path.insert(0, HERE) +from eda import run, port +JS = u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const nat = b => { const o={bubbles:true,cancelable:true,view:window,button:0}; + for (const t of ['pointerdown','mousedown','pointerup','mouseup','click']) + b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o)); }; +for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()==='取消' && b.offsetParent!==null) { nat(b); await sleep(800); } +await eda.dmt_EditorControl.openDocument('942ed1560d81c1e7'); +await sleep(1200); +let n = 0; +for (const o of await eda.pcb_PrimitivePour.getAll()) { await eda.pcb_PrimitivePour.delete(o.primitiveId); n++; } +await eda.pcb_Document.save(); +await sleep(1500); +window.onbeforeunload = null; +setTimeout(() => location.reload(true), 300); +return {deletedPours: n}; +""" +def wid(): + try: + with urllib.request.urlopen('http://127.0.0.1:%d/health' % port(), timeout=3) as r: + return json.loads(r.read()).get('activeWindowId') + except Exception: + return None +w0 = wid() +r = run(JS, timeout=60) +print(u'重载前 windowId %s，删铺铜边框 %s' % (w0, (r.get('result') or {}).get('deletedPours'))) +COUNT_JS = u""" +await eda.dmt_EditorControl.openDocument('942ed1560d81c1e7'); +await new Promise(r => setTimeout(r, 9000)); +let nc=0, nl=0, nv=0, npad=0; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) nc++; +for (const l of await eda.pcb_PrimitiveLine.getAll()) nl++; +for (const v of await eda.pcb_PrimitiveVia.getAll()) nv++; +for (const p of await eda.pcb_PrimitivePad.getAll()) npad++; +return {doc: (await eda.dmt_Pcb.getCurrentPcbInfo() || {}).name, nc, nl, nv, npad}; +""" + + +def assert_alive(): + u"""⚠⚠ 重载之后**必须**先数一遍图元，确认桥接和文档真的接上了再往下走。 + + 2026-09-07 就是漏了这一步把载板弄丢的：重载回来后铜层读回全 0 + （skill §9ae 那个陈旧上下文），而紧接着跑的 `pcb2_pour.py --push` + 又在那个状态下调了一次 `save()` —— 把“空”写回了文档， + 301 件的下板没事、223 件的载板只剩下丝印和板框，只能走工程历史恢复。 + + “重载成功”的判据不是 windowId 变了，是**图元数不为零**。 + 不过关、绝不允许后面任何一步 save()。 + """ + r = run(COUNT_JS, timeout=120) + if not r.get('success'): + sys.exit(u'!! 重载后数图元失败，**不要再跑任何会 save() 的脚本**: %s' + % json.dumps(r, ensure_ascii=False)[:400]) + d = r['result'] + print(u'重载后回查：%s 元件 %s / 导线 %s / 过孔 %s / 焊盘 %s' + % (d.get('doc'), d.get('nc'), d.get('nl'), d.get('nv'), d.get('npad'))) + if not d.get('nc') or not d.get('nl') or not d.get('npad'): + sys.exit(u'!! 铜层读回 0 —— 桥接与文档失同步（skill §9ae）。\n' + u' **立刻停手，不要 save()，不要跑 pcb2_pour.py** —— 那一步会把空写回去。\n' + u' 先 API Gateway → 重新连接，不行就重启客户端，再跑一次本脚本确认数字回来了。') + + +for i in range(30): + time.sleep(5) + w = wid() + if w and w != w0: + print(u'已重载，新 windowId %s（%d s）' % (w, (i + 1) * 5)) + time.sleep(10) + assert_alive() + sys.exit(0) +sys.exit(u'!! 150 s 内 windowId 没变，重载没成功') diff --git a/.claude/pcb2_route_diff.py b/.claude/pcb2_route_diff.py index fa1e11f..43baa39 100644 --- a/.claude/pcb2_route_diff.py +++ b/.claude/pcb2_route_diff.py @@ -40,7 +40,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' +PCB = '942ed1560d81c1e7' SNAP = os.path.join(HERE, '_pcb2_snap_prerouting.json') # 11 对差分 = 22 个网络（和 pcb2_rules.PAIRS 同源，这里独立列一遍并断言一致） diff --git a/.claude/pcb2_route_dp.py b/.claude/pcb2_route_dp.py index 6bbe102..419b001 100644 --- a/.claude/pcb2_route_dp.py +++ b/.claude/pcb2_route_dp.py @@ -46,7 +46,7 @@ from eda import run from pcb2_clear import half, deg from pcb2_place import SITES, to_board -PCB = 'f126ffb29c92f9b2' +PCB = '942ed1560d81c1e7' MIL = 39.3700787401575 GEOM = os.path.join(HERE, '_pcb2_route_geom.json') @@ -73,10 +73,15 @@ PAIR_OF['UP_DP'] = 'UP_DM' PAIR_OF['UP_DM'] = 'UP_DP' +KSEP = chr(0) + + def netof(key): u"""路径的 key -> 网络名。`NET#2` 这样的后缀表示**同一个网络的第二条支路** （J23 的 A6↔B6 / A7↔B7 短接线就是这么加的），下发时按 `NET` 建线。""" - return key.split('#')[0] + # ⚠️ 分隔符不能用 '#'：载板上有 `KEY_OE#`（2026-09-06 595 上载板之后），按 '#' 拆会把它拆成 + # `KEY_OE`，校核时和自己的焊盘当成异网（下板 §26.19 踩过同一条）。用 chr(0)。 + return key.split(KSEP)[0] # ── 站内坐标（u, v）：J7n ↔ U5n 的短差分（v5：全部**底层**，接口边朝板边）──────── @@ -165,6 +170,13 @@ def geom(): lines = [{'id': i, 'net': n or '', 'lay': l, 'x0': a / MIL, 'y0': b / MIL, 'x1': c / MIL, 'y1': e / MIL, 'w': w / MIL} for i, n, l, a, b, c, e, w in d['lines']] + # 2026-09-07：封装自带的非金属化孔（J23 里两个 Ø0.60，`pcb2_npth.py --write` 产出）当成无网络的通孔盘， + # 两个布线器就都会躲开（原来只有 pcb2_vo_vias 读它，`$16N224` 的过孔直接打在孔上，DRC「挖槽区域到过孔 0mil」）。 + npth = os.path.join(HERE, '_pcb2_npth.json') + if os.path.exists(npth): + for cx, cy, r in json.load(open(npth, encoding='utf-8')): + pads.append({'ref': 'NPTH', 'num': '', 'net': '', 'lay': 12, + 'x': cx, 'y': cy, 'hw': r, 'hh': r}) return pads, vias, lines diff --git a/.claude/pcb2_route_sig.py b/.claude/pcb2_route_sig.py index aab36d6..18a54c2 100644 --- a/.claude/pcb2_route_sig.py +++ b/.claude/pcb2_route_sig.py @@ -1,1577 +1,2009 @@ -# -*- coding: utf-8 -*- -u"""载板电源 + 杂散信号布线：**栅格迷宫布线器**（`pcb2_route_dp.py` 的姊妹件）。 - - /c/Python314/python .claude/pcb2_route_sig.py # 全部算 + 本地校核，不下发 - /c/Python314/python .claude/pcb2_route_sig.py --net +5V # 只算这几个网络（可多个） - /c/Python314/python .claude/pcb2_route_sig.py --push # 下发（只删本脚本负责的网络） - /c/Python314/python .claude/pcb2_route_sig.py --plot out.png # 画一张自己算的图 - -## 为什么这里用布线器，差分对却是手写坐标 - -差分对只有 11 对，但每一对都要管耦合、参考面、偏斜、换层窗口 —— 是**几何设计**， -写死坐标才说得清理由。剩下这 60 来个网络是另一回事：三百多个端点、 -大部分是「从 A 走到 B、别撞上东西」，逐条手写既慢又容易漏。 -所以这里搭一个**能被同一套 `check()` 验的**布线器：路径怎么来的不重要， -下发前一律过 `pcb2_route_dp.check()`（和差分对同一份净距判据）。 - -## 障碍模型（三条都实测过，别改成"看着差不多"的写法） - -1. **栅格 0.1 mm，量化误差按最坏算**。障碍按"格心落在铜里"栅格化， - 再做欧氏距离变换（`scipy.ndimage.distance_transform_edt`）。 - 真实铜边最多比"最近的被标记格心"再近 `grid·√2/2 = 0.0708 mm`， - 所以判据一律是 `edt >= 净距 + 半线宽 + QERR`，**QERR 不许省**。 -2. **本轮自己画的线立刻进障碍表**。网络是一个一个布的， - 后布的必须看得见先布的 —— 否则本地校核会在最后一起爆。 -3. **通孔焊盘（layer 12）两层都算障碍**，过孔也是。板框按 220×135 R5 内缩 1 mm。 - -## BM24 的出线（`STUB`）不交给布线器 - -`J7n` 是 0.35 mm 间距，相邻焊盘净距只有 0.17 mm —— 0.1 mm 的栅格根本分辨不出来， -而且出线宽度要在 0.11 / 0.20 / 0.28 三档之间切换（算式见 `pcb2_route_dp.W_ARR`）。 -所以这一小段**手写**：前排一律往南直出、后排一律往北直出（§25.8 的硬约束）， -出了阵列再让布线器接手。GND 脚另外在阵列外并成一条梳子、共用过孔。 -""" -import io -import json -import math -import os -import sys -import time - -import numpy as np -from scipy import ndimage - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -from pcb2_route_dp import (geom, check, expand, netof, push, MIL, PCB, - L_TOP, L_BOT, CLR, VIA_D, VIA_H, seg_rect, seg_pt, seg_seg, - chamfer_routes, sharp_corners) -from pcb2_place import SITES, to_board, BW, BH, PW, PH - -GRID = 0.1 # 栅格步长 mm -QERR = GRID * math.sqrt(2) / 2 # 栅格量化误差上界 0.0708 mm，判据里必须加上 -EDGE = 1.0 # 铜离板边的最小距离 -CORNER_R = 5.0 -VIA_R = VIA_D / 2.0 -HOLE_CLR = 0.30 # 钻孔到钻孔（规则 otherClearance.hole2Hole），**不分网络** -VIA_COST = 2.5 # 换一次层折算成多少 mm 路程（压住"没事就打孔"） -TURN_COST = 0.30 # 拐一次弯折算成多少 mm（换来长直段，少几百条碎线） -BBOX_PAD = 10.0 # 每次连线的搜索窗口比两端包围盒大多少 -ASTAR_W = 1.3 # 加权 A*：h 乘这个数。放弃严格最优换速度 -MAX_CELLS = 1200000 # 单层格数超过这个才把栅格放粗一档（只有跨半块板的网络会碰到） - -W_ARR = 0.11 # 还在 BM24 焊盘阵列里那一段 -W_ESC = 0.20 # 刚出阵列 -W_SIG = 0.20 # 一般信号。**不是 0.25** —— Hub 的卫星圈是 1.2 mm 网格上的 - # 0402，缝只有 1.2 − 0.541 = 0.659 mm， - # 0.25 的线要 2×(0.20+0.125) = 0.65，量化余量一进去就过不去； - # 0.20 要 0.60，留 0.06 的余量，实测这一档才布得通。 -# XTAL1/2 必须 0.20：Hub 南侧竖井只有 2.16 mm，要并排过 4 根 -# （XTAL ×2 + UP_DP/DM ×2）。0.25 的话 0.2 净距下正好塞不进去 —— 实测布不通。 -# `+5V` 0.60（不是 0.80）：§25.10 重排逐针分配之后它是**10 针分散取电**， -# 每个入口只喂本站的 U2n + C70n、段电流 <= 0.6 A，0.60 mm 外层 1 oz 可载 ~2 A。 -# 0.80 在排母到服务带那条已经站满 EN/POGO 线的走廊里挤不过去（实测五处布不通）。 -WIDTH = {'+5V': 0.60, '+3V3_HUB': 0.35, 'XTAL1': 0.20, 'XTAL2': 0.20} -for _n in range(1, 6): - WIDTH['VBUS%d' % _n] = 0.50 - - -def width_of(net): - return WIDTH.get(net, W_SIG) - - -# ══════════════════ BM24 出线（手写，站内坐标 u/v）══════════════════ -# -# ⚠️ **2026-09-06（第十三轮）整段按 v5 重写。** 老的一版是 v3/v4 的坐标， -# v5 把 J7n 从 rot 180 改成 rot 0 又挪了位置，站内坐标整体差一个仿射映射 -# （`u' = u − 5.00`，`v' = 32.00 − v`，v 轴是**镜像**的）。 -# 照抄映射结果也不行 —— v 一镜像，「前排南侧那条缝」跑到了北侧， -# 而北侧现在站着 R76n/R77n；净距必须拿 v5 的实际障碍重算。下面全部是实测值。 -# -# 焊盘几何（`fp_bm24.py`，`--dump` 回读逐站核过，五个站完全同构）： -# 后排（奇数脚，**全是 GND**）v = 33.940，u 48.30~56.70 -# 中间两个大脚 v = 35.000，pin51(VBUS) u 46.47 / pin52(GND) u 58.53 -# 前排（偶数脚） v = 36.060，u 48.30~56.70 -# 两排都是 hh = 0.24；信号脚 hw = 0.0902，脚距 0.35 ⇒ 相邻焊盘边到边 0.1696 -J7_BACK_V, J7_MID_V, J7_FRONT_V = 33.940, 35.000, 36.060 -J7_PAD_HH = 0.24 -# 出线换挡的 v：离焊盘外沿 0.35，0.20 的线到相邻脚的焊盘角还有余量 -J7_FRONT_ESC = J7_FRONT_V + J7_PAD_HH + 0.35 # 36.65，往**外**（+v） -J7_BACK_ESC = J7_BACK_V - J7_PAD_HH - 0.35 # 33.35，往**外**（−v） -J7_FRONT_IN = J7_FRONT_V - J7_PAD_HH - 0.35 # 35.47，前排往**内**（进中央通道） - -# GND 脚的 u（`--check` 会逐站断言） -J7_GND_FRONT = [48.30, 49.35, 50.05, 50.75, 52.15] # pin 2/8/12/16/24 -J7_GND_BACK = [48.30, 51.45, 52.15, 53.20, 54.60, 55.30, 56.35] # pin 1/19/23/29/37/41/47 -J7_GND_BIG = 58.53 # pin 52，0.49×0.76 大焊盘 -J7_THERM_U, J7_CC1_U = 50.40, 51.80 # pin 14 口温 / pin 22 CC1 - -# ══ v5 的车道分配（和 v4 换了个方向，理由在下面）══ -# -# ┌ 前排外侧 v > 36.30 ── **只给 THERM / CC1**（R76n/R77n 就在正北 v 38.0） -# │ 中央通道 v ∈ [34.18, 35.82]，净高 1.64 ── **前排 5 个 GND 的梳子** -# └ 后排外侧 v < 33.70 ── **后排 7 个 GND 的梳子**，一路空到 v 26，最宽敞 -# -# 为什么和 v4 相反：v5 的**后排 25 个脚全是 GND**（没有信号脚要往外挤）， -# 而 THERM(pin14)/CC1(pin22) 都在前排、目标 R76n/R77n 也在前排外侧 —— -# 让它们各走各的最短路，中央通道就整条空出来给前排 GND，不再有 -# v4 那个「东行车道被竖着穿过通道的 GND 线切断」的死结。 -# -# 中央通道梳子 v = 35.00（正中）：到两排焊盘内沿各 0.82 -# 0.30 的线：0.82 − 0.15 = 0.67 ✔ 过孔：0.82 − 0.305 = 0.515 ✔（要 0.50） -# ⚠️ 梳子只走到 u 52.15（最东那个前排 GND 脚），离 pin52 焊盘西沿 58.285 还有 6 mm， -# 所以通道里这条梳子和 pin51/pin52 两个大脚互不相干。 -J7_MID_COMB = J7_MID_V # 35.00 -J7_MID_VIA_U = [48.30, 49.35, 50.75, 52.15] # 相邻间距 1.05/1.40/1.40 >= 0.81 ✔（跳过 50.05） -# -# 后排外侧梳子 v = 33.10：到后排焊盘外沿 33.70 有 0.60 -# 0.30 的线余 0.45 ✔ 过孔余 0.295 ✔（要 0.20；离焊盘 0.60 − 0.305 = 0.295） -# ⚠️ 这一带在**尾插排线车道 `TAIL_LANE` 里**（u 44.6~62.6 / v −1.2~36.3）。 -# 车道的约束是「不放元件」，走线和过孔是允许的（排线平贴着盖过去）。 -J7_BACK_COMB = 33.10 -J7_BACK_VIA_U = [48.30, 52.15, 53.20, 54.60, 56.35] # 间距 3.85/1.05/1.40/1.75 >= 0.81 ✔ -# -# pin52（GND 大焊盘，u 58.53 / v 35.00）：往**东**平着出去打孔， -# 离 J7n 最东那列焊盘 (u 56.79) 2.8、离手机定位柱 PnH3 (u 61.90, v 33.70, Ø2.5) 1.05 ✔ -J7_PIN52_VIA_U = 59.60 - -W_COMB = 0.30 -W_LANE = 0.20 - -# ── THERM / CC1：都往前排外侧出，THERM 走顶层跳过 CC1 ── -# -# 两个脚一个要往东（THERM → R77n.1 u 54.367）、一个要往北（CC1 → R76n.1 u 51.800）， -# **在 u ≈ 51.8 必然交叉**，同层无解。CC1 是最短的那根，让它全程底层直上； -# THERM 打两个孔从顶层跨过去。 -# 西孔 (50.95, 37.20)：离 `*_DPJ` 的换层孔 (50.00, 37.00) **0.97 ≥ 0.81**（孔到孔）； -# 离 J7n.16/18 焊盘 0.86；离 R76n.1 焊盘框 0.78 ✔ -# 东孔 (54.37, 37.20)：离 J7n.38 焊盘 0.90；R77n.1 是同网，不设限 ✔ -# 顶层那一段 v = 37.20：顶层在 J7n 这一带**一根线都没有**（`*_DPJ` 的顶层小跳线在 u ≤ 50.0） -# R76n 的中心特意取 52.233，好让 pin1 正落在 u 51.800 = J7n.22 正北 ⇒ CC1 是一根直线。 -# ⚠️ THERM 出阵列后**第一次拐弯的 v 只有 0.053 mm 的窗口**，而且那一段必须一直保持 0.11： -# 往下：离前排焊盘外沿 36.30 要 w/2 + 0.20 ⇒ v >= 36.555 -# 往上：离 `*_DPJ` 的换层孔 (50.00, 37.00) 要 0.305 + w/2 + 0.20 = 0.560， -# 而它在 u 上只差 0.40 ⇒ |v − 37.00| >= 0.392 ⇒ v <= 36.608 -# 取窗口正中 36.58（上下各余 0.027）。**换成 0.15 的线窗口只剩 0.005，0.20 直接无解** —— -# 2026-09-06 第一版写 0.20 / 拐点 36.65，五个站一起报「线-过孔 净距 0.127」。 -J7_THERM_TURN_V = 36.58 -J7_THERM_VIA = [(50.80, 37.30), (54.367, 37.30)] -J7_THERM_KINK = (50.80, 36.98) # 45° 斜段的终点，之后竖着上到换层孔 -J7_THERM_LANE_V = 37.30 -J7_R76_PIN1_U, J7_R77_PIN1_U = 51.800, 54.367 -J7_R_PAD_V = 38.000 # R76n/R77n 焊盘中心 v（`--check` 会核） -J7_R_ENTER_V = 37.90 # 进焊盘的落点（焊盘 v 37.730~38.270） - - -def _stub(u, v_pad, v_esc, w_out=W_ESC): - u"""BM24 一个脚的直出段（站内坐标）：焊盘 -> 阵列外。""" - return [(u, v_pad, L_TOP, W_ARR), (u, v_esc, L_TOP, w_out)] - - -def bm24_stub(n, u, v_pad, v_esc, w_out=W_ESC): - u"""同上，映射到第 n 站的板坐标。""" - out = [] - for u_, v_, lay, ww in _stub(u, v_pad, v_esc, w_out): - bx, by, _ = to_board(n, u_, v_, 0) - out.append((round(bx, 3), round(by, 3), lay, ww)) - return out - - -# ══════════════════ 板框 ══════════════════ -_CORNERS = ((CORNER_R, CORNER_R), (BW - CORNER_R, CORNER_R), - (CORNER_R, BH - CORNER_R), (BW - CORNER_R, BH - CORNER_R)) - - -def board_mask(XX, YY, m=EDGE): - u"""格心在板内（含 R5 圆角、内缩 m）的布尔数组。""" - ok = (XX >= m) & (XX <= BW - m) & (YY >= m) & (YY <= BH - m) - for cx, cy in _CORNERS: - sx = 1.0 if cx < BW / 2 else -1.0 - sy = 1.0 if cy < BH / 2 else -1.0 - inc = ((XX - cx) * sx < 0) & ((YY - cy) * sy < 0) - ok &= ~(inc & (np.hypot(XX - cx, YY - cy) > CORNER_R - m)) - return ok - - -# ══════════════════ 形状（障碍 / 本网铜都用这一套）══════════════════ -def sh_rect(x, y, hw, hh, layers): - return ('rect', x, y, hw, hh, layers) - - -def sh_via(x, y, r=VIA_R): - return ('via', x, y, r, 0, (L_TOP, L_BOT)) - - -def sh_seg(x0, y0, x1, y1, w, lay): - return ('seg', x0, y0, x1, y1, w / 2.0, (lay,)) - - -def shapes_of(pads, vias, lines): - u"""把 geom() 的三张表变成障碍表：`[(形状, 网络), ...]`。 - - ⚠️ **网络必须跟着形状走**：布某个网络时它自己的铜不能算障碍， - 否则连焊盘都出不来（第一版就是漏了这条，25 个种子格一个邻居都扩不出去）。 - """ - out = [] - for p in pads: - lay = (L_TOP, L_BOT) if p['lay'] == 12 else (p['lay'],) - out.append((sh_rect(p['x'], p['y'], p['hw'], p['hh'], lay), p['net'])) - for v in vias: - out.append((sh_via(v['x'], v['y'], v['r']), v['net'])) - for l in lines: - out.append((sh_seg(l['x0'], l['y0'], l['x1'], l['y1'], l['w'], l['lay']), l['net'])) - return out - - -# ══════════════════ 栅格场 ══════════════════ -class Field(object): - u"""一个搜索窗口里的两层障碍距离场。 - - `edt[L][j, i]` = 该格心到**最近的异网铜**的距离（mm，含量化误差 QERR）。 - 判据统一是 `edt >= 净距 + 半线宽 + QERR`。 - """ - - #: 搜索窗口外面还要多留一圈**只标障碍、不许走线**的边（mm）。见 __init__ 里的注释。 - RIM = 1.2 - - def __init__(self, obstacles, bbox, skip_net=None, grid=GRID): - x0, y0, x1, y1 = bbox - self.g = grid - self.qerr = grid * math.sqrt(2) / 2 - # ⚠️ **窗口边上必须留一圈墙。** 障碍是裁到窗口里再栅格化的， - # 完全落在窗口外的铜一格都不标 —— 于是贴着窗口边走的线看不见它。 - # 2026-09-06 实测：`SCL` 的搜索窗口从 x=44.02 起，J31.6 的焊盘框 - # (42.10~43.80) 整个在窗外，布线器就在 (44.10, 67.40) 打了个孔， - # 离那个焊盘只有 0.134 —— 栅格判据全过，`check()` 才报出来。 - # 做法：数组往外扩 RIM，障碍照标，**再把外面这一圈整体标成占用**。 - # 可走的区域和原来一模一样，但现在看得见窗外 RIM 以内的铜。 - rim = self.RIM - x0 -= rim; y0 -= rim; x1 += rim; y1 += rim - self.x0 = math.floor(x0 / grid) * grid - self.y0 = math.floor(y0 / grid) * grid - self.nx = int(round((x1 - self.x0) / grid)) + 2 - self.ny = int(round((y1 - self.y0) / grid)) + 2 - # ⚠️ **层集合不能写死 (L_TOP, L_BOT)**。下板从 2026-09-06 起在 **Inner2(16)** - # 上有真走线了（`pcb1_i2c_l3.py` 的 I²C 干线），障碍表里就会出现 layer 16 —— - # 写死两层的话这里直接 `KeyError: 16`；就算滤掉，**新过孔也不会对内层那些线 - # 做净距判断**（`viafree` 是 min(edt[TOP], edt[BOT])），孔会直接压在内层干线上。 - # 这里按障碍表里真正出现过的层建数组；只有 1/2 层时行为和以前一模一样。 - self.lays = sorted(set([L_TOP, L_BOT]) - | set(L for s, _n in obstacles for L in s[-1])) - occ = {L: np.zeros((self.ny, self.nx), bool) for L in self.lays} - # ⚠️ 障碍要**先胀 QERR 再栅格化**，见 `_mark` 的注释。 - for s, net in obstacles: - if net == skip_net: - continue - for L in s[-1]: - self._mark(occ[L], s, grow=self.qerr) - # 板框外一律不许有铜 - xs = self.x0 + np.arange(self.nx) * grid - ys = self.y0 + np.arange(self.ny) * grid - XX, YY = np.meshgrid(xs, ys) - out = ~board_mask(XX, YY) - # 外圈那一圈墙（障碍已经标完了，这里只是禁止走线） - nb = max(1, int(round(rim / grid))) - wall = np.zeros((self.ny, self.nx), bool) - wall[:nb, :] = True; wall[-nb:, :] = True - wall[:, :nb] = True; wall[:, -nb:] = True - out |= wall - for L in self.lays: - occ[L] |= out - self.occ = occ - self.edt = {L: ndimage.distance_transform_edt(~occ[L], sampling=grid).astype(np.float32) - for L in self.lays} - # 过孔是通孔 ⇒ **每一层**都要让开（含 Inner2 上的真走线） - self.viafree = np.minimum.reduce([self.edt[L] for L in self.lays]) - # ⚠️ **钻孔间距不分网络**。铜可以重叠，孔不行 —— 规则 otherClearance.hole2Hole = 0.30。 - # `viafree` 是「到**异网**铜的距离」，同网的过孔在它眼里根本不存在， - # 于是布线器会紧挨着 `pcb2_dp_long` 已经打好的孔再打一个： - # 2026-09-06 实测 (92.500, 70.000) 与 (92.400, 70.500) 中心只隔 0.510， - # DRC 报「钻孔 到 钻孔 8.1mil，应 >= 11.8mil」，而净距校核一声不吭。 - occh = np.zeros((self.ny, self.nx), bool) - for s, _net in obstacles: - if s[0] == 'via': - self._mark(occh, ('via', s[1], s[2], VIA_H / 2.0, 0, s[5]), grow=self.qerr) - occh |= out - self.holefree = ndimage.distance_transform_edt( - ~occh, sampling=grid).astype(np.float32) - - # ── 栅格化 ── - def _idx(self, x, y): - return (int(round((x - self.x0) / self.g)), int(round((y - self.y0) / self.g))) - - def _win(self, xa, xb, ya, yb): - i0 = max(0, int(math.ceil((xa - self.x0) / self.g))) - i1 = min(self.nx - 1, int(math.floor((xb - self.x0) / self.g))) - j0 = max(0, int(math.ceil((ya - self.y0) / self.g))) - j1 = min(self.ny - 1, int(math.floor((yb - self.y0) / self.g))) - return i0, i1, j0, j1 - - def _mark(self, mask, s, grow=0.0): - u"""把一个形状打进布尔栅格。 - - ⚠️ **`grow` 不是保险丝，是判据的一部分。** 只标"格心落在铜里"的格时， - 铜的边界到最近的被标记格心可以差到将近一整格（实测：一个 Ø0.61 的过孔 - 边缘在 x=52.781，最近的格心在 52.7，差 0.081 > √2/2·0.1）， - 于是 `edt` 会**高估** 0.08 mm，净距校核就在下发前一刻才炸。 - 把障碍先胀 `QERR = g·√2/2` 再栅格化，任何铜边界点周围 - 半径 QERR 内一定有被标记的格 ⇒ `真实净距 >= edt − QERR` 严格成立， - 判据 `edt >= 净距 + 半线宽 + QERR` 才真的是充分条件。 - """ - k = s[0] - if k == 'rect': - _, x, y, hw, hh, _ = s - hw, hh = hw + grow, hh + grow - i0, i1, j0, j1 = self._win(x - hw, x + hw, y - hh, y + hh) - if i0 <= i1 and j0 <= j1: - mask[j0:j1 + 1, i0:i1 + 1] = True - return - if k == 'via': - _, x, y, r, _, _ = s - r = r + grow - i0, i1, j0, j1 = self._win(x - r, x + r, y - r, y + r) - if i0 > i1 or j0 > j1: - return - xs = self.x0 + np.arange(i0, i1 + 1) * self.g - ys = self.y0 + np.arange(j0, j1 + 1) * self.g - XX, YY = np.meshgrid(xs, ys) - mask[j0:j1 + 1, i0:i1 + 1] |= ((XX - x) ** 2 + (YY - y) ** 2) <= r * r - return - _, xa, ya, xb, yb, h, _ = s - h = h + grow - i0, i1, j0, j1 = self._win(min(xa, xb) - h, max(xa, xb) + h, - min(ya, yb) - h, max(ya, yb) + h) - if i0 > i1 or j0 > j1: - return - xs = self.x0 + np.arange(i0, i1 + 1) * self.g - ys = self.y0 + np.arange(j0, j1 + 1) * self.g - XX, YY = np.meshgrid(xs, ys) - dx, dy = xb - xa, yb - ya - L2 = dx * dx + dy * dy - if L2 < 1e-12: - d2 = (XX - xa) ** 2 + (YY - ya) ** 2 - else: - t = np.clip(((XX - xa) * dx + (YY - ya) * dy) / L2, 0.0, 1.0) - d2 = (XX - (xa + t * dx)) ** 2 + (YY - (ya + t * dy)) ** 2 - mask[j0:j1 + 1, i0:i1 + 1] |= d2 <= h * h - - def mask_of(self, shapes): - m = {L: np.zeros((self.ny, self.nx), bool) for L in self.lays} - for s in shapes: - for L in s[-1]: - self._mark(m[L], s) - return m - - # ── 判据 ── - # `relax` = **本网自己的焊盘**所占的格。焊盘里本来就有铜， - # 线从焊盘中心出来的那一小段落在焊盘内部，不该拿净距去卡它 - # （0402 的两个焊盘只隔 0.5 mm，卡下去等于每个器件都出不了线）。 - # 只放宽焊盘，不放宽本网的**导线** —— 导线本身是合法的，它所在的格 edt 也够。 - def set_relax(self, shapes): - self.relax = self.mask_of(shapes) - - def free(self, lay, w): - f = self.edt[lay] >= CLR + w / 2.0 + self.qerr - if getattr(self, 'relax', None) is not None: - f = f | self.relax[lay] - return f - - def via_ok(self): - return ((self.viafree >= CLR + VIA_R + self.qerr) - & (self.holefree >= VIA_H / 2.0 + HOLE_CLR + self.qerr)) - - def clear_seg(self, x0, y0, x1, y1, lay, w): - u"""一段任意角度的线是否安全（沿线采样，EDT 是 1-Lipschitz 所以可加采样余量）。""" - need = CLR + w / 2.0 + self.qerr - L = math.hypot(x1 - x0, y1 - y0) - n = max(2, int(L / (self.g / 2.0)) + 1) - step = L / (n - 1) if n > 1 else 0.0 - need += step / 2.0 - rl = getattr(self, 'relax', None) - for k in range(n): - t = k / float(n - 1) if n > 1 else 0.0 - i, j = self._idx(x0 + t * (x1 - x0), y0 + t * (y1 - y0)) - if not (0 <= i < self.nx and 0 <= j < self.ny): - return False - if self.edt[lay][j, i] < need and not (rl is not None and rl[lay][j, i]): - return False - return True - - -# ══════════════════ A* ══════════════════ -DIRS = [(1, 0), (1, 1), (0, 1), (-1, 1), (-1, 0), (-1, -1), (0, -1), (1, -1)] - - -def _edges(ok, dx, dy, nx, ny, base): - u"""某一层上、沿 (dx, dy) 这个方向的所有合法走步 -> (起点索引, 终点索引)。 - - 斜着走要**额外**要求两个正交邻格也是通的 —— 否则线会从两个障碍的夹角里"钻"过去。 - """ - xs0, xs1 = max(0, -dx), nx - max(0, dx) - ys0, ys1 = max(0, -dy), ny - max(0, dy) - if xs1 <= xs0 or ys1 <= ys0: - e = np.empty(0, np.int64) - return e, e - m = ok[ys0:ys1, xs0:xs1] & ok[ys0 + dy:ys1 + dy, xs0 + dx:xs1 + dx] - if dx and dy: - m = m & ok[ys0:ys1, xs0 + dx:xs1 + dx] & ok[ys0 + dy:ys1 + dy, xs0:xs1] - jj, ii = np.nonzero(m) - jj = jj.astype(np.int64) + ys0 - ii = ii.astype(np.int64) + xs0 - return base + jj * nx + ii, base + (jj + dy) * nx + (ii + dx) - - -def route_grid(f, src, tgt, w): - u"""多源多汇最短路。`src`/`tgt` 是 {层: 布尔数组}。返回 [(i, j, 层), ...] 或 None。 - - 代价 = 路程(mm) + 每次换层 `VIA_COST`。 - - ## 为什么是 scipy 的 Dijkstra，不是自己写的 A* - - 第一版是纯 Python 的加权 A*（还带拐弯惩罚）。**跨半块板的网络跑不动** —— - `VBUS_UP`（J23 → Hub，95 mm）在 0.1 mm 栅格上是 140 万个节点， - 两分钟没跑完，放粗到 0.2 mm 又因为净距判据跟着变严而布不通。 - 改成把整个栅格建成稀疏图交给 `scipy.sparse.csgraph.dijkstra`（C 实现、多源、 - 带前驱），同一个网络降到秒级。 - - 代价是**丢了拐弯惩罚**（Dijkstra 表达不了"到达方向"）， - 最短路会退化成楼梯。所以 `polish()` 必须做「最远可视 L 形合并」把楼梯收回来 —— - 这两件事是配套的，只改一半会得到几百条碎线。 - """ - from scipy.sparse import coo_matrix - from scipy.sparse.csgraph import dijkstra - - nx, ny, g = f.nx, f.ny, f.g - LAY = [L_TOP, L_BOT] - ok = [f.free(L, w) for L in LAY] - N = nx * ny - rows, cols, vals = [], [], [] - for li in (0, 1): - for dx, dy in ((1, 0), (0, 1), (1, 1), (1, -1)): - fr, to = _edges(ok[li], dx, dy, nx, ny, li * N) - if len(fr): - rows.append(fr) - cols.append(to) - vals.append(np.full(len(fr), g * (math.sqrt(2) if dx and dy else 1.0), - np.float32)) - vm = f.via_ok() & ok[0] & ok[1] - jj, ii = np.nonzero(vm) - if len(jj): - idx = jj.astype(np.int64) * nx + ii.astype(np.int64) - rows.append(idx) - cols.append(idx + N) - vals.append(np.full(len(idx), VIA_COST, np.float32)) - if not rows: - return None - G = coo_matrix((np.concatenate(vals), - (np.concatenate(rows), np.concatenate(cols))), - shape=(2 * N, 2 * N)).tocsr() - - def flat(mask): - out = [] - for li in (0, 1): - jj, ii = np.nonzero(mask[LAY[li]] & ok[li]) - out.append(jj.astype(np.int64) * nx + ii.astype(np.int64) + li * N) - return np.concatenate(out) - - si, ti = flat(src), flat(tgt) - if not len(si) or not len(ti): - return None - D, pred, _srcs = dijkstra(G, directed=False, indices=si, min_only=True, - return_predecessors=True) - d = D[ti] - k = int(np.argmin(d)) - if not np.isfinite(d[k]): - return None - out = [] - idx = int(ti[k]) - seen = set() - while idx >= 0 and idx not in seen: - seen.add(idx) - li, r = divmod(idx, N) - j, i = divmod(r, nx) - out.append((i, j, LAY[li])) - idx = int(pred[idx]) - out.reverse() - return out - - -# ══════════════════ 路径整形 ══════════════════ -def _runs(cells): - u"""8 邻域格路 -> 顶点表（同层的共线段合并；换层处断开）。""" - pts = [cells[0]] - for k in range(1, len(cells) - 1): - i0, j0, l0 = cells[k - 1] - i1, j1, l1 = cells[k] - i2, j2, l2 = cells[k + 1] - if l0 != l1 or l1 != l2: - pts.append(cells[k]) - continue - if (i1 - i0, j1 - j0) != (i2 - i1, j2 - j1): - pts.append(cells[k]) - pts.append(cells[-1]) - return pts - - -def _l_shapes(a, b): - u"""A->B 的 45°/90° 两段折线（两种拐法）；本来就是 8 方向的直接返回一段。""" - (x0, y0), (x1, y1) = a, b - dx, dy = x1 - x0, y1 - y0 - if abs(dx) < 1e-9 or abs(dy) < 1e-9 or abs(abs(dx) - abs(dy)) < 1e-9: - return [[a, b]] - m = min(abs(dx), abs(dy)) - sx = math.copysign(1.0, dx) - sy = math.copysign(1.0, dy) - return [[a, (x0 + sx * m, y0 + sy * m), b], # 先斜后正 - [a, (x1 - sx * m, y1 - sy * m), b]] # 先正后斜 - - -def polish(f, pts, w): - u"""顶点表 -> 少而长的 45°/90° 段。逐层做，换层点原样保留。""" - out = [] - seg_start = 0 - for k in range(len(pts)): - last = (k == len(pts) - 1) - if not last and pts[k + 1][2] == pts[k][2]: - continue - chunk = pts[seg_start:k + 1] - lay = chunk[0][2] - xy = [(f.x0 + i * f.g, f.y0 + j * f.g) for i, j, _ in chunk] - out.append((lay, _polish_one(f, xy, lay, w))) - seg_start = k + 1 - return out - - -def _polish_one(f, xy, lay, w): - if len(xy) <= 2: - return xy - def try_j(i, j): - for cand in _l_shapes(xy[i], xy[j]): - if all(f.clear_seg(a[0], a[1], b[0], b[1], lay, w) - for a, b in zip(cand, cand[1:])): - return cand - return None - - res = [xy[0]] - i = 0 - n = len(xy) - while i < n - 1: - # 先指数外推找到"最后一个还通的 j"的量级，再二分收敛。 - # 逐个从远往近试是 O(n²) 次几何校核，长线（上千个格）会卡住。 - lo, best = i + 1, try_j(i, i + 1) - step = 1 - while lo + step <= n - 1: - c = try_j(i, lo + step) - if c is None: - break - lo, best = lo + step, c - step *= 2 - hi = min(n - 1, lo + step) - while lo + 1 < hi: - mid = (lo + hi) // 2 - c = try_j(i, mid) - if c is None: - hi = mid - else: - lo, best = mid, c - if best is None: - res.append(xy[i + 1]) - i += 1 - continue - res.extend(best[1:]) - i = lo - # 去掉共线冗余点 - out = [res[0]] - for k in range(1, len(res) - 1): - ax, ay = out[-1] - bx, by = res[k] - cx, cy = res[k + 1] - if abs((bx - ax) * (cy - by) - (by - ay) * (cx - bx)) > 1e-9: - out.append(res[k]) - out.append(res[-1]) - return out - - -# ══════════════════ 网络布线 ══════════════════ -class Comp(object): - u"""一个网络里已经连通的一坨铜。 - - `center` 只在"这一坨就是一个焊盘"时非空，值是**焊盘中心**。 - ⚠️ 这一条不是锦上添花：`half()` 给圆焊盘返回的是**外接矩形**， - 路径若停在矩形角上（Ø1.7 的排母脚差 0.32 mm）实际上根本没搭到铜。 - 所以单焊盘的起终点一律钉在圆心，A* 的种子/目标也只取圆心那一格。 - """ - - def __init__(self, shapes, anchor, center=None, layers=None): - self.shapes = list(shapes) - self.anchor = anchor # (x, y) 只用来算"离谁最近" - self.center = center - self.layers = layers - - def merge(self, other, extra): - self.shapes += other.shapes + extra - self.center = None - self.layers = None - - -FINE_PAD = 0.31 # 焊盘短边半长 < 这个数就算"细间距"，出线要先直出 -STUB_EXT = (0.30, 0.20, 0.12) # 直出到焊盘外多少（依次退让） -_CENTROID = {} - - -def _centroid(ref, pads_all): - if ref not in _CENTROID: - ps = [p for p in pads_all if p['ref'] == ref] - _CENTROID[ref] = (sum(p['x'] for p in ps) / len(ps), - sum(p['y'] for p in ps) / len(ps)) if ps else None - return _CENTROID[ref] - - -def clear_exact(x0, y0, x1, y1, lay, w, net, obstacles): - u"""一段线到**异网铜**的真实最小净距（不走栅格，逐个形状精确算）。""" - h = w / 2.0 - best = 1e9 - a, b = (x0, y0), (x1, y1) - for s, n in obstacles: - if n == net or lay not in s[-1]: - continue - if s[0] == 'rect': - d = seg_rect(a, b, s[1], s[2], s[3], s[4]) - h - elif s[0] == 'via': - d = seg_pt(x0, y0, x1, y1, s[1], s[2]) - s[3] - h - else: - d = seg_seg(a, b, (s[1], s[2]), (s[3], s[4])) - s[5] - h - if d < best: - best = d - return best - - -ELONGATED = 1.3 # 长短边之比超过这个，就认为焊盘"有方向" - - -def entry_stub(q, pads_all, obstacles, net, w, all_cands=False): - u"""细间距焊盘的**直出段**：从焊盘中心直着走出焊盘外一小截，路由器从这一截接手。 - - 不这么做的话最短路会从焊盘的**侧面**或**角上**离开： - QFN(0.5 脚距) 和 0402 的邻脚就在 0.2~0.4 mm 外，一出来就违规。 - 上一版 `XTAL1` 进 U32.61 是这么卡死的（布不通）， - `+3V3_HUB` 进 U32.64 更糟 —— 它从**西侧**横着挤进去，离 U32.63 只剩 0.10 mm。 - - ## 方向怎么定（两条规则，缺一不可） - - 1. **焊盘明显是长条的（长短边 ≥ 1.3）⇒ 沿长轴出**。这是封装设计者的意思： - 长轴指向元件外面。QFN 南边一排是 0.30×0.851，J23 的信号脚是 1.30×0.30。 - 2. **接近方的（0402 焊盘 0.50×0.541、晶振 1.40×1.20）⇒ 沿"背离元件形心"那根轴出**。 - - 只按第 2 条会错得很难看：`J23.A5` 上下各有一个焊盘、左右空着， - 而形心被四个屏蔽脚拉到东边 ⇒ 判成"往南出"，**正好撞在 B8 焊盘上**， - 于是没有出线段，两个 2 mm 远的焊盘反而布不通。 - """ - if q['lay'] == 12 or min(q['hw'], q['hh']) >= FINE_PAD: - return [] if all_cands else None - cen = _centroid(q['ref'], pads_all) - if cen is None: - return [] if all_cands else None - dx, dy = q['x'] - cen[0], q['y'] - cen[1] - if q['hw'] >= q['hh'] * ELONGATED: - axes = ('x', 'y') - elif q['hh'] >= q['hw'] * ELONGATED: - axes = ('y', 'x') - else: - axes = ('x', 'y') if abs(dx) >= abs(dy) else ('y', 'x') - # 候选：主轴背离形心 -> 次轴背离形心 -> 主轴朝向形心（万不得已） - cands = [] - for ax in axes: - d = dx if ax == 'x' else dy - cands.append((ax, 1.0 if d >= 0 else -1.0)) - cands.append((axes[0], -cands[0][1])) - ws = min(w, 2 * min(q['hw'], q['hh'])) - out = [] - for ax, sgn in cands: - for ext in STUB_EXT: - if ax == 'x': - end = (q['x'] + sgn * (q['hw'] + ext), q['y']) - else: - end = (q['x'], q['y'] + sgn * (q['hh'] + ext)) - if clear_exact(q['x'], q['y'], end[0], end[1], q['lay'], ws, net, obstacles) >= CLR: - out.append((end, ws)) - break # 同一个方向只留最长的那一档 - if not out: - return [] if all_cands else None - return out if all_cands else out[0] - - -def plan_stubs(order, pads_all, obstacles, pre_pads): - u"""**先给所有网络的所有焊盘留好出线段，再开始布线。** - - 这一步不是优化，是必需的。第一版是"轮到哪个网络才现画它的出线段"， - 于是先布的网络会把后布的网络**出焊盘的那 0.6 mm 占掉**： - - · `VBUS2` 抄近路斜穿 U25 东侧 ⇒ `+5V` 出 U25.1 只剩 −0.02 mm， - 出线段只好掉头往**西**（钻进器件内部），整条 `+5V` 就此布不通； - · `+3V3_HUB` 从西边竖着切进 U42.5 ⇒ 隔壁 U42.6 的 `EDL_EN2` 出不来， - 而这两个焊盘只隔 0.95 mm。 - - 先把出线段全部落地当障碍，等于给每个焊盘**预留了逃逸通道**， - 这是布线器的常规做法（escape routing 先行）。 - """ - stubs, alts = {}, {} - for net in order: - w = width_of(net) - for q in pads_all: - key = (q['ref'], q['num']) - if q['net'] != net or key in pre_pads: - continue - cand = entry_stub(q, pads_all, obstacles, net, w, all_cands=True) - if not cand: - continue - alts[key] = cand - end, ws = cand[0] - stubs[key] = (end, ws) - # 只**预留**首选方向。备选方向不占位 —— 它们只在首选走不通时才拿出来试， - # 那时候本来就是"能捡到什么算什么"。 - obstacles.append((sh_seg(q['x'], q['y'], end[0], end[1], ws, q['lay']), net)) - return stubs, alts - - -def route_net(net, pads_all, obstacles, w=None, pre=None, verbose=True, - stubs=None, alts=None): - u"""把一个网络布通。返回 [路径, ...]（每条是 `expand()` 认的点表）。 - - `pre` 是手写前置段（BM24 出线 / GND 梳子），它们**先算进本网铜**， - 然后端点参与后面的最小生成树。 - `stubs` 是 `plan_stubs()` 预留好的出线段（已经在障碍表里了，这里只取用）。 - `alts` 是同一个焊盘的**备选出线方向**：首选方向布不通时换一个再试。 - - ⚠️ 为什么需要备选：出线方向是按「背离元件形心」定的，那只是个启发式。 - `R709.1`（VBUS_UP）在 Hub 卫星圈 A/B 两圈之间，背离形心 = **朝东**， - 正好扎进 A/B 圈之间那条 0.268 mm 的死胡同 —— 出线段本身是合法的（只有 0.59 mm 长）， - 所以 `plan_stubs` 挑中了它，然后整个网络就再也接不上这个焊盘。 - 实测：只布这一个网络、整块板别的线都不存在，照样布不通 ⇒ 不是拥挤，是方向选错了。 - """ - w = w or width_of(net) - paths = list(pre or []) - comps = [] - used = set() - for p in pre or []: - shp = [] - for x0, y0, x1, y1, lay, ww in expand(p)[0]: - shp.append(sh_seg(x0, y0, x1, y1, ww, lay)) - for x, y in expand(p)[1]: - shp.append(sh_via(x, y)) - # ⚠️ 手写前置段也必须进障碍表。漏了这一条的后果是**后面的网络看不见它们** —— - # BM24 那五组车道是最先落的铜，`POGO2_PWR` 却从中间穿了过去， - # 而且只有最后一步 `check()` 才报出来（−0.200，实打实压在一起）。 - obstacles.extend((sp, net) for sp in shp) - for q in pads_all: - if q['net'] != net: - continue - if seg_rect((p[0][0], p[0][1]), (p[0][0], p[0][1]), - q['x'], q['y'], q['hw'], q['hh']) < 1e-6: - used.add((q['ref'], q['num'])) - comps.append(Comp(shp, (p[-1][0], p[-1][1]))) - for q in pads_all: - if q['net'] != net or (q['ref'], q['num']) in used: - continue - lay = (L_TOP, L_BOT) if q['lay'] == 12 else (q['lay'],) - rect = sh_rect(q['x'], q['y'], q['hw'], q['hh'], lay) - st = (stubs or {}).get((q['ref'], q['num'])) - if st is None: - comps.append(Comp([rect], (q['x'], q['y']), center=(q['x'], q['y']), layers=lay)) - continue - end, ws = st - paths.append([(round(q['x'], 4), round(q['y'], 4), q['lay'], ws), - (round(end[0], 4), round(end[1], 4), q['lay'], ws)]) - seg = sh_seg(q['x'], q['y'], end[0], end[1], ws, q['lay']) - c = Comp([rect, seg], end, center=end, layers=lay) - c.pad, c.rect, c.stub_i = q, rect, len(paths) - 1 # 换出线方向时要用 - c.stub_alts = [a for a in (alts or {}).get((q['ref'], q['num']), [])[1:]] - comps.append(c) - if len(comps) < 2: - return paths - - # `relax`（允许贴着走的自网焊盘）**只放没有出线段的那些**。 - # 有出线段的焊盘已经有了合法的进出口，再把整个焊盘放开的话， - # 最短路会**从焊盘的另一头钻进来**：实测 `+3V3_HUB` 就这么顺着 R715.2 的 - # 焊盘北沿爬进去，那一小段铜离 R715.1 只有 0.175 mm（0402 自己两个焊盘才隔 0.30）。 - relax = [sh_rect(q['x'], q['y'], q['hw'], q['hh'], - (L_TOP, L_BOT) if q['lay'] == 12 else (q['lay'],)) - for q in pads_all - if q['net'] == net and (q['ref'], q['num']) not in (stubs or {})] - - # 生成树用 **Prim**：每一步挑「离**已连上的整坨**最近的那个」。 - # 第一版是"离上一个接上的点最近"（最近邻链），在 33 个焊盘的 `+3V3_HUB` 上 - # 会串成一条长蛇，好几段被逼着绕过整个 Hub 卫星圈。 - cur = comps[0] - rest = comps[1:] - anchors = [cur.anchor] - while rest: - rest.sort(key=lambda c: min(math.hypot(c.anchor[0] - a[0], c.anchor[1] - a[1]) - for a in anchors)) - tgt = rest.pop(0) - # 宽度阶梯：正常宽度过不去就收窄再试。Hub 卫星圈 / 排母缝这些地方 - # 差的往往就是几十微米，收到 0.15 就通了，而载流上这些都是信号线。 - seg = None - for wtry in _widths(w, net): - seg = _connect(net, cur, tgt, obstacles, wtry, relax=relax) - if seg is not None: - break - # 首选出线方向走不通 -> 换个方向再试（见文件头那段说明） - if seg is None and getattr(tgt, 'stub_alts', None): - q = tgt.pad - for end2, ws2 in tgt.stub_alts: - t2 = Comp([tgt.rect, sh_seg(q['x'], q['y'], end2[0], end2[1], ws2, q['lay'])], - end2, center=end2, layers=tgt.layers) - for wtry in _widths(w, net): - seg = _connect(net, cur, t2, obstacles, wtry, relax=relax) - if seg is not None: - break - if seg is not None: - paths[tgt.stub_i] = [ - (round(q['x'], 4), round(q['y'], 4), q['lay'], ws2), - (round(end2[0], 4), round(end2[1], 4), q['lay'], ws2)] - tgt = t2 - if verbose: - print(u' %s.%s 改从 %s 出线' % (q['ref'], q['num'], _fmt(end2))) - break - if seg is None: - if verbose: - print(u' [!!] %s 布不通：%s -> %s' % (net, _fmt(cur.anchor), _fmt(tgt.anchor))) - cur.merge(tgt, []) - anchors.append(tgt.anchor) - continue - path, shp = seg - paths.append(path) - obstacles.extend((sp, net) for sp in shp) - cur.merge(tgt, shp) - anchors.append(tgt.anchor) - return paths - - -W_MIN = 0.15 # 一般信号收窄的下限（嘉立创四层工艺下限 0.102，留足余量） -# ⚠️ **功率网络的下限是设计规则给的，不是工艺给的。** -# `pcb2_rules.TRACK_RULES` 里 PWR1A 的 `strokeWidthMin` 是 0.25、PWR5V 是 0.30、 -# PWR4A 是 0.30；收窄到 0.15 会被 DRC 记成「物理错误·导线」—— -# 实测第一版就这么刷出 **40 条**，而净距校核一条都不报（线宽不是净距问题）。 -W_MIN_NET = {'+5V': 0.30, '+3V3_HUB': 0.15} # PWR1A 的 min 已降到 0.15，见 pcb2_rules -for _n in range(1, 6): - W_MIN_NET['VBUS%d' % _n] = 0.25 - W_MIN_NET['VO%d_P' % _n] = 0.30 - - -def _widths(w, net=None): - lo = W_MIN_NET.get(net, W_MIN) - out = [w] - for v in (round(w * 0.7, 3), lo): - if v < out[-1] - 1e-6 and v >= lo - 1e-6: - out.append(v) - return out - - -def _fmt(p): - return u'(%.2f,%.2f)' % (p[0], p[1]) - - -def _bbox(shapes, pad): - xs, ys = [], [] - for s in shapes: - if s[0] == 'rect': - xs += [s[1] - s[3], s[1] + s[3]] - ys += [s[2] - s[4], s[2] + s[4]] - elif s[0] == 'via': - xs += [s[1] - s[3], s[1] + s[3]] - ys += [s[2] - s[3], s[2] + s[3]] - else: - xs += [s[1] - s[5], s[3] + s[5]] - ys += [s[2] - s[5], s[4] + s[5]] - return (min(xs) - pad, min(ys) - pad, max(xs) + pad, max(ys) + pad) - - -def _connect(net, a, b, obstacles, w, pad=BBOX_PAD, relax=None): - u"""把两坨铜连起来。窗口先小后大、栅格先粗后细，找到就返回。 - - ⚠️ **细栅格那一档不是可有可无的。** 排母 2.54 间距 / Ø1.699 焊盘 ⇒ 缝宽 0.841 mm， - 0.25 的线要 2×(0.20+0.125) = 0.65 —— 明明过得去，但 0.1 mm 栅格上 - 离缝心最近的格心可能偏 0.04，再加 QERR 0.071 就差那么一点点， - 于是"从排母针缝里穿过去"这件事在粗栅格上**整片不可达**。 - 0.05 mm 栅格把这两项都减半，缝就通了。 - """ - # ⚠️ 窗口先**以目标为中心**开小的，再退到「整坨 + 目标」的大窗口（2026-09-06）。 - # 原来一上来就取 a.shapes + b.shapes 的包围盒：`+3V3_HUB` 已连上的那坨横跨全板， - # 窗口一大栅格就被放粗到 0.2 以上，QFN 东侧 0.71 mm 的走廊（U32.46 的出线端） - # 在粗栅格上整片不可达 —— 单独布它能通、全量布就不通，根子在这里不在拥挤。 - # 小窗口里只有离目标近的那部分 `a` 当种子，别的部分对这一段本来也没用。 - tries = [('tgt', 0, 1), ('tgt', 0, 2), ('tgt', 0, 4), ('tgt', 1, 2), ('tgt', 1, 4), - ('all', 0, 1), ('all', 0, 2), ('all', 0, 4), ('all', 1, 1), ('all', 1, 2), - ('all', 1, 4), ('all', 2, 1), ('all', 2, 4)] - for mode, grow, fine in tries: - base = b.shapes if mode == 'tgt' else a.shapes + b.shapes - x0, y0, x1, y1 = _bbox(base, pad + grow * 20.0) - x0, y0 = max(0.0, x0), max(0.0, y0) - x1, y1 = min(BW, x1), min(BH, y1) - if mode == 'tgt': - a_in = [s_ for s_ in a.shapes if _bbox([s_], 0.0)[2] > x0 and _bbox([s_], 0.0)[0] < x1 - and _bbox([s_], 0.0)[3] > y0 and _bbox([s_], 0.0)[1] < y1] - if not a_in: - continue # 这一窗里没有种子，直接开大窗 - a_use = Comp(a_in, a.anchor, center=a.center, layers=a.layers) - else: - a_use = a - # 窗口太大就把栅格放粗一档：判据里的 QERR 跟着变，仍然是**充分条件**， - # 只是长距离那几根线会保守一点（走廊本来就宽，损失不了什么）。 - g = GRID / float(fine) - while ((x1 - x0) / g + 2) * ((y1 - y0) / g + 2) > MAX_CELLS: - g *= 2 - f = Field(obstacles, (x0, y0, x1, y1), skip_net=net, grid=g) - if relax: - f.set_relax(relax) - src = _mask(f, a_use) - tgt = _mask(f, b) - cells = route_grid(f, src, tgt, w) - if cells is None: - continue - pts = _runs(cells) - chunks = polish(f, pts, w) - path = [] - for lay, xy in chunks: - for x, y in xy: - path.append((round(float(x), 3), round(float(y), 3), lay, w)) - path = _dedup(path) - # 端点钉回焊盘圆心（见 Comp 的注释）。 - # ⚠️ 端点处可能有**一串重合点**（换层），要整串一起挪，不能只挪最后一个。 - if a.center: - _snap_end(path, a.center, False) - if b.center: - _snap_end(path, b.center, True) - path = _end_via(path) - segs, vs = expand(path) - shp = [sh_seg(sx0, sy0, sx1, sy1, sw, sl) for sx0, sy0, sx1, sy1, sl, sw in segs] - shp += [sh_via(vx, vy) for vx, vy in vs] - return path, shp - return None - - -def _mask(f, c): - u"""A* 的种子 / 目标格。单焊盘只取圆心那一格，其余按整坨铜。""" - if c.center: - m = {L: np.zeros((f.ny, f.nx), bool) for L in f.lays} - i, j = f._idx(c.center[0], c.center[1]) - if 0 <= i < f.nx and 0 <= j < f.ny: - for L in c.layers: - m[L][j, i] = True - return m - return f.mask_of(c.shapes) - - -def _dedup(path): - out = [] - for p in path: - if out and abs(out[-1][0] - p[0]) < 1e-9 and abs(out[-1][1] - p[1]) < 1e-9 \ - and out[-1][2] == p[2]: - continue - out.append(p) - return out - - -def _same(a, b): - return abs(a[0] - b[0]) < 1e-9 and abs(a[1] - b[1]) < 1e-9 - - -def _snap_end(path, xy, at_end): - u"""把路径某一端**所有重合的点**一起钉到 `xy`（焊盘圆心）。 - - 换层处路径里是两个同坐标不同层的点；只挪其中一个的话， - 过孔就跟导线错开 0.05 mm，`expand()` 认不出换层，孔直接消失。 - """ - if at_end: - k = len(path) - 1 - while k > 0 and _same(path[k - 1], path[k]): - k -= 1 - rng = range(k, len(path)) - else: - k = 0 - while k + 1 < len(path) and _same(path[k], path[k + 1]): - k += 1 - rng = range(0, k + 1) - for i in rng: - path[i] = (round(xy[0], 4), round(xy[1], 4), path[i][2], path[i][3]) - - -def _end_via(path): - u"""路径**最后一个点上的过孔**要补一个重复点，`expand()` 才认得出来。 - - ⚠️ 这是本脚本抓到的最阴的一个 bug。`expand()` 的语义是 - 「第 i 点的层 = 从这一点走到下一点那一段的层」，换层的过孔打在第 i+1 点上， - **但它显式跳过最后一个点**（`i + 1 < n - 1`）——最后一点的层被当成占位符。 - 于是"走到目标焊盘正上方再换层落下去"这种路径，**过孔被静默丢掉**： - 两层的铜各画各的，中间断开。 - - 更糟的是三道校核全都抓不到：净距校核只看有没有撞上（断开当然不撞）， - DRC 的连接性又要 `location.reload()` 才刷新。 - 实测 `$25N40` / `SDA` / `VBUS_DET` / `XTAL2` / `VBUS_EN3` 五个网络就是这么断的。 - 起点侧不用补 —— 起点的重合点对 `expand()` 是"第 0 段长度为 0 + 第 1 点换层"，本来就认得出。 - """ - if len(path) >= 2 and _same(path[-1], path[-2]) and path[-1][2] != path[-2][2]: - return path + [path[-1]] - return path - - -# ══════════════════ 本轮要布的网络 ══════════════════ -def _to_site(n, seq): - return [(round(to_board(n, u_, v_, 0)[0], 3), round(to_board(n, u_, v_, 0)[1], 3), lay, ww) - for u_, v_, lay, ww in seq] - - -def bm24_pre(n): - u"""第 n 站 BM24 的 13 个 GND 脚怎么接到地平面（手写，站内坐标，**全部底层**）。 - - §25.8 判定「51 个脚旁边打不下 Ø0.61 的孔、只能逃逸出来再并」是对的。 - v5 的具体走法（和 v4 反过来，理由见上面那段车道分配）： - - · **前排** pin 2/8/12/16/24 → 往**内**（进中央通道），在 v=35.00 并成一条 0.30 梳子， - 梳子上打 4 个孔（跳过 u 50.05，它和 50.75 只隔 0.70 < 0.81）； - · **后排** pin 1/19/23/29/37/41/47 → 往**外**（v−），在 v=33.10 并成第二条梳子， - 打 5 个孔（那一带一路空到 v 26，是全站最宽敞的地方）； - · **pin 52** 单独往东平出到 u=59.60 打一个孔。 - - ⚠️ 这 65 个脚**已经从 `pcb2_fanout.py` 里整批剔除**（`SKIP_PAD`）， - 全靠这里画出来 —— 漏一个就是一条连接性 DRC。 - """ - B = lambda seq: _to_site(n, seq) - out = [] - # ── 前排：往内进中央通道 ── - # 最西那根出线段和梳子写成**同一条路径**，西端那个 90° 才切得成 45°； - # 其余几根是 T 形接头（线本身不拐弯），保持原样。 - out.append(B([(J7_GND_FRONT[0], J7_FRONT_V, L_BOT, W_ARR), - (J7_GND_FRONT[0], J7_FRONT_IN, L_BOT, W_COMB), - (J7_GND_FRONT[0], J7_MID_COMB, L_BOT, W_COMB), - (J7_GND_FRONT[-1], J7_MID_COMB, L_BOT, W_COMB)])) - for u_ in J7_GND_FRONT[1:]: - out.append(B([(u_, J7_FRONT_V, L_BOT, W_ARR), - (u_, J7_FRONT_IN, L_BOT, W_COMB), - (u_, J7_MID_COMB, L_BOT, W_COMB)])) - for u_ in J7_MID_VIA_U: - out.append(B([(u_, J7_MID_COMB, L_BOT, W_COMB), (u_, J7_MID_COMB, L_TOP, W_COMB)])) - # ── 后排：往外并成第二条梳子 ── - out.append(B([(J7_GND_BACK[0], J7_BACK_V, L_BOT, W_ARR), - (J7_GND_BACK[0], J7_BACK_ESC, L_BOT, W_COMB), - (J7_GND_BACK[0], J7_BACK_COMB, L_BOT, W_COMB), - (J7_GND_BACK[-1], J7_BACK_COMB, L_BOT, W_COMB)])) - for u_ in J7_GND_BACK[1:]: - out.append(B([(u_, J7_BACK_V, L_BOT, W_ARR), - (u_, J7_BACK_ESC, L_BOT, W_COMB), - (u_, J7_BACK_COMB, L_BOT, W_COMB)])) - for u_ in J7_BACK_VIA_U: - out.append(B([(u_, J7_BACK_COMB, L_BOT, W_COMB), (u_, J7_BACK_COMB, L_TOP, W_COMB)])) - # ── pin 52：往东平出打孔 ── - out.append(B([(J7_GND_BIG, J7_MID_V, L_BOT, W_COMB), - (J7_PIN52_VIA_U, J7_MID_V, L_BOT, W_COMB), - (J7_PIN52_VIA_U, J7_MID_V, L_TOP, W_COMB)])) - return out - - -def bm24_lane(n, kind): - u"""THERM / CC1 从前排往**外**出，直接进正北的 R77n.1 / R76n.1（v5）。 - - v4 那条「走中央通道往东绕出来」的路线在 v5 已经没有必要 —— - 后排整排都是 GND，通道判给了前排 GND 的梳子，而 R76n/R77n 就在前排外侧。 - - · `CC1_n`：R76n 的中心特意取 52.233，pin1 正落在 u 51.800 = J7n.22 正北 - ⇒ **一根直线上去**，全程底层。 - · `THERM_n`：目标在 u 54.367，要往东跨过 CC1 那根竖线 —— - **打两个孔走顶层过去**（顶层在 J7n 这一带一根线都没有）。 - 西孔离 `*_DPJ` 的换层孔 0.97 ≥ 0.81，是这一段最紧的一处。 - """ - if kind == 'CC1': - return _to_site(n, [(J7_CC1_U, J7_FRONT_V, L_BOT, W_ARR), - (J7_CC1_U, J7_FRONT_ESC, L_BOT, W_LANE), - (J7_R76_PIN1_U, J7_R_ENTER_V, L_BOT, W_LANE)]) - (wu, wv), (eu, ev) = J7_THERM_VIA - ku, kv = J7_THERM_KINK - # ⚠️ 第 i 点的 width 管的是「这一点到下一点」那一段。 - # 前两段（直出 + 45° 斜出）**必须都是 0.11** —— 理由见 J7_THERM_TURN_V 那一段注释。 - return _to_site(n, [(J7_THERM_U, J7_FRONT_V, L_BOT, W_ARR), - (J7_THERM_U, J7_THERM_TURN_V, L_BOT, W_ARR), # 直出到 36.58，仍 0.11 - (ku, kv, L_BOT, W_LANE), # 45° 斜出，仍 0.11 -> 之后放宽 - (wu, wv, L_BOT, W_LANE), # 竖上到西孔（离 DPJ 孔 0.80） - (wu, wv, L_TOP, W_LANE), # ↑ 换层 - (eu, ev, L_TOP, W_LANE), # 顶层东行（顶层这一带是空的） - (eu, ev, L_BOT, W_LANE), # ↓ 换层 - (J7_R77_PIN1_U, J7_R_ENTER_V, L_BOT, W_LANE)]) - - -# ── 布线顺序（挤的先布、宽的先布）───────────────────────────────────── -# Hub 卫星圈是 1.2 mm 网格上的 0402，缝只有 0.66 mm；服务带里 0402 也是密排。 -# 所以次序是：**Hub 局部 -> 上游 -> 站内局部 -> 电源 -> 长距离控制线**。 -ALL_NETS = set() -PADS_ALL = [] # main() 装进来，`_pogo_by_length()` 要用 -lanes0 = (['THERM_%d' % n for n in range(1, 6)] + ['CC1_%d' % n for n in range(1, 6)]) - - -def _pogo_by_length(): - u"""十五根 POGO，按站分组、组内按两端直线距离从短到长。""" - out = [] - for n in range(1, 6): - row = [] - for k in ('PWR', 'VUP', 'VDN'): - net = 'POGO%d_%s' % (n, k) - ps = [p for p in PADS_ALL if p['net'] == net] - d = (math.hypot(ps[0]['x'] - ps[1]['x'], ps[0]['y'] - ps[1]['y']) - if len(ps) == 2 else 0.0) - row.append((d, net)) - out += [net for _d, net in sorted(row)] - return out - - -def net_order(): - # GND 与 THERM/CC1 的车道排最前：BM24 周围那三条缝是**手写死的几何**， - # 后面所有网络都必须看得见它们、绕开走。 - # - # ⚠️ 2026-09-06 试过把 `+3V3_HUB` 提到这一组最前（想让它先抢卫星圈的缝）， - # **结果更糟**：它有 33 个焊盘，先布就把 Hub 周围铺满， - # `XTAL1`/`CFGSEL0`/`PRTDIS6`/`PRTDIS7`/`HUB_RST` 五根配置线全布不通 - # （没布通的从 4 个涨到 7 个）。⇒ 大网络必须排在点对点的小网络之后。 - hub = ['GND'] + lanes0 + ['VBUS_UP'] + [ - 'RBIAS', 'VDD18', 'VDD18PLL', 'XTAL1', 'XTAL2', - 'CFGSEL0', 'CFGSEL1', 'NONREM0', 'NONREM1', 'PRTDIS6', 'PRTDIS7', - 'HUB_RST', '+3V3_HUB', 'VBUS_DET'] - # `EDL_ENn` / `VBUS_ENn` 在 U4n / U2n 上是**紧挨着 +3V3 脚的那一针**， - # 排在 `+3V3_HUB` 之前，否则 3V3 的长支干会从这 0.95 mm 的缝里横穿过去。 - en = ['EDL_EN%d' % n for n in range(1, 6)] + ['VBUS_EN%d' % n for n in range(1, 6)] - # `+3V3_HUB` 排在 Hub 局部之后、其它一切之前：它有 33 个焊盘、 - # 一半挤在 Hub 的卫星圈里，晚一步就没缝了。 - # `+5V` 紧跟 `+3V3_HUB`：它要从排母穿过已经站满 EN/POGO 线的走廊过来， - # 排在后面的话 site2/site5 那两段就没缝了。 - # 2026-09-06（v5）实测调过一次次序：`+3V3_HUB` 和 `VBUS_UP` 单独跑都能通 - # （45 s / 2 s），一起跑就都断 —— 说明是抢地盘，不是没有路。 - # · `+3V3_HUB` 提到 EN 组**之前**（但仍在 Hub 局部之后，那五根配置线的教训还在）； - # · `VBUS_UP` 提到 `+5V` **之前** —— 它要横穿大半块板去 J23， - # 而 `+5V` 是 0.60 的宽线，先布就把那条走廊占死了。 - up = en + ['VBUS_UP', 'UP_VBUS_DET', '+5V', '$16N222', '$16N224'] - # `$` 开头的是原理图自动命名的局部网（J6n<->U4n、C72n<->U2n）， - # 编号不成规律（site1 是 $21N57/58，其余是 $2xN39/40），所以从网表里捞。 - site = sorted(n for n in ALL_NETS if n.startswith('$')) - power = ['VBUS%d' % n for n in range(1, 6)] - # 每个站的三根 POGO 按**两端直线距离从短到长**排：短的那根余地最小， - # 让它先挑路；长的绕得起。site4/site5 上这条规则把 `VDN` 提到最前 —— - # 它的源在最东、靶点却在最西（J59 比 J57/J58 靠里），后布就被另外两根夹死 - # （`POGO5_VDN` 原来就是这么布不通的）。 - ctrl = [n for n in _pogo_by_length()] + ['SDA', 'SCL'] - out, seen = [], set() - for n in hub + up + site + power + ctrl: - if n not in seen: - seen.add(n) - out.append(n) - return out - - -# ⚠️ 手写的前置段也**必须**过一遍 `_end_via()`。 -# `bm24_pre()` 里那些「走到位置 -> 换层」的路径最后两个点是同坐标不同层， -# 而 `expand()` 显式跳过最后一个点上的过孔 —— 五个站 **50 个 GND 过孔全部丢掉**， -# 两条梳子和 pin52 的连线整个悬空，DRC 报出 J7n 的 pin 1/2/8/12/47/52 断开。 -# 净距校核和 `inner1_verify` 都不会响：悬空的铜不违反任何净距。 -PRE = {} -for _n in range(1, 6): - PRE.setdefault('GND', []).extend(_end_via(p) for p in bm24_pre(_n)) - PRE['THERM_%d' % _n] = [_end_via(bm24_lane(_n, 'THERM'))] - PRE['CC1_%d' % _n] = [_end_via(bm24_lane(_n, 'CC1'))] - -PRE_ONLY = {'GND'} # 只落前置段、不做最小生成树的网络 -OUT = os.path.join(HERE, '_pcb2_sig_routes.json') - - -# ══════════════════ 下发 ══════════════════ -# ⚠️ `pcb2_route_dp.push()` 的做法是「把这些网络上现有的线和过孔全删掉再重画」。 -# 对差分对没问题，对 **GND 是灾难** —— 一按就把 §25.8 那 210 个扇出过孔和 -# 126 条出线全扫掉，而几何校核和 DRC 都只会说"连接性错误变多了"。 -# 所以 GND 走**外科式删除**：只删落在五个 BM24 逃逸框里的 GND 铜。 -# v5 的框取站内 u ∈ [47.5, 60.3]、v ∈ [32.5, 36.5]： -# · 装得下两条梳子（v 35.00 / 33.10）、13 根出线和 pin52 往东那一截； -# · **不碰**框外那些 `pcb2_fanout.py` 画的孔 —— R77n.2 在 v 38.0、U5n.2 的孔在 (48.80, 39.45)， -# 两者都在 v > 36.5；手机定位柱 PnH3 在 u 61.90 > 60.3。 -# · J7n 那 65 个 GND 脚本来就被 `pcb2_fanout.SKIP_PAD` 剔除了，框里除了本脚本自己画的没有别人的铜。 -GND_BOX_UV = (47.5, 32.5, 60.3, 36.5) - - -def gnd_boxes(): - out = [] - for n in SITES: - xs, ys = [], [] - for u_, v_ in ((GND_BOX_UV[0], GND_BOX_UV[1]), (GND_BOX_UV[2], GND_BOX_UV[3])): - bx, by, _ = to_board(n, u_, v_, 0) - xs.append(bx) - ys.append(by) - out.append([round(min(xs), 3), round(min(ys), 3), round(max(xs), 3), round(max(ys), 3)]) - return out - - -JS_PUSH_SIG = u""" -const NETS = %s, BOXES = %s, SEGS = %s, VIAS = %s, MIL = %f; -const S = new Set(NETS); -const inBox = (x, y) => BOXES.some(b => x >= b[0] && x <= b[2] && y >= b[1] && y <= b[3]); -let dl = 0, dv = 0; -for (const o of await eda.pcb_PrimitiveLine.getAll()) { - const L = o.getState_Layer(); if (L !== 1 && L !== 2) continue; - const n = o.getState_Net(); - const keep = n === 'GND' - ? !(inBox(o.getState_StartX()/MIL, o.getState_StartY()/MIL) && - inBox(o.getState_EndX()/MIL, o.getState_EndY()/MIL)) - : !S.has(n); - if (!keep) { await eda.pcb_PrimitiveLine.delete(o.getState_PrimitiveId()); dl++; } -} -for (const o of await eda.pcb_PrimitiveVia.getAll()) { - const n = o.getState_Net(); - const keep = n === 'GND' ? !inBox(o.getState_X()/MIL, o.getState_Y()/MIL) : !S.has(n); - if (!keep) { await eda.pcb_PrimitiveVia.delete(o.getState_PrimitiveId()); dv++; } -} -let nl = 0, nv = 0; -for (const [net, lay, x0, y0, x1, y1, w] of SEGS) { - await eda.pcb_PrimitiveLine.create(net, lay, x0*MIL, y0*MIL, x1*MIL, y1*MIL, w*MIL); nl++; -} -for (const [net, x, y] of VIAS) { - await eda.pcb_PrimitiveVia.create(net, x*MIL, y*MIL, %f*MIL, %f*MIL); nv++; -} -await eda.pcb_Document.save(); -await new Promise(r => setTimeout(r, 2500)); -return {del_lines: dl, del_vias: dv, lines: nl, vias: nv}; -""" - - -def push_sig(routes): - segs, vs = [], [] - for key, path in routes.items(): - net = netof(key) - s_, v_ = expand(path) - for x0, y0, x1, y1, lay, w in s_: - segs.append([net, lay, round(x0, 4), round(y0, 4), round(x1, 4), round(y1, 4), w]) - for x, y in v_: - vs.append([net, round(x, 4), round(y, 4)]) - nets = sorted(set(netof(k) for k in routes) - {'GND'}) - js = ("await eda.dmt_EditorControl.openDocument('%s');" - "await new Promise(r=>setTimeout(r,1800));" % PCB) + ( - JS_PUSH_SIG % (json.dumps(nets), json.dumps(gnd_boxes()), json.dumps(segs), - json.dumps(vs), MIL, VIA_H, VIA_D)) - from eda import run - r = run(js, timeout=1800) - if not r.get('success'): - sys.exit(u'下发失败: ' + json.dumps(r, ensure_ascii=False)[:600]) - d = r['result'] - print(u'下发完成：先删 %d 线 / %d 孔，再画 %d 线 / %d 孔' - % (d['del_lines'], d['del_vias'], d['lines'], d['vias'])) - - -def _to_site_uv(n, x, y): - u"""板坐标 -> 站内 (u, v)。`to_board` 的逆。""" - x0, y0, rho = SITES[n] - if rho == 0: - return (x - x0, y - y0) - return (PW - (x - x0), PH - (y - y0)) - - -def j7_assert(pads): - u"""**把上面那一堆 J7_* 常量和板上的实际焊盘对一遍**（五个站逐一）。 - - ⚠️ 这个断言是 2026-09-06 补的，起因是它不在的时候踩的坑： - v5 把 J7n 从 rot 180 改成 rot 0 又挪了位置，站内坐标整体差 - `u' = u − 5.00 / v' = 32.00 − v`，而脚本照旧用 v4 的常量 —— - `bm24_pre()` 于是在**空地上**画了五套梳子，净距校核全过（空地当然不撞）， - 只有 DRC 的连接性会含糊地多出几十条。⇒ 手写坐标必须有断言兜底。 - """ - bad = [] - for n in SITES: - by = {} - for p in pads: - if p['ref'] != 'J7%d' % n: - continue - u_, v_ = _to_site_uv(n, p['x'], p['y']) - by[p['num']] = (round(u_, 3), round(v_, 3), p['net'], p['lay']) - if not by: - bad.append(u'J7%d 一个焊盘都没找到' % n) - continue - want = ([(str(k), J7_GND_FRONT[i], J7_FRONT_V) for i, k in enumerate((2, 8, 12, 16, 24))] - + [(str(k), J7_GND_BACK[i], J7_BACK_V) for i, k in enumerate((1, 19, 23, 29, 37, 41, 47))] - + [('52', J7_GND_BIG, J7_MID_V)]) - for num, uu, vv in want: - got = by.get(num) - if not got: - bad.append(u'J7%d 没有 pin%s' % (n, num)); continue - if got[2] != 'GND': - bad.append(u'J7%d.pin%s 的网络是 %s，不是 GND' % (n, num, got[2])) - if abs(got[0] - uu) > 0.02 or abs(got[1] - vv) > 0.02: - bad.append(u'J7%d.pin%s 实测 (%.3f, %.3f)，常量写的是 (%.2f, %.2f)' - % (n, num, got[0], got[1], uu, vv)) - for num, uu, net in (('14', J7_THERM_U, 'THERM_%d' % n), ('22', J7_CC1_U, 'CC1_%d' % n)): - got = by.get(num) - if not got: - bad.append(u'J7%d 没有 pin%s' % (n, num)); continue - if got[2] != net: - bad.append(u'J7%d.pin%s 的网络是 %s，应为 %s' % (n, num, got[2], net)) - if abs(got[0] - uu) > 0.02 or abs(got[1] - J7_FRONT_V) > 0.02: - bad.append(u'J7%d.pin%s 实测 u=%.3f v=%.3f，常量 u=%.2f v=%.2f' - % (n, num, got[0], got[1], uu, J7_FRONT_V)) - if by.get('2') and by['2'][3] != L_BOT: - bad.append(u'J7%d 不在底层（lay=%s）—— bm24_pre 的路径层写死了 L_BOT' % (n, by['2'][3])) - # THERM / CC1 的靶子：R76n.1 / R77n.1 - for ref, uu, tag in (('R76%d' % n, J7_R76_PIN1_U, 'CC1'), ('R77%d' % n, J7_R77_PIN1_U, 'THERM')): - hit = [p for p in pads if p['ref'] == ref and p['num'] == '1'] - if not hit: - bad.append(u'找不到 %s.1' % ref); continue - u_, v_ = _to_site_uv(n, hit[0]['x'], hit[0]['y']) - if abs(u_ - uu) > 0.02 or abs(v_ - J7_R_PAD_V) > 0.02: - bad.append(u'%s.1（%s）实测 (%.3f, %.3f)，常量 (%.3f, %.3f)' - % (ref, tag, u_, v_, uu, J7_R_PAD_V)) - if bad: - for t in bad[:20]: - print(u' !! ' + t) - sys.exit(u'\nBM24 的手写常量和板上对不上（%d 条）—— 先改常量再布线。' % len(bad)) - print(u'BM24 手写常量与板上实测一致（五个站 × 13 个 GND 脚 + THERM/CC1 + R76n/R77n）✔') - - -def main(): - only = [a for a in sys.argv[1:] if not a.startswith('--')] - pads, vias, lines = geom() - ALL_NETS.update(p['net'] for p in pads if p['net']) - PADS_ALL[:] = pads - j7_assert(pads) - # ⚠️ 下发时要删掉五个 BM24 框里的旧 GND 铜（§25.8 自动扇出的产物）， - # 所以**算的时候就得当它们已经没了** —— 否则手写的车道会跟一堆 - # 马上就要消失的过孔"撞车"，而真正的冲突反而被淹没。 - boxes = gnd_boxes() - inbox = lambda x, y: any(b[0] <= x <= b[2] and b[1] <= y <= b[3] for b in boxes) - mine = set(net_order()) - {'GND'} - n0 = len(vias) + len(lines) - # ① 本脚本负责的网络：下发时整网删掉重画，所以**算的时候就当它们不存在**。 - # 不摘的话，第二次跑会把自己上一轮的线当成障碍 —— 结果既不幂等， - # 还会在校核里刷出一堆「和马上要删掉的那条线撞了」的假冲突（实测 3 条）。 - # ② GND 只摘五个 BM24 框里的（§25.8 自动扇出的产物，下发时按框删）。 - vias = [v for v in vias - if v['net'] not in mine and not (v['net'] == 'GND' and inbox(v['x'], v['y']))] - lines = [l for l in lines - if l['net'] not in mine and not (l['net'] == 'GND' and inbox(l['x0'], l['y0']) - and inbox(l['x1'], l['y1']))] - print(u'障碍表：焊盘 %d / 过孔 %d / 铜层导线 %d（摘掉本脚本自己负责的旧铜 %d 件）' - % (len(pads), len(vias), len(lines), n0 - len(vias) - len(lines))) - order = [n for n in net_order() if not only or n in only] - obs = shapes_of(pads, vias, lines) - have = set(p['net'] for p in pads) - missing = [n for n in order if n not in have] - if missing: - sys.exit(u'网络表里没有这些网络：%s' % missing) - - # ⚠️ `+3V3_HUB` 上**已经有铜**：`pcb2_dp_long.py` 在 Hub 西缘画了三条 - # （pin5 / pin10 / 顶层干线，15 段 + 4 个孔）。它们被 D± 夹在中间， - # 是差分那一轮算出来的、后面的布线器再也挤不进去的位置。 - # 而 `push_sig()` 的做法是「把本脚本负责的网络整网删掉重画」—— - # 不管的话这三条会被静默抹掉，只在 DRC 里冒出几条连接性错误。 - # ⇒ 从**同一个事实来源**（`pcb2_dp_long.build`）取回来当本网的前置段： - # 既让最小生成树知道这些焊盘已经连上了，下发时也原样重画。 - from pcb2_dp_long import build as _dp_long_build - _kept = [q for k, q in _dp_long_build(pads).items() if netof(k) == '+3V3_HUB'] - if len(_kept) != 3: - sys.exit(u'pcb2_dp_long 里的 +3V3_HUB 前置段应有 3 条，实际 %d 条' % len(_kept)) - # U32 的 7 个 +3V3 脚里，**pin46 在东排、四周被 VBUS_DET / NONREM0 围死**， - # 它唯一的出路是往 QFN **肚子里**走：南排焊盘上沿 63.975 与散热盘南沿 65.60 - # 之间有一条 1.6 mm 的死带（芯片底下，没有别人要用）。 - # 单独跑 `--net +3V3_HUB` 时布线器自己就是这么走的；但排在 Hub 那几根配置线之后跑， - # 那个内角已经被占掉 ⇒ 干脆手写成前置段，和 BM24 的梳子一样**先占住**。 - # (102.25, 63.975) 是 pin52 焊盘的北沿；45° 斜段离 pin51 焊盘框 0.50、 - # 东行段离 pin47/pin45 焊盘框各 0.35（0.24 的线要 0.32）✔ - PRE['+3V3_HUB'] = _kept + [[(102.250, 63.550, L_BOT, 0.24), - (102.250, 64.125, L_BOT, 0.24), - (103.375, 65.250, L_BOT, 0.24), - (104.450, 65.250, L_BOT, 0.24)], - # R716.2（HUB_RST 的上拉）是最东边那颗 +3V3 焊盘， - # 夹在 R711.2 / R720.2 两个 GND 脚之间（南北各 1.2 mm）， - # 只能**翻顶层**从 C750.1 斜拉过来。同样先占住。 - # 两个孔位都是卡着算的： - # 西孔 (105.95, 63.825)：离 R710.2 那条 0.15 扇出线 0.624（要 0.58） - # —— 原来放在 105.88 只有 0.566，差 14 µm； - # 东孔 (109.60, 66.45)：离 `USB5_DP` 竖段 (x 110.30) 0.70（要 0.645） - # —— 原来放在 109.72 只有 0.58，差 65 µm。 - [(105.950, 63.450, L_BOT, 0.35), - (105.950, 63.825, L_BOT, 0.35), - (105.950, 63.825, L_TOP, 0.35), - (106.275, 64.150, L_TOP, 0.35), - (107.300, 64.150, L_TOP, 0.35), - (109.600, 66.450, L_TOP, 0.35), - (109.600, 66.450, L_BOT, 0.35), - (109.333, 66.450, L_BOT, 0.35)]] + PRE.get('+3V3_HUB', []) - print(u'+3V3_HUB 保留 pcb2_dp_long 画的 3 条前置段（%d 段导线 / %d 个孔）' - % (sum(len(expand(q)[0]) for q in _kept), sum(len(expand(q)[1]) for q in _kept))) - - # `HUB_RST`：U32.43 (104.45, 66.75) 到 R716.1 (108.467, 66.45) 之间只有 - # R709(y 65.85) 与 R712(y 67.05) 之间那条 **0.66 mm** 的缝。 - # 0.20 的线走它是够的（上下各 0.23 ≥ 0.20），但**栅格布线器进不去**： - # 它的判据是 `edt >= 0.20 + 0.10 + QERR(0.0708) = 0.371`，而半缝只有 0.33。 - # ⇒ 这一段也手写。（不是布线器的 bug —— 0.1 mm 栅格就是分辨不出 0.03 的余量。） - # ⚠️ 这一段**必须 0.15 不能 0.20**，两处都是算死的： - # 转折点 a 的窗口：往西受 U32.44 焊盘框（东沿 104.875）挡，a >= 104.875 + (w/2+0.20)； - # 往东受 R712.1 焊盘框西南角 (105.584, 66.780) 挡（45° 斜段的垂距）。 - # w=0.20 时窗口只有 15 µm（105.175~105.190），w=0.15 时有 75 µm ⇒ 取 105.19。 - # 东行段 y=66.45 离 (107.624, 67.050) 那个 GND 扇出孔 0.600： - # w=0.20 要 0.605（差 5 µm 不过），w=0.15 要 0.58 ✔ - PRE['HUB_RST'] = [[(104.450, 66.750, L_BOT, 0.15), - (105.190, 66.750, L_BOT, 0.15), - (105.490, 66.450, L_BOT, 0.15), # 45° - (108.467, 66.450, L_BOT, 0.15)]] - - # `VBUS_DET`：U32.44 (104.45, 66.25) 到 R709.2 (105.867, 65.85) —— 和 HUB_RST 同一个口袋。 - # HUB_RST 的手写段占了 y 66.45 那条线之后，这一小段的余量掉到栅格分辨不出来的量级， - # 所以一起手写。45° 斜段离 HUB_RST 斜段 0.4525（要 0.375）、离 U32.45 焊盘框 0.371（要 0.30）。 - PRE['VBUS_DET'] = [[(104.450, 66.250, L_BOT, W_SIG), - (105.050, 66.250, L_BOT, W_SIG), - (105.450, 65.850, L_BOT, W_SIG), # 45° - (105.867, 65.850, L_BOT, W_SIG)]] - - # `+5V`：J32.39 与 J32.40 是排母上下相邻的两针，中间 2.54 mm。 - # 上一轮布线器给 J32.39 留的出线段末端**正好落在 J32.40 的焊盘圈里**（差 0.077）， - # 本脚本的连通域判定认了，EasyEDA 的连接性检查不认 —— DRC 报 - # 「导线 (+5V) 与其他相同网络的对象断开了连接」+「插件焊盘 J32_39 断开」。 - # ⇒ 两针之间直接连一根顶层短线，端点落在焊盘中心，谁都不会误判。 - PRE['+5V'] = [[(182.1298, 68.770, L_TOP, 0.60), - (182.1298, 66.230, L_TOP, 0.60)]] - - pre_pads = set() - for net, ps in PRE.items(): - for p in ps: - for q in pads: - if q['net'] == net and seg_rect((p[0][0], p[0][1]), (p[0][0], p[0][1]), - q['x'], q['y'], q['hw'], q['hh']) < 1e-6: - pre_pads.add((q['ref'], q['num'])) - # ⚠️ **所有前置段一开始就进障碍表**（带各自的网络名）。 - # 原来只有 GND 的在循环里补进去，THERM/CC1/+3V3 的要等轮到自己才进 —— - # 于是排在它们前面的网络看不见这些手写坐标，照样从上面碾过去。 - for _net, _ps in PRE.items(): - for _p in _ps: - _sg, _vv = expand(_p) - for _x0, _y0, _x1, _y1, _lay, _w in _sg: - obs.append((sh_seg(_x0, _y0, _x1, _y1, _w, _lay), _net)) - for _x, _y in _vv: - obs.append((sh_via(_x, _y), _net)) - stubs, stub_alts = plan_stubs(order, pads, obs, pre_pads) - print(u'预留出线段 %d 条' % len(stubs)) - - routes, failed = {}, [] - t0 = time.time() - for net in order: - t = time.time() - if net in PRE_ONLY: - # GND 不做最小生成树 —— 它靠 Inner2 整板地平面 + §25.8 的扇出连通， - # 这里只补 BM24 那 65 个脚的逃逸段（`bm24_pre`），照原样落盘。 - ps = list(PRE[net]) - for p in ps: - for x0, y0, x1, y1, lay, w in expand(p)[0]: - obs.append((sh_seg(x0, y0, x1, y1, w, lay), net)) - for x, y in expand(p)[1]: - obs.append((sh_via(x, y), net)) - ok = True - else: - ps = route_net(net, pads, obs, pre=PRE.get(net), verbose=True, - stubs=stubs, alts=stub_alts) - ok = _wire_ok(net, ps, pads) - if not ok: - failed.append(net) - for k, p in enumerate(ps): - routes[net if k == 0 else '%s#%d' % (net, k + 1)] = p - print(u' %-12s %2d 段路径 / %3d 导线 / %2d 过孔 %5.1fs %s' - % (net, len(ps), sum(len(expand(q)[0]) for q in ps), - sum(len(expand(q)[1]) for q in ps), time.time() - t, - u'' if ok else u' ← 有端点没连上')) - print(u'\n%d 个网络 / %d 条路径 / %d 段导线 / %d 个过孔 （%.0f 秒）' - % (len(order), len(routes), sum(len(expand(p)[0]) for p in routes.values()), - sum(len(expand(p)[1]) for p in routes.values()), time.time() - t0)) - if failed: - print(u'⚠️ %d 个网络没布通：%s' % (len(failed), u' '.join(failed))) - - # ── 45° 化（2026-09-06 用户拍板：全板不许有直角走线）── - # 放在**布完之后统一做**，而不是每条路径各切各的： - # 斜切只会拿掉铜，所以拿"未切之前"的其它段做校核是保守且正确的。 - n0 = len(sharp_corners(routes)) - t = time.time() - routes = chamfer_routes(routes, pads, vias, lines, smooth=True) - left = sharp_corners(routes) - print(u'\n45° 化：直角拐点 %d -> %d（%.0f 秒）' % (n0, len(left), time.time() - t)) - for key, i, xy, ang in left[:20]: - print(u' [!!] 切不动: %-12s (%.2f, %.2f) 转向 %.0f°' % (key, xy[0], xy[1], ang)) - if len(left) > 20: - print(u' （还有 %d 处）' % (len(left) - 20)) - - print(u'\n净距校核（%.2f mm）:' % CLR) - bad = check(routes, pads, vias, lines) - if not bad: - print(u' 全部通过 ✔') - json.dump({k: [list(map(float, q[:2])) + [int(q[2]), float(q[3])] for q in v] - for k, v in routes.items()}, - io.open(OUT, 'w', encoding='utf-8')) - print(u'路径已存 %s' % os.path.basename(OUT)) - - if '--push' in sys.argv: - if bad: - sys.exit(u'\n!! 净距还有问题，不下发。') - if failed and '--force' not in sys.argv: - sys.exit(u'\n!! 还有 %d 个网络没布通，要下发请加 --force。' - u'（没布通的网络只会落下几截悬空的出线段，' - u'下一轮 --push 会把它们连同别的一起删掉重画。）' % len(failed)) - push_sig(routes) - - -def _wire_ok(net, paths, pads_all): - u"""这个网络是不是**真的连成一坨**（按实际铜算连通域，不看 DRC）。 - - ⚠️ 判据必须是"连通域 == 1"，**不能是"每个焊盘都被某条线碰到"**。 - 每个焊盘出门时都先画了一小截 `entry_stub`，所以"被碰到"永远成立 —— - 第一版就是这么写的，于是 20 个断开的网络里只报出 5 个， - 另外 15 个各自剩着一截悬空的出线段，几何校核还全绿。 - """ - items = [] # (层集合, 种类, 数据) - for q in pads_all: - if q['net'] == net: - lay = {L_TOP, L_BOT} if q['lay'] == 12 else {q['lay']} - items.append((lay, 'pad', (q['x'], q['y'], q['hw'], q['hh']))) - for p in paths: - segs, vs = expand(p) - for x0, y0, x1, y1, lay, w in segs: - items.append(({lay}, 'seg', (x0, y0, x1, y1, w / 2.0))) - for x, y in vs: - items.append(({L_TOP, L_BOT}, 'via', (x, y, VIA_R))) - n = len(items) - if n < 2: - return True - par = list(range(n)) - - def find(i): - while par[i] != i: - par[i] = par[par[i]] - i = par[i] - return i - - def touch(a, b): - la, ka, da = a - lb, kb, db = b - if not (la & lb): - return False - if ka > kb: - return touch(b, a) - if ka == 'pad' and kb == 'pad': - return (abs(da[0] - db[0]) <= da[2] + db[2] + 1e-6 - and abs(da[1] - db[1]) <= da[3] + db[3] + 1e-6) - if ka == 'pad' and kb == 'seg': - return seg_rect((db[0], db[1]), (db[2], db[3]), da[0], da[1], da[2], da[3]) <= db[4] + 1e-6 - if ka == 'pad' and kb == 'via': - return seg_rect((db[0], db[1]), (db[0], db[1]), da[0], da[1], da[2], da[3]) <= db[2] + 1e-6 - if ka == 'seg' and kb == 'seg': - return seg_seg((da[0], da[1]), (da[2], da[3]), - (db[0], db[1]), (db[2], db[3])) <= da[4] + db[4] + 1e-6 - if ka == 'seg' and kb == 'via': - return seg_pt(da[0], da[1], da[2], da[3], db[0], db[1]) <= da[4] + db[2] + 1e-6 - return math.hypot(da[0] - db[0], da[1] - db[1]) <= da[2] + db[2] + 1e-6 - - for i in range(n): - for j in range(i + 1, n): - if find(i) != find(j) and touch(items[i], items[j]): - par[find(i)] = find(j) - return len(set(find(i) for i in range(n))) == 1 - - -if __name__ == '__main__': - main() +# -*- coding: utf-8 -*- +u"""载板电源 + 杂散信号布线：**栅格迷宫布线器**（`pcb2_route_dp.py` 的姊妹件）。 + + /c/Python314/python .claude/pcb2_route_sig.py # 全部算 + 本地校核，不下发 + /c/Python314/python .claude/pcb2_route_sig.py --net +5V # 只算这几个网络（可多个） + /c/Python314/python .claude/pcb2_route_sig.py --push # 下发（只删本脚本负责的网络） + /c/Python314/python .claude/pcb2_route_sig.py --refresh ... # 先 pcb2_route_dp.dump() 刷障碍表再算（**每次 --push 之后板子就变了，下一次 --net 必须带**） + /c/Python314/python .claude/pcb2_route_sig.py --plot out.png # 画一张自己算的图 + +## 为什么这里用布线器，差分对却是手写坐标 + +差分对只有 11 对，但每一对都要管耦合、参考面、偏斜、换层窗口 —— 是**几何设计**， +写死坐标才说得清理由。剩下这 60 来个网络是另一回事：三百多个端点、 +大部分是「从 A 走到 B、别撞上东西」，逐条手写既慢又容易漏。 +所以这里搭一个**能被同一套 `check()` 验的**布线器：路径怎么来的不重要， +下发前一律过 `pcb2_route_dp.check()`（和差分对同一份净距判据）。 + +## 障碍模型（三条都实测过，别改成"看着差不多"的写法） + +1. **栅格 0.1 mm，量化误差按最坏算**。障碍按"格心落在铜里"栅格化， + 再做欧氏距离变换（`scipy.ndimage.distance_transform_edt`）。 + 真实铜边最多比"最近的被标记格心"再近 `grid·√2/2 = 0.0708 mm`， + 所以判据一律是 `edt >= 净距 + 半线宽 + QERR`，**QERR 不许省**。 +2. **本轮自己画的线立刻进障碍表**。网络是一个一个布的， + 后布的必须看得见先布的 —— 否则本地校核会在最后一起爆。 +3. **通孔焊盘（layer 12）两层都算障碍**，过孔也是。板框按 220×135 R5 内缩 1 mm。 + +## BM24 的出线（`STUB`）不交给布线器 + +`J7n` 是 0.35 mm 间距，相邻焊盘净距只有 0.17 mm —— 0.1 mm 的栅格根本分辨不出来， +而且出线宽度要在 0.11 / 0.20 / 0.28 三档之间切换（算式见 `pcb2_route_dp.W_ARR`）。 +所以这一小段**手写**：前排一律往南直出、后排一律往北直出（§25.8 的硬约束）， +出了阵列再让布线器接手。GND 脚另外在阵列外并成一条梳子、共用过孔。 +""" +import io +import json +import math +import os +import sys +import time + +import numpy as np +from scipy import ndimage + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from pcb2_route_dp import (geom, check, expand, netof, push, MIL, PCB, KSEP, + L_TOP, L_BOT, CLR, VIA_D, VIA_H, seg_rect, seg_pt, seg_seg, + chamfer_routes, sharp_corners, turn_deg, SHARP, CHAMFER_R, seg_slack) +from pcb2_place import SITES, to_board, BW, BH, PW, PH + +GRID = 0.1 # 栅格步长 mm +QERR = GRID * math.sqrt(2) / 2 # 栅格量化误差上界 0.0708 mm，判据里必须加上 +EDGE = 1.0 # 铜离板边的最小距离 +CORNER_R = 5.0 +VIA_R = VIA_D / 2.0 +HOLE_CLR = 0.30 # 钻孔到钻孔（规则 otherClearance.hole2Hole），**不分网络** +VIA_COST = 2.5 # 换一次层折算成多少 mm 路程（压住"没事就打孔"） +# 2026-09-07 用户定的布线规则：**顶层走水平、底层走纵向**（经典 H/V 分层）。 +# 做成**软代价**而不是硬禁止：逆向走法每 mm 按 DIR_PENALTY 倍计价，45° 斜段按中间值计。 +# 硬禁止会让出线段 / 1~2 mm 的短跳全布不通（焊盘出线方向由封装决定，不由层决定）。 +# 取 2.0：一段 5 mm 的逆向直线代价 10 mm，正好等于「打两个孔翻到顺向层再走 5 mm」(2×2.5+5)， +# 所以 >5 mm 的逆向走线会被自动翻层，<5 mm 的短跳留在原层 —— 这就是想要的分界。 +# ⚠️ pcb1_route_sig.py 复用本引擎的 route_grid，下板同样生效。 +DIR_PREF = {L_TOP: 'H', L_BOT: 'V'} +DIR_PENALTY = 2.0 +# 斜步：第一版取 (1+DIR_PENALTY)/2 = 1.5（按分量计价的「一致」值），实测 15 根 POGO 顶层斜段 73 mm、 +# 水平 31 mm —— 45° 斜走等于同时吃到横竖两个分量，比「先横后竖」便宜，规则形同虚设。 +# 改成 DIAG_K = DIR_PENALTY × 1.2：斜走 1 mm 的代价 (2.4×√2 = 3.4) 略高于横 1 + 竖 2 = 3， +# 长斜段被拆成横竖（polish 再并成 L 形），只剩出线口和 45° 倒角那种短斜段。 +DIAG_K = DIR_PENALTY * 1.2 +# 过孔禁区 (x0, y0, x1, y1) mm。2026-09-07：`VBUS_EN2` 的过孔 (87.1, 70.2) 压在 Inner1 `VO2_P` 岛的颈 +# （`pcb2_pour.ISLANDS` 的 VO2 第一块矩形 x 80~87.3，是这块岛去 J31 的唯一通道）东沿上， +# 反焊盘把颈从 7.3 掐到 6.30（要 ≥ 7.0，4 A / ΔT 20 °C）。外层布线器不知道内层有岛，只能显式禁掉。 +# 范围比矩形各放 0.5（反焊盘半径 0.305 + 净距 0.2）。别的岛的颈目前 ≥ 7.2，没列。 +# 2026-09-07 第三十轮：VO2 的第二块矩形（Hub 北边横带 x 87~100.5 / y 75.5~83，高 7.5）也要禁： +# K1_PWR (97.6,78.4) / K1_VDN (97.0,79.2) / +3V3_HUB (98.7,77.7) 三个孔把这条带从 7.5 掐到 5.30。 +VIA_KEEPOUT = [(79.5, 67.1, 87.8, 83.5), (86.5, 75.0, 101.0, 83.5)] +TURN_COST = 0.30 # 拐一次弯折算成多少 mm（换来长直段，少几百条碎线） +BBOX_PAD = 10.0 # 每次连线的搜索窗口比两端包围盒大多少 +ASTAR_W = 1.3 # 加权 A*：h 乘这个数。放弃严格最优换速度 +MAX_CELLS = 3200000 # 单层格数超过这个才把栅格放粗一档（只有跨半块板的网络会碰到） + # 2026-09-07：1.2M 时全板窗口 (220×135) 在 0.1 栅格下 2.97M 格 -> 被放粗到 0.2， + # 排母 2.54 间距的 0.84 缝在 0.2 栅格上整片不可达；3.2M 让全板窗口保住 0.1。 + +W_ARR = 0.11 # 还在 BM24 焊盘阵列里那一段 +W_ESC = 0.20 # 刚出阵列 +W_SIG = 0.20 # 一般信号。**不是 0.25** —— Hub 的卫星圈是 1.2 mm 网格上的 + # 0402，缝只有 1.2 − 0.541 = 0.659 mm， + # 0.25 的线要 2×(0.20+0.125) = 0.65，量化余量一进去就过不去； + # 0.20 要 0.60，留 0.06 的余量，实测这一档才布得通。 +# XTAL1/2 必须 0.20：Hub 南侧竖井只有 2.16 mm，要并排过 4 根 +# （XTAL ×2 + UP_DP/DM ×2）。0.25 的话 0.2 净距下正好塞不进去 —— 实测布不通。 +# `+5V` 0.60（不是 0.80）：§25.10 重排逐针分配之后它是**10 针分散取电**， +# 每个入口只喂本站的 U2n + C70n、段电流 <= 0.6 A，0.60 mm 外层 1 oz 可载 ~2 A。 +# 0.80 在排母到服务带那条已经站满 EN/POGO 线的走廊里挤不过去（实测五处布不通）。 +WIDTH = {'+5V': 0.60, '+3V3_HUB': 0.35, 'XTAL1': 0.20, 'XTAL2': 0.20} +for _n in range(1, 6): + WIDTH['VBUS%d' % _n] = 0.50 + + +def width_of(net): + return WIDTH.get(net, W_SIG) + + +# ══════════════════ BM24 出线（手写，站内坐标 u/v）══════════════════ +# +# ⚠️ **2026-09-06（第十三轮）整段按 v5 重写。** 老的一版是 v3/v4 的坐标， +# v5 把 J7n 从 rot 180 改成 rot 0 又挪了位置，站内坐标整体差一个仿射映射 +# （`u' = u − 5.00`，`v' = 32.00 − v`，v 轴是**镜像**的）。 +# 照抄映射结果也不行 —— v 一镜像，「前排南侧那条缝」跑到了北侧， +# 而北侧现在站着 R76n/R77n；净距必须拿 v5 的实际障碍重算。下面全部是实测值。 +# +# 焊盘几何（`fp_bm24.py`，`--dump` 回读逐站核过，五个站完全同构）： +# 后排（奇数脚，**全是 GND**）v = 33.940，u 48.30~56.70 +# 中间两个大脚 v = 35.000，pin51(VBUS) u 46.47 / pin52(GND) u 58.53 +# 前排（偶数脚） v = 36.060，u 48.30~56.70 +# 两排都是 hh = 0.24；信号脚 hw = 0.0902，脚距 0.35 ⇒ 相邻焊盘边到边 0.1696 +J7_BACK_V, J7_MID_V, J7_FRONT_V = 33.940, 35.000, 36.060 +J7_PAD_HH = 0.24 +# 出线换挡的 v：离焊盘外沿 0.35，0.20 的线到相邻脚的焊盘角还有余量 +J7_FRONT_ESC = J7_FRONT_V + J7_PAD_HH + 0.35 # 36.65，往**外**（+v） +J7_BACK_ESC = J7_BACK_V - J7_PAD_HH - 0.35 # 33.35，往**外**（−v） +J7_FRONT_IN = J7_FRONT_V - J7_PAD_HH - 0.35 # 35.47，前排往**内**（进中央通道） + +# GND 脚的 u（`--check` 会逐站断言） +J7_GND_FRONT = [48.30, 49.35, 50.05, 50.75, 52.15] # pin 2/8/12/16/24 +J7_GND_BACK = [48.30, 51.45, 52.15, 53.20, 54.60, 55.30, 56.35] # pin 1/19/23/29/37/41/47 +J7_GND_BIG = 58.53 # pin 52，0.49×0.76 大焊盘 +J7_THERM_U, J7_CC1_U = 50.40, 51.80 # pin 14 口温 / pin 22 CC1 + +# ══ v5 的车道分配（和 v4 换了个方向，理由在下面）══ +# +# ┌ 前排外侧 v > 36.30 ── **只给 THERM / CC1**（R76n/R77n 就在正北 v 38.0） +# │ 中央通道 v ∈ [34.18, 35.82]，净高 1.64 ── **前排 5 个 GND 的梳子** +# └ 后排外侧 v < 33.70 ── **后排 7 个 GND 的梳子**，一路空到 v 26，最宽敞 +# +# 为什么和 v4 相反：v5 的**后排 25 个脚全是 GND**（没有信号脚要往外挤）， +# 而 THERM(pin14)/CC1(pin22) 都在前排、目标 R76n/R77n 也在前排外侧 —— +# 让它们各走各的最短路，中央通道就整条空出来给前排 GND，不再有 +# v4 那个「东行车道被竖着穿过通道的 GND 线切断」的死结。 +# +# 中央通道梳子 v = 35.00（正中）：到两排焊盘内沿各 0.82 +# 0.30 的线：0.82 − 0.15 = 0.67 ✔ 过孔：0.82 − 0.305 = 0.515 ✔（要 0.50） +# ⚠️ 梳子只走到 u 52.15（最东那个前排 GND 脚），离 pin52 焊盘西沿 58.285 还有 6 mm， +# 所以通道里这条梳子和 pin51/pin52 两个大脚互不相干。 +J7_MID_COMB = J7_MID_V # 35.00 +J7_MID_VIA_U = [48.30, 49.35, 50.75, 52.15] # 相邻间距 1.05/1.40/1.40 >= 0.81 ✔（跳过 50.05） +# +# 后排外侧梳子 v = 33.10：到后排焊盘外沿 33.70 有 0.60 +# 0.30 的线余 0.45 ✔ 过孔余 0.295 ✔（要 0.20；离焊盘 0.60 − 0.305 = 0.295） +# ⚠️ 这一带在**尾插排线车道 `TAIL_LANE` 里**（u 44.6~62.6 / v −1.2~36.3）。 +# 车道的约束是「不放元件」，走线和过孔是允许的（排线平贴着盖过去）。 +J7_BACK_COMB = 33.10 +J7_BACK_VIA_U = [48.30, 52.15, 53.20, 54.60, 56.35] # 间距 3.85/1.05/1.40/1.75 >= 0.81 ✔ +# +# pin52（GND 大焊盘，u 58.53 / v 35.00）：往**东**平着出去打孔， +# 离 J7n 最东那列焊盘 (u 56.79) 2.8、离手机定位柱 PnH3 (u 61.90, v 33.70, Ø2.5) 1.05 ✔ +J7_PIN52_VIA_U = 59.60 + +W_COMB = 0.30 +W_LANE = 0.20 + +# ── THERM / CC1：都往前排外侧出，THERM 走顶层跳过 CC1 ── +# +# 两个脚一个要往东（THERM → R77n.1 u 54.367）、一个要往北（CC1 → R76n.1 u 51.800）， +# **在 u ≈ 51.8 必然交叉**，同层无解。CC1 是最短的那根，让它全程底层直上； +# THERM 打两个孔从顶层跨过去。 +# 西孔 (50.95, 37.20)：离 `*_DPJ` 的换层孔 (50.00, 37.00) **0.97 ≥ 0.81**（孔到孔）； +# 离 J7n.16/18 焊盘 0.86；离 R76n.1 焊盘框 0.78 ✔ +# 东孔 (54.37, 37.20)：离 J7n.38 焊盘 0.90；R77n.1 是同网，不设限 ✔ +# 顶层那一段 v = 37.20：顶层在 J7n 这一带**一根线都没有**（`*_DPJ` 的顶层小跳线在 u ≤ 50.0） +# R76n 的中心特意取 52.233，好让 pin1 正落在 u 51.800 = J7n.22 正北 ⇒ CC1 是一根直线。 +# ⚠️ THERM 出阵列后**第一次拐弯的 v 只有 0.053 mm 的窗口**，而且那一段必须一直保持 0.11： +# 往下：离前排焊盘外沿 36.30 要 w/2 + 0.20 ⇒ v >= 36.555 +# 往上：离 `*_DPJ` 的换层孔 (50.00, 37.00) 要 0.305 + w/2 + 0.20 = 0.560， +# 而它在 u 上只差 0.40 ⇒ |v − 37.00| >= 0.392 ⇒ v <= 36.608 +# 取窗口正中 36.58（上下各余 0.027）。**换成 0.15 的线窗口只剩 0.005，0.20 直接无解** —— +# 2026-09-06 第一版写 0.20 / 拐点 36.65，五个站一起报「线-过孔 净距 0.127」。 +J7_THERM_TURN_V = 36.58 +J7_THERM_VIA = [(50.80, 37.30), (54.367, 37.30)] +J7_THERM_KINK = (50.80, 36.98) # 45° 斜段的终点，之后竖着上到换层孔 +J7_THERM_LANE_V = 37.30 +J7_R76_PIN1_U, J7_R77_PIN1_U = 51.800, 54.367 +J7_R_PAD_V = 38.000 # R76n/R77n 焊盘中心 v（`--check` 会核） +J7_R_ENTER_V = 37.90 # 进焊盘的落点（焊盘 v 37.730~38.270） + + +def _stub(u, v_pad, v_esc, w_out=W_ESC): + u"""BM24 一个脚的直出段（站内坐标）：焊盘 -> 阵列外。""" + return [(u, v_pad, L_TOP, W_ARR), (u, v_esc, L_TOP, w_out)] + + +def bm24_stub(n, u, v_pad, v_esc, w_out=W_ESC): + u"""同上，映射到第 n 站的板坐标。""" + out = [] + for u_, v_, lay, ww in _stub(u, v_pad, v_esc, w_out): + bx, by, _ = to_board(n, u_, v_, 0) + out.append((round(bx, 3), round(by, 3), lay, ww)) + return out + + +# ══════════════════ 板框 ══════════════════ +_CORNERS = ((CORNER_R, CORNER_R), (BW - CORNER_R, CORNER_R), + (CORNER_R, BH - CORNER_R), (BW - CORNER_R, BH - CORNER_R)) + + +def board_mask(XX, YY, m=EDGE): + u"""格心在板内（含 R5 圆角、内缩 m）的布尔数组。""" + ok = (XX >= m) & (XX <= BW - m) & (YY >= m) & (YY <= BH - m) + for cx, cy in _CORNERS: + sx = 1.0 if cx < BW / 2 else -1.0 + sy = 1.0 if cy < BH / 2 else -1.0 + inc = ((XX - cx) * sx < 0) & ((YY - cy) * sy < 0) + ok &= ~(inc & (np.hypot(XX - cx, YY - cy) > CORNER_R - m)) + return ok + + +# ══════════════════ 形状（障碍 / 本网铜都用这一套）══════════════════ +def sh_rect(x, y, hw, hh, layers): + return ('rect', x, y, hw, hh, layers) + + +def sh_via(x, y, r=VIA_R): + return ('via', x, y, r, 0, (L_TOP, L_BOT)) + + +def sh_seg(x0, y0, x1, y1, w, lay): + return ('seg', x0, y0, x1, y1, w / 2.0, (lay,)) + + +def shapes_of(pads, vias, lines): + u"""把 geom() 的三张表变成障碍表：`[(形状, 网络), ...]`。 + + ⚠️ **网络必须跟着形状走**：布某个网络时它自己的铜不能算障碍， + 否则连焊盘都出不来（第一版就是漏了这条，25 个种子格一个邻居都扩不出去）。 + """ + out = [] + for p in pads: + lay = (L_TOP, L_BOT) if p['lay'] == 12 else (p['lay'],) + out.append((sh_rect(p['x'], p['y'], p['hw'], p['hh'], lay), p['net'])) + for v in vias: + out.append((sh_via(v['x'], v['y'], v['r']), v['net'])) + for l in lines: + out.append((sh_seg(l['x0'], l['y0'], l['x1'], l['y1'], l['w'], l['lay']), l['net'])) + return out + + +# ══════════════════ 栅格场 ══════════════════ +class Field(object): + u"""一个搜索窗口里的两层障碍距离场。 + + `edt[L][j, i]` = 该格心到**最近的异网铜**的距离（mm，含量化误差 QERR）。 + 判据统一是 `edt >= 净距 + 半线宽 + QERR`。 + """ + + #: 搜索窗口外面还要多留一圈**只标障碍、不许走线**的边（mm）。见 __init__ 里的注释。 + RIM = 1.2 + + def __init__(self, obstacles, bbox, skip_net=None, grid=GRID): + x0, y0, x1, y1 = bbox + self.g = grid + self.qerr = grid * math.sqrt(2) / 2 + # ⚠️ **窗口边上必须留一圈墙。** 障碍是裁到窗口里再栅格化的， + # 完全落在窗口外的铜一格都不标 —— 于是贴着窗口边走的线看不见它。 + # 2026-09-06 实测：`SCL` 的搜索窗口从 x=44.02 起，J31.6 的焊盘框 + # (42.10~43.80) 整个在窗外，布线器就在 (44.10, 67.40) 打了个孔， + # 离那个焊盘只有 0.134 —— 栅格判据全过，`check()` 才报出来。 + # 做法：数组往外扩 RIM，障碍照标，**再把外面这一圈整体标成占用**。 + # 可走的区域和原来一模一样，但现在看得见窗外 RIM 以内的铜。 + rim = self.RIM + x0 -= rim; y0 -= rim; x1 += rim; y1 += rim + self.x0 = math.floor(x0 / grid) * grid + self.y0 = math.floor(y0 / grid) * grid + self.nx = int(round((x1 - self.x0) / grid)) + 2 + self.ny = int(round((y1 - self.y0) / grid)) + 2 + # ⚠️ **层集合不能写死 (L_TOP, L_BOT)**。下板从 2026-09-06 起在 **Inner2(16)** + # 上有真走线了（`pcb1_i2c_l3.py` 的 I²C 干线），障碍表里就会出现 layer 16 —— + # 写死两层的话这里直接 `KeyError: 16`；就算滤掉，**新过孔也不会对内层那些线 + # 做净距判断**（`viafree` 是 min(edt[TOP], edt[BOT])），孔会直接压在内层干线上。 + # 这里按障碍表里真正出现过的层建数组；只有 1/2 层时行为和以前一模一样。 + self.lays = sorted(set([L_TOP, L_BOT]) + | set(L for s, _n in obstacles for L in s[-1])) + occ = {L: np.zeros((self.ny, self.nx), bool) for L in self.lays} + # ⚠️ 障碍要**先胀 QERR 再栅格化**，见 `_mark` 的注释。 + for s, net in obstacles: + if net == skip_net: + continue + for L in s[-1]: + self._mark(occ[L], s, grow=self.qerr) + # 板框外一律不许有铜 + xs = self.x0 + np.arange(self.nx) * grid + ys = self.y0 + np.arange(self.ny) * grid + XX, YY = np.meshgrid(xs, ys) + out = ~board_mask(XX, YY) + # 外圈那一圈墙（障碍已经标完了，这里只是禁止走线） + nb = max(1, int(round(rim / grid))) + wall = np.zeros((self.ny, self.nx), bool) + wall[:nb, :] = True; wall[-nb:, :] = True + wall[:, :nb] = True; wall[:, -nb:] = True + out |= wall + for L in self.lays: + occ[L] |= out + self.occ = occ + self.edt = {L: ndimage.distance_transform_edt(~occ[L], sampling=grid).astype(np.float32) + for L in self.lays} + # 过孔是通孔 ⇒ **每一层**都要让开（含 Inner2 上的真走线） + self.viafree = np.minimum.reduce([self.edt[L] for L in self.lays]) + # ⚠️ **钻孔间距不分网络**。铜可以重叠，孔不行 —— 规则 otherClearance.hole2Hole = 0.30。 + # `viafree` 是「到**异网**铜的距离」，同网的过孔在它眼里根本不存在， + # 于是布线器会紧挨着 `pcb2_dp_long` 已经打好的孔再打一个： + # 2026-09-06 实测 (92.500, 70.000) 与 (92.400, 70.500) 中心只隔 0.510， + # DRC 报「钻孔 到 钻孔 8.1mil，应 >= 11.8mil」，而净距校核一声不吭。 + occh = np.zeros((self.ny, self.nx), bool) + for s, _net in obstacles: + if s[0] == 'via': + self._mark(occh, ('via', s[1], s[2], VIA_H / 2.0, 0, s[5]), grow=self.qerr) + occh |= out + self.holefree = ndimage.distance_transform_edt( + ~occh, sampling=grid).astype(np.float32) + + # ── 栅格化 ── + def _idx(self, x, y): + return (int(round((x - self.x0) / self.g)), int(round((y - self.y0) / self.g))) + + def _win(self, xa, xb, ya, yb): + i0 = max(0, int(math.ceil((xa - self.x0) / self.g))) + i1 = min(self.nx - 1, int(math.floor((xb - self.x0) / self.g))) + j0 = max(0, int(math.ceil((ya - self.y0) / self.g))) + j1 = min(self.ny - 1, int(math.floor((yb - self.y0) / self.g))) + return i0, i1, j0, j1 + + def _mark(self, mask, s, grow=0.0): + u"""把一个形状打进布尔栅格。 + + ⚠️ **`grow` 不是保险丝，是判据的一部分。** 只标"格心落在铜里"的格时， + 铜的边界到最近的被标记格心可以差到将近一整格（实测：一个 Ø0.61 的过孔 + 边缘在 x=52.781，最近的格心在 52.7，差 0.081 > √2/2·0.1）， + 于是 `edt` 会**高估** 0.08 mm，净距校核就在下发前一刻才炸。 + 把障碍先胀 `QERR = g·√2/2` 再栅格化，任何铜边界点周围 + 半径 QERR 内一定有被标记的格 ⇒ `真实净距 >= edt − QERR` 严格成立， + 判据 `edt >= 净距 + 半线宽 + QERR` 才真的是充分条件。 + """ + k = s[0] + if k == 'rect': + _, x, y, hw, hh, _ = s + hw, hh = hw + grow, hh + grow + i0, i1, j0, j1 = self._win(x - hw, x + hw, y - hh, y + hh) + if i0 <= i1 and j0 <= j1: + mask[j0:j1 + 1, i0:i1 + 1] = True + return + if k == 'via': + _, x, y, r, _, _ = s + r = r + grow + i0, i1, j0, j1 = self._win(x - r, x + r, y - r, y + r) + if i0 > i1 or j0 > j1: + return + xs = self.x0 + np.arange(i0, i1 + 1) * self.g + ys = self.y0 + np.arange(j0, j1 + 1) * self.g + XX, YY = np.meshgrid(xs, ys) + mask[j0:j1 + 1, i0:i1 + 1] |= ((XX - x) ** 2 + (YY - y) ** 2) <= r * r + return + _, xa, ya, xb, yb, h, _ = s + h = h + grow + i0, i1, j0, j1 = self._win(min(xa, xb) - h, max(xa, xb) + h, + min(ya, yb) - h, max(ya, yb) + h) + if i0 > i1 or j0 > j1: + return + xs = self.x0 + np.arange(i0, i1 + 1) * self.g + ys = self.y0 + np.arange(j0, j1 + 1) * self.g + XX, YY = np.meshgrid(xs, ys) + dx, dy = xb - xa, yb - ya + L2 = dx * dx + dy * dy + if L2 < 1e-12: + d2 = (XX - xa) ** 2 + (YY - ya) ** 2 + else: + t = np.clip(((XX - xa) * dx + (YY - ya) * dy) / L2, 0.0, 1.0) + d2 = (XX - (xa + t * dx)) ** 2 + (YY - (ya + t * dy)) ** 2 + mask[j0:j1 + 1, i0:i1 + 1] |= d2 <= h * h + + def mask_of(self, shapes): + m = {L: np.zeros((self.ny, self.nx), bool) for L in self.lays} + for s in shapes: + for L in s[-1]: + self._mark(m[L], s) + return m + + # ── 判据 ── + # `relax` = **本网自己的焊盘**所占的格。焊盘里本来就有铜， + # 线从焊盘中心出来的那一小段落在焊盘内部，不该拿净距去卡它 + # （0402 的两个焊盘只隔 0.5 mm，卡下去等于每个器件都出不了线）。 + # 只放宽焊盘，不放宽本网的**导线** —— 导线本身是合法的，它所在的格 edt 也够。 + def set_relax(self, shapes): + self.relax = self.mask_of(shapes) + + def free(self, lay, w): + f = self.edt[lay] >= CLR + w / 2.0 + self.qerr + if getattr(self, 'relax', None) is not None: + f = f | self.relax[lay] + return f + + def via_ok(self): + ok = ((self.viafree >= CLR + VIA_R + self.qerr) + & (self.holefree >= VIA_H / 2.0 + HOLE_CLR + self.qerr)) + # 过孔禁区（Inner1 电源岛的颈）：外层布线器看不见内层的岛，一个过孔的反焊盘就能把 4 A 的颈掐窄。 + if VIA_KEEPOUT: + xs = self.x0 + np.arange(self.nx) * self.g + ys = self.y0 + np.arange(self.ny) * self.g + for x0, y0, x1, y1 in VIA_KEEPOUT: + ok &= ~(((xs >= x0) & (xs <= x1))[None, :] & ((ys >= y0) & (ys <= y1))[:, None]) + return ok + + def clear_seg(self, x0, y0, x1, y1, lay, w): + u"""一段任意角度的线是否安全（沿线采样，EDT 是 1-Lipschitz 所以可加采样余量）。""" + need = CLR + w / 2.0 + self.qerr + L = math.hypot(x1 - x0, y1 - y0) + n = max(2, int(L / (self.g / 2.0)) + 1) + step = L / (n - 1) if n > 1 else 0.0 + need += step / 2.0 + rl = getattr(self, 'relax', None) + for k in range(n): + t = k / float(n - 1) if n > 1 else 0.0 + i, j = self._idx(x0 + t * (x1 - x0), y0 + t * (y1 - y0)) + if not (0 <= i < self.nx and 0 <= j < self.ny): + return False + if self.edt[lay][j, i] < need and not (rl is not None and rl[lay][j, i]): + return False + return True + + +# ══════════════════ A* ══════════════════ +DIRS = [(1, 0), (1, 1), (0, 1), (-1, 1), (-1, 0), (-1, -1), (0, -1), (1, -1)] + + +def _edges(ok, dx, dy, nx, ny, base): + u"""某一层上、沿 (dx, dy) 这个方向的所有合法走步 -> (起点索引, 终点索引)。 + + 斜着走要**额外**要求两个正交邻格也是通的 —— 否则线会从两个障碍的夹角里"钻"过去。 + """ + xs0, xs1 = max(0, -dx), nx - max(0, dx) + ys0, ys1 = max(0, -dy), ny - max(0, dy) + if xs1 <= xs0 or ys1 <= ys0: + e = np.empty(0, np.int64) + return e, e + m = ok[ys0:ys1, xs0:xs1] & ok[ys0 + dy:ys1 + dy, xs0 + dx:xs1 + dx] + if dx and dy: + m = m & ok[ys0:ys1, xs0 + dx:xs1 + dx] & ok[ys0 + dy:ys1 + dy, xs0:xs1] + jj, ii = np.nonzero(m) + jj = jj.astype(np.int64) + ys0 + ii = ii.astype(np.int64) + xs0 + return base + jj * nx + ii, base + (jj + dy) * nx + (ii + dx) + + +def route_grid(f, src, tgt, w): + u"""多源多汇最短路。`src`/`tgt` 是 {层: 布尔数组}。返回 [(i, j, 层), ...] 或 None。 + + 代价 = 路程(mm) + 每次换层 `VIA_COST`。 + + ## 为什么是 scipy 的 Dijkstra，不是自己写的 A* + + 第一版是纯 Python 的加权 A*（还带拐弯惩罚）。**跨半块板的网络跑不动** —— + `VBUS_UP`（J23 → Hub，95 mm）在 0.1 mm 栅格上是 140 万个节点， + 两分钟没跑完，放粗到 0.2 mm 又因为净距判据跟着变严而布不通。 + 改成把整个栅格建成稀疏图交给 `scipy.sparse.csgraph.dijkstra`（C 实现、多源、 + 带前驱），同一个网络降到秒级。 + + 代价是**丢了拐弯惩罚**（Dijkstra 表达不了"到达方向"）， + 最短路会退化成楼梯。所以 `polish()` 必须做「最远可视 L 形合并」把楼梯收回来 —— + 这两件事是配套的，只改一半会得到几百条碎线。 + """ + from scipy.sparse import coo_matrix + from scipy.sparse.csgraph import dijkstra + + nx, ny, g = f.nx, f.ny, f.g + LAY = [L_TOP, L_BOT] + ok = [f.free(L, w) for L in LAY] + N = nx * ny + rows, cols, vals = [], [], [] + for li in (0, 1): + pref = DIR_PREF.get(LAY[li]) + for dx, dy in ((1, 0), (0, 1), (1, 1), (1, -1)): + fr, to = _edges(ok[li], dx, dy, nx, ny, li * N) + if len(fr): + # H/V 分层：顶层纵向步 / 底层横向步按 DIR_PENALTY 计价，斜步取中间值 + if dx and dy: + k = DIAG_K if pref else 1.0 + elif (pref == 'H' and dy) or (pref == 'V' and dx): + k = DIR_PENALTY + else: + k = 1.0 + rows.append(fr) + cols.append(to) + vals.append(np.full(len(fr), g * k * (math.sqrt(2) if dx and dy else 1.0), + np.float32)) + vm = f.via_ok() & ok[0] & ok[1] + jj, ii = np.nonzero(vm) + if len(jj): + idx = jj.astype(np.int64) * nx + ii.astype(np.int64) + rows.append(idx) + cols.append(idx + N) + vals.append(np.full(len(idx), VIA_COST, np.float32)) + if not rows: + return None + G = coo_matrix((np.concatenate(vals), + (np.concatenate(rows), np.concatenate(cols))), + shape=(2 * N, 2 * N)).tocsr() + + def flat(mask): + out = [] + for li in (0, 1): + jj, ii = np.nonzero(mask[LAY[li]] & ok[li]) + out.append(jj.astype(np.int64) * nx + ii.astype(np.int64) + li * N) + return np.concatenate(out) + + si, ti = flat(src), flat(tgt) + if not len(si) or not len(ti): + return None + D, pred, _srcs = dijkstra(G, directed=False, indices=si, min_only=True, + return_predecessors=True) + d = D[ti] + k = int(np.argmin(d)) + if not np.isfinite(d[k]): + return None + out = [] + idx = int(ti[k]) + seen = set() + while idx >= 0 and idx not in seen: + seen.add(idx) + li, r = divmod(idx, N) + j, i = divmod(r, nx) + out.append((i, j, LAY[li])) + idx = int(pred[idx]) + out.reverse() + return out + + +# ══════════════════ 路径整形 ══════════════════ +def _runs(cells): + u"""8 邻域格路 -> 顶点表（同层的共线段合并；换层处断开）。""" + pts = [cells[0]] + for k in range(1, len(cells) - 1): + i0, j0, l0 = cells[k - 1] + i1, j1, l1 = cells[k] + i2, j2, l2 = cells[k + 1] + if l0 != l1 or l1 != l2: + pts.append(cells[k]) + continue + if (i1 - i0, j1 - j0) != (i2 - i1, j2 - j1): + pts.append(cells[k]) + pts.append(cells[-1]) + return pts + + +def _l_shapes(a, b): + u"""A->B 的 45°/90° 两段折线（两种拐法）；本来就是 8 方向的直接返回一段。""" + (x0, y0), (x1, y1) = a, b + dx, dy = x1 - x0, y1 - y0 + if abs(dx) < 1e-9 or abs(dy) < 1e-9 or abs(abs(dx) - abs(dy)) < 1e-9: + return [[a, b]] + m = min(abs(dx), abs(dy)) + sx = math.copysign(1.0, dx) + sy = math.copysign(1.0, dy) + return [[a, (x0 + sx * m, y0 + sy * m), b], # 先斜后正 + [a, (x1 - sx * m, y1 - sy * m), b]] # 先正后斜 + + +def polish(f, pts, w): + u"""顶点表 -> 少而长的 45°/90° 段。逐层做，换层点原样保留。""" + out = [] + seg_start = 0 + for k in range(len(pts)): + last = (k == len(pts) - 1) + if not last and pts[k + 1][2] == pts[k][2]: + continue + chunk = pts[seg_start:k + 1] + lay = chunk[0][2] + xy = [(f.x0 + i * f.g, f.y0 + j * f.g) for i, j, _ in chunk] + out.append((lay, _polish_one(f, xy, lay, w))) + seg_start = k + 1 + return out + + +def _polish_one(f, xy, lay, w): + if len(xy) <= 2: + return xy + def try_j(i, j): + for cand in _l_shapes(xy[i], xy[j]): + if all(f.clear_seg(a[0], a[1], b[0], b[1], lay, w) + for a, b in zip(cand, cand[1:])): + return cand + return None + + res = [xy[0]] + i = 0 + n = len(xy) + while i < n - 1: + # 先指数外推找到"最后一个还通的 j"的量级，再二分收敛。 + # 逐个从远往近试是 O(n²) 次几何校核，长线（上千个格）会卡住。 + lo, best = i + 1, try_j(i, i + 1) + step = 1 + while lo + step <= n - 1: + c = try_j(i, lo + step) + if c is None: + break + lo, best = lo + step, c + step *= 2 + hi = min(n - 1, lo + step) + while lo + 1 < hi: + mid = (lo + hi) // 2 + c = try_j(i, mid) + if c is None: + hi = mid + else: + lo, best = mid, c + if best is None: + res.append(xy[i + 1]) + i += 1 + continue + res.extend(best[1:]) + i = lo + # 去掉共线冗余点 + out = [res[0]] + for k in range(1, len(res) - 1): + ax, ay = out[-1] + bx, by = res[k] + cx, cy = res[k + 1] + if abs((bx - ax) * (cy - by) - (by - ay) * (cx - bx)) > 1e-9: + out.append(res[k]) + out.append(res[-1]) + return out + + +# ══════════════════ 网络布线 ══════════════════ +class Comp(object): + u"""一个网络里已经连通的一坨铜。 + + `center` 只在"这一坨就是一个焊盘"时非空，值是**焊盘中心**。 + ⚠️ 这一条不是锦上添花：`half()` 给圆焊盘返回的是**外接矩形**， + 路径若停在矩形角上（Ø1.7 的排母脚差 0.32 mm）实际上根本没搭到铜。 + 所以单焊盘的起终点一律钉在圆心，A* 的种子/目标也只取圆心那一格。 + """ + + def __init__(self, shapes, anchor, center=None, layers=None): + self.shapes = list(shapes) + self.anchor = anchor # (x, y) 只用来算"离谁最近" + self.center = center + self.layers = layers + + def merge(self, other, extra): + self.shapes += other.shapes + extra + self.center = None + self.layers = None + + +FINE_PAD = 0.31 # 焊盘短边半长 < 这个数就算"细间距"，出线要先直出 +STUB_EXT = (0.30, 0.20, 0.12) # 直出到焊盘外多少（依次退让） +_CENTROID = {} + + +def _centroid(ref, pads_all): + if ref not in _CENTROID: + ps = [p for p in pads_all if p['ref'] == ref] + _CENTROID[ref] = (sum(p['x'] for p in ps) / len(ps), + sum(p['y'] for p in ps) / len(ps)) if ps else None + return _CENTROID[ref] + + +def clear_exact(x0, y0, x1, y1, lay, w, net, obstacles): + u"""一段线到**异网铜**的真实最小净距（不走栅格，逐个形状精确算）。""" + h = w / 2.0 + best = 1e9 + a, b = (x0, y0), (x1, y1) + for s, n in obstacles: + if n == net or lay not in s[-1]: + continue + if s[0] == 'rect': + d = seg_rect(a, b, s[1], s[2], s[3], s[4]) - h + elif s[0] == 'via': + d = seg_pt(x0, y0, x1, y1, s[1], s[2]) - s[3] - h + else: + d = seg_seg(a, b, (s[1], s[2]), (s[3], s[4])) - s[5] - h + if d < best: + best = d + return best + + +ELONGATED = 1.3 # 长短边之比超过这个，就认为焊盘"有方向" + + +def entry_stub(q, pads_all, obstacles, net, w, all_cands=False): + u"""细间距焊盘的**直出段**：从焊盘中心直着走出焊盘外一小截，路由器从这一截接手。 + + 不这么做的话最短路会从焊盘的**侧面**或**角上**离开： + QFN(0.5 脚距) 和 0402 的邻脚就在 0.2~0.4 mm 外，一出来就违规。 + 上一版 `XTAL1` 进 U32.61 是这么卡死的（布不通）， + `+3V3_HUB` 进 U32.64 更糟 —— 它从**西侧**横着挤进去，离 U32.63 只剩 0.10 mm。 + + ## 方向怎么定（两条规则，缺一不可） + + 1. **焊盘明显是长条的（长短边 ≥ 1.3）⇒ 沿长轴出**。这是封装设计者的意思： + 长轴指向元件外面。QFN 南边一排是 0.30×0.851，J23 的信号脚是 1.30×0.30。 + 2. **接近方的（0402 焊盘 0.50×0.541、晶振 1.40×1.20）⇒ 沿"背离元件形心"那根轴出**。 + + 只按第 2 条会错得很难看：`J23.A5` 上下各有一个焊盘、左右空着， + 而形心被四个屏蔽脚拉到东边 ⇒ 判成"往南出"，**正好撞在 B8 焊盘上**， + 于是没有出线段，两个 2 mm 远的焊盘反而布不通。 + """ + if q['lay'] == 12 or min(q['hw'], q['hh']) >= FINE_PAD: + return [] if all_cands else None + cen = _centroid(q['ref'], pads_all) + if cen is None: + return [] if all_cands else None + dx, dy = q['x'] - cen[0], q['y'] - cen[1] + if q['hw'] >= q['hh'] * ELONGATED: + axes = ('x', 'y') + elif q['hh'] >= q['hw'] * ELONGATED: + axes = ('y', 'x') + else: + axes = ('x', 'y') if abs(dx) >= abs(dy) else ('y', 'x') + # 候选：主轴背离形心 -> 次轴背离形心 -> 主轴朝向形心（万不得已） + cands = [] + for ax in axes: + d = dx if ax == 'x' else dy + cands.append((ax, 1.0 if d >= 0 else -1.0)) + cands.append((axes[0], -cands[0][1])) + ws = min(w, 2 * min(q['hw'], q['hh'])) + out = [] + for ax, sgn in cands: + for ext in STUB_EXT: + if ax == 'x': + end = (q['x'] + sgn * (q['hw'] + ext), q['y']) + else: + end = (q['x'], q['y'] + sgn * (q['hh'] + ext)) + if clear_exact(q['x'], q['y'], end[0], end[1], q['lay'], ws, net, obstacles) >= CLR: + out.append((end, ws)) + break # 同一个方向只留最长的那一档 + if not out: + return [] if all_cands else None + return out if all_cands else out[0] + + +def plan_stubs(order, pads_all, obstacles, pre_pads): + u"""**先给所有网络的所有焊盘留好出线段，再开始布线。** + + 这一步不是优化，是必需的。第一版是"轮到哪个网络才现画它的出线段"， + 于是先布的网络会把后布的网络**出焊盘的那 0.6 mm 占掉**： + + · `VBUS2` 抄近路斜穿 U25 东侧 ⇒ `+5V` 出 U25.1 只剩 −0.02 mm， + 出线段只好掉头往**西**（钻进器件内部），整条 `+5V` 就此布不通； + · `+3V3_HUB` 从西边竖着切进 U42.5 ⇒ 隔壁 U42.6 的 `EDL_EN2` 出不来， + 而这两个焊盘只隔 0.95 mm。 + + 先把出线段全部落地当障碍，等于给每个焊盘**预留了逃逸通道**， + 这是布线器的常规做法（escape routing 先行）。 + """ + stubs, alts = {}, {} + for net in order: + w = width_of(net) + for q in pads_all: + key = (q['ref'], q['num']) + if q['net'] != net or key in pre_pads: + continue + cand = entry_stub(q, pads_all, obstacles, net, w, all_cands=True) + if not cand: + continue + alts[key] = cand + end, ws = cand[0] + stubs[key] = (end, ws) + # 只**预留**首选方向。备选方向不占位 —— 它们只在首选走不通时才拿出来试， + # 那时候本来就是"能捡到什么算什么"。 + obstacles.append((sh_seg(q['x'], q['y'], end[0], end[1], ws, q['lay']), net)) + return stubs, alts + + +def route_net(net, pads_all, obstacles, w=None, pre=None, verbose=True, + stubs=None, alts=None): + u"""把一个网络布通。返回 [路径, ...]（每条是 `expand()` 认的点表）。 + + `pre` 是手写前置段（BM24 出线 / GND 梳子），它们**先算进本网铜**， + 然后端点参与后面的最小生成树。 + `stubs` 是 `plan_stubs()` 预留好的出线段（已经在障碍表里了，这里只取用）。 + `alts` 是同一个焊盘的**备选出线方向**：首选方向布不通时换一个再试。 + + ⚠️ 为什么需要备选：出线方向是按「背离元件形心」定的，那只是个启发式。 + `R709.1`（VBUS_UP）在 Hub 卫星圈 A/B 两圈之间，背离形心 = **朝东**， + 正好扎进 A/B 圈之间那条 0.268 mm 的死胡同 —— 出线段本身是合法的（只有 0.59 mm 长）， + 所以 `plan_stubs` 挑中了它，然后整个网络就再也接不上这个焊盘。 + 实测：只布这一个网络、整块板别的线都不存在，照样布不通 ⇒ 不是拥挤，是方向选错了。 + """ + w = w or width_of(net) + paths = list(pre or []) + comps = [] + used = set() + for p in pre or []: + shp = [] + for x0, y0, x1, y1, lay, ww in expand(p)[0]: + shp.append(sh_seg(x0, y0, x1, y1, ww, lay)) + for x, y in expand(p)[1]: + shp.append(sh_via(x, y)) + # ⚠️ 手写前置段也必须进障碍表。漏了这一条的后果是**后面的网络看不见它们** —— + # BM24 那五组车道是最先落的铜，`POGO2_PWR` 却从中间穿了过去， + # 而且只有最后一步 `check()` 才报出来（−0.200，实打实压在一起）。 + obstacles.extend((sp, net) for sp in shp) + for q in pads_all: + if q['net'] != net: + continue + if seg_rect((p[0][0], p[0][1]), (p[0][0], p[0][1]), + q['x'], q['y'], q['hw'], q['hh']) < 1e-6: + used.add((q['ref'], q['num'])) + comps.append(Comp(shp, (p[-1][0], p[-1][1]))) + for q in pads_all: + if q['net'] != net or (q['ref'], q['num']) in used: + continue + lay = (L_TOP, L_BOT) if q['lay'] == 12 else (q['lay'],) + rect = sh_rect(q['x'], q['y'], q['hw'], q['hh'], lay) + st = (stubs or {}).get((q['ref'], q['num'])) + if st is None: + comps.append(Comp([rect], (q['x'], q['y']), center=(q['x'], q['y']), layers=lay)) + continue + end, ws = st + paths.append([(round(q['x'], 4), round(q['y'], 4), q['lay'], ws), + (round(end[0], 4), round(end[1], 4), q['lay'], ws)]) + seg = sh_seg(q['x'], q['y'], end[0], end[1], ws, q['lay']) + c = Comp([rect, seg], end, center=end, layers=lay) + c.pad, c.rect, c.stub_i = q, rect, len(paths) - 1 # 换出线方向时要用 + c.stub_alts = [a for a in (alts or {}).get((q['ref'], q['num']), [])[1:]] + comps.append(c) + if len(comps) < 2: + return paths + + # `relax`（允许贴着走的自网焊盘）**只放没有出线段的那些**。 + # 有出线段的焊盘已经有了合法的进出口，再把整个焊盘放开的话， + # 最短路会**从焊盘的另一头钻进来**：实测 `+3V3_HUB` 就这么顺着 R715.2 的 + # 焊盘北沿爬进去，那一小段铜离 R715.1 只有 0.175 mm（0402 自己两个焊盘才隔 0.30）。 + relax = [sh_rect(q['x'], q['y'], q['hw'], q['hh'], + (L_TOP, L_BOT) if q['lay'] == 12 else (q['lay'],)) + for q in pads_all + if q['net'] == net and (q['ref'], q['num']) not in (stubs or {})] + + # 生成树用 **Prim**：每一步挑「离**已连上的整坨**最近的那个」。 + # 第一版是"离上一个接上的点最近"（最近邻链），在 33 个焊盘的 `+3V3_HUB` 上 + # 会串成一条长蛇，好几段被逼着绕过整个 Hub 卫星圈。 + cur = comps[0] + rest = comps[1:] + anchors = [cur.anchor] + while rest: + rest.sort(key=lambda c: min(math.hypot(c.anchor[0] - a[0], c.anchor[1] - a[1]) + for a in anchors)) + tgt = rest.pop(0) + # 宽度阶梯：正常宽度过不去就收窄再试。Hub 卫星圈 / 排母缝这些地方 + # 差的往往就是几十微米，收到 0.15 就通了，而载流上这些都是信号线。 + seg = None + for wtry in _widths(w, net): + seg = _connect(net, cur, tgt, obstacles, wtry, relax=relax) + if seg is not None: + break + # 首选出线方向走不通 -> 换个方向再试（见文件头那段说明） + if seg is None and getattr(tgt, 'stub_alts', None): + q = tgt.pad + for end2, ws2 in tgt.stub_alts: + t2 = Comp([tgt.rect, sh_seg(q['x'], q['y'], end2[0], end2[1], ws2, q['lay'])], + end2, center=end2, layers=tgt.layers) + for wtry in _widths(w, net): + seg = _connect(net, cur, t2, obstacles, wtry, relax=relax) + if seg is not None: + break + if seg is not None: + paths[tgt.stub_i] = [ + (round(q['x'], 4), round(q['y'], 4), q['lay'], ws2), + (round(end2[0], 4), round(end2[1], 4), q['lay'], ws2)] + tgt = t2 + if verbose: + print(u' %s.%s 改从 %s 出线' % (q['ref'], q['num'], _fmt(end2))) + break + if seg is None: + if verbose: + print(u' [!!] %s 布不通：%s -> %s' % (net, _fmt(cur.anchor), _fmt(tgt.anchor))) + cur.merge(tgt, []) + anchors.append(tgt.anchor) + continue + path, shp = seg + paths.append(path) + obstacles.extend((sp, net) for sp in shp) + cur.merge(tgt, shp) + anchors.append(tgt.anchor) + return paths + + +W_MIN = 0.15 # 一般信号收窄的下限（嘉立创四层工艺下限 0.102，留足余量） +# ⚠️ **功率网络的下限是设计规则给的，不是工艺给的。** +# `pcb2_rules.TRACK_RULES` 里 PWR1A 的 `strokeWidthMin` 是 0.25、PWR5V 是 0.30、 +# PWR4A 是 0.30；收窄到 0.15 会被 DRC 记成「物理错误·导线」—— +# 实测第一版就这么刷出 **40 条**，而净距校核一条都不报（线宽不是净距问题）。 +W_MIN_NET = {'+5V': 0.30, '+3V3_HUB': 0.15} # PWR1A 的 min 已降到 0.15，见 pcb2_rules +for _n in range(1, 6): + W_MIN_NET['VBUS%d' % _n] = 0.25 + W_MIN_NET['VO%d_P' % _n] = 0.30 + + +def _widths(w, net=None): + lo = W_MIN_NET.get(net, W_MIN) + out = [w] + for v in (round(w * 0.7, 3), lo): + if v < out[-1] - 1e-6 and v >= lo - 1e-6: + out.append(v) + return out + + +def _fmt(p): + return u'(%.2f,%.2f)' % (p[0], p[1]) + + +def _bbox(shapes, pad): + xs, ys = [], [] + for s in shapes: + if s[0] == 'rect': + xs += [s[1] - s[3], s[1] + s[3]] + ys += [s[2] - s[4], s[2] + s[4]] + elif s[0] == 'via': + xs += [s[1] - s[3], s[1] + s[3]] + ys += [s[2] - s[3], s[2] + s[3]] + else: + xs += [s[1] - s[5], s[3] + s[5]] + ys += [s[2] - s[5], s[4] + s[5]] + return (min(xs) - pad, min(ys) - pad, max(xs) + pad, max(ys) + pad) + + +def _connect(net, a, b, obstacles, w, pad=BBOX_PAD, relax=None): + u"""把两坨铜连起来。窗口先小后大、栅格先粗后细，找到就返回。 + + ⚠️ **细栅格那一档不是可有可无的。** 排母 2.54 间距 / Ø1.699 焊盘 ⇒ 缝宽 0.841 mm， + 0.25 的线要 2×(0.20+0.125) = 0.65 —— 明明过得去，但 0.1 mm 栅格上 + 离缝心最近的格心可能偏 0.04，再加 QERR 0.071 就差那么一点点， + 于是"从排母针缝里穿过去"这件事在粗栅格上**整片不可达**。 + 0.05 mm 栅格把这两项都减半，缝就通了。 + """ + # ⚠️ 窗口先**以目标为中心**开小的，再退到「整坨 + 目标」的大窗口（2026-09-06）。 + # 原来一上来就取 a.shapes + b.shapes 的包围盒：`+3V3_HUB` 已连上的那坨横跨全板， + # 窗口一大栅格就被放粗到 0.2 以上，QFN 东侧 0.71 mm 的走廊（U32.46 的出线端） + # 在粗栅格上整片不可达 —— 单独布它能通、全量布就不通，根子在这里不在拥挤。 + # 小窗口里只有离目标近的那部分 `a` 当种子，别的部分对这一段本来也没用。 + # 2026-09-07：加一档 **'near'**：窗口 = 目标 + 「已连上那坨里离目标最近的一件」。 + # 大网络（+3V3_HUB 33 个焊盘）的远支路（site1 的 U41）在 'tgt' 小窗里没有种子， + # 直接退到 'all' 全板大窗 -> 栅格放粗 -> 排母缝 / 元件簇进不去。'near' 窗只框住真正要连的那一段。 + tries = [('tgt', 0, 1), ('tgt', 0, 2), ('tgt', 0, 4), ('tgt', 1, 2), ('tgt', 1, 4), + ('near', 0, 1), ('near', 0, 2), ('near', 1, 1), ('near', 1, 2), ('near', 2, 2), + ('all', 0, 1), ('all', 0, 2), ('all', 0, 4), ('all', 1, 1), ('all', 1, 2), + ('all', 1, 4), ('all', 2, 1), ('all', 2, 4)] + bc = _bbox(b.shapes, 0.0) + bcx, bcy = (bc[0] + bc[2]) / 2.0, (bc[1] + bc[3]) / 2.0 + + def _d2(s_): + bb = _bbox([s_], 0.0) + return (((bb[0] + bb[2]) / 2.0 - bcx) ** 2 + ((bb[1] + bb[3]) / 2.0 - bcy) ** 2) + a_near = min(a.shapes, key=_d2) if a.shapes else None + for mode, grow, fine in tries: + if mode == 'tgt': + base = b.shapes + elif mode == 'near': + if a_near is None: + continue + base = b.shapes + [a_near] + else: + base = a.shapes + b.shapes + x0, y0, x1, y1 = _bbox(base, pad + grow * 20.0) + x0, y0 = max(0.0, x0), max(0.0, y0) + x1, y1 = min(BW, x1), min(BH, y1) + if mode in ('tgt', 'near'): + a_in = [s_ for s_ in a.shapes if _bbox([s_], 0.0)[2] > x0 and _bbox([s_], 0.0)[0] < x1 + and _bbox([s_], 0.0)[3] > y0 and _bbox([s_], 0.0)[1] < y1] + if not a_in: + continue # 这一窗里没有种子，直接开大窗 + a_use = Comp(a_in, a.anchor, center=a.center, layers=a.layers) + else: + a_use = a + # 窗口太大就把栅格放粗一档：判据里的 QERR 跟着变，仍然是**充分条件**， + # 只是长距离那几根线会保守一点（走廊本来就宽，损失不了什么）。 + g = GRID / float(fine) + while ((x1 - x0) / g + 2) * ((y1 - y0) / g + 2) > MAX_CELLS: + g *= 2 + f = Field(obstacles, (x0, y0, x1, y1), skip_net=net, grid=g) + if relax: + f.set_relax(relax) + src = _mask(f, a_use) + tgt = _mask(f, b) + cells = route_grid(f, src, tgt, w) + if cells is None: + continue + pts = _runs(cells) + chunks = polish(f, pts, w) + path = [] + for lay, xy in chunks: + for x, y in xy: + path.append((round(float(x), 3), round(float(y), 3), lay, w)) + path = _dedup(path) + # 端点钉回焊盘圆心（见 Comp 的注释）。 + # ⚠️ 端点处可能有**一串重合点**（换层），要整串一起挪，不能只挪最后一个。 + if a.center: + _snap_end(path, a.center, False) + else: + _anchor_start(path, a.shapes) + if b.center: + _snap_end(path, b.center, True) + path = _end_via(path) + segs, vs = expand(path) + shp = [sh_seg(sx0, sy0, sx1, sy1, sw, sl) for sx0, sy0, sx1, sy1, sl, sw in segs] + shp += [sh_via(vx, vy) for vx, vy in vs] + return path, shp + return None + + +def _mask(f, c): + u"""A* 的种子 / 目标格。单焊盘只取圆心那一格，其余按整坨铜。""" + if c.center: + m = {L: np.zeros((f.ny, f.nx), bool) for L in f.lays} + i, j = f._idx(c.center[0], c.center[1]) + if 0 <= i < f.nx and 0 <= j < f.ny: + for L in c.layers: + m[L][j, i] = True + return m + return f.mask_of(c.shapes) + + +def _dedup(path): + out = [] + for p in path: + if out and abs(out[-1][0] - p[0]) < 1e-9 and abs(out[-1][1] - p[1]) < 1e-9 \ + and out[-1][2] == p[2]: + continue + out.append(p) + return out + + +def _same(a, b): + return abs(a[0] - b[0]) < 1e-9 and abs(a[1] - b[1]) < 1e-9 + + +def _snap_end(path, xy, at_end): + u"""把路径某一端**所有重合的点**一起钉到 `xy`（焊盘圆心）。 + + 换层处路径里是两个同坐标不同层的点；只挪其中一个的话， + 过孔就跟导线错开 0.05 mm，`expand()` 认不出换层，孔直接消失。 + """ + if at_end: + k = len(path) - 1 + while k > 0 and _same(path[k - 1], path[k]): + k -= 1 + rng = range(k, len(path)) + else: + k = 0 + while k + 1 < len(path) and _same(path[k], path[k + 1]): + k += 1 + rng = range(0, k + 1) + for i in rng: + path[i] = (round(xy[0], 4), round(xy[1], 4), path[i][2], path[i][3]) + + + +def via_corners(routes, limit=SHARP): + u"""换层点两侧的线在平面上成"直角"的那些：[(key, i, (x, y), 转向角)]。 + `sharp_corners` 故意跳过换层点（那是过孔）；用户 2026-09-07 要求换层处也不许 90°。""" + out = [] + for key, path in sorted(routes.items()): + for i in range(1, len(path) - 2): + b, b2 = path[i], path[i + 1] + if not _same(b, b2) or b[2] == b2[2]: + continue + a, c = path[i - 1], path[i + 2] + if _same(a, b) or _same(b2, c): + continue + t = turn_deg(a, b, c) + if t > limit: + out.append((key, i, (b[0], b[1]), t)) + return out + + +def via_chamfer_routes(routes, pads, vias, lines): + u"""换层点的 45° 化（2026-09-07 用户要求：「两层中的走线连接处不要垂直，增加一段锐角走线」）。 + + 顶层横线进孔、底层竖线出孔，在平面上就是一个直角。做法和普通拐角一样切一刀， + 但过孔要挪到斜切段的一端： + A 型：进线层上 R->Q 走 45°，过孔放在 Q（= 原孔位沿出线方向挪 d），出线从 Q 直着走； + B 型：过孔放在 R（= 原孔位沿进线方向退 d），出线层上 R->Q 走 45°。 + 先试 A 再试 B，半径按 CHAMFER_R 逐档退让；斜切段过 `seg_slack`，新孔位过 `_via_legal`。 + 校核用的是**改之前**的其它段（保守）。返回 (新 routes, 切掉的数量)。 + """ + mine, mvias = [], [] + for key, path in routes.items(): + for x0, y0, x1, y1, lay, w in expand(path)[0]: + mine.append((netof(key), lay, x0, y0, x1, y1, w)) + for vx, vy in expand(path)[1]: + mvias.append((netof(key), vx, vy)) + + def via_legal(x, y, net, old=None): + for x0, y0, x1, y1 in VIA_KEEPOUT: + if x0 <= x <= x1 and y0 <= y <= y1: + return False + for q in pads: + if q['net'] != net and q['lay'] in (12, L_TOP, L_BOT): + if seg_rect((x, y), (x, y), q['x'], q['y'], q['hw'], q['hh']) - VIA_R < CLR - 1e-4: + return False + if q['lay'] == 12 and math.hypot(x - q['x'], y - q['y']) < q['hw'] + VIA_H / 2.0 + HOLE_CLR: + return False # 钻孔间距不分网络；焊盘半宽当孔半径，保守 + for v in vias: + d = math.hypot(x - v['x'], y - v['y']) + if v['net'] != net and d - VIA_R - v['r'] < CLR - 1e-4: + return False + if d < VIA_H + HOLE_CLR - 1e-4: + return False + for n2, vx, vy in mvias: + if old is not None and abs(vx - old[0]) < 1e-6 and abs(vy - old[1]) < 1e-6: + continue # 本路径自己原来那个孔（马上要挪走） + d = math.hypot(x - vx, y - vy) + if n2 != net and d - 2 * VIA_R < CLR - 1e-4: + return False + if d < VIA_H + HOLE_CLR - 1e-4: + return False + for l in lines: + if l['net'] != net and seg_pt(l['x0'], l['y0'], l['x1'], l['y1'], x, y) - VIA_R - l['w'] / 2.0 < CLR - 1e-4: + return False + for n2, lay, x0, y0, x1, y1, w in mine: + if n2 != net and seg_pt(x0, y0, x1, y1, x, y) - VIA_R - w / 2.0 < CLR - 1e-4: + return False + return True + + out, ncut = {}, 0 + for key, path in routes.items(): + net = netof(key) + ok = lambda x0, y0, x1, y1, lay, w, _n=net: ( + seg_slack(x0, y0, x1, y1, lay, w, _n, pads, vias, lines, mine, mvias) >= -1e-4) + res = [] + i = 0 + while i < len(path): + b = path[i] + if not (1 <= i <= len(path) - 3): + res.append(b) + i += 1 + continue + b2 = path[i + 1] + a, c = path[i - 1], path[i + 2] + if not _same(b, b2) or b[2] == b2[2] or _same(a, b) or _same(b2, c) or turn_deg(a, b, c) <= SHARP: + res.append(b) + i += 1 + continue + ax, ay = b[0] - a[0], b[1] - a[1] + cx, cy = c[0] - b[0], c[1] - b[1] + la, lc = math.hypot(ax, ay), math.hypot(cx, cy) + wa, wb = a[3], b2[3] + done = None + for r in CHAMFER_R: + d = min(r, la / 2.0, lc / 2.0) + if d < 0.05: + break + R = (round(b[0] - ax / la * d, 4), round(b[1] - ay / la * d, 4)) + Q = (round(b[0] + cx / lc * d, 4), round(b[1] + cy / lc * d, 4)) + # A 型：斜段在进线层，孔在 Q + if ok(R[0], R[1], Q[0], Q[1], a[2], wa) and via_legal(Q[0], Q[1], net, (b[0], b[1])): + done = [(R[0], R[1], a[2], wa), (Q[0], Q[1], a[2], wa), (Q[0], Q[1], b2[2], wb)] + break + # B 型：孔在 R，斜段在出线层 + if ok(R[0], R[1], Q[0], Q[1], b2[2], wb) and via_legal(R[0], R[1], net, (b[0], b[1])): + done = [(R[0], R[1], a[2], wa), (R[0], R[1], b2[2], wb), (Q[0], Q[1], b2[2], wb)] + break + if done is None: + res.append(b) + i += 1 + continue + res.extend(done) + ncut += 1 + i += 2 # 跳过 b2（旧孔位的第二个点） + out[key] = res + return out, ncut + +def reanchor_routes(routes, pads): + u"""切角 / 焊盘矩形角两类问题的兜底：让每条路径的两端都落在本网的铜里。返回补的段数。""" + by_net = {} + for key, path in routes.items(): + by_net.setdefault(netof(key), []).append(key) + padix = {} + for q in pads: + if q['net']: + padix.setdefault(q['net'], []).append(q) + nfix = 0 + for net, keys in by_net.items(): + segs, vias = [], [] + for k in keys: + sg, vv = expand(routes[k]) + segs += [(k, x0, y0, x1, y1, lay, w) for x0, y0, x1, y1, lay, w in sg] + vias += [(k, x, y) for x, y in vv] + for k in keys: + path = routes[k] + if len(path) < 2: + continue + for at_end in (False, True): + x, y, lay, w = path[-1] if at_end else path[0] + inside = False + for q in padix.get(net, []): + if (q['lay'] == 12 or q['lay'] == lay) and math.hypot(x - q['x'], y - q['y']) <= min(q['hw'], q['hh']) + 1e-6: + inside = True + break + if not inside: + for k2, vx, vy in vias: + if math.hypot(x - vx, y - vy) <= VIA_R + 1e-6: + inside = True + break + if not inside: + for k2, x0, y0, x1, y1, l2, w2 in segs: + if k2 == k or l2 != lay: + continue + if seg_pt(x0, y0, x1, y1, x, y) <= w2 / 2.0 + 1e-6: + inside = True + break + if inside: + continue + best = None + for k2, x0, y0, x1, y1, l2, w2 in segs: + if k2 == k or l2 != lay: + continue + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + tt = 0.0 if L2 < 1e-12 else max(0.0, min(1.0, ((x - x0) * dx + (y - y0) * dy) / L2)) + qx, qy = x0 + tt * dx, y0 + tt * dy + d = math.hypot(x - qx, y - qy) + if best is None or d < best[0]: + best = (d, qx, qy) + for q in padix.get(net, []): + if q['lay'] == 12 or q['lay'] == lay: + d = math.hypot(x - q['x'], y - q['y']) + if best is None or d < best[0]: + best = (d, q['x'], q['y']) + if best is None or best[0] > 1.5: + print(u' [!!] %s 的%s点 (%.3f,%.3f) L%d 不在本网铜里，附近 1.5 mm 内也没有可接的铜' + % (k.replace(KSEP, '|'), u'终' if at_end else u'起', x, y, lay)) + continue + pt = (round(best[1], 4), round(best[2], 4), lay, w) + if at_end: + path.append(pt) + else: + path.insert(0, pt) + nfix += 1 + return nfix + + +def _anchor_start(path, shapes): + u"""从「已连上的一坨」出发的路径，起点若落在某个**矩形焊盘形状**里但没在圆心，补一个圆心点。 + + 2026-09-07 第三十轮实测：Comp 的注释早就写了「圆焊盘存的是外接矩形，停在角上搭不到铜」， + 单焊盘的起终点因此钉在圆心；但 MST 后续每条边的**起点**是整坨铜的掩膜（矩形）， + Dijkstra 挑离目标最近的种子 = 矩形角，离 Ø1.7 排母脚圆心 1.2 mm，铜外 0.2 —— + KEY_SRCLK/KEY_RCLK/+5V 在 J32 上、VBUS2/+3V3_HUB 在贴片盘上各留了一个孤岛（DRC 连接性 10 条）。 + 补的这一段全程在本网焊盘内部 / 焊盘自己的净距圈里，不会碰别的网。 + """ + if not path: + return + x, y, lay, w = path[0] + if os.environ.get('ANCHOR_DEBUG'): + nb = [] + for s_ in shapes: + if s_[0] == 'seg': + d = seg_pt(s_[1], s_[2], s_[3], s_[4], x, y) - s_[5] + elif s_[0] == 'via': + d = math.hypot(x - s_[1], y - s_[2]) - s_[3] + else: + d = seg_rect((x, y), (x, y), s_[1], s_[2], s_[3], s_[4]) + if d < 1.0: + nb.append((round(d, 3), s_)) + nb.sort(key=lambda t: t[0]) + print(u' [dbg] 起点 (%.3f,%.3f) L%d 附近形状: %s' % (x, y, lay, nb[:4])) + # 起点已经落在本网的导线 / 过孔铜里（比如出线段的末端）就不用补 + for s_ in shapes: + if lay not in s_[-1]: + continue + if s_[0] == 'seg' and seg_pt(s_[1], s_[2], s_[3], s_[4], x, y) <= s_[5] + 1e-6: + return + if s_[0] == 'via' and math.hypot(x - s_[1], y - s_[2]) <= s_[3] + 1e-6: + return + best = None + for s_ in shapes: + if s_[0] != 'rect' or lay not in s_[-1]: + continue + _, cx, cy, hw, hh, _ = s_ + d = math.hypot(x - cx, y - cy) + if d <= math.hypot(hw, hh) + 0.05 and (best is None or d < best[0]): + best = (d, cx, cy) + if best is not None and best[0] >= 1e-3: + path.insert(0, (round(best[1], 4), round(best[2], 4), lay, w)) + return + if best is not None: + return + if os.environ.get('ANCHOR_DEBUG'): + cont = [] + for s_ in shapes: + if lay not in s_[-1]: + continue + if s_[0] == 'seg' and seg_pt(s_[1], s_[2], s_[3], s_[4], x, y) <= s_[5] + 1e-6: + cont.append(s_) + elif s_[0] == 'via' and math.hypot(x - s_[1], y - s_[2]) <= s_[3] + 1e-6: + cont.append(s_) + print(u' [dbg] 起点 (%.3f,%.3f) L%d 落在: %s' % (x, y, lay, cont[:3])) + # 诊断：起点不在本网任何形状里（2026-09-07 追 VBUS2 / +3V3_HUB 的孤岛） + near = [] + for s_ in shapes: + if s_[0] == 'seg': + near.append((seg_pt(s_[1], s_[2], s_[3], s_[4], x, y) - s_[5], s_)) + elif s_[0] == 'via': + near.append((math.hypot(x - s_[1], y - s_[2]) - s_[3], s_)) + else: + near.append((math.hypot(x - s_[1], y - s_[2]), s_)) + near.sort(key=lambda t: t[0]) + print(u' [?] 起点 (%.3f,%.3f) L%d 不在本网铜里；最近 %s' % (x, y, lay, near[:2])) + + +def _end_via(path): + u"""路径**最后一个点上的过孔**要补一个重复点，`expand()` 才认得出来。 + + ⚠️ 这是本脚本抓到的最阴的一个 bug。`expand()` 的语义是 + 「第 i 点的层 = 从这一点走到下一点那一段的层」，换层的过孔打在第 i+1 点上， + **但它显式跳过最后一个点**（`i + 1 < n - 1`）——最后一点的层被当成占位符。 + 于是"走到目标焊盘正上方再换层落下去"这种路径，**过孔被静默丢掉**： + 两层的铜各画各的，中间断开。 + + 更糟的是三道校核全都抓不到：净距校核只看有没有撞上（断开当然不撞）， + DRC 的连接性又要 `location.reload()` 才刷新。 + 实测 `$25N40` / `SDA` / `VBUS_DET` / `XTAL2` / `VBUS_EN3` 五个网络就是这么断的。 + 起点侧不用补 —— 起点的重合点对 `expand()` 是"第 0 段长度为 0 + 第 1 点换层"，本来就认得出。 + """ + if len(path) >= 2 and _same(path[-1], path[-2]) and path[-1][2] != path[-2][2]: + return path + [path[-1]] + return path + + +# ══════════════════ 本轮要布的网络 ══════════════════ +def _to_site(n, seq): + return [(round(to_board(n, u_, v_, 0)[0], 3), round(to_board(n, u_, v_, 0)[1], 3), lay, ww) + for u_, v_, lay, ww in seq] + + +def bm24_pre(n): + u"""第 n 站 BM24 的 13 个 GND 脚怎么接到地平面（手写，站内坐标，**全部底层**）。 + + §25.8 判定「51 个脚旁边打不下 Ø0.61 的孔、只能逃逸出来再并」是对的。 + v5 的具体走法（和 v4 反过来，理由见上面那段车道分配）： + + · **前排** pin 2/8/12/16/24 → 往**内**（进中央通道），在 v=35.00 并成一条 0.30 梳子， + 梳子上打 4 个孔（跳过 u 50.05，它和 50.75 只隔 0.70 < 0.81）； + · **后排** pin 1/19/23/29/37/41/47 → 往**外**（v−），在 v=33.10 并成第二条梳子， + 打 5 个孔（那一带一路空到 v 26，是全站最宽敞的地方）； + · **pin 52** 单独往东平出到 u=59.60 打一个孔。 + + ⚠️ 这 65 个脚**已经从 `pcb2_fanout.py` 里整批剔除**（`SKIP_PAD`）， + 全靠这里画出来 —— 漏一个就是一条连接性 DRC。 + """ + B = lambda seq: _to_site(n, seq) + out = [] + # ── 前排：往内进中央通道 ── + # 最西那根出线段和梳子写成**同一条路径**，西端那个 90° 才切得成 45°； + # 其余几根是 T 形接头（线本身不拐弯），保持原样。 + out.append(B([(J7_GND_FRONT[0], J7_FRONT_V, L_BOT, W_ARR), + (J7_GND_FRONT[0], J7_FRONT_IN, L_BOT, W_COMB), + (J7_GND_FRONT[0], J7_MID_COMB, L_BOT, W_COMB), + (J7_GND_FRONT[-1], J7_MID_COMB, L_BOT, W_COMB)])) + for u_ in J7_GND_FRONT[1:]: + out.append(B([(u_, J7_FRONT_V, L_BOT, W_ARR), + (u_, J7_FRONT_IN, L_BOT, W_COMB), + (u_, J7_MID_COMB, L_BOT, W_COMB)])) + for u_ in J7_MID_VIA_U: + out.append(B([(u_, J7_MID_COMB, L_BOT, W_COMB), (u_, J7_MID_COMB, L_TOP, W_COMB)])) + # ── 后排：往外并成第二条梳子 ── + out.append(B([(J7_GND_BACK[0], J7_BACK_V, L_BOT, W_ARR), + (J7_GND_BACK[0], J7_BACK_ESC, L_BOT, W_COMB), + (J7_GND_BACK[0], J7_BACK_COMB, L_BOT, W_COMB), + (J7_GND_BACK[-1], J7_BACK_COMB, L_BOT, W_COMB)])) + for u_ in J7_GND_BACK[1:]: + out.append(B([(u_, J7_BACK_V, L_BOT, W_ARR), + (u_, J7_BACK_ESC, L_BOT, W_COMB), + (u_, J7_BACK_COMB, L_BOT, W_COMB)])) + for u_ in J7_BACK_VIA_U: + out.append(B([(u_, J7_BACK_COMB, L_BOT, W_COMB), (u_, J7_BACK_COMB, L_TOP, W_COMB)])) + # ── pin 52：往东平出打孔 ── + out.append(B([(J7_GND_BIG, J7_MID_V, L_BOT, W_COMB), + (J7_PIN52_VIA_U, J7_MID_V, L_BOT, W_COMB), + (J7_PIN52_VIA_U, J7_MID_V, L_TOP, W_COMB)])) + return out + + +def bm24_lane(n, kind): + u"""THERM / CC1 从前排往**外**出，直接进正北的 R77n.1 / R76n.1（v5）。 + + v4 那条「走中央通道往东绕出来」的路线在 v5 已经没有必要 —— + 后排整排都是 GND，通道判给了前排 GND 的梳子，而 R76n/R77n 就在前排外侧。 + + · `CC1_n`：R76n 的中心特意取 52.233，pin1 正落在 u 51.800 = J7n.22 正北 + ⇒ **一根直线上去**，全程底层。 + · `THERM_n`：目标在 u 54.367，要往东跨过 CC1 那根竖线 —— + **打两个孔走顶层过去**（顶层在 J7n 这一带一根线都没有）。 + 西孔离 `*_DPJ` 的换层孔 0.97 ≥ 0.81，是这一段最紧的一处。 + """ + if kind == 'CC1': + return _to_site(n, [(J7_CC1_U, J7_FRONT_V, L_BOT, W_ARR), + (J7_CC1_U, J7_FRONT_ESC, L_BOT, W_LANE), + (J7_R76_PIN1_U, J7_R_ENTER_V, L_BOT, W_LANE)]) + (wu, wv), (eu, ev) = J7_THERM_VIA + ku, kv = J7_THERM_KINK + # ⚠️ 第 i 点的 width 管的是「这一点到下一点」那一段。 + # 前两段（直出 + 45° 斜出）**必须都是 0.11** —— 理由见 J7_THERM_TURN_V 那一段注释。 + return _to_site(n, [(J7_THERM_U, J7_FRONT_V, L_BOT, W_ARR), + (J7_THERM_U, J7_THERM_TURN_V, L_BOT, W_ARR), # 直出到 36.58，仍 0.11 + (ku, kv, L_BOT, W_LANE), # 45° 斜出，仍 0.11 -> 之后放宽 + (wu, wv, L_BOT, W_LANE), # 竖上到西孔（离 DPJ 孔 0.80） + (wu, wv, L_TOP, W_LANE), # ↑ 换层 + (eu, ev, L_TOP, W_LANE), # 顶层东行（顶层这一带是空的） + (eu, ev, L_BOT, W_LANE), # ↓ 换层 + (J7_R77_PIN1_U, J7_R_ENTER_V, L_BOT, W_LANE)]) + + +# ── 布线顺序（挤的先布、宽的先布）───────────────────────────────────── +# Hub 卫星圈是 1.2 mm 网格上的 0402，缝只有 0.66 mm；服务带里 0402 也是密排。 +# 所以次序是：**Hub 局部 -> 上游 -> 站内局部 -> 电源 -> 长距离控制线**。 +ALL_NETS = set() +PADS_ALL = [] # main() 装进来，`_pogo_by_length()` 要用 +lanes0 = (['THERM_%d' % n for n in range(1, 6)] + ['CC1_%d' % n for n in range(1, 6)]) + + +def _pogo_by_length(): + u"""十五根 POGO，按站分组、组内按两端直线距离从短到长。""" + out = [] + for n in range(1, 6): + row = [] + for k in ('PWR', 'VUP', 'VDN'): + net = 'POGO%d_%s' % (n, k) + ps = [p for p in PADS_ALL if p['net'] == net] + d = (math.hypot(ps[0]['x'] - ps[1]['x'], ps[0]['y'] - ps[1]['y']) + if len(ps) == 2 else 0.0) + row.append((d, net)) + out += [net for _d, net in sorted(row)] + return out + + +def net_order(): + # GND 与 THERM/CC1 的车道排最前：BM24 周围那三条缝是**手写死的几何**， + # 后面所有网络都必须看得见它们、绕开走。 + # + # ⚠️ 2026-09-06 试过把 `+3V3_HUB` 提到这一组最前（想让它先抢卫星圈的缝）， + # **结果更糟**：它有 33 个焊盘，先布就把 Hub 周围铺满， + # `XTAL1`/`CFGSEL0`/`PRTDIS6`/`PRTDIS7`/`HUB_RST` 五根配置线全布不通 + # （没布通的从 4 个涨到 7 个）。⇒ 大网络必须排在点对点的小网络之后。 + # 2026-09-07：`HUB_RST` 提到 `VBUS_UP` 之前。R716.1 唯一的出口是 R716/R711 之间 0.66 的底层缝， + # 缝东头是 USB5 竖线墙、必须换层；VBUS_UP 先布时从 R709.1 出来在顶层 y 67.2 横穿卫星圈东行， + # 和 +3V3 前置线（顶层 y 66.2）夹成 0.8 的带，塞不下换层孔 -> HUB_RST 布不通（第三十轮实测）。 + hub = ['GND'] + lanes0 + ['HUB_RST', 'VBUS_UP'] + [ + 'RBIAS', 'VDD18', 'VDD18PLL', 'XTAL1', 'XTAL2', + 'CFGSEL0', 'CFGSEL1', 'NONREM0', 'NONREM1', 'PRTDIS6', 'PRTDIS7', + '+3V3_HUB', 'VBUS_DET'] + # `EDL_ENn` / `VBUS_ENn` 在 U4n / U2n 上是**紧挨着 +3V3 脚的那一针**， + # 排在 `+3V3_HUB` 之前，否则 3V3 的长支干会从这 0.95 mm 的缝里横穿过去。 + en = ['EDL_EN%d' % n for n in range(1, 6)] + ['VBUS_EN%d' % n for n in range(1, 6)] + # `+3V3_HUB` 排在 Hub 局部之后、其它一切之前：它有 33 个焊盘、 + # 一半挤在 Hub 的卫星圈里，晚一步就没缝了。 + # `+5V` 紧跟 `+3V3_HUB`：它要从排母穿过已经站满 EN/POGO 线的走廊过来， + # 排在后面的话 site2/site5 那两段就没缝了。 + # 2026-09-06（v5）实测调过一次次序：`+3V3_HUB` 和 `VBUS_UP` 单独跑都能通 + # （45 s / 2 s），一起跑就都断 —— 说明是抢地盘，不是没有路。 + # · `+3V3_HUB` 提到 EN 组**之前**（但仍在 Hub 局部之后，那五根配置线的教训还在）； + # · `VBUS_UP` 提到 `+5V` **之前** —— 它要横穿大半块板去 J23， + # 而 `+5V` 是 0.60 的宽线，先布就把那条走廊占死了。 + up = en + ['VBUS_UP', 'UP_VBUS_DET', '+5V', '$16N222', '$16N224'] + # `$` 开头的是原理图自动命名的局部网（J6n<->U4n、C72n<->U2n）， + # 编号不成规律（site1 是 $21N57/58，其余是 $2xN39/40），所以从网表里捞。 + site = sorted(n for n in ALL_NETS if n.startswith('$')) + power = ['VBUS%d' % n for n in range(1, 6)] + # 每个站的三根 POGO 按**两端直线距离从短到长**排：短的那根余地最小， + # 让它先挑路；长的绕得起。site4/site5 上这条规则把 `VDN` 提到最前 —— + # 它的源在最东、靶点却在最西（J59 比 J57/J58 靠里），后布就被另外两根夹死 + # （`POGO5_VDN` 原来就是这么布不通的）。 + # 2026-09-06 595 上载板：移位链 4 根（各 4 个焊盘：J32 + 三片）+ 两根级联 + 15 根 K 栅极线（点对点）， + # 排在 POGO 之前 —— K 线从走廊中段扇到五个站，比站内的 POGO 短线更需要先挑路。 + # 2026-09-07 第三十轮（U21 rot 0 / U22 rot 180 之后）：**K 线排在移位链控制线之前**。 + # U22 南排的 K4/K5 六根只能从南带（UP 差分线边 60.74 ~ 焊盘下沿 62.77，2 mm）换层出去； + # KEY_* 先布时把这条带在顶层横着占满（U21 南排 -> U22 北排 -> J32 北排的直路），K4_VDN/K5_VUP/K5_VDN 布不通。 + # 控制线有别的路（U22 两排脚之间 y 64.75~68.25 那 3.5 mm 的通道、J32 北侧），K 线没有。 + keys = ['K%d_%s' % (n, k) for n in range(1, 6) for k in ('PWR', 'VUP', 'VDN')] + keys += ['KEY_SER', 'KEY_SRCLK', 'KEY_RCLK', 'KEY_OE#', 'SR_CAS', 'SR_CAS2'] + ctrl = [n for n in _pogo_by_length()] + ['SDA', 'SCL'] + # 2026-09-06：K 线 / 移位链提前到 `up` 之前 —— 它们是点对点细线，单独布 0.6 s 就通， + # 排在 +5V / VBUS / 站内局部网之后就被挤死（实测两轮各 11~12 根布不通）。 + out, seen = [], set() + for n in hub + keys + up + site + power + ctrl: + if n not in seen: + seen.add(n) + out.append(n) + return out + + +# ⚠️ 手写的前置段也**必须**过一遍 `_end_via()`。 +# `bm24_pre()` 里那些「走到位置 -> 换层」的路径最后两个点是同坐标不同层， +# 而 `expand()` 显式跳过最后一个点上的过孔 —— 五个站 **50 个 GND 过孔全部丢掉**， +# 两条梳子和 pin52 的连线整个悬空，DRC 报出 J7n 的 pin 1/2/8/12/47/52 断开。 +# 净距校核和 `inner1_verify` 都不会响：悬空的铜不违反任何净距。 +PRE = {} +for _n in range(1, 6): + PRE.setdefault('GND', []).extend(_end_via(p) for p in bm24_pre(_n)) + PRE['THERM_%d' % _n] = [_end_via(bm24_lane(_n, 'THERM'))] + PRE['CC1_%d' % _n] = [_end_via(bm24_lane(_n, 'CC1'))] + +PRE_ONLY = {'GND'} # 只落前置段、不做最小生成树的网络 +OUT = os.path.join(HERE, '_pcb2_sig_routes.json') + + +# ══════════════════ 下发 ══════════════════ +# ⚠️ `pcb2_route_dp.push()` 的做法是「把这些网络上现有的线和过孔全删掉再重画」。 +# 对差分对没问题，对 **GND 是灾难** —— 一按就把 §25.8 那 210 个扇出过孔和 +# 126 条出线全扫掉，而几何校核和 DRC 都只会说"连接性错误变多了"。 +# 所以 GND 走**外科式删除**：只删落在五个 BM24 逃逸框里的 GND 铜。 +# v5 的框取站内 u ∈ [47.5, 60.3]、v ∈ [32.5, 36.5]： +# · 装得下两条梳子（v 35.00 / 33.10）、13 根出线和 pin52 往东那一截； +# · **不碰**框外那些 `pcb2_fanout.py` 画的孔 —— R77n.2 在 v 38.0、U5n.2 的孔在 (48.80, 39.45)， +# 两者都在 v > 36.5；手机定位柱 PnH3 在 u 61.90 > 60.3。 +# · J7n 那 65 个 GND 脚本来就被 `pcb2_fanout.SKIP_PAD` 剔除了，框里除了本脚本自己画的没有别人的铜。 +GND_BOX_UV = (47.5, 32.5, 60.3, 36.5) + + +def gnd_boxes(): + out = [] + for n in SITES: + xs, ys = [], [] + for u_, v_ in ((GND_BOX_UV[0], GND_BOX_UV[1]), (GND_BOX_UV[2], GND_BOX_UV[3])): + bx, by, _ = to_board(n, u_, v_, 0) + xs.append(bx) + ys.append(by) + out.append([round(min(xs), 3), round(min(ys), 3), round(max(xs), 3), round(max(ys), 3)]) + return out + + +# ⚠️ 2026-09-06：原来一个请求里「逐条删 + 逐条建 1589 段」，桥接 30 s 超时（EasyEDA 那边还在继续画）， +# 下一步抓几何抓到画了一半的板子。现在拆成：一次性批量删 -> 每 250 段一个请求建线 -> 建孔 -> 存盘。 +JS_PUSH_DEL = u""" +const NETS = %s, BOXES = %s, MIL = %f; +const S = new Set(NETS); +const inBox = (x, y) => BOXES.some(b => x >= b[0] && x <= b[2] && y >= b[1] && y <= b[3]); +const dl = [], dv = []; +for (const o of await eda.pcb_PrimitiveLine.getAll()) { + const L = o.getState_Layer(); if (L !== 1 && L !== 2) continue; + const n = o.getState_Net(); + const keep = n === 'GND' + ? !(inBox(o.getState_StartX()/MIL, o.getState_StartY()/MIL) && + inBox(o.getState_EndX()/MIL, o.getState_EndY()/MIL)) + : !S.has(n); + if (!keep) dl.push(o.getState_PrimitiveId()); +} +for (const o of await eda.pcb_PrimitiveVia.getAll()) { + const n = o.getState_Net(); + const keep = n === 'GND' ? !inBox(o.getState_X()/MIL, o.getState_Y()/MIL) : !S.has(n); + if (!keep) dv.push(o.getState_PrimitiveId()); +} +for (let i = 0; i < dl.length; i += 300) await eda.pcb_PrimitiveLine.delete(dl.slice(i, i + 300)); +for (let i = 0; i < dv.length; i += 300) await eda.pcb_PrimitiveVia.delete(dv.slice(i, i + 300)); +return {del_lines: dl.length, del_vias: dv.length}; +""" +JS_PUSH_LINES = u""" +const SEGS = %s, MIL = %f; let nl = 0; +for (const [net, lay, x0, y0, x1, y1, w] of SEGS) { + await eda.pcb_PrimitiveLine.create(net, lay, x0*MIL, y0*MIL, x1*MIL, y1*MIL, w*MIL); nl++; +} +return nl; +""" +JS_PUSH_VIAS = u""" +const VIAS = %s, MIL = %f; let nv = 0; +for (const [net, x, y] of VIAS) { + await eda.pcb_PrimitiveVia.create(net, x*MIL, y*MIL, %f*MIL, %f*MIL); nv++; +} +return nv; +""" +JS_PUSH_SAVE = u""" +await eda.pcb_Document.save(); +await new Promise(r => setTimeout(r, 2500)); +return 1; +""" + + +def push_sig(routes): + segs, vs = [], [] + for key, path in routes.items(): + net = netof(key) + s_, v_ = expand(path) + for x0, y0, x1, y1, lay, w in s_: + # 2026-09-07：穿过**本网焊盘中心**的线段在中心处拆成两段。EasyEDA 建一条穿过焊盘的线时会在焊盘中心截断、 + # 后半段直接丢掉（KEY_RCLK 穿 U22.12 去接出线段末端，板上只剩到焊盘中心那一半，DRC 连接性 2 条）。 + pts = [(x0, y0)] + L = math.hypot(x1 - x0, y1 - y0) + cuts = [] + for q in PADS_ALL: + if q['net'] != net or (q['lay'] != 12 and q['lay'] != lay) or L < 1e-6: + continue + t = ((q['x'] - x0) * (x1 - x0) + (q['y'] - y0) * (y1 - y0)) / (L * L) + if 0.02 < t < 0.98 and seg_pt(x0, y0, x1, y1, q['x'], q['y']) < 0.15: # 0.15 < 焊盘半宽 0.3，拆出的小折角仍在焊盘里 + cuts.append((t, q['x'], q['y'])) + for _t, qx, qy in sorted(cuts): + pts.append((qx, qy)) + pts.append((x1, y1)) + for (ax, ay), (bx, by) in zip(pts, pts[1:]): + segs.append([net, lay, round(ax, 4), round(ay, 4), round(bx, 4), round(by, 4), w]) + for x, y in v_: + vs.append([net, round(x, 4), round(y, 4)]) + nets = sorted(set(netof(k) for k in routes) - {'GND'}) + from eda import run + OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,1800));" % PCB) + + def call(js, what): + r = run(OPEN + js, timeout=600) + if not r.get('success'): + sys.exit(u'下发失败（%s）: %s' % (what, json.dumps(r, ensure_ascii=False)[:600])) + return r['result'] + # 2026-09-07：BM24 框里的 GND 梳子只有在这一轮**重画 GND** 时才删。 + # 原来无条件删：`--net HUB_RST ...` 补布把 65 个 BM24 GND 脚的逃逸段全删了没重画（gnd_patch 报 65 个悬空域）。 + has_gnd = any(netof(k) == 'GND' for k in routes) + d = call(JS_PUSH_DEL % (json.dumps(nets), json.dumps(gnd_boxes() if has_gnd else []), MIL), u'删旧铜') + nl = 0 + for i in range(0, len(segs), 250): + nl += call(JS_PUSH_LINES % (json.dumps(segs[i:i + 250]), MIL), u'建线 %d~' % i) + nv = 0 + for i in range(0, len(vs), 250): + nv += call(JS_PUSH_VIAS % (json.dumps(vs[i:i + 250]), MIL, VIA_H, VIA_D), u'建孔 %d~' % i) + call(JS_PUSH_SAVE, u'存盘') + print(u'下发完成：先删 %d 线 / %d 孔，再画 %d 线 / %d 孔（分批，每批 250）' + % (d['del_lines'], d['del_vias'], nl, nv)) + + +def _to_site_uv(n, x, y): + u"""板坐标 -> 站内 (u, v)。`to_board` 的逆。""" + x0, y0, rho = SITES[n] + if rho == 0: + return (x - x0, y - y0) + return (PW - (x - x0), PH - (y - y0)) + + +def j7_assert(pads, strict=True): + u"""**把上面那一堆 J7_* 常量和板上的实际焊盘对一遍**（五个站逐一）。 + + ⚠️ 这个断言是 2026-09-06 补的，起因是它不在的时候踩的坑： + v5 把 J7n 从 rot 180 改成 rot 0 又挪了位置，站内坐标整体差 + `u' = u − 5.00 / v' = 32.00 − v`，而脚本照旧用 v4 的常量 —— + `bm24_pre()` 于是在**空地上**画了五套梳子，净距校核全过（空地当然不撞）， + 只有 DRC 的连接性会含糊地多出几十条。⇒ 手写坐标必须有断言兜底。 + """ + bad = [] + for n in SITES: + by = {} + for p in pads: + if p['ref'] != 'J7%d' % n: + continue + u_, v_ = _to_site_uv(n, p['x'], p['y']) + by[p['num']] = (round(u_, 3), round(v_, 3), p['net'], p['lay']) + if not by: + bad.append(u'J7%d 一个焊盘都没找到' % n) + continue + want = ([(str(k), J7_GND_FRONT[i], J7_FRONT_V) for i, k in enumerate((2, 8, 12, 16, 24))] + + [(str(k), J7_GND_BACK[i], J7_BACK_V) for i, k in enumerate((1, 19, 23, 29, 37, 41, 47))] + + [('52', J7_GND_BIG, J7_MID_V)]) + for num, uu, vv in want: + got = by.get(num) + if not got: + bad.append(u'J7%d 没有 pin%s' % (n, num)); continue + if got[2] != 'GND': + bad.append(u'J7%d.pin%s 的网络是 %s，不是 GND' % (n, num, got[2])) + if abs(got[0] - uu) > 0.02 or abs(got[1] - vv) > 0.02: + bad.append(u'J7%d.pin%s 实测 (%.3f, %.3f)，常量写的是 (%.2f, %.2f)' + % (n, num, got[0], got[1], uu, vv)) + for num, uu, net in (('14', J7_THERM_U, 'THERM_%d' % n), ('22', J7_CC1_U, 'CC1_%d' % n)): + got = by.get(num) + if not got: + bad.append(u'J7%d 没有 pin%s' % (n, num)); continue + if got[2] != net: + bad.append(u'J7%d.pin%s 的网络是 %s，应为 %s' % (n, num, got[2], net)) + if abs(got[0] - uu) > 0.02 or abs(got[1] - J7_FRONT_V) > 0.02: + bad.append(u'J7%d.pin%s 实测 u=%.3f v=%.3f，常量 u=%.2f v=%.2f' + % (n, num, got[0], got[1], uu, J7_FRONT_V)) + if by.get('2') and by['2'][3] != L_BOT: + bad.append(u'J7%d 不在底层（lay=%s）—— bm24_pre 的路径层写死了 L_BOT' % (n, by['2'][3])) + # THERM / CC1 的靶子：R76n.1 / R77n.1 + for ref, uu, tag in (('R76%d' % n, J7_R76_PIN1_U, 'CC1'), ('R77%d' % n, J7_R77_PIN1_U, 'THERM')): + hit = [p for p in pads if p['ref'] == ref and p['num'] == '1'] + if not hit: + bad.append(u'找不到 %s.1' % ref); continue + u_, v_ = _to_site_uv(n, hit[0]['x'], hit[0]['y']) + if abs(u_ - uu) > 0.02 or abs(v_ - J7_R_PAD_V) > 0.02: + bad.append(u'%s.1（%s）实测 (%.3f, %.3f)，常量 (%.3f, %.3f)' + % (ref, tag, u_, v_, uu, J7_R_PAD_V)) + if bad: + for t in bad[:20]: + print(u' !! ' + t) + if strict: + sys.exit(u'\nBM24 的手写常量和板上对不上（%d 条）—— 先改常量再布线。' % len(bad)) + # 2026-09-07：pcb2_place 的 PW/PH 改成 67x44 后，站 1~3（rot 180）的元件在板上仍按旧 67.09x44.66 摆着， + # 和 plan() 差 (0.09, 0.66)。只重布不碰 J7n 的网络（如 POGO*）时降级成警告； + # 整板 --push 或重画 BM24 梳子之前必须先 pcb2_place.py --push 把站 1~3 摆到新坐标。 + print(u' ⚠ BM24 常量和板上对不上（%d 条），但这一轮 --net 的网络都不碰 J7n，按警告放行' % len(bad)) + return + print(u'BM24 手写常量与板上实测一致（五个站 × 13 个 GND 脚 + THERM/CC1 + R76n/R77n）✔') + + +def main(): + only = [a for a in sys.argv[1:] if not a.startswith('--')] + if '--refresh' in sys.argv: + from pcb2_route_dp import dump as _dump + _dump() + pads, vias, lines = geom() + ALL_NETS.update(p['net'] for p in pads if p['net']) + PADS_ALL[:] = pads + j7nets = set(p['net'] for p in pads if p['ref'].startswith('J7') and p['net']) + j7_assert(pads, strict=not only or bool(set(only) & j7nets)) + # ⚠️ 下发时要删掉五个 BM24 框里的旧 GND 铜（§25.8 自动扇出的产物）， + # 所以**算的时候就得当它们已经没了** —— 否则手写的车道会跟一堆 + # 马上就要消失的过孔"撞车"，而真正的冲突反而被淹没。 + boxes = gnd_boxes() + inbox = lambda x, y: any(b[0] <= x <= b[2] and b[1] <= y <= b[3] for b in boxes) + # ⚠️ 2026-09-06：带 `--net` 补布时只能摘**这一轮要重画的**网络，其余 115 个网络的旧铜是真障碍—— + # 原来按完整候选表摘，第二遍把 +3V3_HUB / +5V 直接画到第一遍的线上（DRC 319 条 0 mil）。 + mine = (set(only) if only else set(net_order())) - {'GND'} + n0 = len(vias) + len(lines) + # ① 本脚本负责的网络：下发时整网删掉重画，所以**算的时候就当它们不存在**。 + # 不摘的话，第二次跑会把自己上一轮的线当成障碍 —— 结果既不幂等， + # 还会在校核里刷出一堆「和马上要删掉的那条线撞了」的假冲突（实测 3 条）。 + # ② GND 只摘五个 BM24 框里的（§25.8 自动扇出的产物，下发时按框删）。 + vias = [v for v in vias + if v['net'] not in mine and not (v['net'] == 'GND' and inbox(v['x'], v['y']))] + lines = [l for l in lines + if l['net'] not in mine and not (l['net'] == 'GND' and inbox(l['x0'], l['y0']) + and inbox(l['x1'], l['y1']))] + print(u'障碍表：焊盘 %d / 过孔 %d / 铜层导线 %d（摘掉本脚本自己负责的旧铜 %d 件）' + % (len(pads), len(vias), len(lines), n0 - len(vias) - len(lines))) + order = [n for n in net_order() if not only or n in only] + obs = shapes_of(pads, vias, lines) + have = set(p['net'] for p in pads) + missing = [n for n in order if n not in have] + if missing: + sys.exit(u'网络表里没有这些网络：%s' % missing) + + # ⚠️ `+3V3_HUB` 上**已经有铜**：`pcb2_dp_long.py` 在 Hub 西缘画了三条 + # （pin5 / pin10 / 顶层干线，15 段 + 4 个孔）。它们被 D± 夹在中间， + # 是差分那一轮算出来的、后面的布线器再也挤不进去的位置。 + # 而 `push_sig()` 的做法是「把本脚本负责的网络整网删掉重画」—— + # 不管的话这三条会被静默抹掉，只在 DRC 里冒出几条连接性错误。 + # ⇒ 从**同一个事实来源**（`pcb2_dp_long.build`）取回来当本网的前置段： + # 既让最小生成树知道这些焊盘已经连上了，下发时也原样重画。 + from pcb2_dp_long import build as _dp_long_build + _kept = [q for k, q in _dp_long_build(pads).items() if netof(k) == '+3V3_HUB'] + if len(_kept) != 3: + sys.exit(u'pcb2_dp_long 里的 +3V3_HUB 前置段应有 3 条，实际 %d 条' % len(_kept)) + # U32 的 7 个 +3V3 脚里，**pin46 在东排、四周被 VBUS_DET / NONREM0 围死**， + # 它唯一的出路是往 QFN **肚子里**走：南排焊盘上沿 63.975 与散热盘南沿 65.60 + # 之间有一条 1.6 mm 的死带（芯片底下，没有别人要用）。 + # 单独跑 `--net +3V3_HUB` 时布线器自己就是这么走的；但排在 Hub 那几根配置线之后跑， + # 那个内角已经被占掉 ⇒ 干脆手写成前置段，和 BM24 的梳子一样**先占住**。 + # (102.25, 63.975) 是 pin52 焊盘的北沿；45° 斜段离 pin51 焊盘框 0.50、 + # 东行段离 pin47/pin45 焊盘框各 0.35（0.24 的线要 0.32）✔ + PRE['+3V3_HUB'] = _kept + [[(102.250, 63.550, L_BOT, 0.24), + (102.250, 64.125, L_BOT, 0.24), + (103.375, 65.250, L_BOT, 0.24), + (104.450, 65.250, L_BOT, 0.24)], + # R716.2（HUB_RST 的上拉）是最东边那颗 +3V3 焊盘， + # 夹在 R711.2 / R720.2 两个 GND 脚之间（南北各 1.2 mm）， + # 只能**翻顶层**从 C750.1 斜拉过来。同样先占住。 + # 两个孔位都是卡着算的： + # 西孔 (105.95, 63.825)：离 R710.2 那条 0.15 扇出线 0.624（要 0.58） + # —— 原来放在 105.88 只有 0.566，差 14 µm； + # 东孔 (109.60, 66.45)：离 `USB5_DP` 竖段 (x 110.30) 0.70（要 0.645） + # —— 原来放在 109.72 只有 0.58，差 65 µm。 + [(105.950, 63.450, L_BOT, 0.35), + (105.950, 63.825, L_BOT, 0.35), + (105.950, 63.825, L_TOP, 0.35), + (106.275, 64.150, L_TOP, 0.35), + (107.300, 64.150, L_TOP, 0.35), + (109.600, 66.450, L_TOP, 0.35), + (109.600, 66.450, L_BOT, 0.35), + (109.333, 66.450, L_BOT, 0.35)]] + PRE.get('+3V3_HUB', []) + print(u'+3V3_HUB 保留 pcb2_dp_long 画的 3 条前置段（%d 段导线 / %d 个孔）' + % (sum(len(expand(q)[0]) for q in _kept), sum(len(expand(q)[1]) for q in _kept))) + + # `HUB_RST`：U32.43 (104.45, 66.75) 到 R716.1 (108.467, 66.45) 之间只有 + # R709(y 65.85) 与 R712(y 67.05) 之间那条 **0.66 mm** 的缝。 + # 0.20 的线走它是够的（上下各 0.23 ≥ 0.20），但**栅格布线器进不去**： + # 它的判据是 `edt >= 0.20 + 0.10 + QERR(0.0708) = 0.371`，而半缝只有 0.33。 + # ⇒ 这一段也手写。（不是布线器的 bug —— 0.1 mm 栅格就是分辨不出 0.03 的余量。） + # ⚠️ 这一段**必须 0.15 不能 0.20**，两处都是算死的： + # 转折点 a 的窗口：往西受 U32.44 焊盘框（东沿 104.875）挡，a >= 104.875 + (w/2+0.20)； + # 往东受 R712.1 焊盘框西南角 (105.584, 66.780) 挡（45° 斜段的垂距）。 + # w=0.20 时窗口只有 15 µm（105.175~105.190），w=0.15 时有 75 µm ⇒ 取 105.19。 + # 东行段 y=66.45 离 (107.624, 67.050) 那个 GND 扇出孔 0.600： + # w=0.20 要 0.605（差 5 µm 不过），w=0.15 要 0.58 ✔ + PRE['HUB_RST'] = [[(104.450, 66.750, L_BOT, 0.15), + (105.190, 66.750, L_BOT, 0.15), + (105.490, 66.450, L_BOT, 0.15), # 45° + (108.467, 66.450, L_BOT, 0.15)]] + + # `VBUS_DET`：U32.44 (104.45, 66.25) 到 R709.2 (105.867, 65.85) —— 和 HUB_RST 同一个口袋。 + # HUB_RST 的手写段占了 y 66.45 那条线之后，这一小段的余量掉到栅格分辨不出来的量级， + # 所以一起手写。45° 斜段离 HUB_RST 斜段 0.4525（要 0.375）、离 U32.45 焊盘框 0.371（要 0.30）。 + PRE['VBUS_DET'] = [[(104.450, 66.250, L_BOT, W_SIG), + (105.050, 66.250, L_BOT, W_SIG), + (105.450, 65.850, L_BOT, W_SIG), # 45° + (105.867, 65.850, L_BOT, W_SIG)]] + + # `+5V`：J32.39 与 J32.40 是排母上下相邻的两针，中间 2.54 mm。 + # 上一轮布线器给 J32.39 留的出线段末端**正好落在 J32.40 的焊盘圈里**（差 0.077）， + # 本脚本的连通域判定认了，EasyEDA 的连接性检查不认 —— DRC 报 + # 「导线 (+5V) 与其他相同网络的对象断开了连接」+「插件焊盘 J32_39 断开」。 + # ⇒ 两针之间直接连一根顶层短线，端点落在焊盘中心，谁都不会误判。 + PRE['+5V'] = [[(182.1298, 68.770, L_TOP, 0.60), + (182.1298, 66.230, L_TOP, 0.60)]] + + pre_pads = set() + for net, ps in PRE.items(): + for p in ps: + for q in pads: + if q['net'] == net and seg_rect((p[0][0], p[0][1]), (p[0][0], p[0][1]), + q['x'], q['y'], q['hw'], q['hh']) < 1e-6: + pre_pads.add((q['ref'], q['num'])) + # ⚠️ **所有前置段一开始就进障碍表**（带各自的网络名）。 + # 原来只有 GND 的在循环里补进去，THERM/CC1/+3V3 的要等轮到自己才进 —— + # 于是排在它们前面的网络看不见这些手写坐标，照样从上面碾过去。 + for _net, _ps in PRE.items(): + for _p in _ps: + _sg, _vv = expand(_p) + for _x0, _y0, _x1, _y1, _lay, _w in _sg: + obs.append((sh_seg(_x0, _y0, _x1, _y1, _w, _lay), _net)) + for _x, _y in _vv: + obs.append((sh_via(_x, _y), _net)) + stubs, stub_alts = plan_stubs(order, pads, obs, pre_pads) + print(u'预留出线段 %d 条' % len(stubs)) + + routes, failed = {}, [] + t0 = time.time() + for net in order: + t = time.time() + if net in PRE_ONLY: + # GND 不做最小生成树 —— 它靠 Inner2 整板地平面 + §25.8 的扇出连通， + # 这里只补 BM24 那 65 个脚的逃逸段（`bm24_pre`），照原样落盘。 + ps = list(PRE[net]) + for p in ps: + for x0, y0, x1, y1, lay, w in expand(p)[0]: + obs.append((sh_seg(x0, y0, x1, y1, w, lay), net)) + for x, y in expand(p)[1]: + obs.append((sh_via(x, y), net)) + ok = True + else: + ps = route_net(net, pads, obs, pre=PRE.get(net), verbose=True, + stubs=stubs, alts=stub_alts) + ok = _wire_ok(net, ps, pads) + if not ok: + failed.append(net) + for k, p in enumerate(ps): + routes[net if k == 0 else '%s%s%d' % (net, KSEP, k + 1)] = p + print(u' %-12s %2d 段路径 / %3d 导线 / %2d 过孔 %5.1fs %s' + % (net, len(ps), sum(len(expand(q)[0]) for q in ps), + sum(len(expand(q)[1]) for q in ps), time.time() - t, + u'' if ok else u' ← 有端点没连上')) + print(u'\n%d 个网络 / %d 条路径 / %d 段导线 / %d 个过孔 （%.0f 秒）' + % (len(order), len(routes), sum(len(expand(p)[0]) for p in routes.values()), + sum(len(expand(p)[1]) for p in routes.values()), time.time() - t0)) + if failed: + print(u'⚠️ %d 个网络没布通：%s' % (len(failed), u' '.join(failed))) + + # ── 45° 化（2026-09-06 用户拍板：全板不许有直角走线）── + # 放在**布完之后统一做**，而不是每条路径各切各的： + # 斜切只会拿掉铜，所以拿"未切之前"的其它段做校核是保守且正确的。 + n0 = len(sharp_corners(routes)) + t = time.time() + raw = dict(routes) + routes = chamfer_routes(routes, pads, vias, lines, smooth=True) + # ⚠️ `smooth=True` 会挪动路径（最多 0.15 mm），不只是拿掉铜；而它的净距校核拿的是切之前的自身路径 + # ⇒ 切完再 check()，把牵涉到违规的那几条整条退回未切版本（下板 pcb1_route_sig §26.15 同款； + # 2026-09-06 载板 `$22N139` 就这么被抹到 GND 线上 −0.200）。 + for _round in range(4): + bad0 = check(routes, pads, vias, lines, verbose=False) + hurt = set() + for t_, n1, n2, lay_, d_, a_, b_ in bad0: + for key, path in routes.items(): + if netof(key) not in (n1, n2) or key not in raw or routes[key] == raw[key]: + continue + for x0, y0, x1, y1, ll, ww in expand(path)[0]: + if seg_seg((x0, y0), (x1, y1), a_, b_) < 1e-6: + hurt.add(key) + break + if not hurt: + break + print(u' 45° 化后有 %d 条压线，把 %s 退回未切的版本' % (len(bad0), ' '.join(sorted(netof(k) for k in hurt)))) + for k in hurt: + routes[k] = raw[k] + # ── 换层点 45° 化（2026-09-07 用户要求）── + nv0 = len(via_corners(routes)) + raw2 = dict(routes) + routes, ncut = via_chamfer_routes(routes, pads, vias, lines) + for _round in range(4): + bad0 = check(routes, pads, vias, lines, verbose=False) + hurt = set() + for t_, n1, n2, lay_, d_, a_, b_ in bad0: + for key, path in routes.items(): + if netof(key) not in (n1, n2) or key not in raw2 or routes[key] == raw2[key]: + continue + for x0, y0, x1, y1, ll, ww in expand(path)[0]: + if seg_seg((x0, y0), (x1, y1), a_, b_) < 1e-6: + hurt.add(key) + break + for vx, vy in expand(path)[1]: + if seg_seg((vx, vy), (vx, vy), a_, b_) < 1e-6: + hurt.add(key) + break + if not hurt: + break + print(u' 换层 45° 化后有 %d 条压线，把 %s 退回' % (len(bad0), ' '.join(sorted(netof(k) for k in hurt)))) + for k in hurt: + routes[k] = raw2[k] + nv1 = len(via_corners(routes)) + print(u'换层点直角：%d -> %d（切了 %d 处）' % (nv0, nv1, ncut)) + + # ── 端点复接（2026-09-07 第三十轮）── + # 切角会挪走直角处的铜，而后布的支路起点可能正钉在那个角上（VBUS2 (105.9,99.1)、+3V3_HUB (198.1,70.0)）； + # 另外从整坨出发的路径起点也可能落在圆焊盘外接矩形的角上（J32.7/9、J32.40）。 + # 统一在这里兜底：路径两端若不在本网任何铜（别的路径 / 过孔 / 焊盘）里，补一段接到最近的本网铜。 + nfix = reanchor_routes(routes, pads) + if nfix: + print(u' 端点复接：补了 %d 段' % nfix) + left = sharp_corners(routes) + print(u'\n45° 化：直角拐点 %d -> %d（%.0f 秒）' % (n0, len(left), time.time() - t)) + for key, i, xy, ang in left[:20]: + print(u' [!!] 切不动: %-12s (%.2f, %.2f) 转向 %.0f°' % (key, xy[0], xy[1], ang)) + if len(left) > 20: + print(u' （还有 %d 处）' % (len(left) - 20)) + + print(u'\n净距校核（%.2f mm）:' % CLR) + bad = check(routes, pads, vias, lines) + if not bad: + print(u' 全部通过 ✔') + json.dump({k: [list(map(float, q[:2])) + [int(q[2]), float(q[3])] for q in v] + for k, v in routes.items()}, + io.open(OUT, 'w', encoding='utf-8')) + print(u'路径已存 %s' % os.path.basename(OUT)) + + if '--push' in sys.argv: + if bad: + sys.exit(u'\n!! 净距还有问题，不下发。') + if failed and '--force' not in sys.argv: + sys.exit(u'\n!! 还有 %d 个网络没布通，要下发请加 --force。' + u'（没布通的网络只会落下几截悬空的出线段，' + u'下一轮 --push 会把它们连同别的一起删掉重画。）' % len(failed)) + push_sig(routes) + + +def _wire_ok(net, paths, pads_all): + u"""这个网络是不是**真的连成一坨**（按实际铜算连通域，不看 DRC）。 + + ⚠️ 判据必须是"连通域 == 1"，**不能是"每个焊盘都被某条线碰到"**。 + 每个焊盘出门时都先画了一小截 `entry_stub`，所以"被碰到"永远成立 —— + 第一版就是这么写的，于是 20 个断开的网络里只报出 5 个， + 另外 15 个各自剩着一截悬空的出线段，几何校核还全绿。 + """ + items = [] # (层集合, 种类, 数据) + for q in pads_all: + if q['net'] == net: + lay = {L_TOP, L_BOT} if q['lay'] == 12 else {q['lay']} + items.append((lay, 'pad', (q['x'], q['y'], q['hw'], q['hh']))) + for p in paths: + segs, vs = expand(p) + for x0, y0, x1, y1, lay, w in segs: + items.append(({lay}, 'seg', (x0, y0, x1, y1, w / 2.0))) + for x, y in vs: + items.append(({L_TOP, L_BOT}, 'via', (x, y, VIA_R))) + n = len(items) + if n < 2: + return True + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + def touch(a, b): + la, ka, da = a + lb, kb, db = b + if not (la & lb): + return False + if ka > kb: + return touch(b, a) + if ka == 'pad' and kb == 'pad': + return (abs(da[0] - db[0]) <= da[2] + db[2] + 1e-6 + and abs(da[1] - db[1]) <= da[3] + db[3] + 1e-6) + if ka == 'pad' and kb == 'seg': + return seg_rect((db[0], db[1]), (db[2], db[3]), da[0], da[1], da[2], da[3]) <= db[4] + 1e-6 + if ka == 'pad' and kb == 'via': + return seg_rect((db[0], db[1]), (db[0], db[1]), da[0], da[1], da[2], da[3]) <= db[2] + 1e-6 + if ka == 'seg' and kb == 'seg': + return seg_seg((da[0], da[1]), (da[2], da[3]), + (db[0], db[1]), (db[2], db[3])) <= da[4] + db[4] + 1e-6 + if ka == 'seg' and kb == 'via': + return seg_pt(da[0], da[1], da[2], da[3], db[0], db[1]) <= da[4] + db[2] + 1e-6 + return math.hypot(da[0] - db[0], da[1] - db[1]) <= da[2] + db[2] + 1e-6 + + for i in range(n): + for j in range(i + 1, n): + if find(i) != find(j) and touch(items[i], items[j]): + par[find(i)] = find(j) + return len(set(find(i) for i in range(n))) == 1 + + +if __name__ == '__main__': + main() diff --git a/.claude/pcb2_rules.py b/.claude/pcb2_rules.py index 9ee8471..7c66dd9 100644 --- a/.claude/pcb2_rules.py +++ b/.claude/pcb2_rules.py @@ -11,6 +11,21 @@ u"""载板 PCB2-CARRIER 设计规则 + D± 差分对（2026-09-05）。 · 写进去的 mm 会被换算成 mil 再换回来，`0.2` 回读是 `0.19999959999999997`， 任何几何比较都留 1e-4 容差 +## ⚠⚠ 必须在「从原理图导入变更」**之后**跑（2026-09-08 实测） + +网络指派（差分对 / 线宽 / 铺铜连接方式）是**按网络名**挂上去的， +而网络是元件导入时才在 PCB 上出现的。在空板上跑本脚本： + + 差分对 0 / 11 对 + 线宽指派 0 / 12 个网络 + 铺铜全连接指派 0 / 5 个网络 + +—— **而“规则配置已下发”那几行照常打印成功**，看上去像做完了。 +导入元件后重跑一次就是 11/11、12/12、5/5。 + +⇒ 重建板子的顺序是：**切 4 层 → 导入元件 → 下规则 → 摆位**。 +判据就是上面那三个分数，不是“没报错”。 + ## 和下板不同的三处 1. **差分对 11 对，不是 7 对。** 载板上每一路 D± 被 ESD 器件 `U5n` 切成两段： @@ -51,7 +66,7 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) from eda import run -PCB = 'f126ffb29c92f9b2' # PCB2-CARRIER +PCB = '942ed1560d81c1e7' # PCB2-CARRIER # ── 线宽规则（mm）────────────────────────────────────────────────────── TRACK_RULES = { diff --git a/.claude/pcb2_snapshot.py b/.claude/pcb2_snapshot.py index ace0a16..12d5820 100644 --- a/.claude/pcb2_snapshot.py +++ b/.claude/pcb2_snapshot.py @@ -1,52 +1,52 @@ -# -*- coding: utf-8 -*- -u"""把载板 PCB2 当前的全部铜/元件状态落成一个 JSON（可回滚的安全网）。 - - /c/Python314/python .claude/pcb2_snapshot.py - -抓：元件 (位号,x,y,rot,layer)、导线、过孔、铺铜(含多边形)、自由焊盘、layer 11 多段线、填充。 -单位 mil（EasyEDA 原生），不换算。 -""" -import io, json, os, sys -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -from eda import run - -PCB = 'f126ffb29c92f9b2' -JS = u""" -await eda.dmt_EditorControl.openDocument('%s'); -await new Promise(r=>setTimeout(r,1500)); -const out = {comps:[], lines:[], vias:[], pours:[], fills:[], pads:[], polys:[], arcs:[]}; -for (const c of await eda.pcb_PrimitiveComponent.getAll()) - out.comps.push([c.getState_Designator(), c.getState_X(), c.getState_Y(), c.getState_Rotation(), c.getState_Layer()]); -for (const l of await eda.pcb_PrimitiveLine.getAll()) - out.lines.push([l.layer, l.startX, l.startY, l.endX, l.endY, l.lineWidth, l.net]); -for (const a of await eda.pcb_PrimitiveArc.getAll()) - out.arcs.push([a.layer, a.net, JSON.stringify(a).slice(0, 400)]); -for (const v of await eda.pcb_PrimitiveVia.getAll()) - out.vias.push([v.x, v.y, v.holeDiameter, v.diameter, v.net]); -for (const p of await eda.pcb_PrimitivePour.getAll()) { - let poly = null; try { poly = p.complexPolygon; } catch(e) {} - out.pours.push({layer: p.layer, net: p.net, name: p.pourName, prio: p.pourPriority, fill: p.pourFillMethod, - poly: poly ? JSON.parse(JSON.stringify(poly)) : null}); -} -for (const f of await eda.pcb_PrimitiveFill.getAll()) - out.fills.push({layer: f.layer, net: f.net, raw: JSON.parse(JSON.stringify(f)).complexPolygon || null}); -for (const p of await eda.pcb_PrimitivePad.getAll()) { - const pid = p.getState_PrimitiveId(); - out.pads.push([pid, p.getState_PadNumber(), p.getState_Layer(), p.getState_X(), p.getState_Y(), p.getState_Net()]); -} -for (const p of await eda.pcb_PrimitivePolyline.getAll()) - out.polys.push({layer: p.layer, raw: JSON.parse(JSON.stringify(p))}); -return out; -""" % PCB - -if __name__ == '__main__': - r = run(JS, timeout=300) - if not r.get('success'): - print(json.dumps(r, ensure_ascii=False)[:800]); sys.exit(1) - res = r['result'] - out = os.path.join(HERE, sys.argv[1] if len(sys.argv) > 1 else '_pcb2_snap.json') - io.open(out, 'w', encoding='utf-8').write(json.dumps(res)) - print(u'元件 %d / 导线 %d / 弧 %d / 过孔 %d / 铺铜 %d / 填充 %d / 焊盘 %d / 多段线 %d -> %s' % ( - len(res['comps']), len(res['lines']), len(res['arcs']), len(res['vias']), len(res['pours']), - len(res['fills']), len(res['pads']), len(res['polys']), out)) +# -*- coding: utf-8 -*- +u"""把载板 PCB2 当前的全部铜/元件状态落成一个 JSON（可回滚的安全网）。 + + /c/Python314/python .claude/pcb2_snapshot.py + +抓：元件 (位号,x,y,rot,layer)、导线、过孔、铺铜(含多边形)、自由焊盘、layer 11 多段线、填充。 +单位 mil（EasyEDA 原生），不换算。 +""" +import io, json, os, sys +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from eda import run + +PCB = '942ed1560d81c1e7' +JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,1500)); +const out = {comps:[], lines:[], vias:[], pours:[], fills:[], pads:[], polys:[], arcs:[]}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) + out.comps.push([c.getState_Designator(), c.getState_X(), c.getState_Y(), c.getState_Rotation(), c.getState_Layer()]); +for (const l of await eda.pcb_PrimitiveLine.getAll()) + out.lines.push([l.layer, l.startX, l.startY, l.endX, l.endY, l.lineWidth, l.net]); +for (const a of await eda.pcb_PrimitiveArc.getAll()) + out.arcs.push([a.layer, a.net, JSON.stringify(a).slice(0, 400)]); +for (const v of await eda.pcb_PrimitiveVia.getAll()) + out.vias.push([v.x, v.y, v.holeDiameter, v.diameter, v.net]); +for (const p of await eda.pcb_PrimitivePour.getAll()) { + let poly = null; try { poly = p.complexPolygon; } catch(e) {} + out.pours.push({layer: p.layer, net: p.net, name: p.pourName, prio: p.pourPriority, fill: p.pourFillMethod, + poly: poly ? JSON.parse(JSON.stringify(poly)) : null}); +} +for (const f of await eda.pcb_PrimitiveFill.getAll()) + out.fills.push({layer: f.layer, net: f.net, raw: JSON.parse(JSON.stringify(f)).complexPolygon || null}); +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const pid = p.getState_PrimitiveId(); + out.pads.push([pid, p.getState_PadNumber(), p.getState_Layer(), p.getState_X(), p.getState_Y(), p.getState_Net()]); +} +for (const p of await eda.pcb_PrimitivePolyline.getAll()) + out.polys.push({layer: p.layer, raw: JSON.parse(JSON.stringify(p))}); +return out; +""" % PCB + +if __name__ == '__main__': + r = run(JS, timeout=300) + if not r.get('success'): + print(json.dumps(r, ensure_ascii=False)[:800]); sys.exit(1) + res = r['result'] + out = os.path.join(HERE, sys.argv[1] if len(sys.argv) > 1 else '_pcb2_snap.json') + io.open(out, 'w', encoding='utf-8').write(json.dumps(res)) + print(u'元件 %d / 导线 %d / 弧 %d / 过孔 %d / 铺铜 %d / 填充 %d / 焊盘 %d / 多段线 %d -> %s' % ( + len(res['comps']), len(res['lines']), len(res['arcs']), len(res['vias']), len(res['pours']), + len(res['fills']), len(res['pads']), len(res['polys']), out)) diff --git a/.claude/pcb2_vo_vias.py b/.claude/pcb2_vo_vias.py index 9eb91ea..c680943 100644 --- a/.claude/pcb2_vo_vias.py +++ b/.claude/pcb2_vo_vias.py @@ -1,434 +1,435 @@ -# -*- coding: utf-8 -*- -u"""五路 `VOn_P` 的**贴片电容接到 Inner1 电源岛** —— 每个焊盘旁边打一个过孔。 - - /c/Python314/python .claude/pcb2_route_dp.py --dump # 1. 先刷障碍表 - /c/Python314/python .claude/pcb2_vo_vias.py # 2. 只算 + 本地净距校核 - /c/Python314/python .claude/pcb2_vo_vias.py --push # 3. 下发 - /c/Python314/python .claude/pcb2_pour.py --push # 4. **必须重铺**（新过孔要反焊盘） - -## 为什么要有这一步 - -`VO1_P`~`VO5_P` 每个网络 10 个焊盘：**5 个通孔**（`C8n1.1` Ø10 电解正极、`TP8n1` -测试点、排母 3 针）本身就落在 Inner1 的岛上，不用管；剩下 **5 个贴片焊盘** -（`C8n2`/`C8n3` 100µF 1206、`C8n4`/`C8n5` 22µF 1206、`C8n6` 100nF 0402） -只有顶层铜，**和岛之间没有任何通路** —— 这就是 §25.14 里连接性 51 条中的 31 条。 - -所以这一步和布线不是一回事：不需要找路径，只需要**在焊盘边上打一个过孔**， -用一小段线接过去，垂直下到 Inner1 的岛上。25 个焊盘 = 25 个过孔。 - -## 选点判据（不是"看着差不多"） - -| | | -|---|---| -| 方向 | 只取 8 个方向（0/45/90…），**不许出现斜的怪角度**（全板 45° 化，§25.14）| -| 起步距离 | 过孔铜边到本焊盘矩形 **≥ 0.15 mm**（同网，不是 DRC 约束，是不想做 via-in-pad）| -| 净距 | 过孔和那一小段线对**异网**焊盘/过孔/导线 ≥ 0.20 —— 直接借 `pcb2_route_dp.check()` | -| 岛内余量 | 过孔中心离岛多边形边界 ≥ 0.61/2 + 0.30 = **0.605 mm**，免得铺出来只搭上一点点 | -| 线宽 | `PWR4A` 最小 0.30；从 1.00 起往下退让，取第一个过的 | - -⚠️ 过孔打在**路径末点**上 —— `expand()` 会静默丢掉末端过孔（§25.14 那条最阴的 bug）。 - 这里靠把末点写两遍绕开（`_path()` 里 `(vx,vy,L_BOT)` 后面再来一份）。 -""" -import json -import math -import os -import sys - -HERE = os.path.dirname(os.path.abspath(__file__)) -sys.path.insert(0, HERE) -import pcb2_route_dp as R -from pcb2_pour import ISLANDS, island_poly - -W_STEPS = [1.00, 0.80, 0.60, 0.50, 0.40, 0.30] # PWR4A 的 strokeWidthMin = 0.30 -PAD_GAP = 0.15 # 过孔铜边到本焊盘的余量（同网，防 via-in-pad） -EDGE_IN = R.VIA_D / 2.0 + 0.30 # 过孔中心到岛边界的余量 -D_MAX = 3.5 -D_STEP = 0.05 -DRILL = 0.33 # 钻孔间距（规则 otherClearance / copperThickness1oz 都要求 >= 11.8mil - # = 0.2997 mm），留 30 µm 余量。再大就过不了 J23 的屏蔽脚，见 place() 的注释 -DIRS = [(math.cos(math.radians(a)), math.sin(math.radians(a))) for a in range(0, 360, 45)] - -# ── 哪些位号要打孔、各打几个 ───────────────────────────────────────── -# 2026-09-06 补两类（上一版只有 25 个贴片电容）： -# -# `C8n1.1` —— 换成 Rubycon 6.3TPV2200M10X10.5 之后**是贴片**（V-chip）， -# 原来当它是直插电解、以为正极自己就落在岛上，其实一点铜都不通。 -# `J8n.1` —— 电池排线改成 4 焊盘直焊（§13.5 末尾）之后，P+ 也是贴片。 -# `TP8n1` 那个通孔测试点已经取消 ⇒ **每路 VOn_P 现在只剩排母那 3 针是通孔**。 -# -# 个数按设计文档 §10.3「0.3 mm 孔单孔 1~1.5 A，功率网络每个焊盘打 3 个」： -# · `J8n.1` 是这一路 **4 A 的唯一去路**（岛 → 排线 → 手机），必须 3 个； -# · `C8n1.1` 是 2200 µF 的主储能，纹波电流也走它，给 3 个； -# · `C8n2`~`C8n6` 只承担高频纹波，各 1 个 —— 全按 3 个来会往五块岛里 -# 再钻 50 个反焊盘，最窄断面（下限 7.0 mm）扛不住。这是本项目对 §10.3 的 -# 一处**有意偏离**，见 PROGRESS。 -N_VIA = {} -REFS = [] -for _m in range(5): - REFS.append('C8%d1' % _m) - N_VIA['C8%d1' % _m] = 3 - REFS += ['C8%d%d' % (_m, _k) for _k in range(2, 7)] - REFS.append('J8%d' % (_m + 1)) - N_VIA['J8%d' % (_m + 1)] = 3 -CAPS = REFS - - -def poly_of(net): - for _name, n, main, neck in ISLANDS: - if n == net: - return island_poly(main, neck) - raise KeyError(net) - - -def inside(poly, x, y, margin): - u"""点在多边形内，且离每条边 >= margin。岛都是轴对齐的凸/凹矩形拼接，用射线法 + 边距。""" - c = False - n = len(poly) - for i in range(n): - ax, ay = poly[i] - bx, by = poly[(i + 1) % n] - if (ay > y) != (by > y) and x < ax + (bx - ax) * (y - ay) / (by - ay): - c = not c - if not c: - return False - for i in range(n): - ax, ay = poly[i] - bx, by = poly[(i + 1) % n] - if R.seg_pt(ax, ay, bx, by, x, y) < margin: - return False - return True - - -def pad_dist(px, py, hw, hh, x, y): - u"""点到轴对齐焊盘矩形的距离（0 = 在里面）。""" - return math.hypot(max(abs(x - px) - hw, 0.0), max(abs(y - py) - hh, 0.0)) - - -def _path(px, py, vx, vy, w): - u"""末点上的过孔要把点写两遍，否则 expand() 会把它丢掉（§25.14）。""" - return [(px, py, R.L_TOP, w), (vx, vy, R.L_TOP, w), - (vx, vy, R.L_BOT, w), (vx, vy, R.L_BOT, w)] - - -NEAR = 8.0 # 只拿焊盘 8 mm 以内的东西当障碍（全表 816+393+1373，全查太慢） - - -def holes(pads): - u"""每个**带钻孔的焊盘**的孔 -> 一段胶囊 (a, b, r)（圆孔就是 a == b）。 - - **两类孔的待遇不一样**（2026-09-06 用 DRC 一条条试出来的）： - - | | 线能不能压上去 | 过孔能不能靠近 | - |---|---|---| - | 焊盘自己的孔（`SLOT` / `ROUND`，金属化）| **能** —— 它就是焊盘的一部分 | 不能，钻孔间距 | - | 封装自带的非金属化孔（`npth=True`）| **不能**，DRC 报「挖槽区域 到 导线」| 不能 | - - 一开始把两类混在一起判，结果是「谁都连不上 J23 的屏蔽脚」—— - 槽孔焊盘的**任何一点**离自己的槽都不足 0.80 mm，按那个判据连焊盘都碰不得。 - - 槽的长轴按焊盘的长轴定（`_pcb2_route_geom.json` 里的 hw/hh 已经是转过的）， - `_pcb2_pads_full.json` 只存了孔的两个尺寸、没存角度，所以只能这么反推。 - """ - out = [] - # ⚠️ 封装自带的非金属化孔（J23 那两个 Ø0.60）**API 一个都读不出来**， - # 只能从内层铺铜的反焊盘反推 —— `pcb2_npth.py --write` 生成这份清单。 - # 没有它的话，「从 A1B12 往东拉线打孔」这条最自然的走法会被 DRC - # 以「挖槽区域 到 导线 距离 0mil」打回来，而净距校核一条都不报。 - try: - for cx, cy, r in json.load(open(os.path.join(HERE, '_pcb2_npth.json'), encoding='utf-8')): - out.append({'net': None, 'npth': True, 'a': (cx, cy), 'b': (cx, cy), 'r': r}) - except Exception: - print(u' [!] 没有 _pcb2_npth.json —— 先跑 pcb2_npth.py --write，否则封装自带的孔看不见') - full = json.load(open(os.path.join(HERE, '_pcb2_pads_full.json'), encoding='utf-8')) - bykey = {} - for ref, num, _net, _lay, _x, _y, _shape, hole in full: - if hole: - bykey[(ref, num)] = hole - for p in pads: - h = bykey.get((p['ref'], p['num'])) - if not h: - continue - if h[0] == 'ROUND': - r = float(h[1]) / R.MIL / 2.0 - out.append({'net': p['net'], 'npth': False, - 'a': (p['x'], p['y']), 'b': (p['x'], p['y']), 'r': r}) - continue - w, L = sorted((float(h[1]) / R.MIL, float(h[2]) / R.MIL)) # 槽宽 / 槽长 - r, ext = w / 2.0, (L - w) / 2.0 - if p['hw'] >= p['hh']: # 焊盘长轴在 x 上 - out.append({'net': p['net'], 'npth': False, - 'a': (p['x'] - ext, p['y']), 'b': (p['x'] + ext, p['y']), 'r': r}) - else: - out.append({'net': p['net'], 'npth': False, - 'a': (p['x'], p['y'] - ext), 'b': (p['x'], p['y'] + ext), 'r': r}) - return out - - -def local(pads, vias, lines, px, py, hl=()): - return ([p for p in pads if abs(p['x'] - px) < NEAR and abs(p['y'] - py) < NEAR], - [v for v in vias if abs(v['x'] - px) < NEAR and abs(v['y'] - py) < NEAR], - [l for l in lines - if R.seg_pt(l['x0'], l['y0'], l['x1'], l['y1'], px, py) < NEAR], - [h for h in hl if abs(h['a'][0] - px) < NEAR and abs(h['a'][1] - py) < NEAR]) - - -def fits(net, segs, via, lp, lv, ll, lh, mine, mvias): - u"""几段线 + 一个过孔对**异网**的净距都 >= CLR？ - - `segs` = [(lay, x0, y0, x1, y1, w), ...]（本次要画的） - `via` = (x, y) 或 None - `mine` = 本轮已定的线 [(net, lay, x0, y0, x1, y1, w), ...] - `mvias` = 本轮已定的孔 [(net, x, y), ...] - `lh` = 附近的钻孔胶囊（`holes()` 的输出）；**不分网络**，钻孔和铜是两条规则 - - ⚠️ 线的层必须逐段拿，**不能写死顶层** —— 底层的 0402 - 第一版就是这么错的，本地判完全过、到 `check()` 才炸。 - """ - Rv = R.VIA_D / 2.0 - - def seg_bad(lay, x0, y0, x1, y1, w): - h, a, b = w / 2.0, (x0, y0), (x1, y1) - for p in lp: - if p['lay'] != 12 and p['lay'] != lay: - continue - if p['net'] != net: - if R.seg_rect(a, b, p['x'], p['y'], p['hw'], p['hh']) - h < R.CLR - 1e-4: - return True - - for v in lv: - if v['net'] == net: - continue - if R.seg_pt(x0, y0, x1, y1, v['x'], v['y']) - v['r'] - h < R.CLR - 1e-4: - return True - for l in ll: - if l['net'] == net or l['lay'] != lay: - continue - if R.seg_seg(a, b, (l['x0'], l['y0']), (l['x1'], l['y1'])) - h - l['w'] / 2.0 < R.CLR - 1e-4: - return True - for n2, l2, ax, ay, bx, by, w2 in mine: - if n2 == net or l2 != lay: - continue - if R.seg_seg(a, b, (ax, ay), (bx, by)) - h - w2 / 2.0 < R.CLR - 1e-4: - return True - for n2, vx, vy in mvias: - if n2 == net: - continue - if R.seg_pt(x0, y0, x1, y1, vx, vy) - Rv - h < R.CLR - 1e-4: - return True - for q in lh: # 线只躲**非金属化**孔；焊盘自己的孔是焊盘的一部分 - if q['npth'] and R.seg_seg(a, b, q['a'], q['b']) - q['r'] - h < DRILL - 1e-4: - return True - return False - - for s in segs: - if seg_bad(*s): - return False - if via is None: - return True - vx, vy = via - for p in lp: # 过孔穿所有层，两个信号层的焊盘都要让 - if p['net'] != net: - if R.seg_rect((vx, vy), (vx, vy), p['x'], p['y'], p['hw'], p['hh']) - Rv < R.CLR - 1e-4: - return False - elif p['lay'] == 12: - # ⚠️ **同网也要躲开通孔焊盘** —— 铜可以重叠，钻孔不行。 - # 第一版跳过了同网，于是给 J23 的两个 GND 屏蔽脚打的孔正落在 J23_1/J23_4 - # 的**焊盘里**：净距校核全过，DRC 却报「钻孔 到 钻孔 距离 0mil」。 - if R.seg_rect((vx, vy), (vx, vy), p['x'], p['y'], p['hw'], p['hh']) - Rv < DRILL - 1e-4: - return False - for v in lv: - if v['net'] != net: - if math.hypot(vx - v['x'], vy - v['y']) - v['r'] - Rv < R.CLR - 1e-4: - return False - elif math.hypot(vx - v['x'], vy - v['y']) - v['r'] - Rv < DRILL - 1e-4: - return False # 同网过孔之间也是钻孔间距说了算 - for l in ll: - if l['net'] == net: - continue - if R.seg_pt(l['x0'], l['y0'], l['x1'], l['y1'], vx, vy) - Rv - l['w'] / 2.0 < R.CLR - 1e-4: - return False - for n2, l2, ax, ay, bx, by, w2 in mine: - if n2 == net: - continue - if R.seg_pt(ax, ay, bx, by, vx, vy) - Rv - w2 / 2.0 < R.CLR - 1e-4: - return False - for n2, ox, oy in mvias: - # ⚠️ 本轮新打的同网过孔也要按钻孔间距判 —— 漏了这一条，U34 相邻三个 GND 脚 - # 的过孔排成一列、中心只隔 0.23 mm（三个钻孔互相打穿）。 - need = R.CLR if n2 != net else DRILL - if math.hypot(vx - ox, vy - oy) - 2 * Rv < need - 1e-4: - return False - for q in lh: - if R.seg_pt(q['a'][0], q['a'][1], q['b'][0], q['b'][1], vx, vy) - q['r'] - Rv < DRILL - 1e-4: - return False - return True - - -def place(pad, lay, w_steps, lp, lv, ll, lh, mine, mvias, inside_ok=None): - u"""给一个焊盘找一个过孔位。 - - 先试**一段直线**（只取 8 个方向，不会出现斜的怪角度）； - 不行再试**两段 45°**（第二段相对第一段只允许 ±45°，不允许直角）。 - 返回 (w, segs, (vx, vy)) 或 None。`inside_ok(x, y)` 可选，用来卡在铜岛内。 - - ⚠️ 线**默认从焊盘中心起步**（最稳的连接），但焊盘中间可能有钻孔 - （J23 的 A1B12/B1A12 就是 `ROUND 0.36`），压上去 DRC 报「挖槽区域 到 导线」。 - 所以起点会沿出线方向**往外退**，一直退到焊盘边缘内 `INSET` 为止，取第一个过的。 - """ - px, py, hw, hh = pad['x'], pad['y'], pad['hw'], pad['hh'] - RMIN = R.VIA_D / 2.0 + PAD_GAP - # 退到离焊盘边 0.02 为止：J23 的 A1B12 是 1.30×0.60 的焊盘、正中一个 Ø0.36 的 - # **非金属化**定位孔，孔边到焊盘边只有 0.47 mm，要塞下 0.2997 的净距 + 半线宽， - # 起点必须一路退到边上（0.20 的线，实际余量 0.63−0.18−0.10−0.2997 = 50 µm）。 - INSET = 0.02 - - def starts(dx, dy): - u"""沿 (dx, dy) 从焊盘中心往外的候选起点：中心 -> 焊盘边缘内 0.05。""" - t_edge = 1e9 - if abs(dx) > 1e-9: - t_edge = min(t_edge, hw / abs(dx)) - if abs(dy) > 1e-9: - t_edge = min(t_edge, hh / abs(dy)) - t_max = max(0.0, t_edge - INSET) - out, t = [], 0.0 - while t <= t_max + 1e-9: - out.append((round(px + t * dx, 4), round(py + t * dy, 4))) - t += 0.05 - if out[-1] != (round(px + t_max * dx, 4), round(py + t_max * dy, 4)): - out.append((round(px + t_max * dx, 4), round(py + t_max * dy, 4))) - return out - - def try_via(vx, vy, w, segs): - if pad_dist(px, py, hw, hh, vx, vy) < RMIN: - return None - if inside_ok and not inside_ok(vx, vy): - return None - if not fits(pad['net'], segs, (vx, vy), lp, lv, ll, lh, mine, mvias): - return None - return (w, segs, (vx, vy)) - - for w in w_steps: - d = 0.0 - while d <= D_MAX + 1e-9: - d += D_STEP - for dx, dy in DIRS: - vx, vy = round(px + d * dx, 4), round(py + d * dy, 4) - for sx, sy in starts(dx, dy): - if math.hypot(vx - sx, vy - sy) < 1e-6: - continue - got = try_via(vx, vy, w, [(lay, sx, sy, vx, vy, w)]) - if got: - return got - # 一段直线不行：拐一个 45° - for w in w_steps: - for i, (dx, dy) in enumerate(DIRS): - d1 = 0.0 - while d1 <= 2.5 + 1e-9: - d1 += 0.10 - mx, my = round(px + d1 * dx, 4), round(py + d1 * dy, 4) - for j in (i - 1, i + 1): - ex, ey = DIRS[j % len(DIRS)] - d2 = 0.0 - while d2 <= D_MAX + 1e-9: - d2 += D_STEP - vx, vy = round(mx + d2 * ex, 4), round(my + d2 * ey, 4) - for sx, sy in starts(dx, dy): - if math.hypot(mx - sx, my - sy) < 1e-6: - continue - got = try_via(vx, vy, w, [(lay, sx, sy, mx, my, w), - (lay, mx, my, vx, vy, w)]) - if got: - return got - return None - - -def solve(pads, vias, lines): - u"""逐个贴片焊盘挑过孔位置。返回 {key: path}。""" - byref = {} - for p in pads: - byref.setdefault(p['ref'], []).append(p) - - hl = holes(pads) - routes, report, mine, mvias = {}, [], [], [] - for ref in CAPS: - got = [p for p in byref.get(ref, []) if p['net'].startswith('VO') and p['net'].endswith('_P')] - if len(got) != 1: - sys.exit(u'%s 上找不到唯一的 VOn_P 焊盘（找到 %d 个）' % (ref, len(got))) - pad = got[0] - net, px, py = pad['net'], pad['x'], pad['y'] - poly = poly_of(net) - lp, lv, ll, lh = local(pads, vias, lines, px, py, hl) - # 一个焊盘上要几个孔（`N_VIA`）。**逐个放、每放一个就进 mine/mvias** —— - # 后一个孔会自动躲开前一个（同网也按钻孔间距 0.33 判，见 fits()）。 - want = N_VIA.get(ref, 1) - for k in range(want): - # push()/check() 靠 netof(key) 取网络名，所以 '#' 前面必须是网络名 - key = u'%s#%s' % (net, ref) if want == 1 else u'%s#%s-%d' % (net, ref, k + 1) - # ⚠️ 出线画在**焊盘自己那一层**，不是写死顶层。 - # v1 时代全板器件在顶层，写死 L_TOP 没暴露问题；v2 之后 - # VOn_P 的 35 个焊盘**全在底层**，照旧写 L_TOP 会画出 35 条 - # 悬在顶层、一头不搭焊盘的线 —— 而且 fits() 拿 lay 去筛障碍， - # 连净距校核都是照着空荡荡的顶层算的，一条都不会报。 - lay = pad['lay'] - other = R.L_BOT if lay == R.L_TOP else R.L_TOP - got2 = place(pad, lay, W_STEPS, lp, lv, ll, lh, mine, mvias, - inside_ok=lambda x, y: inside(poly, x, y, EDGE_IN)) - if not got2: - report.append((ref if k == 0 else '%s#%d' % (ref, k + 1), net, None)) - continue - w, segs, (vx, vy) = got2 - pts = ([(segs[0][1], segs[0][2], lay, w)] - + [(sx1, sy1, lay, w) for _l, _x0, _y0, sx1, sy1, _w in segs]) - routes[key] = pts + [(vx, vy, other, w), (vx, vy, other, w)] - for l_, x0, y0, x1, y1, w_ in segs: - mine.append((net, l_, x0, y0, x1, y1, w_)) - mvias.append((net, vx, vy)) - report.append((ref if k == 0 else '%s#%d' % (ref, k + 1), net, - (w, math.hypot(vx - px, vy - py), vx, vy, len(segs)))) - return routes, report - - -def main(): - pads, vias, lines = R.geom() - ours = set('VO%d_P' % n for n in range(1, 6)) - vias = [v for v in vias if v['net'] not in ours] - lines = [l for l in lines if l['net'] not in ours] - - routes, report = solve(pads, vias, lines) - fail = 0 - for ref, net, r in report: - if not r: - print(u' [!!] %-6s %-7s 找不到能落孔的位置' % (ref, net)) - fail += 1 - else: - w, d, vx, vy, ns = r - print(u' %-6s %-7s 过孔 (%8.3f,%8.3f) 离焊盘中心 %.2f 线宽 %.2f %d 段' - % (ref, net, vx, vy, d, w, ns)) - segs = sum(len(R.expand(p)[0]) for p in routes.values()) - nv = sum(len(R.expand(p)[1]) for p in routes.values()) - print(u'') - want = sum(N_VIA.get(r, 1) for r in CAPS) - print(u'%d/%d 个过孔搞定（%d 个焊盘）：%d 段导线 / %d 个过孔' - % (len(routes), want, len(CAPS), segs, nv)) - if nv != len(routes): - sys.exit(u'!! 过孔数和焊盘数对不上 —— expand() 又把末端过孔吞了') - - n_sharp = len(R.sharp_corners(routes)) - print(u'直角拐点 %d（每条只有一段直线，应当是 0）' % n_sharp) - - print(u'') - print(u'净距校核（一般 %.2f mm）:' % R.CLR) - bad = R.check(routes, pads, vias, lines) - if not bad: - print(u' 全部通过 ✔') - - if '--push' in sys.argv: - if bad or fail or n_sharp: - sys.exit(u'\n!! 有未解决的问题，不下发。') - print(u'') - R.push(routes) - print(u'⚠️ 下一步必须重铺：/c/Python314/python .claude/pcb2_pour.py --push') - - -if __name__ == '__main__': - main() +# -*- coding: utf-8 -*- +u"""五路 `VOn_P` 的**贴片电容接到 Inner1 电源岛** —— 每个焊盘旁边打一个过孔。 + + /c/Python314/python .claude/pcb2_route_dp.py --dump # 1. 先刷障碍表 + /c/Python314/python .claude/pcb2_vo_vias.py # 2. 只算 + 本地净距校核 + /c/Python314/python .claude/pcb2_vo_vias.py --push # 3. 下发 + /c/Python314/python .claude/pcb2_pour.py --push # 4. **必须重铺**（新过孔要反焊盘） + +## 为什么要有这一步 + +`VO1_P`~`VO5_P` 每个网络 10 个焊盘：**5 个通孔**（`C8n1.1` Ø10 电解正极、`TP8n1` +测试点、排母 3 针）本身就落在 Inner1 的岛上，不用管；剩下 **5 个贴片焊盘** +（`C8n2`/`C8n3` 100µF 1206、`C8n4`/`C8n5` 22µF 1206、`C8n6` 100nF 0402） +只有顶层铜，**和岛之间没有任何通路** —— 这就是 §25.14 里连接性 51 条中的 31 条。 + +所以这一步和布线不是一回事：不需要找路径，只需要**在焊盘边上打一个过孔**， +用一小段线接过去，垂直下到 Inner1 的岛上。25 个焊盘 = 25 个过孔。 + +## 选点判据（不是"看着差不多"） + +| | | +|---|---| +| 方向 | 只取 8 个方向（0/45/90…），**不许出现斜的怪角度**（全板 45° 化，§25.14）| +| 起步距离 | 过孔铜边到本焊盘矩形 **≥ 0.15 mm**（同网，不是 DRC 约束，是不想做 via-in-pad）| +| 净距 | 过孔和那一小段线对**异网**焊盘/过孔/导线 ≥ 0.20 —— 直接借 `pcb2_route_dp.check()` | +| 岛内余量 | 过孔中心离岛多边形边界 ≥ 0.61/2 + 0.30 = **0.605 mm**，免得铺出来只搭上一点点 | +| 线宽 | `PWR4A` 最小 0.30；从 1.00 起往下退让，取第一个过的 | + +⚠️ 过孔打在**路径末点**上 —— `expand()` 会静默丢掉末端过孔（§25.14 那条最阴的 bug）。 + 这里靠把末点写两遍绕开（`_path()` 里 `(vx,vy,L_BOT)` 后面再来一份）。 +""" +import json +import math +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +import pcb2_route_dp as R +from pcb2_pour import ISLANDS, island_poly + +W_STEPS = [1.00, 0.80, 0.60, 0.50, 0.40, 0.30] # PWR4A 的 strokeWidthMin = 0.30 +PAD_GAP = 0.15 # 过孔铜边到本焊盘的余量（同网，防 via-in-pad） +EDGE_IN = R.VIA_D / 2.0 + 0.30 # 过孔中心到岛边界的余量 +D_MAX = 3.5 +D_STEP = 0.05 +DRILL = 0.33 # 钻孔间距（规则 otherClearance / copperThickness1oz 都要求 >= 11.8mil + # = 0.2997 mm），留 30 µm 余量。再大就过不了 J23 的屏蔽脚，见 place() 的注释 +DIRS = [(math.cos(math.radians(a)), math.sin(math.radians(a))) for a in range(0, 360, 45)] + +# ── 哪些位号要打孔、各打几个 ───────────────────────────────────────── +# 2026-09-06 补两类（上一版只有 25 个贴片电容）： +# +# `C8n1.1` —— 换成 Rubycon 6.3TPV2200M10X10.5 之后**是贴片**（V-chip）， +# 原来当它是直插电解、以为正极自己就落在岛上，其实一点铜都不通。 +# `J8n.1` —— 电池排线改成 4 焊盘直焊（§13.5 末尾）之后，P+ 也是贴片。 +# `TP8n1` 那个通孔测试点已经取消 ⇒ **每路 VOn_P 现在只剩排母那 3 针是通孔**。 +# +# 个数按设计文档 §10.3「0.3 mm 孔单孔 1~1.5 A，功率网络每个焊盘打 3 个」： +# · `J8n.1` 是这一路 **4 A 的唯一去路**（岛 → 排线 → 手机），必须 3 个； +# · `C8n1.1` 是 2200 µF 的主储能，纹波电流也走它，给 3 个； +# · `C8n2`~`C8n6` 只承担高频纹波，各 1 个 —— 全按 3 个来会往五块岛里 +# 再钻 50 个反焊盘，最窄断面（下限 7.0 mm）扛不住。这是本项目对 §10.3 的 +# 一处**有意偏离**，见 PROGRESS。 +N_VIA = {} +REFS = [] +for _m in range(5): + REFS.append('C8%d1' % _m) + N_VIA['C8%d1' % _m] = 3 + REFS += ['C8%d%d' % (_m, _k) for _k in range(2, 7)] + REFS.append('J8%d' % (_m + 1)) + N_VIA['J8%d' % (_m + 1)] = 3 +CAPS = REFS + + +def poly_of(net): + for _name, n, main, neck in ISLANDS: + if n == net: + return island_poly(main, neck) + raise KeyError(net) + + +def inside(poly, x, y, margin): + u"""点在多边形内，且离每条边 >= margin。岛都是轴对齐的凸/凹矩形拼接，用射线法 + 边距。""" + c = False + n = len(poly) + for i in range(n): + ax, ay = poly[i] + bx, by = poly[(i + 1) % n] + if (ay > y) != (by > y) and x < ax + (bx - ax) * (y - ay) / (by - ay): + c = not c + if not c: + return False + for i in range(n): + ax, ay = poly[i] + bx, by = poly[(i + 1) % n] + if R.seg_pt(ax, ay, bx, by, x, y) < margin: + return False + return True + + +def pad_dist(px, py, hw, hh, x, y): + u"""点到轴对齐焊盘矩形的距离（0 = 在里面）。""" + return math.hypot(max(abs(x - px) - hw, 0.0), max(abs(y - py) - hh, 0.0)) + + +def _path(px, py, vx, vy, w): + u"""末点上的过孔要把点写两遍，否则 expand() 会把它丢掉（§25.14）。""" + return [(px, py, R.L_TOP, w), (vx, vy, R.L_TOP, w), + (vx, vy, R.L_BOT, w), (vx, vy, R.L_BOT, w)] + + +NEAR = 8.0 # 只拿焊盘 8 mm 以内的东西当障碍（全表 816+393+1373，全查太慢） + + +def holes(pads): + u"""每个**带钻孔的焊盘**的孔 -> 一段胶囊 (a, b, r)（圆孔就是 a == b）。 + + **两类孔的待遇不一样**（2026-09-06 用 DRC 一条条试出来的）： + + | | 线能不能压上去 | 过孔能不能靠近 | + |---|---|---| + | 焊盘自己的孔（`SLOT` / `ROUND`，金属化）| **能** —— 它就是焊盘的一部分 | 不能，钻孔间距 | + | 封装自带的非金属化孔（`npth=True`）| **不能**，DRC 报「挖槽区域 到 导线」| 不能 | + + 一开始把两类混在一起判，结果是「谁都连不上 J23 的屏蔽脚」—— + 槽孔焊盘的**任何一点**离自己的槽都不足 0.80 mm，按那个判据连焊盘都碰不得。 + + 槽的长轴按焊盘的长轴定（`_pcb2_route_geom.json` 里的 hw/hh 已经是转过的）， + `_pcb2_pads_full.json` 只存了孔的两个尺寸、没存角度，所以只能这么反推。 + """ + out = [] + # ⚠️ 封装自带的非金属化孔（J23 那两个 Ø0.60）**API 一个都读不出来**， + # 只能从内层铺铜的反焊盘反推 —— `pcb2_npth.py --write` 生成这份清单。 + # 没有它的话，「从 A1B12 往东拉线打孔」这条最自然的走法会被 DRC + # 以「挖槽区域 到 导线 距离 0mil」打回来，而净距校核一条都不报。 + try: + for cx, cy, r in json.load(open(os.path.join(HERE, '_pcb2_npth.json'), encoding='utf-8')): + out.append({'net': None, 'npth': True, 'a': (cx, cy), 'b': (cx, cy), 'r': r}) + except Exception: + print(u' [!] 没有 _pcb2_npth.json —— 先跑 pcb2_npth.py --write，否则封装自带的孔看不见') + full = json.load(open(os.path.join(HERE, '_pcb2_pads_full.json'), encoding='utf-8')) + bykey = {} + for ref, num, _net, _lay, _x, _y, _shape, hole in full: + if hole: + bykey[(ref, num)] = hole + for p in pads: + h = bykey.get((p['ref'], p['num'])) + if not h: + continue + if h[0] == 'ROUND': + r = float(h[1]) / R.MIL / 2.0 + out.append({'net': p['net'], 'npth': False, + 'a': (p['x'], p['y']), 'b': (p['x'], p['y']), 'r': r}) + continue + w, L = sorted((float(h[1]) / R.MIL, float(h[2]) / R.MIL)) # 槽宽 / 槽长 + r, ext = w / 2.0, (L - w) / 2.0 + if p['hw'] >= p['hh']: # 焊盘长轴在 x 上 + out.append({'net': p['net'], 'npth': False, + 'a': (p['x'] - ext, p['y']), 'b': (p['x'] + ext, p['y']), 'r': r}) + else: + out.append({'net': p['net'], 'npth': False, + 'a': (p['x'], p['y'] - ext), 'b': (p['x'], p['y'] + ext), 'r': r}) + return out + + +def local(pads, vias, lines, px, py, hl=()): + return ([p for p in pads if abs(p['x'] - px) < NEAR and abs(p['y'] - py) < NEAR], + [v for v in vias if abs(v['x'] - px) < NEAR and abs(v['y'] - py) < NEAR], + [l for l in lines + if R.seg_pt(l['x0'], l['y0'], l['x1'], l['y1'], px, py) < NEAR], + [h for h in hl if abs(h['a'][0] - px) < NEAR and abs(h['a'][1] - py) < NEAR]) + + +def fits(net, segs, via, lp, lv, ll, lh, mine, mvias): + u"""几段线 + 一个过孔对**异网**的净距都 >= CLR？ + + `segs` = [(lay, x0, y0, x1, y1, w), ...]（本次要画的） + `via` = (x, y) 或 None + `mine` = 本轮已定的线 [(net, lay, x0, y0, x1, y1, w), ...] + `mvias` = 本轮已定的孔 [(net, x, y), ...] + `lh` = 附近的钻孔胶囊（`holes()` 的输出）；**不分网络**，钻孔和铜是两条规则 + + ⚠️ 线的层必须逐段拿，**不能写死顶层** —— 底层的 0402 + 第一版就是这么错的，本地判完全过、到 `check()` 才炸。 + """ + Rv = R.VIA_D / 2.0 + + def seg_bad(lay, x0, y0, x1, y1, w): + h, a, b = w / 2.0, (x0, y0), (x1, y1) + for p in lp: + if p['lay'] != 12 and p['lay'] != lay: + continue + if p['net'] != net: + if R.seg_rect(a, b, p['x'], p['y'], p['hw'], p['hh']) - h < R.CLR - 1e-4: + return True + + for v in lv: + if v['net'] == net: + continue + if R.seg_pt(x0, y0, x1, y1, v['x'], v['y']) - v['r'] - h < R.CLR - 1e-4: + return True + for l in ll: + if l['net'] == net or l['lay'] != lay: + continue + if R.seg_seg(a, b, (l['x0'], l['y0']), (l['x1'], l['y1'])) - h - l['w'] / 2.0 < R.CLR - 1e-4: + return True + for n2, l2, ax, ay, bx, by, w2 in mine: + if n2 == net or l2 != lay: + continue + if R.seg_seg(a, b, (ax, ay), (bx, by)) - h - w2 / 2.0 < R.CLR - 1e-4: + return True + for n2, vx, vy in mvias: + if n2 == net: + continue + if R.seg_pt(x0, y0, x1, y1, vx, vy) - Rv - h < R.CLR - 1e-4: + return True + for q in lh: # 线只躲**非金属化**孔；焊盘自己的孔是焊盘的一部分 + if q['npth'] and R.seg_seg(a, b, q['a'], q['b']) - q['r'] - h < DRILL - 1e-4: + return True + return False + + for s in segs: + if seg_bad(*s): + return False + if via is None: + return True + vx, vy = via + for p in lp: # 过孔穿所有层，两个信号层的焊盘都要让 + if p['net'] != net: + if R.seg_rect((vx, vy), (vx, vy), p['x'], p['y'], p['hw'], p['hh']) - Rv < R.CLR - 1e-4: + return False + elif p['lay'] == 12: + # ⚠️ **同网也要躲开通孔焊盘** —— 铜可以重叠，钻孔不行。 + # 第一版跳过了同网，于是给 J23 的两个 GND 屏蔽脚打的孔正落在 J23_1/J23_4 + # 的**焊盘里**：净距校核全过，DRC 却报「钻孔 到 钻孔 距离 0mil」。 + if R.seg_rect((vx, vy), (vx, vy), p['x'], p['y'], p['hw'], p['hh']) - Rv < DRILL - 1e-4: + return False + for v in lv: + if v['net'] != net: + if math.hypot(vx - v['x'], vy - v['y']) - v['r'] - Rv < R.CLR - 1e-4: + return False + elif math.hypot(vx - v['x'], vy - v['y']) - v['r'] - Rv < DRILL - 1e-4: + return False # 同网过孔之间也是钻孔间距说了算 + for l in ll: + if l['net'] == net: + continue + if R.seg_pt(l['x0'], l['y0'], l['x1'], l['y1'], vx, vy) - Rv - l['w'] / 2.0 < R.CLR - 1e-4: + return False + for n2, l2, ax, ay, bx, by, w2 in mine: + if n2 == net: + continue + if R.seg_pt(ax, ay, bx, by, vx, vy) - Rv - w2 / 2.0 < R.CLR - 1e-4: + return False + for n2, ox, oy in mvias: + # ⚠️ 本轮新打的同网过孔也要按钻孔间距判 —— 漏了这一条，U34 相邻三个 GND 脚 + # 的过孔排成一列、中心只隔 0.23 mm（三个钻孔互相打穿）。 + need = R.CLR if n2 != net else DRILL + if math.hypot(vx - ox, vy - oy) - 2 * Rv < need - 1e-4: + return False + for q in lh: + if R.seg_pt(q['a'][0], q['a'][1], q['b'][0], q['b'][1], vx, vy) - q['r'] - Rv < DRILL - 1e-4: + return False + return True + + +def place(pad, lay, w_steps, lp, lv, ll, lh, mine, mvias, inside_ok=None): + u"""给一个焊盘找一个过孔位。 + + 先试**一段直线**（只取 8 个方向，不会出现斜的怪角度）； + 不行再试**两段 45°**（第二段相对第一段只允许 ±45°，不允许直角）。 + 返回 (w, segs, (vx, vy)) 或 None。`inside_ok(x, y)` 可选，用来卡在铜岛内。 + + ⚠️ 线**默认从焊盘中心起步**（最稳的连接），但焊盘中间可能有钻孔 + （J23 的 A1B12/B1A12 就是 `ROUND 0.36`），压上去 DRC 报「挖槽区域 到 导线」。 + 所以起点会沿出线方向**往外退**，一直退到焊盘边缘内 `INSET` 为止，取第一个过的。 + """ + px, py, hw, hh = pad['x'], pad['y'], pad['hw'], pad['hh'] + RMIN = R.VIA_D / 2.0 + PAD_GAP + # 退到离焊盘边 0.02 为止：J23 的 A1B12 是 1.30×0.60 的焊盘、正中一个 Ø0.36 的 + # **非金属化**定位孔，孔边到焊盘边只有 0.47 mm，要塞下 0.2997 的净距 + 半线宽， + # 起点必须一路退到边上（0.20 的线，实际余量 0.63−0.18−0.10−0.2997 = 50 µm）。 + INSET = 0.02 + + def starts(dx, dy): + u"""沿 (dx, dy) 从焊盘中心往外的候选起点：中心 -> 焊盘边缘内 0.05。""" + t_edge = 1e9 + if abs(dx) > 1e-9: + t_edge = min(t_edge, hw / abs(dx)) + if abs(dy) > 1e-9: + t_edge = min(t_edge, hh / abs(dy)) + t_max = max(0.0, t_edge - INSET) + out, t = [], 0.0 + while t <= t_max + 1e-9: + out.append((round(px + t * dx, 4), round(py + t * dy, 4))) + t += 0.05 + if out[-1] != (round(px + t_max * dx, 4), round(py + t_max * dy, 4)): + out.append((round(px + t_max * dx, 4), round(py + t_max * dy, 4))) + return out + + def try_via(vx, vy, w, segs): + if pad_dist(px, py, hw, hh, vx, vy) < RMIN: + return None + if inside_ok and not inside_ok(vx, vy): + return None + if not fits(pad['net'], segs, (vx, vy), lp, lv, ll, lh, mine, mvias): + return None + return (w, segs, (vx, vy)) + + for w in w_steps: + d = 0.0 + while d <= D_MAX + 1e-9: + d += D_STEP + for dx, dy in DIRS: + vx, vy = round(px + d * dx, 4), round(py + d * dy, 4) + for sx, sy in starts(dx, dy): + if math.hypot(vx - sx, vy - sy) < 1e-6: + continue + got = try_via(vx, vy, w, [(lay, sx, sy, vx, vy, w)]) + if got: + return got + # 一段直线不行：拐一个 45° + for w in w_steps: + for i, (dx, dy) in enumerate(DIRS): + d1 = 0.0 + while d1 <= 2.5 + 1e-9: + d1 += 0.10 + mx, my = round(px + d1 * dx, 4), round(py + d1 * dy, 4) + for j in (i - 1, i + 1): + ex, ey = DIRS[j % len(DIRS)] + d2 = 0.0 + while d2 <= D_MAX + 1e-9: + d2 += D_STEP + vx, vy = round(mx + d2 * ex, 4), round(my + d2 * ey, 4) + for sx, sy in starts(dx, dy): + if math.hypot(mx - sx, my - sy) < 1e-6: + continue + got = try_via(vx, vy, w, [(lay, sx, sy, mx, my, w), + (lay, mx, my, vx, vy, w)]) + if got: + return got + return None + + +def solve(pads, vias, lines): + u"""逐个贴片焊盘挑过孔位置。返回 {key: path}。""" + byref = {} + for p in pads: + byref.setdefault(p['ref'], []).append(p) + + hl = holes(pads) + routes, report, mine, mvias = {}, [], [], [] + for ref in CAPS: + got = [p for p in byref.get(ref, []) if p['net'].startswith('VO') and p['net'].endswith('_P')] + if len(got) != 1: + sys.exit(u'%s 上找不到唯一的 VOn_P 焊盘（找到 %d 个）' % (ref, len(got))) + pad = got[0] + net, px, py = pad['net'], pad['x'], pad['y'] + poly = poly_of(net) + lp, lv, ll, lh = local(pads, vias, lines, px, py, hl) + # 一个焊盘上要几个孔（`N_VIA`）。**逐个放、每放一个就进 mine/mvias** —— + # 后一个孔会自动躲开前一个（同网也按钻孔间距 0.33 判，见 fits()）。 + want = N_VIA.get(ref, 1) + for k in range(want): + # push()/check() 靠 netof(key) 取网络名，所以 '#' 前面必须是网络名 + # 2026-09-07：分隔符改用 R.KSEP（chr(0)），'#' 会和 KEY_OE# 撞、也让 netof() 拆不开（第三十轮实测 13 条假「过孔-焊盘」） + key = u'%s%s%s' % (net, R.KSEP, ref) if want == 1 else u'%s%s%s-%d' % (net, R.KSEP, ref, k + 1) + # ⚠️ 出线画在**焊盘自己那一层**，不是写死顶层。 + # v1 时代全板器件在顶层，写死 L_TOP 没暴露问题；v2 之后 + # VOn_P 的 35 个焊盘**全在底层**，照旧写 L_TOP 会画出 35 条 + # 悬在顶层、一头不搭焊盘的线 —— 而且 fits() 拿 lay 去筛障碍， + # 连净距校核都是照着空荡荡的顶层算的，一条都不会报。 + lay = pad['lay'] + other = R.L_BOT if lay == R.L_TOP else R.L_TOP + got2 = place(pad, lay, W_STEPS, lp, lv, ll, lh, mine, mvias, + inside_ok=lambda x, y: inside(poly, x, y, EDGE_IN)) + if not got2: + report.append((ref if k == 0 else '%s#%d' % (ref, k + 1), net, None)) + continue + w, segs, (vx, vy) = got2 + pts = ([(segs[0][1], segs[0][2], lay, w)] + + [(sx1, sy1, lay, w) for _l, _x0, _y0, sx1, sy1, _w in segs]) + routes[key] = pts + [(vx, vy, other, w), (vx, vy, other, w)] + for l_, x0, y0, x1, y1, w_ in segs: + mine.append((net, l_, x0, y0, x1, y1, w_)) + mvias.append((net, vx, vy)) + report.append((ref if k == 0 else '%s#%d' % (ref, k + 1), net, + (w, math.hypot(vx - px, vy - py), vx, vy, len(segs)))) + return routes, report + + +def main(): + pads, vias, lines = R.geom() + ours = set('VO%d_P' % n for n in range(1, 6)) + vias = [v for v in vias if v['net'] not in ours] + lines = [l for l in lines if l['net'] not in ours] + + routes, report = solve(pads, vias, lines) + fail = 0 + for ref, net, r in report: + if not r: + print(u' [!!] %-6s %-7s 找不到能落孔的位置' % (ref, net)) + fail += 1 + else: + w, d, vx, vy, ns = r + print(u' %-6s %-7s 过孔 (%8.3f,%8.3f) 离焊盘中心 %.2f 线宽 %.2f %d 段' + % (ref, net, vx, vy, d, w, ns)) + segs = sum(len(R.expand(p)[0]) for p in routes.values()) + nv = sum(len(R.expand(p)[1]) for p in routes.values()) + print(u'') + want = sum(N_VIA.get(r, 1) for r in CAPS) + print(u'%d/%d 个过孔搞定（%d 个焊盘）：%d 段导线 / %d 个过孔' + % (len(routes), want, len(CAPS), segs, nv)) + if nv != len(routes): + sys.exit(u'!! 过孔数和焊盘数对不上 —— expand() 又把末端过孔吞了') + + n_sharp = len(R.sharp_corners(routes)) + print(u'直角拐点 %d（每条只有一段直线，应当是 0）' % n_sharp) + + print(u'') + print(u'净距校核（一般 %.2f mm）:' % R.CLR) + bad = R.check(routes, pads, vias, lines) + if not bad: + print(u' 全部通过 ✔') + + if '--push' in sys.argv: + if bad or fail or n_sharp: + sys.exit(u'\n!! 有未解决的问题，不下发。') + print(u'') + R.push(routes) + print(u'⚠️ 下一步必须重铺：/c/Python314/python .claude/pcb2_pour.py --push') + + +if __name__ == '__main__': + main() diff --git a/.claude/pcb_place.py b/.claude/pcb_place.py index 6f4e98f..3e20061 100644 --- a/.claude/pcb_place.py +++ b/.claude/pcb_place.py @@ -32,10 +32,14 @@ HERE = os.path.dirname(os.path.abspath(__file__)) sys.path.insert(0, HERE) PCB = '7e9415a16a909c51' MIL = 39.3701 # 1 mm = 39.3701 mil -BW, BH = 160.0, 125.0 # 板框 mm +BW, BH = 160.0, 125.0 # 元件区 mm（原点左下角，坐标系不变） +# 2026-09-06 用户指令：两板尺寸取大对齐 —— 下板板框放大到载板的 220×135，原点不动， +# 板框左下角在 (−30,−5)（下板坐标 = 载板坐标 − (30,5)，见 pcb1_env.py）。 +OX, OY, OW, OH = -30.0, -5.0, 220.0, 135.0 CORNER_R = 5.0 # 四角圆角半径 mm # 定位孔：M3 金属化，孔 Φ3.2 / 焊盘 Φ6.0 / 禁布 Φ6.5，孔心与圆角同心 -MH = [(5.0, 5.0), (BW - 5.0, 5.0), (5.0, BH - 5.0), (BW - 5.0, BH - 5.0)] +# 定位孔与载板 pcb2_place.MH 对齐（减 (30,5)）：四角 + 两侧中点；事实来源是 pcb1_place.MH，这里同表 +MH = [(-22.0, 3.0), (182.0, 3.0), (-26.0, 126.0), (186.0, 126.0), (-23.0, 55.0), (183.0, 40.0)] MH_HOLE, MH_PAD, MH_KEEPOUT = 3.2, 6.0, 6.5 # ── 封装占位尺寸（mm，含焊盘；未旋转时 x 向宽 w、y 向高 h）────────────── @@ -469,14 +473,15 @@ def outline_poly(): 要求闭合，不闭合就建不出来）。ARC 的角度**正值 = 逆时针**（本工程 Y 轴朝上）。 """ R = CORNER_R + X0, Y0, X1, Y1 = OX, OY, OX + OW, OY + OH pts = [] L = lambda x, y: pts.append(('L', x, y)) A = lambda x, y: pts.append(('ARC', 90.0, x, y)) - start = (R, 0.0) - L(BW - R, 0.0); A(BW, R) - L(BW, BH - R); A(BW - R, BH) - L(R, BH); A(0.0, BH - R) - L(0.0, R); A(R, 0.0) # 回到起点 + start = (X0 + R, Y0) + L(X1 - R, Y0); A(X1, Y0 + R) + L(X1, Y1 - R); A(X1 - R, Y1) + L(X0 + R, Y1); A(X0, Y1 - R) + L(X0, Y0 + R); A(X0 + R, Y0) # 回到起点 src, mode = [start[0] * MIL, start[1] * MIL], None for p in pts: @@ -549,8 +554,8 @@ return {del, made: r ? r.primitiveId : null, left}; if n['left'] != 1: print(u' !! layer 11 上有 %d 条多段线，应为 1 —— 板框没建成或有残留' % n['left']) sys.exit(1) - print(u'板框: 1 条闭合多段线（4 直边 + 4 圆角 R%.0f），%.0f x %.0f mm；' - u'顺带删掉 %d 个旧图元' % (CORNER_R, BW, BH, n['del'])) + print(u'板框: 1 条闭合多段线（4 直边 + 4 圆角 R%.0f），%.0f x %.0f mm，左下角 (%.0f,%.0f)；' + u'顺带删掉 %d 个旧图元' % (CORNER_R, OW, OH, OX, OY, n['del'])) n = call(""" const MH = %s; diff --git a/.claude/port_audit.py b/.claude/port_audit.py index 7191228..88e4ff8 100644 --- a/.claude/port_audit.py +++ b/.claude/port_audit.py @@ -43,7 +43,13 @@ from eda import run TOL = 0.6 _CACHE = json.load(io.open(os.path.join(HERE, 'eda-parts.json'), encoding='utf-8')) # 默认扫下板；`--board Board2` 扫载板（两块板的页表都在 eda-parts.json 里） -if '--board' in sys.argv: +# `--r2 BLADE` / `--r2 BASE` 扫 R2 刀片式工程（页表在 .claude/r2/r2-uuids.json）—— +# ⚠ 它只按 uuid 打开文档，不切工程：跑之前先让客户端停在 PhoneRail-R2 上。 +if '--r2' in sys.argv: + _b = sys.argv[sys.argv.index('--r2') + 1] + PAGES = json.load(io.open(os.path.join(HERE, 'r2', 'r2-uuids.json'), + encoding='utf-8'))['boards'][_b]['pages'] +elif '--board' in sys.argv: _b = sys.argv[sys.argv.index('--board') + 1] PAGES = _CACHE['schematic_boards'][_b]['pages'] else: diff --git a/.claude/r2/A-CONTRACT.md b/.claude/r2/A-CONTRACT.md new file mode 100644 index 0000000..b4b2863 --- /dev/null +++ b/.claude/r2/A-CONTRACT.md @@ -0,0 +1,225 @@ +# R2 底板（BASE）剩余四页的**跨页契约** — 2026-09-08 + +`A1-INPUT` / `A2-AUX` 已画完。本文件钉死 `A3-CTRL` / `A4-HUB` / `A5-SLOTS` / `A6-FAN` +四页之间的**网络名、方向、器件归属、位号区段**。四页由四个子代理并行设计， +**只有主代理能下发到 EasyEDA**（全机只有一个 EDA 客户端，`openDocument` 是全局状态， +两个人同时推必然把图元放到别人的页上）。 + +⛔ **子代理绝对不许**：跑 `.claude/eda.py`、`dump_page.py`、`xpage.py`、`shot.py`、 +`verify_sch.py`、任何带 `--push` 的脚本，或任何会连 `127.0.0.1:4962x` 的东西。 +你的交付物是**一个能本地自检通过的 Python 脚本**，主代理负责下发与几何验证。 + +--- + +## 0. 已经存在的东西（不要重画，也不要改名） + +| 页 | 内容 | 对外端口 / 旗 | +|---|---|---| +| `A1-INPUT` | J1 DC-005 → F1 → Q1 反接 → C2~C6 → Rs6 → 12V 母线；U13 INA226(0x43)；U29 TL431 泄放 | `+12V`(旗) `GND`(旗) `+3V3`(旗) `SDA` `SCL` `INA_ALERT`(端口) | +| `A2-AUX` | U19 12V→3V3（0.5A）；U30 12V→5V（2A） | `+12V` `+3V3` `GND`(旗) `+5V`(端口，OUT) | + +`xpage` 现在的 4 个单实例 `+5V` / `SDA` / `SCL` / `INA_ALERT` 就是等你们补对端的。 + +--- + +## 1. 网络名总表（**唯一事实来源**） + +### 1.1 电源 + +| 网络 | 图元类型 | 说明 | +|---|---|---| +| `+12V` | **Power 旗** | 全板 12V 母线 | +| `+3V3` | **Power 旗** | U19 出来的控制轨（0.5A），给 ESP32 / mux / DAC / 刀片逻辑 | +| `+5V` | **端口** | U30 出来的 5V（2A）。A2 已发 OUT，A4/A5 用 **IN** | +| `+3V3_HUB` | **Power 旗**（仅 A4 页内） | U31 AMS1117 给 U32 专用，**不许**和 `+3V3` 并 | +| `FAN_12V_SW` | **Power 旗**（仅 A6 页内） | Q7 高边开关之后的风扇 12V | +| `GND` | **Ground 旗** | — | + +### 1.2 跨页信号（发出方 → 接收方） + +| 网络 | 发出 | 接收 | 说明 | +|---|---|---|---| +| `SDA` / `SCL` | A1(U13) | **A3**（上拉 + ESP32 + U35 上游 + U6/U7 DAC） | I²C **主干**，不经 mux | +| `INA_ALERT` | A1(U13) | **A3**（ESP32 GPIO） | 开漏，上拉放在 A3 | +| `SDA1`~`SDA5` / `SCL1`~`SCL5` | **A3**(U35 通道 0~4) | **A5**（槽 1~5） | mux 分支，**上拉在刀片上**（B2-CTRL 的 R40/R41），底板这一侧不加 | +| `VDAC1`~`VDAC5` | **A3**(U6/U7) | **A5** | 模拟量，跨金手指进刀片 | +| `EFUSE_EN1`~`EFUSE_EN5` | **A3**(ESP32 直驱) | **A5** | 不经 IO 扩展 | +| `PRSNT1#`~`PRSNT5#` | **A5**(槽 **B31** 一针) | **A3**（ESP32 输入 + 上拉） | ⚠️ **2026-09-08 修正**：底板是**主板侧**，`A1` 与 `B31` 必须是**两个节点** —— `A1 → GND`、`B31 → PRSNT{n}#`。短接 A1↔B31 的是**刀片**（`b4_edge.py`，PCIe add-in card 的标准做法），插上刀片才把 B31 拉到地。若底板也照字面「镜像」把两针并成一个网，回路里一个对地通路都没有 ⇒ **插不插都读「未插入」，而 DRC/ERC/几何验证/跨页对账四道全过**。见 `a5_slots.py` 表头的对照表 | +| `INT#` | **A5**（五槽 B11 并联） | **A3**（ESP32 + **唯一一颗 10k 上拉到 +3V3**） | 开漏 wire-OR，五槽共一个网络 | +| `HUB_RST` | **A3**(ESP32) | **A4**(U32) | ⚠ 见 §3 的保命约束 | +| `UP_VBUS_DET` | **A4** | **A3**(ESP32) | 电脑在不在 | +| `USB1_DP/DM` ~ `USB5_DP/DM` | **A4**(U32 下行口 1~5) | **A5**（槽 B14/B15） | | +| `USB6_DP` / `USB6_DM` | **A4**(U32 下行口 6) | **A3**（ESP32 原生 USB，IO19=D−/IO20=D+） | D13 | +| `FAN_EN` | **A3**(ESP32) | **A6** | 高边总开关，复位态必须**关电** | +| `FAN_PWM` | **A3**(ESP32) | **A6** | 两只风扇共用（A6 里经反相成 `FAN_PWM_L`） | +| `FAN_TACH_IN` / `FAN_TACH_OUT` | **A6** | **A3**(ESP32) | 两路独立测速 | +| `NTC1` / `NTC2` | **A6**(RT601/RT602 分压节点) | **A3**(ESP32 **ADC1** 脚) | ⚠ 必须 ADC1（IO1~IO10），ADC2 与 WiFi 冲突 | + +### 1.3 页内网络（不跨页，别在别的页上用这些名字） + +- A3：`MUX_RST#`（U35 的 RESET#，10k 上拉 + 一个 ESP32 GPIO）、`EN` / `IO0` / `TXD0` / `RXD0`（J33） +- A4：`UP_DP` `UP_DM` `VBUS_UP` `VBUS_DET` `XTAL1` `XTAL2` `RBIAS` `VDD18` `VDD18PLL` + `CFGSEL0` `CFGSEL1` `NONREM0` `NONREM1`（全部沿用 R1 `C2-HUB` 的名字） +- A6：`FAN_PWM_L` `FAN_IN_TACH_RAW` `FAN_OUT_TACH_RAW` +- A5：无（全是 §1.2 的网络 + 电源 + 地） + +### 1.4 **明确不存在**的网络（R1 有、R2 没有，写了就是错） + +`BUCK_PG`（A2 的 U19 没引 PG）、`IOEXP_INT#`（改叫 `INT#`）、 +`EFUSE_PG*` / `EFUSE_FLT*`（eFuse 在刀片上，状态走刀片自己的 PCA9555）、 +`VBUS_EN*`（在刀片 B2-CTRL 上）、`KEY_*`（74HC595 已作废，D9）、 +`USB_DP` / `USB_DM` 不带编号的形式（那是刀片页内的名字）。 + +--- + +## 2. 位号区段（防撞） + +| 页 | 允许使用 | +|---|---| +| A1（已画） | `J1` `F1` `Q1` `Q3` `DZ1` `D1` `R1` `R4` `R5` `R6` `R9A~R9E` `C1~C6` `C11` `Rs6` `U13` `U29` | +| A2（已画） | `U19` `U30` `L2` `L3` `R2` `R3` `R706` `R707` `C7~C10` `C731~C735` | +| **A3-CTRL** | `U20` `U35` `U6` `U7` `J33`，新增无源件用 `R601~R650` / `C601~C650` | +| **A4-HUB** | `U31` `U32` `Y1` `J23`，无源件 `R708~R730` / `C737` `C740~C759` | +| **A5-SLOTS** / **A5B-SLOTS** | 插槽 `J34~J38`（槽 1~5）、D± 退路座 `J39~J43`，无源件 `R760~R790` / `C761~C790` | +| **A6-FAN** | `Q6~Q10` `D2` `DZ3` `J26` `J27` `RT601` `RT602`，电容 `C736` `C738` `C739`，电阻 `R733` `R734` `R746~R757` + 新增 `R660~R699` | + +> ⚠️ **2026-09-08 修订**：原表里 A4 的 `C740~C760` 与 A5 的 `C760~C790` 在 `C760` 上撞车（A6 代理发现）， +> 已改成 `C740~C759` / `C761~C790`。A6 原来只点名了 `C738`，现补 `C736` / `C739`（全表仅剩的两个无主号）。 +> `A5B-SLOTS` 是 2026-09-08 新开的第七页（`e493f8bce3a51aae`），与 A5 共用同一段号。 + +--- + +## 3. 三条会烧板 / 会自断后路的硬约束 + +1. **`HUB_RST` 必须外部上拉到 `+3V3_HUB`（10k），且 ESP32 复位期间 Hub 保持工作。** + ESP32 的控制台就挂在这颗 Hub 后面（D13），误复位 = 自断控制台 + 下次烧不进去。 + 固件侧只在启动自检脉冲一次 —— 硬件侧要保证「不驱动 = 不复位」。 +2. **`FAN_EN` 复位态必须是关电。** Q7 是 P-MOS 高边，栅极靠 Q6 拉低才导通； + Q6 栅极要有 100k 下拉，ESP32 高阻时风扇不转（R1 P6 已经是这个拓扑，照抄）。 +3. **`+3V3_HUB` 与 `+3V3` 是两条轨**（U32 满载 ≈420 mA，挂不进 U19 那条 0.5A 轨）。 + 两者只共地。A4 页上不许出现把它们并起来的导线或同名旗。 + +--- + +## 4. 器件与引脚几何（全部实测，直接用，不要自己猜） + +`.claude/eda-parts.json` 是器件表；下面是**这四页要用到的新器件**的引脚相对坐标（rot 0，相对元件中心）： + +``` +TCA9548APWR (C130026) 左列 x=-50，右列 x=+50 + 1 A0 (-50, 55) 13 SD4 (50,-55) + 2 A1 (-50, 45) 14 SC4 (50,-45) + 3 RESET#(-50, 35) 15 SD5 (50,-35) + 4 SD0 (-50, 25) 16 SC5 (50,-25) + 5 SC0 (-50, 15) 17 SD6 (50,-15) + 6 SD1 (-50, 5) 18 SC6 (50, -5) + 7 SC1 (-50, -5) 19 SD7 (50, 5) + 8 SD2 (-50,-15) 20 SC7 (50, 15) + 9 SC2 (-50,-25) 21 A2 (50, 25) + 10 SD3 (-50,-35) 22 SCL (50, 35) + 11 SC3 (-50,-45) 23 SDA (50, 45) + 12 GND (-50,-55) 24 VCC (50, 55) + +NCP18XH103F03RB (C13564) 1 (-20,0) 2 (+20,0) 无极性 +2.54mm 1*5P 直排针 (C50951) 1(-20,20) 2(-20,10) 3(-20,0) 4(-20,-10) 5(-20,-20) 全部朝左 +AMS1117-3.3 (C6186) 1 GND(-45,10) 2 VOUT(-45,0) 3 VIN(-45,-10) 4 VOUT(+45,0) +PCIE-064-02-F-D-TH (C4597619) A1~A32: x=-35, y=155-10*(n-1) + B1~B32: x=+35, y=155-10*(n-1) +``` + +其余器件（ESP32-S3-WROOM-1 / DAC63204 / USB2517I / Y1 / AO3400A / AO3401A / +SS34 / BZT52C8V2 / TYPE-C-31-M-12 / 2510-4A / A1251WV-S-4P / 各种 0402）的引脚坐标 +**从 R1 的实测 dump 里直接读**，见 §5。 + +--- + +## 5. R1 参照版图（已 dump 成 JSON，直接读，**不要连 EDA**） + +| 文件 | 是哪一页 | 给谁用 | +|---|---|---| +| `.claude/r2/_p3_live.json` | R1 `P3-CONTROL`（U20 ESP32 + J22 + RT601/602） | **A3**（ESP32 那一块整块搬）、**A6**（NTC 分压那一小块搬走） | +| `.claude/r2/_p3b_live2.json` | R1 `P3B-EXPAND`（U6/U7 DAC + U23 PCA9555） | **A3**（两颗 DAC 整块搬，U23 不要） | +| `.claude/r2/_c2hub_live.json` | R1 `C2-HUB`（U32 + Y1 + J23 + 一堆去耦） | **A4**（整页搬，加第 6 个下行口） | +| `.claude/r2/_p6_live.json` | R1 `P6-FAN-EDL`（风扇部分 + EDL 部分） | **A6**（**只要风扇部分**，EDL 已挪去刀片 B3-PHONE） | +| `.claude/r2/b4_edge.py` | R2 刀片 `B4-EDGE`（金手指 64 针分配） | **A5**（针位表照抄并做**逐脚对账**） | + +JSON 结构见 `.claude/r2/dump_page.py` 的文档串： +`parts` = `[位号, 器件名, 子部件, x, y, rot, mirror, uuid, libraryUuid, [[脚号,脚名,x,y],...]]`， +`wires` = **端点对**（不是折线），`flags` = `[种类, 网名, x, y, rot]`， +`ports` = `[dir, 网名, x, y, rot]`，`texts` = `[x, y, 内容, rot, 字号]`。 + +⚠️ **搬版图时引脚坐标是绝对坐标**：算出 `(引脚x - 元件x, 引脚y - 元件y)` 得到相对量， +再加上你的新元件中心。**不要相信任何"方向表"**（skill §6c：同一个 `rot` 在不同型号上语义相反）。 + +--- + +## 6. 每页交付物 + +一个 `.claude/r2/aN_xxx.py`，**照抄 `a1_input.py` / `a2_aux.py` 的骨架**： + +```python +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, by_rel, two_pin, pins_of, _on # 按需 + +PAGE, NAME = '<页uuid>', '<页名>' + +def placement(): ... # [[位号, eda-parts的键, x, y, rot], ...] +def expect(): ... # {位号: {脚号: (绝对x, 绝对y)}} 放件后逐脚回读比对用 +def build(): ... # 返回填好 W/F/PT/TX 的 Sheet + +def main(): + s = build(); s.assert_grid() + errs = s.netcheck(PINS, NC, ALLOW_SPLIT) + s.report(len(placement()), errs) + if '--push' in sys.argv: + s.clear(); s.place(placement(), expect()); s.push_geometry() +``` + +**页 uuid**（`.claude/r2/r2-uuids.json` 的 `boards.BASE.pages`）： + +| 页 | uuid | +|---|---| +| A3-CTRL | `38327f806bc13133` | +| A4-HUB | `09d583ff95cd35d9` | +| A5-SLOTS | `2c73c5bf77f34053` | +| A6-FAN | `68c9ffaa578572d3` | + +跑 `/c/Python314/python .claude/r2/aN_xxx.py`（**不带 `--push`**）必须打印出： + +``` +元件 N 导线 N 旗 N 端口 N 文字 N +交叉点（不相连，供人工确认）: N +本地自检通过（短路 0 / 漏连 0 / 悬空 0 / 旗端口全在端点） +``` + +--- + +## 7. 画图硬规矩（全部来自 `.claude/skills/easyeda-sch-geometry/SKILL.md`，**先读它**） + +1. **Y 轴向上**（§1）。 +2. 所有坐标必须是 **5 的倍数**（§3、§8a-2b）—— 否则旗/端口静默不连。 +3. 导线只能**横平竖直**，用 `s.w(net, p1, p2, p3...)` 逐段声明。 +4. 旗 / 端口的锚点必须落在**某段导线的端点**上，不能压在中段（§8a-2）， + 也不能和元件引脚**同坐标**（§8a：那会变成零长度导线，验证过得去、重画就断）。 +5. 同一个锚点上如果有两段**共线**的导线，合并后就成了中段 —— `netcheck` 会报。 +6. 页面范围 `x 20~1145` / `y 10~812`；**标题栏**在 `x>455 且 y<192`，文字不许伸进去（§8c）。 +7. 文字宽度经验值：`右边界 ≈ x + 字号 × (中文字数 + 0.5×其余字符数)`。 +8. **叠字是这个项目的常见事故**：端口的符号+标签往锚点**左边**伸出去约 70 个单位， + `flag_clash` 那种「横向 <20」的判据够不着。排版时给端口左边留 ≥80 的空白。 +9. 电源/地旗的 `rot`：`0` = 符号朝上（往上挂），`180` = 朝下。极性件别信方向表，按**脚号**断言。 +10. `ALLOW_SPLIT` 只放行「靠同名旗/端口成网、导线上天然分块」的网络（`GND` `+12V` `+3V3` `+5V` 这类）。 + 信号网络出现「被拆成 N 块」就是真漏连，不许往 `ALLOW_SPLIT` 里加来消错。 + +--- + +## 8. 汇报格式 + +做完后回报（**不要贴整段脚本**）： + +1. 脚本路径 + dry-run 的那三行统计输出（原样贴）。 +2. 本页画了什么（一句话一块）。 +3. **你发出/接收的端口清单**（网名 + dir），主代理要拿它对账。 +4. 你做的**设计决定**与依据（尤其是 GPIO 分配、strap 电平、上下拉取值）。 +5. 你发现的**风险 / 与方案文档不一致的地方**（B3=+12V 那种错就是这么揪出来的）。 +6. 交叉点清单（如果有），说明为什么可接受。 diff --git a/.claude/r2/A5B-SLOTS-nowv.png b/.claude/r2/A5B-SLOTS-nowv.png new file mode 100644 index 0000000..06e38bf Binary files /dev/null and b/.claude/r2/A5B-SLOTS-nowv.png differ diff --git a/.claude/r2/B1-POWER.png b/.claude/r2/B1-POWER.png new file mode 100644 index 0000000..5b1bf15 Binary files /dev/null and b/.claude/r2/B1-POWER.png differ diff --git a/.claude/r2/B2-CTRL.png b/.claude/r2/B2-CTRL.png new file mode 100644 index 0000000..cb05378 Binary files /dev/null and b/.claude/r2/B2-CTRL.png differ diff --git a/.claude/r2/B3-PHONE.png b/.claude/r2/B3-PHONE.png new file mode 100644 index 0000000..26fcb32 Binary files /dev/null and b/.claude/r2/B3-PHONE.png differ diff --git a/.claude/r2/B3B-USB.png b/.claude/r2/B3B-USB.png new file mode 100644 index 0000000..4d3339d Binary files /dev/null and b/.claude/r2/B3B-USB.png differ diff --git a/.claude/r2/HANDROUTE-M6.md b/.claude/r2/HANDROUTE-M6.md new file mode 100644 index 0000000..73d9ae2 --- /dev/null +++ b/.claude/r2/HANDROUTE-M6.md @@ -0,0 +1,38 @@ +# M6 手工补线作业单（按板上实际铜算，5 个网） + +布线方向约定：底层（器件面）纵向、顶层横向；信号线宽 0.15，过孔 0.6/0.3。 +⚠ 这些脚的出口都被**自家邻脚的引出脚 / 过孔**封死（如 `U2.15` 被 `EFUSE_EN` 的孔 (89.5,31) 卡到只剩 0.04 mm），脚本布线器四种办法（换顺序 / PathFinder / 只补线 / 过孔扇出）都到不了。交互式布线时先挪开挡路的那根引出脚或过孔再拉线。 + + +## VDAC（2 只脚）— R8.2 一根铜都没有 + - `J1.A16` (49.50, 3.45) 底层 + - `R8.2` (93.50, 49.85) 底层 + 现有铜 7.8 mm + +## $1N147（3 只脚）— U2.15 一根铜都没有 + - `R9.2` (77.20, 27.35) 底层 + - `R10.1` (79.33, 27.35) 底层 + - `U2.15` (89.75, 30.02) 底层 + 现有铜 2.1 mm + +## $1N156（2 只脚）— R11.1 U2.17 一根铜都没有 + - `R11.1` (82.33, 27.35) 底层 + - `U2.17` (91.00, 29.27) 底层 + 现有铜 0.0 mm + +## EFUSE_PG（3 只脚）— U2.2 一根铜都没有 + - `R15.1` (79.33, 31.35) 底层 + - `U2.2` (89.75, 27.02) 底层 + - `U4.16` (79.32, 20.12) 底层 + 现有铜 52.7 mm + +## $1N165（8 只脚）— R16.1 一根铜都没有 + - `R16.1` (79.33, 29.35) 底层 + - `Rs1.2` (87.87, 23.04) 底层 + - `U2.6` (87.75, 27.02) 底层 + - `U2.5` (88.25, 27.02) 底层 + - `U2.4` (88.75, 27.02) 底层 + - `U2.8` (87.00, 28.27) 底层 + - `U2.7` (87.00, 27.77) 底层 + - `U3.10` (85.05, 19.10) 底层 + 现有铜 23.1 mm diff --git a/.claude/r2/HANDROUTE.md b/.claude/r2/HANDROUTE.md new file mode 100644 index 0000000..6243d78 --- /dev/null +++ b/.claude/r2/HANDROUTE.md @@ -0,0 +1,92 @@ +# 手工布线作业单（13 条） + +布线方向约定：**底层（器件面）纵向、顶层横向**；线宽 ≥ 规则下限（信号 0.15）。 + +## VBUS_EN（3 只脚） + - `R62.2` (59.20, 14.85) 底层 + - `U4.8` (73.28, 19.47) 底层 + - `U5.3` (42.45, 21.45) 底层 + 现有铜 0.00 mm；一根都没有，整条要画 + +## EFUSE_EN（4 只脚） + - `J1.A11` (42.50, 3.45) 底层 + - `Q1.1` (78.55, 35.28) 底层 + - `R14.1` (82.33, 31.35) 底层 + - `U2.14` (89.25, 30.02) 底层 + 现有铜 88.19 mm；已有部分，缺的是把它们连成一片 + +## $1N164（3 只脚） + - `R16.2` (80.20, 29.35) 底层 + - `R17.1` (82.33, 29.35) 底层 + - `U2.3` (89.25, 27.02) 底层 + 现有铜 2.13 mm；已有部分，缺的是把它们连成一片 + +## USB_DPJ（2 只脚） + - `J4.6` (48.26, 19.94) 顶层 + - `U7.3` (49.04, 17.75) 底层 + 现有铜 0.00 mm；一根都没有，整条要画 + +## $1N151（2 只脚） + - `R12.2` (77.20, 29.35) 底层 + - `U2.19` (91.00, 28.27) 底层 + 现有铜 0.00 mm；一根都没有，整条要画 + +## SCL（4 只脚） + - `J1.B5` (36.50, 3.45) 顶层 + - `R41.1` (77.83, 25.45) 底层 + - `U3.5` (83.05, 14.87) 底层 + - `U4.22` (79.32, 16.23) 底层 + 现有铜 245.61 mm；已有部分，缺的是把它们连成一片 + +## KEY_PWR（2 只脚） + - `R42.2` (2.30, 22.85) 底层 + - `U4.4` (73.28, 16.88) 底层 + 现有铜 0.00 mm；一根都没有，整条要画 + +## INT#（2 只脚） + - `J1.B11` (42.50, 3.45) 顶层 + - `U4.1` (73.28, 14.93) 底层 + 现有铜 7.75 mm；已有部分，缺的是把它们连成一片 + +## PRSNT#（2 只脚） + - `J1.A1` (32.50, 4.00) 底层 + - `J1.B31` (64.50, 4.00) 顶层 + 现有铜 15.50 mm；已有部分，缺的是把它们连成一片 + +## +3V3（14 只脚） + - `C13.1` (86.38, 18.00) 底层 + - `C40.1` (72.30, 25.45) 底层 + - `C69.1` (67.30, 22.35) 底层 + - `J1.A10` (41.50, 3.45) 底层 + - `J1.A9` (40.50, 3.45) 底层 + - `J1.B8` (39.50, 3.45) 顶层 + - `R13.1` (76.33, 31.35) 底层 + - `R15.2` (80.20, 31.35) 底层 + - `R18.1` (80.83, 33.35) 底层 + - `R40.2` (75.70, 25.45) 底层 + - `R41.2` (78.70, 25.45) 底层 + - `U3.6` (83.05, 19.10) 底层 + - `U4.24` (79.32, 14.93) 底层 + - `U6.5` (65.30, 21.30) 底层 + 现有铜 131.15 mm；已有部分，缺的是把它们连成一片 + +## VBUS（6 只脚） + - `C67.1` (44.80, 14.85) 底层 + - `J4.51` (45.73, 21.00) 顶层 + - `R64.2` (45.70, 16.85) 底层 + - `U5.5` (45.15, 20.50) 底层 + - `U5.6` (45.15, 19.55) 底层 + - `U7.5` (48.09, 15.45) 底层 + 现有铜 21.65 mm；已有部分，缺的是把它们连成一片 + +## EFUSE_FLT（3 只脚） + - `R13.2` (77.20, 31.35) 底层 + - `U2.20` (91.00, 27.77) 底层 + - `U4.13` (79.32, 22.07) 底层 + 现有铜 57.31 mm；已有部分，缺的是把它们连成一片 + +## EFUSE_PG（3 只脚） + - `R15.1` (79.33, 31.35) 底层 + - `U2.2` (89.75, 27.02) 底层 + - `U4.16` (79.32, 20.12) 底层 + 现有铜 49.57 mm；已有部分，缺的是把它们连成一片 diff --git a/.claude/r2/M10-slots-rot180.png b/.claude/r2/M10-slots-rot180.png new file mode 100644 index 0000000..baa2426 Binary files /dev/null and b/.claude/r2/M10-slots-rot180.png differ diff --git a/.claude/r2/M11-functional-layout.png b/.claude/r2/M11-functional-layout.png new file mode 100644 index 0000000..4f26acf Binary files /dev/null and b/.claude/r2/M11-functional-layout.png differ diff --git a/.claude/r2/M11b-rc-layout.png b/.claude/r2/M11b-rc-layout.png new file mode 100644 index 0000000..1116991 Binary files /dev/null and b/.claude/r2/M11b-rc-layout.png differ diff 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R733.1 没布通", "FAN_OUT_TACH_RAW: R755.2 没布通", "PRSNT1#: J34.63 没布通", "TXD0: U20.37 没布通", "EFUSE_EN5: U20.21 没布通", "EFUSE_EN4: U20.20 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN2: U20.18 没布通", "EFUSE_EN1: U20.17 没布通", "RXD0: U20.36 没布通", "IO0: U20.27 没布通", "$3N173: R614.2 出不来", "$3N192: U7.13 出不来", "XTAL1: U32.61 没布通", "RBIAS: U32.63 没布通", "$3N197: U7.5 没布通", "VDAC2: U6.11 出不来", "VDAC2: U6.12 出不来", "FAN_IN_TACH_RAW: R751.2 没布通", "SCL2: U35.7 没布通", "SCL4: U35.11 没布通", "SDA3: U35.8 没布通", "SCL3: U35.9 没布通"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.json b/.claude/r2/_base_routes.json new file mode 100644 index 0000000..71140b2 --- /dev/null +++ b/.claude/r2/_base_routes.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 17.125, 44.5, 16.375, 44.5, 0.3, "VIN_SW"], [2, 16.375, 44.5, 12.625, 40.75, 0.3, "VIN_SW"], [2, 12.625, 40.75, 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"NTC2"], [90.5, 81.75, "NTC2"], [43.125, 6.125, "INT#"], [43.125, 9.375, "INT#"], [43.25, 23.125, "INT#"], [43.25, 24.375, "INT#"], [37.25, 47.75, "INT#"], [39.125, 47.375, "INT#"], [43.25, 45.625, "INT#"], [46.75, 43.5, "INT#"], [63.625, 41.625, "INT#"], [65.375, 37.875, "INT#"], [69.125, 41.625, "INT#"], [69.125, 60.25, "INT#"], [69.75, 64.0, "INT#"], [70.875, 73.625, "INT#"], [78.625, 75.5, "INT#"], [43.625, 84.125, "INT#"], [43.25, 85.375, "INT#"], [75.875, 80.625, "INT#"], [78.125, 80.625, "INA_ALERT"], [78.125, 78.875, "INA_ALERT"], [64.0, 78.625, "INA_ALERT"], [51.75, 78.125, "INA_ALERT"], [45.375, 74.875, "INA_ALERT"], [36.0, 74.875, "INA_ALERT"], [36.0, 79.5, "FAN_PWM"], [48.0, 79.5, "FAN_PWM"], [51.75, 79.5, "FAN_PWM"], [68.375, 74.5, "FAN_PWM"], [68.5, 64.0, "FAN_PWM"], [68.5, 62.75, "FAN_PWM"], [70.875, 61.5, "FAN_PWM"], [73.75, 61.5, "FAN_PWM"], [28.25, 81.0, "FAN_TACH_OUT"], [46.875, 80.375, "FAN_TACH_OUT"], [50.625, 80.375, "FAN_TACH_OUT"], [69.25, 75.625, "FAN_TACH_OUT"], [69.125, 66.25, "FAN_TACH_OUT"], [83.625, 61.5, "FAN_TACH_OUT"], [43.25, 10.75, "EFUSE_EN5"], [44.625, 10.625, "EFUSE_EN5"], [62.25, 10.0, "EFUSE_EN5"], [69.25, 12.75, "EFUSE_EN5"], [69.25, 19.875, "EFUSE_EN5"], [69.875, 25.625, "EFUSE_EN5"], [70.25, 42.75, "EFUSE_EN5"], [72.25, 60.25, "EFUSE_EN5"], [87.0, 73.25, "EFUSE_EN5"], [89.5, 76.0, "EFUSE_EN5"], [76.5, 75.5, "EFUSE_EN5"], [64.375, 6.125, "PRSNT5#"], [50.25, 6.75, "PRSNT5#"], [31.625, 10.625, "PRSNT5#"], [31.625, 47.5, "PRSNT5#"], [31.625, 51.75, "PRSNT5#"], [38.25, 71.0, "PRSNT5#"], [40.625, 71.0, "PRSNT5#"], [43.625, 75.5, "PRSNT5#"], [46.0, 78.875, "PRSNT5#"], [49.5, 81.25, "PRSNT5#"], [73.375, 75.5, "PRSNT5#"], [73.375, 73.625, "PRSNT5#"], [72.375, 80.625, "PRSNT5#"], [31.0, 42.0, "FAN_EN"], [32.25, 42.0, "FAN_EN"], [38.375, 48.875, "FAN_EN"], [63.625, 47.5, "FAN_EN"], [65.375, 43.5, "FAN_EN"], [67.75, 45.875, "FAN_EN"], [88.625, 10.625, "UP_VBUS_DET"], [71.875, 44.375, "UP_VBUS_DET"], [72.25, 55.5, "UP_VBUS_DET"], [67.125, 66.25, "UP_VBUS_DET"], [67.875, 72.375, "UP_VBUS_DET"], [81.375, 82.875, "MUX_RST#"], [81.125, 78.875, "MUX_RST#"], [64.625, 26.5, "PRSNT4#"], [70.875, 28.25, "PRSNT4#"], [71.125, 32.375, "PRSNT4#"], [76.375, 46.125, "PRSNT4#"], [76.375, 53.875, "PRSNT4#"], [76.75, 58.0, "PRSNT4#"], [84.25, 94.125, "IO0"], [71.5, 78.0, "IO0"], [78.375, 94.125, "TXD0"], [79.375, 87.25, "TXD0"], [83.25, 83.25, "TXD0"], [85.25, 79.0, "TXD0"], [35.125, 47.375, "SCL3"], [37.25, 49.75, "SCL3"], [45.375, 49.875, "SCL3"], [45.375, 55.625, "SCL3"], [43.0, 58.0, "SCL3"], [32.25, 80.375, "$6N49"], [29.625, 78.25, "$6N49"], [32.375, 78.875, "$6N74"], [33.375, 80.375, "$6N74"], [34.5, 80.375, "FAN_IN_TACH_RAW"], [28.25, 78.0, "FAN_IN_TACH_RAW"], [81.5, 28.125, "+3V3_HUB"], [80.75, 27.375, "+3V3_HUB"], [76.25, 27.25, "+3V3_HUB"], [75.5, 27.25, "+3V3_HUB"], [66.625, 35.0, "+3V3_HUB"], [60.625, 35.625, "+3V3_HUB"], [60.625, 38.75, "+3V3_HUB"], [58.875, 39.5, "+3V3_HUB"], [57.0, 39.125, "+3V3_HUB"], [57.5, 42.75, "+3V3_HUB"], [72.5, 27.25, "+3V3_HUB"], [60.625, 23.125, "+3V3_HUB"], [53.625, 23.0, "+3V3_HUB"], [44.25, 32.5, "+3V3_HUB"], [44.125, 33.25, "+3V3_HUB"], [42.75, 37.75, "+3V3_HUB"], [41.0, 36.75, "+3V3_HUB"], [38.875, 36.375, "+3V3_HUB"], [36.75, 37.875, "+3V3_HUB"], [37.75, 40.125, "+3V3_HUB"], [37.75, 40.875, "+3V3_HUB"], [37.75, 42.125, "+3V3_HUB"], [39.5, 42.125, "+3V3_HUB"], [37.375, 37.875, "+3V3_HUB"], [38.25, 35.75, "+3V3_HUB"], [13.125, 38.0, "GND"], [13.0, 65.25, "+3V3"], [13.0, 71.75, "+3V3"], [18.5, 41.25, "GND"], [16.5, 41.25, "+3V3"], [88.875, 55.25, "+3V3"], [91.125, 56.875, "+3V3"], [90.5, 55.5, "GND"], [86.25, 54.25, "GND"], [33.75, 56.625, "GND"], [33.0, 55.25, "+3V3"], [91.25, 84.0, "GND"], [92.5, 81.75, "GND"], [41.25, 38.5, "GND"], [40.75, 39.875, "GND"], [74.25, 30.25, "GND"], [31.75, 93.375, "GND"], [35.625, 91.875, "GND"], [40.5, 91.875, "+3V3"], [41.5, 91.875, "+3V3"], [44.75, 93.25, "GND"], [46.5, 91.875, "GND"], [47.5, 91.875, "GND"], [48.5, 91.875, "GND"], [50.5, 94.625, "GND"], [51.5, 94.625, "GND"], [53.5, 94.625, "GND"], [54.5, 94.625, "GND"], [55.5, 94.625, "GND"], [56.5, 94.625, "GND"], [57.5, 94.625, "GND"], [58.5, 94.625, "GND"], [59.5, 94.625, "GND"], [60.5, 94.625, "GND"], [61.5, 94.625, "GND"], [62.5, 94.625, "GND"], [63.5, 94.625, "GND"], [64.5, 94.625, "GND"], [35.625, 87.375, "GND"], [38.5, 87.375, "GND"], [39.5, 87.375, "+3V3"], [45.5, 87.375, "GND"], [46.375, 87.375, "GND"], [49.625, 87.375, "GND"], [50.5, 87.375, "GND"], [51.5, 87.375, "GND"], [53.25, 84.625, "GND"], [54.5, 84.625, "GND"], [55.5, 87.375, "GND"], [56.5, 87.375, "GND"], [57.5, 87.375, "GND"], [58.5, 87.375, "GND"], [59.5, 87.375, "GND"], [60.5, 87.375, "GND"], [61.5, 87.375, "GND"], [62.5, 87.375, "GND"], [63.5, 87.375, "GND"], [66.25, 86.0, "GND"], [31.75, 73.0, "GND"], [47.625, 71.5, "GND"], [48.5, 71.5, "GND"], [50.5, 74.25, "GND"], [51.5, 71.5, "GND"], [53.5, 71.5, "GND"], [54.5, 71.5, "GND"], [55.5, 71.5, "GND"], [56.5, 71.5, "GND"], [57.5, 71.5, "GND"], [58.5, 71.5, "GND"], [59.5, 71.5, "GND"], [60.5, 71.5, "GND"], [61.5, 71.5, "GND"], [62.5, 71.5, "GND"], [63.5, 71.5, "GND"], [35.625, 67.125, "GND"], [38.5, 67.125, "GND"], [39.5, 67.125, "+3V3"], [45.5, 64.375, "GND"], [50.25, 64.375, "GND"], [51.5, 64.375, "GND"], [52.5, 64.375, "GND"], [53.5, 64.375, "GND"], [56.625, 67.125, "GND"], [57.5, 67.125, "GND"], [58.5, 67.125, "GND"], [59.5, 67.125, "GND"], [60.5, 64.375, "GND"], [61.5, 64.375, "GND"], [62.5, 64.375, "GND"], [63.5, 67.125, "GND"], [66.25, 65.125, "GND"], [35.625, 51.25, "GND"], [40.5, 51.25, "+3V3"], [41.5, 51.25, "+3V3"], [49.25, 51.125, "GND"], [50.5, 51.25, "GND"], [32.375, 30.875, "GND"], [35.625, 30.875, "GND"], [40.5, 30.875, "+3V3"], [41.5, 30.875, "+3V3"], [35.625, 23.75, "GND"], [38.5, 23.75, "GND"], [39.5, 23.75, "+3V3"], [45.5, 26.5, "GND"], [46.5, 26.5, "GND"], [49.5, 23.75, "GND"], [50.5, 23.75, "GND"], [51.375, 23.75, "GND"], [52.5, 26.5, "GND"], [53.5, 26.5, "GND"], [54.5, 26.5, "GND"], [55.25, 26.5, "GND"], [57.625, 23.75, "GND"], [58.5, 23.75, "GND"], [60.75, 26.5, "GND"], [61.5, 26.5, "GND"], [62.75, 23.75, "GND"], [63.5, 23.75, "GND"], [65.5, 23.75, "GND"], [35.625, 13.375, "GND"], [40.5, 13.375, "+3V3"], [41.5, 13.375, "+3V3"], [44.75, 12.0, "GND"], [46.5, 13.375, "GND"], [47.5, 13.375, "GND"], [48.5, 13.375, "GND"], [51.0, 13.375, "GND"], [64.125, 10.5, "GND"], [35.625, 6.125, "GND"], [38.5, 6.125, "GND"], [39.5, 6.125, "+3V3"], [44.75, 4.75, "GND"], [46.375, 6.125, "GND"], [49.5, 3.375, "GND"], [50.5, 3.375, "GND"], [51.5, 3.375, "GND"], [52.5, 3.375, "GND"], [53.5, 3.375, "GND"], [54.5, 3.375, "GND"], [55.5, 3.375, "GND"], [56.5, 3.375, "GND"], [57.5, 3.375, "GND"], [58.5, 3.375, "GND"], [59.5, 3.375, "GND"], [60.5, 3.375, "GND"], [61.5, 3.375, "GND"], [62.5, 3.375, "GND"], [63.5, 3.375, "GND"], [66.25, 4.75, "GND"], [11.5, 68.5, "+3V3"], [22.25, 86.625, "GND"], [15.0, 81.375, "GND"], [27.0, 79.125, "GND"], [25.875, 82.75, "GND"], [8.125, 22.125, "GND"], [4.625, 70.625, "+3V3"], [2.25, 64.625, "GND"], [4.625, 41.75, "GND"], [82.0, 92.125, "+3V3"], [86.375, 81.25, "+3V3"], [78.875, 81.875, "+3V3"], [80.625, 57.375, "+3V3"], [77.625, 56.125, "+3V3"], [74.625, 56.125, "+3V3"], [77.625, 55.125, "+3V3"], [71.625, 81.875, "+3V3"], [80.625, 84.125, "+3V3"], [86.875, 84.125, "+3V3"], [17.125, 62.875, "GND"], [84.875, 12.125, "GND"], [81.875, 12.125, "GND"], [92.125, 10.5, "GND"], [21.75, 83.375, "GND"], [2.5, 87.625, "GND"], [23.375, 76.625, "+3V3"], [13.75, 76.875, "GND"], [23.25, 79.75, "+3V3"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.625, 45.0, "GND"], [16.0, 42.625, "GND"], [17.375, 42.0, "+3V3"], [89.5, 61.5, "GND"], [89.5, 79.0, "GND"], [80.0, 68.875, "GND"], [3.25, 45.0, "GND"], [18.375, 70.125, "GND"], [77.0, 24.625, "GND"], [55.0, 41.375, "GND"], [35.625, 61.0, "GND"], [42.0, 43.875, "GND"]], "logs": ["+12V: R4.2 找不到落过孔的地方", "VIN_SW: C4.2 没布通", "VBUS_DET: U32.44 没布通", "CFGSEL1: U32.42 没布通", "NONREM1: U32.40 没布通", "CFGSEL0: U32.41 没布通", "VDD18PLL: U32.62 没布通", "+5V: J37.32 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "SDA: U13.4 没布通", "INT#: J35.43 没布通", "FAN_TACH_IN: U20.fan:5 没布通", "MUX_RST#: U35.fan:3 没布通", "EFUSE_EN4: U20.fan:20 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "SCL5: U35.fan:14 没布通", "EFUSE_EN1: U20.fan:17 没布通", "SDA5: U35.fan:13 没布通", "EN: U20.fan:3 没布通", "EN: C603.1 没布通", "PRSNT1#: U20.fan:8 没布通", "PRSNT1#: R606.2 没布通", "SCL4: U35.fan:11 没布通", "EFUSE_EN3: U20.fan:19 没布通", "SDA4: U35.fan:10 没布通", "EFUSE_EN2: U20.fan:18 没布通", "PRSNT3#: R608.2 没布通", "PRSNT3#: U20.fan:10 没布通", "PRSNT2#: R607.2 没布通", "PRSNT2#: U20.fan:9 没布通", "RXD0: U20.fan:36 没布通", "SDA1: U35.fan:4 没布通", "BST3V3: C8.2 没布通", "$2N72: R706.2 没布通", "$2N72: R707.1 没布通", "$2N70: C733.2 没布通", "$6N48: R747.1 没布通", "FAN_OUT_TACH_RAW: R754.1 没布通", "FAN_PWM_L: J26.4 没布通", "FAN_12V_SW: J27.2 没布通", "FAN_12V_SW: R750.2 没布通", "FAN_12V_SW: R754.2 出不来", "FAN_12V_SW: J26.2 没布通", "FAN_12V_SW: D2.1 没布通", "FAN_12V_SW: Q7.3 没布通", "+3V3_HUB: U32.fan:vd 没布通", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.52 没布通", "+3V3_HUB: U32.57 没布通", "+3V3_HUB: U32.64 没布通", "+3V3_HUB: C750.1 没布通", "GND: C604.2 找不到落过孔的地方", "+3V3: C604.1 找不到落过孔的地方", "GND: C607.2 找不到落过孔的地方", "+3V3: C607.1 找不到落过孔的地方", "GND: C609.1 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J35.4 找不到落过孔的地方", "+3V3: J35.9 找不到落过孔的地方", "+3V3: J35.10 找不到落过孔的地方", "GND: J35.31 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.12 找不到落过孔的地方", "GND: J36.13 找不到落过孔的地方", "GND: J36.14 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.21 找不到落过孔的地方", "GND: J36.22 找不到落过孔的地方", "GND: J36.23 找不到落过孔的地方", "GND: J36.24 找不到落过孔的地方", "GND: J36.25 找不到落过孔的地方", "GND: J36.26 找不到落过孔的地方", "GND: J36.27 找不到落过孔的地方", "GND: J36.28 找不到落过孔的地方", "GND: J36.29 找不到落过孔的地方", "GND: J36.30 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "+3V3: J36.40 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.12 找不到落过孔的地方", "GND: J37.13 找不到落过孔的地方", "GND: J37.14 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: J38.1 找不到落过孔的地方", "GND: J38.20 找不到落过孔的地方", "+3V3: R602.1 找不到落过孔的地方", "+3V3: R604.1 找不到落过孔的地方", "+3V3: R614.1 找不到落过孔的地方", "GND: R615.1 找不到落过孔的地方", "+3V3: R616.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R719.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +12V: R4.2 一根铜都没有", "[连通性] BST3V3: C8.2 U19.6 一根铜都没有", "[连通性] +3V3: C604.1 C607.1 J35.9 J35.10 一根铜都没有", "[连通性] EN: C603.1 一根铜都没有", "[连通性] $2N70: C733.2 一根铜都没有", "[连通性] +5V: J37.32 一根铜都没有", "[连通性] NTC1: C736.1 R660.2 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: C750.1 U32.46 U32.52 U32.57 一根铜都没有", "[连通性] FAN_12V_SW: C738.1 D2.1 J26.2 J27.2 一根铜都没有", "[连通性] NTC2: 铜分成 2 块", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $6N49: 铜分成 2 块", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] FAN_OUT_TACH_RAW: J27.3 一根铜都没有", "[连通性] RXD0: J33.3 一根铜都没有", "[连通性] EFUSE_EN1: J34.11 一根铜都没有", "[连通性] SDA1: J34.38 一根铜都没有", "[连通性] INT#: J35.43 一根铜都没有", "[连通性] PRSNT1#: J34.63 R606.2 一根铜都没有", "[连通性] EFUSE_EN2: J35.11 一根铜都没有", "[连通性] PRSNT2#: J35.63 R607.2 一根铜都没有", "[连通性] EFUSE_EN3: J36.11 一根铜都没有", "[连通性] PRSNT3#: J36.63 R608.2 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] SDA4: J37.38 一根铜都没有", "[连通性] SCL5: J38.37 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: 铜分成 2 块", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] FAN_TACH_IN: 铜分成 2 块", "[连通性] SDA: U13.4 一根铜都没有", "[连通性] INA_ALERT: 铜分成 2 块", "[连通性] MUX_RST#: 铜分成 2 块", "[连通性] $2N72: R706.2 R707.1 U30.4 一根铜都没有", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.pre-server.json b/.claude/r2/_base_routes.pre-server.json new file mode 100644 index 0000000..5b4dec6 --- /dev/null +++ b/.claude/r2/_base_routes.pre-server.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 17.125, 44.5, 16.375, 44.5, 0.3, "VIN_SW"], [2, 16.375, 44.5, 12.625, 40.75, 0.3, "VIN_SW"], [2, 12.625, 40.75, 12.625, 40.625, 0.3, "VIN_SW"], [2, 17.389, 44.501, 17.125, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.625, 40.625, 0.3, "VIN_SW"], [1, 18.5, 43.875, 17.375, 45.0, 0.3, "+12V"], [1, 17.375, 45.0, 16.0, 45.0, 0.3, "+12V"], [1, 16.0, 45.0, 15.75, 45.25, 0.3, "+12V"], [1, 15.75, 45.25, 14.0, 45.25, 0.3, "+12V"], [1, 14.0, 45.25, 13.75, 45.5, 0.3, "+12V"], [1, 13.75, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.625, 46.375, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.875, 0.3, "+12V"], [2, 12.499, 46.566, 12.625, 46.375, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, "UP_DM"], [2, 50.249, 43.03, 50.249, 47.9995, 0.28, "USB3_DM"], [2, 50.249, 47.9995, 48.499, 47.9995, 0.28, "USB3_DM"], [2, 48.499, 47.9995, 48.499, 47.5995, 0.28, "USB3_DM"], [2, 50.749, 43.03, 50.749, 48.799499999999995, 0.28, "USB3_DP"], [2, 50.749, 48.799499999999995, 47.501, 48.799499999999995, 0.28, "USB3_DP"], [2, 47.501, 48.799499999999995, 47.501, 48.299499999999995, 0.28, "USB3_DP"], [1, 48.499, 47.5995, 48.499, 45.4, 0.28, "USB3_DM"], [1, 47.501, 48.299499999999995, 47.501, 45.4, 0.28, "USB3_DP"], [2, 53.749, 43.03, 53.749, 43.906, 0.2, "+3V3_HUB"], [2, 53.749, 43.906, 56.877, 43.906, 0.2, "+3V3_HUB"], [2, 56.877, 43.906, 56.877, 38.829, 0.2, "+3V3_HUB"], [2, 56.877, 38.829, 55.951, 38.829, 0.2, "+3V3_HUB"], [2, 49.751, 43.03, 49.751, 46.299, 0.2, "+3V3_HUB"], [2, 49.751, 46.299, 49.401, 46.899, 0.2, "+3V3_HUB"], [2, 52.25, 43.03, 52.25, 46.299, 0.2, "+3V3_HUB"], [2, 52.25, 46.299, 53.0, 46.899, 0.2, "+3V3_HUB"], [1, 49.401, 46.899, 65.999, 46.899, 0.2, "+3V3_HUB"], [2, 47.749, 43.03, 47.749, 43.755, 0.28, "USB1_DM"], [2, 47.749, 43.755, 44.249, 47.255, 0.28, "USB1_DM"], [2, 44.249, 47.255, 44.249, 89.14, 0.28, "USB1_DM"], [2, 44.249, 89.14, 48.499, 89.14, 0.28, "USB1_DM"], [2, 48.499, 89.14, 48.499, 88.04, 0.28, "USB1_DM"], [1, 48.499, 88.04, 48.499, 86.04, 0.28, "USB1_DM"], [2, 48.25, 43.03, 48.25, 44.005, 0.28, "USB1_DP"], [2, 48.25, 44.005, 44.75, 47.505, 0.28, "USB1_DP"], [2, 44.75, 47.505, 44.75, 88.64, 0.28, "USB1_DP"], [2, 44.75, 88.64, 47.501, 88.64, 0.28, "USB1_DP"], [2, 47.501, 88.64, 47.501, 88.04, 0.28, "USB1_DP"], [1, 47.501, 88.04, 47.501, 86.04, 0.28, "USB1_DP"], [2, 48.75, 43.03, 48.75, 44.255, 0.28, "USB2_DM"], [2, 48.75, 44.255, 46.25, 46.755, 0.28, "USB2_DM"], [2, 46.25, 46.755, 46.25, 68.819, 0.28, "USB2_DM"], [2, 46.25, 68.819, 48.499, 68.819, 0.28, "USB2_DM"], [2, 48.499, 68.819, 48.499, 67.719, 0.28, "USB2_DM"], [1, 48.499, 67.719, 48.499, 65.72, 0.28, "USB2_DM"], [2, 49.251, 43.03, 49.251, 44.505, 0.28, "USB2_DP"], [2, 49.251, 44.505, 46.751, 47.005, 0.28, "USB2_DP"], [2, 46.751, 47.005, 46.751, 68.319, 0.28, "USB2_DP"], [2, 46.751, 68.319, 47.501, 68.319, 0.28, "USB2_DP"], [2, 47.501, 68.319, 47.501, 67.719, 0.28, "USB2_DP"], [1, 47.501, 67.719, 47.501, 65.72, 0.28, "USB2_DP"], [2, 53.251, 43.03, 53.251, 44.406, 0.28, "USB5_DP"], [2, 53.251, 44.406, 59.5, 44.406, 0.28, "USB5_DP"], [2, 59.5, 44.406, 59.5, 7.9, 0.28, "USB5_DP"], [2, 59.5, 7.9, 47.501, 7.9, 0.28, "USB5_DP"], [2, 47.501, 7.9, 47.501, 6.76, 0.28, "USB5_DP"], [1, 47.501, 6.76, 47.501, 4.76, 0.28, "USB5_DP"], [2, 52.751, 43.03, 52.751, 44.906, 0.28, "USB5_DM"], [2, 52.751, 44.906, 60.0, 44.906, 0.28, "USB5_DM"], [2, 60.0, 44.906, 60.0, 7.4, 0.28, "USB5_DM"], [2, 60.0, 7.4, 48.499, 7.4, 0.28, "USB5_DM"], [2, 48.499, 7.4, 48.499, 6.76, 0.28, "USB5_DM"], [1, 48.499, 6.76, 48.499, 4.76, 0.28, "USB5_DM"], [2, 51.75, 43.03, 51.75, 47.749, 0.28, "USB4_DP"], [2, 51.75, 47.749, 61.3, 47.749, 0.28, "USB4_DP"], [2, 61.3, 47.749, 61.3, 30.399, 0.28, "USB4_DP"], [1, 61.3, 30.399, 47.501, 30.399, 0.28, "USB4_DP"], [1, 47.501, 30.399, 47.501, 25.08, 0.28, "USB4_DP"], [2, 51.25, 43.03, 51.25, 48.249, 0.28, "USB4_DM"], [2, 51.25, 48.249, 62.0, 48.249, 0.28, "USB4_DM"], [2, 62.0, 48.249, 62.0, 29.599, 0.28, "USB4_DM"], [1, 62.0, 29.599, 48.499, 29.599, 0.28, "USB4_DM"], [1, 48.499, 29.599, 48.499, 25.08, 0.28, "USB4_DM"], [2, 47.051, 36.83, 46.276, 36.83, 0.2, "USB6_DM"], [2, 46.276, 36.83, 45.776, 36.58, 0.2, "USB6_DM"], [2, 47.051, 37.33, 46.276, 37.33, 0.2, "USB6_DP"], [2, 46.276, 37.33, 45.175, 37.33, 0.2, "USB6_DP"], [2, 47.051, 39.329, 46.276, 39.329, 0.2, "UP_DM"], [2, 46.276, 39.329, 45.776, 39.079, 0.2, "UP_DM"], [2, 47.051, 39.83, 46.276, 39.83, 0.2, "UP_DP"], [2, 46.276, 39.83, 45.175, 39.83, 0.2, "UP_DP"], [2, 72.625, 59.25, 70.75, 57.375, 0.28, "USB6_DP"], [2, 70.75, 57.375, 70.75, 57.125, 0.28, "USB6_DP"], [1, 70.75, 57.125, 70.625, 57.0, 0.28, "USB6_DP"], [1, 70.625, 57.0, 70.625, 52.875, 0.28, "USB6_DP"], [1, 70.625, 52.875, 70.5, 52.75, 0.28, "USB6_DP"], [1, 70.5, 52.75, 70.5, 52.5, 0.28, "USB6_DP"], [1, 70.5, 52.5, 70.375, 52.375, 0.28, "USB6_DP"], [1, 70.375, 52.375, 70.375, 46.25, 0.28, "USB6_DP"], [1, 70.375, 46.25, 70.25, 46.125, 0.28, "USB6_DP"], [1, 70.25, 46.125, 69.25, 46.125, 0.28, "USB6_DP"], [1, 69.25, 46.125, 60.875, 37.75, 0.28, "USB6_DP"], [1, 60.875, 37.75, 45.375, 37.75, 0.28, "USB6_DP"], [2, 73.386, 60.249, 72.625, 59.25, 0.28, "USB6_DP"], [1, 45.175, 37.33, 45.375, 37.75, 0.28, "USB6_DP"], [2, 74.25, 59.25, 71.875, 56.875, 0.28, "USB6_DM"], [2, 71.875, 56.875, 71.875, 56.375, 0.28, "USB6_DM"], [2, 71.875, 56.375, 71.375, 55.875, 0.28, "USB6_DM"], [1, 71.375, 55.875, 71.25, 55.75, 0.28, "USB6_DM"], [1, 71.25, 55.75, 71.25, 52.375, 0.28, "USB6_DM"], [1, 71.25, 52.375, 71.125, 52.25, 0.28, "USB6_DM"], [1, 71.125, 52.25, 71.125, 52.0, 0.28, "USB6_DM"], [1, 71.125, 52.0, 71.0, 51.875, 0.28, "USB6_DM"], [1, 71.0, 51.875, 71.0, 45.75, 0.28, "USB6_DM"], [1, 71.0, 45.75, 62.0, 36.75, 0.28, "USB6_DM"], [1, 62.0, 36.75, 46.25, 36.75, 0.28, "USB6_DM"], [2, 74.656, 60.249, 74.25, 59.25, 0.28, "USB6_DM"], [1, 45.776, 36.58, 46.25, 36.75, 0.28, "USB6_DM"], [1, 44.75, 39.375, 44.625, 39.25, 0.28, "UP_DP"], [1, 44.625, 39.25, 44.625, 38.5, 0.28, "UP_DP"], [1, 44.625, 38.5, 44.25, 38.125, 0.28, "UP_DP"], [1, 44.25, 38.125, 44.25, 36.5, 0.28, "UP_DP"], [1, 44.25, 36.5, 44.875, 35.875, 0.28, "UP_DP"], [1, 44.875, 35.875, 44.875, 35.75, 0.28, "UP_DP"], [1, 44.875, 35.75, 45.0, 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"GND"], [62.5, 10.625, "GND"], [63.5, 10.625, "GND"], [35.625, 6.125, "GND"], [38.5, 6.125, "GND"], [39.5, 6.125, "+3V3"], [44.75, 4.5, "GND"], [46.375, 6.125, "GND"], [49.625, 6.125, "GND"], [50.5, 6.125, "GND"], [51.5, 6.125, "GND"], [52.5, 6.125, "GND"], [53.5, 6.125, "GND"], [54.5, 6.125, "GND"], [55.5, 6.125, "GND"], [56.5, 6.125, "GND"], [57.5, 6.125, "GND"], [58.5, 6.125, "GND"], [59.5, 6.125, "GND"], [60.5, 6.125, "GND"], [61.5, 6.125, "GND"], [62.5, 6.125, "GND"], [63.5, 6.125, "GND"], [66.25, 4.75, "GND"], [11.5, 68.5, "+3V3"], [22.25, 88.0, "GND"], [15.0, 82.75, "GND"], [26.25, 78.25, "GND"], [25.0, 82.0, "GND"], [8.125, 22.125, "GND"], [5.375, 71.25, "+3V3"], [2.25, 64.625, "GND"], [4.625, 41.75, "GND"], [75.125, 81.875, "+3V3"], [78.875, 81.875, "+3V3"], [80.625, 57.375, "+3V3"], [74.25, 57.375, "+3V3"], [70.875, 81.25, "+3V3"], [80.625, 84.125, "+3V3"], [88.625, 80.5, "+3V3"], [86.875, 84.125, "+3V3"], [17.875, 63.5, "GND"], [84.5, 10.875, "GND"], [64.75, 35.375, "GND"], [92.125, 10.5, "GND"], [21.75, 83.375, "GND"], [18.125, 83.0, "GND"], [3.125, 88.0, "GND"], [23.375, 76.625, "+3V3"], [13.75, 76.875, "GND"], [21.875, 79.625, "+3V3"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.625, 45.0, "GND"], [16.0, 42.625, "GND"], [17.375, 42.0, "+3V3"], [6.25, 70.125, "GND"], [89.5, 79.0, "GND"], [80.0, 69.5, "GND"], [3.25, 45.0, "GND"], [18.5, 70.125, "GND"], [77.0, 24.625, "GND"], [55.0, 41.375, "GND"], [35.5, 63.375, "GND"], [42.0, 43.875, "GND"]], "logs": ["+12V: R4.2 找不到落过孔的地方", "VIN_SW: C4.2 没布通", "VBUS_DET: U32.44 没布通", "CFGSEL1: U32.42 没布通", "NONREM1: U32.40 没布通", "CFGSEL0: U32.41 没布通", "VDD18PLL: U32.62 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "SDA: U13.4 没布通", "$3N197: U7.fan:5 没布通", "$3N173: U6.fan:16 没布通", "FAN_TACH_IN: U20.fan:5 没布通", "MUX_RST#: U35.fan:3 没布通", "EFUSE_EN4: U20.fan:20 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "SCL5: U35.fan:14 没布通", "SDA5: U35.fan:13 没布通", "EN: U20.fan:3 没布通", "EN: C603.1 没布通", "PRSNT1#: U20.fan:8 没布通", "PRSNT1#: R606.2 没布通", "SCL4: U35.fan:11 没布通", "EFUSE_EN3: U20.fan:19 没布通", "SDA4: U35.fan:10 没布通", "SDA1: U35.fan:4 没布通", "SCL3: U35.fan:9 没布通", "$6N48: R747.1 没布通", "$6N45: R748.2 没布通", "$2N72: R706.2 没布通", "$6N55: R733.2 没布通", "FAN_PWM_L: J26.4 没布通", "+5V: R706.1 没布通", "+5V: J35.19 没布通", "+5V: J36.19 没布通", "+5V: J34.19 没布通", "+5V: J35.32 没布通", "+5V: J36.32 没布通", "+5V: J37.19 没布通", "+5V: J34.32 没布通", "+5V: J37.32 没布通", "+5V: J38.19 没布通", "+5V: C753.1 没布通", "+5V: C752.1 没布通", "+5V: J38.32 没布通", "FAN_12V_SW: J27.2 没布通", "FAN_12V_SW: R750.2 没布通", "FAN_12V_SW: R754.2 没布通", "FAN_12V_SW: C738.1 没布通", "+3V3_HUB: U32.fan:vd 没布通", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.52 没布通", "+3V3_HUB: U32.57 没布通", "+3V3_HUB: C750.1 没布通", "GND: C604.2 找不到落过孔的地方", "+3V3: C604.1 找不到落过孔的地方", "GND: C607.2 找不到落过孔的地方", "+3V3: C607.1 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.17 找不到落过孔的地方", "GND: J35.18 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "+3V3: J35.40 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "+3V3: J36.10 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "+3V3: J36.40 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.12 找不到落过孔的地方", "GND: J37.13 找不到落过孔的地方", "GND: J37.14 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "+3V3: R601.1 找不到落过孔的地方", "+3V3: R602.1 找不到落过孔的地方", "+3V3: R607.1 找不到落过孔的地方", "+3V3: R609.1 找不到落过孔的地方", "+3V3: R614.1 找不到落过孔的地方", "+3V3: R616.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R718.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U20.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +12V: R4.2 一根铜都没有", "[连通性] +3V3: C604.1 C607.1 J35.40 J36.10 一根铜都没有", "[连通性] EN: C603.1 一根铜都没有", "[连通性] $3N173: 铜分成 2 块", "[连通性] +5V: C752.1 J34.19 J34.32 J35.19 一根铜都没有", "[连通性] NTC1: C736.1 R660.2 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: C750.1 U32.46 U32.52 U32.57 一根铜都没有", "[连通性] FAN_12V_SW: C738.1 J27.2 R750.2 R754.2 一根铜都没有", "[连通性] NTC2: 铜分成 2 块", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $6N49: 铜分成 2 块", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] SDA1: J34.38 一根铜都没有", "[连通性] INT#: 铜分成 2 块", "[连通性] PRSNT1#: J34.63 R606.2 一根铜都没有", "[连通性] EFUSE_EN3: J36.11 一根铜都没有", "[连通性] SCL3: J36.37 一根铜都没有", "[连通性] PRSNT3#: 铜分成 2 块", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] SDA4: J37.38 一根铜都没有", "[连通性] SCL5: J38.37 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: 铜分成 2 块", "[连通性] $6N55: Q6.1 一根铜都没有", "[连通性] $6N45: R748.2 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] FAN_TACH_IN: 铜分成 2 块", "[连通性] SDA: U13.4 一根铜都没有", "[连通性] INA_ALERT: 铜分成 2 块", "[连通性] MUX_RST#: 铜分成 2 块", "[连通性] $3N197: R617.2 一根铜都没有", "[连通性] $2N72: R706.2 一根铜都没有", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.pre-shift.json b/.claude/r2/_base_routes.pre-shift.json new file mode 100644 index 0000000..6f52a10 --- /dev/null +++ b/.claude/r2/_base_routes.pre-shift.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 16.75, 44.5, 16.5, 44.5, 0.3, "VIN_SW"], [2, 16.5, 44.5, 12.75, 40.75, 0.3, "VIN_SW"], [2, 17.389, 44.501, 16.75, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.75, 40.75, 0.3, "VIN_SW"], [1, 18.5, 43.75, 16.0, 46.25, 0.3, "+12V"], [1, 16.0, 46.25, 13.25, 46.25, 0.3, "+12V"], [1, 13.25, 46.25, 13.0, 46.5, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.75, 0.3, "+12V"], [2, 12.499, 46.566, 13.0, 46.5, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, "UP_DM"], [2, 47.5, 44.0, 48.0, 44.0, 0.28, "USB3_DP"], [2, 48.0, 44.0, 48.25, 43.75, 0.28, "USB3_DP"], [1, 47.501, 45.4, 47.5, 44.0, 0.28, "USB3_DP"], [2, 48.25, 43.03, 48.25, 43.75, 0.28, "USB3_DP"], [1, 48.75, 44.0, 48.75, 43.0, 0.28, "USB3_DM"], [1, 48.75, 43.0, 47.75, 42.0, 0.28, "USB3_DM"], [2, 47.75, 42.0, 47.5, 42.25, 0.28, "USB3_DM"], [1, 48.499, 45.4, 48.75, 44.0, 0.28, "USB3_DM"], [2, 47.749, 43.03, 47.749, 42.3145, 0.28, "USB3_DM"], [2, 47.749, 42.3145, 47.5, 42.25, 0.28, "USB3_DM"], [1, 47.25, 64.5, 46.5, 63.75, 0.28, "USB2_DP"], [1, 46.5, 63.75, 46.5, 62.0, 0.28, "USB2_DP"], [1, 46.5, 62.0, 45.5, 61.0, 0.28, "USB2_DP"], [1, 45.5, 61.0, 45.5, 58.0, 0.28, "USB2_DP"], [1, 45.5, 58.0, 44.75, 57.25, 0.28, "USB2_DP"], [1, 44.75, 57.25, 44.75, 43.75, 0.28, "USB2_DP"], [1, 44.75, 43.75, 46.0, 42.5, 0.28, "USB2_DP"], [1, 46.0, 42.5, 46.0, 42.0, 0.28, "USB2_DP"], [2, 46.0, 42.0, 46.25, 42.25, 0.28, "USB2_DP"], [1, 47.501, 65.72, 47.25, 64.5, 0.28, "USB2_DP"], [2, 46.749, 43.03, 46.749, 42.3145, 0.28, "USB2_DP"], [2, 46.749, 42.3145, 46.25, 42.25, 0.28, "USB2_DP"], [1, 48.25, 64.5, 48.25, 64.25, 0.28, "USB2_DM"], [1, 48.25, 64.25, 48.0, 64.0, 0.28, "USB2_DM"], [2, 48.0, 64.0, 47.0, 63.0, 0.28, "USB2_DM"], [2, 47.0, 63.0, 46.5, 63.0, 0.28, "USB2_DM"], [2, 46.5, 63.0, 46.25, 62.75, 0.28, "USB2_DM"], [2, 46.25, 62.75, 45.75, 62.75, 0.28, "USB2_DM"], [1, 45.75, 62.75, 44.75, 61.75, 0.28, "USB2_DM"], [1, 44.75, 61.75, 44.75, 58.75, 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52.5, "GND"], [50.5, 52.5, "GND"], [51.25, 52.0, "GND"], [54.75, 53.75, "GND"], [55.75, 52.75, "GND"], [56.5, 52.5, "GND"], [57.5, 52.5, "GND"], [58.5, 52.5, "GND"], [59.5, 52.5, "GND"], [60.5, 52.5, "GND"], [61.5, 52.5, "GND"], [62.5, 52.5, "GND"], [63.25, 53.0, "GND"], [64.25, 54.0, "GND"], [35.75, 47.0, "GND"], [45.75, 45.5, "GND"], [46.5, 45.5, "GND"], [49.5, 45.5, "GND"], [50.5, 45.5, "GND"], [51.5, 45.5, "GND"], [52.5, 45.5, "GND"], [53.5, 45.5, "GND"], [54.5, 45.5, "GND"], [55.5, 45.5, "GND"], [56.5, 45.5, "GND"], [57.25, 45.5, "GND"], [60.5, 45.25, "GND"], [61.5, 45.5, "GND"], [62.5, 45.5, "GND"], [63.5, 45.5, "GND"], [31.75, 31.25, "GND"], [45.75, 32.25, "GND"], [46.5, 32.25, "GND"], [47.5, 32.25, "GND"], [48.5, 32.25, "GND"], [50.5, 32.5, "GND"], [56.5, 32.25, "GND"], [57.25, 32.75, "GND"], [58.0, 33.75, "GND"], [61.25, 30.75, "GND"], [61.75, 31.25, "GND"], [63.0, 33.75, "GND"], [63.25, 32.75, "GND"], [64.25, 33.75, "GND"], [35.75, 23.5, "GND"], [44.75, 24.5, "GND"], [45.75, 23.5, "GND"], [50.25, 26.5, "GND"], [50.5, 25.0, "GND"], [51.5, 25.0, "GND"], [52.5, 25.0, "GND"], [53.5, 25.0, "GND"], [54.5, 25.0, "GND"], [55.25, 25.75, "GND"], [56.0, 26.5, "GND"], [58.75, 23.75, "GND"], [59.75, 25.0, "GND"], [60.5, 25.0, "GND"], [61.5, 25.0, "GND"], [62.5, 25.0, "GND"], [63.25, 25.0, "GND"], [65.75, 24.75, "GND"], [32.25, 12.0, "GND"], [35.75, 10.5, "GND"], [45.5, 12.0, "GND"], [46.5, 12.0, "GND"], [47.25, 12.75, "GND"], [50.5, 12.0, "GND"], [51.25, 12.0, "GND"], [53.75, 12.0, "GND"], [54.5, 12.0, "GND"], [55.5, 12.0, "GND"], [56.5, 12.0, "GND"], [57.5, 12.0, "GND"], [58.5, 12.0, "GND"], [59.5, 12.0, "GND"], [60.5, 12.0, "GND"], [61.5, 11.75, "GND"], [62.5, 11.5, "GND"], [63.5, 11.5, "GND"], [64.25, 11.5, "GND"], [35.75, 6.25, "GND"], [38.5, 4.5, "GND"], [45.5, 4.75, "GND"], [46.5, 4.75, "GND"], [49.5, 4.75, "GND"], [50.5, 4.75, "GND"], [51.5, 4.75, "GND"], [52.5, 4.75, "GND"], [53.5, 4.75, "GND"], [54.5, 4.75, "GND"], [55.5, 4.75, "GND"], [56.5, 4.75, "GND"], [57.5, 4.75, "GND"], [58.5, 4.75, "GND"], [59.5, 4.75, "GND"], [60.5, 4.75, "GND"], [61.5, 4.75, "GND"], [62.5, 4.75, "GND"], [63.5, 4.75, "GND"], [65.5, 4.75, "GND"], [21.75, 88.0, "GND"], [15.0, 82.5, "GND"], [27.0, 78.25, "GND"], [25.0, 81.75, "GND"], [9.25, 22.5, "GND"], [3.5, 65.0, "GND"], [2.0, 42.75, "GND"], [62.25, 62.0, "GND"], [17.0, 63.75, "GND"], [42.25, 34.75, "GND"], [84.75, 11.0, "GND"], [81.75, 11.0, "GND"], [61.0, 35.5, "GND"], [90.25, 9.75, "GND"], [24.75, 88.75, "GND"], [16.25, 83.25, "GND"], [6.25, 88.75, "GND"], [21.0, 85.0, "GND"], [86.75, 26.0, "GND"], [20.25, 8.0, "GND"], [21.5, 45.0, "GND"], [89.25, 62.5, "GND"], [83.5, 66.0, "GND"], [3.25, 46.25, "GND"], [77.0, 23.75, "GND"], [36.0, 62.25, "GND"], [42.75, 62.25, "GND"], [37.5, 54.75, "GND"]], "logs": ["USB1_DP: U32.2 出不来", "USB4_DM: U32.8 出不来", "UP_DM: U32.58 出不来", "VIN_SW: C4.2 没布通", "+5V: J37.19 没布通", "FAN_12V_SW: R750.2 没布通", "+3V3: U6.15 出不来", "+3V3: U7.15 出不来", "+3V3: R660.1 出不来", "+3V3_HUB: U32.13 出不来", "+3V3_HUB: U32.10 出不来", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.5 出不来", "+3V3_HUB: U32.52 出不来", "+3V3_HUB: U32.57 出不来", "+3V3_HUB: C749.1 没布通", "INT#: R604.2 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "PRSNT3#: R608.2 出不来", "BLD_REF: R4.1 出不来", "VDD18: U32.25 没布通", "XTAL2: U32.60 没布通", "SDA: R602.2 出不来", "SDA: U6.7 出不来", "SDA: U13.4 没布通", "INA_ALERT: U13.3 没布通", "HUB_RST: U32.43 没布通", "HUB_RST: R716.1 没布通", "VBUS_DET: R710.1 没布通", "VBUS_DET: U32.44 没布通", "NONREM1: U32.40 没布通", "VDD18PLL: U32.62 没布通", "NONREM0: U32.45 没布通", "CFGSEL1: U32.42 没布通", "CFGSEL0: U32.41 没布通", "VDAC4: U6.10 没布通", "VDAC4: U6.9 没布通", "VDAC3: U7.12 没布通", "VDAC3: U7.11 没布通", "XTAL1: U32.61 没布通", "$4N221: J23.B5 没布通", "$2N72: R706.2 没布通", "MUX_RST#: R611.2 没布通", "NTC2: R661.2 没布通", "NTC2: C739.1 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "PRSNT4#: U20.11 没布通", "$6N48: R747.1 没布通", "FAN_IN_TACH_RAW: R751.2 没布通", "EFUSE_EN4: J37.11 没布通", "SDA4: U35.10 没布通", "SCL1: U35.5 没布通", "SDA3: U35.8 没布通", "FAN_PWM: R733.1 没布通", "FAN_EN: R748.1 没布通", "UP_VBUS_DET: R722.1 没布通", "UP_VBUS_DET: R721.2 没布通", "$6N64: R751.1 没布通", "$6N64: R752.2 没布通", "SCL5: U35.14 没布通", "SCL4: U35.11 没布通", "SDA1: U35.4 没布通", "SCL3: U35.9 没布通", "SDA5: U35.13 没布通", "RXD0: U20.36 没布通", "TXD0: U20.37 没布通", "FAN_TACH_OUT: U20.4 没布通", "FAN_TACH_IN: Q9.3 没布通", "EFUSE_EN5: U20.21 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN1: U20.17 没布通", "EFUSE_EN2: J35.11 没布通", "IO0: U20.27 没布通", "FAN_PWM_L: J26.4 没布通", "GND: C6.1 找不到落过孔的地方", "GND: C603.2 找不到落过孔的地方", "GND: C604.2 找不到落过孔的地方", "GND: C607.2 找不到落过孔的地方", "GND: C610.2 找不到落过孔的地方", "GND: C739.2 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C746.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: C753.2 找不到落过孔的地方", "GND: J23.A1B12 找不到落过孔的地方", "GND: J23.A1B12 找不到落过孔的地方", "GND: J23.A1B12 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J34.36 找不到落过孔的地方", "GND: J34.50 找不到落过孔的地方", "GND: J35.4 找不到落过孔的地方", "GND: J35.17 找不到落过孔的地方", "GND: J35.18 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J35.49 找不到落过孔的地方", "GND: J35.50 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.39 找不到落过孔的地方", "GND: J37.56 找不到落过孔的地方", "GND: J38.15 找不到落过孔的地方", "GND: R615.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U13.7 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U20.40 找不到落过孔的地方", "GND: U20.41 找不到落过孔的地方", "GND: U20.41 找不到落过孔的地方", "GND: U20.41 找不到落过孔的地方", "GND: U30.1 找不到落过孔的地方", "GND: U32.19 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "GND: Y1.4 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +3V3: R660.1 U6.15 U7.15 一根铜都没有", "[连通性] +5V: J37.19 一根铜都没有", "[连通性] NTC1: C736.1 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: C749.1 U32.13 U32.10 U32.5 一根铜都没有", "[连通性] FAN_12V_SW: R750.2 一根铜都没有", "[连通性] NTC2: C739.1 RT602.1 一根铜都没有", "[连通性] XTAL1: U32.61 一根铜都没有", "[连通性] XTAL2: U32.60 一根铜都没有", "[连通性] VDD18: C742.1 U32.25 一根铜都没有", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] UP_DM: U32.58 一根铜都没有", "[连通性] $4N221: J23.B5 R718.1 一根铜都没有", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_IN_TACH_RAW: R751.2 一根铜都没有", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] TXD0: J33.2 U20.37 一根铜都没有", "[连通性] RXD0: J33.3 U20.36 一根铜都没有", "[连通性] IO0: J33.5 U20.27 一根铜都没有", "[连通性] EFUSE_EN1: J34.11 U20.17 一根铜都没有", "[连通性] SCL1: J34.37 U35.5 一根铜都没有", "[连通性] SDA1: J34.38 U35.4 一根铜都没有", "[连通性] INT#: R604.2 一根铜都没有", "[连通性] USB1_DP: J34.46 U32.2 一根铜都没有", "[连通性] EFUSE_EN2: J35.11 U20.18 一根铜都没有", "[连通性] VDAC2: 铜分成 2 块", "[连通性] EFUSE_EN3: J36.11 U20.19 一根铜都没有", "[连通性] VDAC3: J36.16 U7.12 U7.11 一根铜都没有", "[连通性] SCL3: J36.37 U35.9 一根铜都没有", "[连通性] SDA3: J36.38 U35.8 一根铜都没有", "[连通性] PRSNT3#: R608.2 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 U20.20 一根铜都没有", "[连通性] VDAC4: J37.16 U6.10 U6.9 一根铜都没有", "[连通性] SCL4: J37.37 U35.11 一根铜都没有", "[连通性] SDA4: J37.38 U35.10 一根铜都没有", "[连通性] USB4_DM: J37.47 U32.8 一根铜都没有", "[连通性] PRSNT4#: U20.11 一根铜都没有", "[连通性] EFUSE_EN5: J38.11 U20.21 一根铜都没有", "[连通性] SCL5: J38.37 U35.14 一根铜都没有", "[连通性] SDA5: J38.38 U35.13 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] $6N64: Q9.1 R751.1 R752.2 一根铜都没有", "[连通性] FAN_TACH_IN: U20.5 一根铜都没有", "[连通性] FAN_TACH_OUT: U20.4 一根铜都没有", "[连通性] BLD_REF: U29.1 一根铜都没有", "[连通性] SDA: R602.2 U6.7 U13.4 一根铜都没有", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] MUX_RST#: U35.3 一根铜都没有", "[连通性] $2N72: R706.2 一根铜都没有", "[连通性] VBUS_DET: R709.2 R710.1 U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: R716.1 U20.12 U32.43 一根铜都没有", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有", "[连通性] NONREM0: R720.1 U32.45 一根铜都没有", "[连通性] UP_VBUS_DET: R721.2 R722.1 U20.23 一根铜都没有", "[连通性] FAN_PWM: R733.1 U20.6 一根铜都没有", "[连通性] FAN_EN: R748.1 U20.7 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.r10-grid183.json b/.claude/r2/_base_routes.r10-grid183.json new file mode 100644 index 0000000..34ae197 --- /dev/null +++ b/.claude/r2/_base_routes.r10-grid183.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 17.125, 44.5, 16.375, 44.5, 0.3, "VIN_SW"], [2, 16.375, 44.5, 12.625, 40.75, 0.3, "VIN_SW"], [2, 12.625, 40.75, 12.625, 40.625, 0.3, "VIN_SW"], [2, 17.389, 44.501, 17.125, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.625, 40.625, 0.3, "VIN_SW"], [1, 18.5, 43.875, 17.375, 45.0, 0.3, "+12V"], [1, 17.375, 45.0, 16.0, 45.0, 0.3, "+12V"], [1, 16.0, 45.0, 15.75, 45.25, 0.3, "+12V"], [1, 15.75, 45.25, 14.0, 45.25, 0.3, "+12V"], [1, 14.0, 45.25, 13.75, 45.5, 0.3, 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"GND"], [58.5, 23.75, "GND"], [60.75, 26.5, "GND"], [61.5, 26.5, "GND"], [63.0, 26.5, "GND"], [65.5, 23.75, "GND"], [31.75, 12.0, "GND"], [35.625, 10.625, "GND"], [44.75, 12.0, "GND"], [46.5, 10.625, "GND"], [47.5, 10.625, "GND"], [48.5, 10.625, "GND"], [50.5, 10.625, "GND"], [51.5, 10.625, "GND"], [53.5, 10.625, "GND"], [54.5, 10.625, "GND"], [55.5, 10.625, "GND"], [56.5, 10.625, "GND"], [57.5, 10.625, "GND"], [58.5, 10.625, "GND"], [60.75, 10.625, "GND"], [61.5, 10.625, "GND"], [62.5, 10.625, "GND"], [63.5, 10.625, "GND"], [64.5, 10.625, "GND"], [35.625, 3.375, "GND"], [38.5, 3.375, "GND"], [44.75, 4.75, "GND"], [46.375, 6.125, "GND"], [49.625, 6.125, "GND"], [50.5, 6.125, "GND"], [51.5, 6.125, "GND"], [52.5, 6.125, "GND"], [53.5, 6.125, "GND"], [54.5, 6.125, "GND"], [55.5, 6.125, "GND"], [56.5, 6.125, "GND"], [57.5, 6.125, "GND"], [58.5, 6.125, "GND"], [59.5, 6.125, "GND"], [60.5, 6.125, "GND"], [61.5, 6.125, "GND"], [62.5, 6.125, "GND"], [63.5, 6.125, "GND"], [66.25, 4.75, "GND"], [22.25, 86.625, "GND"], [15.0, 81.375, "GND"], [26.25, 78.25, "GND"], [25.0, 82.0, "GND"], [8.125, 22.125, "GND"], [2.25, 64.625, "GND"], [4.625, 41.75, "GND"], [62.125, 63.875, "GND"], [17.125, 62.875, "GND"], [84.875, 12.125, "GND"], [81.875, 12.125, "GND"], [64.75, 35.375, "GND"], [92.125, 10.5, "GND"], [21.75, 83.375, "GND"], [16.875, 83.0, "GND"], [1.875, 88.25, "GND"], [13.5, 78.125, "GND"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.625, 45.0, "GND"], [16.0, 42.625, "GND"], [6.25, 70.125, "GND"], [89.5, 61.5, "GND"], [80.0, 69.5, "GND"], [3.25, 45.0, "GND"], [18.5, 70.125, "GND"], [77.0, 24.625, "GND"], [55.0, 41.375, "GND"], [35.5, 63.375, "GND"], [43.125, 61.625, "GND"], [37.875, 57.5, "GND"]], "logs": ["+12V: R4.2 找不到落过孔的地方", "VIN_SW: C4.2 没布通", "VBUS_DET: U32.44 没布通", "CFGSEL1: U32.42 没布通", "NONREM1: U32.40 没布通", "CFGSEL0: U32.41 没布通", "VDD18PLL: U32.62 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "INA_ALERT: U13.3 没布通", "EFUSE_EN5: U20.fan:21 没布通", "PRSNT5#: U20.fan:22 没布通", "PRSNT5#: R610.2 没布通", "FAN_EN: U20.fan:7 没布通", "UP_VBUS_DET: U20.fan:23 没布通", "FAN_TACH_IN: U20.fan:5 没布通", "EFUSE_EN4: U20.fan:20 没布通", "SDA5: U35.fan:13 没布通", "EN: U20.fan:3 没布通", "EN: C603.1 没布通", "PRSNT1#: U20.fan:8 没布通", "PRSNT1#: R606.2 没布通", "SCL4: U35.fan:11 没布通", "EFUSE_EN3: U20.fan:19 没布通", "SDA4: U35.fan:10 没布通", "EFUSE_EN2: U20.fan:18 没布通", "PRSNT3#: R608.2 没布通", "SDA1: U35.fan:4 没布通", "SCL3: U35.fan:9 没布通", "$6N48: R747.1 没布通", "$6N45: R748.2 没布通", "+5V: R706.1 没布通", "+5V: J36.19 没布通", "+5V: J35.32 没布通", "+5V: J36.32 没布通", "+5V: J37.19 没布通", "+5V: J37.32 没布通", "+5V: J38.19 没布通", "+5V: C753.1 没布通", "+5V: C752.1 没布通", "+5V: J38.32 没布通", "FAN_12V_SW: C738.1 没布通", "FAN_12V_SW: R750.2 没布通", "FAN_12V_SW: J26.2 没布通", "FAN_12V_SW: R754.2 出不来", "FAN_12V_SW: D2.1 没布通", "FAN_12V_SW: Q7.3 没布通", "+3V3: R607.1 没布通", "+3V3: R603.1 没布通", "+3V3: U7.fan:15 没布通", "+3V3: C607.1 没布通", "+3V3: R602.1 没布通", "+3V3: R605.1 没布通", "+3V3: R616.1 没布通", "+3V3: R604.1 没布通", "+3V3: R610.1 没布通", "+3V3: U6.fan:15 没布通", "+3V3: C604.1 没布通", "+3V3: R614.1 没布通", "+3V3: R601.1 没布通", "+3V3: J35.10 没布通", "+3V3: J35.40 没布通", "+3V3: J35.9 没布通", "+3V3: U35.fan:24 没布通", "+3V3: C610.1 没布通", "+3V3: J34.40 没布通", "+3V3: J34.10 没布通", "+3V3: J34.9 没布通", "+3V3: R753.1 没布通", "+3V3: R757.1 没布通", "+3V3: C9.2 没布通", "+3V3: R2.2 没布通", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.52 没布通", "+3V3_HUB: U32.57 没布通", "GND: C604.2 找不到落过孔的地方", "GND: C607.2 找不到落过孔的地方", "GND: C609.1 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C750.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J34.48 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.15 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U20.40 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "GND: Y1.4 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +12V: R4.2 一根铜都没有", "[连通性] +3V3: C604.1 C607.1 C610.1 J34.9 一根铜都没有", "[连通性] EN: C603.1 一根铜都没有", "[连通性] +5V: C752.1 J35.32 J36.19 J36.32 一根铜都没有", "[连通性] +3V3_HUB: U32.46 U32.52 U32.57 一根铜都没有", "[连通性] FAN_12V_SW: C738.1 D2.1 J26.2 J27.2 一根铜都没有", "[连通性] NTC2: 铜分成 2 块", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $6N49: 铜分成 2 块", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] SDA1: J34.38 一根铜都没有", "[连通性] INT#: 铜分成 3 块", "[连通性] PRSNT1#: J34.63 R606.2 一根铜都没有", "[连通性] EFUSE_EN2: J35.11 一根铜都没有", "[连通性] EFUSE_EN3: J36.11 一根铜都没有", "[连通性] SCL3: J36.37 一根铜都没有", "[连通性] PRSNT3#: R608.2 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] SDA4: J37.38 一根铜都没有", "[连通性] EFUSE_EN5: J38.11 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: J38.63 R610.2 一根铜都没有", "[连通性] $6N45: R748.2 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] FAN_TACH_IN: 铜分成 2 块", "[连通性] SDA: 铜分成 2 块", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] MUX_RST#: 铜分成 2 块", "[连通性] $2N72: 铜分成 2 块", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有", "[连通性] UP_VBUS_DET: 铜分成 2 块", "[连通性] FAN_EN: R748.1 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.r11-3v3plane183.json b/.claude/r2/_base_routes.r11-3v3plane183.json new file mode 100644 index 0000000..5b4dec6 --- /dev/null +++ b/.claude/r2/_base_routes.r11-3v3plane183.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 17.125, 44.5, 16.375, 44.5, 0.3, "VIN_SW"], [2, 16.375, 44.5, 12.625, 40.75, 0.3, "VIN_SW"], [2, 12.625, 40.75, 12.625, 40.625, 0.3, "VIN_SW"], [2, 17.389, 44.501, 17.125, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.625, 40.625, 0.3, "VIN_SW"], [1, 18.5, 43.875, 17.375, 45.0, 0.3, "+12V"], [1, 17.375, 45.0, 16.0, 45.0, 0.3, "+12V"], [1, 16.0, 45.0, 15.75, 45.25, 0.3, "+12V"], [1, 15.75, 45.25, 14.0, 45.25, 0.3, "+12V"], [1, 14.0, 45.25, 13.75, 45.5, 0.3, "+12V"], [1, 13.75, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.625, 46.375, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.875, 0.3, "+12V"], [2, 12.499, 46.566, 12.625, 46.375, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, "UP_DM"], [2, 50.249, 43.03, 50.249, 47.9995, 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"EFUSE_EN2"], [58.75, 77.5, "EFUSE_EN2"], [62.5, 77.375, "EFUSE_EN2"], [67.25, 76.75, "EFUSE_EN2"], [84.25, 94.125, "IO0"], [71.5, 77.875, "IO0"], [65.375, 43.875, "PRSNT3#"], [74.375, 55.5, "PRSNT3#"], [77.5, 53.25, "PRSNT3#"], [78.125, 58.0, "PRSNT3#"], [78.375, 94.125, "TXD0"], [80.125, 92.375, "TXD0"], [84.375, 82.125, "TXD0"], [85.75, 78.875, "TXD0"], [64.625, 64.375, "PRSNT2#"], [65.0, 63.875, "PRSNT2#"], [69.0, 52.0, "PRSNT2#"], [66.25, 49.5, "PRSNT2#"], [63.875, 47.5, "PRSNT2#"], [62.625, 43.5, "PRSNT2#"], [64.25, 43.375, "PRSNT2#"], [76.375, 52.375, "PRSNT2#"], [78.375, 56.125, "PRSNT2#"], [79.375, 58.0, "PRSNT2#"], [80.875, 94.125, "RXD0"], [79.5, 90.375, "RXD0"], [80.25, 87.875, "RXD0"], [85.875, 80.125, "RXD0"], [31.5, 91.125, "$6N49"], [31.5, 89.0, "$6N49"], [28.25, 81.875, "$6N64"], [30.0, 82.625, "$6N64"], [32.0, 87.875, "$6N64"], [32.625, 90.375, "$6N64"], [81.5, 28.125, "+3V3_HUB"], [75.5, 27.25, "+3V3_HUB"], [73.875, 44.75, "+3V3_HUB"], [63.875, 41.875, "+3V3_HUB"], [58.875, 39.875, "+3V3_HUB"], [57.0, 39.125, "+3V3_HUB"], [57.625, 43.375, "+3V3_HUB"], [68.5, 25.25, "+3V3_HUB"], [62.875, 27.0, "+3V3_HUB"], [49.625, 29.0, "+3V3_HUB"], [46.25, 30.25, "+3V3_HUB"], [44.125, 33.25, "+3V3_HUB"], [46.875, 43.375, "+3V3_HUB"], [42.75, 37.75, "+3V3_HUB"], [41.0, 36.75, "+3V3_HUB"], [38.125, 39.75, "+3V3_HUB"], [37.75, 40.875, "+3V3_HUB"], [37.75, 42.125, "+3V3_HUB"], [39.5, 42.125, "+3V3_HUB"], [13.125, 38.0, "GND"], [14.125, 64.0, "+3V3"], [15.25, 71.75, "+3V3"], [18.5, 41.25, "GND"], [16.5, 41.25, "+3V3"], [88.875, 55.25, "+3V3"], [91.125, 56.875, "+3V3"], [90.5, 55.5, "GND"], [86.875, 53.625, "GND"], [59.25, 54.125, "GND"], [33.0, 57.25, "GND"], [33.0, 55.25, "+3V3"], [91.25, 84.0, "GND"], [92.5, 81.75, "GND"], [41.25, 38.5, "GND"], [40.75, 39.875, "GND"], [74.125, 30.25, "GND"], [33.125, 91.75, "GND"], [35.625, 91.875, "GND"], [40.5, 91.875, "+3V3"], [41.5, 91.875, "+3V3"], [44.75, 93.5, "GND"], [46.5, 91.875, "GND"], [47.5, 91.875, "GND"], [48.5, 94.625, "GND"], [50.5, 94.625, "GND"], [51.5, 94.625, "GND"], [53.5, 91.875, "GND"], [54.5, 91.875, "GND"], [55.5, 91.875, "GND"], [56.5, 91.875, "GND"], [57.5, 91.875, "GND"], [58.5, 91.875, "GND"], [59.5, 91.875, "GND"], [60.5, 91.875, "GND"], [61.5, 91.875, "GND"], [62.5, 91.875, "GND"], [63.5, 91.875, "GND"], [64.5, 91.875, "GND"], [35.625, 87.5, "GND"], [38.5, 87.375, "GND"], [39.5, 87.375, "+3V3"], [45.5, 87.375, "GND"], [46.375, 87.375, "GND"], [50.125, 87.375, "GND"], [51.5, 87.375, "GND"], [52.5, 87.375, "GND"], [53.5, 87.375, "GND"], [54.125, 87.375, "GND"], [55.5, 84.625, "GND"], [56.875, 87.375, "GND"], [57.5, 87.375, "GND"], [58.5, 87.375, "GND"], [59.5, 87.375, "GND"], [60.5, 87.375, "GND"], [61.5, 87.375, "GND"], [62.5, 87.375, "GND"], [63.5, 87.375, "GND"], [66.25, 86.0, "GND"], [31.75, 72.875, "GND"], [35.625, 74.25, "GND"], [40.5, 71.5, "+3V3"], [41.5, 71.5, "+3V3"], [45.5, 71.5, "GND"], [46.5, 71.5, "GND"], [53.5, 71.5, "GND"], [58.875, 71.5, "GND"], [59.5, 71.5, "GND"], [60.5, 71.5, "GND"], [61.5, 71.5, "GND"], [62.5, 71.5, "GND"], [63.5, 71.5, "GND"], [64.125, 71.5, "GND"], [50.25, 64.375, "GND"], [51.5, 64.375, "GND"], [52.5, 64.375, "GND"], [53.5, 64.375, "GND"], [54.5, 64.375, "GND"], [56.625, 67.125, "GND"], [57.5, 67.125, "GND"], [58.5, 67.125, "GND"], [59.5, 67.125, "GND"], [60.5, 64.375, "GND"], [61.5, 64.375, "GND"], [62.5, 64.375, "GND"], [63.5, 67.125, "GND"], [66.25, 65.75, "GND"], [35.625, 51.25, "GND"], [40.375, 51.125, "+3V3"], [47.5, 54.0, "GND"], [48.5, 54.0, "GND"], [60.0, 54.0, "GND"], [31.75, 32.25, "GND"], [40.5, 30.875, "+3V3"], [41.5, 30.875, "+3V3"], [35.625, 23.75, "GND"], [38.5, 23.75, "GND"], [39.5, 23.75, "+3V3"], [44.75, 25.125, "GND"], [46.5, 23.75, "GND"], [49.5, 23.75, "GND"], [50.125, 23.75, "GND"], [52.875, 23.75, "GND"], [53.5, 23.75, "GND"], [54.5, 23.75, "GND"], [55.5, 23.75, "GND"], [56.5, 23.75, "GND"], [57.5, 23.75, "GND"], [58.5, 23.75, "GND"], [62.625, 23.75, "GND"], [63.5, 23.75, "GND"], [65.5, 23.75, "GND"], [31.75, 12.0, "GND"], [35.625, 10.625, "GND"], [40.5, 10.625, "+3V3"], [41.5, 10.625, "+3V3"], [44.75, 12.0, "GND"], [46.5, 10.625, "GND"], [47.5, 10.625, "GND"], [48.5, 10.625, "GND"], [50.5, 10.625, "GND"], [51.5, 10.625, "GND"], [53.5, 10.625, "GND"], [54.5, 10.625, "GND"], [55.5, 10.625, "GND"], [56.5, 10.625, "GND"], [57.5, 10.625, "GND"], [58.5, 10.625, "GND"], [60.75, 10.625, "GND"], [61.5, 10.625, "GND"], [62.5, 10.625, "GND"], [63.5, 10.625, "GND"], [35.625, 6.125, "GND"], [38.5, 6.125, "GND"], [39.5, 6.125, "+3V3"], [44.75, 4.5, "GND"], [46.375, 6.125, "GND"], [49.625, 6.125, "GND"], [50.5, 6.125, "GND"], [51.5, 6.125, "GND"], [52.5, 6.125, "GND"], [53.5, 6.125, "GND"], [54.5, 6.125, "GND"], [55.5, 6.125, "GND"], [56.5, 6.125, "GND"], [57.5, 6.125, "GND"], [58.5, 6.125, "GND"], [59.5, 6.125, "GND"], [60.5, 6.125, "GND"], [61.5, 6.125, "GND"], [62.5, 6.125, "GND"], [63.5, 6.125, "GND"], [66.25, 4.75, "GND"], [11.5, 68.5, "+3V3"], [22.25, 88.0, "GND"], [15.0, 82.75, "GND"], [26.25, 78.25, "GND"], [25.0, 82.0, "GND"], [8.125, 22.125, "GND"], [5.375, 71.25, "+3V3"], [2.25, 64.625, "GND"], [4.625, 41.75, "GND"], [75.125, 81.875, "+3V3"], [78.875, 81.875, "+3V3"], [80.625, 57.375, "+3V3"], [74.25, 57.375, "+3V3"], [70.875, 81.25, "+3V3"], [80.625, 84.125, "+3V3"], [88.625, 80.5, "+3V3"], [86.875, 84.125, "+3V3"], [17.875, 63.5, "GND"], [84.5, 10.875, "GND"], [64.75, 35.375, "GND"], [92.125, 10.5, "GND"], [21.75, 83.375, "GND"], [18.125, 83.0, "GND"], [3.125, 88.0, "GND"], [23.375, 76.625, "+3V3"], [13.75, 76.875, "GND"], [21.875, 79.625, "+3V3"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.625, 45.0, "GND"], [16.0, 42.625, "GND"], [17.375, 42.0, "+3V3"], [6.25, 70.125, "GND"], [89.5, 79.0, "GND"], [80.0, 69.5, "GND"], [3.25, 45.0, "GND"], [18.5, 70.125, "GND"], [77.0, 24.625, "GND"], [55.0, 41.375, "GND"], [35.5, 63.375, "GND"], [42.0, 43.875, "GND"]], "logs": ["+12V: R4.2 找不到落过孔的地方", "VIN_SW: C4.2 没布通", "VBUS_DET: U32.44 没布通", "CFGSEL1: U32.42 没布通", "NONREM1: U32.40 没布通", "CFGSEL0: U32.41 没布通", "VDD18PLL: U32.62 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "SDA: U13.4 没布通", "$3N197: U7.fan:5 没布通", "$3N173: U6.fan:16 没布通", "FAN_TACH_IN: U20.fan:5 没布通", "MUX_RST#: U35.fan:3 没布通", "EFUSE_EN4: U20.fan:20 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "SCL5: U35.fan:14 没布通", "SDA5: U35.fan:13 没布通", "EN: U20.fan:3 没布通", "EN: C603.1 没布通", "PRSNT1#: U20.fan:8 没布通", "PRSNT1#: R606.2 没布通", "SCL4: U35.fan:11 没布通", "EFUSE_EN3: U20.fan:19 没布通", "SDA4: U35.fan:10 没布通", "SDA1: U35.fan:4 没布通", "SCL3: U35.fan:9 没布通", "$6N48: R747.1 没布通", "$6N45: R748.2 没布通", "$2N72: R706.2 没布通", "$6N55: R733.2 没布通", "FAN_PWM_L: J26.4 没布通", "+5V: R706.1 没布通", "+5V: J35.19 没布通", "+5V: J36.19 没布通", "+5V: J34.19 没布通", "+5V: J35.32 没布通", "+5V: J36.32 没布通", "+5V: J37.19 没布通", "+5V: J34.32 没布通", "+5V: J37.32 没布通", "+5V: J38.19 没布通", "+5V: C753.1 没布通", "+5V: C752.1 没布通", "+5V: J38.32 没布通", "FAN_12V_SW: J27.2 没布通", "FAN_12V_SW: R750.2 没布通", "FAN_12V_SW: R754.2 没布通", "FAN_12V_SW: C738.1 没布通", "+3V3_HUB: U32.fan:vd 没布通", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.52 没布通", "+3V3_HUB: U32.57 没布通", "+3V3_HUB: C750.1 没布通", "GND: C604.2 找不到落过孔的地方", "+3V3: C604.1 找不到落过孔的地方", "GND: C607.2 找不到落过孔的地方", "+3V3: C607.1 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.17 找不到落过孔的地方", "GND: J35.18 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "+3V3: J35.40 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "+3V3: J36.10 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "+3V3: J36.40 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.12 找不到落过孔的地方", "GND: J37.13 找不到落过孔的地方", "GND: J37.14 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "+3V3: R601.1 找不到落过孔的地方", "+3V3: R602.1 找不到落过孔的地方", "+3V3: R607.1 找不到落过孔的地方", "+3V3: R609.1 找不到落过孔的地方", "+3V3: R614.1 找不到落过孔的地方", "+3V3: R616.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R718.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U20.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +12V: R4.2 一根铜都没有", "[连通性] +3V3: C604.1 C607.1 J35.40 J36.10 一根铜都没有", "[连通性] EN: C603.1 一根铜都没有", "[连通性] $3N173: 铜分成 2 块", "[连通性] +5V: C752.1 J34.19 J34.32 J35.19 一根铜都没有", "[连通性] NTC1: C736.1 R660.2 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: C750.1 U32.46 U32.52 U32.57 一根铜都没有", "[连通性] FAN_12V_SW: C738.1 J27.2 R750.2 R754.2 一根铜都没有", "[连通性] NTC2: 铜分成 2 块", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $6N49: 铜分成 2 块", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] SDA1: J34.38 一根铜都没有", "[连通性] INT#: 铜分成 2 块", "[连通性] PRSNT1#: J34.63 R606.2 一根铜都没有", "[连通性] EFUSE_EN3: J36.11 一根铜都没有", "[连通性] SCL3: J36.37 一根铜都没有", "[连通性] PRSNT3#: 铜分成 2 块", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] SDA4: J37.38 一根铜都没有", "[连通性] SCL5: J38.37 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: 铜分成 2 块", "[连通性] $6N55: Q6.1 一根铜都没有", "[连通性] $6N45: R748.2 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] FAN_TACH_IN: 铜分成 2 块", "[连通性] SDA: U13.4 一根铜都没有", "[连通性] INA_ALERT: 铜分成 2 块", "[连通性] MUX_RST#: 铜分成 2 块", "[连通性] $3N197: R617.2 一根铜都没有", "[连通性] $2N72: R706.2 一根铜都没有", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.r6-pf192.json b/.claude/r2/_base_routes.r6-pf192.json new file mode 100644 index 0000000..f47d34b --- /dev/null +++ b/.claude/r2/_base_routes.r6-pf192.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 16.75, 44.5, 16.5, 44.5, 0.3, "VIN_SW"], [2, 16.5, 44.5, 12.75, 40.75, 0.3, "VIN_SW"], [2, 17.389, 44.501, 16.75, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.75, 40.75, 0.3, "VIN_SW"], [1, 18.5, 43.75, 17.75, 43.75, 0.3, "+12V"], [1, 17.75, 43.75, 16.0, 45.5, 0.3, "+12V"], [1, 16.0, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.75, 46.25, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.75, 0.3, "+12V"], [2, 12.499, 46.566, 12.75, 46.25, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, 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[62.5, 87.5, "GND"], [63.5, 87.5, "GND"], [66.25, 86.0, "GND"], [31.75, 71.75, "GND"], [35.75, 74.5, "GND"], [45.75, 74.25, "GND"], [46.5, 74.25, "GND"], [47.5, 74.25, "GND"], [51.0, 74.25, "GND"], [49.75, 67.25, "GND"], [50.75, 64.25, "GND"], [51.5, 64.25, "GND"], [52.5, 64.25, "GND"], [53.5, 64.25, "GND"], [55.75, 64.25, "GND"], [56.5, 67.25, "GND"], [57.5, 67.25, "GND"], [58.25, 67.25, "GND"], [62.0, 64.25, "GND"], [62.75, 64.25, "GND"], [57.25, 54.0, "GND"], [44.75, 32.25, "GND"], [46.5, 30.75, "GND"], [35.75, 23.5, "GND"], [44.75, 25.0, "GND"], [46.25, 23.75, "GND"], [49.5, 23.75, "GND"], [50.5, 23.75, "GND"], [51.5, 23.75, "GND"], [52.5, 23.75, "GND"], [53.5, 23.75, "GND"], [54.5, 26.5, "GND"], [56.25, 23.75, "GND"], [57.5, 23.75, "GND"], [58.5, 23.75, "GND"], [61.0, 23.75, "GND"], [62.5, 23.75, "GND"], [63.5, 23.75, "GND"], [65.5, 23.75, "GND"], [31.75, 12.0, "GND"], [44.75, 12.0, "GND"], [46.5, 10.5, "GND"], [47.5, 10.5, "GND"], [48.5, 10.5, "GND"], [50.5, 10.5, "GND"], [51.5, 10.5, "GND"], [53.5, 10.5, "GND"], [54.5, 10.5, "GND"], [55.5, 10.5, "GND"], [56.5, 10.5, "GND"], [57.5, 10.5, "GND"], [58.5, 10.5, "GND"], [61.0, 10.5, "GND"], [62.5, 10.5, "GND"], [63.5, 10.5, "GND"], [64.5, 10.5, "GND"], [35.75, 3.25, "GND"], [38.5, 3.25, "GND"], [44.75, 4.75, "GND"], [46.5, 3.25, "GND"], [49.5, 3.25, "GND"], [50.5, 6.25, "GND"], [51.5, 6.25, "GND"], [52.5, 6.25, "GND"], [53.5, 6.25, "GND"], [54.5, 6.25, "GND"], [55.5, 6.25, "GND"], [56.5, 6.25, "GND"], [57.5, 6.25, "GND"], [58.5, 6.25, "GND"], [59.5, 6.25, "GND"], [60.5, 6.25, "GND"], [61.5, 6.25, "GND"], [62.5, 6.25, "GND"], [63.5, 6.25, "GND"], [66.25, 4.75, "GND"], [21.75, 87.25, "GND"], [15.0, 83.25, "GND"], [26.25, 78.25, "GND"], [25.25, 81.0, "GND"], [8.5, 22.5, "GND"], [4.25, 64.75, "GND"], [2.0, 42.0, "GND"], [55.75, 62.75, "GND"], [16.75, 63.25, "GND"], [84.75, 11.75, "GND"], [57.25, 36.75, "GND"], [90.5, 10.5, "GND"], [25.25, 89.0, "GND"], [15.75, 83.25, "GND"], [5.5, 88.75, "GND"], [20.25, 85.0, "GND"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.5, 45.0, "GND"], [89.25, 61.5, "GND"], [80.0, 67.0, "GND"], [3.25, 45.5, "GND"], [77.0, 22.75, "GND"], [55.0, 40.75, "GND"]], "logs": ["VIN_SW: C4.2 没布通", "FAN_12V_SW: R750.2 没布通", "+3V3_HUB: R712.2 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "BLD_A: R6.1 没布通", "$2N72: R706.2 没布通", "$2N72: R707.1 没布通", "FAN_12V_SW: R750.2 没布通", "+3V3: J36.9 没布通", "+3V3: J36.10 没布通", "+3V3: R608.1 没布通", "+3V3: R611.1 没布通", "+3V3: R602.1 出不来", "+3V3_HUB: R712.2 没布通", "SCL: U6.6 出不来", "RBIAS: U32.63 没布通", "CFGSEL1: U32.42 没布通", "HUB_RST: U32.43 没布通", "HUB_RST: R716.1 没布通", "INA_ALERT: U13.3 没布通", "XTAL1: U32.61 没布通", "NONREM0: U32.45 没布通", "VBUS_DET: U32.44 没布通", "VDD18PLL: U32.62 没布通", "$6N48: R747.1 没布通", "PRSNT4#: R609.2 出不来", "PRSNT4#: U20.fan:11 没布通", "PRSNT5#: U20.fan:22 没布通", "PRSNT5#: R610.2 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "INT#: J36.43 没布通", "INT#: J35.43 没布通", "INT#: U20.fan:32 没布通", "INT#: J34.43 没布通", "INT#: R604.2 没布通", "SDA: U35.fan:23 没布通", "SDA: R602.2 没布通", "SDA: U13.4 没布通", "FAN_EN: U20.fan:7 没布通", "NTC2: U20.fan:38 没布通", "NTC2: R661.2 没布通", "NTC2: C739.1 没布通", "FAN_IN_TACH_RAW: R750.1 没布通", "FAN_IN_TACH_RAW: R751.2 没布通", "VDAC5: U7.fan:10 没布通", "VDAC4: U6.fan:10 没布通", "EN: U20.fan:3 没布通", "EN: C603.1 没布通", "EFUSE_EN5: U20.fan:21 没布通", "EFUSE_EN4: U20.fan:20 没布通", "SDA5: U35.fan:13 没布通", "VDAC3: U7.fan:11 没布通", "SCL4: U35.fan:11 没布通", "SCL3: J36.37 没布通", "GND: C609.1 找不到落过孔的地方", "GND: C610.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C743.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C746.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J34.48 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.20 找不到落过孔的地方", "GND: J35.21 找不到落过孔的地方", "GND: J35.22 找不到落过孔的地方", "GND: J35.23 找不到落过孔的地方", "GND: J35.24 找不到落过孔的地方", "GND: J35.25 找不到落过孔的地方", "GND: J35.26 找不到落过孔的地方", "GND: J35.27 找不到落过孔的地方", "GND: J35.28 找不到落过孔的地方", "GND: J35.29 找不到落过孔的地方", "GND: J35.30 找不到落过孔的地方", "GND: J35.31 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J35.64 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.4 找不到落过孔的地方", "GND: J36.12 找不到落过孔的地方", "GND: J36.13 找不到落过孔的地方", "GND: J36.14 找不到落过孔的地方", "GND: J36.15 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.1 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: J37.39 找不到落过孔的地方", "GND: J38.4 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R718.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U13.7 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U20.40 找不到落过孔的地方", "GND: U30.1 找不到落过孔的地方", "GND: U35.2 找不到落过孔的地方", "GND: U35.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +3V3: J36.9 J36.10 R602.1 R608.1 一根铜都没有", "[连通性] EN: C603.1 一根铜都没有", "[连通性] $3N189: 铜分成 2 块", "[连通性] +5V: 铜分成 5 块", "[连通性] NTC1: C736.1 R660.2 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: 铜分成 12 块", "[连通性] FAN_12V_SW: R750.2 一根铜都没有", "[连通性] NTC2: C739.1 R661.2 RT602.1 一根铜都没有", "[连通性] XTAL1: U32.61 一根铜都没有", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_IN_TACH_RAW: J26.3 R750.1 R751.2 一根铜都没有", "[连通性] INT#: J34.43 J35.43 J36.43 R604.2 一根铜都没有", "[连通性] VDAC3: J36.16 一根铜都没有", "[连通性] SCL3: J36.37 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] VDAC4: J37.16 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] PRSNT4#: J37.63 R609.2 一根铜都没有", "[连通性] EFUSE_EN5: J38.11 一根铜都没有", "[连通性] VDAC5: J38.16 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: J38.63 R610.2 一根铜都没有", "[连通性] BLD_A: R6.1 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] SDA: R602.2 U13.4 一根铜都没有", "[连通性] SCL: U6.6 一根铜都没有", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] MUX_RST#: 铜分成 2 块", "[连通性] $2N72: R706.2 R707.1 U30.4 一根铜都没有", "[连通性] RBIAS: R708.1 U32.63 一根铜都没有", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: R716.1 U32.43 一根铜都没有", "[连通性] NONREM0: R720.1 U32.45 一根铜都没有", "[连通性] FAN_EN: R748.1 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.r7-fanzone220.json b/.claude/r2/_base_routes.r7-fanzone220.json new file mode 100644 index 0000000..2e1d8da --- /dev/null +++ b/.claude/r2/_base_routes.r7-fanzone220.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 16.75, 44.5, 16.5, 44.5, 0.3, "VIN_SW"], [2, 16.5, 44.5, 12.75, 40.75, 0.3, "VIN_SW"], [2, 17.389, 44.501, 16.75, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.75, 40.75, 0.3, "VIN_SW"], [1, 18.5, 43.75, 17.75, 43.75, 0.3, "+12V"], [1, 17.75, 43.75, 16.0, 45.5, 0.3, "+12V"], [1, 16.0, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.75, 46.25, 0.3, "+12V"], [2, 17.389, 44, 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"GND"], [25.0, 81.0, "GND"], [8.5, 22.5, "GND"], [4.25, 64.75, "GND"], [2.0, 42.0, "GND"], [16.75, 63.25, "GND"], [57.25, 36.75, "GND"], [24.5, 88.25, "GND"], [15.75, 83.25, "GND"], [5.5, 88.75, "GND"], [20.25, 85.0, "GND"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.5, 45.0, "GND"], [89.25, 61.5, "GND"], [80.0, 69.0, "GND"], [3.25, 45.5, "GND"], [77.0, 22.75, "GND"], [55.0, 40.75, "GND"]], "logs": ["VIN_SW: C4.2 没布通", "+5V: J36.19 没布通", "+5V: J36.32 没布通", "FAN_12V_SW: R750.2 没布通", "+3V3_HUB: R712.2 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "BLD_A: R6.1 没布通", "SCL: U6.6 出不来", "$2N72: R706.2 没布通", "$2N72: R707.1 没布通", "+5V: J36.19 没布通", "+5V: J36.32 没布通", "FAN_12V_SW: R750.2 没布通", "+3V3: U6.fan:15 没布通", "+3V3: U7.fan:15 没布通", "+3V3: C607.fan:1 没布通", "+3V3: R660.fan:1 没布通", "+3V3_HUB: R712.2 没布通", "SCL: U6.6 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: R709.1 没布通", "RBIAS: U32.63 出不来", "XTAL2: U32.60 没布通", "XTAL1: U32.61 没布通", "CFGSEL1: U32.42 没布通", "HUB_RST: U32.43 没布通", "HUB_RST: R716.1 没布通", "SDA3: U35.8 没布通", "NONREM0: U32.45 没布通", "VDD18PLL: U32.62 没布通", "VBUS_DET: U32.44 没布通", "$4N221: J23.B5 没布通", "SDA: U7.fan:8 没布通", "SDA: U35.fan:23 没布通", "SDA: U20.fan:34 没布通", "SDA: R602.fan:2 没布通", "SDA: U13.4 没布通", "INA_ALERT: U13.3 没布通", "FAN_EN: U20.fan:7 没布通", "PRSNT5#: U20.fan:22 没布通", "PRSNT5#: R610.fan:2 没布通", "UP_VBUS_DET: U20.fan:23 没布通", "PRSNT1#: U20.fan:8 没布通", "PRSNT1#: R606.fan:2 没布通", "EN: U20.fan:3 没布通", "EN: C603.fan:1 没布通", "TXD0: U20.fan:37 没布通", "RXD0: U20.fan:36 没布通", "EFUSE_EN4: U20.fan:20 没布通", "VDAC3: U7.fan:11 没布通", "FAN_IN_TACH_RAW: R750.1 没布通", "FAN_IN_TACH_RAW: R751.2 没布通", "VDAC4: U6.fan:10 没布通", "NTC2: U20.fan:38 没布通", "NTC2: R661.fan:2 没布通", "NTC2: C739.fan:1 没布通", "EFUSE_EN1: U20.fan:17 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.fan:2 没布通", "NTC1: C736.fan:1 没布通", "VDAC2: U6.fan:11 没布通", "SCL2: U35.fan:7 没布通", "SDA5: U35.fan:13 没布通", "SCL4: U35.fan:11 没布通", "SDA4: U35.fan:10 没布通", "SCL3: U35.fan:9 没布通", "PRSNT2#: R607.fan:2 没布通", "GND: C607.2 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C741.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C743.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C746.2 找不到落过孔的地方", "GND: C747.2 找不到落过孔的地方", "GND: C748.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C750.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J34.39 找不到落过孔的地方", "GND: J34.48 找不到落过孔的地方", "GND: J35.12 找不到落过孔的地方", "GND: J35.13 找不到落过孔的地方", "GND: J35.14 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.17 找不到落过孔的地方", "GND: J35.18 找不到落过孔的地方", "GND: J35.20 找不到落过孔的地方", "GND: J35.21 找不到落过孔的地方", "GND: J35.22 找不到落过孔的地方", "GND: J35.23 找不到落过孔的地方", "GND: J35.24 找不到落过孔的地方", "GND: J35.25 找不到落过孔的地方", "GND: J35.26 找不到落过孔的地方", "GND: J35.27 找不到落过孔的地方", "GND: J35.28 找不到落过孔的地方", "GND: J35.29 找不到落过孔的地方", "GND: J35.30 找不到落过孔的地方", "GND: J35.31 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J35.48 找不到落过孔的地方", "GND: J35.64 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.4 找不到落过孔的地方", "GND: J36.12 找不到落过孔的地方", "GND: J36.13 找不到落过孔的地方", "GND: J36.14 找不到落过孔的地方", "GND: J36.15 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: J37.64 找不到落过孔的地方", "GND: J38.4 找不到落过孔的地方", "GND: R615.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R717.2 找不到落过孔的地方", "GND: R718.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: R722.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U13.7 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U20.40 找不到落过孔的地方", "GND: U30.1 找不到落过孔的地方", "GND: U35.2 找不到落过孔的地方", "GND: U35.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "GND: Y1.4 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +3V3: 铜分成 12 块", "[连通性] EN: 铜分成 3 块", "[连通性] +5V: J36.19 J36.32 一根铜都没有", "[连通性] NTC1: 铜分成 4 块", "[连通性] +3V3_HUB: 铜分成 12 块", "[连通性] FAN_12V_SW: R750.2 一根铜都没有", "[连通性] NTC2: RT602.1 一根铜都没有", "[连通性] XTAL1: U32.61 一根铜都没有", "[连通性] XTAL2: U32.60 一根铜都没有", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $4N221: J23.B5 R718.1 一根铜都没有", "[连通性] VBUS_UP: R709.1 一根铜都没有", "[连通性] FAN_IN_TACH_RAW: J26.3 R750.1 R751.2 一根铜都没有", "[连通性] TXD0: J33.2 一根铜都没有", "[连通性] RXD0: J33.3 一根铜都没有", "[连通性] EFUSE_EN1: J34.11 一根铜都没有", "[连通性] INT#: 铜分成 2 块", "[连通性] PRSNT1#: J34.63 一根铜都没有", "[连通性] VDAC2: J35.16 一根铜都没有", "[连通性] SCL2: J35.37 一根铜都没有", "[连通性] PRSNT2#: J35.63 一根铜都没有", "[连通性] VDAC3: J36.16 一根铜都没有", "[连通性] SCL3: J36.37 一根铜都没有", "[连通性] SDA3: J36.38 U35.8 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] VDAC4: J37.16 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] SDA4: J37.38 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: J38.63 一根铜都没有", "[连通性] BLD_A: R6.1 一根铜都没有", "[连通性] SDA: U13.4 一根铜都没有", "[连通性] SCL: U6.6 一根铜都没有", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] $2N72: R706.2 R707.1 U30.4 一根铜都没有", "[连通性] RBIAS: R708.1 U32.63 一根铜都没有", "[连通性] VBUS_DET: U32.44 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: R716.1 U32.43 一根铜都没有", "[连通性] NONREM0: R720.1 U32.45 一根铜都没有", "[连通性] UP_VBUS_DET: 铜分成 2 块", "[连通性] FAN_EN: R748.1 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.r9-pf199.json b/.claude/r2/_base_routes.r9-pf199.json new file mode 100644 index 0000000..b35ed65 --- /dev/null +++ b/.claude/r2/_base_routes.r9-pf199.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 16.75, 44.5, 16.5, 44.5, 0.3, "VIN_SW"], [2, 16.5, 44.5, 12.75, 40.75, 0.3, "VIN_SW"], [2, 17.389, 44.501, 16.75, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.75, 40.75, 0.3, "VIN_SW"], [1, 18.5, 43.75, 17.75, 43.75, 0.3, "+12V"], [1, 17.75, 43.75, 16.0, 45.5, 0.3, "+12V"], [1, 16.0, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.75, 46.25, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.75, 0.3, "+12V"], [2, 12.499, 46.566, 12.75, 46.25, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, "UP_DM"], [2, 50.249, 43.03, 50.249, 47.9995, 0.28, "USB3_DM"], [2, 50.249, 47.9995, 48.499, 47.9995, 0.28, "USB3_DM"], [2, 48.499, 47.9995, 48.499, 47.5995, 0.28, "USB3_DM"], [2, 50.749, 43.03, 50.749, 48.799499999999995, 0.28, "USB3_DP"], [2, 50.749, 48.799499999999995, 47.501, 48.799499999999995, 0.28, "USB3_DP"], [2, 47.501, 48.799499999999995, 47.501, 48.299499999999995, 0.28, "USB3_DP"], [1, 48.499, 47.5995, 48.499, 45.4, 0.28, "USB3_DM"], [1, 47.501, 48.299499999999995, 47.501, 45.4, 0.28, "USB3_DP"], [2, 53.749, 43.03, 53.749, 43.906, 0.2, "+3V3_HUB"], [2, 53.749, 43.906, 56.877, 43.906, 0.2, "+3V3_HUB"], [2, 56.877, 43.906, 56.877, 38.829, 0.2, "+3V3_HUB"], [2, 56.877, 38.829, 55.951, 38.829, 0.2, "+3V3_HUB"], [2, 49.751, 43.03, 49.751, 46.299, 0.2, "+3V3_HUB"], [2, 49.751, 46.299, 49.401, 46.899, 0.2, "+3V3_HUB"], [2, 52.25, 43.03, 52.25, 46.299, 0.2, "+3V3_HUB"], [2, 52.25, 46.299, 53.0, 46.899, 0.2, "+3V3_HUB"], [1, 49.401, 46.899, 65.999, 46.899, 0.2, "+3V3_HUB"], [2, 47.749, 43.03, 47.749, 43.755, 0.28, "USB1_DM"], [2, 47.749, 43.755, 44.249, 47.255, 0.28, "USB1_DM"], [2, 44.249, 47.255, 44.249, 89.14, 0.28, "USB1_DM"], [2, 44.249, 89.14, 48.499, 89.14, 0.28, "USB1_DM"], [2, 48.499, 89.14, 48.499, 88.04, 0.28, "USB1_DM"], [1, 48.499, 88.04, 48.499, 86.04, 0.28, "USB1_DM"], [2, 48.25, 43.03, 48.25, 44.005, 0.28, "USB1_DP"], [2, 48.25, 44.005, 44.75, 47.505, 0.28, "USB1_DP"], [2, 44.75, 47.505, 44.75, 88.64, 0.28, "USB1_DP"], [2, 44.75, 88.64, 47.501, 88.64, 0.28, "USB1_DP"], [2, 47.501, 88.64, 47.501, 88.04, 0.28, "USB1_DP"], [1, 47.501, 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23.75, "GND"], [62.5, 26.5, "GND"], [65.5, 23.75, "GND"], [31.75, 12.0, "GND"], [35.75, 10.5, "GND"], [44.75, 12.0, "GND"], [46.5, 10.5, "GND"], [47.5, 10.5, "GND"], [48.5, 10.5, "GND"], [50.5, 10.5, "GND"], [51.5, 10.5, "GND"], [53.5, 10.5, "GND"], [54.5, 10.5, "GND"], [55.5, 10.5, "GND"], [56.5, 10.5, "GND"], [57.5, 10.5, "GND"], [58.5, 10.5, "GND"], [61.0, 10.5, "GND"], [62.5, 10.5, "GND"], [63.5, 10.5, "GND"], [64.5, 10.5, "GND"], [35.75, 6.25, "GND"], [38.5, 3.25, "GND"], [44.75, 4.75, "GND"], [46.5, 3.25, "GND"], [49.5, 3.25, "GND"], [50.5, 6.25, "GND"], [51.5, 6.25, "GND"], [52.5, 6.25, "GND"], [53.5, 6.25, "GND"], [54.5, 6.25, "GND"], [55.5, 6.25, "GND"], [56.5, 6.25, "GND"], [57.5, 6.25, "GND"], [58.5, 6.25, "GND"], [59.5, 6.25, "GND"], [60.5, 6.25, "GND"], [61.5, 6.25, "GND"], [62.5, 6.25, "GND"], [63.5, 6.25, "GND"], [66.25, 4.75, "GND"], [22.25, 86.5, "GND"], [15.25, 82.75, "GND"], [26.25, 78.25, "GND"], [25.0, 83.5, "GND"], [8.0, 22.25, "GND"], [2.0, 64.5, "GND"], [3.25, 41.5, "GND"], [17.25, 62.75, "GND"], [84.75, 12.25, "GND"], [92.25, 10.75, "GND"], [21.5, 83.5, "GND"], [16.75, 82.75, "GND"], [1.75, 88.0, "GND"], [13.0, 77.5, "GND"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.5, 45.0, "GND"], [89.25, 61.5, "GND"], [89.25, 79.0, "GND"], [80.0, 69.0, "GND"], [3.5, 46.5, "GND"], [18.25, 70.25, "GND"], [77.0, 22.75, "GND"]], "logs": ["CFGSEL1: U32.42 没布通", "CFGSEL0: U32.41 没布通", "NONREM1: U32.40 没布通", "VDD18PLL: U32.62 出不来", "VIN_SW: C4.2 没布通", "+5V: J37.19 没布通", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.57 没布通", "+3V3_HUB: U32.64 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VDAC4: U6.fan:10 没布通", "$2N72: R706.2 没布通", "$2N72: R707.1 没布通", "+5V: J37.19 没布通", "+3V3: R2.2 没布通", "+3V3: R753.1 没布通", "+3V3: R757.1 没布通", "+3V3: J36.9 没布通", "+3V3: J36.10 没布通", "+3V3: J36.40 没布通", "+3V3: R614.1 没布通", "+3V3: J37.9 没布通", "+3V3: C604.1 没布通", "+3V3: U6.fan:15 没布通", "+3V3: J37.10 没布通", "SCL: U35.fan:22 没布通", "SCL: U6.6 出不来", "SCL: U7.fan:6 没布通", "SCL: U20.fan:35 没布通", "SCL: R603.2 没布通", "PRSNT5#: R610.2 出不来", "$3N176: U6.13 出不来", "$2N70: C733.2 没布通", "INA_ALERT: U13.3 没布通", "$3N173: R614.2 没布通", "SDA: U7.fan:8 没布通", "SDA: U35.fan:23 没布通", "SDA: U20.fan:34 没布通", "SDA: R602.2 没布通", "SDA: U13.4 没布通", "FAN_EN: U20.fan:7 没布通", "$6N48: R747.1 没布通", "NTC1: U20.fan:39 没布通", "NTC1: R660.2 没布通", "NTC1: C736.1 没布通", "PRSNT4#: R609.2 没布通", "PRSNT4#: U20.fan:11 没布通", "SCL1: U35.fan:5 没布通", "FAN_OUT_TACH_RAW: R754.1 没布通", "UP_VBUS_DET: U20.fan:23 没布通", "VDAC5: U7.fan:10 没布通", "SCL5: U35.fan:14 没布通", "EFUSE_EN5: U20.fan:21 没布通", "EFUSE_EN4: U20.fan:20 没布通", "VDAC2: U6.fan:11 没布通", "VDAC3: U7.fan:11 没布通", "SCL4: U35.fan:11 没布通", "SDA5: U35.fan:13 没布通", "FAN_PWM_L: J26.4 没布通", "GND: C604.2 找不到落过孔的地方", "GND: C609.1 找不到落过孔的地方", "GND: C610.2 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C740.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C743.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: C750.2 找不到落过孔的地方", "GND: C751.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J34.48 找不到落过孔的地方", "GND: J35.4 找不到落过孔的地方", "GND: J35.12 找不到落过孔的地方", "GND: J35.13 找不到落过孔的地方", "GND: J35.14 找不到落过孔的地方", "GND: J35.15 找不到落过孔的地方", "GND: J35.17 找不到落过孔的地方", "GND: J35.18 找不到落过孔的地方", "GND: J35.20 找不到落过孔的地方", "GND: J35.36 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.44 找不到落过孔的地方", "GND: J35.45 找不到落过孔的地方", "GND: J35.62 找不到落过孔的地方", "GND: J35.64 找不到落过孔的地方", "GND: J36.1 找不到落过孔的地方", "GND: J36.4 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.21 找不到落过孔的地方", "GND: J36.22 找不到落过孔的地方", "GND: J36.23 找不到落过孔的地方", "GND: J36.24 找不到落过孔的地方", "GND: J36.25 找不到落过孔的地方", "GND: J36.26 找不到落过孔的地方", "GND: J36.27 找不到落过孔的地方", "GND: J36.28 找不到落过孔的地方", "GND: J36.29 找不到落过孔的地方", "GND: J36.30 找不到落过孔的地方", "GND: J36.36 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.49 找不到落过孔的地方", "GND: J36.50 找不到落过孔的地方", "GND: J36.51 找不到落过孔的地方", "GND: J36.52 找不到落过孔的地方", "GND: J36.53 找不到落过孔的地方", "GND: J36.54 找不到落过孔的地方", "GND: J36.55 找不到落过孔的地方", "GND: J36.56 找不到落过孔的地方", "GND: J36.57 找不到落过孔的地方", "GND: J36.58 找不到落过孔的地方", "GND: J36.59 找不到落过孔的地方", "GND: J36.60 找不到落过孔的地方", "GND: J36.61 找不到落过孔的地方", "GND: J36.62 找不到落过孔的地方", "GND: J37.1 找不到落过孔的地方", "GND: J37.4 找不到落过孔的地方", "GND: J37.12 找不到落过孔的地方", "GND: J37.13 找不到落过孔的地方", "GND: J37.14 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.21 找不到落过孔的地方", "GND: J37.22 找不到落过孔的地方", "GND: J37.23 找不到落过孔的地方", "GND: J37.24 找不到落过孔的地方", "GND: J37.25 找不到落过孔的地方", "GND: J37.26 找不到落过孔的地方", "GND: J37.27 找不到落过孔的地方", "GND: J37.28 找不到落过孔的地方", "GND: J37.29 找不到落过孔的地方", "GND: J37.30 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: J37.36 找不到落过孔的地方", "GND: J37.62 找不到落过孔的地方", "GND: R615.1 找不到落过孔的地方", "GND: R710.2 找不到落过孔的地方", "GND: R711.2 找不到落过孔的地方", "GND: R718.2 找不到落过孔的地方", "GND: R719.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U13.7 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U32.19 找不到落过孔的地方", "GND: U35.2 找不到落过孔的地方", "GND: U35.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "GND: Y1.4 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +3V3: C604.1 J36.9 J36.10 J36.40 一根铜都没有", "[连通性] $3N176: C608.1 U6.13 一根铜都没有", "[连通性] $3N173: R614.2 一根铜都没有", "[连通性] $2N70: C733.2 一根铜都没有", "[连通性] +5V: J37.19 一根铜都没有", "[连通性] NTC1: C736.1 R660.2 RT601.1 一根铜都没有", "[连通性] +3V3_HUB: U32.46 U32.57 U32.64 一根铜都没有", "[连通性] FAN_12V_SW: 铜分成 3 块", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] FAN_OUT_TACH_RAW: J27.3 一根铜都没有", "[连通性] SCL1: J34.37 一根铜都没有", "[连通性] VDAC2: J35.16 一根铜都没有", "[连通性] PRSNT2#: 铜分成 2 块", "[连通性] VDAC3: J36.16 一根铜都没有", "[连通性] PRSNT3#: 铜分成 2 块", "[连通性] EFUSE_EN4: J37.11 一根铜都没有", "[连通性] VDAC4: J37.16 一根铜都没有", "[连通性] SCL4: J37.37 一根铜都没有", "[连通性] PRSNT4#: J37.63 R609.2 一根铜都没有", "[连通性] EFUSE_EN5: J38.11 一根铜都没有", "[连通性] VDAC5: J38.16 一根铜都没有", "[连通性] SCL5: J38.37 一根铜都没有", "[连通性] SDA5: J38.38 一根铜都没有", "[连通性] PRSNT5#: R610.2 一根铜都没有", "[连通性] $6N48: Q8.3 R747.1 一根铜都没有", "[连通性] SDA: R602.2 U13.4 一根铜都没有", "[连通性] SCL: R603.2 U6.6 一根铜都没有", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] $2N72: R706.2 R707.1 U30.4 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] NONREM1: R719.1 U32.40 一根铜都没有", "[连通性] UP_VBUS_DET: 铜分成 2 块", "[连通性] FAN_EN: R748.1 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes.rejected.json b/.claude/r2/_base_routes.rejected.json new file mode 100644 index 0000000..55170ab --- /dev/null +++ b/.claude/r2/_base_routes.rejected.json @@ -0,0 +1 @@ +{"schema": 8, "layers": 4, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "v12_patch": [5.3, 44.4, 14.3, 48.05], "segs": [[2, 16.75, 44.5, 16.5, 44.5, 0.3, "VIN_SW"], [2, 16.5, 44.5, 12.75, 40.75, 0.3, "VIN_SW"], [2, 17.389, 44.501, 16.75, 44.5, 0.3, "VIN_SW"], [2, 12.499, 40.434, 12.75, 40.75, 0.3, "VIN_SW"], [1, 18.5, 43.75, 17.75, 43.75, 0.3, "+12V"], [1, 17.75, 43.75, 16.0, 45.5, 0.3, "+12V"], [1, 16.0, 45.5, 13.5, 45.5, 0.3, "+12V"], [2, 13.5, 45.5, 12.75, 46.25, 0.3, "+12V"], [2, 17.389, 44, 18.499499999999998, 44, 0.3, "+12V"], [2, 18.499499999999998, 44, 18.5, 43.75, 0.3, "+12V"], [2, 12.499, 46.566, 12.75, 46.25, 0.3, "+12V"], [2, 7.124999999999999, 46.224999999999994, 12.475000000000001, 46.224999999999994, 3.6499999999999986, "+12V"], [2, 83.251, 7.724, 83.251, 6.474, 0.15, "UP_DP"], [2, 83.251, 6.474, 84.249, 6.474, 0.15, "UP_DP"], [2, 84.249, 6.474, 84.249, 7.724, 0.15, "UP_DP"], [2, 83.749, 7.724, 83.749, 8.974, 0.15, "UP_DM"], [2, 83.749, 8.974, 84.75, 8.974, 0.15, "UP_DM"], [2, 84.75, 8.974, 84.75, 7.724, 0.15, "UP_DM"], [2, 50.249, 43.03, 50.249, 47.9995, 0.28, "USB3_DM"], [2, 50.249, 47.9995, 48.499, 47.9995, 0.28, "USB3_DM"], [2, 48.499, 47.9995, 48.499, 47.5995, 0.28, "USB3_DM"], [2, 50.749, 43.03, 50.749, 48.799499999999995, 0.28, "USB3_DP"], [2, 50.749, 48.799499999999995, 47.501, 48.799499999999995, 0.28, "USB3_DP"], [2, 47.501, 48.799499999999995, 47.501, 48.299499999999995, 0.28, "USB3_DP"], [1, 48.499, 47.5995, 48.499, 45.4, 0.28, "USB3_DM"], [1, 47.501, 48.299499999999995, 47.501, 45.4, 0.28, "USB3_DP"], [1, 47.25, 64.5, 47.0, 64.25, 0.28, "USB2_DP"], [1, 47.0, 64.25, 47.0, 61.5, 0.28, "USB2_DP"], [1, 47.0, 61.5, 46.5, 61.0, 0.28, "USB2_DP"], [2, 46.5, 61.0, 46.5, 49.5, 0.28, "USB2_DP"], [2, 46.5, 49.5, 46.25, 49.25, 0.28, "USB2_DP"], [2, 46.25, 49.25, 46.25, 46.75, 0.28, "USB2_DP"], [2, 46.25, 46.75, 49.25, 43.75, 0.28, "USB2_DP"], [1, 47.501, 65.72, 47.25, 64.5, 0.28, "USB2_DP"], [2, 49.251, 43.03, 49.25, 43.75, 0.28, "USB2_DP"], [1, 48.25, 64.5, 48.25, 63.0, 0.28, "USB2_DM"], [1, 48.25, 63.0, 48.0, 62.75, 0.28, "USB2_DM"], [1, 48.0, 62.75, 48.0, 60.25, 0.28, "USB2_DM"], [1, 48.0, 60.25, 47.5, 59.75, 0.28, "USB2_DM"], [1, 47.5, 59.75, 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10.5, "GND"], [58.5, 10.5, "GND"], [59.5, 10.5, "GND"], [60.5, 10.5, "GND"], [61.5, 10.5, "GND"], [62.5, 10.5, "GND"], [63.5, 10.5, "GND"], [35.75, 3.25, "GND"], [38.5, 6.25, "GND"], [44.75, 4.75, "GND"], [46.5, 3.25, "GND"], [49.5, 6.25, "GND"], [50.5, 6.25, "GND"], [51.5, 6.25, "GND"], [52.5, 6.25, "GND"], [53.5, 6.25, "GND"], [54.5, 6.25, "GND"], [55.5, 6.25, "GND"], [56.5, 6.25, "GND"], [57.5, 6.25, "GND"], [58.5, 6.25, "GND"], [59.5, 6.25, "GND"], [60.5, 6.25, "GND"], [61.5, 6.25, "GND"], [62.5, 6.25, "GND"], [63.5, 6.25, "GND"], [66.25, 4.75, "GND"], [21.5, 88.75, "GND"], [15.0, 83.25, "GND"], [27.75, 78.25, "GND"], [25.0, 81.0, "GND"], [8.5, 22.5, "GND"], [4.25, 64.75, "GND"], [2.0, 42.0, "GND"], [16.75, 63.25, "GND"], [85.75, 11.75, "GND"], [82.75, 11.75, "GND"], [62.0, 34.75, "GND"], [90.75, 10.5, "GND"], [23.75, 88.75, "GND"], [15.75, 83.25, "GND"], [5.5, 88.75, "GND"], [21.75, 85.5, "GND"], [87.5, 26.0, "GND"], [21.0, 8.0, "GND"], [21.5, 45.0, "GND"], [18.75, 42.5, "GND"], [89.25, 76.5, "GND"], [80.0, 69.0, "GND"], [3.25, 45.5, "GND"], [77.0, 22.75, "GND"], [57.0, 41.25, "GND"], [35.5, 63.5, "GND"]], "logs": ["USB1_DP: U32.2 出不来", "USB1_DM: U32.1 出不来", "USB4_DM: U32.8 出不来", "UP_DP: U32.59 出不来", "UP_DM: U32.58 出不来", "VIN_SW: C4.2 没布通", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "BLD_REF: R4.1 出不来", "XTAL2: U32.60 没布通", "VDD18PLL: U32.62 没布通", "XTAL1: U32.61 没布通", "SDA: U6.7 出不来", "VBUS_DET: U32.44 没布通", "VBUS_DET: R709.2 没布通", "CFGSEL1: U32.42 没布通", "CFGSEL0: U32.41 没布通", "BLD_A: R6.1 没布通", "VDAC2: U6.11 出不来", "VDAC3: U7.11 出不来", "PRSNT3#: R608.2 没布通", "$3N192: U7.13 出不来", "$3N176: U6.13 出不来", "INA_ALERT: U13.3 出不来", "$6N49: R746.1 没布通", "$2N72: R706.2 没布通", "$2N72: R707.1 没布通", "FAN_EN: R748.1 没布通", "$6N74: R756.2 没布通", "$6N74: R755.1 没布通", "SDA1: U35.4 出不来", "SCL3: U35.9 出不来", "SDA5: U35.13 没布通", "RXD0: U20.36 没布通", "TXD0: U20.37 没布通", "FAN_TACH_OUT: Q10.3 没布通", "FAN_TACH_IN: U20.5 没布通", "EFUSE_EN4: U20.20 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN2: J35.11 没布通", "EFUSE_EN1: U20.17 没布通", "FAN_PWM_L: J26.4 没布通", "+5V: J35.19 没布通", "+5V: J36.19 没布通", "+5V: J35.32 没布通", "+5V: J36.32 没布通", "+5V: J37.19 没布通", "+5V: J37.32 没布通", "+5V: J38.19 没布通", "+5V: C753.1 没布通", "+5V: C752.1 没布通", "+5V: J38.32 没布通", "FAN_12V_SW: J27.2 没布通", "FAN_12V_SW: R750.2 没布通", "FAN_12V_SW: C738.1 没布通", "FAN_12V_SW: R754.2 没布通", "+3V3: U13.6 没布通", "+3V3: C11.1 没布通", "+3V3: J36.9 没布通", "+3V3: J36.10 没布通", "+3V3: J36.40 没布通", "+3V3: C604.1 没布通", "+3V3: J37.9 没布通", "+3V3: U6.15 出不来", "+3V3: J37.10 没布通", "+3V3: J37.40 没布通", "+3V3: C607.1 没布通", "+3V3: U7.15 出不来", "+3V3: J38.9 没布通", "+3V3: J38.10 没布通", "+3V3: R608.1 出不来", "+3V3: R607.1 没布通", "+3V3: J38.40 没布通", "+3V3: R605.1 出不来", "+3V3: R606.1 没布通", "+3V3: R611.1 没布通", "+3V3: R602.1 没布通", "+3V3: R603.1 没布通", "+3V3: C601.2 没布通", "+3V3: R660.1 出不来", "+3V3: C602.2 没布通", "+3V3_HUB: U32.10 出不来", "+3V3_HUB: U32.46 没布通", "+3V3_HUB: U32.5 出不来", "+3V3_HUB: U32.52 没布通", "+3V3_HUB: U32.57 出不来", "+3V3_HUB: U32.64 没布通", "+3V3_HUB: C751.1 没布通", "+3V3_HUB: C744.1 出不来", "GND: C604.2 找不到落过孔的地方", "GND: C609.1 找不到落过孔的地方", "GND: C610.2 找不到落过孔的地方", "GND: C612.1 找不到落过孔的地方", "GND: C739.2 找不到落过孔的地方", "GND: C742.2 找不到落过孔的地方", "GND: C743.2 找不到落过孔的地方", "GND: C744.2 找不到落过孔的地方", "GND: C745.2 找不到落过孔的地方", "GND: C746.2 找不到落过孔的地方", "GND: C749.2 找不到落过孔的地方", "GND: J23.B1A12 找不到落过孔的地方", "GND: J35.4 找不到落过孔的地方", "GND: J35.39 找不到落过孔的地方", "GND: J35.48 找不到落过孔的地方", "GND: J36.15 找不到落过孔的地方", "GND: J36.17 找不到落过孔的地方", "GND: J36.18 找不到落过孔的地方", "GND: J36.20 找不到落过孔的地方", "GND: J36.21 找不到落过孔的地方", "GND: J36.22 找不到落过孔的地方", "GND: J36.23 找不到落过孔的地方", "GND: J36.24 找不到落过孔的地方", "GND: J36.25 找不到落过孔的地方", "GND: J36.26 找不到落过孔的地方", "GND: J36.27 找不到落过孔的地方", "GND: J36.28 找不到落过孔的地方", "GND: J36.29 找不到落过孔的地方", "GND: J36.30 找不到落过孔的地方", "GND: J36.31 找不到落过孔的地方", "GND: J36.39 找不到落过孔的地方", "GND: J36.44 找不到落过孔的地方", "GND: J36.45 找不到落过孔的地方", "GND: J36.48 找不到落过孔的地方", "GND: J36.64 找不到落过孔的地方", "GND: J37.12 找不到落过孔的地方", "GND: J37.13 找不到落过孔的地方", "GND: J37.14 找不到落过孔的地方", "GND: J37.15 找不到落过孔的地方", "GND: J37.17 找不到落过孔的地方", "GND: J37.18 找不到落过孔的地方", "GND: J37.20 找不到落过孔的地方", "GND: J37.31 找不到落过孔的地方", "GND: J37.36 找不到落过孔的地方", "GND: J37.44 找不到落过孔的地方", "GND: J37.45 找不到落过孔的地方", "GND: J37.64 找不到落过孔的地方", "GND: J38.1 找不到落过孔的地方", "GND: J38.15 找不到落过孔的地方", "GND: J38.17 找不到落过孔的地方", "GND: R615.1 找不到落过孔的地方", "GND: R617.1 找不到落过孔的地方", "GND: R708.2 找不到落过孔的地方", "GND: R720.2 找不到落过孔的地方", "GND: U6.14 找不到落过孔的地方", "GND: U7.14 找不到落过孔的地方", "GND: U19.1 找不到落过孔的地方", "GND: U20.1 找不到落过孔的地方", "GND: U30.1 找不到落过孔的地方", "GND: U35.12 找不到落过孔的地方", "GND: U35.21 找不到落过孔的地方", "GND: Y1.2 找不到落过孔的地方", "[连通性] VIN_SW: C4.2 一根铜都没有", "[连通性] +3V3: C11.1 C602.2 J36.9 J36.10 一根铜都没有", "[连通性] EN: 铜分成 2 块", "[连通性] $3N176: C608.1 U6.13 一根铜都没有", "[连通性] $3N192: C611.1 U7.13 一根铜都没有", "[连通性] +5V: C752.1 J35.19 J35.32 J36.19 一根铜都没有", "[连通性] +3V3_HUB: C751.1 U32.10 U32.5 U32.46 一根铜都没有", "[连通性] FAN_12V_SW: C738.1 J27.2 R750.2 R754.2 一根铜都没有", "[连通性] XTAL1: U32.61 一根铜都没有", "[连通性] XTAL2: U32.60 一根铜都没有", "[连通性] VDD18PLL: C743.1 U32.62 一根铜都没有", "[连通性] $6N49: R746.1 一根铜都没有", "[连通性] UP_DM: U32.58 一根铜都没有", "[连通性] UP_DP: U32.59 一根铜都没有", "[连通性] VBUS_UP: 铜分成 2 块", "[连通性] FAN_IN_TACH_RAW: 铜分成 2 块", "[连通性] FAN_PWM_L: J26.4 一根铜都没有", "[连通性] TXD0: J33.2 U20.37 一根铜都没有", "[连通性] RXD0: J33.3 U20.36 一根铜都没有", "[连通性] EFUSE_EN1: J34.11 U20.17 一根铜都没有", "[连通性] SDA1: J34.38 U35.4 一根铜都没有", "[连通性] INT#: 铜分成 4 块", "[连通性] USB1_DP: J34.46 U32.2 一根铜都没有", "[连通性] USB1_DM: J34.47 U32.1 一根铜都没有", "[连通性] EFUSE_EN2: J35.11 U20.18 一根铜都没有", "[连通性] VDAC2: U6.11 一根铜都没有", "[连通性] EFUSE_EN3: J36.11 U20.19 一根铜都没有", "[连通性] VDAC3: U7.11 一根铜都没有", "[连通性] SCL3: J36.37 U35.9 一根铜都没有", "[连通性] PRSNT3#: R608.2 一根铜都没有", "[连通性] EFUSE_EN4: J37.11 U20.20 一根铜都没有", "[连通性] USB4_DM: J37.47 U32.8 一根铜都没有", "[连通性] SDA5: J38.38 U35.13 一根铜都没有", "[连通性] BLD_A: R6.1 一根铜都没有", "[连通性] FAN_TACH_IN: U20.5 一根铜都没有", "[连通性] $6N74: Q10.1 R755.1 R756.2 一根铜都没有", "[连通性] FAN_TACH_OUT: U20.4 一根铜都没有", "[连通性] BLD_REF: U29.1 一根铜都没有", "[连通性] SDA: U6.7 一根铜都没有", "[连通性] INA_ALERT: U13.3 一根铜都没有", "[连通性] $2N72: R706.2 R707.1 U30.4 一根铜都没有", "[连通性] VBUS_DET: R709.2 R710.1 U32.44 一根铜都没有", "[连通性] CFGSEL0: R711.1 U32.41 一根铜都没有", "[连通性] CFGSEL1: R712.1 U32.42 一根铜都没有", "[连通性] HUB_RST: 铜分成 2 块", "[连通性] FAN_EN: R748.1 U20.7 一根铜都没有"]} \ No newline at end of file diff --git a/.claude/r2/_base_routes_before3v3.json b/.claude/r2/_base_routes_before3v3.json new file mode 100644 index 0000000..4229cdd --- /dev/null +++ b/.claude/r2/_base_routes_before3v3.json @@ -0,0 +1 @@ +{"segs": [[1, 24.8755, 63.251, 25.4755, 63.251, 0.15, "USB1_DM"], [1, 25.4755, 63.251, 29.927, 58.8, 0.15, "USB1_DM"], [1, 29.927, 58.8, 30.5, 58.8, 0.15, "USB1_DM"], [1, 24.8755, 63.749, 25.4755, 63.749, 0.15, "USB1_DP"], [1, 25.4755, 63.749, 28.823, 60.401, 0.15, "USB1_DP"], [1, 28.823, 60.401, 32.0, 60.401, 0.15, "USB1_DP"], [1, 24.8755, 64.249, 25.4755, 64.249, 0.15, "USB2_DM"], [1, 25.4755, 64.249, 27.723, 62.001, 0.15, "USB2_DM"], [1, 27.723, 62.001, 35.0, 62.001, 0.15, "USB2_DM"], [1, 24.8755, 64.75, 25.4755, 64.75, 0.15, "USB2_DP"], [1, 25.4755, 64.75, 26.625, 63.601, 0.15, "USB2_DP"], [1, 26.625, 63.601, 36.5, 63.601, 0.15, "USB2_DP"], [1, 24.8755, 65.75, 25.4755, 65.75, 0.15, "USB3_DM"], [1, 25.4755, 65.75, 26.025, 65.201, 0.15, "USB3_DM"], [1, 26.025, 65.201, 41.0, 65.201, 0.15, "USB3_DM"], [1, 24.8755, 66.251, 25.4755, 66.251, 0.15, "USB3_DP"], [1, 25.4755, 66.251, 26.024, 66.8, 0.15, "USB3_DP"], [1, 26.024, 66.8, 39.5, 66.8, 0.15, "USB3_DP"], [1, 24.8755, 66.749, 25.4755, 66.749, 0.15, "USB4_DM"], [1, 25.4755, 66.749, 27.128, 68.401, 0.15, "USB4_DM"], [1, 27.128, 68.401, 36.5, 68.401, 0.15, "USB4_DM"], [1, 24.8755, 67.249, 25.4755, 67.249, 0.15, "USB4_DP"], [1, 25.4755, 67.249, 28.228, 70.001, 0.15, "USB4_DP"], [1, 28.228, 70.001, 35.0, 70.001, 0.15, "USB4_DP"], [1, 24.8755, 68.25, 25.4755, 68.25, 0.15, "USB5_DM"], [1, 25.4755, 68.25, 28.825, 71.6, 0.15, "USB5_DM"], [1, 28.825, 71.6, 32.0, 71.6, 0.15, "USB5_DM"], [1, 24.8755, 68.75, 25.4755, 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C610.1 没布通", "+3V3: R604.1 没布通", "+3V3: C602.2 没布通", "+3V3: J35.10 没布通", "+3V3: J35.9 没布通", "+3V3: R605.1 没布通", "+3V3: U35.24 没布通", "+3V3: R603.1 没布通", "+3V3: C9.2 没布通", "+3V3: R606.1 没布通", "+3V3: R616.1 没布通", "+3V3: R614.1 没布通", "+3V3: J34.40 没布通", "+3V3: U6.15 没布通", "+3V3: C601.2 没布通", "+3V3: R602.1 没布通", "+3V3: C11.1 没布通", "+3V3: C10.2 没布通", "+3V3: C607.1 没布通", "+3V3: J34.10 没布通", "+3V3: J34.9 没布通", "+3V3: U7.15 没布通", "+3V3: C604.1 没布通", "+3V3: U13.6 没布通", "+3V3_HUB: RAIL.rail 出不来", "+3V3_HUB: RAIL.rail 出不来", "+3V3_HUB: RAIL.rail 出不来", "GATE: Q1.4 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "HUB_RST: R716.1 出不来", "$2N72: U30.4 出不来", "XTAL2: Y1.3 没布通", "XTAL2: C741.1 出不来", "FB3V3: U19.4 没布通", "EN: R601.2 没布通", "EN: C603.1 没布通", "SCL: R603.2 没布通", "SCL: U35.22 没布通", "SCL: U6.6 没布通", "SCL: U7.7 出不来", "SCL: U7.6 没布通", "SCL: U13.2 没布通", "SCL: U13.5 没布通", "INA_ALERT: R605.2 没布通", "INA_ALERT: U13.3 没布通", "VBUS_DET: R710.1 没布通", "VBUS_DET: U32.44 没布通", "CFGSEL0: U32.41 没布通", "$6N45: R748.2 没布通", "$6N45: R749.2 没布通", "PRSNT2#: R607.2 没布通", "PRSNT2#: U20.9 没布通", "$6N49: R747.2 没布通", "VDAC5: U7.10 没布通", "VDAC5: U7.9 没布通", "VDAC4: U6.10 没布通", "VDAC4: U6.9 没布通", "VDAC3: U7.12 没布通", "VDAC3: U7.11 没布通", "VDAC1: U6.4 没布通", "VDAC1: U6.3 没布通", "VDAC2: U6.12 没布通", "VDAC2: U6.11 没布通", "SCL4: U35.11 没布通", "$6N48: R747.1 没布通", "UP_VBUS_DET: R722.1 没布通", "UP_VBUS_DET: R721.2 没布通", "$4N221: J23.B5 出不来", "CFGSEL1: U32.42 没布通", "$2N74: C733.1 没布通", "SDA4: U35.10 没布通", "$2N70: C733.2 没布通", "SCL5: U35.14 没布通", "SDA3: U35.8 没布通", "SCL1: U35.5 没布通", "MUX_RST#: R611.2 没布通", "MUX_RST#: U35.3 没布通", "SCL2: U35.7 没布通", "SDA2: U35.6 没布通", "PRSNT5#: R610.2 没布通", "PRSNT5#: J38.63 没布通", "PRSNT4#: R609.2 没布通", "PRSNT4#: U20.11 没布通", "PRSNT1#: R606.2 没布通", "PRSNT1#: J34.63 没布通", "BLD_A: R6.1 没布通", "$3N173: C609.2 没布通", "$3N173: U6.16 没布通", "$3N192: U7.13 没布通", "$3N176: U6.13 没布通", "INT#: U20.32 没布通", "INT#: J34.43 没布通", "INT#: R604.2 没布通", "$6N55: R734.1 没布通", "$6N55: R733.2 没布通", "$6N64: R751.1 没布通", "$6N64: R752.2 没布通", "$6N74: R755.1 没布通", "$6N74: R756.2 没布通", "PRSNT3#: R608.2 没布通", "PRSNT3#: U20.10 没布通", "FAN_TACH_IN: U20.5 没布通", "FAN_TACH_IN: R753.2 没布通", "FAN_TACH_OUT: U20.4 没布通", "FAN_TACH_OUT: R757.2 没布通", "FAN_EN: R748.1 没布通", "FAN_PWM: R733.1 没布通", "SCL3: U35.9 没布通", "SDA1: U35.4 没布通", "$1N114: Q3.8 没布通", "$1N114: Q3.7 没布通", "$1N114: Q3.6 没布通", "$1N114: Q3.5 没布通", "SDA5: U35.13 没布通", "RXD0: U20.36 没布通", "TXD0: U20.37 没布通", "IO0: U20.27 没布通", "EFUSE_EN1: U20.17 没布通", "EFUSE_EN2: U20.18 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN4: U20.20 没布通", "EFUSE_EN5: J38.11 没布通", "FAN_PWM_L: Q6.3 没布通"]} \ No newline at end of file diff --git a/.claude/r2/_base_sch_bom.json b/.claude/r2/_base_sch_bom.json new file mode 100644 index 0000000..f5463b1 --- /dev/null +++ b/.claude/r2/_base_sch_bom.json @@ -0,0 +1 @@ +{"A1-INPUT": [{"d": "Q1", "uuid": "895b6d7b689cc531", "fp": {"name": "SOP-8_L5.0-W4.0-P1.27-LS6.0-BL"}}, {"d": "Q3", "uuid": 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45, + 786, + "手机主板 J1401 ──原厂「主板→尾插」排线── 本页的 J7x 座 ──> C3-USB 上的 ESD / Rp / 口温 / VBUS 开关。", + 0, + 10 + ], + [ + 45, + 350, + "⚠⚠ 打样前必做：买一块原厂尾插小板当量具（§13.5）", + 0, + 12 + ], + [ + 45, + 332, + "我们这颗座子接的就是原厂小板上那颗座子的位置 —— 同一根排线的同一端。", + 0, + 10 + ], + [ + 45, + 316, + "所以「物理位置 ↔ 网络」照抄原厂小板的就一定对，不用管 Hirose 编号，", + 0, + 10 + ], + [ + 45, + 300, + "也不用管排线翻没翻。裸板上从 USB-C 母座（0.5mm 间距，好扎）打通断，", + 0, + 10 + ], + [ + 45, + 284, + "量出 D+/D−/VBUS/CC1/GND/口温 各通到 BM24 座的哪个物理位置，抄进封装即可。", + 0, + 10 + ], + [ + 45, + 268, + "顺带一次解决：座子是公头还是母座、口温电阻到底多大、ESD 用什么 —— 全照抄。", + 0, + 10 + ], + [ + 45, + 244, + "（公开渠道没有小板资料：我们这份 PDF 44 页全是主板，mobilerdx 的「完整包」", + 0, + 10 + ], + [ + 45, + 228, + " 也是同一套，vinafix 上 dipper 只有 Mi 8 Lite / Mi 8X。2026-09-04 查过。）", + 0, + 10 + ], + [ + 45, + 212, + "本页按 §13.4 的 Hirose 编号连线，排线翻不翻只影响封装：", + 0, + 10 + ], + [ + 45, + 196, + "这颗座子无论如何都要自建封装（立创那个是 DIP 绕圈编号），", + 0, + 10 + ], + [ + 45, + 180, + "自建时把「焊盘号 = 经排线看过去的 Hirose 脚号」定死即可，", + 0, + 10 + ], + [ + 45, + 164, + "两种候选正好差一个 180° 贴片方向。", + 0, + 10 + ], + [ + 620, + 350, + "⚠ BM24 只有 10 次插拔寿命，而一根排线上有两个插拔点。", + 0, + 10 + ], + [ + 620, + 334, + " 插上就别反复拔，备件按每台 2 根备。", + 0, + 10 + ], + [ + 620, + 310, + "⚠ 没画的引脚（音频 / 射频控制 / 各路 VREG / CC2）全部悬空。", + 0, + 10 + ], + [ + 620, + 294, + " CC2 必须悬空 —— 只拉一边 CC，手机才判得出插入方向。", + 0, + 10 + ], + [ + 620, + 270, + "⚠ 调试串口（pin24 TX / pin29 RX）故意不引：1.8V 电平，", + 0, + 10 + ], + [ + 620, + 254, + " 接 ESP32 要加电平转换；而且 pin29 夹在两个地脚中间，", + 0, + 10 + ], + [ + 620, + 238, + " 引出来会把这一片排版挤垄。真要用就是一次改板。", + 0, + 10 + ], + [ + 130, + 735, + "CH1 手机位", + 0, + 12 + ], + [ + 480, + 735, + "CH2 手机位", + 0, + 12 + ], + [ + 830, + 735, + "CH3 手机位", + 0, + 12 + ], + [ + 45, + 806, + "【载板 C5-J1401A】手机尾插 J1401 对插座 —— CH1/2/3（方案 D，§13.5）", + 0, + 14 + ], + [ + 45, + 786, + "手机主板 J1401 ──原厂「主板→尾插」排线── 本页的 J7x 座 ──> C3-USB 上的 ESD / Rp / 口温 / VBUS 开关。", + 0, + 10 + ], + [ + 45, + 350, + "引脚映射（2026-09-04 实测 + 推导，§13.5）：原厂排线在摊平的平面里是**恒等映射**", + 0, + 12 + ], + [ + 45, + 332, + "（上方内侧↔下方内侧、上方外侧↔下方外侧，从左到右一一导通，用户实测）；", + 0, + 10 + ], + [ + 45, + 316, + "两个公头在同一面、相差 180°。于是 J1401(排, m) ↔ 本座子(同排, 26-m)：", + 0, + 10 + ], + [ + 45, + 296, + " 奇数脚 N → 50-N 偶数脚 N → 52-N", + 0, + 12 + ], + [ + 45, + 276, + "即 D+ 46→6、D- 48→4、CC1 30→22、口温 38→14；地 12 个 → 1,2,8,12,16,19,23,24,29,37,41,47。", + 0, + 10 + ], + [ + 45, + 260, + "（这条推导不需要知道「哪一排是奇数排」—— 两边都用 Hirose 脚号表达，那个未知量抵消了。）", + 0, + 10 + ], + [ + 45, + 232, + "⚠ 电源触点约定：符号 pin51 = Hirose pin1/2 那一端，pin52 = pin49/50 那一端。", + 0, + 10 + ], + [ + 45, + 216, + " J1401 的 G1(地) 在它的 pin1/2 端，经上面的反序落到我们这颗的 pin49/50 端", + 0, + 10 + ], + [ + 45, + 200, + " → **52 = GND，51 = VBUS**。⚠ 首件仍要实测，接反就是 5V 对地短路。", + 0, + 10 + ], + [ + 620, + 350, + "⚠ 机械：两个公头同一面 → 两个母座都得朝上、大致共面。", + 0, + 10 + ], + [ + 620, + 334, + " 而 J1401 朝天、本座子也朝天、载板在手机下面，所以排线必须走", + 0, + 10 + ], + [ + 620, + 318, + " **台阶式下折**（下 90° 再上 90°，净旋转为零，公头仍朝下），", + 0, + 10 + ], + [ + 620, + 302, + " **不能走 U 形回折**（会把面翻过来，插不进去）。", + 0, + 10 + ], + [ + 620, + 286, + " → 本座子要放在手机轮廓之外、J1401 出线的那一侧，PCB 摆位时定死。", + 0, + 10 + ], + [ + 620, + 258, + "⚠ BM24 只有 10 次插拔寿命，而一根排线上有两个插拔点 —— 插上就别反复拔。", + 0, + 10 + ], + [ + 620, + 234, + "⚠ 没画的引脚（音频 / 射频控制 / 各路 VREG / CC2）全部悬空。", + 0, + 10 + ], + [ + 620, + 218, + " CC2 必须悬空 —— 只拉一边 CC，手机才判得出插入方向。", + 0, + 10 + ], + [ + 620, + 202, + "⚠ 调试串口（pin24 TX / pin29 RX）故意不引：1.8V 电平，接 ESP32 要电平转换。", + 0, + 10 + ], + [ + 130, + 735, + "CH1 手机位", + 0, + 12 + ], + [ + 480, + 735, + "CH2 手机位", + 0, + 12 + ], + [ + 830, + 735, + "CH3 手机位", + 0, + 12 + ], + [ + 45, + 806, + "【载板 C5-J1401A】手机尾插 J1401 对插座 —— CH1/2/3（方案 D，§13.5）", + 0, + 14 + ], + [ + 45, + 786, + "手机主板 J1401 ──原厂「主板→尾插」排线── 本页的 J7x 座 ──> C3-USB 上的 ESD / Rp / 口温 / VBUS 开关。", + 0, + 10 + ], + [ + 45, + 350, + "引脚映射（2026-09-04 实测 + 推导，§13.5）：原厂排线在摊平的平面里是**恒等映射**", + 0, + 12 + ], + [ + 45, + 332, + "（上方内侧↔下方内侧、上方外侧↔下方外侧，从左到右一一导通，用户实测）；", + 0, + 10 + ], + [ + 45, + 316, + "两个公头在同一面、相差 180°。于是 J1401(排, m) ↔ 本座子(同排, 26-m)：", + 0, + 10 + ], + [ + 45, + 296, + " 奇数脚 N → 50-N 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sr595_edl_bit）。", + 0, + 10 + ], + [ + 45, + 756, + "供电 +3V3_HUB（U31）。OE# 上拉 100k（R609）：ESP32 复位期间 / 排针没插时 24 路输出全高阻，", + 0, + 10 + ], + [ + 45, + 740, + "配合每个 MOS 栅极 / EDL_EN 的 100k 下拉（C4-SITEn），15 个按键不会误按、五台手机不会误进 9008。", + 0, + 10 + ], + [ + 720, + 700, + "HUB_RST 是低有效（USB2517I RESET_N，R716 上拉）：", + 0, + 10 + ], + [ + 720, + 684, + "影子位 = 1 才是「Hub 正常跑」，上电安全影子是 1<<23 不是 0。", + 0, + 10 + ], + [ + 720, + 660, + "K*_PWR / K*_VUP / K*_VDN 去 C4-SITE1~5 的按键 MOS 栅极；", + 0, + 10 + ], + [ + 720, + 644, + "EDL_EN1~5 去 C4-SITE1~5 的 TS5A3157。全是载板内部网络，不再过排针。", + 0, + 10 + ], + [ + 720, + 620, + "空脚：U21.QE、U22.QA、U22.QE；U33.QH' 是链尾。", + 0, + 10 + ], + [ + 45, + 806, + "【C6-KEYS】三片 74HC595 —— 15 路侧键 + 5 路 EDL_EN + HUB_RST（2026-09-06 从下板搬来，§26.23）", + 0, + 13 + ], + [ + 45, + 790, + "链序 U21 → U22 → U33，整条 24 位；SRCLK / RCLK / OE# 三片共用，四根控制线从 J32 北排 3~6 行进来（C1-CONN）。", + 0, + 10 + ], + [ + 45, + 776, + "先移入的字节落在 U33；固件发送顺序 U33 → U22 → U21，每字节 QH 先发。输出位表见设计文档 §17.2（固件 sr595_key_bit / sr595_edl_bit）。", + 0, + 10 + ], + [ + 45, + 762, + "供电 +3V3_HUB（U31）。OE# 上拉 100k（R609）：ESP32 复位期间 / 排针没插时 24 路输出全高阻，", + 0, + 10 + ], + [ + 45, + 748, + "配合每个 MOS 栅极 / EDL_EN 的 100k 下拉（C4-SITEn），15 个按键不会误按、五台手机不会误进 9008。", + 0, + 10 + ], + [ + 720, + 640, + "HUB_RST 是低有效（USB2517I RESET_N，R716 上拉）：", + 0, + 10 + ], + [ + 720, + 624, + "影子位 = 1 才是「Hub 正常跑」，上电安全影子是 1<<23 不是 0。", + 0, + 10 + ], + [ + 720, + 600, + "K*_PWR / K*_VUP / K*_VDN 去 C4-SITE1~5 的按键 MOS 栅极；", + 0, + 10 + ], + [ + 720, + 584, + "EDL_EN1~5 去 C4-SITE1~5 的 TS5A3157。全是载板内部网络，不再过排针。", + 0, + 10 + ], + [ + 720, + 560, + "空脚：U21.QE、U22.QA、U22.QE；U33.QH' 是链尾。", + 0, + 10 + ] + ], + "nRect": 0, + "nPoly": 0 +} \ No newline at end of file diff --git a/.claude/r2/_dup.js b/.claude/r2/_dup.js new file mode 100644 index 0000000..077f862 --- /dev/null +++ b/.claude/r2/_dup.js @@ -0,0 +1,10 @@ +const cs = (await eda.sch_PrimitiveComponent.getAll()).filter(c => c.getState_ComponentType() === 'part'); +const out = cs.map(c => [c.getState_Designator(), Math.round(c.getState_X()), Math.round(c.getState_Y()), + (c.getState_Component()||{}).name]); +const cnt = {}; +for (const o of out) cnt[o[0]] = (cnt[o[0]] || 0) + 1; +const dup = Object.keys(cnt).filter(k => cnt[k] > 1); +const d1 = cs.find(c => c.getState_Designator() === 'D1'); +const d1p = d1 ? (await d1.getAllPins()).map(p => [p.getState_PinNumber(), + (p.getState_PinName ? p.getState_PinName() : ''), Math.round(p.getState_X()), Math.round(p.getState_Y())]) : null; +return { n: out.length, dup, dupRows: out.filter(o => dup.indexOf(o[0]) >= 0), d1p }; diff --git a/.claude/r2/_m6_board_copper.json b/.claude/r2/_m6_board_copper.json new file mode 100644 index 0000000..b947161 --- /dev/null +++ b/.claude/r2/_m6_board_copper.json @@ -0,0 +1 @@ +{"segs": [[1, 35.5, 4, 35.5, 7, 0.2, "GND"], [1, 38.5, 4, 38.5, 7, 0.2, "GND"], [1, 45.5, 7, 46.5, 7, 0.4, "GND"], [1, 45.5, 4, 45.5, 7, 0.2, "GND"], [1, 46.5, 4, 46.5, 7, 0.2, "GND"], [1, 49.5, 4, 49.5, 7, 0.2, "GND"], [1, 50.5, 4, 50.5, 7, 0.2, "GND"], [1, 49.5, 7, 50.5, 7, 0.4, "GND"], [1, 51.5, 4, 51.5, 7, 0.2, "GND"], [1, 50.5, 7, 51.5, 7, 0.4, "GND"], [1, 52.5, 4, 52.5, 7, 0.2, "GND"], [1, 51.5, 7, 52.5, 7, 0.4, "GND"], [1, 53.5, 4, 53.5, 7, 0.2, "GND"], [1, 52.5, 7, 53.5, 7, 0.4, "GND"], [1, 54.5, 4, 54.5, 7, 0.2, "GND"], [1, 53.5, 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27.75, "KPAD_PWR"], [5.5, 28, "KPAD_PWR"], [59.5, 40.25, "+5V"], [56.25, 40.25, "+5V"], [59.5, 45, "+5V"], [82, 45, "+5V"], [82, 40.25, "+5V"], [85.25, 40.25, "+5V"], [85.25, 37.5, "+5V"], [96.25, 36.75, "+5V"], [96.25, 10.75, "+5V"], [65.75, 10.75, "+5V"], [65.75, 20, "+5V"], [61.25, 20, "+5V"], [63.5, 10.5, "+5V"], [53, 10.5, "+5V"], [59.25, 17.25, "USB_DM"], [58.5, 15, "USB_DM"], [51.25, 15, "USB_DM"], [51.25, 17.25, "USB_DM"], [40, 17.5, "USB_DM"], [39.25, 35.75, "USB_DM"], [47.75, 35.75, "USB_DM"], [86.75, 44.75, "$1N137"], [84.75, 44.75, "$1N137"], [88.25, 37.75, "VO"], [89, 37.75, "VO"], [89.25, 42, "VO"], [93, 42, "VO"], [86.25, 30.5, "VO"], [84, 30.5, "VO"], [84, 26.5, "VO"], [76.25, 26.75, "VO"], [86.25, 51, "+12V_F"], [89.25, 51, "+12V_F"], [86.25, 51.75, "+12V_F"], [86, 57.75, "+12V_F"], [87.5, 57.75, "+12V_F"], [95, 51.5, "+12V_F"], [86, 62.5, "+12V_F"], [88.5, 62.5, "+12V_F"], [93.5, 52.25, "$1N128"], [87.5, 52.25, "$1N128"], [94.5, 54.25, "$1N131"], [93.75, 54.25, "$1N131"], [94, 57, "$1N131"], [80.5, 56.75, "$1N131"], [80.5, 41.25, "$1N131"], [96, 41, "$1N131"], [96, 46.5, "$1N131"], [92.25, 48.75, "$1N131"], [95.75, 48.25, "$1N129"], [92.75, 50, "$1N129"]]} \ No newline at end of file diff --git a/.claude/r2/_m6_hand.py b/.claude/r2/_m6_hand.py new file mode 100644 index 0000000..dabfda1 --- /dev/null +++ b/.claude/r2/_m6_hand.py @@ -0,0 +1,56 @@ +# -*- coding: utf-8 -*- +u"""M6 手工补线清单（五个被自家邻脚封死的焊盘）。推导见方案 §26.6。""" +W = 0.15 +# 要删的旧线 (layer, x0,y0,x1,y1, net) —— 按端点匹配 +DEL_SEGS = [ + (2, 88.331, 32.565, 88.75, 30.015, 'VO'), # 13 脚的斜线 -> 换成 12-13 短接 + (2, 89.25, 30.015, 89.25, 30.77, 'EFUSE_EN'), + (2, 89.25, 30.77, 89.5, 31.0, 'EFUSE_EN'), + (1, 89.5, 32.0, 89.5, 31.0, 'EFUSE_EN'), + (1, 81.75, 32.0, 89.5, 32.0, 'EFUSE_EN'), + (2, 91.75, 28.77, 92.0, 29.5, '$1N158'), +] +DEL_VIAS = [(89.5, 31.0, 'EFUSE_EN'), (92.0, 29.5, '$1N158')] +S = [] # (layer, x0,y0,x1,y1, w, net) +V = [] # (x,y,net) +def seg(l, pts, w, net): + for a, b in zip(pts, pts[1:]): + S.append((l, a[0], a[1], b[0], b[1], w, net)) +# ── 让路：VO 12-13 短接、EFUSE_EN 改从 (89.05,32) 上顶层、$1N158 过孔改到 (92,28.77) +seg(2, [(88.25, 30.015), (88.75, 30.015)], 0.3, 'VO') +seg(2, [(89.25, 30.015), (89.25, 31.3), (89.05, 31.5), (89.05, 32.0)], 0.3, 'EFUSE_EN') +V.append((89.05, 32.0, 'EFUSE_EN')) +seg(1, [(89.05, 32.0), (81.75, 32.0)], 0.3, 'EFUSE_EN') +seg(2, [(91.75, 28.77), (92.0, 28.77)], 0.15, '$1N158') +V.append((92.0, 28.77, '$1N158')) +seg(1, [(92.0, 28.77), (92.0, 29.5)], 0.15, '$1N158') +# ── $1N147：U2.15 上逃 -> 顶层 y31.4 向西 -> x66.9 下来 -> y28.35 向东 -> 过孔落到 R9.2 上方 +seg(2, [(89.751, 30.015), (89.75, 31.1), (90.05, 31.4), (90.6, 31.4)], W, '$1N147') +V.append((90.6, 31.4, '$1N147')) +seg(1, [(90.6, 31.4), (66.9, 31.4), (66.9, 28.35), (77.0, 28.35)], W, '$1N147') +V.append((77.0, 28.35, '$1N147')) +seg(2, [(77.0, 28.35), (77.2, 27.62)], W, '$1N147') +# ── $1N156：U2.17 东逃 -> 过孔 (92.65,29.27) -> 顶层下到 y26.6 -> 西到 84.6 -> y25.75 -> 过孔 (81.3,25.75) -> 底层进 R11.1 +seg(2, [(91.001, 29.266), (92.65, 29.27)], W, '$1N156') +V.append((92.65, 29.27, '$1N156')) +seg(1, [(92.65, 29.27), (92.65, 26.6), (84.6, 26.6), (84.6, 25.75), (81.3, 25.75)], W, '$1N156') +V.append((81.3, 25.75, '$1N156')) +seg(2, [(81.3, 25.75), (81.3, 26.9), (82.0, 27.35), (82.33, 27.35)], W, '$1N156') +# ── EFUSE_PG：U2.2 下逃 -> 过孔 (90.25,25.4) -> 顶层 y25.4 西到 86.6 -> 过孔 -> 底层绕 +3V3 孔 -> x80.6 南下 -> U4.16 +seg(2, [(89.751, 27.015), (89.75, 26.55), (90.1, 26.2), (90.25, 26.05), (90.25, 25.4)], W, 'EFUSE_PG') +V.append((90.25, 25.4, 'EFUSE_PG')) +seg(1, [(90.25, 25.4), (86.6, 25.4)], W, 'EFUSE_PG') +V.append((86.6, 25.4, 'EFUSE_PG')) +seg(2, [(86.6, 25.4), (84.8, 25.4), (84.6, 25.55), (83.0, 25.55), (82.55, 25.1), (80.6, 25.1), (80.6, 20.2), (80.15, 20.2)], W, 'EFUSE_PG') +# ── $1N165：R16.1 北侧过孔 (79.1,29.95) -> 顶层 y29.95 东到 93.3 -> 南到 24.6 -> 西到 88.9 -> 过孔 -> Rs1.2 +seg(2, [(79.33, 29.62), (79.1, 29.95)], W, '$1N165') +V.append((79.1, 29.95, '$1N165')) +seg(1, [(79.1, 29.95), (93.3, 29.95), (93.3, 24.6), (88.9, 24.6)], W, '$1N165') +V.append((88.9, 24.6, '$1N165')) +seg(2, [(88.9, 24.6), (88.5, 24.4)], W, '$1N165') +# ── VDAC：金手指引出点 (49.5,11.75) 底层北上 -> 绕过尾插槽西侧 x46 -> 过孔 (46.3,29) -> 顶层北上 -> y45.55/45.8 东行 -> x96.6 南下 -> 过孔 (94.5,49.85) -> R8.2 +seg(2, [(49.5, 11.75), (49.5, 21.0), (46.3, 21.0), (46.3, 29.0)], W, 'VDAC') +V.append((46.3, 29.0, 'VDAC')) +seg(1, [(46.3, 29.0), (46.3, 45.55), (82.5, 45.55), (82.9, 45.8), (96.6, 45.8), (96.6, 49.85), (94.5, 49.85)], W, 'VDAC') +V.append((94.5, 49.85, 'VDAC')) +seg(2, [(94.5, 49.85), (93.785, 49.85)], W, 'VDAC') diff --git a/.claude/r2/_m6_pf.log b/.claude/r2/_m6_pf.log new file mode 100644 index 0000000..6fceb49 --- /dev/null +++ b/.claude/r2/_m6_pf.log @@ -0,0 +1,71 @@ +板上已有过孔 471 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） + PF 第 1 轮：冲突格点 1005，没布通 3（present=1.0） + PF 第 2 轮：冲突格点 824，没布通 3（present=1.2） + PF 第 3 轮：冲突格点 726，没布通 3（present=1.6） + PF 第 4 轮：冲突格点 701，没布通 3（present=2.0） + PF 第 5 轮：冲突格点 621，没布通 3（present=2.4） + PF 第 6 轮：冲突格点 577，没布通 3（present=3.1） + PF 第 7 轮：冲突格点 549，没布通 3（present=3.8） + PF 第 8 轮：冲突格点 527，没布通 3（present=4.8） + PF 第 9 轮：冲突格点 514，没布通 3（present=6.0） + PF 第 10 轮：冲突格点 580，没布通 3（present=7.5） + PF 第 11 轮：冲突格点 496，没布通 3（present=9.3） + PF 第 12 轮：冲突格点 549，没布通 3（present=11.6） + PF 第 13 轮：冲突格点 570，没布通 3（present=14.6） + PF 第 14 轮：冲突格点 553，没布通 3（present=18.2） + PF 第 15 轮：冲突格点 549，没布通 3（present=22.7） + PF 第 16 轮：冲突格点 555，没布通 3（present=28.4） + PF 第 17 轮：冲突格点 544，没布通 3（present=35.5） + PF 第 18 轮：冲突格点 545，没布通 3（present=44.4） + PF 第 19 轮：冲突格点 535，没布通 3（present=55.5） + PF 第 20 轮：冲突格点 628，没布通 3（present=69.4） + PF 第 21 轮：冲突格点 595，没布通 3（present=86.7） + PF 第 22 轮：冲突格点 617，没布通 3（present=108.4） + PF 第 23 轮：冲突格点 584，没布通 3（present=135.5） + PF 第 24 轮：冲突格点 600，没布通 3（present=169.4） + PF 第 25 轮：冲突格点 610，没布通 3（present=211.8） + PF 第 26 轮：冲突格点 601，没布通 3（present=264.7） + PF 第 27 轮：冲突格点 602，没布通 3（present=330.9） + PF 第 28 轮：冲突格点 608，没布通 3（present=413.6） + PF 第 29 轮：冲突格点 606，没布通 3（present=517.0） + PF 第 30 轮：冲突格点 599，没布通 3（present=646.2） + 精确几何：真违规涉及 7 个网 —— $1N128 $1N131 $1N135 +5V USB_DM VDAC VO +线宽被焊盘封顶: VO 1.50→0.30 +5V 0.60→0.60 +同网过孔合并 2 个（中心距 < 0.60 mm） + 第 1 轮：31 条没搞定 +导线 748 段 / 总长 2104.8 mm / 过孔 264 +涉及 51 个网络 +[!] 31 条没搞定: + +3V3: R40.2 没布通 + EFUSE_PG: R15.1 没布通 + EFUSE_PG: U2.2 出不来 + SDA: U4.23 没布通 + SDA: J1.launch 没布通 + INA_ALERT: U3.3 没布通 + EDL_EN: U4.7 没布通 + $1N147: U2.15 出不来 + KEY_VDN: U4.6 没布通 + $1N165: R16.1 没布通 + CC1: J4.22 没布通 + $1N156: U2.17 没布通 + $1N128: U1.1 没布通 + $1N131: U1.8 没布通 + VDAC: J1.launch 没布通 + USB_DM: U7.6 没布通 + [连通性] VO: 铜分成 2 块 + [连通性] $1N131: U1.8 一根铜都没有 + [连通性] +3V3: R40.2 一根铜都没有 + [连通性] VDAC: R8.2 一根铜都没有 + [连通性] SDA: U4.23 一根铜都没有 + [连通性] USB_DM: U7.6 一根铜都没有 + [连通性] CC1: J4.22 R64.1 一根铜都没有 + [连通性] $1N128: R3.2 U1.1 一根铜都没有 + [连通性] $1N147: U2.15 一根铜都没有 + [连通性] $1N156: R11.1 U2.17 一根铜都没有 + [连通性] EFUSE_PG: R15.1 U2.2 U4.16 一根铜都没有 + [连通性] $1N165: R16.1 一根铜都没有 + [连通性] KEY_VDN: R46.2 U4.6 一根铜都没有 + [连通性] EDL_EN: U4.7 一根铜都没有 + [连通性] INA_ALERT: U3.3 U4.15 一根铜都没有 +exit 0 diff --git a/.claude/r2/_m6_repair.json b/.claude/r2/_m6_repair.json new file mode 100644 index 0000000..7dc6fdc --- /dev/null +++ b/.claude/r2/_m6_repair.json @@ -0,0 +1 @@ +{"segs": [[2, 51.75, 38.0, 51.75, 37.5, 0.49, "VBUS"], [1, 53.25, 39.0, 53.25, 39.75, 0.49, "VBUS"], [2, 51.75, 37.5, 51.75, 37.25, 0.49, "VBUS"], [1, 51.75, 37.25, 51.75, 37.0, 0.49, "VBUS"], [1, 51.75, 37.0, 49.25, 37.0, 0.49, "VBUS"], [1, 50.0, 37.0, 50.0, 33.75, 0.49, "VBUS"], [1, 53.25, 39.5, 55.25, 39.5, 0.49, "VBUS"], [1, 55.25, 39.5, 55.25, 39.25, 0.49, "VBUS"], [1, 55.25, 39.25, 60.75, 39.25, 0.49, "VBUS"], [1, 60.75, 39.25, 60.75, 39.0, 0.49, "VBUS"], [1, 60.75, 39.0, 61.75, 39.0, 0.49, "VBUS"], [1, 61.75, 39.0, 61.75, 37.5, 0.49, "VBUS"], [2, 61.75, 37.5, 61.75, 37.0, 0.49, "VBUS"], [2, 52.601, 38.25, 51.75, 38.0, 0.49, "VBUS"], [2, 52.601, 37.3, 51.75, 37.5, 0.49, "VBUS"], [2, 52.601, 38.25, 53.25, 39.0, 0.49, "VBUS"], [2, 53.198, 40.35, 53.25, 39.75, 0.49, "VBUS"], [2, 49.266, 36.586, 49.25, 37.0, 0.49, "VBUS"], [2, 50.551, 33, 50.0, 33.75, 0.49, "VBUS"], [2, 62.301, 36.35, 61.75, 37.0, 0.49, "VBUS"], [2, 86.75, 38.0, 86.75, 37.25, 0.3, "VO"], [2, 89.25, 38.0, 89.25, 34.75, 0.3, "VO"], [2, 89.25, 34.75, 89.0, 34.75, 0.3, "VO"], [1, 89.0, 34.75, 87.5, 34.75, 0.3, "VO"], [2, 90.75, 40.5, 90.75, 43.5, 0.3, "VO"], [2, 90.75, 43.5, 91.0, 43.5, 0.3, "VO"], [2, 91.0, 43.5, 91.0, 44.0, 0.3, "VO"], [1, 91.0, 44.0, 93.0, 44.0, 0.3, "VO"], [1, 88.25, 34.75, 88.25, 33.25, 0.3, "VO"], [1, 88.25, 33.25, 86.25, 33.25, 0.3, "VO"], [1, 86.25, 33.25, 86.25, 32.75, 0.3, "VO"], [2, 86.25, 32.75, 86.25, 31.0, 0.3, "VO"], [1, 86.25, 31.0, 88.0, 31.0, 0.3, "VO"], [1, 88.0, 31.0, 88.25, 31.0, 0.3, "VO"], [1, 88.25, 31.0, 88.25, 30.75, 0.3, "VO"], [1, 88.25, 30.75, 87.75, 30.75, 0.3, "VO"], [1, 87.75, 30.75, 87.25, 30.75, 0.3, "VO"], [1, 87.25, 30.75, 87.25, 30.25, 0.3, "VO"], [2, 87.25, 30.25, 87.25, 29.75, 0.3, "VO"], [2, 87.25, 29.75, 86.75, 29.75, 0.3, "VO"], [2, 86.75, 29.75, 86.25, 29.25, 0.3, "VO"], [1, 86.25, 31.0, 84.0, 31.0, 0.3, "VO"], [2, 84.0, 31.0, 84.0, 26.5, 0.3, "VO"], [1, 84.0, 26.5, 77.25, 26.5, 0.3, "VO"], [1, 77.25, 26.5, 77.25, 26.75, 0.3, "VO"], [1, 77.25, 26.75, 76.25, 26.75, 0.3, "VO"], [2, 88.75, 39.276, 86.75, 38.0, 0.3, "VO"], [2, 87.158, 36.759, 86.75, 37.25, 0.3, "VO"], [2, 88.75, 39.276, 89.25, 38.0, 0.3, "VO"], [2, 87.158, 34.379, 87.5, 34.75, 0.3, "VO"], [2, 88.75, 39.276, 90.75, 40.5, 0.3, "VO"], [2, 93.632, 43.851, 93.0, 44.0, 0.3, "VO"], [2, 88.331, 32.565, 88.25, 33.25, 0.3, "VO"], [2, 88.75, 30.015, 88.75, 30.7645, 0.3, "VO"], [2, 88.75, 30.7645, 88.0, 31.0, 0.3, "VO"], [2, 88.25, 30.015, 88.25, 30.75, 0.3, "VO"], [2, 87.749, 30.015, 87.75, 30.75, 0.3, "VO"], [2, 87, 29.266, 87.25, 29.75, 0.3, "VO"], [2, 87, 28.765, 86.2505, 28.765, 0.3, "VO"], [2, 86.2505, 28.765, 86.25, 29.25, 0.3, "VO"], [2, 76.332, 27.351, 76.25, 26.75, 0.3, "VO"], [2, 87.25, 25.0, 87.25, 26.25, 0.3, "$1N165"], [2, 87.25, 26.25, 87.75, 26.25, 0.3, "$1N165"], [2, 87.75, 26.25, 88.25, 26.25, 0.3, "$1N165"], [2, 87.25, 26.25, 87.25, 27.25, 0.3, "$1N165"], [1, 87.0, 21.0, 85.5, 21.0, 0.3, "$1N165"], [1, 85.5, 21.0, 85.5, 20.25, 0.3, "$1N165"], [2, 87.25, 27.25, 86.75, 27.25, 0.3, "$1N165"], [2, 86.75, 27.25, 86.25, 27.75, 0.3, "$1N165"], [2, 87.866, 23.035, 87.25, 25.0, 0.3, "$1N165"], [2, 87.749, 27.015, 87.25, 26.25, 0.3, "$1N165"], [2, 88.25, 27.015, 88.25, 26.2655, 0.3, "$1N165"], [2, 88.25, 26.2655, 87.75, 26.25, 0.3, "$1N165"], [2, 88.75, 27.015, 88.75, 26.2655, 0.3, "$1N165"], [2, 88.75, 26.2655, 88.25, 26.25, 0.3, "$1N165"], [2, 87, 27.765, 87.25, 27.25, 0.3, "$1N165"], [2, 87.866, 23.035, 87.0, 21.0, 0.3, "$1N165"], [2, 85.049, 19.096, 85.5, 20.25, 0.279, "$1N165"], [2, 87, 28.265, 86.2505, 28.265, 0.3, "$1N165"], [2, 86.2505, 28.265, 86.25, 27.75, 0.3, "$1N165"], [1, 82.75, 18.0, 85.75, 18.0, 0.279, "+3V3"], [1, 85.25, 18.0, 85.25, 15.25, 0.279, "+3V3"], [1, 85.25, 15.25, 83.5, 15.25, 0.279, "+3V3"], [1, 83.5, 15.25, 83.5, 14.75, 0.279, "+3V3"], [1, 83.5, 14.75, 80.5, 14.75, 0.279, "+3V3"], [2, 83.0, 20.25, 83.0, 25.0, 0.279, "+3V3"], [1, 83.0, 25.0, 79.25, 25.0, 0.279, "+3V3"], [1, 83.0, 25.0, 93.0, 25.0, 0.279, "+3V3"], [1, 93.0, 25.0, 93.0, 30.5, 0.279, "+3V3"], [1, 93.0, 30.5, 91.5, 30.5, 0.279, "+3V3"], [2, 91.5, 30.5, 91.5, 38.0, 0.279, "+3V3"], [2, 91.5, 38.0, 91.25, 38.25, 0.279, "+3V3"], [1, 91.25, 38.25, 90.0, 38.25, 0.279, "+3V3"], [1, 90.0, 38.25, 90.0, 38.75, 0.279, "+3V3"], [1, 90.0, 38.75, 86.25, 38.75, 0.279, "+3V3"], [1, 86.25, 38.75, 86.25, 40.5, 0.279, "+3V3"], [2, 86.25, 40.5, 86.25, 42.25, 0.279, "+3V3"], [1, 86.25, 42.25, 78.75, 42.25, 0.279, "+3V3"], [2, 78.75, 42.25, 78.75, 36.75, 0.279, "+3V3"], [1, 78.75, 36.75, 72.0, 36.75, 0.279, "+3V3"], [2, 72.0, 36.75, 72.0, 29.25, 0.279, "+3V3"], [1, 72.0, 29.25, 73.0, 29.25, 0.279, "+3V3"], [1, 73.0, 29.25, 73.0, 29.0, 0.279, "+3V3"], [1, 73.0, 29.0, 74.75, 29.0, 0.279, "+3V3"], [2, 74.75, 29.0, 74.75, 28.0, 0.279, "+3V3"], [2, 74.75, 28.0, 75.0, 27.75, 0.279, "+3V3"], [2, 75.0, 27.75, 75.0, 26.75, 0.279, "+3V3"], [1, 75.0, 26.75, 75.0, 26.0, 0.279, "+3V3"], [1, 75.0, 26.0, 72.25, 26.0, 0.279, "+3V3"], [1, 72.0, 31.0, 80.25, 31.0, 0.279, "+3V3"], [1, 80.25, 31.0, 80.75, 31.0, 0.279, "+3V3"], [1, 80.75, 31.0, 80.75, 31.25, 0.279, "+3V3"], [2, 80.75, 31.25, 80.75, 32.75, 0.279, "+3V3"], [1, 72.0, 36.75, 71.5, 36.75, 0.279, "+3V3"], [1, 71.5, 36.75, 71.5, 37.25, 0.279, "+3V3"], [1, 71.5, 37.25, 69.5, 37.25, 0.279, "+3V3"], [1, 69.5, 37.25, 69.5, 37.75, 0.279, "+3V3"], [1, 69.5, 37.75, 68.5, 37.75, 0.279, "+3V3"], [1, 68.5, 37.75, 68.5, 38.25, 0.279, "+3V3"], [1, 68.5, 38.25, 69.75, 38.25, 0.279, "+3V3"], [1, 69.75, 38.25, 69.75, 40.75, 0.279, "+3V3"], [1, 72.0, 31.0, 50.0, 31.0, 0.279, "+3V3"], [1, 50.0, 31.0, 50.0, 30.75, 0.279, "+3V3"], [1, 50.0, 30.75, 46.5, 30.75, 0.279, "+3V3"], [1, 46.5, 30.75, 46.5, 29.25, 0.279, "+3V3"], [1, 46.5, 29.25, 41.75, 29.25, 0.279, "+3V3"], [2, 41.75, 29.25, 41.75, 29.0, 0.279, "+3V3"], [2, 41.75, 29.0, 41.5, 28.75, 0.279, "+3V3"], [2, 41.5, 28.75, 41.5, 12.25, 0.279, "+3V3"], [2, 41.5, 12.25, 41.5, 12.0, 0.279, "+3V3"], [2, 41.5, 12.0, 41.0, 12.0, 0.279, "+3V3"], [2, 41.0, 12.0, 40.0, 12.0, 0.279, "+3V3"], [2, 83.05, 19.096, 82.75, 18.0, 0.279, "+3V3"], [2, 86.38, 18.001, 85.75, 18.0, 0.279, "+3V3"], [2, 79.322, 14.925, 80.5, 14.75, 0.279, "+3V3"], [2, 83.05, 19.096, 83.0, 20.25, 0.279, "+3V3"], [2, 78.697, 25.451, 79.25, 25.0, 0.279, "+3V3"], [2, 72.301, 25.451, 72.25, 26.0, 0.279, "+3V3"], [2, 80.198, 31.351, 80.25, 31.0, 0.279, "+3V3"], [2, 76.332, 31.351, 75.75, 31.0, 0.279, "+3V3"], [2, 80.833, 33.35, 80.75, 32.75, 0.279, "+3V3"], [2, 67.701, 38.199, 68.5, 38.25, 0.279, "+3V3"], [2, 70.399, 41.25, 69.75, 40.75, 0.279, "+3V3"], [2, 41.5, 11.75, 41.5, 12.25, 0.279, "+3V3"], [2, 40.5, 11.75, 41.0, 12.0, 0.279, "+3V3"], [2, 39.5, 11.75, 40.0, 12.0, 0.279, "+3V3"], [2, 78.75, 26.75, 77.75, 26.75, 0.15, "$1N147"], [2, 79.332, 27.351, 78.75, 26.75, 0.15, "$1N147"], [2, 77.198, 27.351, 77.75, 26.75, 0.15, "$1N147"], [2, 74.5, 25.0, 74.5, 23.25, 0.15, "SDA"], [1, 74.5, 23.25, 76.25, 23.25, 0.15, "SDA"], [2, 76.25, 23.25, 76.25, 19.25, 0.15, "SDA"], [2, 76.25, 19.25, 76.5, 19.25, 0.15, "SDA"], [2, 76.5, 19.25, 76.5, 16.75, 0.15, "SDA"], [2, 76.5, 16.75, 76.25, 16.75, 0.15, "SDA"], [2, 76.25, 16.75, 76.25, 14.75, 0.15, "SDA"], [1, 76.25, 14.75, 78.0, 14.75, 0.15, "SDA"], [2, 78.0, 14.75, 78.25, 15.0, 0.15, "SDA"], [2, 78.25, 15.0, 78.25, 15.5, 0.15, "SDA"], [1, 78.0, 14.75, 79.25, 14.75, 0.15, "SDA"], [1, 79.25, 14.75, 79.25, 13.75, 0.15, "SDA"], [1, 79.25, 13.75, 83.5, 13.75, 0.15, "SDA"], [1, 83.5, 13.75, 83.5, 13.5, 0.15, "SDA"], [2, 83.5, 13.5, 83.5, 13.75, 0.15, "SDA"], [1, 76.25, 19.25, 72.75, 19.25, 0.15, "SDA"], [1, 72.75, 19.25, 72.75, 19.0, 0.15, "SDA"], [1, 72.75, 19.0, 53.75, 19.0, 0.15, "SDA"], [2, 53.75, 19.0, 53.75, 22.0, 0.15, "SDA"], [2, 53.75, 22.0, 50.25, 22.0, 0.15, "SDA"], [2, 50.25, 22.0, 50.25, 19.0, 0.15, "SDA"], [1, 50.25, 19.0, 39.0, 19.0, 0.15, "SDA"], [2, 39.0, 19.0, 39.0, 12.75, 0.15, "SDA"], [2, 39.0, 12.75, 38.5, 12.75, 0.15, "SDA"], [2, 38.5, 12.75, 38.5, 12.0, 0.15, "SDA"], [2, 38.5, 12.0, 38.0, 12.0, 0.15, "SDA"], [2, 74.831, 25.451, 74.5, 25.0, 0.15, "SDA"], [2, 79.322, 15.575, 78.25, 15.5, 0.15, "SDA"], [2, 83.551, 14.874, 83.5, 13.75, 0.15, "SDA"], [2, 37.5, 11.75, 38.0, 12.0, 0.15, "SDA"]], "vias": [[53.25, 39.0, "VBUS"], [53.25, 39.75, "VBUS"], [51.75, 37.25, "VBUS"], [49.25, 37.0, "VBUS"], [50.0, 33.75, "VBUS"], [61.75, 37.5, "VBUS"], [89.0, 34.75, "VO"], [87.5, 34.75, "VO"], [91.0, 44.0, "VO"], [93.0, 44.0, "VO"], [88.25, 33.25, "VO"], [86.25, 32.75, "VO"], [86.25, 31.0, "VO"], [88.0, 31.0, "VO"], [88.25, 30.75, "VO"], [87.75, 30.75, "VO"], [87.25, 30.25, "VO"], [84.0, 31.0, "VO"], [84.0, 26.5, "VO"], [76.25, 26.75, "VO"], [87.0, 21.0, "$1N165"], [85.5, 20.25, "$1N165"], [82.75, 18.0, "+3V3"], [85.75, 18.0, "+3V3"], [80.5, 14.75, "+3V3"], [83.0, 25.0, "+3V3"], [79.25, 25.0, "+3V3"], [91.5, 30.5, "+3V3"], [91.25, 38.25, "+3V3"], [86.25, 40.5, "+3V3"], [86.25, 42.25, "+3V3"], [78.75, 42.25, "+3V3"], [78.75, 36.75, "+3V3"], [72.0, 36.75, "+3V3"], [72.0, 29.25, "+3V3"], [74.75, 29.0, "+3V3"], [75.0, 26.75, "+3V3"], [72.25, 26.0, "+3V3"], [72.0, 31.0, "+3V3"], [80.25, 31.0, "+3V3"], [75.75, 31.0, "+3V3"], [80.75, 31.25, "+3V3"], [68.5, 38.25, "+3V3"], [69.75, 40.75, "+3V3"], [41.75, 29.25, "+3V3"], [74.5, 23.25, "SDA"], [76.25, 23.25, "SDA"], [76.25, 14.75, "SDA"], [78.0, 14.75, "SDA"], [83.5, 13.5, "SDA"], [76.25, 19.25, "SDA"], [53.75, 19.0, "SDA"], [50.25, 19.0, "SDA"], [39.0, 19.0, "SDA"]]} \ No newline at end of file diff --git a/.claude/r2/_m6_restore.log b/.claude/r2/_m6_restore.log new file mode 100644 index 0000000..dc720ad --- /dev/null +++ b/.claude/r2/_m6_restore.log @@ -0,0 +1,31 @@ +{'lines': 712, 'vias': 452} +GND 缝合过孔 182 个（5 mm 网格） +{'deleted': 0, 'made': 182, 'now': 182} +（用缓存 _blade_routes.json） +导线 714 段 / 总长 2341.4 mm / 过孔 289 +涉及 56 个网络 +[!] 16 条没搞定: + EFUSE_PG: U2.2 出不来 + $1N147: U2.15 出不来 + $1N165: R16.1 没布通 + $1N156: U2.17 没布通 + VDAC: J1.launch 出不来 + USB_DM: J1.launch 出不来 + [连通性] VO: 铜分成 2 块 + [连通性] VO: 铜分成 2 块 + [连通性] +3V3: 铜分成 3 块 + [连通性] VBUS: 铜分成 2 块 + [连通性] VDAC: R8.2 一根铜都没有 + [连通性] SDA: 铜分成 2 块 + [连通性] $1N147: U2.15 一根铜都没有 + [连通性] $1N156: R11.1 U2.17 一根铜都没有 + [连通性] EFUSE_PG: U2.2 一根铜都没有 + [连通性] $1N165: R16.1 一根铜都没有 + 下发 120 段 / 289 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 114 段 / 0 过孔 + 共 714 段 +exit 0 diff --git a/.claude/r2/_m6_route.log b/.claude/r2/_m6_route.log new file mode 100644 index 0000000..316705c --- /dev/null +++ b/.claude/r2/_m6_route.log @@ -0,0 +1,74 @@ +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: $1N165 1.50→0.30 + 拆线重布第 1 轮：13 -> 13 +同网过孔合并 7 个（中心距 < 0.60 mm） + 第 1 轮：23 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: $1N165 1.50→0.30 + 拆线重布第 1 轮：13 -> 13 +同网过孔合并 7 个（中心距 < 0.60 mm） + 第 2 轮：23 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: $1N165 1.50→0.30 + 拆线重布第 1 轮：13 -> 13 +同网过孔合并 7 个（中心距 < 0.60 mm） + 第 3 轮：23 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: $1N165 1.50→0.30 + 拆线重布第 1 轮：13 -> 13 +同网过孔合并 7 个（中心距 < 0.60 mm） + 第 4 轮：23 条没搞定 +导线 701 段 / 总长 2282.7 mm / 过孔 280 +涉及 54 个网络 +[!] 23 条没搞定: + VO_P: C61.2 找不到落过孔的地方 + VO_P: C62.2 找不到落过孔的地方 + VO_P: C63.2 找不到落过孔的地方 + VO_P: C64.2 找不到落过孔的地方 + VO_P: C65.2 找不到落过孔的地方 + VO_P: J5.1 找不到落过孔的地方 + EFUSE_PG: U2.2 出不来 + $1N147: U2.15 出不来 + KEY_VDN: U4.6 没布通 + $1N156: U2.17 没布通 + VDAC: J1.launch 出不来 + $3N44: J3.1 没布通 + USB_DM: J1.launch 出不来 + [连通性] +3V3: 铜分成 2 块 + [连通性] VO_P: C61.2 C62.2 C63.2 C64.2 一根铜都没有 + [连通性] VBUS: 铜分成 2 块 + [连通性] VDAC: R8.2 一根铜都没有 + [连通性] SDA: 铜分成 2 块 + [连通性] $3N44: J3.1 U6.1 一根铜都没有 + [连通性] $1N147: U2.15 一根铜都没有 + [连通性] $1N156: R11.1 U2.17 一根铜都没有 + [连通性] EFUSE_PG: U2.2 一根铜都没有 + [连通性] KEY_VDN: R46.2 U4.6 一根铜都没有 + 下发 120 段 / 280 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 101 段 / 0 过孔 + 共 701 段 +exit 0 diff --git a/.claude/r2/_m6_route2.log b/.claude/r2/_m6_route2.log new file mode 100644 index 0000000..d6360ba --- /dev/null +++ b/.claude/r2/_m6_route2.log @@ -0,0 +1,74 @@ +{'lines': 730, 'vias': 462} +GND 缝合过孔 182 个（5 mm 网格） +{'deleted': 0, 'made': 182, 'now': 182} +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 + 拆线重布第 1 轮：8 -> 8 +同网过孔合并 5 个（中心距 < 0.60 mm） + 第 1 轮：17 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 + 拆线重布第 1 轮：7 -> 7 +同网过孔合并 6 个（中心距 < 0.60 mm） + 第 2 轮：16 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 + 拆线重布第 1 轮：7 -> 7 +同网过孔合并 6 个（中心距 < 0.60 mm） + 第 3 轮：16 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 $1N165 1.50→0.30 +线宽被焊盘封顶: VO 1.50→0.30 +5V 0.60→0.60 $1N165 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 + 拆线重布第 1 轮：7 -> 7 +同网过孔合并 6 个（中心距 < 0.60 mm） + 第 4 轮：16 条没搞定 +导线 714 段 / 总长 2341.4 mm / 过孔 289 +涉及 56 个网络 +[!] 16 条没搞定: + EFUSE_PG: U2.2 出不来 + $1N147: U2.15 出不来 + $1N165: R16.1 没布通 + $1N156: U2.17 没布通 + VDAC: J1.launch 出不来 + USB_DM: J1.launch 出不来 + [连通性] VO: 铜分成 2 块 + [连通性] VO: 铜分成 2 块 + [连通性] +3V3: 铜分成 3 块 + [连通性] VBUS: 铜分成 2 块 + [连通性] VDAC: R8.2 一根铜都没有 + [连通性] SDA: 铜分成 2 块 + [连通性] $1N147: U2.15 一根铜都没有 + [连通性] $1N156: R11.1 U2.17 一根铜都没有 + [连通性] EFUSE_PG: U2.2 一根铜都没有 + [连通性] $1N165: R16.1 一根铜都没有 + 下发 120 段 / 289 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 114 段 / 0 过孔 + 共 714 段 +exit 0 diff --git a/.claude/r2/_m6_route3.log b/.claude/r2/_m6_route3.log new file mode 100644 index 0000000..99fc70b --- /dev/null +++ b/.claude/r2/_m6_route3.log @@ -0,0 +1,67 @@ +{'lines': 744, 'vias': 471} +GND 缝合过孔 182 个（5 mm 网格） +{'deleted': 0, 'made': 182, 'now': 182} +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +线宽被焊盘封顶: +5V 0.60→0.60 + 拆线重布第 1 轮：9 -> 9 +同网过孔合并 5 个（中心距 < 0.60 mm） + 第 1 轮：20 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 + 拆线重布第 1 轮：10 -> 10 +同网过孔合并 5 个（中心距 < 0.60 mm） + 第 2 轮：21 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +线宽被焊盘封顶: +5V 0.60→0.60 + 拆线重布第 1 轮：9 -> 9 +同网过孔合并 5 个（中心距 < 0.60 mm） + 第 3 轮：20 条没搞定 +板上已有过孔 182 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.50 VO 1.50→0.30 +线宽被焊盘封顶: +5V 0.60→0.60 + 拆线重布第 1 轮：9 -> 9 +同网过孔合并 5 个（中心距 < 0.60 mm） + 第 4 轮：20 条没搞定 +导线 681 段 / 总长 2132.0 mm / 过孔 270 +涉及 54 个网络 +[!] 20 条没搞定: + EFUSE_EN: U2.14 出不来 + $1N164: U2.3 出不来 + USB_DP: J1.launch 出不来 + $1N158: U2.18 出不来 + KEY_VUP: U4.5 出不来 + KEY_VDN: U4.6 出不来 + VO: R9.1 没布通 + $1N131: U1.8 没布通 + USB_DM: J1.launch 出不来 + [连通性] +12V_F: 铜分成 2 块 + [连通性] VO: R9.1 一根铜都没有 + [连通性] $1N131: U1.8 一根铜都没有 + [连通性] +3V3: 铜分成 2 块 + [连通性] $1N158: C14.1 U2.18 一根铜都没有 + [连通性] VBUS: 铜分成 2 块 + [连通性] EFUSE_EN: U2.14 一根铜都没有 + [连通性] EFUSE_PG: 铜分成 2 块 + [连通性] $1N164: U2.3 一根铜都没有 + [连通性] KEY_VUP: R44.2 U4.5 一根铜都没有 + [连通性] KEY_VDN: R46.2 U4.6 一根铜都没有 + 下发 120 段 / 270 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 120 段 / 0 过孔 + 下发 81 段 / 0 过孔 + 共 681 段 +exit 0 diff --git a/.claude/r2/_m6_viafan.log b/.claude/r2/_m6_viafan.log new file mode 100644 index 0000000..32fb08b --- /dev/null +++ b/.claude/r2/_m6_viafan.log @@ -0,0 +1,81 @@ +板上已有过孔 452 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +过孔扇出 23 只脚（U2 U4 U3），落点全在顶层 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 + 拆线重布第 1 轮：17 -> 17 +同网过孔合并 1 个（中心距 < 0.50 mm） + 第 1 轮：33 条没搞定 +板上已有过孔 452 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +过孔扇出 23 只脚（U2 U4 U3），落点全在顶层 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 + 拆线重布第 1 轮：17 -> 17 +同网过孔合并 1 个（中心距 < 0.50 mm） + 第 2 轮：33 条没搞定 +板上已有过孔 452 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +过孔扇出 23 只脚（U2 U4 U3），落点全在顶层 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 + 拆线重布第 1 轮：17 -> 17 +同网过孔合并 1 个（中心距 < 0.50 mm） + 第 3 轮：33 条没搞定 +板上已有过孔 452 个 +直连 31 段（焊盘贴焊盘，A* 的干线口径进不去） +过孔扇出 23 只脚（U2 U4 U3），落点全在顶层 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +5V 0.60→0.60 +线宽被焊盘封顶: +12V_F 0.80→0.28 $1N137 2.00→0.30 VO 1.50→0.30 + 拆线重布第 1 轮：17 -> 17 +同网过孔合并 1 个（中心距 < 0.50 mm） + 第 4 轮：33 条没搞定 +导线 763 段 / 总长 2157.0 mm / 过孔 289 +涉及 56 个网络 +[!] 33 条没搞定: + EFUSE_EN: U2.fan:14 出不来 + SCL: R41.1 没布通 + SCL: U4.fan:22 出不来 + KEY_PWR: U4.fan:4 出不来 + INT#: U4.fan:1 出不来 + EFUSE_FLT: R13.2 没布通 + INA_ALERT: U3.fan:3 没布通 + EDL_EN: U4.fan:7 没布通 + $1N158: U2.fan:18 出不来 + KEY_VUP: U4.fan:5 没布通 + +5V: J2.1 没布通 + +5V: J1.launch 没布通 + +5V: J1.launch 没布通 + VO: U2.9 出不来 + VO: R9.1 没布通 + $1N131: U1.8 没布通 + $3N44: J3.1 没布通 + [连通性] VO: R9.1 U2.9 一根铜都没有 + [连通性] $1N131: U1.8 一根铜都没有 + [连通性] +3V3: 铜分成 3 块 + [连通性] $1N158: C14.1 一根铜都没有 + [连通性] +5V: J2.1 一根铜都没有 + [连通性] VBUS: 铜分成 2 块 + [连通性] EFUSE_EN: 铜分成 2 块 + [连通性] SCL: R41.1 一根铜都没有 + [连通性] SDA: 铜分成 3 块 + [连通性] USB_DM: 铜分成 2 块 + [连通性] $3N44: J3.1 U6.1 一根铜都没有 + [连通性] EFUSE_FLT: R13.2 一根铜都没有 + [连通性] KEY_PWR: R42.2 一根铜都没有 + [连通性] KEY_VUP: R44.2 一根铜都没有 + [连通性] EDL_EN: 铜分成 2 块 + [连通性] INA_ALERT: 铜分成 2 块 +exit 0 diff --git a/.claude/r2/_m9b_route1.log b/.claude/r2/_m9b_route1.log new file mode 100644 index 0000000..c78924f --- /dev/null +++ b/.claude/r2/_m9b_route1.log @@ -0,0 +1,68 @@ +板上已有过孔 646 个；通孔焊盘 24 只（已拆成两层） + 软铺铜 +3V3_HUB 1 块 吸收 9 只脚，区外 12 只（每只一个落点）+ 0 个跨块桥 + 3V3 槽墙 25 块 吸收 15 只槽脚，墙外 32 只 + **一个**落点 (72.0, 109.6) + U32 逃逸扇形：84 段 0.25 mm 细线（东排 10 只 → x=29.0，南排 4 只 → y=57.5） + 五对编号 D±：按构造画了 30 段（不走 A*，见 dp_build） + 差分对 USB6 布了 16 段（A*） + 差分对 USBUP 布了 10 段（A*） +第一相：D± 144 段，底层 D± 走廊封死 1.5 mm +线宽被焊盘封顶: FAN_12V_SW 0.80→0.54 + 第 1 轮：145 条没搞定 +导线 1487 段 / 总长 3066.6 mm（底层 729.3 mm = 24%）/ 过孔 307 +涉及 53 个网络 +差分对实测铜长: + USB1_DP 74.9 mm + USB1_DM 73.3 mm + USB2_DP 56.8 mm + USB2_DM 55.3 mm + USB3_DP 48.5 mm + USB3_DM 45.7 mm + USB4_DP 66.5 mm + USB4_DM 63.3 mm + USB5_DP 84.3 mm + USB5_DM 81.1 mm + USB6_DP 6.6 mm + USB6_DM 47.0 mm + UP_DP 62.5 mm + UP_DM 6.5 mm +[!] 145 条没搞定: + USB6_DP: U20.launch 没布通 + UP_DM: J23.launch 没布通 + VIN_FUSED: Q1.3 出不来 + VIN_FUSED: DZ1.1 出不来 + VIN_FUSED: C1.1 没布通 + +12V: Q3.3 没布通 + +12V: Q3.2 没布通 + +12V: Q3.1 没布通 + +12V: R4.2 出不来 + +12V: C7.2 没布通 + +12V: C731.1 没布通 + +12V: C732.1 没布通 + +12V: R6.2 出不来 + +3V3: R753.1 没布通 + +3V3: R601.1 没布通 + +3V3: R609.1 没布通 + +3V3: R608.1 没布通 + +3V3: R610.1 没布通 + +3V3: R611.1 没布通 + +3V3: R661.1 没布通 + +3V3: R757.1 没布通 + +3V3: R660.1 没布通 + +3V3: U20.2 没布通 + +3V3: R607.1 没布通 + +3V3: C610.1 没布通 + +3V3: R604.1 没布通 + +3V3: C602.2 没布通 + +3V3: R605.1 没布通 + +3V3: U35.24 没布通 + +3V3: R603.1 没布通 + +3V3: C9.2 没布通 + +3V3: R606.1 没布通 + +3V3: R616.1 没布通 + +3V3: R614.1 没布通 + +3V3: U6.15 没布通 + +3V3: C601.2 没布通 + +3V3: R602.1 没布通 + +3V3: C11.1 没布通 + +3V3: C10.2 没布通 + +3V3: C607.1 没布通 diff --git a/.claude/r2/_m9b_route2.log b/.claude/r2/_m9b_route2.log new file mode 100644 index 0000000..65c0b6d --- /dev/null +++ b/.claude/r2/_m9b_route2.log @@ -0,0 +1,68 @@ +板上已有过孔 646 个；通孔焊盘 24 只（已拆成两层） + 软铺铜 +3V3_HUB 1 块 吸收 9 只脚，区外 12 只（每只一个落点）+ 0 个跨块桥 + 3V3 槽墙 25 块 吸收 15 只槽脚，墙外 32 只 + 10 个 WALL 落点（互相不布线） + U32 逃逸扇形：84 段 0.25 mm 细线（东排 10 只 → x=29.0，南排 4 只 → y=57.5） + 五对编号 D±：按构造画了 30 段（不走 A*，见 dp_build） + 差分对 USB6 布了 16 段（A*） + 差分对 USBUP 布了 10 段（A*） +第一相：D± 144 段，底层 D± 走廊封死 1.5 mm +线宽被焊盘封顶: FAN_12V_SW 0.80→0.54 + 第 1 轮：147 条没搞定 +导线 1465 段 / 总长 2940.6 mm（底层 726.4 mm = 25%）/ 过孔 297 +涉及 54 个网络 +差分对实测铜长: + USB1_DP 74.9 mm + USB1_DM 73.3 mm + USB2_DP 56.8 mm + USB2_DM 55.3 mm + USB3_DP 48.5 mm + USB3_DM 45.7 mm + USB4_DP 66.5 mm + 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779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 200, + "[C] DAC63204 x2 —— 5 路调压（U6 = 0x4A / A0->SDA，U7 = 0x4B / A0->SCL）", + 0, + 12 + ], + [ + 45, + 189, + "三处 datasheet 强制要求，图上看不出来但接错就出问题：", + 0, + 12 + ], + [ + 45, + 178, + " 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈", + 0, + 12 + ], + [ + 45, + 167, + " 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 156, + " 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD", + 0, + 12 + ], + [ + 45, + 145, + "内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 806, + "[A] 74HC595 x2 —— 15 路侧键驱动（U21 在前，Q7S 级联到 U22 的 DS）", + 0, + 12 + ], + [ + 45, + 795, + "先移入的位落到 U22.Q7；OE# 上拉 100k，ESP32 复位期间输出高阻", + 0, + 12 + ], + [ + 445, + 790, + "[B] PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）", + 0, + 12 + ], + [ + 445, + 779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 205, + "[C] DAC63204 x2 —— 5 路调压（U6=0x4A / A0->SDA，U7=0x4B / A0->SCL）", + 0, + 12 + ], + [ + 45, + 190, + "三处 datasheet 强制要求，图上看不出来但接错就出问题：", + 0, + 12 + ], + [ + 45, + 175, + " 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈", + 0, + 12 + ], + [ + 45, + 160, + " 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 145, + " 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD", + 0, + 12 + ], + [ + 45, + 130, + "内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 806, + "[A] 74HC595 x2 —— 15 路侧键驱动", + 0, + 12 + ], + [ + 600, + 806, + "[B] PCA9555 输入扩展（地址 0x20）", + 0, + 12 + ], + [ + 45, + 205, + "[C] DAC63204 x2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 190, + "595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。", + 0, + 12 + ], + [ + 45, + 178, + "OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。", + 0, + 12 + ], + [ + 45, + 166, + "PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），", + 0, + 12 + ], + [ + 45, + 154, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 95, + 790, + "[A] 74HC595 x2 —— 15 路侧键驱动", + 0, + 12 + ], + [ + 600, + 785, + "[B] PCA9555 输入扩展（地址 0x20）", + 0, + 12 + ], + [ + 150, + 205, + "[C] DAC63204 x2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 190, + "595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。", + 0, + 12 + ], + [ + 45, + 178, + "OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。", + 0, + 12 + ], + [ + 45, + 166, + "PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），", + 0, + 12 + ], + [ + 45, + 154, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 45, + 806, + "[A] 74HC595 x2 —— 15 路侧键驱动", + 0, + 12 + ], + [ + 600, + 806, + "[B] PCA9555 输入扩展（地址 0x20）", + 0, + 12 + ], + [ + 150, + 205, + "[C] DAC63204 x2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 190, + "595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。", + 0, + 12 + ], + [ + 45, + 175, + "U22.Q7 = HUB_RST，远程复位板载 USB Hub（§21.7）；OE# 高阻时靠 R716 上拉保持不复位。", + 0, + 12 + ], + [ + 45, + 178, + "OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。", + 0, + 12 + ], + [ + 45, + 166, + "PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），", + 0, + 12 + ], + [ + 45, + 154, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 45, + 806, + "【A】74HC595 ×3 的前两片（U21 / U22）—— 侧键驱动 + HUB_RST", + 0, + 12 + ], + [ + 45, + 795, + "链序 U21 → U22 → U33（在 P6-FAN-EDL），SR_CAS / SR_CAS2 级联，整条链 24 位；", + 0, + 12 + ], + [ + 45, + 784, + "SRCLK / RCLK / OE# 三片共用，OE# 上拉 100k ⇒ ESP32 复位期间 24 路输出全部高阻。", + 0, + 12 + ], + [ + 445, + 790, + "【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）", + 0, + 12 + ], + [ + 445, + 779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 205, + "【C】DAC63204 ×2 —— 5 路调压（U6 = 0x4A / A0→SDA，U7 = 0x4B / A0→SCL）", + 0, + 12 + ], + [ + 45, + 190, + "三处 datasheet 强制要求，图上看不出来但接错就出问题：", + 0, + 12 + ], + [ + 45, + 178, + " 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈", + 0, + 12 + ], + [ + 45, + 167, + " 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 156, + " 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD", + 0, + 12 + ], + [ + 45, + 145, + "内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 130, + "通道 2026-09-06 按 PCB 几何重排（§26.18）：U6 = VDAC2 / VDAC4 / VDAC1（都去西半板），", + 0, + 12 + ], + [ + 45, + 119, + "U7 = VDAC3 / VDAC5（都去东半板）。四个通道完全对等，改的只是固件里的通道号。", + 0, + 12 + ], + [ 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142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 95, + 790, + "[A] 74HC595 x2 —— 15 路侧键驱动", + 0, + 12 + ], + [ + 600, + 785, + "[B] PCA9555 输入扩展（地址 0x20）", + 0, + 12 + ], + [ + 150, + 205, + "[C] DAC63204 x2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 190, + "595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。", + 0, + 12 + ], + [ + 45, + 178, + "OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。", + 0, + 12 + ], + [ + 45, + 166, + "PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），", + 0, + 12 + ], + [ + 45, + 154, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 45, + 806, + "[A] 74HC595 x2 —— 15 路侧键驱动", + 0, + 12 + ], + [ + 600, + 806, + "[B] PCA9555 输入扩展（地址 0x20）", + 0, + 12 + ], + [ + 150, + 205, + "[C] DAC63204 x2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 190, + "595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。", + 0, + 12 + ], + [ + 45, + 175, + "U22.Q7 = HUB_RST，远程复位板载 USB Hub（§21.7）；OE# 高阻时靠 R716 上拉保持不复位。", + 0, + 12 + ], + [ + 45, + 178, + "OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。", + 0, + 12 + ], + [ + 45, + 166, + "PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），", + 0, + 12 + ], + [ + 45, + 154, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 142, + "DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。", + 0, + 12 + ], + [ + 45, + 130, + "FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时", + 0, + 12 + ], + [ + 45, + 118, + "100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。", + 0, + 12 + ], + [ + 45, + 806, + "【A】74HC595 ×3 的前两片（U21 / U22）—— 侧键驱动 + HUB_RST", + 0, + 12 + ], + [ + 45, + 795, + "链序 U21 → U22 → U33（在 P6-FAN-EDL），SR_CAS / SR_CAS2 级联，整条链 24 位；", + 0, + 12 + ], + [ + 45, + 784, + "SRCLK / RCLK / OE# 三片共用，OE# 上拉 100k ⇒ ESP32 复位期间 24 路输出全部高阻。", + 0, + 12 + ], + [ + 445, + 790, + "【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）", + 0, + 12 + ], + [ + 445, + 779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 205, + "【C】DAC63204 ×2 —— 5 路调压（U6 = 0x4A / A0→SDA，U7 = 0x4B / A0→SCL）", + 0, + 12 + ], + [ + 45, + 190, + "三处 datasheet 强制要求，图上看不出来但接错就出问题：", + 0, + 12 + ], + [ + 45, + 178, + " 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈", + 0, + 12 + ], + [ + 45, + 167, + " 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 156, + " 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD", + 0, + 12 + ], + [ + 45, + 145, + "内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 130, + "通道 2026-09-06 按 PCB 几何重排（§26.18）：U6 = VDAC2 / VDAC4 / VDAC1（都去西半板），", + 0, + 12 + ], + [ + 45, + 119, + "U7 = VDAC3 / VDAC5（都去东半板）。四个通道完全对等，改的只是固件里的通道号。", + 0, + 12 + ], + [ + 45, + 806, + "【A】74HC595 ×3 的前两片（U21 / U22）", + 0, + 12 + ], + [ + 45, + 795, + "链序 U21 → U22 → U33（在 P6），整条链 24 位；", + 0, + 12 + ], + [ + 45, + 784, + "SRCLK/RCLK/OE# 三片共用，OE# 上拉 100k ⇒ 复位全高阻", + 0, + 12 + ], + [ + 445, + 790, + "【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）", + 0, + 12 + ], + [ + 445, + 779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 205, + "【C】DAC63204 ×2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 194, + "U6 = 0x4A（A0→SDA），U7 = 0x4B（A0→SCL）", + 0, + 12 + ], + [ + 45, + 180, + "三处 datasheet 强制要求，接错也不报错：", + 0, + 12 + ], + [ + 45, + 169, + " 1) FBx 必须接回 OUTx（电压模式的闭环反馈）", + 0, + 12 + ], + [ + 45, + 158, + " 2) CAP 接 2.2uF 到 AGND（LDO 旁路 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 147, + " 3) VREF 空置时 100nF 到地 + 10k 上拉 VDD", + 0, + 12 + ], + [ + 45, + 136, + "内部基准 1.212V，×2 -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 122, + "通道按几何重排（§26.18）：U6 = VDAC2/4/1（去西半板），", + 0, + 12 + ], + [ + 45, + 111, + "U7 = VDAC3/5（去东半板）。四通道对等，只改固件通道号。", + 0, + 12 + ], + [ + 45, + 806, + "【A】（已搬走）74HC595 ×3 与 15 颗按键 MOS 2026-09-06 整窝挪到载板", + 0, + 12 + ], + [ + 45, + 795, + "（载板 C6-KEYS / C4-SITEn，§26.23）。KEY_SER/SRCLK/RCLK/OE#", + 0, + 12 + ], + [ + 45, + 784, + "四根线从 P3 的 ESP32 直接去 P5-BTB 的 J25 北排 3~6 行。", + 0, + 12 + ], + [ + 445, + 790, + "【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）", + 0, + 12 + ], + [ + 445, + 779, + "IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，", + 0, + 12 + ], + [ + 445, + 768, + "固件严禁把 Port0[7] / Port1[7:5] 配成输出。", + 0, + 12 + ], + [ + 45, + 205, + "【C】DAC63204 ×2 —— 5 路调压", + 0, + 12 + ], + [ + 45, + 194, + "U6 = 0x4A（A0→SDA），U7 = 0x4B（A0→SCL）", + 0, + 12 + ], + [ + 45, + 180, + "三处 datasheet 强制要求，接错也不报错：", + 0, + 12 + ], + [ + 45, + 169, + " 1) FBx 必须接回 OUTx（电压模式的闭环反馈）", + 0, + 12 + ], + [ + 45, + 158, + " 2) CAP 接 2.2uF 到 AGND（LDO 旁路 0.5~15uF）", + 0, + 12 + ], + [ + 45, + 147, + " 3) VREF 空置时 100nF 到地 + 10k 上拉 VDD", + 0, + 12 + ], + [ + 45, + 136, + "内部基准 1.212V，×2 -> 满量程 2.424V（不是 2.5V）", + 0, + 12 + ], + [ + 45, + 122, + "通道按几何重排（§26.18）：U6 = VDAC2/4/1（去西半板），", + 0, + 12 + ], + [ + 45, + 111, + "U7 = VDAC3/5（去东半板）。四通道对等，只改固件通道号。", + 0, + 12 + ] + ], + "nRect": 0, + "nPoly": 0 +} \ No newline at end of file diff --git a/.claude/r2/_p6_live.json b/.claude/r2/_p6_live.json new file mode 100644 index 0000000..1ca986d --- /dev/null +++ b/.claude/r2/_p6_live.json @@ -0,0 +1,2511 @@ +{ + "page": "P6-FAN-EDL", + "parts": [ + [ + "Q6", + "AO3400A_C20917", + "AO3400A.1", + 320, + 330, + 0, + false, + "5c88a333de602eb7", + "0819f05c4eef4c71ace90d822a990e87", + [ + [ + "3", + "D", + 330, + 350 + ], + [ + "1", + "G", + 300, + 330 + ], + [ + "2", + "S", + 330, + 310 + ] + ] + ], + [ + "Q8", + "AO3400A_C20917", + "AO3400A.1", + 280, + 560, + 0, + false, + "5c88a333de602eb7", + "0819f05c4eef4c71ace90d822a990e87", + [ + [ + "3", + "D", + 290, + 580 + ], + [ + "1", + "G", + 260, + 560 + ], + [ + "2", + "S", + 290, + 540 + ] + ] + ], + [ + "Q9", + "AO3400A_C20917", + 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EDL_EN", + 0, + 12 + ], + [ + 460, + 786, + "级联在 U22 之后：U22.QH'(9) -> U33.SER(14)，网络名 SR_CAS2。", + 0, + 10 + ], + [ + 460, + 770, + "整条链变成 24 位，先移入的字节落到 U33。SRCLK / RCLK / OE# 与前两片共用。", + 0, + 10 + ], + [ + 460, + 754, + "QA~QE = EDL_EN1~5；QF/QG/QH 备用不接。", + 0, + 10 + ], + [ + 45, + 340, + "【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）", + 0, + 12 + ], + [ + 45, + 318, + "Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，", + 0, + 10 + ], + [ + 45, + 302, + "少了它 MOS 会被反峰打穿。FAN_PWM = IO47，FAN_TACH = IO48。", + 0, + 10 + ], + [ + 45, + 286, + "5 个 TACH 并联做线或，停一个频率掉约 1/5（分不出是哪一个）。", + 0, + 10 + ], + [ + 45, + 262, + "TACH 必须分压：低边 PWM 关断时风扇地被抬到 12V，TACH 是集电极", + 0, + 10 + ], + [ + 45, + 246, + "开路，也跟着到 12V —— 直连 IO48 会打穿 ESP32。", + 0, + 10 + ], + [ + 45, + 230, + "10k 上拉到 12V + 10k/3.3k 分压 -> IO48 最高 2.98V。关断期间读到", + 0, + 10 + ], + [ + 45, + 214, + "稳定高电平（测不到转速），导通期间才有脉冲 —— 这是低边调速的", + 0, + 10 + ], + [ + 45, + 198, + "固有限制，不是接线错。", + 0, + 10 + ], + [ + 45, + 174, + "EDL_EN 的 100k 下拉不放这一页 —— 跟按键 MOS 栅极一样，放在载板", + 0, + 10 + ], + [ + 45, + 158, + "上紧挨模拟开关（§8.1 复位安全）。", + 0, + 10 + ], + [ + 45, + 134, + "风扇电流 4x0.10 + 1x0.30 = 0.70A @12V；12V 预算 7.6 -> 8.3A，10A 适配器仍有余量。", + 0, + 10 + ], + [ + 45, + 118, + "风扇座 KF2510-3A：pin1 = +12V，pin2 = 风扇回流（MOS 漏极），pin3 = TACH。", + 0, + 10 + ], + [ + 460, + 806, + "【A】第三片 74HC595（U33）—— 5 路 EDL_EN", + 0, + 12 + ], + [ + 460, + 786, + "级联在 U22 之后：U22.QH'(9) -> U33.SER(14)，网络名 SR_CAS2。", + 0, + 10 + ], + [ + 460, + 770, + "整条链变成 24 位，先移入的字节落到 U33。SRCLK / RCLK / OE# 与前两片共用。", + 0, + 10 + ], + [ + 460, + 754, + "QA~QE = EDL_EN1~5；QF/QG/QH 备用不接。", + 0, + 10 + ], + [ + 45, + 340, + "【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）", + 0, + 12 + ], + [ + 45, + 318, + "Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，", + 0, + 10 + ], + [ + 45, + 302, + "少了它 MOS 会被反峰打穿。FAN_PWM = IO47，FAN_TACH = IO48。", + 0, + 10 + ], + [ + 45, + 286, + "5 个 TACH 并联做线或，停一个频率掉约 1/5（分不出是哪一个）。", + 0, + 10 + ], + [ + 45, + 262, + "TACH 必须分压：低边 PWM 关断时风扇地被抬到 12V，TACH 是集电极", + 0, + 10 + ], + [ + 45, + 246, + "开路，也跟着到 12V —— 直连 IO48 会打穿 ESP32。", + 0, + 10 + ], + [ + 45, + 230, + "10k 上拉到 12V + 10k/3.3k 分压 -> IO48 最高 2.98V。关断期间读到", + 0, + 10 + ], + [ + 45, + 214, + "稳定高电平（测不到转速），导通期间才有脉冲 —— 这是低边调速的", + 0, + 10 + ], + [ + 45, + 198, + "固有限制，不是接线错。", + 0, + 10 + ], + [ + 45, + 174, + "EDL_EN 的 100k 下拉不放这一页 —— 跟按键 MOS 栅极一样，放在载板", + 0, + 10 + ], + [ + 45, + 158, + "上紧挨模拟开关（§8.1 复位安全）。", + 0, + 10 + ], + [ + 45, + 134, + "风扇电流 4x0.10 + 1x0.30 = 0.70A @12V；12V 预算 7.6 -> 8.3A，10A 适配器仍有余量。", + 0, + 10 + ], + [ + 45, + 118, + "风扇座 KF2510-3A：pin1 = +12V，pin2 = 风扇回流（MOS 漏极），pin3 = TACH。", + 0, + 10 + ], + [ + 45, + 806, + "【A】第三片 74HC595（U33）—— CH2 / CH3 的六个侧键 + EDL_EN1 + HUB_RST", + 0, + 12 + ], + [ + 45, + 790, + "级联在 U22 之后：U22.QH'(9) -> U33.SER(14)，网络名 SR_CAS2，整条链 24 位。", + 0, + 12 + ], + [ + 45, + 774, + "2026-09-06 按 PCB 几何重排（§26.18）：U33 在 y≈70 mm，正对北排的 CH2 / CH3，", + 0, + 12 + ], + [ + 45, + 758, + "比原来从 U21(y≈50) 拉过去近 20~30 mm。Q0=EDL_EN1，Q1~Q3=K2，Q4~Q6=K3，Q7=HUB_RST。", + 0, + 12 + ], + [ + 45, + 742, + "EDL_EN 与按键的 100k 下拉不放这一页 —— 放在载板上紧挨模拟开关（§8.1 复位安全）。", + 0, + 12 + ], + [ + 45, + 520, + "【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）", + 0, + 12 + ], + [ + 45, + 500, + "Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，", + 0, + 12 + ], + [ + 45, + 484, + "少了它 MOS 会被反峰打穿。FAN_PWM = IO18（模块脚 11），FAN_TACH = IO16（模块脚 9）。", + 0, + 12 + ], + [ + 45, + 468, + "5 个 TACH 并联做线或，停一个频率掉约 1/5（分不出是哪一个）。", + 0, + 12 + ], + [ + 45, + 444, + "TACH 必须分压：低边 PWM 关断时风扇地被抬到 12V，", + 0, + 12 + ], + [ + 45, + 428, + "TACH 是集电极开路，也跟着到 12V —— 直连 GPIO 会打穿 ESP32。", + 0, + 12 + ], + [ + 45, + 412, + "10k 上拉到 12V + 10k/3.3k 分压 -> 最高 2.98V。", + 0, + 12 + ], + [ + 45, + 396, + "关断期间读到稳定高电平（测不到转速），导通期间才有脉冲 ——", + 0, + 12 + ], + [ + 45, + 380, + "这是低边调速的固有限制，不是接线错。", + 0, + 12 + ], + [ + 45, + 175, + "风扇电流 4x0.10 + 1x0.30 = 0.70A @12V；12V 输入预算 7.6 -> 8.3A，10A 适配器仍有余量。", + 0, + 12 + ], + [ + 45, + 159, + "风扇座 2510-3A 直针（C2803349）：pin1 = +12V，pin2 = 风扇回流（MOS 漏极），pin3 = TACH。", + 0, + 12 + ], + [ + 45, + 806, + "【A】第三片 74HC595（U33）—— CH2 / CH3 的六个侧键 + EDL_EN1 + HUB_RST", + 0, + 12 + ], + [ + 45, + 790, + "级联在 U22 之后：U22.QH'(9) -> U33.SER(14)，网络名 SR_CAS2，整条链 24 位。", + 0, + 12 + ], + [ + 45, + 774, + "2026-09-06 按 PCB 几何重排（§26.18）：U33 在 y≈70 mm，正对北排的 CH2 / CH3，", + 0, + 12 + ], + [ + 45, + 758, + "比原来从 U21(y≈50) 拉过去近 20~30 mm。Q0=EDL_EN1，Q1~Q3=K2，Q4~Q6=K3，Q7=HUB_RST。", + 0, + 12 + ], + [ + 45, + 742, + "EDL_EN 与按键的 100k 下拉不放这一页 —— 放在载板上紧挨模拟开关（§8.1 复位安全）。", + 0, + 12 + ], + [ + 45, + 520, + "【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）", + 0, + 12 + ], + [ + 45, + 500, + "Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，", + 0, + 12 + ], + [ + 45, + 484, + "少了它 MOS 会被反峰打穿。FAN_PWM = IO18（模块脚 11），FAN_TACH = IO16（模块脚 9）。", + 0, + 12 + ], + [ + 45, + 468, + "5 个 TACH 并联做线或，停一个频率掉约 1/5（分不出是哪一个）。", + 0, + 12 + ], + [ + 45, + 444, + "TACH 必须分压：低边 PWM 关断时风扇地被抬到 12V，", + 0, + 12 + ], + [ + 45, + 428, + "TACH 是集电极开路，也跟着到 12V —— 直连 GPIO 会打穿 ESP32。", + 0, + 12 + ], + [ + 45, + 412, + "10k 上拉到 12V + 10k/3.3k 分压 -> 最高 2.98V。", + 0, + 12 + ], + [ + 45, + 396, + "关断期间读到稳定高电平（测不到转速），导通期间才有脉冲 ——", + 0, + 12 + ], + [ + 45, + 380, + "这是低边调速的固有限制，不是接线错。", + 0, + 12 + ], + [ + 45, + 190, + "风扇电流 4x0.10 + 1x0.30 = 0.70A @12V；", + 0, + 12 + ], + [ + 45, + 176, + "12V 输入预算 7.6 -> 8.3A，10A 适配器仍有余量。", + 0, + 12 + ], + [ + 45, + 162, + "风扇座 2510-3A 直针（C2803349）：", + 0, + 12 + ], + [ + 45, + 148, + "pin1 = +12V，pin2 = 风扇回流（MOS 漏极），pin3 = TACH。", + 0, + 12 + ], + [ + 45, + 806, + "【A】（已搬走）第三片 74HC595（U33）2026-09-06 随整条链挪到载板 C6-KEYS（§26.23）。", + 0, + 12 + ], + [ + 45, + 790, + "EDL_EN1~5 / HUB_RST 从此是载板内部网络，不再过排针。这一页只剩风扇。", + 0, + 12 + ], + [ + 45, + 520, + "【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）", + 0, + 12 + ], + [ + 45, + 500, + "Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，", + 0, + 12 + ], + [ + 45, + 484, + "少了它 MOS 会被反峰打穿。FAN_PWM = IO18（模块脚 11），FAN_TACH = IO16（模块脚 9）。", + 0, + 12 + ], + [ + 45, + 468, + "5 个 TACH 并联做线或，停一个频率掉约 1/5（分不出是哪一个）。", + 0, + 12 + ], + [ + 45, + 444, + "TACH 必须分压：低边 PWM 关断时风扇地被抬到 12V，", + 0, + 12 + ], + [ + 45, + 428, + "TACH 是集电极开路，也跟着到 12V —— 直连 GPIO 会打穿 ESP32。", + 0, + 12 + ], + [ + 45, + 412, + "10k 上拉到 12V + 10k/3.3k 分压 -> 最高 2.98V。", + 0, + 12 + ], + [ + 45, + 396, + "关断期间读到稳定高电平（测不到转速），导通期间才有脉冲 ——", + 0, + 12 + ], + [ + 45, + 380, + "这是低边调速的固有限制，不是接线错。", + 0, + 12 + ], + [ + 45, + 190, + "风扇电流 4x0.10 + 1x0.30 = 0.70A @12V；", + 0, + 12 + ], + [ + 45, + 176, + "12V 输入预算 7.6 -> 8.3A，10A 适配器仍有余量。", + 0, + 12 + ], + [ + 45, + 162, + "风扇座 2510-3A 直针（C2803349）：", + 0, + 12 + ], + [ + 45, + 148, + "pin1 = +12V，pin2 = 风扇回流（MOS 漏极），pin3 = TACH。", + 0, + 12 + ], + [ + 45, + 190, + "【风扇】FAN-R2：两只 4 线 PWM 风扇，一进一出", + 0, + 12 + ], + [ + 45, + 168, + "型号 山洋 9G0612P4S001 / C2920592。高边默认关电 + 独立 PWM + 两路独立测速。", + 0, + 10 + ], + [ + 45, + 150, + "Q7(AO3401A) 串在 +12V 与 FAN_12V_SW 之间，R746 把栅极拉回源极；", + 0, + 10 + ], + [ + 45, + 132, + "Q8 经 R748 由 FAN_EN(IO5) 驱动，R749 在复位/高阻时拉低 = 默认断电。", + 0, + 10 + ], + [ + 45, + 114, + "DZ3(BZT52C8V2) K 接源极、A 接栅极，钳位负 Vgs（绝对最大 ±12V）。", + 0, + 10 + ], + [ + 45, + 92, + "调速走风扇自己的 PWM 脚(pin4)：Q6 只拉低这根线，不再切风扇回流。", + 0, + 10 + ], + [ + 45, + 74, + "栅极高 = 风扇 PWM 线低，固件必须反相：D_gpio = 1 - D_fan。", + 0, + 10 + ], + [ + 45, + 56, + "0% PWM 风扇仍转约 3300RPM，要停转只能撤 FAN_EN，不能靠占空比。", + 0, + 10 + ], + [ + 45, + 430, + "测速两路独立：TACH 上拉到 FAN_12V_SW，15k/10k 分压驱动 Q9/Q10，", + 0, + 10 + ], + [ + 45, + 412, + "漏极经 10k 上拉到 +3V3 —— 接收电路反相，TACH 低对应 GPIO 高。", + 0, + 10 + ], + [ + 850, + 595, + "风扇座 J26/J27（2510-4A 直针 1x4P）：", + 0, + 10 + ], + [ + 850, + 575, + "1=GND 2=+12V(开关后) 3=TACH 4=PWM", + 0, + 10 + ], + [ + 850, + 555, + "注意：针序与旧的 3 针 J26~J30 不同，装配前对丝印。", + 0, + 10 + ], + [ + 45, + 190, + "【风扇】FAN-R2：两只 4 线 PWM 风扇，一进一出", + 0, + 12 + ], + [ + 45, + 168, + "型号 山洋 9G0612P4S001 / C2920592。高边默认关电 + 独立 PWM + 两路独立测速。", + 0, + 10 + ], + [ + 45, + 150, + "Q7(AO3401A) 串在 +12V 与 FAN_12V_SW 之间，R746 把栅极拉回源极；", + 0, + 10 + ], + [ + 45, + 132, + "Q8 经 R748 由 FAN_EN(IO5) 驱动，R749 在复位/高阻时拉低 = 默认断电。", + 0, + 10 + ], + [ + 45, + 114, + "DZ3(BZT52C8V2) K 接源极、A 接栅极，钳位负 Vgs（绝对最大 ±12V）。", + 0, + 10 + ], + [ + 45, + 92, + "调速走风扇自己的 PWM 脚(pin4)：Q6 只拉低这根线，不再切风扇回流。", + 0, + 10 + ], + [ + 45, + 74, + "栅极高 = 风扇 PWM 线低，固件必须反相：D_gpio = 1 - D_fan。", + 0, + 10 + ], + [ + 45, + 56, + "0% PWM 风扇仍转约 3300RPM，要停转只能撤 FAN_EN，不能靠占空比。", + 0, + 10 + ], + [ + 430, + 300, + "测速两路独立：TACH 上拉到 FAN_12V_SW，15k/10k 分压驱动 Q9/Q10，", + 0, + 10 + ], + [ + 430, + 282, + "漏极经 10k 上拉到 +3V3 —— 接收电路反相，TACH 低对应 GPIO 高。", + 0, + 10 + ], + [ + 850, + 595, + "风扇座 J26/J27（2510-4A 直针 1x4P）：", + 0, + 10 + ], + [ + 850, + 575, + "1=GND 2=+12V(开关后) 3=TACH 4=PWM", + 0, + 10 + ], + [ + 850, + 555, + "注意：针序与旧的 3 针 J26~J30 不同，装配前对丝印。", + 0, + 10 + ] + ], + "nRect": 0, + "nPoly": 0 +} \ No newline at end of file diff --git a/.claude/r2/_pcb_base_m8.py.bak b/.claude/r2/_pcb_base_m8.py.bak new file mode 100644 index 0000000..411c40e --- /dev/null +++ b/.claude/r2/_pcb_base_m8.py.bak @@ -0,0 +1,478 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB（M8）：板框 + 分区 + 插槽阵列 + 安装孔。 + + /c/Python314/python .claude/r2/pcb_base.py # 只算 + 自检 + /c/Python314/python .claude/r2/pcb_base.py --outline # 画/重画板框（幂等） + /c/Python314/python .claude/r2/pcb_base.py --holes # 打安装孔 + /c/Python314/python .claude/r2/pcb_base.py --verify # 读回校验 + +与 `pcb_blade.py` 是同一套接口（`PCB` / `BW` / `BH` / `ZONES` / `mill_cuts()` …）， +下游的 `pcb_place` / `router` / `pcb_pour` 用 `--base` 切到这一份。 + +## 坐标系 + +**板左下角 = (0, 0)，x 向右、y 向上**（EasyEDA PCB 里 y 向上为正，方案 §22.5）。 +x = 槽距方向（5 槽并排），y = 槽长方向 / 板深。方案 §6.5 那张分区图可以直接抄。 + +## ⛔ 板框必须是**折线**不是导线 + +`pcb_PrimitiveLine` 在嘉立创里是**导线（铜）**。M4b~M6 的刀片板框就是这么画的： +渲染成品红、DRC 干净、四道几何校验全过，而客户端根本不认它是板框 +（自动布线一路弹「请先绘制板框！」）。见方案 §27.3。 +⇒ 板框只用 `pcb_PrimitivePolyline`。底板文档里现成那 4 条 `Line`（建工程时的默认框） + 属于同一个坑，`push_outline()` 会把它们删掉。 + +## 刀片投影是硬碰撞，不是净距问题 + +插槽把刀片底边抬到底板上方 ~11 mm ⇒ **投影带内元件 ≤ 8 mm**（方案 §6.6）。 +两颗 470 µF 直立电解、DC-005 座、TH 排针 / 风扇座都只能放到投影带**外面** +（`y < PROJ[0]` 或 `y > PROJ[1]`）。`zone_of()` / `height_ok()` 就是干这个的。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本，先插 .claude 会 import 到 R1 那一份且不报错。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import fp_edge # noqa: E402 + +PCB = '7b9524b6aaf6f235' # BASE-PCB（r2-uuids.json） +MIL = fp_edge.MIL + +# ── 板框（mm，出处 方案 §3.1）───────────────────────────────────────── +BW, BH = 110.0, 125.0 +CORNER_R = 5.0 # 底板四角 R5（刀片是 R2） +CORNER_SEG = 10 +OUTLINE_W = 0.15 + +# ── 插槽阵列（方案 §6.3；槽距 20.32 = T1 定稿）────────────────────────── +SLOT_PITCH = 20.32 +SLOT_N = 5 +SLOT_CX = BW / 2.0 # 阵列中心 = 板中心 = Hub 的 x +SLOT_CY = 64.5 # 槽体中心 y ⇒ 槽体 45.0~84.0（39 mm） +# ⚠ 39 是方案 §3.1 抄的「槽体长度」，**不是封装占的地方**。`PCIE-64P11L` 的焊盘外框 +# 实测 **42.0 × 9.2**（含两端 3.0×5.0 的屏蔽脚 65），转 90° 之后沿 y 占 42、沿 x 占 9.2。 +# 分区就按实测走，别按 39 —— 差的那 3 mm 正好会让槽体啃进 hub / ctrl 两带。 +SLOT_BODY_L = 42.0 # 槽体沿 y（= 转 90° 后的封装长边，实测） +SLOT_BODY_W = 9.2 # 槽体沿 x（实测） +# 焊盘两列：中心 x = 槽心 ± 3.6，盘 2.0(x) × 0.7(y)，即 x 占 ±2.6~±4.6。 +# ⇒ 相邻槽之间的**布线走廊净宽 = 20.32 − 9.2 = 11.12**，两端各剩 9.76。 +PAD_COL_DX = 3.6 +PAD_L, PAD_W = 2.0, 0.7 + +# 刀片投影：刀片 98 宽沿 y 铺开，中心对齐槽体中心 +BLADE_W = 98.0 +PROJ = (round(SLOT_CY - BLADE_W / 2, 2), round(SLOT_CY + BLADE_W / 2, 2)) # 15.5 ~ 113.5 +H_PROJ = 8.0 # 投影带内元件高度上限（方案 §6.6，已留 3 mm 余量） + +# 刀片 x（刀片自身坐标）→ 底板 y 的映射：blade_x = 0 落在投影带下沿。 +# ⇒ 刀片的**功率列**（blade x 72~98，最吵最热）落在 y 87.5~113.5，正对风墙； +# 手机主板（blade x 3~70）落在 y 18.5~85.6。 +def blade_x_to_base_y(bx): + return round(PROJ[0] + bx, 3) + + +def slot_x(i): + u"""槽 i（1~5）的中心 x。""" + return round(SLOT_CX + (i - (SLOT_N + 1) / 2.0) * SLOT_PITCH, 3) + + +def slot_xs(): + return [slot_x(i) for i in range(1, SLOT_N + 1)] + + +# ── 分区（方案 §6.5）────────────────────────────────────────────────── +# ⚠ 'slots' 带内除了 J34~J38 什么都不放：那 39×110 是 D± 走廊 + 槽体本身。 +ZONES = { + 'input': (0.0, 0.0, BW, 15.5), # 投影带外：DC 座 / F1 / Q1 / C2,C3 直立电解 / 泄放 + 'hub': (0.0, 15.5, BW, 43.5), # U32 居中 + Y1 + U31 + 5 个 D± 退路座 + 'slots': (0.0, 43.5, BW, 85.5), # 5 个插槽（42 mm）+ 走廊（L2 一刀不许割） + 'ctrl': (0.0, 85.5, BW, 113.5), # ESP32 / mux / DAC / 3V3 / 5V（全部 ≤8 mm） + 'fan': (0.0, 113.5, BW, BH), # 投影带外：风扇座 / J33 应急口（可高） +} + +# ── 12V 母线（9 A）：**梳子形**，一条脊 + 五根齿 ──────────────────────── +# ⛔ **不能靠布线器的 1.5 mm 线送 9 A**。布线器把 `+12V` 当一个网布成一棵树， +# 树干那一段要背 ~7.5 A 而只有 1.5 mm（1 oz 外层 ΔT20K 只带 3.2 A）， +# DRC / 连通性 / 几何四道判据一条都不会响。⇒ 母线做成铺铜，布线器的线与它并联。 +# +# ⛔ **为什么不是「槽阵南沿一条横杠」**（第一版就是这么画的）： +# 横杠沿 x 送电，而五对 D± 要从 U32 往北**竖着穿过它** —— 两层板上一根竖线 +# 就把横杠**整个切断**，五处切口把它剁成五段，每段还得各自找电。 +# 横杠上的「铜宽够不够」根本不是问题所在，问题是它压根不连通， +# **而铺铜管理器、DRC、断面校核三个都只会告诉你「有铜」。** +# +# ⇒ 改成梳子： +# · `SPINE` 横脊走**输入带最南那 5 mm**（y 0.8~5.8），从 `BUS_IN` 一路往西 +# 钻到 `J1` 的桶身底下。那一条上只有 `J1` 的三只脚（全在 y≥8.2）和板边， +# 南北穿过它的东西一个都没有 —— 它南边就是板边。 +# ⛔ **横脊原来放在 hub 带（y 16.2~24.2），那是错的**：hub 带一共只有 28 mm， +# 横脊一占，`U32` 北边的 D± 扇出带就只剩 8.6 mm，而 +# **10 根 1.2 mm 的线要从 0.5 mm 间距的 QFN 脚上散开到 1.41 mm 间距， +# 光斜着散开就要 4.1 mm**，再加三条车道 8.1 —— 塞不下。 +# 实测现象：内侧那三对（`USB2`/`USB3`/`USB4`）一段都布不出来。 +# 挪到输入带之后 hub 带整条 28 mm 归 `U32`，扇出带 14.6 mm，宽裕。 +# · 五根**支路**从脊往北接各槽的 +12V 针（y 48~50）。它们只有 **1.5 A**， +# 交给布线器画 1.5 mm 的线就够（1 oz 外层 ΔT20K 带 3.2 A），不必铺铜。 +# +# ⛔ **齿曾经也是铺铜，画完才发现走不了**：槽的第 65 脚（屏蔽脚，3.0×5.0，接 GND） +# 正好坐在两列焊盘之间那条 5.2 mm 无盘带的**正中**（转 90° 后 y 43.5~46.5）， +# 把齿从中间堵死 —— 断面校核量出来是 **0.00 mm**。 +# 这是「按封装的焊盘外框想当然」的典型：外框里看着是空的，实际有一只大脚。 +# +# ⚠ `BUS_IN` 西端必须**盖住 `Rs6` 的 +12V 焊盘**（x 63.2~65.2）： +# 不盖住的话，9 A 要靠布线器那根 1.5 mm 的线从分流电阻爬到母线上。 +# ⛔ 脊只能 **5 mm 高**，不是最初画的 8 —— hub 带一共只有 28 mm，要塞下 +# 「脊 + U32(9.75) + 南边逃逸 + 北边 D± 扇出」。第一版 8 mm 的脊把 U32 逼到 y=37， +# 它北沿离插槽焊盘只剩 **1.6 mm**，五对 D± 根本扇不开（布线器实测 USB2 布了 0 段）。 +# 载流上 5 mm 也够：脊上最大电流不是 9 A 而是 ~6 A（进料点在东段 x63~91， +# 往西只带 3 个槽 + 两颗 Buck），1 oz 外层 6 A ΔT20K 要 5.2 mm。 +SPINE = (8.0, 0.8, 91.0, 5.8) # 西端 8.0：让开 H1 螺钉头（0.8~7.2） +BUS_IN = (63.0, 0.8, 91.0, 16.0) # 输入带里的 9 A 母线（15.2 mm 高） + + +def bus_rects(): + return [BUS_IN, SPINE] + + +# ── D± 扇出带：`U32` 北沿到槽体南沿之间那条，**一件都不许放** ───────────── +# 五对 D± 全部在这里分东西两路（USB1/USB2 往东、USB4/USB5 往西、USB3 直上）。 +# 带子 = `U32` 北沿(28.9) 到槽体南沿(43.5) = **14.6 mm**： +# 先要 4.1 mm 让 10 根线从 0.5 mm 的脚距斜着散到 1.41 mm 的线距，再要三条 2.7 的车道。 +# ⛔ 不设这条禁区的实测后果：排布器把 `U32` 的去耦和退路座填满整条带， +# 布线器报「`USB2` 布了 0 段」，而摆位自检 / 朝向断言 / DRC **一条都不响**。 +FANOUT = (2.0, 28.9, 108.0, 43.5) + + +# ── ESP32 天线缺口：西板边挖掉一块，天线整段悬空 ───────────────────────── +# 2026-09-09 用户拍板。**原来的做法是错的**：`U20` 摆在板中央 (17, 96, rot0)、 +# 天线朝北埋在板里，净空只有 20 × 7.5 一小块 ⇒ 天线尖**正前方 1.0 mm 就是 +# 重新铺起来的整块地平面**（再往北 3 mm 是风扇带的 RT601/RT602）， +# 东西两侧净空也只比模组宽 0.5 mm。等于给天线加了块反射板。 +# 而设计文档 §PCB 要点写的是「天线区域下方禁止铺铜、禁止走线，**模组放板边**」—— +# 后半条从来没做到，前半条也只做了「下方那一小块」。 +# ⇒ `U20` 转 **rot=90（天线朝西）**挪到西板边，天线那 7 mm 下方的**板材整块挖掉**。 +# +# 尺寸依据（全部从 `_base_pads.json` 量出来，不是抄封装库）： +# 模组本体 18.0 × 25.5；焊盘外框 19.0 × 19.0（三面出脚，每边比本体宽 0.5） +# ⇒ 天线段 = 25.5 − (19.0 − 0.5×2) = **7.5 mm**（本体 7.0 + 0.5 余量）。 +# 缺口比模组两侧各宽 1.0 mm（y 85~107），深 7.5；`U20` 焊盘西沿 8.5， +# 离缺口边 1.0 mm ⇒ 焊盘还在板上、天线整段在板外，只有天线根部 1 mm 压着无铜的 FR4。 +# ⚠ 内角是铣刀铣出来的，实际会带 Ø2 铣刀的圆角，不必在板框里画圆角。 +ANT_NOTCH = (0.0, 85.0, 7.5, 107.0) + + +def notch_rect(): + u"""天线缺口（板材挖掉的那一块）。板框在这里内凹，不走 `mill_cuts()`。""" + return ANT_NOTCH + + +def keepout_rects(): + u"""摆位禁区（不是铺铜禁区）：12V 母线 + D± 扇出带 + 天线缺口（那儿没板材）。""" + return bus_rects() + [FANOUT, ANT_NOTCH] + + +# ── 安装孔（M3 尼龙立柱，NPTH）──────────────────────────────────────── +# **2026-09-09 用户拍板：只留四角 4 个**（原来还在东西两侧中点加了 H5/H6 当插拔力的支点， +# 用户决定省掉两颗立柱）。⇒ 5 片刀片一起插拔时板中部无支撑，装配时**从槽阵下方托住再插**。 +HOLE_D = 3.2 # M3 过孔 +HOLE_KEEP = 3.2 # 螺钉头 Ø6.0 /2 + 余量 +HOLE_INSET = 4.0 # 孔心离板边 +MOUNT_HOLES = { + 'H1': (HOLE_INSET, HOLE_INSET), + 'H2': (BW - HOLE_INSET, HOLE_INSET), + 'H3': (HOLE_INSET, BH - HOLE_INSET), + 'H4': (BW - HOLE_INSET, BH - HOLE_INSET), +} + +# ── 下游脚本要的空壳（底板没有排线槽 / 手机定位孔 / 金手指缺口）────────── +FLEX_W = {} +SLOT_Y = None +PHONE_ORG = None +PHONE_WH = None + + +def phone_holes(): + u"""下游（`router` / `pcb_place`）拿这个当「两层都不许压的孔」表。 + + 刀片上是手机主板定位孔；底板上没有手机，但四个 M3 安装孔一样不许压 —— + 它们是 `pcb_PrimitivePad` 不是元件引脚，**不在 `_base_pads.json` 里**， + 不从这儿喂进去布线器就会直接从孔上压过去（而 DRC 只报 NPTH 到铜，很晚才看见）。 + """ + return dict(MOUNT_HOLES) + + +def mill_cuts(): + u"""板上铣穿的内槽：底板一个都没有。""" + return [] + + +def notch_break(): + return None + + +def corner(cx, cy, a0, a1): + pts = [] + for k in range(CORNER_SEG + 1): + a = math.radians(a0 + (a1 - a0) * k / CORNER_SEG) + pts.append((cx + CORNER_R * math.cos(a), cy + CORNER_R * math.sin(a))) + return pts + + +def outline_pts(): + u"""板框点列（逆时针，从底边左端 (r,0) 起，闭合回 (r,0)）。 + + ⚠ 相邻重合点必须去掉：零长度线段会被编辑器静默吃掉，读回条数对不上（刀片踩过）。 + """ + r = CORNER_R + pts = [(r, 0.0), (BW - r, 0.0)] + pts += corner(BW - r, r, 270, 360) + pts += [(BW, BH - r)] + pts += corner(BW - r, BH - r, 0, 90) + pts += [(r, BH)] + pts += corner(r, BH - r, 90, 180) + # ESP32 天线缺口：西边从北往南走，走到 y=107 拐进板里 7.5，到 y=85 再拐回来 + pts += [(0.0, ANT_NOTCH[3]), (ANT_NOTCH[2], ANT_NOTCH[3]), + (ANT_NOTCH[2], ANT_NOTCH[1]), (0.0, ANT_NOTCH[1])] + pts += [(0.0, r)] + pts += corner(r, r, 180, 270) + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + assert abs(out[0][0] - out[-1][0]) < 1e-9 and abs(out[0][1] - out[-1][1]) < 1e-9, \ + u'板框点列没有闭合' + return out + + +def outline_polygon(): + return outline_pts() + + +def zone_of(y): + for k, z in ZONES.items(): + if z[1] <= y < z[3]: + return k + return None + + +def height_ok(y, h): + u"""y 处允许 h mm 高的件吗（刀片投影是硬碰撞）。""" + return not (PROJ[0] <= y <= PROJ[1] and h > H_PROJ) + + +def selfcheck(): + bad = [] + xs = slot_xs() + if abs(xs[0] - 14.36) > 0.01 or abs(xs[-1] - 95.64) > 0.01: + bad.append(u'槽阵 x 与方案 §6.3 对不上: %s' % xs) + # 槽体不许出板边 + if xs[0] - SLOT_BODY_W / 2 < 2.0 or xs[-1] + SLOT_BODY_W / 2 > BW - 2.0: + bad.append(u'槽体贴板边太近: %.2f / %.2f' % (xs[0] - SLOT_BODY_W / 2, + xs[-1] + SLOT_BODY_W / 2)) + # 槽体必须整个落在 'slots' 带里 + z = ZONES['slots'] + if abs((SLOT_CY - SLOT_BODY_L / 2) - z[1]) > 0.01 or abs((SLOT_CY + SLOT_BODY_L / 2) - z[3]) > 0.01: + bad.append(u'槽体 y %.1f~%.1f 与 slots 带 %.1f~%.1f 对不上' + % (SLOT_CY - SLOT_BODY_L / 2, SLOT_CY + SLOT_BODY_L / 2, z[1], z[3])) + # 分区必须首尾相接、铺满板 + ks = sorted(ZONES, key=lambda k: ZONES[k][1]) + for a, b in zip(ks, ks[1:]): + if abs(ZONES[a][3] - ZONES[b][1]) > 1e-6: + bad.append(u'分区 %s 顶 %.1f != %s 底 %.1f' % (a, ZONES[a][3], b, ZONES[b][1])) + if abs(ZONES[ks[0]][1]) > 1e-6 or abs(ZONES[ks[-1]][3] - BH) > 1e-6: + bad.append(u'分区没铺满 0~%.1f' % BH) + # 投影带边界必须正好是 input 顶 / fan 底 —— 高件区就是投影带外那两条 + if abs(PROJ[0] - ZONES['input'][3]) > 1e-6 or abs(PROJ[1] - ZONES['fan'][1]) > 1e-6: + bad.append(u'刀片投影 %s 与 input/fan 带边界对不上' % (PROJ,)) + # 安装孔不许压在槽体上，也不许出板 + for n, (hx, hy) in MOUNT_HOLES.items(): + if not (HOLE_KEEP < hx < BW - HOLE_KEEP and HOLE_KEEP < hy < BH - HOLE_KEEP): + bad.append(u'安装孔 %s 出板或贴边: (%.1f, %.1f)' % (n, hx, hy)) + for sx in slot_xs(): + if abs(hx - sx) < SLOT_BODY_W / 2 + HOLE_KEEP and \ + ZONES['slots'][1] - HOLE_KEEP < hy < ZONES['slots'][3] + HOLE_KEEP: + bad.append(u'安装孔 %s 压到槽 x=%.2f' % (n, sx)) + # 四角圆角不许吃掉安装孔 + for n, (hx, hy) in MOUNT_HOLES.items(): + for cx, cy in ((CORNER_R, CORNER_R), (BW - CORNER_R, CORNER_R), + (CORNER_R, BH - CORNER_R), (BW - CORNER_R, BH - CORNER_R)): + out_x = hx < cx if cx < BW / 2 else hx > cx + out_y = hy < cy if cy < BH / 2 else hy > cy + if out_x and out_y and math.hypot(hx - cx, hy - cy) > CORNER_R - HOLE_KEEP: + bad.append(u'安装孔 %s 被 R%.0f 圆角切到' % (n, CORNER_R)) + # 天线缺口：那儿没板材，孔和螺钉头都不许沾（H1/H3 在 x=4，只差 y 就撞上） + for n, (hx, hy) in MOUNT_HOLES.items(): + if (ANT_NOTCH[0] - HOLE_KEEP < hx < ANT_NOTCH[2] + HOLE_KEEP and + ANT_NOTCH[1] - HOLE_KEEP < hy < ANT_NOTCH[3] + HOLE_KEEP): + bad.append(u'安装孔 %s 落进 ESP32 天线缺口 (%.1f, %.1f)' % (n, hx, hy)) + assert not bad, u'底板自检不过:\n ' + u'\n '.join(bad) + return True + + +# ── 下发 ────────────────────────────────────────────────────────────── +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def mil(v): + return round(v * MIL, 4) + + +def polygon_src(pts): + a = [mil(pts[0][0]), mil(pts[0][1])] + for q in pts[1:]: + a += ['L', mil(q[0]), mil(q[1])] + if pts[0] != pts[-1]: + a += ['L', mil(pts[0][0]), mil(pts[0][1])] + return a + + +def push_outline(): + u"""板框 = 一条闭合折线；顺带删掉建工程时留下的 4 条层 11 **导线**（§27.3 的坑）。""" + src = polygon_src(outline_polygon()) + js = ("await eda.dmt_EditorControl.openDocument('%s');" % PCB + + "await new Promise(r=>setTimeout(r,2500));" + + "const oldL = (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11)" + ".map(l=>l.primitiveId);" + + "if (oldL.length) await eda.pcb_PrimitiveLine.delete(oldL);" + + "const oldP = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).map(p=>p.getState_PrimitiveId());" + + "if (oldP.length) await eda.pcb_PrimitivePolyline.delete(oldP);" + + "const poly = await eda.pcb_MathPolygon.createPolygon(%s);" % json.dumps(src) + + "const r = await eda.pcb_PrimitivePolyline.create('', 11, poly, %s);" % mil(OUTLINE_W) + + "await eda.pcb_Document.save();" + + "return {delLine: oldL.length, delPoly: oldP.length, made: !!r," + " now: (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).length," + " line11: (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11).length};") + r = call(js, timeout=300) + print(u'板框折线: %s（删旧导线 %d / 旧折线 %d）；层 11 现有折线 %d / 导线 %d' + % (u'建好' if r['made'] else u'失败', r['delLine'], r['delPoly'], r['now'], r['line11'])) + if not r['made'] or r['now'] != 1: + raise SystemExit(u'!! 板框没画成') + return r + + +PUSH_HOLES_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const H = %s, D = %s; +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const num = p.getState_PadNumber(); + if (typeof num === 'string' && /^H[1-9]$/.test(num)) + await eda.pcb_PrimitivePad.delete(p.getState_PrimitiveId()); +} +let k = 0; +for (const [name, x, y] of H) { + // layer 12 = 多层；末位 metallization=false ⇒ NPTH。参数位序照抄 pcb_blade.push_holes + await eda.pcb_PrimitivePad.create(12, name, x, y, 0, ['ELLIPSE', D, D], '', + ['ROUND', D], 0, 0, 0, false); + k++; +} +await eda.pcb_Document.save(); +return {made: k, now: (await eda.pcb_PrimitivePad.getAll()) + .filter(p => /^H[1-9]$/.test(String(p.getState_PadNumber()))).length}; +""" + + +def push_holes(): + arr = [[k, mil(v[0]), mil(v[1])] for k, v in sorted(MOUNT_HOLES.items())] + r = call(PUSH_HOLES_JS % (PCB, json.dumps(arr), mil(HOLE_D)), timeout=300) + print(u'安装孔: 下发 %d / 读回 %d，NPTH Φ%.1f（M3 尼龙立柱）' % (r['made'], r['now'], HOLE_D)) + for k, v in sorted(MOUNT_HOLES.items()): + print(u' %-3s (%6.2f, %6.2f)' % (k, v[0], v[1])) + return r + + +def verify(): + r = call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "const ps = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11);" + "const line11 = (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>l.layer===11).length;" + "const holes = (await eda.pcb_PrimitivePad.getAll())" + ".filter(p=>/^H[1-9]$/.test(String(p.getState_PadNumber())))" + ".map(p=>[String(p.getState_PadNumber()), p.getState_X(), p.getState_Y()]);" + "return {n: ps.length, poly: ps.length ? ps[0].getState_Polygon() : null," + " line11, holes, comps: (await eda.pcb_PrimitiveComponent.getAll()).length};" % PCB, + timeout=180) + bad = [] + if r['n'] != 1: + bad.append(u'层 11 上有 %d 条折线（应为 1）' % r['n']) + if r['line11']: + bad.append(u'层 11 上还有 %d 条**导线**（板框画成铜的老坑，§27.3）' % r['line11']) + pts = [] + src = r['poly'] + if isinstance(src, dict): + src = src.get('pointArr') or src.get('points') or src.get('polygon') or src + if isinstance(src, list): + i = 0 + while i < len(src): + if src[i] in ('L', 'l'): + i += 1 + continue + if isinstance(src[i], (int, float)) and i + 1 < len(src) and isinstance(src[i + 1], (int, float)): + pts.append((src[i] / MIL, src[i + 1] / MIL)) + i += 2 + else: + i += 1 + if pts: + xs = [p[0] for p in pts] + ys = [p[1] for p in pts] + if abs(min(xs)) > 0.01 or abs(max(xs) - BW) > 0.01 or \ + abs(min(ys)) > 0.01 or abs(max(ys) - BH) > 0.01: + bad.append(u'外接矩形 %.2f~%.2f x %.2f~%.2f != 0~%.0f x 0~%.0f' + % (min(xs), max(xs), min(ys), max(ys), BW, BH)) + if abs(pts[0][0] - pts[-1][0]) > 0.01 or abs(pts[0][1] - pts[-1][1]) > 0.01: + bad.append(u'折线首尾不重合: %s vs %s' % (pts[0], pts[-1])) + if abs(len(pts) - len(outline_polygon())) > 1: + bad.append(u'点数 %d != %d' % (len(pts), len(outline_polygon()))) + print(u'读回板框折线 1 条 / %d 点，外接 %.2f~%.2f x %.2f~%.2f；层 11 遗留导线 %d' + % (len(pts), min(xs), max(xs), min(ys), max(ys), r['line11'])) + else: + bad.append(u'读不回折线点列（原始值 %s）' % str(r['poly'])[:120]) + got = {h[0]: (round(h[1] / MIL, 3), round(h[2] / MIL, 3)) for h in r['holes']} + for n, (hx, hy) in sorted(MOUNT_HOLES.items()): + if n not in got: + bad.append(u'安装孔 %s 没打' % n) + elif abs(got[n][0] - hx) > 0.02 or abs(got[n][1] - hy) > 0.02: + bad.append(u'安装孔 %s 位置 %s != (%.1f, %.1f)' % (n, got[n], hx, hy)) + print(u'安装孔读回 %d 个；板上元件 %d 件' % (len(got), r['comps'])) + if bad: + print(u'[X] 校验不过:') + for b in bad: + print(u' ' + b) + else: + print(u'[OK] 板框是一条闭合折线、外接矩形对上、安装孔齐') + return bad + + +if __name__ == '__main__': + selfcheck() + print(u'底板 %.0f x %.0f，四角 R%.0f；PCB=%s' % (BW, BH, CORNER_R, PCB)) + print(u'槽阵 5 槽 @%.2f: %s' % (SLOT_PITCH, u' / '.join('%.2f' % x for x in slot_xs()))) + print(u'槽体 y %.1f~%.1f；刀片投影 y %.1f~%.1f（带内元件 ≤ %.0f mm）' + % (SLOT_CY - SLOT_BODY_L / 2, SLOT_CY + SLOT_BODY_L / 2, PROJ[0], PROJ[1], H_PROJ)) + for k in sorted(ZONES, key=lambda k: ZONES[k][1]): + z = ZONES[k] + print(u' %-7s y %6.2f ~ %6.2f (%5.1f mm)%s' + % (k, z[1], z[3], z[3] - z[1], u' ← 投影外，可放高件' if k in ('input', 'fan') else u'')) + if '--outline' in sys.argv: + push_outline() + verify() + elif '--holes' in sys.argv: + push_holes() + verify() + elif '--verify' in sys.argv: + verify() diff --git a/.claude/r2/_pcb_place_v1.py.bak b/.claude/r2/_pcb_place_v1.py.bak new file mode 100644 index 0000000..3cb3f3b --- /dev/null +++ b/.claude/r2/_pcb_place_v1.py.bak @@ -0,0 +1,382 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 摆位（M4c-2）。 + + /c/Python314/python .claude/r2/pcb_place.py # 只算 + 自检（不下发） + /c/Python314/python .claude/r2/pcb_place.py --push # 下发摆位 + /c/Python314/python .claude/r2/pcb_place.py --verify # 读回校验 + +## 三类件，三种定位方式 + +1. **机械锚定件**（位置由小米8 主板决定，不许挪）：`K1~K4` 侧键触点盘、 + `J5` 电池排线焊盘、`J4` BM24 尾插座。坐标从 **`.claude/mi8_mech.json`** 换算， + 不手抄。手机主板在刀片上的落点是 `PHONE_ORG`（方案 §3.1：x 3~70.09 / y 29~73.66， + 长边水平、**接口边朝下**）。 +2. **手工钉死件**：`J1` 金手指（`pcb_blade.J1_X`）、`C60` Ø10.3 的 2200 µF、 + `J2` D± 退路座、`J3` EDL 座 —— 各有各的理由，见 `ANCHORS` 的注释。 +3. **其余 70 件**：按功能分组、按「电流流向」排序，塞进四个区（`REGIONS`）， + 用一个简单的货架式排布器摆。**顺序是设计意图，坐标不是** —— + 要改布局改 `GROUPS` 里的顺序和区，不要去改具体坐标。 + +## 分区（方案 §3.1，坐标见 `pcb_blade.py`） + +| 区 | 范围 | 放什么 | +|---|---|---| +| 金手指区 | y 0~11 | **只有 J1，其余一件不放**（插槽体 ~9 mm 要让开）| +| 服务带 | y 12~28 | 电池/尾插/EDL/侧键 MOS/阻尼组 —— 全部接口都在这一带 | +| 手机投影 | x 3~70.1 / y 29~73.7 | **只有 K1~K4 四个裸铜盘**（螺柱间隙只有 1.0 mm，放不下别的）| +| 功率列 | x 72~98 | Buck / eFuse / 检流 / PCA9555。**按「离手机越远越吵」内外分两条** | + +功率列内部：外条（x 86~98，靠板边）放 SW 节点、电感、Cin —— 最吵的； +内条（x 72~85，贴手机）放 FB 分压、DAC 低通、INA226、PCA9555 —— 最怕吵的。 +这是方案 §3.1 的「按离手机越远越吵排」和风险 R-12。 + +## B 面（底层）留空 + +方案 §3.2 的高度表把 `L1`（SPM6530T，3.0 mm）算作「B 面最高件」，但同一张表里 +**A 面功率列可用 11.7~13.7 mm** —— 3.0 的电感放 A 面绰绰有余，而且能贴着 `U1` 摆， +**SW 节点不用打过孔**（§7.2 第二条：SW 面积最小化）。所以这一版 **83 件全在 A 面**， +B 面空着。这让 `h_B` 从 3.0 变成 0，槽距只会更宽裕 —— 是放松，不是违反。 +""" +import io +import json +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 + +MIL = B.MIL +PCB = B.PCB +BBOX = os.path.join(HERE, '_blade_bbox.json') +MECH = os.path.join(os.path.dirname(HERE), 'mi8_mech.json') + +GAP = 0.6 # 件间净距（mm） + +# 手机主板在刀片上的落点：本体 (u,v) -> 板 (x,y) = (PHONE_ORG + (u,v)) +# 方案 §3.1：主板 67.09 × 44.66，长边水平、**接口边（v=0 那条，J600/J1401/侧键都在上面）朝下**。 +# ⚠ 事实来源在 pcb_blade（板级），这里只做别名，不要抄第二份 +PHONE_ORG = B.PHONE_ORG +PHONE_WH = B.PHONE_WH + +# 焊盘外框量不到本体的几个件：给真实本体尺寸（mm） +BODY = { + 'C60': (11.0, 11.0), # Ø10.3 铝电解，2200 µF（T2 = 高 10.5） + 'L1': (7.6, 7.0), # SPM6530T-4R7M + 'J4': (13.2, 3.6), # BM24-50DS + 'U4': (8.0, 8.0), +} +# ⚠ **全部放 A 面，B 面留空。** 方案 §3.2 的高度表把 `L1`（SPM6530T 3.0 mm）算成 +# 「B 面最高件」，但那张表同时写着 **A 面功率列可用 11.7~13.7 mm** —— 3.0 的电感 +# 放 A 面绰绰有余，而且能贴着 U1 摆、SW 节点不用打过孔（§7.2 第二条：SW 面积最小化）。 +# B 面空着只会让槽距更宽裕（h_B 从 3.0 变 0），是**放松**不是违反。 +BOTTOM = [] + + +def phone(u, v): + return (round(PHONE_ORG[0] + u, 3), round(PHONE_ORG[1] + v, 3)) + + +def anchors(): + u"""机械锚定 + 手工钉死的件 -> (x, y, rot)。""" + m = json.load(io.open(MECH, encoding='utf-8')) + sk = m['side_key_contacts'] + a = {} + # ── 侧键触点盘：主板自己的弹片直接压在这四个裸铜盘上（R1 §22.3e 中框式）── + # 位置**完全由主板决定**，Ø1.5 的盘只容许 0.50 mm 位置误差（pcb2_place 的算账）。 + for ref, key in (('K1', 'PWR'), ('K2', 'VUP'), ('K3', 'VDN'), ('K4', 'GND')): + a[ref] = phone(*sk[key]) + (0,) + # ── 电池排线焊盘：排线从 J600 翻过接口边折下来，落在接口边正下方 ── + a['J5'] = (phone(m['contacts_up']['J600'][0], 0)[0], 25.6, 0) + # ── BM24 尾插座：同理，落在 J1401 正下方 ── + a['J4'] = (phone(m['contacts_up']['J1401'][0], 0)[0], 21.0, 0) + # ── 手工钉死的四个 ── + # C60：Ø10.3 / 高 10.5，**只能放没有手机压着的地方**（§21.2）， + # 且要紧挨 J5（它是 VO_P 上的阻尼组主电容，回路越短越好）。 + a['C60'] = (37.5, 19.0, 0) + # J2：D± 退路座。要靠近金手指的 D± 针（B14/B15，x≈62/63）， + # **金手指到 J2 之间要留割断位**（D12 / §17.4），所以摆在指区正上方偏右。 + a['J2'] = (62.0, 15.0, 0) + # J3：EDL 座。跟着 U6（TS5A3157 模拟开关）走 —— 它是手机侧信号， + # 放到功率列去的话 EDL 线要横穿 40 mm。摆在服务带右段、U6 上方。 + a['J3'] = (66.5, 25.0, 0) + return a + + +# ── 分组：**顺序 = 电流/信号流向**，排布器按这个顺序摆 ────────────────── +GROUPS = [ + # (区, 组名, [位号...]) + # ⚠ 功率列**自下而上 = 输出端 → 输入端**（和电流方向相反）。理由： + # `VO_P` 是 4 A，出口必须离服务带的 `C60`/`J5` 越近越好；`+12V` 只有 1.45 A， + # 而且走 L3 灌铜，从金手指爬到板子上半段无所谓。反过来排就是拿 4 A 换 1.45 A。 + # ⚠ `U3` INA226 和 `Rs1` **必须同组且相邻**（§7.2 第四条：取样脚落在 Rs 的 + # Kelvin 焊盘上，不许就近扎孔）。放到内条去就隔了整整一列。 + ('POWER_OUT', u'eFuse + 检流 + INA226', ['U2', 'C14', 'Rs1', 'U3', 'C13', + 'R19', 'Q2']), + ('POWER_OUT', u'Buck 输出', ['C6', 'C7', 'C8']), + ('POWER_OUT', u'Buck 本体 + SW + L', ['U1', 'C5', 'L1', 'C9']), + ('POWER_OUT', u'12V 入口 + Buck 输入', ['F1', 'D1', 'C1', 'C2', 'C3', 'C4']), + # 内条按同样的自下而上顺序，让每一级和外条大致齐平 + ('POWER_IN', u'PCA9555 + I2C 上拉', ['U4', 'C40', 'R40', 'R41']), + ('POWER_IN', u'eFuse 外围', ['R9', 'R10', 'R11', 'R12', 'R16', 'R17', + 'R13', 'R15', 'R14', 'Q1', 'R18']), + ('POWER_IN', u'FB 分压 + DAC 低通', ['R1', 'R2', 'R7', 'R8', 'C12']), + ('POWER_IN', u'Buck 外围', ['R3', 'R4', 'R5', 'R6', 'C10', 'C11']), + ('SERVICE_L', u'侧键 MOS（贴着 K1~K3）', ['Q3', 'R42', 'R43', 'Q4', 'R44', 'R45', + 'Q5', 'R46', 'R47']), + ('SERVICE_M', u'VO_P 阻尼组 + 电池外围', ['C61', 'C62', 'C63', 'C64', 'C65', + 'R60', 'R61']), + ('SERVICE_R', u'尾插 USB + VBUS 开关', ['U7', 'U5', 'C66', 'C67', 'C68', + 'R62', 'R64', 'R65']), + ('SERVICE_R', u'EDL 模拟开关', ['U6', 'R63', 'C69']), +] + +# ── 区（x0, y0, x1, y1），排布器在里面自下而上、自左而右铺 ──────────────── +REGIONS = { + 'POWER_OUT': (85.8, 12.0, 97.5, 74.0), + 'POWER_IN': (72.3, 12.0, 85.0, 74.0), + 'SERVICE_L': (2.5, 12.0, 19.5, 28.0), + 'SERVICE_M': (20.0, 12.0, 41.5, 28.0), + 'SERVICE_R': (42.0, 12.0, 71.0, 28.0), +} + + +def sizes(): + d = json.load(io.open(BBOX, encoding='utf-8')) + out = {} + for ref, v in d.items(): + w, h = BODY.get(ref, (v['w'], v['h'])) + out[ref] = (max(w, 0.6), max(h, 0.6)) + return out + + +def overlaps(r, rects): + for q in rects: + if r[0] < q[2] and q[0] < r[2] and r[1] < q[3] and q[1] < r[3]: + return True + return False + + +def plan(): + u"""返回 {位号: (x, y, rot)} 和占位矩形表。""" + sz = sizes() + pos = dict(anchors()) + pos['J1'] = (B.J1_X, B.J1_Y, B.J1_ROT) + rects = [] + for ref, (x, y, _r) in pos.items(): + w, h = sz[ref] + rects.append((x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2)) + + # 每个区一个 y 游标：**一个组占一条完整的横带**，下一组从带子上沿重新开始。 + # 不这么做的话小件会回填到前面组的空隙里，功能级在 y 上互相咬 —— + # 后面 L3 要按「哪一段是 12V、哪一段是 VO」切铜面就切不出来了。 + cursor = {k: v[1] for k, v in REGIONS.items()} + unplaced = [] + for region, _name, refs in GROUPS: + x0, _y0, x1, y1 = REGIONS[region] + y0 = cursor[region] + band_top = y0 + for ref in refs: + if ref in pos: + continue + w, h = sz[ref] + w += GAP + h += GAP + placed = False + # 自下而上扫，步长 0.5；每一行自左而右扫 + yy = y0 + while yy + h <= y1 + 1e-9 and not placed: + xx = x0 + while xx + w <= x1 + 1e-9: + r = (xx, yy, xx + w, yy + h) + if not overlaps(r, rects): + rects.append(r) + pos[ref] = (round(xx + w / 2, 3), round(yy + h / 2, 3), 0) + band_top = max(band_top, yy + h) + placed = True + break + xx += 0.5 + yy += 0.5 + if not placed: + unplaced.append((ref, region)) + cursor[region] = band_top + 0.4 + return pos, rects, unplaced, sz + + +def bands(): + u"""每个组占的 y 带 —— L3 切铜面按这个来，别手抄坐标。""" + pos, _r, _u, sz = plan() + out = [] + for region, name, refs in GROUPS: + ys = [(pos[r][1] - sz[r][1] / 2, pos[r][1] + sz[r][1] / 2) for r in refs if r in pos] + if ys: + out.append((region, name, round(min(a for a, _ in ys), 2), + round(max(b for _, b in ys), 2))) + return out + + +def selfcheck(pos, rects, unplaced, sz): + bad = [] + if unplaced: + bad.append(u'放不下: %s' % ', '.join(u'%s(%s)' % t for t in unplaced)) + d = json.load(io.open(BBOX, encoding='utf-8')) + missing = sorted(set(d) - set(pos)) + if missing: + bad.append(u'没安排位置: %s' % ' '.join(missing)) + # 重叠。⚠ K1~K4 例外：四个盘的位置是**主板定的**（实测最小间距 1.78 mm、 + # 盘 Ø1.5 ⇒ 净距 0.28），通用的 GAP=0.6 会把它们互判成重叠。 + # 它们之间改按「铜净距 ≥ 0.2」单独校核。 + import math + keys = ['K1', 'K2', 'K3', 'K4'] + rmap = {} + for ref in pos: + if ref in keys: + continue + x, y, _ = pos[ref] + w, h = sz[ref] + rmap[ref] = (x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2) + rl = sorted(rmap.items()) + for i in range(len(rl)): + for j in range(i + 1, len(rl)): + a, b = rl[i][1], rl[j][1] + if a[0] < b[2] - 1e-6 and b[0] < a[2] - 1e-6 and \ + a[1] < b[3] - 1e-6 and b[1] < a[3] - 1e-6: + bad.append(u'%s 和 %s 重叠' % (rl[i][0], rl[j][0])) + PAD_D = 1.5 + for i in range(len(keys)): + for j in range(i + 1, len(keys)): + ax, ay, _ = pos[keys[i]] + bx, by, _ = pos[keys[j]] + gap = math.hypot(ax - bx, ay - by) - PAD_D + if gap < 0.2: + bad.append(u'%s/%s 铜净距 %.2f < 0.2' % (keys[i], keys[j], gap)) + # 全部在板内 + for ref, (x, y, _r) in pos.items(): + w, h = sz[ref] + if ref == 'J1': + continue + if x - w / 2 < 0.5 or x + w / 2 > B.BW - 0.5 or \ + y - h / 2 < 0.5 or y + h / 2 > B.BH - 0.5: + bad.append(u'%s 出板框: (%.2f,%.2f) %.1fx%.1f' % (ref, x, y, w, h)) + # 金手指区（y<11）除 J1 外一件不许有 + for ref, (x, y, _r) in pos.items(): + if ref == 'J1': + continue + if y - sz[ref][1] / 2 < 11.0: + bad.append(u'%s 侵入金手指区（y=%.2f，插槽体要 ~9 mm）' % (ref, y)) + # 手机投影里只许 K1~K4 + px0, py0 = PHONE_ORG + px1, py1 = px0 + PHONE_WH[0], py0 + PHONE_WH[1] + for ref, (x, y, _r) in pos.items(): + if ref.startswith('K'): + continue + w, h = sz[ref] + if x + w / 2 > px0 and x - w / 2 < px1 and y + h / 2 > py0 and y - h / 2 < py1: + bad.append(u'%s 落进手机投影（螺柱间隙只有 1.0 mm）' % ref) + # ⛔ 螺钉头避让：任何元件离主板定位孔中心都要 >= HOLE_KEEP。 + # M4c 第一版把这七个孔整个忘了 —— 高度预算和 K1~K4 的接触压力全靠它们。 + for hname, (hx, hy) in B.phone_holes().items(): + for ref, (x, y, _r) in pos.items(): + w, h = sz[ref] + dx = max(abs(hx - x) - w / 2.0, 0.0) + dy = max(abs(hy - y) - h / 2.0, 0.0) + if math.hypot(dx, dy) < B.HOLE_KEEP: + bad.append(u'%s 离定位孔 %s 只有 %.2f < %.1f（螺钉头压上去）' + % (ref, hname, math.hypot(dx, dy), B.HOLE_KEEP)) + # C60 不许在手机底下（已由上一条覆盖），另外校核它确实在服务带/功率列 + cx, cy, _ = pos['C60'] + if not (12.0 <= cy - BODY['C60'][1] / 2 and cy + BODY['C60'][1] / 2 <= 28.0): + bad.append(u'C60 不在服务带里（可用高度 11.7~13.7 只有这一带和功率列有）') + return bad + + +PUSH_JS = u""" +const MIL = %s, P = %s, BOT = %s; +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const bot = new Set(BOT); +let n = 0, miss = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const d = c.designator; + if (!P[d]) { miss.push(d); continue; } + const id = c.getState_PrimitiveId(); + await eda.pcb_PrimitiveComponent.modify(id, {layer: bot.has(d) ? 2 : 1}); + await eda.pcb_PrimitiveComponent.modify(id, + {x: P[d][0]*MIL, y: P[d][1]*MIL, rotation: P[d][2]}); + n++; +} +await eda.pcb_Document.save(); +return {n, miss}; +""" + + +def push(pos): + r = run(PUSH_JS % (MIL, json.dumps(pos), json.dumps(BOTTOM), PCB), timeout=600) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + print(u'已摆 %d 件；没找到位置的: %s' % (r['result']['n'], r['result']['miss'] or u'无')) + + +def verify(pos, sz): + r = run("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "return (await eda.pcb_PrimitiveComponent.getAll()).map(" + " c=>[c.designator, c.x, c.y, c.rotation, c.layer]);" % PCB, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + got = {a[0]: (a[1] / MIL, a[2] / MIL, a[3], a[4]) for a in r['result']} + bad = [] + for ref, (x, y, rot) in pos.items(): + if ref not in got: + bad.append(u'板上没有 %s' % ref) + continue + gx, gy, grot, glay = got[ref] + if abs(gx - x) > 0.02 or abs(gy - y) > 0.02: + bad.append(u'%s 在 (%.2f,%.2f)，应为 (%.2f,%.2f)' % (ref, gx, gy, x, y)) + want_lay = 2 if ref in BOTTOM else 1 + if glay != want_lay: + bad.append(u'%s 在 layer %s，应为 %s' % (ref, glay, want_lay)) + print(u'读回 %d 件' % len(got)) + if bad: + print(u'[X] %d 条不过:' % len(bad)) + for b in bad[:20]: + print(u' ' + b) + else: + print(u'[OK] %d 件位置 / 层 全部对上' % len(got)) + return bad + + +if __name__ == '__main__': + pos, rects, unplaced, sz = plan() + bad = selfcheck(pos, rects, unplaced, sz) + print(u'安排了 %d 件（含 J1）' % len(pos)) + for region, name, refs in GROUPS: + xs = [pos[r] for r in refs if r in pos] + if xs: + print(u' %-11s %-22s x %5.1f~%5.1f y %5.1f~%5.1f %d 件' + % (region, name, min(p[0] for p in xs), max(p[0] for p in xs), + min(p[1] for p in xs), max(p[1] for p in xs), len(xs))) + print(u' 锚定件: ' + ' '.join(u'%s(%.1f,%.1f)' % (k, pos[k][0], pos[k][1]) + for k in ('K1', 'K2', 'K3', 'K4', 'J5', 'J4', + 'C60', 'J2', 'J3'))) + if bad: + print(u'[X] 自检不过 (%d):' % len(bad)) + for b in bad[:20]: + print(u' ' + b) + if '--push' in sys.argv: + sys.exit(1) + else: + print(u'[OK] 自检通过：无重叠 / 全在板内 / 金手指区干净 / 手机投影只有 K1~K4') + if '--push' in sys.argv: + push(pos) + verify(pos, sz) + elif '--verify' in sys.argv: + verify(pos, sz) diff --git a/.claude/r2/_ping.js b/.claude/r2/_ping.js new file mode 100644 index 0000000..9746742 --- /dev/null +++ b/.claude/r2/_ping.js @@ -0,0 +1,11 @@ +await eda.dmt_EditorControl.openDocument('7b9524b6aaf6f235'); +await new Promise(r=>setTimeout(r,2000)); +const out = {}; +for (const k of ['pcb_PrimitiveHole','pcb_PrimitivePad','pcb_PrimitiveRegion']) { + try { const a = await eda[k].getAll(); out[k] = a ? a.length : 'null'; } catch(e){ out[k]='no api'; } +} +try { + const hs = await eda.pcb_PrimitiveHole.getAll(); + out.holes = hs.map(h=>[Math.round(h.x/3.937)/10, Math.round(h.y/3.937)/10, h.holeDiameter]); +} catch(e){ out.holes = 'x'; } +return out; diff --git a/.claude/r2/_pins.js b/.claude/r2/_pins.js new file mode 100644 index 0000000..aa42ff0 --- /dev/null +++ b/.claude/r2/_pins.js @@ -0,0 +1,7 @@ +const out = {}; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + if (c.getState_ComponentType() !== 'part') continue; + out[c.getState_Designator()] = (await c.getAllPins()).map( + p => [p.getState_PinNumber(), Math.round(p.getState_X()), Math.round(p.getState_Y())]); +} +return out; diff --git a/.claude/r2/_place_base_m8.py.bak b/.claude/r2/_place_base_m8.py.bak new file mode 100644 index 0000000..9517d9c --- /dev/null +++ b/.claude/r2/_place_base_m8.py.bak @@ -0,0 +1,772 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 摆位（M8c）。 + + /c/Python314/python .claude/r2/place_base.py # 只算 + 自检，不下发 + /c/Python314/python .claude/r2/place_base.py --push # 下发摆位 + /c/Python314/python .claude/r2/place_base.py --verify # 读回校验（含朝向断言） + /c/Python314/python .claude/r2/place_base.py --dump # 重抓焊盘坐标 _base_pads.json + /c/Python314/python .claude/r2/place_base.py --bbox # 重抓封装外框 _base_bbox.json + +算法照搬刀片 M7 那一版（方案 §27.5）：**大件先挑「离目标最近的空位」**， +目标点精确到对端焊盘；不是「按面积自下而上塞」。 + +## 五条带（`pcb_base.ZONES`） + +| 带 | y | 放什么 | 为什么 | +|---|---|---|---| +| input | 0~15.5 | A1-INPUT 全部 + `J23` USB-C | **投影带外**，唯一能放 Φ8 直立电解 / DC 座的地方 | +| hub | 15.5~43.5 | A4-HUB | `U32` 顶着槽阵南沿，D± 一出脚就往北 | +| slots | 43.5~85.5 | 只有 `J34~J38` | 走廊要留给 12 根/条的信号，**一件都不放** | +| ctrl | 85.5~113.5 | A3-CTRL + A2-AUX + 风扇小件 | 全部 ≤8 mm，压在刀片投影下没问题 | +| fan | 113.5~125 | `J26/J27` 风扇座 + `J33` 应急口 | **投影带外**，TH 立式 11 mm 高只能在这 | + +## ⛔ 三条「几何验证抓不到、错了就整板报废」的朝向 + +1. **`U32` rot=270**：下行口 pin1~16 在封装原生朝向是**西边**（实测 dx=-4.45）， + 转 270° 才朝北正对槽阵。转 90° 会朝南 —— 五对 D± 得从芯片底下绕出来。 +2. **插槽物理顺序是反的：西 → 东 = `J38 J37 J36 J35 J34`**。 + `U32` 转 270° 之后北排的 x 顺序是 **USB1 在东、USB5 在西**（pin1 dy=+3.75 → x=+3.75）。 + 若按位号自然顺序把 `J34` 摆在西边，五对 D± 会**互相交叉**；两层板上交叉 = 打过孔换到 + L2 = 在 D± 走廊正下方割地平面，正是方案 §6.2 第 1 条明令禁止的那件事。 + ⇒ 宁可位号顺序看着别扭。丝印上会写清楚。 +3. **插槽 rot=90**：封装原生长边沿 x、A 排在 +y。转 90°（逆时针）之后 + A1/B1 落在**南**（y=48）、A 排在**西**列、B 排在**东**列。 + 于是 `+12V`（A2/A3/B1~B3，y 48~50）正对南边的入口链， + `D±`（B14/B15，y 63/64）在东列 —— 与上面第 2 条一起决定了走廊分工。 + ⚠ 旋转方向（顺/逆）是**推导 + 读回校验**的：`verify()` 里三条断言就是干这个的， + 断言不过说明本机客户端的 rot 语义与假设相反，把 90/270 对调即可。 + +## D± 长度：最远一路 ~70 mm，是**已知并接受**的（2026-09-09 用户拍板） + +方案 §6.3 预估 41 mm，前提是 §6.2 第 3 条「D± 排在靠 Hub 那一端的针位」。 +但 M2d 定稿的针位表把 `USB_DP/DM` 放在 **B14/B15**，换算到底板 y=63/64 —— +**正好在 42 mm 长插槽的正中**。Hub 只能坐在槽阵南边，于是每一路都要 +「出脚 → 沿 y≈41 走 x → 拐进走廊 → 北上 20 mm」。端槽 x 距离 40.6 mm 是几何定死的。 +⇒ 最远 ~70 / 最近 ~30。仍远短于 R1 载板的 92 mm，全程 L2 完整地平面做参考， + 且 `J39~J43` 五个 D± 退路座（D12）本来就是为这一条留的。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +BBOX = os.path.join(HERE, '_base_bbox.json') +NETS = os.path.join(HERE, '_base_pcb_nets.json') +PADS = os.path.join(HERE, '_base_pads.json') +POS_JSON = os.path.join(HERE, '_base_place.json') + +GAP = 0.6 # 件间净距（装配下限，自检按它判重叠） +PACK_GAP = 1.5 # 排布器摆放节距（刀片 M7 用 1.8；底板件多、板面紧，1.5） +EDGE_KEEP = 1.0 # 件离板边 +STEP = 0.5 # 候选格点步长 +SNAP = 0.25 # 布线网格 + +# ── 高度表（mm）：投影带（y 15.5~113.5）内**硬上限 8**，方案 §6.6 ────────── +HEIGHT = { + 'J1': 11.0, # DC-005 桶身 + 'C2': 12.0, 'C3': 12.0, # Φ8 直立电解 470 µF + 'J26': 11.0, 'J27': 11.0, # 2510 4P 立式 + 'J33': 11.5, # 2.54 排针立式 + 'J23': 3.3, # USB-C 沉板座 + 'U20': 3.1, 'L3': 4.5, 'L2': 4.0, 'F1': 2.0, +} +H_DEFAULT = 2.0 + +# ── 焊盘外框量不到本体的件：给真实本体（mm）。⛔ 不给的话自检会让小件贴到 +# 直立电解的肚子上 / 排针的塑壳里 —— 焊盘框只有 5.1×1.6，本体是 Φ8。 +BODY = { + 'J1': (14.5, 9.0), # DC-005 桶身（桶口朝板边，见 EDGE_PARTS） + 'C2': (8.0, 8.0), 'C3': (8.0, 8.0), # Φ8 直立电解 470 µF + 'J23': (9.0, 7.5), # USB-C 沉板座本体 + 'J26': (10.2, 5.0), 'J27': (10.2, 5.0), # 2510 4P 带卡扣 + 'J33': (12.7, 2.54), # 2.54 排针塑座 + 'L3': (7.6, 6.5), # 焊盘只量到 3.4，本体 6.5 + 'U20': (19.0, 19.0), # 焊盘外框实测 19.002 × 18.99；天线那 7.5 mm 另有 antenna_keepout 管 +} +# 本体相对**焊盘质心**的偏移（本体不居中的件）。R1 §pcb1_place 实测： +# DC-005 的本体在 x −10.68~+3.92 ⇒ 中心偏 −3.38，桶口朝 −X（rot 0）。 +BODY_OFF = { + 'J1': (-3.38, 0.0), + 'J23': (0.0, -1.5), # USB-C 焊盘在里、口在外 +} +# 本体越过板边是**对的**那几个（接口件）：不判「出板」，改判「够不够得着板边」。 +# 值 = 开口朝哪条边。⚠ 朝向靠 rot 换算：DC-005 桶口原生朝 −X ⇒ 朝南要 rot 90。 +EDGE_PARTS = {'J1': 'S', 'J23': 'S'} + + +# ── 手排件：位置有理由的都钉死，其余交给排布器 ──────────────────────────── +def hand(): + u"""{位号: (x, y, rot)}。每一条都写清楚为什么在这。""" + H = {} + # 5 个插槽：**物理顺序反着来**（见文件头第 2 条） + for i, ref in enumerate(SLOT_ORDER, start=1): + H[ref] = (B.slot_x(i), B.SLOT_CY, 90) + # Hub：顶着槽阵南沿（本体 9.75，顶边 = 37 + 4.9 = 41.9，离槽体 1.6） + # ⛔ y 只能是 24。12V 横脊挪到输入带之后 hub 带整条 28 mm 归 U32： + # 南边逃逸 15.5~19.1（3.6，够 7 根 strap）/ 本体 19.1~28.9 / **北边 D± 扇出 14.6**。 + # 扇出带的账：10 根 1.2 mm 的线要从 0.5 mm 脚距斜着散到 1.41 mm 线距 ⇒ 4.1 mm， + # 再加三条 2.7 的车道 = 12.2。放 37（扇出 1.6）或 30（扇出 8.6）都不够， + # 布线器的现象是内侧那几对「布了 0 段」。 + H['U32'] = (55.0, 24.0, 270) + # 晶振：rot270 之后 XTAL1/2（pin 60/61）在**东**边 y≈+2 ⇒ 贴着东边放 + H['Y1'] = (63.0, 26.6, 0) + # 上行 USB-C：前边（y=0），东端。⚠ 座子开口朝 -y（原生朝向焊盘在里、口在外）， + # 本体深 ~7.5 ⇒ 焊盘中心 y=4.2 时前脸正好压在板边。**这一条只能靠截图确认。** + H['J23'] = (97.0, 5.25, 0) # 本体 y 0~7.5，前脸压板边 + # ── 入口链：**整条手排**，西 → 东，电流方向 = +x ─────────────────────── + # ⛔ 交给排布器的下场（第一版实测）：`F1`/`Q1`/`D1`/栅极 RC 被「离目标最近」 + # 摊到整条 110 mm 的带子上，`VIN_FUSED` 一个网的焊盘外框就有 42 mm 宽， + # 四段铺铜互相重叠 —— 而这是**全板电流最大的一条链（9 A）**， + # 它的形状决定断面够不够，不能让通用排布器决定。 + H['J1'] = (15.0, 11.2, 90) # rot 90 = 桶口朝南；本体 y −0.5~14.1（偏移抄 R1 pcb1_place） + H['F1'] = (22.5, 14.0, 0) # 1206 保险，卧着放，电流顺着 +x 直穿 + H['Q1'] = (28.5, 11.0, 0) # SOP-8 P-MOS 防反接：1~4 脚在西(VIN_FUSED)、5~8 在东(VIN_SW) + H['D1'] = (35.5, 12.5, 0) # SMBJ13A TVS，贴在漏极铜的东缘 + H['C2'] = (44.2, 10.5, 0) # Φ8 直立电解 470 µF（南沿 6.5 让开 12V 横脊的 5.8） + H['C3'] = (53.6, 10.5, 0) + H['C4'] = (33.5, 8.6, 0) # 0805 VIN_SW 旁路：挪到 Q1/D1 底下那块空地 —— 输入带被横脊吃掉 5 mm 之后， + # Φ8 电解占满剩下的 8.6 mm 高，它俩挤不进电解那一列 + H['C5'] = (37.8, 8.6, 0) + H['C6'] = (22.5, 9.0, 0) # 100nF 高频旁路：原位置 y=2.5 被 12V 横脊占了 # 0402 高频旁路，压在储能铜的南沿； + # ⚠ 它是 VIN_SW 的一员，交给排布器会被摊到 x=77， + # 把 VIN_SW 的铜面一路撑进 12V 母线的地盘 + # 检流：Rs6 与 U13 贴在一起走 Kelvin（同 R1 / 刀片 U3-Rs1） + H['Rs6'] = (62.0, 10.5, 0) # 2512 5 mΩ，卧着放（南沿 10.9 让开横脊） + # ⚠ `U13` 挪到 hub 带：输入带被 12V 横脊吃掉南边 5 mm 之后，剩下的 9.2 mm + # 放不下「Rs6 3.46 + U13 5.84 + 净距 0.6 = 9.9」。Kelvin 取样线因此长了几毫米 —— + # 判据不变：两根取样线的端点必须落在 `Rs6` 的两个焊盘上，中间不许有过孔。 + H['U13'] = (62.5, 19.0, 0) # INA226，Rs6 正北 + # 风墙：两只风扇座 + 应急串口，全在投影带外 + H['J26'] = (20.0, 119.0, 0) + H['J27'] = (40.0, 119.0, 0) + H['J33'] = (92.0, 119.0, 0) + # ESP32：天线在封装的 +y 那一头（焊盘只有三面，北面 7 mm 是天线）。 + # ⛔ **2026-09-09 用户拍板改成 rot=90（天线朝西）+ 挪到西板边 + 板材挖缺口**。 + # 旧值 (17.0, 96.0, 0) 把天线埋在板中央：天线尖正前方 1.0 mm 就是整块地平面， + # 再往北 3 mm 是风扇带的 RT601/RT602 —— 等于给天线加了块反射板， + # 而设计文档 §PCB 要点要求的是「模组**放板边**」。见 `pcb_base.ANT_NOTCH`。 + # rot 是 CCW：+y 转 90° → −x（朝西），与 `U32` rot=270「西→北」同一套语义。 + # x=18.0 ⇒ 焊盘西沿 8.5，离缺口边（x=7.5）1.0 mm；天线段 x 1.0~8.5 基本悬空。 + # ⚠ 连带代价（已知、可接受）：pin1~14 从西列转到**南排**（FAN_* / PRSNT / USB6 D±）， + # pin15~26 从南排转到**东列**（EFUSE_EN1~5），pin27~40 转到**北排**（I²C / NTC / UART）。 + # 风扇那几根因此要绕模组东侧往北走 ~40 mm —— 都是低速信号，交给布线器。 + H['U20'] = (18.0, 96.0, 90) + # mux / DAC / 两颗 Buck：ctrl 带里按功能分块，剩下的交给排布器 + H['U35'] = (40.0, 90.0, 0) # I²C mux，南面 SCL1~4 朝槽阵 + H['U6'] = (52.0, 90.0, 0) # DAC 1/2/4 + H['U7'] = (62.0, 90.0, 0) # DAC 3/5 + H['U19'] = (78.0, 90.0, 0) # 3V3 Buck + H['U30'] = (95.0, 90.0, 0) # 5V Buck + # ⚠ `U31`（AMS1117）和五个 D± 退路座 `J39~J43` **交给排布器**： + # 12V 母线改成梳子之后，hub 带里的空位被脊和五根齿切得很碎，手写坐标一改 + # 母线就得跟着改一遍。它们的目标点很明确（`U31`→`U32`，退路座→自己那一路的 + # `USBn_DP/DM`），排布器按「离目标最近的空位」摆比手写稳。 + return H + + +# 西 → 东。见文件头第 2 条。 +SLOT_ORDER = ['J38', 'J37', 'J36', 'J35', 'J34'] +# ⛔ 2026-09-09 用户拍板：底板上的 5 个 D± 退路座 `J39~J43` 全部删掉 +# （原理图 A5B-SLOTS 也删了）。底板侧不再有 D± 退路 —— +# `USBn_DP/DM` 从 `U32` 直达槽针，一条路走到黑。 + + +def corridor_x(i): + u"""槽 i（1=最西）东侧走廊的中心 x。""" + xs = B.slot_xs() + if i < B.SLOT_N: + return round((xs[i - 1] + xs[i]) / 2.0, 3) + return round((xs[-1] + B.SLOT_BODY_W / 2 + B.BW) / 2.0, 3) + + +# ── 分区：谁进哪条带（页 → 带，加少量覆盖）──────────────────────────────── +PAGE_REGION = { + 'A1-INPUT': 'input', 'A4-HUB': 'hub', 'A5-SLOTS': 'slots', 'A5B-SLOTS': 'hub', + 'A3-CTRL': 'ctrl', 'A2-AUX': 'ctrl', 'A6-FAN': 'fan', +} +REGION_OVERRIDE = { + 'J23': 'input', # USB-C 要在前边板沿，不在 hub 带 + 'J33': 'fan', # 立式排针 11.5 mm，只能在投影带外 +} +# 泄放块（TL431 + 10 Ω/10 W 五颗 2512 + 驱动）整块挪到 ctrl 带 —— 方案 §6.5 就是这么分的。 +# ⛔ 留在 input 带的后果实测过：排布器按「离目标最近」把 `Q3` 塞进 `VIN_SW` 的铜面正中， +# 9 A 那段铜被它的两只脚掐到 3.0 mm（要 8）。泄放只在回灌瞬态导通，占空比极低， +# 放在刀片投影下（2512 高 0.6 mm）没有高度问题，而且正对风道。 +for _r in ('U29', 'Q3', 'R4', 'R5', 'R6', 'C11', 'R9A', 'R9B', 'R9C', 'R9D', 'R9E'): + REGION_OVERRIDE[_r] = 'ctrl' +# `Q1` 的栅极 RC（缓启动）挪到 hub 带：它们是 GATE / VIN_FUSED 网，留在输入带就会 +# 坐在 **9 A 的 `VIN_SW` 铜面正中**，把断面从 8.7 掐到 5.0（实测）。 +# 栅极 RC 是低速软启动回路，离 Q1 十来毫米没有影响。 +for _r in ('DZ1', 'C1', 'R1'): + REGION_OVERRIDE[_r] = 'hub' +# 排不下就往这条带溢出（风扇带只有 11.5 mm 深，27 个小件塞不满也塞不下全部） +OVERFLOW = {'fan': 'ctrl', 'ctrl': 'hub', 'input': 'hub', 'hub': 'ctrl'} + +# 排布器可用矩形 = 分区带按 EDGE_KEEP 内缩 +def regions(): + out = {} + for k, (x0, y0, x1, y1) in B.ZONES.items(): + out[k] = (max(x0 + EDGE_KEEP, EDGE_KEEP), y0 + (0.2 if y0 > 0 else EDGE_KEEP), + min(x1 - EDGE_KEEP, B.BW - EDGE_KEEP), y1 - (0.2 if y1 < B.BH else EDGE_KEEP)) + return out + + +# ── 数据 ───────────────────────────────────────────────────────────────── +def sizes(): + d = json.load(io.open(BBOX, encoding='utf-8')) + out = {} + for k, v in d.items(): + bw, bh = BODY.get(k, (0.0, 0.0)) + out[k] = (max(v['w'], bw, 0.6), max(v['h'], bh, 0.6)) + return out + + +def page_of(): + u"""{位号: 页名}，从原理图 BOM 反查。""" + bom = json.load(io.open(os.path.join(HERE, '_base_sch_bom.json'), encoding='utf-8')) + return {r['d']: pg for pg, rows in bom.items() for r in rows} + + +def net_pins(): + u"""{网名: [(位号, 脚号)]}，去掉 GND 这种到处都是的。""" + nets = json.load(io.open(NETS, encoding='utf-8')) + out = {} + for ref, pads in nets.items(): + for pn, net in pads: + if net: + out.setdefault(net, []).append((ref, str(pn))) + return out + + +BIG_NETS = {'GND', '+12V', '+3V3', '+5V', '+3V3_HUB'} + + +def peers(): + u"""{位号: [对端位号]}，只算「小网」（≤6 只脚），大网不带方向信息。""" + out = {} + for net, pins in net_pins().items(): + if net in BIG_NETS or len(pins) > 6: + continue + refs = sorted(set(r for r, _ in pins)) + for a in refs: + out.setdefault(a, []).extend(b for b in refs if b != a) + return out + + +def wh(ref, rot, sz): + w, h = sz[ref] + return (h, w) if rot % 180 else (w, h) + + +def body_rect(ref, x, y, rot, sz): + u"""本体矩形（板坐标）。偏移要跟着 rot 转 —— 不转的话 DC 座的桶身会算到反方向去。""" + w, h = wh(ref, rot, sz) + ox, oy = BODY_OFF.get(ref, (0.0, 0.0)) + t = math.radians(rot % 360) + dx = ox * math.cos(t) - oy * math.sin(t) + dy = ox * math.sin(t) + oy * math.cos(t) + cx, cy = x + dx, y + dy + return (cx - w / 2, cy - h / 2, cx + w / 2, cy + h / 2) + + +def height(ref): + return HEIGHT.get(ref, H_DEFAULT) + + +def overlaps(r, rects): + for q in rects: + if r[0] < q[2] and q[0] < r[2] and r[1] < q[3] and q[1] < r[3]: + return True + return False + + +def blockers(sz): + u"""固定障碍：四个螺钉头避让圈 + 板角 R5 之外的地方 + `U20` 的天线净空。""" + out = [] + k = B.HOLE_KEEP + for _n, (hx, hy) in B.MOUNT_HOLES.items(): + out.append((hx - k, hy - k, hx + k, hy + k)) + # ESP32 天线净空（跟着 rot 转；rot=90 时在模组**西边**，正对板框缺口） + out.append(antenna_keepout(sz)) + # ⛔ 12V 母线 + D± 扇出带是摆位禁区。往母线上塞件，铜面被挖成细条而断面校核 + # 只看得到「有铜」；往扇出带塞件，五对 D± 直接布不出来。 + out += list(B.keepout_rects()) + return out + + +ANT_LEN = 7.5 # 天线段：本体 25.5 − (焊盘框 19.0 − 每边出脚 0.5) = 7.0，留 0.5 +ANT_SIDE = 0.5 # 天线两侧各留 + + +def antenna_keepout(sz): + u"""`U20` 天线净空：两层都不许铺铜、不许走线、不许放件。 + + ⛔ **必须跟着 rot 转**。天线在封装的 +y 那一头；rot 是 CCW ⇒ 90° 之后朝西。 + 写死成「焊盘北沿之外那一块」的下场：模组转过去了、净空还留在北边， + 于是铺铜照样把铜铺到天线底下 —— 而摆位自检 / DRC / 几何校验**一条都不会响** + （这一版就是这么来的：模组在板中央、天线尖前 1 mm 一整块地平面）。 + """ + ax, ay, rot = hand()['U20'] + w, h = wh('U20', rot, sz) + r = int(round(rot)) % 360 + if r == 0: # 天线朝北 + return (ax - w / 2 - ANT_SIDE, ay + h / 2, + ax + w / 2 + ANT_SIDE, ay + h / 2 + ANT_LEN) + if r == 90: # 天线朝西 + return (ax - w / 2 - ANT_LEN, ay - h / 2 - ANT_SIDE, + ax - w / 2, ay + h / 2 + ANT_SIDE) + if r == 180: # 天线朝南 + return (ax - w / 2 - ANT_SIDE, ay - h / 2 - ANT_LEN, + ax + w / 2 + ANT_SIDE, ay - h / 2) + if r == 270: # 天线朝东 + return (ax + w / 2, ay - h / 2 - ANT_SIDE, + ax + w / 2 + ANT_LEN, ay + h / 2 + ANT_SIDE) + raise ValueError(u'U20 只支持 0/90/180/270，拿到 %s' % rot) + + +# ── 排布 ───────────────────────────────────────────────────────────────── +def target_point(ref, pr, pos, sz, fallback): + u"""目标点 = 已定位的对端件的质心（有芯片对端时只认芯片）。""" + ps = [p for p in pr.get(ref, []) if p in pos] + if not ps: + return fallback + chips = [p for p in ps if sz.get(p, (0, 0))[0] * sz.get(p, (0, 0))[1] > 12.0] + use = chips or ps + return (sum(pos[p][0] for p in use) / len(use), sum(pos[p][1] for p in use) / len(use)) + + +def plan(): + sz = sizes() + pg = page_of() + pos = dict(hand()) + rects = list(blockers(sz)) + for ref, (x, y, r) in pos.items(): + w, h = wh(ref, r, sz) + rects.append((x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2)) + + R = regions() + todo = {} + for ref in sz: + if ref in pos: + continue + reg = REGION_OVERRIDE.get(ref) or PAGE_REGION[pg[ref]] + todo.setdefault(reg, []).append(ref) + + pr = peers() + unplaced = [] + order = ['input', 'hub', 'ctrl', 'fan'] + for reg in order: + refs = sorted(todo.get(reg, []), key=lambda r: (-sz[r][0] * sz[r][1], r)) + for ref in refs: + placed = False + chain = [reg] + nxt = OVERFLOW.get(reg) + while nxt and nxt not in chain: + chain.append(nxt) + nxt = OVERFLOW.get(nxt) + for rg in chain: + x0, y0, x1, y1 = R[rg] + w, h = sz[ref][0] + PACK_GAP, sz[ref][1] + PACK_GAP + t = target_point(ref, pr, pos, sz, ((x0 + x1) / 2.0, (y0 + y1) / 2.0)) + best = None + yy = y0 + while yy + h <= y1 + 1e-9: + xx = x0 + while xx + w <= x1 + 1e-9: + r = (xx, yy, xx + w, yy + h) + if not overlaps(r, rects): + cx, cy = xx + w / 2, yy + h / 2 + key = (math.hypot(cx - t[0], cy - t[1]), yy, xx) + if best is None or key < best[0]: + best = (key, r, cx, cy) + xx += STEP + yy += STEP + if best is not None: + _k, r, cx, cy = best + rects.append(r) + pos[ref] = (round(cx, 3), round(cy, 3), 0) + placed = True + break + if not placed: + unplaced.append((ref, reg)) + snap(pos, sz, rects) + return pos, rects, unplaced, sz + + +# ⛔ **插槽不许吸网格**：两列焊盘相距 7.2 mm（= 28.8 格），两列不可能同时落在 0.25 上， +# 而吸一下就把 20.32 的槽距打成 20.25/20.5 交替 —— 3D 打印导轨是按 20.32 等距做的。 +# ⇒ 槽距的精确值比焊盘对格重要，插槽整体排除。 +NO_SNAP = set(SLOT_ORDER) + + +def snap(pos, sz, rects): + u"""把件吸到 0.25 布线网格上；破了 GAP 的退回去（刀片 M7 §27.9 的做法）。""" + before = dict(pos) + for ref, (x, y, r) in list(pos.items()): + if ref in NO_SNAP: + continue + pos[ref] = (round(round(x / SNAP) * SNAP, 3), round(round(y / SNAP) * SNAP, 3), r) + for _ in range(6): + bad = set() + items = sorted(pos) + for i, a in enumerate(items): + wa, ha = wh(a, pos[a][2], sz) + ra = (pos[a][0] - wa / 2, pos[a][1] - ha / 2, pos[a][0] + wa / 2, pos[a][1] + ha / 2) + for b in items[i + 1:]: + wb, hb = wh(b, pos[b][2], sz) + rb = (pos[b][0] - wb / 2, pos[b][1] - hb / 2, pos[b][0] + wb / 2, pos[b][1] + hb / 2) + if ra[0] < rb[2] + GAP and rb[0] < ra[2] + GAP and \ + ra[1] < rb[3] + GAP and rb[1] < ra[3] + GAP: + bad.add(a if pos[a] != before[a] else b) + bad = {r for r in bad if pos[r] != before[r]} + if not bad: + break + for ref in bad: + pos[ref] = before[ref] + return pos + + +# ── 自检 ───────────────────────────────────────────────────────────────── +def selfcheck(pos, unplaced, sz): + bad = [] + if unplaced: + bad.append(u'排不下 %d 件: %s' % (len(unplaced), ' '.join(r for r, _ in unplaced))) + items = sorted(pos) + keep = antenna_keepout(sz) + for i, a in enumerate(items): + x, y, r = pos[a] + w, h = wh(a, r, sz) + # 板内 + 离板边。⚠ 接口件本体越过板边是对的，改判「够得着板边」 + if a in EDGE_PARTS: + br = body_rect(a, x, y, r, sz) + if abs(br[1]) > 1.0: + bad.append(u'%s 是接口件，本体南沿 y=%.2f 没贴到板边（差 %.2f）' + % (a, br[1], abs(br[1]))) + if not (EDGE_KEEP - 0.01 <= x - w / 2 and x + w / 2 <= B.BW - EDGE_KEEP + 0.01): + bad.append(u'%s 东西向出板: x=%.2f w=%.2f' % (a, x, w)) + elif not (EDGE_KEEP - 0.01 <= x - w / 2 and x + w / 2 <= B.BW - EDGE_KEEP + 0.01 and + EDGE_KEEP - 0.01 <= y - h / 2 and y + h / 2 <= B.BH - EDGE_KEEP + 0.01): + bad.append(u'%s 出板或贴边: (%.2f,%.2f) %.2fx%.2f' % (a, x, y, w, h)) + # ⛔ ESP32 天线缺口那一块**没有板材**：谁伸进去谁悬空 + # （`U20` 除外 —— 它的天线本来就该悬在那儿，这是这个缺口存在的理由） + if a != 'U20': + nk = B.notch_rect() + if (x + w / 2 > nk[0] - EDGE_KEEP + 0.01 and x - w / 2 < nk[2] + EDGE_KEEP - 0.01 and + y + h / 2 > nk[1] - EDGE_KEEP + 0.01 and y - h / 2 < nk[3] + EDGE_KEEP - 0.01): + bad.append(u'%s 伸进了 ESP32 天线缺口（那儿没板材）: (%.2f,%.2f)' % (a, x, y)) + # 刀片投影内不许放高件（硬碰撞） + if not B.height_ok(y, height(a)): + bad.append(u'%s 高 %.1f mm 落在刀片投影 y=%.1f 上（上限 %.0f）' + % (a, height(a), y, B.H_PROJ)) + # 螺钉头 + for n, (hx, hy) in B.MOUNT_HOLES.items(): + if abs(x - hx) < w / 2 + B.HOLE_KEEP and abs(y - hy) < h / 2 + B.HOLE_KEEP: + bad.append(u'%s 压在螺钉 %s 的头下' % (a, n)) + # 天线净空 + if x + w / 2 > keep[0] and keep[2] > x - w / 2 and y + h / 2 > keep[1] and keep[3] > y - h / 2: + if a != 'U20': + bad.append(u'%s 进了 U20 的天线净空' % a) + # 槽带里除了插槽什么都不许有 + if a not in SLOT_ORDER and B.ZONES['slots'][1] < y < B.ZONES['slots'][3]: + bad.append(u'%s 摆进了插槽带 y=%.1f（走廊要留给布线）' % (a, y)) + for b in items[i + 1:]: + x2, y2, r2 = pos[b] + w2, h2 = wh(b, r2, sz) + if abs(x - x2) < (w + w2) / 2 + GAP and abs(y - y2) < (h + h2) / 2 + GAP: + bad.append(u'%s 与 %s 挨太近（净距 < %.1f）' % (a, b, GAP)) + return bad + + +# ── 下发 / 读回 ─────────────────────────────────────────────────────────── +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + + +def call(js, timeout=300): + r = run(OPEN + js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:700]) + sys.exit(1) + return r['result'] + + +def push(pos): + arr = [[k, round(v[0] * MIL, 4), round(v[1] * MIL, 4), v[2]] for k, v in sorted(pos.items())] + r = call(""" +const P = %s; +const by = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) by[c.designator] = c; +let k = 0, miss = []; +for (const [d, x, y, rot] of P) { + const c = by[d]; + if (!c) { miss.push(d); continue; } + await eda.pcb_PrimitiveComponent.modify(c.getState_PrimitiveId(), + {x: x, y: y, rotation: rot}); + k++; +} +await eda.pcb_Document.save(); +return {moved: k, miss: miss}; +""" % json.dumps(arr), timeout=600) + print(u'摆位下发 %d 件%s' % (r['moved'], (u'；板上没有: %s' % r['miss']) if r['miss'] else u'')) + return r + + +BBOX_JS = u""" +const MIL = %s; +const out = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + let x0=1e9, y0=1e9, x1=-1e9, y1=-1e9; + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let poly = false; + if (String(pad[0])==='POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v=>typeof v==='number'); + let mnx=1e9,mny=1e9,mxx=-1e9,mxy=-1e9; + for (let k=0;k+1 45 && prot < 135) { const t=w; w=h; h=t; } + x0=Math.min(x0,p.x-w/2); x1=Math.max(x1,p.x+w/2); + y0=Math.min(y0,p.y-h/2); y1=Math.max(y1,p.y+h/2); + } + out[c.designator] = {n: ps.length, w: (x1-x0)/MIL, h: (y1-y0)/MIL, rot: c.rotation, + fp: (c.footprint && c.footprint.name) ? c.footprint.name : c.footprint}; +} +return out; +""" % MIL + + +def dump_bbox(): + u"""抓封装外框 → `_base_bbox.json`。 + + ⛔ **必须按 rot 反转回封装自身的朝向**：板上读回来的是**板坐标**的外框， + 件转了 90° 之后 42×9.2 会记成 9.2×42。而 `wh()` 又会按 rot 再转一次 —— + 转两次等于没转，自检立刻报「插槽互相重叠 / 出板」。 + （第一版就是这么翻车的：摆位下发之后重抓一次 bbox，五个插槽全变成 44×7.9。） + """ + d = call(BBOX_JS, timeout=600) + for k, v in d.items(): + if int(v.get('rot') or 0) % 180 == 90: + v['w'], v['h'] = v['h'], v['w'] + v['w'] = round(v['w'], 3) + v['h'] = round(v['h'], 3) + io.open(BBOX, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False, indent=0)) + print(u'已写 _base_bbox.json：%d 件（已按 rot 反转回封装朝向）' % len(d)) + return d + + +DUMP_JS = u""" +const MIL = %s; +const out = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let cx = p.x, cy = p.y, poly = false; + if (String(pad[0]) === 'POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v => typeof v === 'number'); + const pts = []; + for (let k=0; k+1q[1]))].sort((a,b)=>a-b); + for (let b2=0; b2+1a-b); + for (let k=0; k+1 45 && rot < 135) { const t=w; w=h; h=t; } + out.push([c.designator, String(p.padNumber), Math.round(cx/MIL*1000)/1000, + Math.round(cy/MIL*1000)/1000, Math.round(w/MIL*1000)/1000, + Math.round(h/MIL*1000)/1000, p.layer, p.net||'', String(pad[0])]); + } +} +return out; +""" % MIL + + +def dump_pads(): + d = call(DUMP_JS, timeout=600) + io.open(PADS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) + print(u'已写 _base_pads.json：%d 个焊盘' % len(d)) + return d + + +def verify(pos, sz): + u"""读回坐标逐件对账 + **三条朝向断言**（几何验证抓不到的那三条）。""" + d = dump_pads() + got = {} + for ref, pn, x, y, _w, _h, _lay, net, _sh in d: + got.setdefault(ref, {})[pn] = (x, y, net) + bad = [] + r = call("const o={}; for (const c of await eda.pcb_PrimitiveComponent.getAll())" + " o[c.designator]=[c.x/%s, c.y/%s, c.rotation]; return o;" % (MIL, MIL)) + for ref, (x, y, rot) in sorted(pos.items()): + if ref not in r: + bad.append(u'%s 板上没有' % ref) + continue + gx, gy, grot = r[ref] + if abs(gx - x) > 0.02 or abs(gy - y) > 0.02 or (grot or 0) % 360 != rot % 360: + bad.append(u'%s 读回 (%.2f,%.2f,%s) != (%.2f,%.2f,%s)' % (ref, gx, gy, grot, x, y, rot)) + + def pad(ref, pn): + return got.get(ref, {}).get(pn) + + # 断言 1：U32 下行口在**北**边，且 USB1 在东、USB5 在西 + p1, p11 = pad('U32', '2'), pad('U32', '12') # USB1_DP / USB5_DP + if not p1 or not p11: + bad.append(u'U32 的 USB1_DP/USB5_DP 焊盘没读到') + else: + if p1[1] <= pos['U32'][1] or p11[1] <= pos['U32'][1]: + bad.append(u'U32 下行口没朝北（USB1_DP y=%.2f，芯片中心 y=%.2f）⇒ rot 语义相反，' + u'把 270 换成 90' % (p1[1], pos['U32'][1])) + if p1[0] <= p11[0]: + bad.append(u'U32 北排顺序不对：USB1 x=%.2f 应该在 USB5 x=%.2f 的**东**边' + % (p1[0], p11[0])) + # 断言 2：插槽 A1/B1 在南、D± 在东列 + for ref in SLOT_ORDER: + p2, p46, p47 = pad(ref, '2'), pad(ref, '46'), pad(ref, '47') # A2=+12V / B14,B15=D± + cx, cy = pos[ref][0], pos[ref][1] + if not p2 or not p46: + bad.append(u'%s 的 2/46 脚没读到' % ref) + continue + if p2[1] > cy: + bad.append(u'%s 的 +12V 脚（A2）在北边 y=%.2f，应该在南 ⇒ 插槽 rot 反了' % (ref, p2[1])) + if p46[0] < cx: + bad.append(u'%s 的 D± 在西列 x=%.2f，应该在东列 ⇒ 插槽 rot 反了' % (ref, p46[0])) + if abs(p46[1] - p47[1]) > 1.2 or abs(p46[0] - p47[0]) > 0.1: + bad.append(u'%s 的 D± 两只脚不在同一列' % ref) + # 断言 3：五对 D± 从 U32 到各槽**不交叉**（按 x 单调） + xs = [] + for i, ref in enumerate(SLOT_ORDER, start=1): + pn = {'J38': '12', 'J37': '9', 'J36': '7', 'J35': '4', 'J34': '2'}[ref] # U32 侧 DP 脚 + pu = pad('U32', pn) + ps = pad(ref, '46') + if pu and ps: + xs.append((pu[0], ps[0], ref)) + for a, b in zip(xs, xs[1:]): + if not (a[0] < b[0] and a[1] < b[1]): + bad.append(u'D± 扇出会交叉：%s(U32 x=%.2f→槽 x=%.2f) 与 %s(%.2f→%.2f)' + % (a[2], a[0], a[1], b[2], b[0], b[1])) + # 断言 4：`U20` 的天线朝**西**且整段落在板框缺口里 + # ⛔ 这一条是 2026-09-09 补的：天线朝向 rot 一改就全变，而 + # 摆位自检只看焊盘外框（19×19，天线那 7 mm 根本不在模型里）、 + # DRC 只看铜、`board_check` 只看连通性 —— 没有一道能看出天线埋在板里。 + # 判据用**板上读回的焊盘**：pin1 / pin40 是紧挨天线那一头的两只脚。 + pa, pb = pad('U20', '1'), pad('U20', '40') + if not pa or not pb: + bad.append(u'U20 的 1/40 脚没读到，天线朝向无法判定') + else: + mx, my = (pa[0] + pb[0]) / 2.0, (pa[1] + pb[1]) / 2.0 + cx, cy = pos['U20'][0], pos['U20'][1] + if mx > cx - 5.0: + bad.append(u'U20 天线没朝西：pin1/40 中点 x=%.2f，模组中心 x=%.2f ' + u'⇒ rot 不是 90 或 rot 语义相反' % (mx, cx)) + nk = B.notch_rect() + tip = mx - ANT_LEN + # tip = 天线尖；判据是「尖落在缺口的深度里 + 那一头的焊盘还在板上 + y 在缺口里」 + if not (nk[0] - 0.01 <= tip <= nk[2] + 0.01 and mx > nk[2] and + nk[1] <= my <= nk[3]): + bad.append(u'U20 天线尖 x=%.2f (y=%.2f) 没落在板框缺口 x %.1f~%.1f / y %.1f~%.1f 里 ' + u'⇒ 天线又埋回板子里了' % (tip, my, nk[0], nk[2], nk[1], nk[3])) + if bad: + print(u'[X] 读回校验 %d 条不过:' % len(bad)) + for t in bad[:25]: + print(u' ' + t) + else: + print(u'[OK] %d 件坐标/角度逐件对上；四条朝向断言全过' % len(pos) + + u'（U32 下行口朝北且 USB1 在东、插槽 +12V 在南 / D± 在东列、' + u'五对 D± 不交叉、U20 天线朝西且落在板框缺口里）') + return bad + + +def report(pos, sz): + print(u'') + print(u'带内件数:') + cnt = {} + for ref, (x, y, _r) in pos.items(): + cnt.setdefault(B.zone_of(y) or '?', []).append(ref) + for k in ('input', 'hub', 'slots', 'ctrl', 'fan'): + v = cnt.get(k, []) + z = B.ZONES[k] + area = (z[2] - z[0]) * (z[3] - z[1]) + used = sum(sz[r][0] * sz[r][1] for r in v) + print(u' %-6s %3d 件 焊盘外框 %5.0f / %5.0f mm² (%.0f%%)' + % (k, len(v), used, area, 100.0 * used / area)) + print(u'') + print(u'插槽（西 → 东，注意位号是**反**的）:') + for i, ref in enumerate(SLOT_ORDER, start=1): + print(u' %s x=%.2f 东侧走廊中心 x=%.2f' % (ref, pos[ref][0], corridor_x(i))) + print(u'') + print(u'D± 估算长度（曼哈顿，U32 脚 → 走廊 → 槽脚）:') + for i, ref in enumerate(SLOT_ORDER, start=1): + cx = corridor_x(i) + ux, uy = pos['U32'][0], pos['U32'][1] + sz['U32'][1] / 2 + sx = pos[ref][0] + B.PAD_COL_DX + B.PAD_L / 2 + sy = B.SLOT_CY - 1.5 + L = abs(cx - ux) + abs(B.ZONES['slots'][1] - uy) + abs(sy - B.ZONES['slots'][1]) + abs(sx - cx) + print(u' %s ≈ %.0f mm' % (ref, L)) + + +if __name__ == '__main__': + if '--bbox' in sys.argv: + dump_bbox() + sys.exit(0) + if '--dump' in sys.argv: + dump_pads() + sys.exit(0) + pos, rects, unplaced, sz = plan() + bad = selfcheck(pos, unplaced, sz) + print(u'底板摆位：%d 件（手排 %d + 排布 %d）' % (len(pos), len(hand()), len(pos) - len(hand()))) + if bad: + print(u'[X] 自检 %d 条不过:' % len(bad)) + for t in bad[:30]: + print(u' ' + t) + else: + print(u'[OK] 自检全过（不出板 / 不重叠 / 投影带限高 / 螺钉头 / 槽带空 / 天线净空）') + report(pos, sz) + io.open(POS_JSON, 'w', encoding='utf-8').write( + json.dumps({k: list(v) for k, v in pos.items()}, ensure_ascii=False, indent=0)) + if '--push' in sys.argv: + if bad: + print(u'!! 自检不过，不下发') + sys.exit(1) + push(pos) + verify(pos, sz) + elif '--verify' in sys.argv: + verify(pos, sz) diff --git a/.claude/r2/_probe3.json b/.claude/r2/_probe3.json new file mode 100644 index 0000000..739722c --- /dev/null +++ b/.claude/r2/_probe3.json @@ -0,0 +1,249 @@ +{ + "success": true, + "result": { + "SOFNG": { + "name": "PCIE-64P11L", + "n": 65, + "first": [ + [ + "1", + "A1", + -35, + 155 + ], + [ + "2", + "A2", + -35, + 145 + ], + [ + "3", + "A3", + -35, + 135 + ], + [ + "4", + "A4", + -35, + 125 + ], + [ + "5", + "A5", + -35, + 115 + ], + [ + "6", + "A6", + -35, + 105 + ] + ], + "last": [ + [ + "60", + "B28", + 35, + -115 + ], + [ + "61", + "B29", + 35, + -125 + ], + [ + "62", + "B30", + 35, + -135 + ], + [ + "63", + "B31", + 35, + -145 + ], + [ + "64", + "B32", + 35, + -155 + ], + [ + "65", + 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"f0e083ad-3d54-48a1-9f66-06208d0d8fed" +} diff --git a/.claude/r2/_shot_reg.py b/.claude/r2/_shot_reg.py new file mode 100644 index 0000000..9f5e6b6 --- /dev/null +++ b/.claude/r2/_shot_reg.py @@ -0,0 +1,18 @@ +import base64, json, sys, os +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) +from eda import run +page, x0, y0, x1, y1, out = sys.argv[1], float(sys.argv[2]), float(sys.argv[3]), float(sys.argv[4]), float(sys.argv[5]), sys.argv[6] +js = """ +const sleep = ms => new Promise(r => setTimeout(r, ms)); +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(1200); +await eda.dmt_EditorControl.zoomToRegion(%f, %f, %f, %f); +await sleep(1500); +const img = await eda.dmt_EditorControl.getCurrentRenderedAreaImage(); +const bytes = new Uint8Array(await new Response(img).arrayBuffer()); +let s=''; for (let i=0;i', out, os.path.getsize(out)) diff --git a/.claude/r2/_srch.js b/.claude/r2/_srch.js new file mode 100644 index 0000000..7d0b5f7 --- /dev/null +++ b/.claude/r2/_srch.js @@ -0,0 +1,10 @@ +const out = {}; +for (const q of ['C310989', 'F1206', 'FUSE 2A', '2A 1206 fuse']) { + try { + const r = await eda.lib_Device.search(q); + out[q] = (r || []).slice(0, 8).map(d => [d.name, d.uuid, d.libraryUuid, + (d.attributes && (d.attributes['Supplier Part'] || d.attributes['supplierId'])) || '', + (d.attributes && d.attributes['Value']) || '']); + } catch (e) { out[q] = 'ERR ' + String(e).slice(0, 120); } +} +return out; diff --git a/.claude/r2/_srch2.js b/.claude/r2/_srch2.js new file mode 100644 index 0000000..80e5cb6 --- /dev/null +++ b/.claude/r2/_srch2.js @@ -0,0 +1,9 @@ +const out = {}; +for (const q of ['F1206HC', 'F1206HC2A', 'Slow-Acting SMD fuse', '慢断 1206']) { + try { + const r = await eda.lib_Device.search(q); + out[q] = (r || []).slice(0, 12).map(d => [d.name, d.uuid, d.description || '', + JSON.stringify(d.attributes || {}).slice(0, 160)]); + } catch (e) { out[q] = 'ERR ' + String(e).slice(0, 120); } +} +return out; diff --git a/.claude/r2/_srch3.js b/.claude/r2/_srch3.js new file mode 100644 index 0000000..f39591a --- /dev/null +++ b/.claude/r2/_srch3.js @@ -0,0 +1,9 @@ +const out = {}; +for (const q of ['保险丝 2A', '贴片保险丝 2A', 'JFC1206', 'SMD1206 2A', '1206 2A 保险']) { + try { + const r = await eda.lib_Device.search(q); + out[q] = (r || []).filter(d => /2A|2\.0A/.test((d.description || '') + d.name)) + .slice(0, 10).map(d => [d.name, d.uuid, (d.description || '').slice(0, 90)]); + } catch (e) { out[q] = 'ERR ' + String(e).slice(0, 120); } +} +return out; diff --git a/.claude/r2/_srch4.js b/.claude/r2/_srch4.js new file mode 100644 index 0000000..44609a4 --- /dev/null +++ b/.claude/r2/_srch4.js @@ -0,0 +1,11 @@ +const seen = {}, hit = []; +for (const q of ['1206 保险丝', '保险丝', 'fuse 1206', '贴片式保险丝']) { + let r = []; + try { r = await eda.lib_Device.search(q) || []; } catch (e) {} + for (const d of r) { + if (seen[d.uuid]) continue; seen[d.uuid] = 1; + const s = (d.description || '') + ' ' + d.name; + if (/额定电流:2A|额定电流:2\.0A/.test(s)) hit.push([d.name, d.uuid, d.libraryUuid, (d.description||'').slice(0,110)]); + } +} +return { nSeen: Object.keys(seen).length, hit }; diff --git a/.claude/r2/_st.js b/.claude/r2/_st.js new file mode 100644 index 0000000..bbc82ec --- /dev/null +++ b/.claude/r2/_st.js @@ -0,0 +1,5 @@ +const cs = (await eda.sch_PrimitiveComponent.getAll()).filter(c => c.getState_ComponentType() === 'part'); +const cur = await eda.dmt_Schematic.getCurrentSchematicPageInfo(); +return { page: cur && cur.name, n: cs.length, + list: cs.map(c => [c.getState_Designator(), Math.round(c.getState_X()), Math.round(c.getState_Y()), + (c.getState_Component()||{}).name]) }; diff --git a/.claude/r2/a1_input.py b/.claude/r2/a1_input.py new file mode 100644 index 0000000..163ecae --- /dev/null +++ b/.claude/r2/a1_input.py @@ -0,0 +1,313 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A1-INPUT** 页：12V 入口链 + 输入侧检流 + 母线泄放。 + + /c/Python314/python .claude/r2/a1_input.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a1_input.py --push # 清页 + 重画（幂等） + +M3 的第一页。做法同 `b1_power.py`：**搬 R1 的版图，不重排** —— +R1 的 `P1-INPUT`（`9a6096762e036e23`）整页读回在 `_p1_live.json`， +本脚本按下面三条改，其余坐标一个字不动。 + +| | 内容 | +|---|---| +| **删** | `U19` 3V3 Buck 那一块（`U19` `C7` `L2` `C9` `C10` `R2` `R3` `C8`，8 件）→ 挪到 **`A2-AUX`**，和 `U30` 5V Buck 放一页 | +| **加** | 入口链三个节点的**网络名**：`VIN_RAW`（J1→F1）/ `VIN_FUSED`（F1→Q1 源）/ `VIN_SW`（Q1 漏→Rs6）| +| **换** | 文字整套重写（见下） | + +位号沿用 R1（`J1` `F1` `Q1` `D1` `DZ1` `R1` `C1~C6` `U13` `Rs6` `U29` `R4~R6` `Q3` `R9A~E` `C11`）， +方案文档 §4 的 BOM 归属表就是这么写的。`R2`/`R3` 留给 `A2-AUX`。 + +## 为什么要给入口链三个节点起名 + +R1 上这三段是**无名网络**，PCB 侧只能按 `$1N223` / `$1N227` / `$1N236` 认 —— +第三十四轮那次「+12V 从 4 个碎片炸成 23 个」的假象就出在这一带。 +底板的这一段要过 **9 A**、要铺铜 + 断面校核（方案文档 §6.4）， +按名字认比按 `$1N…` 认稳得多。三面旗都是 `Power` 型，天然单实例， +已进 `xpage.py` 的 `NAMING_ONLY`。 + +## ⚠ 两条从 R1 带过来、必须知道的 + +1. **`J1` 是圆形 DC 座，不是 XT30**：脚 1 = 中心极正，脚 2/3 = 负极静/动触点， + 两个都接地并联降接触电阻。R1 页上那句 `J1: 1 = GND(-) 2 = +12V(+)` 是**换座之前的旧文字**， + 本页已改正。⚠ DC-005 家族额定 2~5 A 而整机最坏 9.99 A —— 已知风险、用户明确接受。 +2. **`BLD_REF` 端口与 `R4.1` 同坐标**（`(80,235)`）—— CLAUDE.md 点名的那类坑。 + 这里是安全的：`R4.1`→`R5.2` 之间**有一段真导线**，端口落在它的端点上，不是零长度。 + 脚本里有断言盯着这一处，重画之后仍然要看 `verify_sch` 的 `BLD_REF` 那一行。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, _on, call # noqa: E402 + +PAGE, NAME = '9d86e72abb1a6571', 'A1-INPUT' +R2_PROJECT = '05a65c22f14846b8b95360ef8d3c1e2e' +SRC = os.path.join(HERE, '_p1_live.json') + +# ── 挪到 A2-AUX 的 3V3 Buck 那一块 ────────────────────────────────── +DROP = set(['U19', 'C7', 'L2', 'C9', 'C10', 'R2', 'R3', 'C8']) + +# ── 入口链三个节点：起名 + 挂旗的位置（支线从既有导线上分叉出来）────── +# (网名, 分叉点, 旗点, 旗 rot)；rot 180 = Power 旗的符号朝下 +NEW_FLAGS = [ + # ⚠ VIN_RAW 一开始放在 (190,660)，正好压在 J1.3 那面 GND 旗 (185,665) 上 —— + # crossings() 查不出来（旗不是导线），是 flag_clash() 抓到的。 + ('VIN_RAW', (225, 710), (225, 650), 180), + ('VIN_FUSED', (390, 650), (390, 610), 180), + ('VIN_SW', (830, 770), (830, 690), 180), +] +# 每个新网络用一个「标志引脚」认出它属于哪个既有导线组 +SIG_PIN = {'VIN_RAW': 'F1.1', 'VIN_FUSED': 'F1.2', 'VIN_SW': 'Rs6.1'} + +# ⚠ 文字全部塞进「删掉 3V3 Buck 之后空出来的那一带」（x 60~760 / y 330~570）。 +# R1 原来把说明压在元件行上（y 700~790 与 y 190~270），本页元件位置一个没动， +# 照抄文字坐标就会盖在 J1/F1/Q1/D1/C2 和 R4/R5/R6/U29 上 —— 已经踩过一次。 +TEXTS = [ + (60, 795, u'【A1-INPUT】底板 12V 入口：DC 座 → 保险 → 反接保护 → 储能 → 检流；外加 12V 母线泄放', 14), + (60, 560, u'【A】输入保护 / 缓启动：J1 → F1 12A → Q1 AO4407 反接保护，栅极 RC 缓启动 tau = R1*C1 = 10ms', 11), + (60, 543, u'J1 是圆形 DC 座 DC-005-5.5*2.5：脚1 = 中心极(正) → F1；脚2/3 = 负极静/动触点，两个都接地并联降接触电阻', 10), + (60, 526, u'⚠ DC-005 家族额定 2~5A，而整机最坏 9.99A（设计文档 §22.6）—— 已知风险、用户明确接受：', 10), + (60, 509, u' 发热点在插头内芯与弹片的接触面，板上加铜救不了。装配前用表核脚序：无插头时 2-3 导通、1 对 2/3 断开', 10), + (60, 482, u'【E】入口储能与钳位：D1 SMBJ13A 钳位 21.5V；C2/C3 470µF + C4/C5 10µF + C6 100nF', 11), + (60, 465, u'入口链三个节点已命名：VIN_RAW（J1→F1）/ VIN_FUSED（F1→Q1 源）/ VIN_SW（Q1 漏→Rs6）；', 10), + (60, 448, u' 这一段过 9A，PCB 上要铺铜 + 断面校核（方案 §6.4，≥8mm 净铜宽）', 10), + (60, 421, u'【B】12V 母线泄放（防 USB 反灌抬高母线）', 11), + (60, 404, u'阈值 = 2.495V x (R4+R5)/R5 = 2.495 x 5.32 = 13.27V；TL431 导通时阴极 2.0~2.2V → Q3 Vgs = -9.8V 全导通', 10), + (60, 387, u'R9A~R9E: 5 x 2Ω 2512 串联 = 10Ω/10W，高 0.8mm（立式水泥电阻站起来超高度预算）', 10), + (60, 370, u'泄放为突发额定：13.3V 下 1.33A / 17.7W，持续故障由固件关 VBUS 兜底', 10), + (60, 343, u'【C】3V3 辅助电源（U19/L2/C7/C9/C10/R2/R3/C8）已挪到 A2-AUX，和 12V→5V 的 U30 放同一页', 11), + (620, 245, u'【D】输入侧电流 / 电压监测（整板功率预算）', 11), + (620, 228, u'Rs6 5mΩ：满板约 9A → 45mV（INA226 满量程 81.92mV / 分辨率 0.5mA）', 10), + (620, 211, u'U13 地址 A1=GND、A0=SCL → 0x43（地址表不是顺排）。挂 I2C 主干，不经 TCA9548A', 10), + (620, 194, u'体电容在 Rs6 上游；PCB 上 Rs6 放在体电容与五槽分叉点之间，Kelvin 四线焊盘', 10), +] + + +def load(): + u"""读回 R1 的 P1-INPUT，拆成「导线组 → 网络名」。""" + src = json.load(io.open(SRC, encoding='utf-8')) + pts = src['wires'] + segs = [((int(round(pts[i][0])), int(round(pts[i][1]))), + (int(round(pts[i + 1][0])), int(round(pts[i + 1][1])))) + for i in range(0, len(pts), 2)] + for a, b in segs: + assert a != b, u'源页有零长度导线 %s（skill §8a）' % (a,) + assert (a[0] == b[0]) != (a[1] == b[1]), u'源页有斜线 %s-%s' % (a, b) + + n = len(segs) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2 = segs[i] + b1, b2 = segs[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + + pins = {} # 位号 -> {脚号: (x,y)} + pinat = {} # (x,y) -> '位号.脚号' + pinname = {} # 位号 -> {脚号: 脚名} + for p in src['parts']: + d = p[0] + pins[d] = dict((str(q[0]), (int(round(q[2])), int(round(q[3])))) for q in p[9]) + pinname[d] = dict((str(q[0]), q[1]) for q in p[9]) + for q in p[9]: + pinat[(int(round(q[2])), int(round(q[3])))] = '%s.%s' % (d, q[0]) + + # 组 -> 名字 / 组 -> 引脚 + gname, gpins = defaultdict(set), defaultdict(set) + for it, key in [(src['flags'], 1), (src['ports'], 1)]: + for f in it: + xy = (int(round(f[2])), int(round(f[3]))) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'旗/端口 %s @%s 不在任何导线上' % (f[key], xy) + gname[find(hit[0])].add(f[key]) + for d, ps in pins.items(): + for num, xy in ps.items(): + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'源页悬空引脚 %s.%s @%s' % (d, num, xy) + gpins[find(hit[0])].add('%s.%s' % (d, num)) + return src, segs, find, pins, pinat, pinname, gname, gpins + + +def build(): + src, segs, find, pins, pinat, pinname, gname, gpins = load() + + # ── 1. 判断每个导线组是留是删（必须整组同进退）─────────────────── + keep_grp = {} + for r_, ps in gpins.items(): + owners = set(p.split('.')[0] for p in ps) + kept, dropped = owners - DROP, owners & DROP + assert not (kept and dropped), \ + u'导线组同时挂着留下的 %s 和删掉的 %s，不能整组同进退' % (sorted(kept), sorted(dropped)) + keep_grp[r_] = bool(kept) + for i in range(len(segs)): + assert find(i) in keep_grp, u'有导线组一个引脚都不挂：%s' % (segs[i],) + + # ── 2. 给每个留下的组定网络名 ─────────────────────────────────── + sig2net = dict((v, k) for k, v in SIG_PIN.items()) + gnet = {} + for r_, keep in keep_grp.items(): + if not keep: + continue + names = gname.get(r_, set()) + forced = [sig2net[p] for p in gpins[r_] if p in sig2net] + if forced: + assert not names, u'组 %s 本来就有名字 %s，不该再起名' % (sorted(gpins[r_]), names) + assert len(set(forced)) == 1, forced + gnet[r_] = forced[0] + elif not names: + # R1 上本来就无名的短节点（泄放 MOS 漏极、R9A~E 之间的 4 个串联节点）。 + # 这些段只走 1.33A 突发、走线两三毫米，不铺铜也不做断面校核， + # 沿用 R1 的「让 EasyEDA 自动起名」。`#` 开头的名字只给本地自检用，不下发。 + gnet[r_] = '#' + '+'.join(sorted(gpins[r_])[:2]) + else: + assert len(names) == 1, \ + u'组 %s 的名字不唯一：%s' % (sorted(gpins[r_])[:4], sorted(names)) + gnet[r_] = sorted(names)[0] + + s = Sheet(PAGE, NAME) + for i, (a, b) in enumerate(segs): + r_ = find(i) + if keep_grp[r_]: + s.w(gnet[r_], a, b) + + # ── 3. 旗 / 端口：删掉挂在被删组上的 ───────────────────────────── + def kept_at(xy): + hit = [i for i in range(len(segs)) if _on(xy, segs[i][0], segs[i][1])] + return keep_grp[find(hit[0])] if hit else False + + for f in src['flags']: + xy = (int(round(f[2])), int(round(f[3]))) + if kept_at(xy): + # 读回来的符号名是 'Ground-GND' / 'Power-5V'，createNetFlag 只认前缀 + s.F.append([f[0].split('-')[0], f[1], xy[0], xy[1], f[4]]) + for p in src['ports']: + xy = (int(round(p[2])), int(round(p[3]))) + if kept_at(xy): + s.PT.append([p[0].replace('Netport-', ''), p[1], xy[0], xy[1], p[4]]) + + # ── 4. 入口链三个节点起名：从既有导线上分叉出一小段，挂 Power 旗 ── + for net, tap, flag, rot in NEW_FLAGS: + sig = SIG_PIN[net] + onseg = [i for i in range(len(segs)) if _on(tap, segs[i][0], segs[i][1])] + assert onseg, u'%s 的分叉点 %s 不在任何导线上' % (net, tap) + assert gnet.get(find(onseg[0])) == net, \ + u'%s 的分叉点 %s 落在了 %s 上' % (net, tap, gnet.get(find(onseg[0]))) + assert sig in gpins[find(onseg[0])], u'%s 的组里没有 %s' % (net, sig) + assert tap not in pinat, u'%s 的分叉点压在引脚 %s 上' % (net, pinat[tap]) + s.w(net, tap, flag) + s.pwr(net, flag[0], flag[1], rot) + + for t in TEXTS: + s.txt(t[0], t[1], t[2], t[3]) + + place, exp = [], {} + from schcheck import PARTS + byname = {} + for k, v in PARTS.items(): + byname.setdefault(v['name'], k) + for p in src['parts']: + d, nm = p[0], p[1] + if d in DROP: + continue + base = nm.split('_C')[0] if '_C' in nm else nm + k = byname.get(nm) or byname.get(base) + assert k, u'eda-parts.json 里找不到器件 %r（%s）' % (nm, d) + assert not p[6], u'%s 是镜像件，Sheet.place 处理不了' % d + place.append([d, k, int(round(p[3])), int(round(p[4])), p[5]]) + exp[d] = dict((str(q[0]), (int(round(q[2])), int(round(q[3])))) for q in p[9]) + + # CLAUDE.md 点名的那一处：端口与引脚同坐标，靠一段真导线兜着 + assert ('BLD_REF', 80, 235) in [(x[1], x[2], x[3]) for x in s.PT], \ + u'BLD_REF @(80,235) 那个端口丢了' + assert any(_on((80, 235), a, b) and a != b for a, b, _ in s.W), \ + u'BLD_REF @(80,235) 底下没有真导线 —— 就是 CLAUDE.md 说的零长度那类坑' + + return s, place, exp, pinname + + +def text_clash(s, exp): + u"""文字压在导线 / 引脚 / 旗端口上 —— schcheck 只查右边界，这一条是本页新加的。 + + 宽度按 skill §12 的经验值（全角 = 字号，半角 = 半个字号）， + 高度保守地取 ±0.8 字号。宁可误报，也不要再出现「说明盖住 J1/F1/Q1」那种图。 + """ + errs = [] + boxes = [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + w = size * (cjk + 0.5 * (len(txt) - cjk)) + boxes.append((x, y - size * 0.8, x + w, y + size * 0.8, txt)) + + pts = [] + for d, ps in exp.items(): + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + + for x0, y0, x1, y1, txt in boxes: + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:26])) + for a, b, net in s.W: + if a[1] == b[1]: # 横线 + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (net, a[1], txt[:26])) + else: # 竖线 + if x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (net, a[0], txt[:26])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + u"""两面旗/端口的**符号**叠在一起 —— crossings() 查不到（旗不是导线）。 + + 判据按符号尺寸定，不是按标签：一格（10）以内上下叠 **且** 横向也挨着才算叠。 + 同一个 x 上下差一格排开（R1 的 `BLD_REF`/`BLD_A` 就是这么放的）是正常写法，不报。 + """ + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +def main(): + push = '--push' in sys.argv + s, place, exp, _pinname = build() + s.assert_grid() + errs = s.netcheck(exp, {}, set(['GND', '+12V', '+3V3', 'GATE', + 'BLD_A', 'BLD_REF'])) + errs += text_clash(s, exp) + flag_clash(s) + print(u'搬 R1 P1-INPUT：%d 件（删掉 3V3 Buck 那 %d 件）' % (len(place), len(DROP))) + s.report(len(place), errs) + if not push: + return + call("await eda.dmt_Project.openProject('%s'); await new Promise(r=>setTimeout(r,2500)); return 1;" + % R2_PROJECT) + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a2_aux.py b/.claude/r2/a2_aux.py new file mode 100644 index 0000000..8d2b820 --- /dev/null +++ b/.claude/r2/a2_aux.py @@ -0,0 +1,355 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A2-AUX** 页：两路辅助电源 12V→3V3（U19）与 12V→5V（U30）。 + + /c/Python314/python .claude/r2/a2_aux.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a2_aux.py --push # 清页 + 重画（幂等） + +M3 的第二页。**两块都是从 R1 搬过来的**，各自整块平移，块内坐标一个字不动： + +| 块 | 来源 | 平移 | +|---|---|---| +| 3V3（`U19` `C7` `C8` `C9` `C10` `L2` `R2` `R3`）| R1 `P1-INPUT`，正是 `a1_input.py` 里 `DROP` 掉的那 8 件 | 上移 230 | +| 5V（`U30` `C731~C733` `L3` `C734/C735` `R706/R707`）| R1 `P1B-5V` 整页 | 下移 110 | + +两块原来的 y 都在 390 附近、x 有 460~795 的重叠段，**不平移就是叠在一起**。 +平移量按两块的实测 bbox 算出来（3V3 块 x100~795 / y390~535，5V 块 x460~900 / y390~665）， +脚本里 `assert_no_overlap()` 每次都重算一遍，改坐标改出重叠会当场终止。 + +## 一处改名：`BST` → `BST3V3` + +R1 的 3V3 块把三个内部节点用端口起了名：`SW3V3` / `FB3V3` / **`BST`**。 +前两个带了后缀，第三个没有。现在**两个 Buck 同页**，隔壁 5V 那颗的自举节点就在旁边， +`BST` 这个名字会变成一个等着人踩的坑（下一页随手写个 `BST` 就静默并网了）。⇒ 加后缀。 + +5V 那三个内部节点（SW / BST / FB）**沿用 R1 不起名**：那一块是紧凑画法、 +三个节点各自只有两三厘米导线，不跨页也不铺铜，没有 `A1-INPUT` 里 `VIN_*` 那种理由。 + +## 本页不含的两件事 + +- `U31` AMS1117-3.3（Hub 专用 3V3）在 **`A4-HUB`** —— R1 的 P1B-5V 页上有两行讲它的文字， + 是**说明**不是电路，本页把这两行改写成「它不在这页」。 +- `+5V` 的去处（Hub `U32` + 五个槽的 VBUS）在 `A4-HUB` / `A5-SLOTS`。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, _on, call, PARTS # noqa: E402 + +PAGE, NAME = '3361444ab04474c5', 'A2-AUX' +R2_PROJECT = '05a65c22f14846b8b95360ef8d3c1e2e' + +SRC_3V3 = os.path.join(HERE, '_p1_live.json') # R1 P1-INPUT，只取 3V3 那一块 +SRC_5V = os.path.join(HERE, '_p1b_live.json') # R1 P1B-5V，整页 +KEEP_3V3 = set(['U19', 'C7', 'L2', 'C9', 'C10', 'R2', 'R3', 'C8']) + +OFF_3V3 = (0, 230) # 3V3 块整体上移，坐到页面上半 +OFF_5V = (0, -110) # 5V 块整体下移 +NET_RENAME = {'BST': 'BST3V3'} + +# ── 5V 块唯一一处挪位：C733 左移 40（平移之后的坐标）────────────────── +# R1 那一页上 C733 紧贴 U30 左边，**「100nF」这个值标签正好压在「U30」位号上**， +# 渲染出来是「100uF0」—— 自举电容的值被读错就是另一颗器件了，属于必须修的那种叠字。 +# 只动这一颗和它自己的两根短脚线，U30 / C731 / C732 / L3 全部原地不动。 +# ⚠ 不要顺手把 (550,490) 也remap 掉：那是 SW 竖线的分叉点， +# 挪了它 SW 与 +12V 的交叉点会从离 C731.1 的 10 变成离 C732.1 的 10，更糟。 +C733_DX = -40 +WIRE_EDITS = [ # (旧段, 新段)，必须一一命中 + (((550, 500), (550, 490)), ((510, 500), (510, 490))), + (((550, 490), (565, 490)), ((510, 490), (565, 490))), + (((550, 540), (550, 550)), ((510, 540), (510, 550))), + (((660, 550), (550, 550)), ((660, 550), (510, 550))), +] + +# ── 3V3 块同类的一处叠字：`BST3V3` / `FB3V3` 两个端口的标签压住 C7 的「2.2uF」── +# 端口的符号 + 标签往锚点**左边**伸出去约 70 个单位（实测），而 C7 的标签在 x 113~134。 +# ⇒ 把两个端口往右挪到 225、顺带把夹在中间的 +12V 旗挪到 245（三者互相让开 ≥20）。 +# 导线只是缩短，U19 侧的端点一个没动。 +EDITS_3V3_W = [ + (((265, 690), (175, 690)), ((265, 690), (225, 690))), + (((265, 710), (195, 710)), ((265, 710), (225, 710))), + (((265, 700), (235, 700)), ((265, 700), (245, 700))), +] +EDITS_3V3_PT = {('BST3V3', 175, 690): 225, ('FB3V3', 195, 710): 225} +EDITS_3V3_F = {('+12V', 235, 700): 245} + +TEXTS = [ + (45, 795, u'【A2-AUX】底板辅助电源：12V→3V3（U19，给 ESP32 与全部逻辑）+ 12V→5V（U30，给 Hub 与手机 VBUS）', 14), + (45, 545, u'【A】12V → 3V3 / 500mA', 11), + (45, 528, u'U19 LMR51430YDDCR，Vref 0.6V，', 10), + (45, 511, u'R2/R3 = 100k/22.1k → 3.315V', 10), + (45, 494, u'EN 绝对最大 = VIN+0.3V，可直接接 VIN', 10), + (45, 477, u'Y 后缀 = 1.1MHz（已复核 SLUSEF4A）', 10), + (45, 450, u'【B】12V → 5V / 2A', 11), + (45, 433, u'U30 与 U19 同料号，Vref 0.6V，', 10), + (45, 416, u'R706/R707 = 100k/13.7k → 4.98V', 10), + (45, 399, u'L3 = SPM6530T-4R7M（与刀片 L1 同料）', 10), + (45, 382, u'1.1MHz 下 ΔIL = 0.56A，2A 负载', 10), + (45, 365, u'峰值 2.28A << Isat 6.2A', 10), + (45, 265, u'5V 负载：正常 <0.5A（关充电后手机基本不从 VBUS 取电）；最坏 2.8A（五路 input_suspend 全失效）', 10), + (45, 248, u'⚠ 两条轨都直接吃 +12V —— 是 Q1 反接保护之后、Rs6 检流之后的那一段，不依赖任何一路手机输出', 10), + (45, 231, u'⚠ Hub 专用的 U31 AMS1117-3.3 不在本页，在 A4-HUB：它只给 U32 供电（满配约 420mA），挂不到 U19 这条 0.5A 轨上', 10), + (45, 214, u'内部节点：3V3 侧用端口起了名（SW3V3 / BST3V3 / FB3V3）；5V 侧沿用 R1 不起名 —— 紧凑画法，三个节点各自只有两三厘米导线', 10), +] + + +def load(path, keep, off): + u"""读回一页，按 keep 过滤，整块平移。返回 (导线[(a,b,net)], 旗, 端口, place, expect)。 + + ⚠ 过滤的判据是「导线组里的引脚属于谁」，不是坐标框 —— 坐标框会把别人的线一起切走。 + """ + src = json.load(io.open(path, encoding='utf-8')) + dx, dy = off + pts = src['wires'] + segs = [((int(round(pts[i][0])) + dx, int(round(pts[i][1])) + dy), + (int(round(pts[i + 1][0])) + dx, int(round(pts[i + 1][1])) + dy)) + for i in range(0, len(pts), 2)] + for a, b in segs: + assert a != b, u'%s 有零长度导线 %s（skill §8a）' % (path, (a,)) + assert (a[0] == b[0]) != (a[1] == b[1]), u'%s 有斜线 %s-%s' % (path, a, b) + + n = len(segs) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2 = segs[i] + b1, b2 = segs[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + + gname, gowner, gpins = defaultdict(set), defaultdict(set), defaultdict(set) + for lst, strip in ((src['flags'], False), (src['ports'], True)): + for f in lst: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'%s 的旗/端口 %s 不在任何导线上' % (path, f[1]) + gname[find(hit[0])].add(NET_RENAME.get(f[1], f[1])) + for p in src['parts']: + for q in p[9]: + xy = (int(round(q[2])) + dx, int(round(q[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'%s 源页悬空引脚 %s.%s' % (path, p[0], q[0]) + gowner[find(hit[0])].add(p[0]) + gpins[find(hit[0])].add('%s.%s' % (p[0], q[0])) + + keepgrp = {} + for r_, owners in gowner.items(): + inside, outside = owners & keep, owners - keep + assert not (inside and outside), \ + u'%s 的导线组同时挂着 %s 和 %s，切不开' % (path, sorted(inside), sorted(outside)) + keepgrp[r_] = bool(inside) + + W, F, PT = [], [], [] + for r_, ok in keepgrp.items(): + if not ok: + continue + names = gname.get(r_, set()) + assert len(names) <= 1, u'组 %s 名字不唯一：%s' % (sorted(gpins[r_])[:3], sorted(names)) + # 无名的短节点（5V 那颗的 SW / BST / FB）沿用 R1 的自动命名， + # `#` 开头的名字只给本地自检用，不下发。 + net = sorted(names)[0] if names else '#' + '+'.join(sorted(gpins[r_])[:2]) + for i in range(n): + if find(i) == r_: + W.append((segs[i][0], segs[i][1], net)) + + def kept_at(xy): + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + return keepgrp[find(hit[0])] if hit else False + + for f in src['flags']: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + if kept_at(xy): + F.append([f[0].split('-')[0], NET_RENAME.get(f[1], f[1]), xy[0], xy[1], f[4]]) + for p in src['ports']: + xy = (int(round(p[2])) + dx, int(round(p[3])) + dy) + if kept_at(xy): + PT.append([p[0].replace('Netport-', ''), NET_RENAME.get(p[1], p[1]), + xy[0], xy[1], p[4]]) + + byname = {} + for k, v in PARTS.items(): + byname.setdefault(v['name'], k) + place, exp = [], {} + for p in src['parts']: + d, nm = p[0], p[1] + if d not in keep: + continue + base = nm.split('_C')[0] if '_C' in nm else nm + k = byname.get(nm) or byname.get(base) + assert k, u'eda-parts.json 里找不到器件 %r（%s）' % (nm, d) + assert not p[6], u'%s 是镜像件，Sheet.place 处理不了' % d + place.append([d, k, int(round(p[3])) + dx, int(round(p[4])) + dy, p[5]]) + exp[d] = dict((str(q[0]), (int(round(q[2])) + dx, int(round(q[3])) + dy)) + for q in p[9]) + return W, F, PT, place, exp + + +def bbox(W, F, PT, exp): + xs, ys = [], [] + for a, b, _ in W: + xs += [a[0], b[0]] + ys += [a[1], b[1]] + for it in F + PT: + xs.append(it[2]) + ys.append(it[3]) + for ps in exp.values(): + for xy in ps.values(): + xs.append(xy[0]) + ys.append(xy[1]) + return min(xs), max(xs), min(ys), max(ys) + + +def assert_no_overlap(b1, b2, gap=40): + u"""两块的包围盒必须分开 —— 平移量改错了当场终止，别等截图。""" + ax0, ax1, ay0, ay1 = b1 + bx0, bx1, by0, by1 = b2 + sep_x = ax1 + gap <= bx0 or bx1 + gap <= ax0 + sep_y = ay1 + gap <= by0 or by1 + gap <= ay0 + assert sep_x or sep_y, \ + u'两块重叠：3V3 x%d..%d y%d..%d vs 5V x%d..%d y%d..%d' % ( + ax0, ax1, ay0, ay1, bx0, bx1, by0, by1) + + +def text_clash(s, exp): + u"""文字压在导线 / 引脚 / 旗端口上（同 a1_input.py，本页照用）。""" + errs = [] + boxes = [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + w = size * (cjk + 0.5 * (len(txt) - cjk)) + boxes.append((x, y - size * 0.8, x + w, y + size * 0.8, txt)) + pts = [] + for d, ps in exp.items(): + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + for x0, y0, x1, y1, txt in boxes: + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:26])) + for a, b, net in s.W: + if a[1] == b[1]: + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (net, a[1], txt[:26])) + else: + if x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (net, a[0], txt[:26])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + u"""两面旗/端口的符号叠在一起（同 a1_input.py）。""" + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +def edit_wires(W, edits): + u"""按 (旧段 → 新段) 表改导线，**每一条都必须命中**（改错坐标当场终止）。""" + norm = lambda s: (min(s[0], s[1]), max(s[0], s[1])) + todo = dict((norm(o), n) for o, n in edits) + out = [] + for a, b, net in W: + k = norm((a, b)) + if k in todo: + na, nb = todo.pop(k) + out.append((na, nb, net)) + else: + out.append((a, b, net)) + assert not todo, u'导线改动表有没命中的段：%s' % sorted(todo) + return out + + +def tweak_c733(W, place, exp): + u"""把 C733 连同它自己的两根短脚线左移 40，解开与 U30 位号的叠字。""" + out = edit_wires(W, WIRE_EDITS) + for it in place: + if it[0] == 'C733': + it[2] += C733_DX + exp['C733'] = dict((k, (v[0] + C733_DX, v[1])) for k, v in exp['C733'].items()) + return out + + +def tweak_3v3(W, F, PT): + u"""把 BST3V3 / FB3V3 两个端口和夹在中间的 +12V 旗往右挪开 C7 的标签。""" + out = edit_wires(W, EDITS_3V3_W) + for lst, table in ((PT, EDITS_3V3_PT), (F, EDITS_3V3_F)): + hit = 0 + for it in lst: + key = (it[1], it[2], it[3]) + if key in table: + it[2] = table[key] + hit += 1 + assert hit == len(table), u'旗/端口挪位表只命中 %d/%d' % (hit, len(table)) + return out + + +def build(): + a = load(SRC_3V3, KEEP_3V3, OFF_3V3) + a = (tweak_3v3(a[0], a[1], a[2]),) + a[1:] + src5 = json.load(io.open(SRC_5V, encoding='utf-8')) + all5 = set(p[0] for p in src5['parts']) + b = load(SRC_5V, all5, OFF_5V) + b = (tweak_c733(b[0], b[3], b[4]),) + b[1:] + assert_no_overlap(bbox(*a[:3], exp=a[4]), bbox(*b[:3], exp=b[4])) + + dup = set(a[4]) & set(b[4]) + assert not dup, u'两块位号撞车：%s' % sorted(dup) + + s = Sheet(PAGE, NAME) + for W, F, PT, _pl, _ex in (a, b): + for seg in W: + s.W.append(seg) + s.F += F + s.PT += PT + for t in TEXTS: + s.txt(t[0], t[1], t[2], t[3]) + + place = a[3] + b[3] + exp = dict(a[4]) + exp.update(b[4]) + return s, place, exp + + +def main(): + push = '--push' in sys.argv + s, place, exp = build() + s.assert_grid() + # 两块之间只靠 +12V / GND 两条电源旗成网，导线上天然分块 + errs = s.netcheck(exp, {}, set(['GND', '+12V', '+3V3', 'SW3V3', 'FB3V3', 'BST3V3'])) + errs += text_clash(s, exp) + flag_clash(s) + print(u'3V3 块 %d 件 + 5V 块 %d 件 = %d 件' + % (len(KEEP_3V3), len(place) - len(KEEP_3V3), len(place))) + s.report(len(place), errs) + if not push: + return + call("await eda.dmt_Project.openProject('%s'); await new Promise(r=>setTimeout(r,2500)); return 1;" + % R2_PROJECT) + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a3-ctrl-nc.json b/.claude/r2/a3-ctrl-nc.json new file mode 100644 index 0000000..5209c05 --- /dev/null +++ b/.claude/r2/a3-ctrl-nc.json @@ -0,0 +1,30 @@ +{ + "U20": [ + "15", + "16", + "24", + "25", + "26", + "28", + "29", + "30" + ], + "U35": [ + "15", + "16", + "17", + "18", + "19", + "20" + ], + "U6": [ + "1", + "2" + ], + "U7": [ + "1", + "2", + "3", + "4" + ] +} \ No newline at end of file diff --git a/.claude/r2/a3_ctrl.py b/.claude/r2/a3_ctrl.py new file mode 100644 index 0000000..ae4e862 --- /dev/null +++ b/.claude/r2/a3_ctrl.py @@ -0,0 +1,740 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A3-CTRL** 页：ESP32-S3 主控 + TCA9548A I²C 多路 + DAC63204 ×2 + 应急 UART。 + + /c/Python314/python .claude/r2/a3_ctrl.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a3_ctrl.py --push # 清页 + 重画（幂等） + +四页并行设计里的第三页。跨页网络名 / 位号区段 / 端口方向以 `.claude/r2/A-CONTRACT.md` 为准。 + +## 页面分区 + +| 区 | 位置 | 内容 | +|---|---|---| +| A | 左上 x37..600 y370..812 | `U20` ESP32-S3-WROOM-1 + 3V3 去耦（C601/C602）+ EN 上电复位（R601/C603）+ 26 根信号引出 | +| B | 左下 x35..245 y85..380 | 上拉电阻组 R602~R611（I²C 主干 ×2、INT#、INA_ALERT、PRSNT1#~5#、MUX_RST#）| +| C | 中部 x303..570 y395..480 | `J33` 应急 UART 排针（GND/TXD0/RXD0/EN/IO0），塞在 U20 与 U35 之间那条空带 | +| D | 中下 x246..612 y185..440 | `U35` TCA9548A（0x70）+ VCC 去耦 C604 | +| E | 右下 x613..1133 y200..440 | `U6` DAC63204（0x4A）整块从 R1 P3B 搬来 | +| F | 右上 x613..1133 y470..710 | `U7` DAC63204（0x4B）整块从 R1 P3B 搬来 | + +## 从 R1 搬了什么、丢了什么 + +- **ESP32 那一块没有整块 `load()` 搬**，只照抄了 U20 / C601 / C602 / R601 / C603 + 五件的**电气拓扑**（3V3 去耦 + EN 的 10k/100nF 上电复位），导线重画。 + 理由：R2 的信号集合和 R1 完全不是一回事（去掉 J22、RT601/602、KEY_*、VBUS_EN*、 + BUCK_PG，加上 PRSNT#×5、MUX_RST#、HUB_RST），26 根引出线要重新指派引脚， + 把 R1 的线搬过来再逐条改名比重画更容易出错。位置也重排过：R1 的 R601/C603 在 x=120， + 搬到 x=130 之后位号文字（画在符号右侧）会顶到 U20 的符号体（x≥205），所以整列重摆。 +- **两颗 DAC 是真·整块搬**（`load()`，见下），U23 PCA9555 及其外围一件不要。 + +## DAC 两块的平移量与「为什么不能并排放在底部」 + +R1 `P3B-EXPAND` 的 DAC 区是一条 **x33..1123 × y220..460 的横带**（含旗/端口符号）， +整条搬过来会横穿 U20 的地线（U20 的 GND/EPAD 引出到 x=320、y380..440）， +而且源坐标 `(310,430)` 那条竖线的**端点**正好落在 U20 地线的 y=430 横段上 —— +那不是"交叉"，是 **T 型相连 = 把 GND 短到 DAC 的 EP 网络上**。所以必须拆成两块竖着摞： + +| 块 | 平移 | 落位 | +|---|---|---| +| U6（源 x33..553 / y220..460）| dx=+580 dy=−20 | x613..1133 / y200..440 | +| U7（源 x563..1123 / y220..460）| dx=+50 dy=+250 | x613..1133 / y470..710 | + +dy 的下界是**标题栏**：U6 的 `VDAC4` 端口在源坐标 (480,260)，dy 再小 8 个单位 +它就掉进 `x>455 且 y<192` 的标题栏里（skill §8c）。`build()` 里逐个断言了这一条。 + +## ⭐ GPIO 重新指派（本页最要紧的一件事） + +R1 的 `.claude/_esp32_pinmap.json:new` **不能直接用**：那张表里 5 个 `VBUS_EN*` +和 4 个 `KEY_*` 的脚在 R2 全部空出来了（D9 作废 74HC595、VBUS_EN 挪到刀片）， +而 R2 新增了 `PRSNT1#~5#`、`MUX_RST#`。逐条复核后重排，结果写进 `PINMAP` 表， +并同步写回 `_esp32_pinmap.json` 的 `"r2_base"` 键（不动 `new`/`old`/`pin2io`）。 + +硬约束（逐条对着 ESP32-S3 数据手册核过）： + +1. **`NTC1`/`NTC2` 必须落在 ADC1**（IO1~IO10；ADC2 与 WiFi 共用，开 WiFi 后读不到）。 + ⇒ `NTC1=IO1`（模组脚 39）、`NTC2=IO2`（脚 38），和 R1 一致。 +2. **flash/PSRAM 占用的脚**：ESP32-S3-WROOM-1 模组把 SPI flash 的 IO26~IO32 根本没引出 + ——符号 41 个脚里查不到这几个（实测 `_p3_live.json`），所以不用躲。 + **IO35/IO36/IO37 引出来了，但 R8（八线 PSRAM）版本用它们做 PSRAM 的 D4~D7。** + ⚠ **本页按「可能上 R8 版」保守处理：IO35/36/37 一律不接**（进 NC 表）。 + ⇒ **待确认项**：若最终确定选 N8（四线 PSRAM 或无 PSRAM）版，这三个脚可放出来当 GPIO。 + 不接的代价只是少三个备用脚；接了再换 R8 版就是死机 —— 所以往保守一侧倒。 +3. **strapping 脚**：IO0 / IO3 / IO45 / IO46。 + - `IO0` 给 J33 第 5 脚（进下载模式用）—— 模组内部有上拉，排针悬空 = 高 = 正常启动 ✓ + - `IO3`(JTAG_SEL) / `IO45`(VDD_SPI 电压) / `IO46`(ROM 打印) **一律不接**， + 悬空时靠内部弱下拉取默认值，是出厂推荐状态。 +4. **只输入的脚**：IO46 在 S3 上是 input-only，且它是 strapping —— 已归入不接。 +5. **原生 USB 硬连线**：`IO19 = USB_D−`、`IO20 = USB_D+`（模组脚 13 / 14，脚名与脚号 + 实测自 `_p3_live.json`，没有猜）。这两根不走 GPIO matrix，改不了。 + ⇒ `USB6_DM=IO19`、`USB6_DP=IO20`（契约 §1.2 同样这么写）。 +6. 其余信号全部走 GPIO matrix，落哪个脚都行 ⇒ 按「出线方向 = 目的地」排： + 低位脚（IO38~IO42，符号下缘）给往页面下方去的 I²C 与 MUX / 中断簇， + 高位脚（IO4~IO18，符号上缘）给 EFUSE_EN / PRSNT / FAN 这些纯端口信号。 + +**引脚够不够**：模组引出 34 个 IO，扣掉 6 个 strapping/PSRAM 保留 + 2 个 USB， +剩 26 个，减去 23 根信号 ⇒ 只剩 **IO47 / IO48 两个备用脚**。一个不多。 + +## 契约里少写了一根：`HUB_RST` + +契约 §1.2 明写 `HUB_RST` 由 **A3 的 ESP32** 发出去 A4，但任务书列 GPIO 时漏了它。 +本页按契约办：`HUB_RST = IO8`（模组脚 12），不是 strapping 脚。 +硬约束 §3.1 的"不驱动 = 不复位"由 A4 侧 10k 上拉到 `+3V3_HUB` 保证，本页只出一个端口。 + +## 外部上拉 vs ESP32 内部上拉（PRSNT1#~5#） + +`PRSNT#` 完全可以用 ESP32 的内部上拉（~45kΩ）省掉 5 颗电阻。**本项目仍然用外部 10k**： + +1. ESP32 复位期间（EN 拉低到固件跑起来之间）内部上拉是关的，PRSNT# 会浮着 —— + 而这几根线跨了金手指、外面挂着五片可插拔的刀片，浮空输入在这种长走线上会乱跳。 +2. 45kΩ 对一条穿过金手指、带插拔弹跳的线来说太软；10k 的噪声容限和 + `INT#` / `INA_ALERT` 那两条开漏线一致，调试时可以用同一套判据。 +3. 以后若要把 PRSNT# 改成开漏 wire-OR 或接到别的芯片上，外部上拉不用改板。 + +同理 `INT#`（五槽 wire-OR，契约 §1.2 钉死上拉在本页）和 `INA_ALERT`（A1 的 U13 开漏） +也各一颗 10k。刀片上 B2-CTRL 已有本槽 I²C 分支的 4.7k，**底板只管主干这一对**（R602/R603）。 + +## 踩过 / 绕开的坑 + +- **TCA9548A 的 `SDn` 脚号在 `SCn` 前面**（4=SD0 5=SC0 6=SD1 7=SC1 …）。按 SCL/SDA 的 + 书写习惯接过去就是整排反的，而且几何验证一路 PASS。本页 `U35_CH` 把 (SDn, SCn) 脚号 + 写成显式二元组，不靠顺序推。 +- **端口标签往锚点某一侧伸出去约 40+6.7×字符数**（skill §7 第 8 条 / §8b）。本页三处 + 险些相撞：上拉组标签右边界 245 vs U35 的 `MUX_RST#` 标签左边界 256（留 11）； + U35 右侧标签右边界 612 vs DAC 块左边界 613（留 1，就是靠 dx=+580/+50 顶出来的）； + ESP32 第二列标签右边界 590 vs 同上。改任何一个 x 都要重算这三处 —— `label_clash()` + 会兜住同一 y 上的相叠，跨块的间距靠 `build()` 里那条 `bx[0] >= 613` 断言。 +- **`dir` 决定标签朝哪边**（skill §8b）：`IN` 的标签在引脚**左**侧，`BI`/`OUT` 在右侧。 + 所以本页用 `port_rot(dir, side)`，`side` 说的是"标签往哪边伸"，rot 由 dir 反推。 + 一律写 rot=0 会让所有 IN 口的标签整排倒过去压到 U20 身上。 +- **TXD0 / RXD0 两根从 U20 左侧并排引出的线怎么不打架**：判据是"**里侧那根拐得更低**"。 + TXD0（脚 37，y=585）走里侧竖线 x=185 且拐在 y=410，RXD0（脚 36，y=595）走外侧 + x=175 拐在 y=430。反过来排就会在 (185,585) 出一个交叉点 —— 第一版就是这么写的， + `crossings()` 当场报出来了。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, _on, call, pins_of, PARTS # noqa: E402 + +PAGE, NAME = '38327f806bc13133', 'A3-CTRL' +R2_PROJECT = '05a65c22f14846b8b95360ef8d3c1e2e' + +SRC_DAC = os.path.join(HERE, '_p3b_live2.json') # R1 P3B-EXPAND +KEEP_U6 = set(['U6', 'C607', 'C608', 'C609', 'R614', 'R615']) +KEEP_U7 = set(['U7', 'C610', 'C611', 'C612', 'R616', 'R617']) +OFF_U6 = (580, -20) +OFF_U7 = (50, 250) +# R1 上这两颗 DAC 都有空着的通道：U6 只用 3 路（VDAC1/2/4，通道 3 空）， +# U7 只用 2 路（VDAC3/5，通道 2/3 空）。源页上这些 OUTx/FBx 本来就没接线。 +# ⚠ datasheet 要求"FBx 接回 OUTx"只对**启用的**通道成立；空通道上电默认关闭、 +# 输出高阻，R1 就是这么留的，本页照搬不动。写成显式表，免得被当成漏连。 +DAC_NC = {'U6': ['1', '2'], 'U7': ['1', '2', '3', '4']} # FB3/OUT3 (+U7 的 OUT2/FB2) + +# ── 器件键（`.claude/eda-parts.json`）─────────────────────────────────── +K_ESP = 'C9900163599' # ESP32-S3-WROOM-1 +K_MUX = 'C130026' # TCA9548APWR +K_HDR = 'C50951' # 2.54mm 1*5P 直排针 +K_10K = 'C25744' # 0402 10kΩ (0402WGF1002TCE) +K_4K7 = 'C25900' # 0402 4.7kΩ (0402WGF4701TCE = 470×10^1) +K_100N = 'C1525' # 0402 100nF +K_22U = 'C12891' # 1206 22µF（引脚 ±15，不是 ±20） + +U20X, U20Y = 250, 600 # ESP32 中心 +U35X, U35Y = 450, 280 # TCA9548A 中心 +J33X, J33Y = 430, 455 # 应急 UART 排针中心（挪到 U20 与 U35 之间那条空带） +COL1, COL2 = 340, 470 # ESP32 信号端口的两列锚点 x + +# ── U20 引脚相对坐标（实测自 `_p3_live.json`，rot 0）──────────────────── +U20_REL = { + '1': (45, -160), '2': (-45, 15), '3': (-45, 5), '4': (45, 160), + '5': (45, 150), '6': (45, 140), '7': (45, 130), '8': (45, 50), + '9': (45, 40), '10': (45, 30), '11': (45, 20), '12': (45, 120), + '13': (45, 10), '14': (45, 0), '15': (45, 170), '16': (45, -110), + '17': (45, 110), '18': (45, 100), '19': (45, 90), '20': (45, 80), + '21': (45, 70), '22': (45, 60), '23': (45, -10), '24': (45, -120), + '25': (45, -130), '26': (45, -100), '27': (45, 200), '28': (45, -20), + '29': (45, -30), '30': (45, -40), '31': (45, -50), '32': (45, -60), + '33': (45, -70), '34': (45, -80), '35': (45, -90), '36': (-45, -5), + '37': (-45, -15), '38': (45, 180), '39': (45, 190), '40': (45, -170), + '41': (45, -200), +} +# 模组脚号 -> IOxx（与 `_esp32_pinmap.json:pin2io` 一致，缺的几条是本页按符号脚名补的） +PIN2IO = { + '4': 'IO4', '5': 'IO5', '6': 'IO6', '7': 'IO7', '8': 'IO15', '9': 'IO16', + '10': 'IO17', '11': 'IO18', '12': 'IO8', '13': 'IO19', '14': 'IO20', + '15': 'IO3', '16': 'IO46', '17': 'IO9', '18': 'IO10', '19': 'IO11', + '20': 'IO12', '21': 'IO13', '22': 'IO14', '23': 'IO21', '24': 'IO47', + '25': 'IO48', '26': 'IO45', '27': 'IO0', '28': 'IO35', '29': 'IO36', + '30': 'IO37', '31': 'IO38', '32': 'IO39', '33': 'IO40', '34': 'IO41', + '35': 'IO42', '36': 'IO44', '37': 'IO43', '38': 'IO2', '39': 'IO1', +} +ADC1 = set('IO%d' % i for i in range(1, 11)) + +# ── ⭐ R2 底板 GPIO 分配表 ────────────────────────────────────────────── +# (模组脚号, 网络名, dir, 端口列, 理由) +# dir 是**本页这一侧**的方向：ESP32 输出 = OUT，ESP32 采样 = IN，双向 = BI。 +PINMAP = [ + ('27', 'IO0', 'BI', COL1, u'strapping/下载；接 J33 第 5 脚，悬空=正常启动'), + ('39', 'NTC1', 'IN', COL2, u'IO1 = ADC1_CH0 —— 必须 ADC1，ADC2 与 WiFi 冲突'), + ('38', 'NTC2', 'IN', COL1, u'IO2 = ADC1_CH1 —— 同上'), + ('4', 'FAN_TACH_OUT', 'IN', COL2, u'IO4 测速脉冲输入，任意 GPIO'), + ('5', 'FAN_TACH_IN', 'IN', COL1, u'IO5 测速脉冲输入，任意 GPIO'), + ('6', 'FAN_PWM', 'OUT', COL2, u'IO6 LEDC PWM，任意 GPIO'), + ('7', 'FAN_EN', 'OUT', COL1, u'IO7 复位高阻=关电，由 A6 的 100k 下拉保证'), + ('12', 'HUB_RST', 'OUT', COL2, u'IO8 非 strapping；不复位由 A4 的 10k 上拉保证'), + ('17', 'EFUSE_EN5', 'OUT', COL1, u'IO9 直驱刀片 eFuse EN'), + ('18', 'EFUSE_EN4', 'OUT', COL2, u'IO10 直驱刀片 eFuse EN'), + ('19', 'EFUSE_EN3', 'OUT', COL1, u'IO11 直驱刀片 eFuse EN'), + ('20', 'EFUSE_EN2', 'OUT', COL2, u'IO12 直驱刀片 eFuse EN'), + ('21', 'EFUSE_EN1', 'OUT', COL1, u'IO13 直驱刀片 eFuse EN'), + ('22', 'PRSNT5#', 'IN', COL2, u'IO14 在位检测，本页外部 10k 上拉'), + ('8', 'PRSNT4#', 'IN', COL1, u'IO15 在位检测，本页外部 10k 上拉'), + ('9', 'PRSNT3#', 'IN', COL2, u'IO16 在位检测，本页外部 10k 上拉'), + ('10', 'PRSNT2#', 'IN', COL1, u'IO17 在位检测，本页外部 10k 上拉'), + ('11', 'PRSNT1#', 'IN', COL2, u'IO18 在位检测，本页外部 10k 上拉'), + ('13', 'USB6_DM', 'BI', COL1, u'IO19 ⚠ 原生 USB PHY 硬连线 D−，不可改'), + ('14', 'USB6_DP', 'BI', COL2, u'IO20 ⚠ 原生 USB PHY 硬连线 D+，不可改'), + ('23', 'UP_VBUS_DET', 'IN', COL1, u'IO21 电脑在不在，A4 分压后送来'), + ('31', 'INA_ALERT', 'IN', COL2, u'IO38 A1 的 U13 开漏，本页 10k 上拉'), + ('32', 'INT#', 'IN', COL1, u'IO39 五槽 wire-OR 开漏，本页唯一一颗 10k 上拉'), + ('33', 'MUX_RST#', 'BI', COL2, u'IO40 U35 复位；本页 10k 上拉 ⇒ 高阻=不复位'), + ('34', 'SDA', 'BI', COL1, u'IO41 I²C 主干（不经 mux）'), + ('35', 'SCL', 'BI', COL2, u'IO42 I²C 主干（不经 mux）'), +] +# 有意不接（进 NC 表，不算悬空） +U20_NC = ['15', '16', '24', '25', '26', '28', '29', '30'] +U20_NC_WHY = { + '15': u'IO3 strapping(JTAG_SEL)', '16': u'IO46 strapping + input-only', + '24': u'IO47 备用', '25': u'IO48 备用', '26': u'IO45 strapping(VDD_SPI)', + '28': u'IO35 留给 R8 版八线 PSRAM', '29': u'IO36 同上', '30': u'IO37 同上', +} + +# ── TCA9548A 引脚相对坐标（契约 §4，实测）。⚠ SDn 脚号在 SCn 前面 ─────── +U35_REL = { + '1': (-50, 55), '2': (-50, 45), '3': (-50, 35), '4': (-50, 25), + '5': (-50, 15), '6': (-50, 5), '7': (-50, -5), '8': (-50, -15), + '9': (-50, -25), '10': (-50, -35), '11': (-50, -45), '12': (-50, -55), + '13': (50, -55), '14': (50, -45), '15': (50, -35), '16': (50, -25), + '17': (50, -15), '18': (50, -5), '19': (50, 5), '20': (50, 15), + '21': (50, 25), '22': (50, 35), '23': (50, 45), '24': (50, 55), +} +# (SDn 脚号, SCn 脚号, 槽号)。通道 0~3 在左列，通道 4 在右列（脚 13=SD4 / 14=SC4） +U35_CH_L = [('4', '5', 1), ('6', '7', 2), ('8', '9', 3), ('10', '11', 4)] +U35_NC = ['15', '16', '17', '18', '19', '20'] # 通道 5~7 悬空 + +# ── 上拉电阻组（左下）：(y, 位号, 器件键, 网名, dir, 说明) ─────────────── +BANK_X_BUS, BANK_X_R, BANK_X_PT = 45, 85, 145 +# ⚠ 行距 30 而不是 20：0402 的**位号 + 值是两行文字，画在符号右侧**，占竖直方向 +# 约 20 个单位。20 行距时上下两颗的文字会贴在一起（几何验证抓不到，只有渲染出来才看得见）。 +BANK_PITCH, BANK_TOP = 30, 380 +BANK = [ + ('R602', K_4K7, 'SDA', 'BI', u'I²C 主干上拉 4.7k'), + ('R603', K_4K7, 'SCL', 'BI', u'I²C 主干上拉 4.7k'), + ('R604', K_10K, 'INT#', 'IN', u'五槽 wire-OR 的唯一一颗上拉'), + ('R605', K_10K, 'INA_ALERT', 'IN', u'A1 的 U13 开漏'), + ('R606', K_10K, 'PRSNT1#', 'IN', u'刀片在位时把它拉到地'), + ('R607', K_10K, 'PRSNT2#', 'IN', u'刀片在位时把它拉到地'), + ('R608', K_10K, 'PRSNT3#', 'IN', u'刀片在位时把它拉到地'), + ('R609', K_10K, 'PRSNT4#', 'IN', u'刀片在位时把它拉到地'), + ('R610', K_10K, 'PRSNT5#', 'IN', u'刀片在位时把它拉到地'), + ('R611', K_10K, 'MUX_RST#', 'BI', u'高阻 = 不复位'), +] +BANK_Y = dict((b[0], BANK_TOP - BANK_PITCH * i) for i, b in enumerate(BANK)) + +# ── J33 应急 UART：脚号 -> 网名（脚 1 是 GND，直接挂地旗）─────────────── +J33_MAP = [('2', 'TXD0'), ('3', 'RXD0'), ('4', 'EN'), ('5', 'IO0')] +J33_REL = {'1': (-20, 20), '2': (-20, 10), '3': (-20, 0), + '4': (-20, -10), '5': (-20, -20)} + +TEXTS = [ + (620, 805, u'【A3-CTRL】ESP32-S3 主控 + TCA9548A I²C 多路 + DAC63204 ×2 + 应急 UART', 12), + (620, 782, u'【E/F】DAC63204 ×2（U6=0x4A / A0→SDA，U7=0x4B / A0→SCL），挂 I²C 主干、不经 mux。', 10), + (620, 766, u'三处 datasheet 强制要求（图上看不出来、接错也不报错）：FBx 必须接回 OUTx；', 10), + (620, 750, u'CAP 接 2.2µF 到 AGND；VREF 空置时 100nF 到地 + 10k 上拉 VDD。', 10), + (620, 734, u'内部基准 1.212V ×2 ⇒ 满量程 2.424V（不是 2.5V）。U6 出 VDAC1/2/4，U7 出 VDAC3/5。', 10), + (620, 718, u'⚠ U23 PCA9555 留在刀片上（B2-CTRL），本页一件不搬。', 10), + # ⚠ 2026-09-08 主代理改：第一行原来在 y=96，**压住 R611(85,110) 的「10kΩ」值标签** + # （值画在电阻符号下方，占到 y≈90）。`text_clash` 只查文字 vs 导线/引脚、 + # `label_clash` 只查端口标签 vs 旗，两者都够不着「文字 vs 元件的位号/值」这一类。 + # 把六个区（A ESP32 / B 上拉组 / C J33 / D U35 / E·F 两颗 DAC）和标题栏 + # （x>455 且 y<192）当障碍全页扫过：本页能放下这一块的只有左下角 y 10~80 那条, + # ⇒ 五行压进 74/58/42/26/10，字号 10→9（字号 10 的五行放不进 70 的高度）。 + (90, 74, u'【B】上拉组：SDA/SCL 主干 4.7k（分支的那对在刀片 B2-CTRL），', 9), + (90, 58, u'INT# 是五槽 wire-OR 唯一的一颗 10k，INA_ALERT 对 A1 的 U13 开漏。', 9), + (90, 42, u'PRSNT1#~5# 用外部 10k 而非 ESP32 内部上拉：复位期间内部上拉是关的，', 9), + (90, 26, u'跨金手指的长线浮空会乱跳，45k 对插拔弹跳也太软。', 9), + (90, 10, u'【C】J33 = D13 的保命口：控制台挂在 Hub 后面，Hub 一复位就自断后路。', 9), +] + + +# ══════════════════════════════════════════════════════════════════════ +# 从 R1 页面整块搬运（照抄 a2_aux.py 的 load()，本页不需要改名表） +# ══════════════════════════════════════════════════════════════════════ +def load(path, keep, off, src_nc=None): + u"""读回一页，按 keep 过滤，整块平移。返回 (导线[(a,b,net)], 旗, 端口, place, expect)。 + + ⚠ 过滤的判据是「导线组里的引脚属于谁」，不是坐标框 —— 坐标框会把别人的线一起切走。 + `src_nc = {位号: [脚号...]}` 是**源页上本来就没接**的脚（R1 两颗 DAC 都有空着的通道）， + 不列进来就会被当成"源页悬空引脚"而终止。 + """ + src_nc = src_nc or {} + src = json.load(io.open(path, encoding='utf-8')) + dx, dy = off + pts = src['wires'] + segs = [((int(round(pts[i][0])) + dx, int(round(pts[i][1])) + dy), + (int(round(pts[i + 1][0])) + dx, int(round(pts[i + 1][1])) + dy)) + for i in range(0, len(pts), 2)] + for a, b in segs: + assert a != b, u'%s 有零长度导线 %s（skill §8a）' % (path, (a,)) + assert (a[0] == b[0]) != (a[1] == b[1]), u'%s 有斜线 %s-%s' % (path, a, b) + + n = len(segs) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2 = segs[i] + b1, b2 = segs[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + + gname, gowner, gpins = defaultdict(set), defaultdict(set), defaultdict(set) + for lst in (src['flags'], src['ports']): + for f in lst: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'%s 的旗/端口 %s 不在任何导线上' % (path, f[1]) + gname[find(hit[0])].add(f[1]) + for p in src['parts']: + for q in p[9]: + if str(q[0]) in src_nc.get(p[0], []): + continue + xy = (int(round(q[2])) + dx, int(round(q[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'%s 源页悬空引脚 %s.%s' % (path, p[0], q[0]) + gowner[find(hit[0])].add(p[0]) + gpins[find(hit[0])].add('%s.%s' % (p[0], q[0])) + + keepgrp = {} + for r_, owners in gowner.items(): + inside, outside = owners & keep, owners - keep + assert not (inside and outside), \ + u'%s 的导线组同时挂着 %s 和 %s，切不开' % (path, sorted(inside), sorted(outside)) + keepgrp[r_] = bool(inside) + + W, F, PT = [], [], [] + for r_, ok in keepgrp.items(): + if not ok: + continue + names = gname.get(r_, set()) + assert len(names) <= 1, u'组 %s 名字不唯一：%s' % (sorted(gpins[r_])[:3], sorted(names)) + # 无名的短节点沿用 R1 的自动命名，`#` 开头的名字只给本地自检用，不下发。 + net = sorted(names)[0] if names else '#' + '+'.join(sorted(gpins[r_])[:2]) + for i in range(n): + if find(i) == r_: + W.append((segs[i][0], segs[i][1], net)) + + def kept_at(xy): + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + return keepgrp[find(hit[0])] if hit else False + + for f in src['flags']: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + if kept_at(xy): + F.append([f[0].split('-')[0], f[1], xy[0], xy[1], f[4]]) + for p in src['ports']: + xy = (int(round(p[2])) + dx, int(round(p[3])) + dy) + if kept_at(xy): + PT.append([p[0].replace('Netport-', ''), p[1], xy[0], xy[1], p[4]]) + + byname = {} + for k, v in PARTS.items(): + byname.setdefault(v['name'], k) + place, exp = [], {} + for p in src['parts']: + d, nm = p[0], p[1] + if d not in keep: + continue + base = nm.split('_C')[0] if '_C' in nm else nm + k = byname.get(nm) or byname.get(base) + assert k, u'eda-parts.json 里找不到器件 %r（%s）' % (nm, d) + assert not p[6], u'%s 是镜像件，Sheet.place 处理不了' % d + place.append([d, k, int(round(p[3])) + dx, int(round(p[4])) + dy, p[5]]) + exp[d] = dict((str(q[0]), (int(round(q[2])) + dx, int(round(q[3])) + dy)) + for q in p[9]) + return W, F, PT, place, exp + + +# ══════════════════════════════════════════════════════════════════════ +# 本页手画的部分 +# ══════════════════════════════════════════════════════════════════════ +def rel(cx, cy, table): + return dict((k, (cx + dx, cy + dy)) for k, (dx, dy) in table.items()) + + +def hz(cx, cy, half=20): + u"""横放两脚件的期望（非极性件只比坐标集合，翻转只换脚号，无害）。""" + return {'?': set([(cx - half, cy), (cx + half, cy)])} + + +def vt(cx, cy, half=20): + u"""竖放两脚件的期望。""" + return {'?': set([(cx, cy - half), (cx, cy + half)])} + + +def port_rot(d, side): + u"""side='R' 标签往右伸、'L' 往左伸。skill §8b：IN 的方向和 BI/OUT 相反。""" + if side == 'R': + return 180 if d == 'IN' else 0 + return 0 if d == 'IN' else 180 + + +def build_local(s): + u"""A/B/C/D 四区（ESP32、上拉组、J33、TCA9548A）。返回 (place, expect)。""" + place, exp = [], {} + U = rel(U20X, U20Y, U20_REL) # U20 绝对引脚坐标 + M = rel(U35X, U35Y, U35_REL) # U35 绝对引脚坐标 + + # ── A 区：ESP32 ──────────────────────────────────────────────────── + place.append(['U20', K_ESP, U20X, U20Y, 0]) + exp['U20'] = dict(U) + + # 3V3 干线 x=160（U20 脚2 -> 上到旗），C601/C602 去耦挂在上面 + place.append(['C601', K_22U, 100, 760, 0]) # 1206，引脚 ±15（skill §8d 实测） + place.append(['C602', K_100N, 100, 710, 0]) # 0402，引脚 ±20 + exp['C601'] = hz(100, 760, 15) + exp['C602'] = hz(100, 710, 20) + s.w('+3V3', (160, 615), (160, 790)) + s.pwr('+3V3', 160, 790, 0) # 符号在上、引脚在下，导线从下方 ✓ + s.w('+3V3', (115, 760), (160, 760)) + s.w('+3V3', (120, 710), (160, 710)) + s.w('+3V3', (160, 615), (205, 615)) # -> U20 脚2 (3V3) + + # EN 上电复位：R601 10k 上拉 + C603 100nF 到地 + place.append(['R601', K_10K, 130, 660, 270]) # rot270 -> 引脚 (x, y±20) + # ⚠ C603 摆在 x=100 而不是和 R601 同一条 x=130：0402 的**型号文字画在符号右侧** + # （skill §8b-3），x=130 时它横着占到 x≈200，正好压在 RXD0 那根竖线（x=175）上。 + place.append(['C603', K_100N, 100, 480, 270]) + exp['R601'] = vt(130, 660) + exp['C603'] = vt(100, 480) + s.w('+3V3', (130, 680), (160, 680)) # R601 上脚 -> 3V3 干线（T） + s.w('EN', (130, 500), (130, 640)) # R601 下脚往下的 EN 竖线 + s.w('EN', (100, 500), (130, 500)) # -> C603 上脚 + s.w('EN', (130, 605), (205, 605)) # T 到 U20 脚3 (EN) + s.w('EN', (90, 520), (130, 520)) # T 出一小段给端口（避开 GND 干线） + s.port('BI', 'EN', 90, 520, port_rot('BI', 'L')) + + # 地：C601/C602 走 x=60 干线；C603 单独一条，让开 EN 端口的标签 + s.w('GND', (60, 690), (60, 760)) + s.w('GND', (60, 760), (85, 760)) + s.w('GND', (60, 710), (80, 710)) + s.gnd(60, 690, 0) # 符号在下、引脚在上，导线从上方 ✓ + s.w('GND', (60, 460), (100, 460)) + s.w('GND', (60, 440), (60, 460)) + s.gnd(60, 440, 0) + + # TXD0 / RXD0：外圈先拐的嵌套走法，避免两条互相交叉（见文档串） + # 判据：**里侧那根（x 大的）必须拐得更低**，它的横段才不会切到外侧那根的竖段。 + # 反过来排（TXD0 走 x=175 在 y=430 拐）会在 (185,585) 造出一个交叉点。 + s.w('TXD0', (185, 585), (205, 585)) # 脚 37，里侧竖线 x=185，拐在 y=410 + s.w('TXD0', (185, 410), (185, 585)) + s.w('TXD0', (160, 410), (185, 410)) + s.port('BI', 'TXD0', 160, 410, port_rot('BI', 'L')) + s.w('RXD0', (175, 595), (205, 595)) # 脚 36，外侧竖线 x=175，拐在 y=430 + s.w('RXD0', (175, 430), (175, 595)) + s.w('RXD0', (160, 430), (175, 430)) + s.port('BI', 'RXD0', 160, 430, port_rot('BI', 'L')) + + # U20 的地（脚 1 / 40 + EPAD 41） + for pin in ('1', '40', '41'): + s.w('GND', U[pin], (320, U[pin][1])) + s.w('GND', (320, 400), (320, 440)) + s.w('GND', (320, 370), (320, 400)) + s.gnd(320, 370, 0) + + # 26 根信号引出线 + 端口 + for pin, net, d, col, _why in PINMAP: + y = U[pin][1] + s.w(net, (295, y), (col, y)) + s.port(d, net, col, y, port_rot(d, 'R')) + + # ── B 区：上拉电阻组 ─────────────────────────────────────────────── + bot = BANK_Y[BANK[-1][0]] - 5 + s.w('+3V3', (BANK_X_BUS, bot), (BANK_X_BUS, BANK_TOP)) + s.pwr('+3V3', BANK_X_BUS, bot, 180) # 符号在下、引脚在上，导线从上方 ✓ + for ref, key, net, d, _why in BANK: + y = BANK_Y[ref] + place.append([ref, key, BANK_X_R, y, 0]) + exp[ref] = hz(BANK_X_R, y, 20) + s.w('+3V3', (BANK_X_BUS, y), (BANK_X_R - 20, y)) + s.w(net, (BANK_X_R + 20, y), (BANK_X_PT, y)) + s.port(d, net, BANK_X_PT, y, port_rot(d, 'R')) + + # ── C 区：J33 应急 UART ──────────────────────────────────────────── + place.append(['J33', K_HDR, J33X, J33Y, 0]) + J = rel(J33X, J33Y, J33_REL) + exp['J33'] = dict(J) + # 脚1 的地往左走到 x=115 再下去 —— 往右走会贴着连接器符号的上沿画过去， + # 往下走会撞上第 5 脚那一排端口标签（x73..140）。 + # 脚1 的地从**第 2~5 脚那排引出线的上方**往左走再下去 —— 从下面走会切到那四根线。 + s.w('GND', J['1'], (340, J['1'][1])) + # 地旗的引脚落在 y=415 而不是 440：地符号往下伸约 20，440 时它会压住 + # 第 5 脚（IO0）那个端口的标签（x310..370 @ y435）。 + s.w('GND', (340, 415), (340, J['1'][1])) + s.gnd(340, 415, 0) # 符号在下、引脚在上，导线从上方 ✓ + for pin, net in J33_MAP: + s.w(net, (370, J[pin][1]), J[pin]) + s.port('BI', net, 370, J[pin][1], port_rot('BI', 'L')) + + # ── D 区：TCA9548A ───────────────────────────────────────────────── + place.append(['U35', K_MUX, U35X, U35Y, 0]) + exp['U35'] = dict(M) + # 通道 0~3 -> SDA1/SCL1 ~ SDA4/SCL4（左列） + for sd, sc, ch in U35_CH_L: + for pin, net in ((sd, 'SDA%d' % ch), (sc, 'SCL%d' % ch)): + s.w(net, (350, M[pin][1]), M[pin]) + s.port('BI', net, 350, M[pin][1], port_rot('BI', 'L')) + # 通道 4 -> SDA5/SCL5（右列：脚 13 = SD4、脚 14 = SC4） + for pin, net in (('13', 'SDA5'), ('14', 'SCL5')): + s.w(net, M[pin], (545, M[pin][1])) + s.port('BI', net, 545, M[pin][1], port_rot('BI', 'R')) + # RESET# -> MUX_RST#（10k 上拉在 B 区） + s.w('MUX_RST#', (350, M['3'][1]), M['3']) + s.port('BI', 'MUX_RST#', 350, M['3'][1], port_rot('BI', 'L')) + # A0 / A1 / A2 全接地 -> 地址 0x70 + s.w('GND', (370, M['1'][1]), M['1']) + s.w('GND', (370, M['2'][1]), M['2']) + s.w('GND', (370, 325), (370, 355)) + s.gnd(370, 355, 180) # 符号在上、引脚在下，导线从下方 ✓ + s.w('GND', M['21'], (585, M['21'][1])) # A2 从右侧绕出去，避开 SDA5/SCL5 + s.w('GND', (585, 270), (585, 305)) + s.gnd(585, 270, 0) + # GND 脚 + s.w('GND', (370, M['12'][1]), M['12']) + s.w('GND', (370, 205), (370, 225)) + s.gnd(370, 205, 0) + # 上游 I²C 主干 + for pin, net in (('22', 'SCL'), ('23', 'SDA')): + s.w(net, M[pin], (545, M[pin][1])) + s.port('BI', net, 545, M[pin][1], port_rot('BI', 'R')) + # VCC + 去耦 C604 + place.append(['C604', K_100N, 570, 385, 0]) + exp['C604'] = hz(570, 385, 20) + s.w('+3V3', M['24'], (530, M['24'][1])) + s.w('+3V3', (530, 335), (530, 405)) + s.w('+3V3', (530, 385), (550, 385)) + s.pwr('+3V3', 530, 405, 0) + s.w('GND', (590, 385), (590, 415)) + s.gnd(590, 415, 180) + return place, exp + + +# ══════════════════════════════════════════════════════════════════════ +# 排版自检（照抄 a1_input.py / a2_aux.py，加了一条端口标签相叠） +# ══════════════════════════════════════════════════════════════════════ +def text_clash(s, exp): + errs, boxes, pts = [], [], [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + w = size * (cjk + 0.5 * (len(txt) - cjk)) + boxes.append((x, y - size * 0.8, x + w, y + size * 0.8, txt)) + for d, ps in exp.items(): + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + for x0, y0, x1, y1, txt in boxes: + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:26])) + for a, b, net in s.W: + if a[1] == b[1]: + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (net, a[1], txt[:26])) + else: + if x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (net, a[0], txt[:26])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +def label_clash(s): + u"""**不同列**的端口标签横向对撞。skill §8b：符号+标签往某一侧伸 40+6.7×字符。 + + `flag_clash` 只看锚点距离（横向 <20），够不着这一类 —— P3B 上就出过 + 「左边器件的 rot=0 标签和右边器件的 rot=180 标签在中间撞上」，两列看着离得很远。 + ⚠ **同一列**（锚点 x 相同）按 10 的间距排下来是正常的（skill §8b-2， + R1 的 P3 一列排了 21 个），所以这里只比不同 x 的。 + """ + errs, boxes = [], [] + for d, net, x, y, rot in s.PT: + w = 40 + 6.7 * len(net) + left = (rot == 0) if d == 'IN' else (rot == 180) + lo, hi = (x - w, x) if left else (x, x + w) + boxes.append((lo, hi, y - 8, y + 8, net, x, True)) + # 旗的符号：横向约 ±10，纵向从引脚往符号那一侧伸约 20（Ground rot0 / Power rot180 + # 是往下，另两种往上）。**端口标签压住地旗**在本页真的发生过一次（J33 的 IO0）。 + for kind, net, x, y, rot in s.F: + down = (kind == 'Ground') == (rot == 0) + boxes.append((x - 10, x + 10, y - 20 if down else y, y if down else y + 20, + net, None, False)) + for i in range(len(boxes)): + for j in range(i + 1, len(boxes)): + a, b = boxes[i], boxes[j] + if a[6] and b[6] and a[5] == b[5]: # 同一列的端口，10 间距是正常的 + continue + if a[0] < b[1] and b[0] < a[1] and a[2] < b[3] and b[2] < a[3]: + errs.append(u'符号/标签相叠: %s 与 %s（x %.0f..%.0f × %.0f..%.0f）' + % (a[4], b[4], max(a[0], b[0]), min(a[1], b[1]), + max(a[2], b[2]), min(a[3], b[3]))) + return sorted(set(errs)) + + +def bbox(W, F, PT, exp): + xs, ys = [], [] + for a, b, _ in W: + xs += [a[0], b[0]] + ys += [a[1], b[1]] + for it in F + PT: + xs.append(it[2]) + ys.append(it[3]) + for ps in exp.values(): + for xy in ps.values(): + xs.append(xy[0]) + ys.append(xy[1]) + return min(xs), max(xs), min(ys), max(ys) + + +def assert_no_overlap(n1, b1, n2, b2, gap=30): + ax0, ax1, ay0, ay1 = b1 + bx0, bx1, by0, by1 = b2 + sep_x = ax1 + gap <= bx0 or bx1 + gap <= ax0 + sep_y = ay1 + gap <= by0 or by1 + gap <= ay0 + assert sep_x or sep_y, u'%s 与 %s 重叠：x%d..%d y%d..%d vs x%d..%d y%d..%d' % ( + n1, n2, ax0, ax1, ay0, ay1, bx0, bx1, by0, by1) + + +def build(): + s = Sheet(PAGE, NAME) + place, exp = build_local(s) + + a = load(SRC_DAC, KEEP_U6, OFF_U6, DAC_NC) + b = load(SRC_DAC, KEEP_U7, OFF_U7, DAC_NC) + assert_no_overlap(u'U6 块', bbox(*a[:3], exp=a[4]), u'U7 块', bbox(*b[:3], exp=b[4])) + for tag, blk in ((u'U6 块', a), (u'U7 块', b)): + bx = bbox(*blk[:3], exp=blk[4]) + assert bx[0] >= 613, u'%s 左边界 %d 顶到 ESP32/U35 的端口标签' % (tag, bx[0]) + assert bx[3] <= 700, u'%s 上边界 %d 顶到说明文字' % (tag, bx[3]) + for it in blk[1] + blk[2]: # 旗/端口不许掉进标题栏 + assert not (it[2] > 455 and it[3] < 192), \ + u'%s 的 %s @(%d,%d) 掉进标题栏' % (tag, it[1], it[2], it[3]) + # 端口标签算进来的真实左右边界（skill §7 第 8 条：符号+标签约 40+6.7×字符） + for d, net, x, _y, rot in blk[2]: + w = 40 + 6.7 * len(net) + left = (rot == 0) if d == 'IN' else (rot == 180) + lo, hi = (x - w, x) if left else (x, x + w) + assert lo >= 600, u'%s 的 %s 标签左边界 %.0f 顶到左边的块' % (tag, net, lo) + assert hi <= 1145, u'%s 的 %s 标签右边界 %.0f 出框' % (tag, net, hi) + + for W, F, PT, pl, ex in (a, b): + s.W += list(W) + s.F += F + s.PT += PT + dup = set(ex) & set(exp) + assert not dup, u'位号撞车：%s' % sorted(dup) + place += pl + exp.update(ex) + for t in TEXTS: + s.txt(t[0], t[1], t[2], t[3]) + return s, place, exp + + +# 靠同名旗/端口成网、导线上天然分块的网络（契约 §7 第 10 条） +ALLOW_SPLIT = set(['GND', '+3V3', 'SDA', 'SCL', 'EN', 'TXD0', 'RXD0', 'IO0', + 'MUX_RST#', 'INT#', 'INA_ALERT', + 'PRSNT1#', 'PRSNT2#', 'PRSNT3#', 'PRSNT4#', 'PRSNT5#']) + + +def check_pinmap(): + u"""GPIO 分配表本身的自检：不撞 NC、不重号、NTC 在 ADC1、USB 是硬连线那两个。""" + used = [p for p, _n, _d, _c, _w in PINMAP] + assert len(set(used)) == len(used), u'PINMAP 有重复脚号' + assert not (set(used) & set(U20_NC)), u'PINMAP 用到了 NC 表里的脚' + # 电源 / 地 / EN / UART 这几个脚不走 PINMAP，单独列出来兜底 + HARD = set(['1', '2', '3', '36', '37', '40', '41']) # GND 3V3 EN RXD0 TXD0 GND EPAD + miss = set(U20_REL) - set(used) - set(U20_NC) - HARD + assert not miss, u'有脚既不在 PINMAP 也不在 NC 表里：%s' % sorted(miss) + by = dict((n, p) for p, n, _d, _c, _w in PINMAP) + for net in ('NTC1', 'NTC2'): + assert PIN2IO[by[net]] in ADC1, \ + u'%s 落在 %s，不是 ADC1（IO1~IO10）' % (net, PIN2IO[by[net]]) + assert PIN2IO[by['USB6_DM']] == 'IO19', u'USB6_DM 必须是 IO19（原生 USB D−）' + assert PIN2IO[by['USB6_DP']] == 'IO20', u'USB6_DP 必须是 IO20（原生 USB D+）' + # 契约 §1.4：R1 有、R2 没有的网络，写了就是错 + dead = set(['BUCK_PG', 'IOEXP_INT#', 'USB_DP', 'USB_DM']) + for _p, n, _d, _c, _w in PINMAP: + assert n not in dead and not n.startswith('KEY_') and not n.startswith('VBUS_EN'), \ + u'%s 是契约 §1.4 明确不存在的网络' % n + + +def dump_pinmap(): + u"""把本页的分配写回 `.claude/_esp32_pinmap.json` 的 "r2_base" 键（不动 new/old/pin2io）。""" + path = os.path.join(os.path.dirname(HERE), '_esp32_pinmap.json') + d = json.load(io.open(path, encoding='utf-8')) + d['r2_base'] = dict((net, int(pin)) for pin, net, _d, _c, _w in PINMAP) + d['r2_base_nc'] = dict((p, U20_NC_WHY[p]) for p in U20_NC) + with io.open(path, 'w', encoding='utf-8') as f: + f.write(json.dumps(d, ensure_ascii=False, indent=1, sort_keys=True)) + print(u'已更新 %s 的 r2_base（%d 根）' % (os.path.basename(path), len(PINMAP))) + + +def main(): + push = '--push' in sys.argv + check_pinmap() + s, place, exp = build() + s.assert_grid() + nc = {'U20': U20_NC, 'U35': U35_NC} + nc.update(DAC_NC) + pins = pins_of(exp) # 把 {'?': {两个坐标}} 摊平成 {脚号: (x,y)} + errs = s.netcheck(pins, nc, ALLOW_SPLIT) + errs += text_clash(s, pins) + flag_clash(s) + label_clash(s) + print(u'ESP32：用掉 %d 脚，有意不接 %d 脚（其中 IO47/IO48 是仅剩的备用）' + % (len(PINMAP), len(U20_NC))) + s.report(len(place), errs) + dump_pinmap() + if not push: + return + call("await eda.dmt_Project.openProject('%s'); await new Promise(r=>setTimeout(r,2500)); return 1;" + % R2_PROJECT) + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a4-hub-nc.json b/.claude/r2/a4-hub-nc.json new file mode 100644 index 0000000..2b7fc60 --- /dev/null +++ b/.claude/r2/a4-hub-nc.json @@ -0,0 +1,38 @@ +{ + "U32": [ + "14", + "15", + "16", + "17", + "18", + "20", + "21", + "22", + "23", + "26", + "27", + "28", + "29", + "30", + "31", + "32", + "33", + "34", + "35", + "36", + "37", + "38", + "39", + "47", + "48", + "49", + "50", + "51", + "55", + "56" + ], + "J23": [ + "A8", + "B8" + ] +} \ No newline at end of file diff --git a/.claude/r2/a4_hub.py b/.claude/r2/a4_hub.py new file mode 100644 index 0000000..434947b --- /dev/null +++ b/.claude/r2/a4_hub.py @@ -0,0 +1,573 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A4-HUB** 页：USB2517I 七口 Hub + Hub 专用 3.3V LDO。 + + /c/Python314/python .claude/r2/a4_hub.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a4_hub.py --push # 清页 + 重画（幂等，只有主代理跑） + +M3 的第四页。**主体是 R1 载板 `C2-HUB` 整页原样搬过来**（`OFF = (0,0)`，块内坐标一个字 +不动，连 U32 / J23 / Y1 / 去耦阵列的绝对引脚坐标都照抄 `_c2hub_live.json`）， +在此之上做三处改动： + +| # | 改动 | 依据 | +|---|---|---| +| 1 | **新增 `U31` AMS1117-3.3 + `C752`/`C753`/`C737`** —— R1 里这颗不在 C2-HUB 页上 | 契约 §1.1 / §2 | +| 2 | **放出第 6 个下行口**：`USBDN6_DM/DP`(53/54) → `USB6_DM/DP` 双向端口去 A3 | 方案 §8.2（D13）| +| 3 | `HUB_RST` 的保命上拉保留并写进页面文字；`UP_VBUS_DET` 端口 `BI`→`OUT`、`HUB_RST` 的第二个端口 `BI`→`IN` | 契约 §3 第 1 条 / §1.2 | + +--- + +## ⭐ T6：`CFG_SEL[2:0]=110` 下七个下行口是不是默认全开？—— **是，全开** + +逐条对 `kicad/datasheets/ic/USB2517.pdf`（Microchip **DS00001598C**，USB2517/USB2517I， +59 页，sha256 记在同名 `.json` 里；和 `eda-parts.json` 指名要用的 SMSC 2517 Rev 2.8 +是同一份内容的 Microchip 重排版，**不是** USB251x**B** 的 00001692C）： + +| 手册位置 | 原文 | 结论 | +|---|---|---| +| **Table 5-2**（p.15~16）`CFG_SEL[2:0]=110` | 「Internal Default Configuration • Strap Options are Disabled」 | strap **一个都不采样**，`PRT_DIS_*` 失效 | +| **Table 7-1**（p.20）`0Ah PDS` Port Disable (Self) | 默认 **00h** | ⇒ 七个口**全部可用** | +| **Table 7-1**（p.20）`0Bh PDB` Port Disable (Bus) | 默认 **00h** | 同上（本板自供电，看 0Ah）| +| **7.2.1.11**（p.26）`PORT_DIS_SP` 位定义 | 「'0' = port is available, '1' = port is disabled」 | 00h = 一个都没禁 | +| **Table 7-1**（p.20）`09h NRD` Non-Removable | 默认 **00h** | 全部可移除；`NON_REM[1:0]` 是 strap，同样不采样 | +| **Table 7-1**（p.20）`06h CFG1` | 默认 **9Bh**，bit7 `SELF_BUS_PWR`=1 | 自供电（只有 `010` 那一档强制总线供电，`110` 不改）| + +⇒ **第 6 个口不需要改任何 strap，直接把 `USBDN6_DP/DM` 引出来接线即可**。 +方案 §8.2 表第 6 条写的「若需要禁用多余口，改的是 strap 而不是电路」在这里反过来了： +本来就全开，要做的是**连线**，不是改 strap。 + +⚠️ 沿用 R1 第三十三轮的定案（设计文档 §21.6b）：`CFG_SEL[2:0]=110`（strap 禁用） +取代旧的「`PRT_SWP1~5` 各 100k 下拉」，本页三个 CFG_SEL 脚照 R1 接： + + CFG_SEL2(13) —— Table 5-3 缓冲类型 `I`（纯输入）→ 直接接 +3V3_HUB，不加电阻 + CFG_SEL1(42) —— 复用 HS_IND 输出，必须经 R712 10k **上拉**（硬接会和输出打架） + CFG_SEL0(41) —— R711 10k 下拉 ⇒ 1/1/0 = 110 + +⚠️ **口 7 是全开且悬空的**（`USBDN7_DP/DM` 55/56 不接）。这是**故意**的，理由见 §21.6b： +strap 停采样以后原来那两颗 10k 上拉会把 D+ 分压到 `3.3×15/(10+15)=1.98V`， +正好压在全速「已插入」的 2.0V 判据上 → 反复枚举失败的幽灵口，比 `lsusb` 里多一个 +空口难看得多。悬空时被 Hub 内部 15k 下拉拉低 = 空闲，无害。R1 已把 `R714/R715` 删掉， +本页同样不装。 + +## 第 6 个口要不要串阻 / ESD？——**不要**，和 R1 的五个口一样直连 + +R1 的口 1~5（`_c2hub_live.json` 实测）是 `U32` 引脚 → 一段短线 → `USBn_DP/DM` 端口， +**中间一颗元件都没有**；设计文档也写着「不要在 D± 上串电阻或加 ESD 之外的任何东西」， +而 ESD 在手机原厂尾插小板上。第 6 个口的对端是**同一块板上的 ESP32-S3 原生 USB** +（IO19=D−/IO20=D+），不过连接器、不出板、走线 ≈25mm（方案 §6.3 第 6 对）， +比五个手机口的处境好得多 ⇒ 照做，直连。 + +## U31：5V → 3.3V，只喂 U32 + + Vin = +5V（A2 的 U30，2A 轨） Vout = +3V3_HUB（**只**给 U32） + Hub 满配电流 ≈ 0.42 A（设计文档 §9.4） + 耗散 P = 0.42 × (5.0 − 3.3) = **0.714 W**，SOT-223 封装 + → PCB 上必须给 SOT-223 的散热片（2 脚 tab）铺一块铜： + θJA 靠铜面从 ~150 °C/W 压到 ~60 °C/W ⇒ ΔT ≈ 43 K，环境 40 °C 下结温 ~83 °C， + 对 125 °C 的上限有余量。**这条是 PCB 的约束，原理图上只能记着。** + 压差裕量：AMS1117 手册 p.1「dropout guaranteed maximum 1.3 V」（@0.8 A）， + 这里只有 0.42 A、压差 1.7 V ⇒ 够。 + +输出电容 **必须是固态钽** `C737` T491A226K010AT 22µF/10V（`C116575`）—— +AMS1117 手册 §Stability 原文：「The addition of **22µF solid tantalum** on the output +will ensure stability for all operating conditions.」**陶瓷不算数**（ESR 太低会让环路失稳）。 +⚠️ 这颗**1 脚是正极**（钽的条纹侧），本脚本用显式引脚号断言 `1` 在上、`2` 在下， +放件时若方向反了 `Sheet.place()` 会自己翻 180 重试（skill §6b/§6c）。 + +输入侧 `C752` 10µF/50V 0805（`C440198`）+ `C753` 100nF 0402（`C1525`），都在 `+5V` 干线上。 + +⚠️ **契约 §3 第 3 条：`+3V3_HUB` 与 `+3V3` 是两条轨。** 本页从头到尾没有 `+3V3`， +也没有 `+12V`；两条轨只在 GND 上相遇（`build()` 里有断言）。 + +## HUB_RST 的保命处理（契约 §3 第 1 条，硬约束） + +`R716` 10k 把 `RESET_N`(43) 上拉到 `+3V3_HUB`（R1 已有，本页原样保留、不许删， +`main()` 里逐脚断言它还在原位）。ESP32 复位 / 高阻 / 未烧固件时 `HUB_RST` 被这颗电阻 +拉高 = **Hub 保持工作**。理由写进页面文字：D13 之后 ESP32 的控制台与烧录口就挂在这颗 +Hub 后面，一旦「不驱动 = 复位」，误复位就等于自断控制台，而且下一次烧录也进不来 +（退路是 A3 的 `J33` 5P UART 应急口，但那是退路，不是设计依据）。 + +## 几何约定（skill） + +Y 轴向上（§1）、坐标全部 5 的倍数（§3/§8a-2b）、旗端口只落在导线端点（§8a/§8a-2）、 +端口方向决定标签在左还是在右（§8b：`IN` 与 `BI`/`OUT` 相反）、 +netport 符号只有 ~10 高，10 单位间距排一列不打架（§8b-2）、 +标题栏 `x>455 且 y<192`（§8c）、文字宽度 ≈ 字号×(CJK + 0.5×ASCII)（§12）。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, _on, call, two_pin, PARTS # noqa: E402 + +PAGE, NAME = '09d583ff95cd35d9', 'A4-HUB' +R2_PROJECT = '05a65c22f14846b8b95360ef8d3c1e2e' + +SRC = os.path.join(HERE, '_c2hub_live.json') # R1 载板 C2-HUB 实测 dump +OFF = (0, 0) # 整页原样搬，一个字不动 + +# ── ⚠ 唯一一处必须挪的 R1 图元：VBUS_UP 分压那一小块 ──────────────────── +# R1 载板 C2-HUB 上它坐在 y 45~135 / x 780~1060，搬到本页正好**落进 A4 标题栏** +# （skill §8c：标题栏是 x>455 且 y<192，比想象的大）—— 图上 R721 / R722 / +# UP_VBUS_DET 端口直接压在「PhoneRail-R2」和日期格上。 +# 六项几何验证不看这个（它只管连接性），`text_clash` 也只查文字， +# **是靠人眼截图发现的**。整块平移 +380，落到 x 730~1070 / y 425~515 那条空带 +# （上边是 U32 左列端口的 y≤465 @ x=760、下边是 +3V3_HUB 端口 y=525，都不撞）。 +SHIFT_RECT = (770, 40, 1080, 140) # 源页坐标里的这一块 +SHIFT_D = (0, 380) + + +def _in_rect(x, y, r=SHIFT_RECT): + return r[0] <= x <= r[2] and r[1] <= y <= r[3] + + +def shift_block(W, F, PT, place, exp): + u"""把 SHIFT_RECT 里的图元整块平移 SHIFT_D。跨界的导线一律当错误。""" + dx, dy = SHIFT_D + W2 = [] + n = 0 + for a, b, net in W: + ia, ib = _in_rect(*a), _in_rect(*b) + assert ia == ib, u'导线 %s %s-%s 跨过 SHIFT_RECT 边界，不能整块平移' % (net, a, b) + if ia: + W2.append(((a[0] + dx, a[1] + dy), (b[0] + dx, b[1] + dy), net)) + n += 1 + else: + W2.append((a, b, net)) + for lst in (F, PT): + for it in lst: + if _in_rect(it[2], it[3]): + it[2] += dx + it[3] += dy + n += 1 + moved = [] + for it in place: + if _in_rect(it[2], it[3]): + it[2] += dx + it[3] += dy + moved.append(it[0]) + n += 1 + for d in moved: + exp[d] = dict((k, (v[0] + dx, v[1] + dy)) for k, v in exp[d].items()) + assert sorted(moved) == ['R721', 'R722'], u'平移到的元件不是 R721/R722 而是 %s' % (moved,) + assert n, u'SHIFT_RECT 一个图元都没框到 —— 源页坐标变了？' + return W2 + +# ── 改动 3：端口方向按契约 §1.2 校正（键 = (网名, x, y) → 新 dir）─────────── +# R1 这两个是随手写的 BI；契约里 `UP_VBUS_DET` 是 A4 发给 A3、`HUB_RST` 是 A3 发给 A4， +# 主代理要拿端口清单对账，方向必须对得上。**只改 dir，坐标一个字不动**。 +# ⚠ 顺带：`IN` 与 `BI`/`OUT` 的标签方向正好相反（skill §8b），所以改 dir 会让标签换边 —— +# (1130,340) 是 rot=180，`BI` 时标签在左、`IN` 时在右，右边到 1145 只剩 15， +# 于是这一个连 rot 一起翻成 0（`PORT_ROT`），标签仍旧落在左边。 +PORT_DIR = { + ('UP_VBUS_DET', 930, 60): 'OUT', # A4 → A3（电脑在不在） + ('HUB_RST', 1130, 340): 'IN', # A3 → A4；(760,435) 那个 R1 本来就是 IN +} +PORT_ROT = {('HUB_RST', 1130, 340): 0} + +# ── 改动 2：第 6 个下行口（D13）────────────────────────────────────────── +# U32 右列 53=USBDN6_DM(680,535) / 54=USBDN6_DP(680,545)。 +# 右侧端口列在 x=760，R1 已占 405/415/425/455/465/525/575/585/595/605/615/625/635/645/655， +# **535 / 545 正好是空的**，插进去即可，间距仍是 10（skill §8b-2）。 +USB6 = [('USB6_DM', 535), ('USB6_DP', 545)] + +# ── 改动 1：U31 AMS1117-3.3 块（新画）─────────────────────────────────── +# 落在 R1 版图留下的空带 x 300~900 / y 190~330（`assert_clear()` 每次重算校验）。 +# 引脚（契约 §4 实测，rot 0，相对中心）：1 GND(-45,+10) 2 VOUT(-45,0) 3 VIN(-45,-10) 4 VOUT(+45,0) +# ⚠ GND 夹在 VIN 与 VOUT 中间、且在 VIN **上方**，所以「+5V 从左边平进、GND 往左再往下」 +# 是唯一不产生交叉的走法：GND 的下行点必须**在 +5V 端口符号左边** +# （+5V 引脚 x=440，IN+rot0 的符号往左伸到 380；GND 下行点 x=350），差 30 净空。 +U31_C = (700, 265) +U31_PINS = {'1': (655, 275), '2': (655, 265), '3': (655, 255), '4': (745, 265)} +C752_C, C753_C = (480, 235), (520, 235) # 输入 10µF/50V 0805 + 100nF 0402，跨距 ±20 +# ⚠ 2026-09-08 主代理实测更正（原来写 (810,250) / rot270 / ±15，推送时 place() 四轮翻转全对不上）： +# T491A226K010AT（C116575）**空页四个角度逐一放件读回**的结果是 +# rot 0 → pin1 (0,+20) rot 90 → pin1 (-20,0) rot180 → pin1 (0,-20) rot270 → pin1 (+20,0) +# ⇒ 正极（1 脚）朝上要的是 **rot 0**，跨距是 **±20 不是 ±15**。 +# `p1b-pins.json` 里那个 ±15 是别的封装的电容，skill §8d：引脚跨距因符号而异，必须读回。 +C737_C = (810, 245) # 输出 22µF/10V 固态钽：rot0、±20 ⇒ 1脚(正)在 265、2脚在 225 +NEW_PARTS = [ + ['U31', 'C6186', U31_C[0], U31_C[1], 0], + ['C752', 'C440198', C752_C[0], C752_C[1], 270], + ['C753', 'C1525', C753_C[0], C753_C[1], 270], + ['C737', 'C116575', C737_C[0], C737_C[1], 0], +] +BLOCK = (300, 190, 900, 330) # 新块要占的净空矩形（含端口标签） + +# ── U32 上故意不接的脚（设计文档 §21.6 / §21.6b）+ J23 的 SBU ────────────── +# 53/54 已被改动 2 接走，所以**不在**这张表里。 +NC = { + 'U32': ['14', '15', '16', '17', '18', '20', '21', '22', '23', '26', '27', '28', + '29', '30', '31', '32', '33', '34', '35', '36', '37', '38', '39', + '47', '48', '49', '50', '51', '55', '56'], + 'J23': ['A8', 'B8'], # SBU1/SBU2，USB2.0 用不上 +} + +# ── 靠同名旗/端口成网、导线上天然分块的网络（契约 §7 第 10 条）────────────── +# R1 这一页的画法就是「每个芯片脚一段短线 + 一个同名 netport」，所以页内网络天然多块。 +# 五个下行口 / USB6 / UP_VBUS_DET / +5V **不在**表里 —— 它们只许有一块。 +ALLOW_SPLIT = set([ + 'GND', '+3V3_HUB', + 'VDD18', 'VDD18PLL', 'XTAL1', 'XTAL2', 'RBIAS', + 'CFGSEL0', 'CFGSEL1', 'NONREM0', 'NONREM1', + 'UP_DP', 'UP_DM', 'VBUS_UP', 'VBUS_DET', 'HUB_RST', +]) + +# ⚠ 可用的文字区只有三块（R1 版图 + 标题栏 x>455 且 y<192 挤剩下的，`text_clash` +# / `label_clash` 每次重算）： +# A 标题 (45, 800) +# B 说明块 x 345~800 / y 690~780 —— R1 原来放说明的位置 +# C U31 说明块 x 45~355 / y 195~260 —— x=60 的地线在 y 270~300，别越过 260 +# D HUB_RST x 900~1145 / y 204~240 —— 就在 R716 底下；x=1130 的线从 y=250 起 +# 左下 y<190 那一片**不能用**：J23 的本体和 12 根引脚就在 x 155~360 / y 45~180。 +# y<665 而 x 345~680 那一片也不能用：U32 的符号本体在那里（引脚只到 y=660， +# 本体还要往上一点），所以 B 块最低只能到 y=690（R1 原来也是到这儿为止）。 +TEXTS = [ + (45, 800, u'【A4-HUB】板载 USB 2.0 七口 Hub + Hub 专用 3.3V —— 对电脑只有一根线（D13）', 14), + + # B：Hub 配置 / T6 / 第 6 口 / HUB_RST + (345, 780, u'U32 USB2517I：CFG_SEL[2:0]=110 = 内部默认配置 + strap 禁用（§21.6b）', 11), + (345, 762, u'CFG_SEL2(13) 纯输入接 +3V3_HUB；CFG_SEL1 经 R712 上拉、CFG_SEL0 经 R711 下拉', 11), + (345, 744, u'T6 已核 DS00001598C p.20 Table 7-1：0Ah/0Bh 端口禁用默认 00h ⇒ 七口全开', 11), + (345, 726, u'⇒ 口 6 无需改 strap 直接连线；口 1~5 → A5 五槽，口 6 → A3 的 ESP32 原生 USB', 11), + (345, 708, u'口 7 全开但悬空（R714/R715 已删：10k 上拉把 D+ 分到 1.98V 会变幽灵口）', 11), + (345, 690, u'HUB_RST 固件只在启动自检脉冲一次；误复位 = 自断控制台 + 下次烧不进去', 11), + + # C：U31 说明（就在 U31 块左边） + # ⚠ 2026-09-08 主代理改：原来这四行在 x=45，**被 R1 带来的地旗 (60,270) 压穿** + # —— `Ground rot=0` 的符号带 GND 标签往锚点**下方**伸到 y≈240，正好落在第 1/2 行上 + # （渲染成「U32 满配」上盖一个 GND）。同 A2-AUX 的两处叠字，六项几何验证与 + # `text_clash`（只查文字之间）都够不着，靠人眼截图发现。⇒ 整块挪到 x=100 / y 246~300、字号 10→9。 + # x=110 那一版会被 x=350 的地竖线（y 195~275）划穿 —— 脚本自带的 `text_clash` + # 当场报了出来；x=200 那一版又压上 U32 左排引脚（y 330~660 一直伸到 x=320）。 +# ⚠ 注意 `flag_clash` **不建模旗的标签占地**：`Ground rot=0` 的符号带 GND 字 +# 从锚点往下伸约 38 个单位（本页实测 (60,270) 的旗压到 y≈240）。把这个盒子 +# 连同 U32 的引脚包围盒 (310,330)-(690,670)、其余文字块一起当障碍全页扫一遍， +# **字号 10 的四行一个位置都放不下**，字号 9 才有 —— 这就是它比别的块小一号的原因。 + (100, 300, u'【U31】+5V → +3V3_HUB 专用 LDO（AMS1117-3.3）', 9), + (100, 282, u'U32 满配约 0.42A，挂不进 U19 那条 0.5A 的 +3V3 轨', 9), + (100, 264, u'耗散 0.42A×1.7V=0.71W @SOT-223，tab 必须铺铜', 9), + (100, 246, u'C737 必须 22µF 固态钽（手册 Stability），陶瓷不算数', 9), + + # D：HUB_RST 的保命上拉（就在 R716 底下） + (900, 240, u'⚠ R716 10k 是 HUB_RST 的保命上拉：', 10), + (900, 222, u'ESP32 复位 / 高阻时 Hub 保持工作 ——', 10), + (900, 204, u'控制台与烧录口就在它后面（D13）', 10), +] + + +# ══════════════════════════════════════════════════════════════════════════ +def load(path, off): + u"""整页读回并平移。返回 (导线[(a,b,net)], 旗, 端口, place, expect, 悬空引脚数)。 + + 与 `a2_aux.load()` 的两点不同： + 1. 本页**整页搬**，没有 keep 过滤（U32 一颗芯片就把全页导线连成一片，切不开）； + 2. **允许悬空引脚** —— U32 有 30 个脚是故意不接的（见 NC）， + `a2_aux` 那句 `assert hit` 在这里会当场炸掉。改成计数，由 `build()` 和 NC 对账。 + """ + src = json.load(io.open(path, encoding='utf-8')) + dx, dy = off + pts = src['wires'] + segs = [((int(round(pts[i][0])) + dx, int(round(pts[i][1])) + dy), + (int(round(pts[i + 1][0])) + dx, int(round(pts[i + 1][1])) + dy)) + for i in range(0, len(pts), 2)] + for a, b in segs: + assert a != b, u'%s 有零长度导线 %s（skill §8a）' % (path, (a,)) + assert (a[0] == b[0]) != (a[1] == b[1]), u'%s 有斜线 %s-%s' % (path, a, b) + + n = len(segs) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2 = segs[i] + b1, b2 = segs[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + + gname, gpins = defaultdict(set), defaultdict(set) + for lst in (src['flags'], src['ports']): + for f in lst: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + assert hit, u'%s 的旗/端口 %s 不在任何导线上' % (path, f[1]) + gname[find(hit[0])].add(f[1]) + nfloat = 0 + for p in src['parts']: + for q in p[9]: + xy = (int(round(q[2])) + dx, int(round(q[3])) + dy) + hit = [i for i in range(n) if _on(xy, segs[i][0], segs[i][1])] + if not hit: # 故意不接的脚，由 NC 兜底核对 + nfloat += 1 + continue + gpins[find(hit[0])].add('%s.%s' % (p[0], q[0])) + + W, F, PT = [], [], [] + for r_ in sorted(set(find(i) for i in range(n))): + names = gname.get(r_, set()) + assert len(names) <= 1, u'组 %s 名字不唯一：%s' % (sorted(gpins[r_])[:3], sorted(names)) + # 无名的短节点（J23 的两个 CC）沿用 R1 不起名，`#` 开头只给本地自检用、不下发 + net = sorted(names)[0] if names else '#' + '+'.join(sorted(gpins[r_])[:2]) + for i in range(n): + if find(i) == r_: + W.append((segs[i][0], segs[i][1], net)) + + for f in src['flags']: + xy = (int(round(f[2])) + dx, int(round(f[3])) + dy) + F.append([f[0].split('-')[0], f[1], xy[0], xy[1], f[4]]) + hit_dir = 0 + for p in src['ports']: + xy = (int(round(p[2])) + dx, int(round(p[3])) + dy) + d, rot = p[0].replace('Netport-', ''), p[4] + key = (p[1], xy[0], xy[1]) + if key in PORT_DIR: + d = PORT_DIR[key] + rot = PORT_ROT.get(key, rot) + hit_dir += 1 + PT.append([d, p[1], xy[0], xy[1], rot]) + assert hit_dir == len(PORT_DIR), \ + u'端口方向修正表只命中 %d/%d（坐标写错了）' % (hit_dir, len(PORT_DIR)) + + byname = {} + for k, v in PARTS.items(): + byname.setdefault(v['name'], k) + place, exp = [], {} + for p in src['parts']: + d, nm = p[0], p[1] + base = nm.split('_C')[0] if '_C' in nm else nm + k = byname.get(nm) or byname.get(base) + assert k, u'eda-parts.json 里找不到器件 %r（%s）' % (nm, d) + assert not p[6], u'%s 是镜像件，Sheet.place 处理不了' % d + place.append([d, k, int(round(p[3])) + dx, int(round(p[4])) + dy, p[5]]) + exp[d] = dict((str(q[0]), (int(round(q[2])) + dx, int(round(q[3])) + dy)) + for q in p[9]) + return W, F, PT, place, exp, nfloat + + +def assert_clear(W, F, PT, exp, rect): + u"""新块要占的矩形里不许有 R1 的任何图元 —— 坐标改错了当场终止，别等截图。""" + x0, y0, x1, y1 = rect + bad = [] + for a, b, net in W: + for p in (a, b): + if x0 <= p[0] <= x1 and y0 <= p[1] <= y1: + bad.append(u'导线 %s 端点 %s' % (net, (p,))) + if a[0] == b[0] and x0 <= a[0] <= x1 \ + and min(a[1], b[1]) < y1 and max(a[1], b[1]) > y0: + bad.append(u'竖线 %s x=%d 穿过' % (net, a[0])) + if a[1] == b[1] and y0 <= a[1] <= y1 \ + and min(a[0], b[0]) < x1 and max(a[0], b[0]) > x0: + bad.append(u'横线 %s y=%d 穿过' % (net, a[1])) + for it in F + PT: + if x0 <= it[2] <= x1 and y0 <= it[3] <= y1: + bad.append(u'旗/端口 %s @(%d,%d)' % (it[1], it[2], it[3])) + for d, ps in exp.items(): + for num, xy in ps.items(): + if x0 <= xy[0] <= x1 and y0 <= xy[1] <= y1: + bad.append(u'引脚 %s.%s @%s' % (d, num, (xy,))) + assert not bad, u'新块矩形 %s 里有 R1 的东西：\n %s' % (rect, '\n '.join(sorted(set(bad)))) + + +def add_u31(s): + u"""U31 AMS1117-3.3：+5V(IN 端口) → U31 → +3V3_HUB(Power 旗)。 + + 走法（Y 轴向上）： + + +5V ─●──●──────── 3 VIN ← y=255，从左平进，全程无竖线 + C752 C753 2 VOUT ──< +3V3_HUB ← 635，BI+rot180，符号往左 + │ │ 1 GND ──┐ + ⏚─────┴────┴──────────┬────┘ ← GND 先往左到 x=350 再下行 + 350,195 y=215 地干线 ──● C737 下脚 + + 2 脚和 4 脚都是 VOUT（4 脚是散热片），**两个都接**：4 脚往右接 C737 与电源旗， + 2 脚被 1/3 脚夹在中间（同一个 x、上下各差 10）只能往左，走 y=255 与 y=275 之间那条 + 20 单位的走廊，末端放一个同名 `+3V3_HUB` netport —— + netport 符号只有 ~10 高，R1 这一页两列端口就是 10 单位间距排下来的（skill §8b-2）。 + """ + p = U31_PINS + # 输入：+5V 干线（C752 / C753 的上脚落在这条线上，EasyEDA 会在引脚处截断，skill §8b） + # ⚠ 两颗电容必须待在 x<535 —— 535~635 是下面那个 `+3V3_HUB` 端口标签占的横向范围。 + s.w('+5V', (440, 255), (C752_C[0], 255), (C753_C[0], 255), p['3']) + s.port('IN', '+5V', 440, 255, 0) # IN + rot0 ⇒ 符号在**左**（§8b），占 380~440 + # 地：U31 GND 左出 → x=350 下行 → 地旗；y=215 是全块的地干线，T 在竖线中段 + s.w('GND', p['1'], (350, 275), (350, 195)) + s.gnd(350, 195, 0) # Ground rot0：符号在下、引脚在上，导线从上方来 + s.w('GND', (350, 215), (C752_C[0], 215), (C753_C[0], 215), + (C737_C[0], 215), (C737_C[0], 225)) + # 输出：4 脚（散热片）→ C737 → 电源旗；2 脚往左出一个同名端口 + s.w('+3V3_HUB', (635, 265), p['2']) + s.port('BI', '+3V3_HUB', 635, 265, 180) # BI + rot180 ⇒ 符号在**左**，占 535~635 + s.w('+3V3_HUB', p['4'], (C737_C[0], 265), (880, 265), (880, 320)) + s.pwr('+3V3_HUB', 880, 320, 0) # Power rot0：符号在上、引脚在下，导线从下方来 + + +def add_usb6(s): + u"""第 6 个下行口引到右侧端口列（D13）。串阻 / ESD 一律不加，同 R1 的口 1~5。""" + for net, y in USB6: + s.w(net, (680, y), (760, y)) + s.port('BI', net, 760, y, 0) # BI + rot0 ⇒ 符号在右，占 760~854 + + +def _text_boxes(s): + out = [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + w = size * (cjk + 0.5 * (len(txt) - cjk)) + out.append((x, y - size * 0.8, x + w, y + size * 0.8, txt)) + return out + + +def text_clash(s, exp): + u"""文字压在导线 / 引脚 / 旗端口上（同 a1_input.py / a2_aux.py）。""" + errs = [] + pts = [] + for d, ps in exp.items(): + if '?' in ps: + for xy in ps['?']: + pts.append((xy[0], xy[1], u'引脚 %s' % d)) + else: + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + for x0, y0, x1, y1, txt in _text_boxes(s): + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:26])) + for a, b, net in s.W: + if a[1] == b[1]: + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (net, a[1], txt[:26])) + else: + if x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (net, a[0], txt[:26])) + return sorted(set(errs)) + + +def label_clash(s): + u"""端口的符号+标签往锚点某一侧伸出去 ~40+6.7×字符（skill §8b），会压住页面文字。 + + 契约 §7 第 8 条点名说这是本项目的常见事故，而 `flag_clash` 的「横向 <20」判据 + 根本够不着。这里把标签算成一个盒子，和**页面文字**逐个比，顺带查越框。 + """ + errs = [] + tb = _text_boxes(s) + for d, net, x, y, rot in s.PT: + left = (d == 'IN') == (int(rot) % 360 == 0) # §8b：IN 与 BI/OUT 正好相反 + # 净空用 6.7/字符（§8b 说是偏保守的安全值）；**越框**只能用实测的 5/字符 + # （`PORTTEST` 8 字符实测 80 单位 = 40 + 5×8），否则 R1 那个贴着右边框的 + # `NONREM0`（1070 + 40 + 5×7 = 1145，正好压线）会被误判成越框。 + for k, tag in ((6.7, None), (5.0, 'frame')): + w = 40 + k * len(net) + bx0, bx1 = (x - w, x) if left else (x, x + w) + if tag == 'frame': + if bx0 < 20 or bx1 > 1145: + errs.append(u'端口 %s @(%d,%d,%s,rot%d) 的标签越框 %.0f~%.0f' + % (net, x, y, d, rot, bx0, bx1)) + continue + for tx0, ty0, tx1, ty1, txt in tb: + if bx0 < tx1 and tx0 < bx1 and ty0 < y + 6 and y - 6 < ty1: + errs.append(u'端口 %s @(%d,%d) 的标签压住文字: %s' % (net, x, y, txt[:26])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + u"""两面旗/端口的符号叠在一起（同 a1_input.py / a2_aux.py）。""" + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +def build(): + W, F, PT, place, exp, nfloat = load(SRC, OFF) + W = shift_block(W, F, PT, place, exp) + want_nc = sum(len(v) for v in NC.values()) + len(USB6) # 53/54 在源页上还是悬空的 + assert nfloat == want_nc, \ + u'源页悬空引脚 %d 个，NC 表 + 第 6 口 = %d 个（对不上就是漏接或者表过期）' \ + % (nfloat, want_nc) + assert_clear(W, F, PT, exp, BLOCK) + + s = Sheet(PAGE, NAME) + s.W += W + s.F += F + s.PT += PT + add_u31(s) + add_usb6(s) + for t in TEXTS: + s.txt(t[0], t[1], t[2], t[3]) + + place = place + [list(x) for x in NEW_PARTS] + exp = dict(exp) + exp['U31'] = dict(U31_PINS) # 4 脚件，逐脚断言 + exp['C752'] = two_pin(C752_C[0], C752_C[1]) # 无极性，只比坐标集合 + exp['C753'] = two_pin(C753_C[0], C753_C[1]) + exp['C737'] = {'1': (C737_C[0], C737_C[1] + 20), # ⚠ 钽电容：1 脚是正极，必须在上 + '2': (C737_C[0], C737_C[1] - 20)} # 跨距 ±20、rot0（本页实测，见 C737_C 处注释） + assert len(set(d for d, _k, _x, _y, _r in place)) == len(place), u'位号撞车' + # 契约 §2：A4 只许用 U31 / U32 / Y1 / J23 + R708~R730 + C737 / C740~C760 + for d, _k, _x, _y, _r in place: + ok = d in ('U31', 'U32', 'Y1', 'J23') \ + or (d[0] == 'R' and d[1:].isdigit() and 708 <= int(d[1:]) <= 730) \ + or (d == 'C737') \ + or (d[0] == 'C' and d[1:].isdigit() and 740 <= int(d[1:]) <= 760) + assert ok, u'位号 %s 不在契约 §2 给 A4 的区段里' % d + # 契约 §3 第 3 条 + 本页不许出现 +12V + for it in s.F + s.PT: + assert it[1] not in ('+3V3', '+12V'), u'本页不该出现 %s' % it[1] + return s, place, exp + + +def main(): + push = '--push' in sys.argv + s, place, exp = build() + s.assert_grid() + pins = {} + for d, want in exp.items(): + if '?' in want: + a, b = sorted(want['?']) + pins[d] = {'1': a, '2': b} + else: + pins[d] = dict(want) + errs = s.netcheck(pins, NC, ALLOW_SPLIT) + errs += text_clash(s, exp) + label_clash(s) + flag_clash(s) + # 契约 §3 第 1 条的硬约束复核：HUB_RST 必须有一颗 10k 上拉到 +3V3_HUB + assert PARTS['C25744']['name'] == '0402WGF1002TCE', u'C25744 不再是 10k 电阻' + r716 = [it for it in place if it[0] == 'R716'] + assert len(r716) == 1 and r716[0][1] == 'C25744', u'R716 不是 10k（HUB_RST 上拉没了）' + assert pins['R716']['1'] == (1130, 320) and pins['R716']['2'] == (1130, 280), \ + u'R716（HUB_RST 上拉）位置变了，重新核对 §3 第 1 条' + # 第 6 个下行口确实接出去了 + for net, y in USB6: + assert any(it[1] == net and it[0] == 'BI' for it in s.PT), u'%s 端口没画' % net + print(u'R1 C2-HUB 原样搬 %d 件 + 新增 %d 件（U31 块）= %d 件' + % (len(place) - len(NEW_PARTS), len(NEW_PARTS), len(place))) + s.report(len(place), errs) + if not push: + return + call("await eda.dmt_Project.openProject('%s'); await new Promise(r=>setTimeout(r,2500)); return 1;" + % R2_PROJECT) + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a5-slots-nc.json b/.claude/r2/a5-slots-nc.json new file mode 100644 index 0000000..afe4b83 --- /dev/null +++ b/.claude/r2/a5-slots-nc.json @@ -0,0 +1,26 @@ +{ + "J34": [ + "5", + "6", + "7", + "8", + "42", + "41" + ], + "J35": [ + "5", + "6", + "7", + "8", + "42", + "41" + ], + "J36": [ + "5", + "6", + "7", + "8", + "42", + "41" + ] +} \ No newline at end of file diff --git a/.claude/r2/a5_slots.py b/.claude/r2/a5_slots.py new file mode 100644 index 0000000..c908d22 --- /dev/null +++ b/.claude/r2/a5_slots.py @@ -0,0 +1,457 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A5-SLOTS** 页：PCI-E x4 插槽阵（槽 1~3）。 + + /c/Python314/python .claude/r2/a5_slots.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a5_slots.py --push # 清页 + 重画（幂等，只有主代理能跑） + +配套的 `a5b_slots.py` 画槽 4/5 + 5 个 D± 退路座（J39~J43）。**为什么要拆两页见下面 §版面**。 + +本页是 `b4_edge.py`（刀片金手指）的**对端**：64 针的语义完全由 `b4_edge.PIN_NET` 定， +本脚本直接 `import` 它，不再抄一份，改针位表只能改那一处。 + +## ⚠️ 唯一一处**故意不镜像**刀片：`PRSNT#` + +刀片（`b4_edge.py`）把 `A1` 和 `B31` **短接在一起**，而且那个网络在刀片上没有别的对端 —— +它就是一段悬空的跳线（PCI-E CEM 里 add-in card 的标准做法）。 +所以在底板（= 主板侧）上这两针**必须是两个不同的节点**，才构成在位检测回路： + +| | `A1`（PRSNT1#） | `B31`（PRSNT2#） | +|---|---|---| +| 真 PCIe 主板 | 接地 | 上拉 + 被读 | +| **本页（底板）** | **`GND`** | **`PRSNT{n}#`** → A3 的 ESP32 输入（上拉也在 A3）| +| 刀片 B4-EDGE | ←── 两针短接（插上才把 B31 拉到地）──→ | + +⛔ **如果底板也照字面「镜像」、把 A1/B31 并成同一个 `PRSNT{n}#`**， +整条回路里就一个对地通路都没有：ESP32 靠上拉永远读到高， +**插不插刀片都报「未插入」，而且 DRC/ERC/几何验证一道都不会响**。 +`ROLE_OVERRIDE` 里就这一条，改它之前先把上面这张表看完。 + +## 版面：5 个槽一页放不下，拆成 A5 + A5B（先算账再动手） + +每槽 64 针两排同高、pitch 10 ⇒ 引脚跨度 **310**，两排引脚横跨 70。 +按「地梳齿 + 母线 + 信号端口排在母线与引脚之间」（抄 `b4_edge`）压到最紧： + +``` +cx-170 ── 地旗体 ─┐ +cx-160 ── A 排地母线（19 根梳齿从 cx-35 拉过来） +cx-140 ── A 排信号端口列（标签朝内伸，符号也朝内，左边不占地） +cx-80 / cx-65 ── A 排 +12V / +3V3 汇流竖线 +cx-35 / cx+35 ── 引脚列 +cx+80 ── B 排 +12V 汇流竖线 +cx+140 ── B 排信号端口列 +cx+160 ── B 排地母线 +cx+175 ── B8 的 +3V3 东出通道（母线在这一行断开） +cx+185 ── 旗体右边界 +``` + +⇒ 每槽净宽 **355**、槽距 ≥ 365。一行 3 槽 = 1085 ≤ 页面可用 1125 ✅； +4 槽 = 1450 ❌；5 槽 = 1815 ❌。竖着排两行也不行：一行连旗带引脚约 400， +两行 820 > 802，而且下面那一行必然压进标题栏（`x>455 且 y<192`）。 + +**⇒ 结论：A5-SLOTS 放槽 1~3，新开 A5B-SLOTS 放槽 4~5 + 全部 5 个 D± 退路座。** +退路座整组放在 A5B 是因为 A5 上一寸空白都不剩了，而 A5B 空出一大片； +它们是同一件事（D12 的退路），放一起也好找。 + +## 交叉点 0 是设计出来的，不是碰巧 + +母线在这种页面上是一堵墙，**任何信号都别想横穿**。所以： + +- A 排：所有信号支线止步于 `cx-140`、电源汇流止步于 `cx-65`，母线在 `cx-160` —— + 母线可以从 A4 一路连到 A31 **不用断**，全 A 排只要一面地旗。 +- B 排：母线只在 **B8 那一行断开**（B9/B10 本来就悬空）， + 这是 `+3V3` 横穿到母线以东挂旗的唯一通道，两段各自带一面地旗（抄 `b4_edge` §17.2）。 +- `A1` 的地不往西走（会和 A2/A3 的 +12V 汇流竖线打架），改成从引脚**竖直往上引 25 挂旗**。 + +## ALLOW_SPLIT 放宽了哪些，凭什么 + +`GND` `+12V` `+3V3` `+5V` 是靠同名旗/端口成网的，天然分块。 +另外放行 **`INT#`**：五个槽的 B11 是 wire-OR 并联，**唯一一颗上拉在 A3**， +每槽出一个同名 OUT 端口是这种总线的标准画法（而且它还跨两页，本来就连不成一块）。 +`PRSNT{n}#` / `SDA{n}` / `SCL{n}` / `VDAC{n}` / `EFUSE_EN{n}` **都不放行**，一块就是一块。 + +放宽之后靠 `check_pin_nets()` 兜底：**5 槽 × 64 针逐脚**断言 +「这根针踩着的那段导线，声明的网络名 == 期望名」，少接一根、接错一根当场报出来。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, by_rel, _on # noqa: E402 +from b4_edge import PIN_NET, EDGE_REL, WV4_REL # noqa: E402 + +PAGE, NAME = '2c73c5bf77f34053', 'A5-SLOTS' + +EDGE, WV4 = 'C19188869', 'C225106' # PCIE-64P11L（SOFNG）/ A1251WV-S-4P + +# ── ⚠ 2026-09-08 换料结掉 T8：SAMTEC PCIE-064-02-F-D-TH → SOFNG PCIE-64P11L ───── +# 用户要 PC 标准的便宜料。要注意的是**两颗的脚号体系不一样**： +# +# 刀片 `PCIE-X4-EDGE-64P`（金手指，符号借自 Samtec） 脚号 = `A1`~`A32` / `B1`~`B32` +# 底板 `PCIE-64P11L`（真插槽） 脚号 = `1`~`64`，**脚名**才是 A1~B32 +# +# 换算：`A(n) → 脚号 n`、`B(n) → 脚号 32+n`。 +# 引脚**相对坐标两颗完全一致**（A 排 x=-35 / B 排 x=+35，y = 155-10*(n-1))， +# 所以版图、母线、端口位置一个字都不用改 —— 只有 `expect()` / `nc_table()` 换脚号。 +# ⚠ 它比金手指**多一根 `65` 脚 = 外壳/屏蔽，在 (0,+175)**（符号顶端正中），本页接 GND； +# 不接的话 `verify_sch` 会报悬空引脚。 +# ⛔ 它是**贴片立式**（原来那颗是直插）：保持力只靠焊盘剪切。五片刀片各驮一块手机主板， +# M4 布板时必须另加固定件（梳齿 / 压条），不能只靠插槽 —— 已写进页面文字与 eda-parts role。 +SHIELD_PIN, SHIELD_REL = '65', (0, 175) + + +def slot_pin(cem): + u"""CEM 针名（`A1`~`A32` / `B1`~`B32`）→ `PCIE-64P11L` 符号的脚号（`'1'`~`'64'`）。""" + i = int(cem[1:]) + assert 1 <= i <= 32 and cem[0] in 'AB', cem + return str(i if cem[0] == 'A' else 32 + i) + + +SLOT_REL = dict((slot_pin(k), v) for k, v in EDGE_REL.items()) +SLOT_REL[SHIELD_PIN] = SHIELD_REL +assert len(SLOT_REL) == 65 and SLOT_REL['1'] == (-35, 155) and SLOT_REL['33'] == (35, 155) +assert SLOT_REL['64'] == (35, -155), SLOT_REL['64'] + +SLOT_REF = {1: 'J34', 2: 'J35', 3: 'J36', 4: 'J37', 5: 'J38'} +WV_REF = {1: 'J39', 2: 'J40', 3: 'J41', 4: 'J42', 5: 'J43'} + +# ── 本页的槽位（A5B 画槽 4/5，坐标在 a5b_slots.py）──────────────────── +SLOT_XY = {1: (200, 470), 2: (565, 470), 3: (930, 470)} # 槽距 365 + +# ── 针 → 网络：刀片的 PIN_NET 加槽号后缀，只有 A1 例外（见表头）────── +ROLE_OVERRIDE = {'A1': 'GND'} # ⚠ 底板 = 主板侧，A1 接地；改前先读表头 +GLOBAL = set(['GND', '+12V', '+3V3', '+5V', 'INT#', 'NC']) # 不加槽号的 + + +def base_net(pin, n): + u"""刀片侧针名 → 底板侧网络名（n = 槽号）。""" + role = ROLE_OVERRIDE.get(pin, PIN_NET[pin]) + if role in GLOBAL: + return role + if role == 'PRSNT#': + return 'PRSNT%d#' % n + if role.startswith('USB_'): # USB_DP / USB_DM + return 'USB%d_%s' % (n, role[4:]) + return '%s%d' % (role, n) # SCL / SDA / VDAC / EFUSE_EN + + +# 逐脚自检：镜像关系必须是「除了 A1 全都对得上」 +assert len(PIN_NET) == 64, len(PIN_NET) +assert PIN_NET['A1'] == 'PRSNT#' and PIN_NET['B31'] == 'PRSNT#', u'刀片侧 PRSNT# 针位变了' +assert base_net('A1', 1) == 'GND' and base_net('B31', 1) == 'PRSNT1#' +assert [p for p in PIN_NET if PIN_NET[p] != base_net(p, 1).rstrip('1') + and base_net(p, 1) not in ('USB1_DP', 'USB1_DM', 'PRSNT1#')] == ['A1'], \ + u'除了 A1 之外还有针没有镜像刀片 —— 要么 PIN_NET 变了，要么 base_net 写漏了' + +NCPINS = sorted([p for p, r in PIN_NET.items() if r == 'NC']) +assert NCPINS == sorted(['A5', 'A6', 'A7', 'A8', 'B9', 'B10']), NCPINS + +AGND = [n for n in range(1, 33) if base_net('A%d' % n, 1) == 'GND'] +BGND = [n for n in range(1, 33) if base_net('B%d' % n, 1) == 'GND'] +assert AGND[0] == 1 and len(AGND) == 20, AGND # A1 也归了地 +assert len(BGND) == 20, BGND +BGND_TOP = [n for n in BGND if n <= 7] # B4 / B7，母线上段 +BGND_BOT = [n for n in BGND if n >= 12] # B12 以下，母线下段 +assert BGND_TOP == [4, 7] and BGND_BOT[0] == 12 and BGND_BOT[-1] == 32 + +# A 排信号（脚号, 端口方向）；A1 已经归地，不在这里 +A_SIG = [(11, 'IN'), (16, 'IN'), (19, 'IN'), (32, 'IN')] +B_SIG = [(5, 'BI'), (6, 'BI'), (11, 'OUT'), (14, 'BI'), (15, 'BI'), (31, 'OUT')] + +# D± 退路座（A1251WV-S-4P）：逐槽镜像刀片 J2 的 1=+5V 2=DP 3=DM 4/5/6=GND +WV_NET = {'1': '+5V', '2': 'USB%d_DP', '3': 'USB%d_DM', + '4': 'GND', '5': 'GND', '6': 'GND'} + + +# ── 一个槽的版图 ────────────────────────────────────────────────────── +def geom(cx, cy): + return dict(AX=cx - 35, BX=cx + 35, ABUS=cx - 160, BBUS=cx + 160, + APORT=cx - 140, BPORT=cx + 140, + A12=cx - 80, A33=cx - 65, B12=cx + 80, B33=cx + 175) + + +def rowy(cy, n): + u"""第 n 号针的 y（A/B 两排同高，pitch 10，A1/B1 在 cy+155）。""" + return cy + 155 - 10 * (n - 1) + + +def draw_slot(s, n, cx, cy): + g = geom(cx, cy) + AX, BX = g['AX'], g['BX'] + + def r(k): + return rowy(cy, k) + + def net(pin): + return base_net(pin, n) + + # ── A 排：地 ──────────────────────────────────────────────────── + # A1 单独往上挂旗：它往西走会和 A2/A3 的 +12V 汇流竖线在 (A12, r1) 撞成交叉 + s.w('GND', (AX, r(1)), (AX, r(1) + 25)) + s.gnd(AX, r(1) + 25, 180) + # 65 脚 = 连接器外壳/屏蔽（符号顶端正中 (0,+175)），接地。金手指那颗没有这根针。 + # ⚠ 不要往**上**引再挂一面地旗：cy+195 那一带是页眉文字的地盘（A5B 上就撞了）。 + # 往左 35 正好落在 A1 那根地短线 (AX, r1)~(AX, r1+25) 的中段上 —— T 型相连， + # 不新增旗、不占用连接器上方的任何空间。 + s.w('GND', (cx, cy + 175), (AX, cy + 175)) + for k in AGND[1:]: + s.w('GND', (AX, r(k)), (g['ABUS'], r(k))) + # 母线连续（A4 → A31）：信号止步于 cx-140、电源止步于 cx-65，没人横穿 + s.w('GND', (g['ABUS'], r(4)), (g['ABUS'], r(31) - 20)) + s.gnd(g['ABUS'], r(31) - 20, 0) + + # ── A 排：+12V（A2/A3）与 +3V3（A9/A10），各自一面 Power 旗 ────── + for k in (2, 3): + s.w('+12V', (AX, r(k)), (g['A12'], r(k))) + s.w('+12V', (g['A12'], r(3)), (g['A12'], r(1) + 10)) + s.pwr('+12V', g['A12'], r(1) + 10, 0) + for k in (9, 10): + s.w('+3V3', (AX, r(k)), (g['A33'], r(k))) + # 往上挂到 A5~A8 那段悬空针留出来的空白里（旗体上沿离 A4 的梳齿还有 10） + s.w('+3V3', (g['A33'], r(10)), (g['A33'], r(9) + 20)) + s.pwr('+3V3', g['A33'], r(9) + 20, 0) + + # ── A 排：信号端口（+5V ×2 / EFUSE_ENn / VDACn）────────────────── + for k, d in A_SIG: + nm = net('A%d' % k) + s.w(nm, (AX, r(k)), (g['APORT'], r(k))) + s.port(d, nm, g['APORT'], r(k), 180) # IN + rot180 = 符号/标签朝内 + + # ── B 排：地（母线在 B8 那一行断开，给 +3V3 让出东出通道）──────── + for k in BGND_TOP: + s.w('GND', (BX, r(k)), (g['BBUS'], r(k))) + s.w('GND', (g['BBUS'], r(4) + 20), (g['BBUS'], r(7))) + s.gnd(g['BBUS'], r(4) + 20, 180) + for k in BGND_BOT: + s.w('GND', (BX, r(k)), (g['BBUS'], r(k))) + s.w('GND', (g['BBUS'], r(12)), (g['BBUS'], r(32) - 20)) + s.gnd(g['BBUS'], r(32) - 20, 0) + + # ── B 排：+12V（B1/B2/B3）与 +3V3（B8，穿母线缺口）─────────────── + for k in (1, 2, 3): + s.w('+12V', (BX, r(k)), (g['B12'], r(k))) + s.w('+12V', (g['B12'], r(3)), (g['B12'], r(1) + 20)) + s.pwr('+12V', g['B12'], r(1) + 20, 0) + s.w('+3V3', (BX, r(8)), (g['B33'], r(8))) + s.w('+3V3', (g['B33'], r(8)), (g['B33'], r(8) - 20)) + s.pwr('+3V3', g['B33'], r(8) - 20, 180) + + # ── B 排：信号端口（SCLn/SDAn/INT#/USBn_DP/DM/PRSNTn#）─────────── + for k, d in B_SIG: + nm = net('B%d' % k) + s.w(nm, (BX, r(k)), (g['BPORT'], r(k))) + s.port(d, nm, g['BPORT'], r(k), 180) # BI/OUT + rot180 = 标签朝内 + + +def draw_wv(s, n, jx, jy): + u"""D± 退路座（D12）：1=+5V 2=USBn_DP 3=USBn_DM 4/5/6=GND，引脚全部朝左。""" + px, gx, ptx = jx - 25, jx - 45, jx - 75 + for dy, nm, d, rot in ((15, '+5V', 'IN', 0), + (5, 'USB%d_DP' % n, 'BI', 180), + (-5, 'USB%d_DM' % n, 'BI', 180)): + s.w(nm, (px, jy + dy), (ptx, jy + dy)) + s.port(d, nm, ptx, jy + dy, rot) # 标签一律朝左（背离座子） + # 地分两段：脚 5（固定脚，在最上）往上挂，脚 4/6 往下挂 —— + # 中间三行是信号，一根竖着的地母线穿过去就是三个交叉点 + s.w('GND', (px, jy + 35), (gx, jy + 35)) + s.w('GND', (gx, jy + 35), (gx, jy + 55)) + s.gnd(gx, jy + 55, 180) + s.w('GND', (px, jy - 15), (gx, jy - 15)) + s.w('GND', (px, jy - 35), (gx, jy - 35)) + s.w('GND', (gx, jy - 15), (gx, jy - 55)) + s.gnd(gx, jy - 55, 0) + + +# ── 组装 ────────────────────────────────────────────────────────────── +def placement(slots, wvs): + return ([[SLOT_REF[n], EDGE, cx, cy, 0] for n, (cx, cy) in sorted(slots.items())] + + [[WV_REF[n], WV4, jx, jy, 0] for n, (jx, jy) in sorted(wvs.items())]) + + +def expect(slots, wvs): + out = {} + for n, (cx, cy) in slots.items(): + out[SLOT_REF[n]] = by_rel(cx, cy, SLOT_REL) # 脚号 1~64 + 65 屏蔽 + for n, (jx, jy) in wvs.items(): + out[WV_REF[n]] = by_rel(jx, jy, WV4_REL) + return out + + +def nc_table(slots): + return dict((SLOT_REF[n], [slot_pin(p) for p in NCPINS]) for n in slots) + + +def allow_split(slots, wvs): + u"""只放行「靠同名旗/端口成网」的：电源地、跨页 wire-OR 的 INT#、以及本页同时有槽和退路座的 D±。""" + out = set(['GND', '+12V', '+3V3', '+5V', 'INT#']) + for n in wvs: + if n in slots: # 槽和它的退路座在同一页 = 天然两块 + out.add('USB%d_DP' % n) + out.add('USB%d_DM' % n) + return out + + +def build(slots, wvs, texts, page, name): + s = Sheet(page, name) + for n, (cx, cy) in sorted(slots.items()): + draw_slot(s, n, cx, cy) + for n, (jx, jy) in sorted(wvs.items()): + draw_wv(s, n, jx, jy) + for t in texts: + s.txt(t[0], t[1], t[2], t[3]) + return s + + +# ── 逐脚对账（ALLOW_SPLIT 放宽之后的硬判据）────────────────────────── +def check_pin_nets(s, slots, wvs): + u"""5 槽 × 64 针 + 退路座 6 针：断言每根针踩着的导线声明的网络名 == 期望名。""" + errs, seen = [], 0 + for n, (cx, cy) in sorted(slots.items()): + g = geom(cx, cy) + for p in sorted(PIN_NET): + x = g['AX'] if p[0] == 'A' else g['BX'] + xy = (x, rowy(cy, int(p[1:]))) + want = base_net(p, n) + got = sorted(set(w[2] for w in s.W if _on(xy, w[0], w[1]))) + seen += 1 + if want == 'NC': + if got: + errs.append(u'%s(槽%d).%s 应当悬空，却踩在 %s 上' + % (SLOT_REF[n], n, p, got)) + elif got != [want]: + errs.append(u'%s(槽%d).%s 应当是 %s，实际踩着 %s' + % (SLOT_REF[n], n, p, want, got or u'（空）')) + for n, (jx, jy) in sorted(wvs.items()): + for p, dy in (('1', 15), ('2', 5), ('3', -5), ('4', -15), ('5', 35), ('6', -35)): + xy = (jx - 25, jy + dy) + want = WV_NET[p] + want = want % n if '%d' in want else want + got = sorted(set(w[2] for w in s.W if _on(xy, w[0], w[1]))) + seen += 1 + if got != [want]: + errs.append(u'%s(槽%d).%s 应当是 %s，实际踩着 %s' + % (WV_REF[n], n, p, want, got or u'（空）')) + return errs, seen + + +def text_clash(s, exp): + u"""文字压在导线 / 引脚 / 旗端口上（抄 a1_input.py，本页文字全靠这条守住空白带）。""" + errs, boxes, pts = [], [], [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + w = size * (cjk + 0.5 * (len(txt) - cjk)) + boxes.append((x, y - size * 0.8, x + w, y + size * 0.8, txt)) + for d, ps in exp.items(): + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + for x0, y0, x1, y1, txt in boxes: + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:26])) + for a, b, nt in s.W: + if a[1] == b[1]: + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (nt, a[1], txt[:26])) + elif x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (nt, a[0], txt[:26])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + u"""两面旗/端口的符号叠在一起 —— crossings() 查不到（旗不是导线）。""" + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +def port_extent(s, slots, wvs, pad=20): + u"""端口的符号+标签往哪边伸多远（契约 §7 第 8 条：约 70~100 个单位，flag_clash 够不着）。 + + IN + rot0 / BI/OUT + rot180 → 标签在**左**；IN + rot180 / BI/OUT + rot0 → 在**右**（skill §8b）。 + 这里只查一件事：某个端口的标签有没有伸进**别的槽**的引脚列。 + """ + errs = [] + cols = [] + for n, (cx, cy) in slots.items(): + cols.append((SLOT_REF[n], cx - 35, cx + 35, rowy(cy, 32), rowy(cy, 1))) + for n, (jx, jy) in wvs.items(): + cols.append((WV_REF[n], jx - 25, jx + 25, jy - 35, jy + 35)) + for d, nm, x, y, rot in s.PT: + w = 40 + 6.7 * len(nm) # skill §8b 的保守估算 + left = (d == 'IN') == (rot == 0) # IN+rot0 / BI·OUT+rot180 → 标签在左 + x0, x1 = (x - w, x) if left else (x, x + w) + # 归属：先按 y 落在谁的引脚带里，再按 x 取最近的一件 + cand = [c for c in cols if c[3] <= y <= c[4]] or cols + own = min(cand, key=lambda c: abs(x - (c[1] + c[2]) / 2.0))[0] + for ref, cx0, cx1, cy0, cy1 in cols: + if ref == own: + continue # 自己那一件：标签朝内压在自己的引出线上是有意的 + if cy0 - 40 <= y <= cy1 + 40 and x0 <= cx1 + pad and x1 >= cx0 - pad: + errs.append(u'端口 %s @(%d,%d) 的标签（%d~%d）伸进了 %s 的地盘' + % (nm, x, y, x0, x1, ref)) + return sorted(set(errs)) + + +# ── 页面文字 ────────────────────────────────────────────────────────── +TEXTS = [ + (45, 800, u'【A5-SLOTS】5 个 PCI-E x4 插槽之 槽 1~3（槽 4/5 与 5 个 D± 退路座在 A5B-SLOTS：一页排不下 5 槽，算账见脚本表头）', 13), + (45, 778, u'⚠ 插槽旁必须丝印「NOT PCIe — PhoneRail blade only」（方案 §5.2）—— 本页只是写在这里，PCB 阶段落地', 11), + (45, 758, u'针位逐脚镜像刀片 B4-EDGE 的 PIN_NET（T4 已对 CEM 核过）：+12V=A2/A3/B1/B2/B3，+3V3=A9/A10/B8，+5V=A19/A32（每版 CEM 都是 RSVD）', 10), + (45, 740, u'SCL=B5 / SDA=B6 / INT#=B11（五槽 wire-OR，唯一一颗上拉在 A3）/ EFUSE_EN=A11 / VDAC=A16 / D±=B14·B15（两侧 B13·B16 天然夹地）', 10), + (45, 722, u'⚠ B10（+3.3Vaux）必须悬空：真显卡误插进本槽时，底板若在这针上给电会直接打穿它的 aux 域。A5~A8、B9 同样悬空，每槽共 6 针', 10), + (45, 704, u'⚠ B3 是 +12V 不是 RSVD、B12 是 CLKREQ# 不是 RSVD（方案文档旧描述有误，以 b4_edge.py 的 PIN_NET 为准）；B12/B17/B30 与全部 lane 针接地', 10), + (45, 686, u'✅ T8 已结（2026-09-08 换料）：J34~J38 = SOFNG PCIE-64P11L（C19188869），PC 标准 x4 64PIN。⛔ 贴片立式，保持力只靠焊盘 —— 刀片要另加固定件', 10), + (45, 250, u'⚠ PRSNT 是全页唯一**不镜像**刀片的地方：底板 A1 = GND、B31 = PRSNTn#（上拉与读取都在 A3）。', 11), + (45, 232, u' 刀片上 A1↔B31 是一段悬空短接线，插上才把 B31 拉到地 —— 底板若也把两针并成一个网，回路里没有对地通路，ESP32 永远读「未插入」', 10), + (45, 214, u'每槽 64 针 = 20 地 + 6 悬空 + 18 有名信号。地针走「梳齿 + 母线 + 每段一面地旗」；A 排母线（cx−160）从 A4 连到 A31 不用断，', 10), + (45, 196, u' B 排母线（cx+160）只在 B8 那一行断开，让 +3V3 横穿到母线以东挂旗（抄 B4-EDGE §17.2）；所有信号止步于 cx±140 ⇒ 交叉点 0', 10), +] + + +def main(slots=None, wvs=None, texts=None, page=PAGE, name=NAME): + slots = SLOT_XY if slots is None else slots + wvs = {} if wvs is None else wvs + texts = TEXTS if texts is None else texts + push = '--push' in sys.argv + place = placement(slots, wvs) + exp = expect(slots, wvs) + nc = nc_table(slots) + s = build(slots, wvs, texts, page, name) + s.assert_grid() + pins = dict((d, dict((k, tuple(v)) for k, v in want.items())) + for d, want in exp.items()) + errs = s.netcheck(pins, nc, allow_split(slots, wvs)) + pin_errs, npin = check_pin_nets(s, slots, wvs) + errs += pin_errs + text_clash(s, exp) + flag_clash(s) + port_extent(s, slots, wvs) + nnc = sum(len(v) for v in nc.values()) + print(u'%s：%d 个插槽 × 64 针 + %d 个 D± 退路座 × 6 针 = 逐脚对账 %d 根' + % (name, len(slots), len(wvs), npin)) + print(u' 每槽 地 %d / 悬空 %d / 有名信号 %d；本页悬空针合计 %d' + % (len(AGND) + len(BGND), len(NCPINS), + 64 - len(AGND) - len(BGND) - len(NCPINS), nnc)) + s.report(len(place), errs) + if page is None: + print(u'⚠ 本页还没有 uuid（等主代理建页后填 PAGE），--push 不可用') + return + with io.open(os.path.join(HERE, '%s-nc.json' % name.lower()), 'w', + encoding='utf-8') as f: + f.write(json.dumps(nc, ensure_ascii=False, indent=1)) + if not push: + return + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets --nc .claude/r2/%s-nc.json' % name.lower()) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a5b-slots-nc.json b/.claude/r2/a5b-slots-nc.json new file mode 100644 index 0000000..7e86850 --- /dev/null +++ b/.claude/r2/a5b-slots-nc.json @@ -0,0 +1,18 @@ +{ + "J37": [ + "5", + "6", + "7", + "8", + "42", + "41" + ], + "J38": [ + "5", + "6", + "7", + "8", + "42", + "41" + ] +} \ No newline at end of file diff --git a/.claude/r2/a5b_slots.py b/.claude/r2/a5b_slots.py new file mode 100644 index 0000000..770cfcf --- /dev/null +++ b/.claude/r2/a5b_slots.py @@ -0,0 +1,81 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A5B-SLOTS** 页：PCI-E x4 插槽阵（槽 4~5）。 + +⛔ **2026-09-09 用户拍板：底板上的 5 个 D± 退路座 `J39~J43` 全部去掉。** + 它们是 D12「金手指那条 D± 万一不稳，割断改飞 5 根短线」的底板侧接口。 + ⇒ 现在底板侧**没有退路**：`USBn_DP/DM` 从 `U32` 直接到插槽针，一条路走到黑。 + ⚠ 连带影响两条： + ① 刀片上的 `J2`（B4-EDGE 那个同款 4P 座）失去了对端，除非另配线束，否则也用不上； + ② 「最远一路 D± ~70 mm」当初拍板接受时，理由之一就是「退路座本来就是为这一条留的」 + （方案 §28.10）—— 这条理由现在没了，D± 只能一次做对。 + + /c/Python314/python .claude/r2/a5b_slots.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a5b_slots.py --push # 清页 + 重画（只有主代理能跑） + +⚠️ **这一页在契约 §6 的四页表里没有，是 A5 算完版面之后新开的。** +一页排不下 5 个槽（每槽净宽 355、槽距 365，一行 3 槽已经吃掉 1085/1125）， +两行又会压进标题栏 —— 完整的账在 `a5_slots.py` 的表头 §版面。 +所有画法（针位、母线、端口方向、逐脚对账）都在 `a5_slots.py` 里，本文件只给坐标和文字。 + +**页 uuid 还没有**：`PAGE = None`，等主代理在 BASE 原理图（`372e2399adb7a6db`）里 +建出这一页、把 uuid 写进 `.claude/r2/r2-uuids.json` 的 `boards.BASE.pages` 之后填进来。 + +## 退路座去掉之后本页变简单了 + +原来 `USB4_DP/DM` / `USB5_DP/DM` 在本页同时出现在「槽」和「退路座」两处， +天然是两块铜、要靠 `ALLOW_SPLIT` + `check_pin_nets` 逐脚对账放行； +`USB1~3_DP/DM` 更是只有退路座一处。**现在这几条全部消失** —— +本页只剩槽 4/5，每个网在页内要么只有一处、要么本来就连通。 +""" +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +import a5_slots as A5 # noqa: E402 + +PAGE = 'e493f8bce3a51aae' +NAME = 'A5B-SLOTS' + +# 槽 4/5 仍放 cy=580（退路座删了之后 y<385 整条带子空着，不动版面免得又踩叠字） +SLOT_XY = {4: (200, 580), 5: (565, 580)} +# 退路座一字排开，间距 210：标签往左伸 ≈162，右边是座子本体 +25 ⇒ 相邻之间还剩 23 +WV_XY = {} # 退路座已删（2026-09-09 用户拍板） + +TEXTS = [ + (45, 800, u'【A5B-SLOTS】5 个 PCI-E x4 插槽之 槽 4~5（槽 1~3 在 A5-SLOTS）', 13), + (790, 770, u'针位与画法完全同 A5-SLOTS：', 11), + (790, 752, u' A 排地母线 cx−160、B 排 cx+160，', 10), + (790, 734, u' B 排在 B8 那一行断开让 +3V3 东出。', 10), + (790, 710, u'⚠ 底板 A1 = GND、B31 = PRSNTn#：', 11), + (790, 692, u' 刀片上 A1↔B31 才是短接线，', 10), + (790, 674, u' 插上刀片才把 B31 拉到地。', 10), + (790, 656, u' 两针都叫 PRSNTn# = 检测永远失效。', 10), + (790, 632, u'⚠ B10（+3.3Vaux）必须悬空，', 11), + (790, 614, u' 连同 A5~A8 / B9 每槽 6 针悬空。', 10), + (790, 590, u'✅ T8 已结（换料）：J34~J38 =', 11), + (790, 572, u' SOFNG PCIE-64P11L（C19188869），', 10), + (790, 554, u' PC 标准 x4 64PIN。', 10), + (790, 536, u' ⛔ 贴片立式，保持力只靠焊盘 ——', 10), + (790, 518, u' 刀片必须另加固定件。', 10), + (790, 494, u'⛔ 2026-09-09 用户拍板：5 个 D±', 11), + (790, 476, u' 退路座 J39~J43 全部删除。', 10), + (790, 458, u' 底板侧不再有 D± 退路 ——', 10), + (790, 434, u' USBn_DP/DM 从 U32 直达槽针，', 10), + (790, 416, u' 一条路走到黑；刀片上的 J2 也', 10), + (790, 398, u' 随之失去对端。', 10), + # ⚠ 这三行历史上踩过一次叠字：原来是 (45, 196) 的一整行长文字，正好从退路座的 + # GND 旗标签中间穿过去，`verify_sch` 六项全过、只有放大截图看得出来 + # （同 A2-AUX 的两处叠字，方案 §19.2）。退路座虽然删了，这三行仍留在右侧空白区。 + (790, 374, u'⚠ 本页不在契约 §6 的四页表里：一页', 10), + (790, 356, u' 排不下 5 个槽（355×5=1815 ≫ 1125），', 10), + (790, 338, u' 账见 a5_slots.py 表头。', 10), +] + + +def main(): + A5.main(slots=SLOT_XY, wvs=WV_XY, texts=TEXTS, page=PAGE, name=NAME) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/a6_fan.py b/.claude/r2/a6_fan.py new file mode 100644 index 0000000..bcb4efd --- /dev/null +++ b/.claude/r2/a6_fan.py @@ -0,0 +1,553 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 **A6-FAN** 页：风墙驱动（高边总开关 + 反相 PWM + 两路测速）+ 两路 NTC 测温。 + + /c/Python314/python .claude/r2/a6_fan.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/a6_fan.py --push # 清页 + 重画（幂等） + +## 内容从哪来 + +| 块 | 来源 | 处理 | +|---|---|---| +| 风扇全部（`Q6~Q10` `D2` `DZ3` `J26/J27` `C738` `R733/R734/R746~R757`）| R1 `P6-FAN-EDL`（`_p6_live.json`）| **拓扑一字不改**，版图重排 | +| NTC（`RT601` `RT602` + 分压电阻 + 滤波电容）| R1 `P3-CONTROL`（`_p3_live.json`）| 拓扑照搬，**位号改号** | + +⛔ **EDL 部分不在本页**（已随方案挪到刀片 `B3-PHONE`）。 +实测 `_p6_live.json` 里 **一件 EDL 器件都没有** —— 24 个元件全是风扇块 +（R1 早在 2026-09-06 就把第三片 74HC595 / `U33` 整条链挪到载板 `C6-KEYS` 了， +页面 `texts` 里还留着「已搬走」那两行说明）。所以没有「逐件挑掉」这一步， +`REF_KEEP` 就是 dump 里的全部 24 件，脚本用它做逐脚拓扑对账（见下）。 + +## 位号改号（NTC 那一块） + +R1 P3 的 NTC 上臂用的是 `R601~R650` 那一档（`R618` / `R619`，10k `C25744`）， +而契约 §2 把 `R601~R650` 整段划给了 **A3-CTRL**。⇒ 本页改用 A6 的新号段 `R660~R699`： + +| R1 P3 | 本页 | 是什么 | +|---|---|---| +| `R618` | **`R660`** | NTC1 分压上臂 10k → `+3V3` | +| `R619` | **`R661`** | NTC2 分压上臂 10k → `+3V3` | +| `C613` | **`C736`** | NTC1 节点滤波 100nF | +| `C614` | **`C739`** | NTC2 节点滤波 100nF | +| `RT601` / `RT602` | 原名 | 契约 §2 明确点名给 A6 | + +⚠ 契约 §2 只给了 A6 电阻新号段，**没给电容号段**（`C738` 是单点分配）。 +`C736` / `C739` 是全表唯一两个没人认领的编号（A2 到 `C735`、A4 从 `C737`/`C740` 起、 +A5 `C760~C790`），选它们既不撞车也不用改契约。**已在汇报里单列。** + +## 版图为什么不是 1:1 平移 + +`schcheck.Sheet.place()` 的 `create(..., mirror=false)` 写死不支持镜像， +而 R1 P6 上 **`Q7` / `Q9` / `Q10` 三颗 MOS 是 `mirror=True`** 放的（栅极在右）。 +⇒ 这三颗改用 **`rot=180` 不镜像**，栅极同样在右，但漏源上下互换： + + AO3400A/AO3401A rot 0 : G(cx-20,cy) D(cx+10,cy+20) S(cx+10,cy-20) + rot180: G(cx+20,cy) D(cx-10,cy-20) S(cx-10,cy+20) + +- `Q7`（P-MOS 高边）rot180 后 **S 在上 / D 在下**，正好还是「源极接 +12V 母线、 + 漏极向下出 `FAN_12V_SW`」，只是栅极网络要挪到它右边 ⇒ `DZ3` / `R746` / `R747` + 从 x=150/240 挪到 x=380/470，`Q7` 留在 x=300。 +- `Q9` / `Q10`（TACH 接收 N-MOS）rot180 后 **D 在下 / S 在上**，所以这两颗的 + 地旗在上（`Ground rot=180`）、`+3V3` 上拉旗在下（`Power rot=180`）。 + 看着别扭但电气一致；换成 rot0 会把栅极甩到左边，而原始 TACH 是从右边的风扇座 + 过来的，绕线要横穿 MOS 本体，更糟。**这是本页唯一一处违反「电源在上、地在下」的地方。** + +改完靠 `topo_check()` 兜底：把 R1 dump 和本页各自**按几何反推一遍网表**， +再逐个 `位号.脚号` 比对分组，**完全不看坐标、不看网络名**。 +只要拓扑动了一根线就会当场终止。 + +## 三条硬约束怎么落实的 + +1. **`FAN_EN` 复位态关电**（契约 §3 第 2 条）：`FAN_EN` → `R748` 1k → `Q8` 栅极， + `R749` 100k 下拉；`Q8` 关 ⇒ `R746` 100k 把 `Q7` 栅极拉回源极 ⇒ P-MOS 截止。 + ESP32 高阻 / 复位期间风扇不转。**拓扑照抄 R1，一点没简化。** +2. **`DZ3` 钳位**：`AO3401A` 的 `Vgs` 绝对最大 ±12V（`eda-parts` `C15127` 的 role）， + 13.2V 母线直接把栅极拉到地就超了。`DZ3`(BZT52C8V2) **K 接源极 / A 接栅极**。 +3. **`D2`(SS34)**：**K 接 `FAN_12V_SW` / A 接 `GND`**，做负向钳位 + （高边拓扑下它不再是低边续流二极管，见 `FAN_CIRCUIT.md`）。 + +⚠ 2 和 3 都是极性件，本项目已经在极性件上栽过三次（C60 电解、U5 镜像、C801）。 +所以 `EXPECT` 里 **`D2` / `DZ3` 写死脚号→绝对坐标**（`'1': K 在上, '2': A 在下`）， +不是 `two_pin()` 那种只比坐标集合的宽松判据 —— 翻 180° 会当场被 `place()` 判死。 +`eda-parts` 的 role 说 `DZ3` 要 `create(rot=90)`、`D2` 要 `setState_Rotation(270)`， +两句话本身就打架；**本脚本一律传 270 并按脚号断言**，`place()` 的翻转重试循环 +会把真实方向试出来，对不上就终止。方向表一张都别信（skill §6b/§6c）。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, _on, call, PARTS # noqa: E402 + +PAGE, NAME = '68c9ffaa578572d3', 'A6-FAN' +R2_PROJECT = '05a65c22f14846b8b95360ef8d3c1e2e' + +REF_P6 = os.path.join(HERE, '_p6_live.json') # R1 P6-FAN-EDL（实测只剩风扇） +REF_P3 = os.path.join(HERE, '_p3_live.json') # R1 P3-CONTROL（只取 NTC 六件） + +# 器件键（`.claude/eda-parts.json`） +K_NMOS = 'C20917' # AO3400A +K_PMOS = 'C15127' # AO3401A（Vgs ±12V ⇒ 必配 DZ3） +K_SS34 = 'C8678' # SS34 肖特基 +K_ZEN = 'C2891776' # BZT52C8V2 8.2V +K_FAN4 = 'C2847671' # 2510-4A 四线风扇座 +K_22U = 'C12891' # 22uF/25V 1206（引脚 ±15，不是 ±20） +K_100N = 'C1525' # 100nF 0402 +K_NTC = 'C13564' # NCP18XH103F03RB 10k B=3380K +K_1K = 'C11702' +K_10K = 'C25744' +K_15K = 'C25756' # TACH 栅极串阻（10k 会让高电平不够） +K_100K = 'C25741' + +DY = -240 # 排风通道 = 进风通道整体下移 +NTC_DX = 260 # NTC 第二路 = 第一路整体右移 + +# ── R1 → 本页的位号改号（NTC 那一块，见文档串）──────────────────────── +NTC_REMAP = {'R618': 'R660', 'R619': 'R661', 'C613': 'C736', 'C614': 'C739'} +NTC_KEEP = set(['RT601', 'RT602', 'R660', 'R661', 'C736', 'C739']) + +# ── 拓扑对账时要把 R1 侧的 1/2 脚对调的非极性件 ────────────────────── +# R1 上 R753/R757 的上拉在漏极**上方**（p2 接 +3V3）；本页 Q9/Q10 转了 180°， +# 漏极在下，上拉挪到漏极**下方**（p1 接 +3V3）。电阻无极性，电气完全一致， +# 但按「位号.脚号」比对会不一致 ⇒ 在参照侧对调后再比。 +REF_SWAP = set(['R753', 'R757']) + + +# ══════════════════════════════════════════════════════════════════════ +# 引脚期望（skill §6b/§6c：方向表不可信，一律按脚号断言绝对坐标） +# ══════════════════════════════════════════════════════════════════════ +def rc(x, y, rot, half=20): + u"""两脚无极性件（R / C / NTC）。实测：rot0 → 1 在左；rot90 → 1 在下；rot270 → 1 在上。""" + if rot == 0: + return {'1': (x - half, y), '2': (x + half, y)} + if rot == 90: + return {'1': (x, y - half), '2': (x, y + half)} + if rot == 270: + return {'1': (x, y + half), '2': (x, y - half)} + raise AssertionError(u'rc 只支持 0/90/270') + + +def mos(x, y, rot): + u"""SOT-23 MOS：脚号 1=G 2=S 3=D（AO3400A 与 AO3401A 同一套偏移，实测）。""" + if rot == 0: + return {'1': (x - 20, y), '3': (x + 10, y + 20), '2': (x + 10, y - 20)} + if rot == 180: + return {'1': (x + 20, y), '3': (x - 10, y - 20), '2': (x - 10, y + 20)} + raise AssertionError(u'mos 只支持 0/180') + + +def diode_k_up(x, y): + u"""极性件：pin1 = K 在上，pin2 = A 在下。**写死脚号，不用坐标集合。**""" + return {'1': (x, y + 20), '2': (x, y - 20)} + + +def fan4(x, y): + u"""2510-4A：全部在左侧，1=GND 2=FAN_12V_SW 3=TACH 4=PWM（eda-parts role）。""" + return {'1': (x - 20, y + 15), '2': (x - 20, y + 5), + '3': (x - 20, y - 5), '4': (x - 20, y - 15)} + + +# ══════════════════════════════════════════════════════════════════════ +# 放置表 +# ══════════════════════════════════════════════════════════════════════ +def placement(): + p = [ + # ── A 高边总开关：FAN_EN → Q8 → Q7 → FAN_12V_SW ──────────────── + ['R748', K_1K, 200, 560, 0], # FAN_EN 栅极串阻 + ['R749', K_100K, 230, 510, 90], # Q8 栅极下拉（复位默认关电） + ['Q8', K_NMOS, 280, 560, 0], + ['R747', K_1K, 380, 660, 90], # Q8 漏极 → Q7 栅极 + ['DZ3', K_ZEN, 380, 750, 270], # K 接源极 / A 接栅极 + ['R746', K_100K, 470, 750, 90], # Q7 栅极拉回源极 + ['Q7', K_PMOS, 300, 730, 180], # rot180：G 在右 / S 在上 / D 在下 + # ── C FAN_12V_SW 上的钳位与储能 ──────────────────────────────── + ['C738', K_22U, 190, 650, 270], + ['D2', K_SS34, 250, 650, 270], # K 接 FAN_12V_SW / A 接 GND + # ── B PWM 反相器：FAN_PWM → Q6 → FAN_PWM_L（开漏）────────────── + ['R733', K_1K, 200, 370, 0], + ['R734', K_100K, 250, 310, 270], + ['Q6', K_NMOS, 320, 370, 0], + # ── D 进风测速 + J26 ─────────────────────────────────────────── + ['Q9', K_NMOS, 750, 720, 180], + ['R750', K_10K, 960, 750, 90], # TACH 上拉到 FAN_12V_SW + ['R751', K_15K, 810, 720, 0], # 栅极串阻（10k 高电平不够） + ['R752', K_10K, 790, 680, 90], # 栅极对地 + ['R753', K_10K, 740, 650, 90], # 漏极上拉 +3V3 + ['J26', K_FAN4, 1085, 725, 0], + # ── NTC1 / NTC2（从 R1 P3-CONTROL 搬来）──────────────────────── + ['RT601', K_NTC, 600, 270, 270], + ['R660', K_10K, 600, 330, 270], + # ⚠ 从 x=660 挪到 700：RT601 的型号文字「NCP18XH103F03RB」画在符号右边、约 65 单位宽， + # 原来 60 的间距下正好压住 C736 的位号/值（渲染成 …F03RB0nF），和 A2-AUX 的 + # C733「100uF0」是同一类事故 —— 六项几何验证与 flag_clash 都够不着，只有放大截图看得出来。 + ['C736', K_100N, 700, 270, 270], + ] + # 排风通道 = 进风通道整体下移 DY，位号 +4 + for d, k, x, y, r in [it for it in p if it[0] in + ('Q9', 'R750', 'R751', 'R752', 'R753', 'J26')]: + out = {'Q9': 'Q10', 'R750': 'R754', 'R751': 'R755', + 'R752': 'R756', 'R753': 'R757', 'J26': 'J27'}[d] + p.append([out, k, x, y + DY, r]) + # NTC 第二路 = 第一路整体右移 + for d, k, x, y, r in [it for it in p if it[0] in ('RT601', 'R660', 'C736')]: + out = {'RT601': 'RT602', 'R660': 'R661', 'C736': 'C739'}[d] + p.append([out, k, x + NTC_DX, y, r]) + return p + + +def expect(): + e = {} + for d, _k, x, y, r in placement(): + if d in ('Q6', 'Q7', 'Q8', 'Q9', 'Q10'): + e[d] = mos(x, y, r) + elif d in ('D2', 'DZ3'): + e[d] = diode_k_up(x, y) # 极性件：写死脚号 + elif d in ('J26', 'J27'): + e[d] = fan4(x, y) + elif d == 'C738': + e[d] = rc(x, y, r, 15) # 1206 是 ±15（skill §8d） + else: + e[d] = rc(x, y, r) + return e + + +# ══════════════════════════════════════════════════════════════════════ +# 页面文字 +# ══════════════════════════════════════════════════════════════════════ +TEXTS = [ + (45, 245, u'【A6-FAN】风墙：高边总开关 + 反相 PWM + 两路独立测速 + 两路 NTC', 11), + (45, 225, u'FAN_EN 复位/高阻 → Q8 截止 → R746(100k) 把 Q7 栅极拉回源极 → 风扇断电', 10), + (45, 207, u'（契约 §3 第 2 条：复位态必须关电）R749 100k 保证 Q8 栅极不浮空', 10), + (45, 189, u'DZ3 BZT52C8V2：K 接 Q7 源极、A 接栅极，把 Vgs 钳在 -8.2V', 10), + (45, 171, u'AO3401A 的 Vgs 绝对最大 ±12V，13.2V 母线直接拉地就超了', 10), + (45, 153, u'Q6 开漏反相器：栅极高 = 风扇 PWM 线被拉低，固件 D_gpio = 1 - D_fan', 10), + (45, 135, u'0% PWM 风扇仍转约 3300RPM，要停转只能撤 FAN_EN，不能靠占空比', 10), + (45, 117, u'D2 SS34：K 接 FAN_12V_SW、A 接 GND，负向钳位（不是低边续流）', 10), + (45, 99, u'测速：10k 上拉到 FAN_12V_SW，15k/10k 分压 → 栅极 3.43V@12V；', 10), + (45, 81, u'漏极 10k 上拉 +3V3，反相输出。ESP32 只看到 0/3.3V，不接触 12V', 10), + (45, 63, u'首板只装一只风扇（方案 §0.2 A3）：空着那一路 TACH 悬空，被 10k', 10), + (45, 45, u'拉到 12V → 接收 MOS 常通 → GPIO 恒低无跳变；关电时则恒高。', 10), + (45, 27, u'两种都是 0 脉冲，固件必须按配置屏蔽未装的那一路，否则误报停转', 10), + (410, 665, u'NTC：RT601/RT602 10k B=3380K，上臂 R660/R661 10k 接 +3V3', 10), + (410, 647, u'25℃ 分压 1.65V；NTC1/NTC2 必须进 ESP32 的 ADC1（IO1~IO10）', 10), + (410, 629, u'摆位：J26/J27 在底板 y>114.5，刀片投影外，可放高件（§6.6）', 10), + (410, 611, u'⚠ 四针针序与旧的 3 针风扇座不同，装配前先对丝印', 10), + (835, 615, u'J26 = 进风，J27 = 排风（2510-4A 四线直针）', 10), + (835, 595, u'1=GND(黑) 2=FAN_12V_SW(红) 3=TACH(黄) 4=PWM(棕)', 10), +] + +# 每一列文字的右边界（`assert_grid` 只管标题栏那条，这里再管一次不许压到电路） +TEXT_CAP = [(200, 540), (800, 790), (10000, 1145)] + + +# ══════════════════════════════════════════════════════════════════════ +# 连线 +# ══════════════════════════════════════════════════════════════════════ +def build(): + s = Sheet(PAGE, NAME) + w, g, p, pt, tx = s.w, s.gnd, s.pwr, s.port, s.txt + + # ── A 高边总开关 ────────────────────────────────────────────────── + w('FAN_EN', (140, 560), (180, 560)) + pt('IN', 'FAN_EN', 140, 560, 0) # IN + rot0 ⇒ 标签朝左 + w('#Q8_G', (220, 560), (260, 560)) # R748.2 → Q8.G + w('#Q8_G', (230, 530), (230, 560)) # R749.2 + w('GND', (230, 460), (230, 490)) + g(230, 460, 0) + w('GND', (290, 500), (290, 540)) # Q8.S + g(290, 500, 0) + w('#Q8_D', (290, 580), (380, 580)) + w('#Q8_D', (380, 580), (380, 640)) # → R747.1 + w('#Q7_G', (380, 680), (380, 730)) # R747.2 → 栅极母线 + w('#Q7_G', (320, 730), (470, 730)) # Q7.G / DZ3.A / R746.1 + w('+12V', (290, 750), (290, 790)) # Q7.S + w('+12V', (290, 790), (545, 790)) + w('+12V', (380, 770), (380, 790)) # DZ3.K + w('+12V', (470, 770), (470, 790)) # R746.2 + p('+12V', 545, 790, 0) + + # ── C FAN_12V_SW 母线 + 钳位 / 储能 ─────────────────────────────── + w('FAN_12V_SW', (290, 690), (290, 710)) # Q7.D + w('FAN_12V_SW', (140, 690), (290, 690)) + p('FAN_12V_SW', 140, 690, 0) + w('FAN_12V_SW', (190, 665), (190, 690)) # C738.1 + w('GND', (190, 600), (190, 635)) + g(190, 600, 0) + w('FAN_12V_SW', (250, 670), (250, 690)) # D2.1 = K + w('GND', (250, 600), (250, 630)) # D2.2 = A + g(250, 600, 0) + + # ── B PWM 反相器 ────────────────────────────────────────────────── + w('FAN_PWM', (140, 370), (180, 370)) + pt('IN', 'FAN_PWM', 140, 370, 0) + w('#Q6_G', (220, 370), (300, 370)) # R733.2 → Q6.G + w('#Q6_G', (250, 330), (250, 370)) # R734.1 + w('GND', (250, 280), (250, 290)) + g(250, 280, 0) + w('GND', (330, 350), (370, 350)) # Q6.S + w('GND', (370, 320), (370, 350)) + g(370, 320, 0) + w('FAN_PWM_L', (330, 390), (330, 430)) # Q6.D（开漏，靠风扇内部上拉） + w('FAN_PWM_L', (330, 430), (400, 430)) + pt('BI', 'FAN_PWM_L', 400, 430, 0) + + # ── D/E 两路测速接收 + 风扇座 ───────────────────────────────────── + for dy, raw, out in ((0, 'FAN_IN_TACH_RAW', 'FAN_TACH_IN'), + (DY, 'FAN_OUT_TACH_RAW', 'FAN_TACH_OUT')): + gate = '#Q9_G' if dy == 0 else '#Q10_G' + w('GND', (1050, 740 + dy), (1065, 740 + dy)) # J.1 + w('GND', (1050, 740 + dy), (1050, 770 + dy)) + g(1050, 770 + dy, 180) + w('FAN_12V_SW', (1030, 730 + dy), (1065, 730 + dy)) # J.2 + w('FAN_12V_SW', (1030, 730 + dy), (1030, 790 + dy)) + p('FAN_12V_SW', 1030, 790 + dy, 0) + w('FAN_PWM_L', (1020, 710 + dy), (1065, 710 + dy)) # J.4 + w('FAN_PWM_L', (1020, 670 + dy), (1020, 710 + dy)) + pt('BI', 'FAN_PWM_L', 1020, 670 + dy, 180) + w(raw, (830, 720 + dy), (1065, 720 + dy)) # J.3 → R751.2 + w(raw, (960, 720 + dy), (960, 730 + dy)) # R750.1 + w(raw, (990, 650 + dy), (990, 720 + dy)) + pt('BI', raw, 990, 650 + dy, 180) + w('FAN_12V_SW', (960, 770 + dy), (960, 790 + dy)) # R750.2 + p('FAN_12V_SW', 960, 790 + dy, 0) + w(gate, (770, 720 + dy), (790, 720 + dy)) # Q9.G ← R751.1 + w(gate, (790, 700 + dy), (790, 720 + dy)) # R752.2 + w('GND', (790, 630 + dy), (790, 660 + dy)) # R752.1 + g(790, 630 + dy, 0) + w('GND', (740, 740 + dy), (740, 770 + dy)) # Q9.S（rot180 ⇒ 在上） + g(740, 770 + dy, 180) + w(out, (740, 670 + dy), (740, 700 + dy)) # Q9.D ← → R753.2 + w(out, (680, 690 + dy), (740, 690 + dy)) + pt('OUT', out, 680, 690 + dy, 180) + w('+3V3', (740, 610 + dy), (740, 630 + dy)) # R753.1 + p('+3V3', 740, 610 + dy, 180) + + # ── NTC 两路（R1 P3-CONTROL 搬来，上臂改号 R660/R661）───────────── + for dx, net in ((0, 'NTC1'), (NTC_DX, 'NTC2')): + w('+3V3', (600 + dx, 350), (600 + dx, 360)) # R660.1 + p('+3V3', 600 + dx, 360, 0) + w(net, (600 + dx, 290), (600 + dx, 310)) # RT601.1 ← → R660.2 + w(net, (600 + dx, 300), (760 + dx, 300)) + w(net, (700 + dx, 290), (700 + dx, 300)) # C736.1 + pt('OUT', net, 760 + dx, 300, 0) + w('GND', (600 + dx, 220), (600 + dx, 250)) # RT601.2 + g(600 + dx, 220, 0) + w('GND', (700 + dx, 220), (700 + dx, 250)) # C736.2 + g(700 + dx, 220, 0) + + for t in TEXTS: + tx(t[0], t[1], t[2], t[3]) + return s + + +# ══════════════════════════════════════════════════════════════════════ +# 本地自检：几何 + 与 R1 的逐脚拓扑对账 +# ══════════════════════════════════════════════════════════════════════ +def _uf(segs): + n = len(segs) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2 = segs[i] + b1, b2 = segs[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + return find + + +def partition(segs, named, pins, where, strict=True): + u"""纯几何反推网表：返回「同一网络的 `位号.脚号` 集合」的集合。 + + 同名旗/端口所在的组按名字合并（`GND` / `+12V` 这类天然分块的网络）； + 无名组各自成网。**不看坐标、不看我自己声明的网络名** —— 这样才能用来 + 和 R1 的 dump 对账。 + """ + find = _uf(segs) + gname, gpins = defaultdict(set), defaultdict(set) + for name, xy in named: + hit = [i for i in range(len(segs)) if _on(xy, segs[i][0], segs[i][1])] + if not hit: + assert not strict, u'%s：旗/端口 %s @%s 不在任何导线上' % (where, name, xy) + continue + gname[find(hit[0])].add(name) + for d, pd in pins.items(): + for num, xy in pd.items(): + hit = [i for i in range(len(segs)) if _on(tuple(xy), segs[i][0], segs[i][1])] + if not hit: + assert not strict, u'%s：悬空引脚 %s.%s @%s' % (where, d, num, xy) + continue + gpins[find(hit[0])].add('%s.%s' % (d, num)) + merged = defaultdict(set) + for r, ps in gpins.items(): + names = sorted(gname.get(r, set())) + assert len(names) <= 1, u'%s：一个组挂了多个名字 %s' % (where, names) + merged[names[0] if names else '#%d' % r] |= ps + return frozenset(frozenset(v) for v in merged.values()) + + +def restrict(part, keep, remap=None, swap=()): + u"""只留下 keep 里的位号；顺便做位号改名与「非极性件 1/2 脚对调」。""" + flip = {'1': '2', '2': '1'} + out = set() + for grp in part: + cur = set() + for it in grp: + d, num = it.split('.') + if d in swap: + num = flip[num] + d = (remap or {}).get(d, d) + if d in keep: + cur.add('%s.%s' % (d, num)) + if cur: + out.add(frozenset(cur)) + return frozenset(out) + + +def load_ref(path): + src = json.load(io.open(path, encoding='utf-8')) + r = lambda v: int(round(v)) # noqa: E731 + pts = src['wires'] + segs = [((r(pts[i][0]), r(pts[i][1])), (r(pts[i + 1][0]), r(pts[i + 1][1]))) + for i in range(0, len(pts), 2)] + segs = [t for t in segs if t[0] != t[1]] + named = ([(f[1], (r(f[2]), r(f[3]))) for f in src['flags']] + + [(q[1], (r(q[2]), r(q[3]))) for q in src['ports']]) + pins = dict((q[0], dict((str(z[0]), (r(z[2]), r(z[3]))) for z in q[9])) + for q in src['parts']) + return segs, named, pins, set(pins) + + +def topo_check(s, exp): + u"""把本页与 R1 两页的网表分组逐个比对。差一根线就报出来。""" + errs = [] + mine = partition([(a, b) for a, b, _n in s.W], + [(it[1], (it[2], it[3])) for it in s.F + s.PT], + exp, u'本页') + + segs, named, pins, allref = load_ref(REF_P6) + ref6 = partition(segs, named, pins, u'R1 P6', strict=False) + edl = sorted(d for d in allref if d.startswith('U4') or d.startswith('J6')) + assert not edl, u'_p6_live.json 里居然有 EDL 器件 %s，要逐件挑掉' % (edl,) + a = restrict(ref6, allref, swap=REF_SWAP) + b = restrict(mine, allref) + for grp in sorted(a - b, key=lambda z: sorted(z)): + errs.append(u'R1 P6 有、本页没有的网络分组: %s' % (sorted(grp),)) + for grp in sorted(b - a, key=lambda z: sorted(z)): + errs.append(u'本页多出来的网络分组: %s' % (sorted(grp),)) + + segs, named, pins, _all3 = load_ref(REF_P3) + ref3 = partition(segs, named, pins, u'R1 P3', strict=False) + a = restrict(ref3, NTC_KEEP, remap=NTC_REMAP) + b = restrict(mine, NTC_KEEP) + for grp in sorted(a - b, key=lambda z: sorted(z)): + errs.append(u'R1 P3 的 NTC 块有、本页没有的分组: %s' % (sorted(grp),)) + for grp in sorted(b - a, key=lambda z: sorted(z)): + errs.append(u'本页 NTC 块多出来的分组: %s' % (sorted(grp),)) + return errs + + +def geom_check(s, exp): + u"""几件 `netcheck` 管不到、但本项目真踩过的事故。""" + errs = [] + # skill §8a：旗/端口的引脚不许和元件引脚同坐标（零长度导线，重画就断） + pinxy = {} + for d, pd in exp.items(): + for num, xy in pd.items(): + key = tuple(xy) + assert key not in pinxy, u'引脚重叠: %s.%s 与 %s @%s' % (d, num, pinxy[key], key) + pinxy[key] = '%s.%s' % (d, num) + for it in s.F + s.PT: + if (it[2], it[3]) in pinxy: + errs.append(u'旗/端口 %s 压在元件引脚 %s 上（skill §8a）' + % (it[1], pinxy[(it[2], it[3])])) + # 文字右边界（分列各自的上限） + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + right = x + size * (cjk + 0.5 * (len(txt) - cjk)) + cap = next(c for lo, c in TEXT_CAP if x < lo) + if right > cap: + errs.append(u'文字右边界 %.0f 超过本列上限 %d: %s' % (right, cap, txt[:22])) + return errs + + +def text_clash(s, exp): + u"""文字压在导线 / 引脚 / 旗端口上（同 a1_input.py / a2_aux.py）。""" + errs, boxes, pts = [], [], [] + for x, y, txt, size in s.TX: + cjk = sum(1 for ch in txt if ord(ch) > 0x2E7F) + boxes.append((x, y - size * 0.8, x + size * (cjk + 0.5 * (len(txt) - cjk)), + y + size * 0.8, txt)) + for d, ps in exp.items(): + for num, xy in ps.items(): + pts.append((xy[0], xy[1], u'引脚 %s.%s' % (d, num))) + for it in s.F + s.PT: + pts.append((it[2], it[3], u'旗/端口 %s' % it[1])) + for x0, y0, x1, y1, txt in boxes: + for px, py, what in pts: + if x0 <= px <= x1 and y0 <= py <= y1: + errs.append(u'文字压住 %s @(%d,%d): %s' % (what, px, py, txt[:22])) + for a, b, net in s.W: + if a[1] == b[1]: + if y0 <= a[1] <= y1 and min(a[0], b[0]) <= x1 and max(a[0], b[0]) >= x0: + errs.append(u'文字压住导线 %s y=%d: %s' % (net, a[1], txt[:22])) + elif x0 <= a[0] <= x1 and min(a[1], b[1]) <= y1 and max(a[1], b[1]) >= y0: + errs.append(u'文字压住导线 %s x=%d: %s' % (net, a[0], txt[:22])) + return sorted(set(errs)) + + +def flag_clash(s, gx=20, gy=10): + errs, items = [], [(it[1], it[2], it[3]) for it in s.F + s.PT] + for i in range(len(items)): + for j in range(i + 1, len(items)): + (n1, x1, y1), (n2, x2, y2) = items[i], items[j] + if abs(x1 - x2) < gx and abs(y1 - y2) < gy: + errs.append(u'旗/端口 %s @(%d,%d) 与 %s @(%d,%d) 挨太近' + % (n1, x1, y1, n2, x2, y2)) + return sorted(set(errs)) + + +# `ALLOW_SPLIT` 只放行「靠同名旗/端口成网」的电源与三处开漏节点（契约 §7 第 10 条）： +# GND / +3V3 / FAN_12V_SW —— 多面旗，导线上天然分块 +# FAN_PWM_L —— Q6 漏极一处 + 两个风扇座各一处，共 3 个同名端口 +ALLOW_SPLIT = set(['GND', '+3V3', 'FAN_12V_SW', 'FAN_PWM_L']) +NC = {} # 本页没有悬空不接的引脚 + + +def main(): + push = '--push' in sys.argv + s = build() + exp = expect() + s.assert_grid() + for d, _k, _x, _y, _r in placement(): + assert _k in PARTS, u'eda-parts.json 里没有器件键 %s（%s）' % (_k, d) + errs = s.netcheck(exp, NC, ALLOW_SPLIT) + errs += geom_check(s, exp) + topo_check(s, exp) + errs += text_clash(s, exp) + flag_clash(s) + print(u'风扇块 %d 件（R1 P6 原样）+ NTC 块 6 件（R1 P3 搬来，上臂改号 R660/R661）' + % (len(placement()) - 6)) + s.report(len(placement()), errs) + if not push: + return + call("await eda.dmt_Project.openProject('%s'); await new Promise(r=>setTimeout(r,2500)); return 1;" + % R2_PROJECT) + s.clear() + s.place(placement(), exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets 和 .claude/xpage.py') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/archive_base2L/_base_bbox.json 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"HUB_RST: R716.1 没布通", "HUB_RST: U32.43 没布通", "NTC2: R661.2 没布通", "NTC2: C739.1 没布通", "FAN_TACH_IN: R753.2 没布通", "INA_ALERT: U13.3 出不来", "NTC1: RT601.1 没布通", "PRSNT4#: U20.11 没布通", "PRSNT4#: R609.2 没布通", "$2N72: R706.2 没布通", "UP_VBUS_DET: R722.1 没布通", "UP_VBUS_DET: R721.2 没布通", "INT#: R604.2 没布通", "INT#: U20.32 没布通", "MUX_RST#: R611.2 没布通", "MUX_RST#: U35.3 没布通", "$6N64: R751.1 没布通", "$6N64: Q9.1 没布通", "$2N74: C733.1 没布通", "PRSNT3#: U20.10 没布通", "PRSNT3#: R608.2 没布通", "PRSNT2#: R607.2 没布通", "EN: U20.3 没布通", "EN: C603.1 没布通", "EN: R601.2 没布通", "FAN_EN: R748.1 没布通", "$6N48: R747.1 没布通", "FAN_PWM: R733.1 没布通", "FAN_OUT_TACH_RAW: R755.2 没布通", "PRSNT1#: J34.63 没布通", "TXD0: U20.37 没布通", "EFUSE_EN5: U20.21 没布通", "EFUSE_EN4: U20.20 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN2: U20.18 没布通", "EFUSE_EN1: U20.17 没布通", "RXD0: U20.36 没布通", "IO0: U20.27 没布通", "$3N173: R614.2 出不来", "$3N192: U7.13 出不来", "XTAL1: U32.61 没布通", "RBIAS: U32.63 没布通", "$3N197: U7.5 没布通", "VDAC2: U6.11 出不来", "VDAC2: U6.12 出不来", "FAN_IN_TACH_RAW: R751.2 没布通", "SCL2: U35.7 没布通", "SCL4: U35.11 没布通", "SDA3: U35.8 没布通", "SCL3: U35.9 没布通"]} \ No newline at end of file diff --git a/.claude/r2/archive_base2L/_base_routes.rejected.json b/.claude/r2/archive_base2L/_base_routes.rejected.json new file mode 100644 index 0000000..88764dd --- /dev/null +++ b/.claude/r2/archive_base2L/_base_routes.rejected.json @@ -0,0 +1 @@ +{"schema": 7, "slot_rot": 0, "usb_slot_ref": {"1": "J34", "2": "J35", "3": "J36", "4": "J37", "5": "J38"}, "segs": [[1, 89.2, 72.5, 89.2, 59.7, 0.5, "+3V3_HUB"], [2, 38.0, 31.26, 38.0, 40.78, 0.8, "+3V3"], [2, 38.0, 51.58, 38.0, 61.1, 0.8, "+3V3"], [2, 38.0, 71.9, 38.0, 81.42, 0.8, "+3V3"], [2, 38.0, 92.22, 38.0, 101.74, 0.8, "+3V3"], [1, 34.079, 1.2, 34.079, 0.7, 0.3, "VIN_FUSED"], [1, 34.079, 0.7, 29.344, 0.7, 0.3, "VIN_FUSED"], [1, 29.344, 0.7, 29.344, 1.649, 0.3, "VIN_FUSED"], [1, 84.2355, 51.153, 83.63550000000001, 51.153, 0.15, "USB5_DP"], [1, 83.63550000000001, 51.153, 79.186, 46.703, 0.15, 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75.75, "VDAC3"], [25.5, 75.75, "VDAC3"], [9.75, 75.25, "VDAC3"], [10.25, 70.5, "VDAC3"], [9.75, 66.5, "VDAC3"], [93.75, 46.25, "XTAL1"], [95.5, 46.25, "XTAL1"], [93.75, 47.75, "XTAL1"], [92.0, 49.5, "XTAL1"], [85.0, 47.5, "RBIAS"], [86.5, 49.5, "RBIAS"], [9.0, 61.5, "$3N192"], [9.25, 62.5, "$3N192"], [87.25, 47.5, "VDD18"], [88.75, 49.5, "VDD18"], [25.5, 39.75, "VDAC5"], [15.25, 53.75, "VDAC5"], [12.5, 56.5, "VDAC5"], [9.5, 59.5, "VDAC5"], [7.0, 68.5, "VDAC5"], [9.0, 68.5, "VDAC5"], [68.75, 14.5, "BLD_REF"], [72.75, 12.25, "BLD_REF"], [96.75, 104.75, "FAN_TACH_IN"], [96.5, 104.0, "FAN_TACH_IN"], [95.0, 89.75, "FAN_TACH_IN"], [92.5, 86.75, "FAN_TACH_IN"], [92.5, 84.75, "FAN_TACH_IN"], [94.75, 83.0, "FAN_TACH_IN"], [90.25, 89.25, "INA_ALERT"], [87.5, 84.75, "INA_ALERT"], [12.75, 62.0, "$3N189"], [14.75, 62.25, "$3N189"], [47.0, 112.0, "VDAC1"], [49.0, 114.25, "VDAC1"], [53.0, 113.5, "VDAC1"], [61.0, 116.75, "VDAC1"], [61.75, 119.0, "VDAC1"], [38.25, 123.75, "VDAC1"], [25.5, 115.25, "VDAC1"], [15.25, 105.0, "VDAC1"], [12.75, 86.25, "VDAC1"], [14.25, 84.75, "VDAC1"], [14.25, 79.25, "VDAC1"], [13.75, 78.25, "VDAC1"], [13.75, 77.75, "VDAC1"], [44.75, 52.0, "VDAC4"], [43.0, 53.75, "VDAC4"], [25.5, 55.25, "VDAC4"], [2.0, 64.75, "VDAC4"], [6.5, 79.0, "VDAC4"], [9.0, 76.75, "VDAC4"], [9.5, 77.75, "VDAC4"], [100.5, 87.25, "NTC1"], [100.0, 86.0, "NTC1"], [102.0, 109.0, "FAN_TACH_OUT"], [101.25, 108.5, "FAN_TACH_OUT"], [25.5, 29.5, "SCL5"], [15.25, 39.75, "SCL5"], [10.5, 44.5, "SCL5"], [9.0, 46.0, "SCL5"], [40.75, 47.5, "INT#"], [40.75, 51.75, "INT#"], [40.75, 52.75, "INT#"], [40.75, 54.75, "INT#"], [40.75, 58.75, "INT#"], [40.25, 62.25, "INT#"], [40.75, 38.25, "INT#"], [39.25, 36.75, "INT#"], [42.75, 64.75, "INT#"], [43.0, 68.5, "INT#"], [40.25, 74.5, "INT#"], [40.25, 81.0, "INT#"], [40.25, 82.5, "INT#"], [43.0, 85.25, "INT#"], [43.0, 88.75, "INT#"], [40.5, 92.5, "INT#"], [40.5, 101.25, "INT#"], [40.5, 103.0, "INT#"], [103.0, 112.25, "$6N74"], [98.25, 113.25, "$6N74"], [96.0, 113.5, "$6N74"], [95.0, 113.5, "$6N74"], [100.75, 119.5, "$6N49"], [97.25, 120.75, "$6N49"], [55.75, 118.5, "SW3V3"], [59.0, 118.5, "SW3V3"], [33.5, 102.0, "SCL1"], [30.0, 100.0, "SCL1"], [25.5, 96.75, "SCL1"], [12.75, 87.75, "SCL1"], [1.25, 70.5, "SCL1"], [4.75, 63.75, "SCL1"], [34.5, 74.0, "SDA2"], [34.0, 67.5, "SDA2"], [32.5, 64.5, "SDA2"], [32.75, 61.0, "SDA2"], [32.75, 60.25, "SDA2"], [32.75, 58.25, "SDA2"], [33.25, 55.75, "SDA2"], [31.75, 54.25, "SDA2"], [30.0, 52.5, "SDA2"], [29.0, 50.75, "SDA2"], [27.25, 41.75, "SDA2"], [27.0, 38.75, "SDA2"], [25.5, 38.25, "SDA2"], [8.5, 52.5, "SDA2"], [32.0, 74.0, "SCL2"], [29.0, 69.75, "SCL2"], [29.25, 66.25, "SCL2"], [27.0, 58.25, "SCL2"], [27.0, 56.25, "SCL2"], [27.0, 54.25, "SCL2"], [25.5, 52.5, "SCL2"], [28.5, 38.75, "SCL2"], [25.5, 36.75, "SCL2"], [15.25, 46.25, "SCL2"], [12.5, 46.5, "SCL2"], [6.75, 52.5, "SCL2"], [35.0, 41.25, "SDA4"], [32.5, 38.75, "SDA4"], [25.5, 35.25, "SDA4"], [13.25, 40.25, "SDA4"], [10.0, 43.0, "SDA4"], [7.25, 45.75, "SDA4"], [4.5, 48.5, "SDA4"], [4.75, 52.5, "SDA4"], [33.0, 41.0, "SCL4"], [31.0, 37.5, "SCL4"], [26.75, 32.25, "SCL4"], [15.25, 37.5, "SCL4"], [12.5, 38.75, "SCL4"], [10.5, 39.25, "SCL4"], [2.5, 47.5, "SCL4"], [3.25, 52.75, "SCL4"], [35.75, 60.25, "SDA3"], [35.75, 58.25, "SDA3"], [35.75, 54.75, "SDA3"], [35.75, 52.75, "SDA3"], [35.75, 51.5, "SDA3"], [35.75, 48.25, "SDA3"], [35.75, 44.25, "SDA3"], [34.75, 38.75, "SDA3"], [28.25, 32.25, "SDA3"], [15.25, 36.0, "SDA3"], [12.5, 37.25, "SDA3"], [10.5, 37.75, "SDA3"], [2.5, 45.25, "SDA3"], [5.25, 58.5, "SDA3"], [72.25, 113.75, "$6N55"], [74.75, 113.25, "$6N55"], [77.25, 6.5, "$1N114"], [75.25, 8.5, "$1N114"], [84.5, 12.75, "$1N127"], [78.75, 9.25, "$1N127"]], "logs": ["+12V: U19.5 出不来", "+5V: U31.3 没布通", "+3V3: U7.15 出不来", "SCL: U7.6 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "VBUS_UP: J23.A4B9 出不来", "$2N70: C733.2 没布通", "SDA: U13.4 出不来", "SDA: U6.7 出不来", "SDA: U6.8 没布通", "SDA: U7.8 没布通", "SDA: R602.2 没布通", "SDA: U35.23 没布通", "HUB_RST: R716.1 没布通", "HUB_RST: U32.43 没布通", "XTAL2: U32.60 出不来", "VBUS_DET: U32.44 没布通", "CFGSEL1: U32.42 没布通", "NONREM0: U32.45 没布通", "CFGSEL0: U32.41 没布通", "$3N176: U6.13 出不来", "NONREM1: U32.40 没布通", "VDAC5: U7.10 出不来", "NTC2: R661.2 没布通", "NTC2: C739.1 没布通", "FAN_TACH_IN: R753.2 没布通", "INA_ALERT: U13.3 出不来", "VDAC2: U6.11 出不来", "VDAC2: U6.12 出不来", "$6N64: R751.1 没布通", "$6N64: R752.2 没布通", "NTC1: RT601.1 没布通", "PRSNT4#: U20.11 没布通", "PRSNT4#: R609.2 没布通", "$2N72: R706.2 没布通", "UP_VBUS_DET: R722.1 没布通", "UP_VBUS_DET: R721.2 没布通", "INT#: R604.2 没布通", "INT#: U20.32 没布通", "MUX_RST#: R611.2 没布通", "MUX_RST#: U35.3 没布通", "FAN_EN: R748.1 没布通", "$6N48: R747.1 没布通", "FAN_OUT_TACH_RAW: R754.1 没布通", "$2N74: C733.1 没布通", "PRSNT3#: U20.10 没布通", "PRSNT3#: R608.2 没布通", "PRSNT2#: R607.2 没布通", "EN: U20.3 没布通", "EN: C603.1 没布通", "EN: R601.2 没布通", "PRSNT1#: R606.2 没布通", "FAN_PWM: R733.1 没布通", "BST3V3: U19.6 没布通", "SDA1: U35.4 没布通", "SCL3: U35.9 没布通", "TXD0: U20.37 没布通", "SDA5: U35.13 没布通", "EFUSE_EN5: U20.21 没布通", "EFUSE_EN4: U20.20 没布通", "EFUSE_EN3: U20.19 没布通", "EFUSE_EN2: U20.18 没布通", "EFUSE_EN1: U20.17 没布通", "RXD0: U20.36 没布通", "IO0: U20.27 没布通", "FAN_PWM_L: Q6.3 没布通", "FAN_PWM_L: J26.4 没布通"]} \ No newline at end of file diff --git a/.claude/r2/archive_base2L/pcb_base.py b/.claude/r2/archive_base2L/pcb_base.py new file mode 100644 index 0000000..3d62b70 --- /dev/null +++ b/.claude/r2/archive_base2L/pcb_base.py @@ -0,0 +1,673 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB（M8）：板框 + 分区 + 插槽阵列 + 安装孔。 + + /c/Python314/python .claude/r2/pcb_base.py # 只算 + 自检 + /c/Python314/python .claude/r2/pcb_base.py --outline # 画/重画板框（幂等） + /c/Python314/python .claude/r2/pcb_base.py --holes # 打安装孔 + /c/Python314/python .claude/r2/pcb_base.py --verify # 读回校验 + +与 `pcb_blade.py` 是同一套接口（`PCB` / `BW` / `BH` / `ZONES` / `mill_cuts()` …）， +下游的 `pcb_place` / `router` / `pcb_pour` 用 `--base` 切到这一份。 + +## 坐标系 + +**板左下角 = (0, 0)，x 向右、y 向上**（EasyEDA PCB 里 y 向上为正，方案 §22.5）。 +x = 槽距方向（5 槽并排），y = 槽长方向 / 板深。方案 §6.5 那张分区图可以直接抄。 + +## ⛔ 板框必须是**折线**不是导线 + +`pcb_PrimitiveLine` 在嘉立创里是**导线（铜）**。M4b~M6 的刀片板框就是这么画的： +渲染成品红、DRC 干净、四道几何校验全过，而客户端根本不认它是板框 +（自动布线一路弹「请先绘制板框！」）。见方案 §27.3。 +⇒ 板框只用 `pcb_PrimitivePolyline`。底板文档里现成那 4 条 `Line`（建工程时的默认框） + 属于同一个坑，`push_outline()` 会把它们删掉。 + +## 刀片投影是硬碰撞，不是净距问题 + +插槽把刀片底边抬到底板上方 ~11 mm ⇒ **投影带内元件 ≤ 8 mm**（方案 §6.6）。 +两颗 470 µF 直立电解、DC-005 座、TH 排针 / 风扇座都只能放到投影带**外面** +（`y < PROJ[0]` 或 `y > PROJ[1]`）。`zone_of()` / `height_ok()` 就是干这个的。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本，先插 .claude 会 import 到 R1 那一份且不报错。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import fp_edge # noqa: E402 + +PCB = '7b9524b6aaf6f235' # BASE-PCB（r2-uuids.json） +MIL = fp_edge.MIL + +# ── 板框（mm，出处 方案 §3.1）───────────────────────────────────────── +BW, BH = 110.0, 125.0 +CORNER_R = 5.0 # 底板四角 R5（刀片是 R2） +CORNER_SEG = 10 +OUTLINE_W = 0.15 + +# ══ M9 新坐标模型（2026-09-09 用户拍板）══════════════════════════════════ +# ⛔ **M8 的分带式布局（槽阵横排 + ctrl 带在北）在两层板上是死的**， +# 根因见方案 §29.1：单颗 Hub 扭出 5 路 D±，在扇出带里形成一道**横贯全板的墙** +# （`USB5`/`USB1` 共用 y=41.4 那条道，两段拼起来 x 24.5~105.1）， +# 而墙以北没有横向通道（5 个槽体 + 每槽两端的屏蔽脚把槽阵横向堵死）。 +# ⇒ 12V / 5V / 3V3 和 25 条槽上信号全都过不去，实测 173/314 条布不出来， +# 四轮打平（173/174/175/173），换 `BOT_PEN` 无效（178，更差）。 +# +# ⇒ **槽阵转 90°**：槽体长轴沿 x，五片刀片沿 y 堆叠。于是 +# **D± 走西缘、电源走东缘，走廊里全是平行车道，一个交叉都没有。** +# +# 为什么这条能成立（针位实测，见 §29.2）：把槽转成 A1 端**朝东**之后， +# 每只脚落在哪一列 x 是定死的 —— +# x 71.5 +12V(5) ← 紧贴东缘，12V 铜条只进走廊 4.5 mm +# x 66.5 SCL/SDA x 64.0 +3V3(3) x 61.5 EFUSE_EN / INT# +# x 56.0 D± x 54.5 VDAC x 51.5 / 38.5 +5V +# x 39.5 PRSNT# +# **x > 69 只有 `+12V` 一个网** ⇒ 12V 的铜条可以在走廊东端做成「顶天立地」的一堵墙 +# （同时够到上下两排焊盘），而不挡任何别的东西：其余全部从西边进来，最远只到 x=67。 +SLOT_PITCH = 20.32 # 刀片堆叠间距（沿 y），= 手机+刀片+间隙，机械定死 +SLOT_N = 5 +SLOT_ROT = 0 # 2026-09-10 用户要求：五个插槽从 rot 180 再转 180° +# ⚠ 槽体长轴中心**不在板中心**：西区要塞下 ESP32 的「天线 7.5 + 焊盘 19 = 26.5」， +# 所以整条阵列往东挪 3 mm。刀片 98 沿 x ⇒ 盖住 x 9~107，两边各留 3 mm。 +# ⛔ 再东移 2 mm（58→60）：D± 通道要塞下**三条**并行车道。一对 1.2 mm 的线在占用图里 +# 要 `1.41 + 2×0.81 = 3.03 mm`，三条 = 9.6，8 mm 的通道装不下 —— 现象是每对永远 +# 只进得去一根（「DP 通、DM 出不来」，七对里六对）。刀片随之盖住 x 11~109。 +# ⛔ **2026-09-09 用户拍板 A 方案**：通道从 10 加宽到 13.5，槽阵再东移 3.5（60→63.5）。 +# 账：一对 1.0 mm 的 D± 在占用图里要 `1.21 + 2×0.71 = 2.63`；车道还要能被一根 +# 0.25 的逃逸线横穿（吃掉 1.67）而仍装得下一对 ⇒ 车道 4.5，三条 = 13.5。 +# 代价：刀片（98 宽）盖住 x 14.5~112.5，**伸出东板边 2.5 mm**（用户已确认）。 +SLOT_CX = 46.5 # 插槽翻转后整体西移，东侧留 13.5 mm D± 通道 +# ⚠ 阵列中心比板中心（62.5）**往北挪 1 mm**：南带要塞下 DC-005 的 14.5 mm 桶身，外加 0.6 净距， +# 17.26 差 1 mm。北带少 1 mm 不影响（风扇块全是小件）。 +# M13：整组北移 3 mm，为最南槽 USB5 与 9 A 输入铜之间留出独立顶层走廊。 +# 槽距不变，并保留北侧辅助 Buck / 风扇服务带。 +ARRAY_CY = 66.5 +SLOT_BODY_L = 42.0 # 槽体沿 **x**（实测 `PCIE-64P11L` 焊盘外框） +SLOT_BODY_W = 9.2 # 槽体沿 **y** +# 两排焊盘：y = 槽心 ± 3.6；单盘 0.7(x) × 2.0(y)，脚距 1.0 +PAD_ROW_DY = 3.6 +PAD_L, PAD_W = 0.7, 2.0 +# 长轴上的针位（u = 距槽体中心，正 = 西）。A1 端朝东 ⇒ 板上 x = SLOT_CX − u。 +PIN_U = {'+12V': (-16.5, -14.5), 'I2C': (-12.5, -11.5), '+3V3': (-9.5, -7.5), + 'EN': (-6.5, -6.5), 'DIFF': (-1.5, -0.5), 'VDAC': (0.5, 0.5), + '+5V': (3.5, 16.5), 'PRSNT': (15.5, 15.5)} + + +def pin_x(u): + u"""长轴坐标 u（封装）→ 板上 x。rot 0 与 rot 180 互为镜像。""" + return round(SLOT_CX + u if SLOT_ROT == 0 else SLOT_CX - u, 3) + + +def slot_y(i): + u"""槽 i（1 = 最南）的中心 y。""" + return round(ARRAY_CY + (i - (SLOT_N + 1) / 2.0) * SLOT_PITCH, 3) + + +def slot_ys(): + return [slot_y(i) for i in range(1, SLOT_N + 1)] + + +def slot_body(i): + y = slot_y(i) + return (SLOT_CX - SLOT_BODY_L / 2, y - SLOT_BODY_W / 2, + SLOT_CX + SLOT_BODY_L / 2, y + SLOT_BODY_W / 2) + + +# ── 走廊：槽体之间那 11.12 mm，外加阵列两头 ──────────────────────────────── +# 走廊 k（0 = 阵列最南那条，5 = 最北）。内部四条各服务上下两个槽的一排焊盘。 +def corridor(k): + y0 = 0.0 if k == 0 else slot_y(k) + SLOT_BODY_W / 2 + y1 = BH if k == SLOT_N else slot_y(k + 1) - SLOT_BODY_W / 2 + return (0.0, round(y0, 3), BW, round(y1, 3)) + + +def corridors(): + return [corridor(k) for k in range(SLOT_N + 1)] + + +# ── 三条纵向分区（沿 x）─────────────────────────────────────────────────── +# 西区：12V 干道；中区：5 个槽体；东区：D± 通道 + Hub / 控制器。 +WEST = (0.0, 25.5) # 西侧 12V 服务区 +MID = (SLOT_CX - SLOT_BODY_L / 2, SLOT_CX + SLOT_BODY_L / 2) # 34 ~ 76 +EAST = (81.0, BW) # 东侧 Hub / ESP32 / mux / DAC 功能区 + +# 逻辑 USB 号 -> 插槽位号 / 物理槽位（南起 1..5）。 +# 插槽翻转后物理顺序与 USB 号反向；混用会让五对 D± 全交叉。 +USB_SLOT_REF = {1: 'J34', 2: 'J35', 3: 'J36', 4: 'J37', 5: 'J38'} +USB_SLOT_POS = {i: SLOT_N + 1 - i for i in range(1, SLOT_N + 1)} + + +def usb_corridor(i): + u"""USB i 的 D± 所在插槽南侧走廊。""" + return corridor(USB_SLOT_POS[i] - 1) + +# ── 刀片投影：每片刀片盖住 x 6~104，沿 y 占 ±7.35 ────────────────────────── +# 保守起见整条阵列带按投影处理（限高 8 mm，方案 §6.6）。 +BLADE_W = 98.0 # 刀片沿 x +BLADE_X0 = round(SLOT_CX - BLADE_W / 2, 2) # 6.0 +PROJ = (round(slot_y(1) - SLOT_BODY_W / 2, 2), + round(slot_y(SLOT_N) + SLOT_BODY_W / 2, 2)) # 17.26 ~ 107.74 +H_PROJ = 8.0 + + +def blade_x_to_base_x(bx): + u"""刀片自身坐标 x → 底板 x（刀片 98 沿 x 铺开，居中对齐槽体）。""" + return round(BLADE_X0 + bx, 3) + + +# ── 分区（y 方向只剩三条：南带 / 阵列带 / 北带）──────────────────────────── +ZONES = { + 'input': (0.0, 0.0, BW, PROJ[0]), # 投影外，可放高件：DC 座 / F1 / Q1 / Φ8 电解 + 'array': (0.0, PROJ[0], BW, PROJ[1]), # 槽体 + 走廊 + 西区器件 + 东区高速路 + 'fan': (0.0, PROJ[1], BW, BH), # 投影外：风扇座 ×2 / 驱动 / J33 应急口 +} + +# ── 12V（9 A）：南带进料 → 西侧高速路 → 每条走廊分段进槽 ──────────────── +# M12 当前布局把 U35/U6/U7 放在 x=10~15；主干只能使用它们与槽体之间 +# x=15.5~24.5 的连续通道。实测无异网焊盘侵入，9 mm 净宽仍高于 8 mm 要求。 +# ⛔ 北端只到 y=110：再往北是风扇驱动 `Q6`/`Q7`（它们本来就该贴着风扇座）， +# 高速路铺过去会被它们的非 12V 脚掐到 **5.70 mm**（断面校核实测）。 +# 那一段只带风扇 + 两颗 Buck（~3 A，5.7 mm 够），但校核按 9 A 一刀切 ⇒ +# 与其放宽判据，不如让干道在 110 收口，北边的 12V 由走廊 5 那堵铜墙供。 +# ⛔ 铜墙必须**伸进上下两个槽体 2.0 mm**：焊盘中心距槽心 3.6、盘高 2.0，也就是占了槽体边缘往里 0~2.0 那一段。 +# 只画走廊本身的话**一只 12V 脚都碰不到**，而铺铜管理器 / DRC 都不会响 +# （只有 `board_check` 从板上读回铜做并查集才看得见）。 +RIB_OVER = 1.4 +# 旧 BUS_S 与定稿后的 J1/F1/Q1 输入链重叠，会把 VIN_RAW 直接短到 +12V。 +# 干道改从投影带南沿开始，Rs6 -> 干道由路由器单独连接。 +# 南端避开 y=16.25 的 2 mm VIN_SW 引线；向东加宽后，扣除其净距仍超过 8 mm。 +# 东界距 x=27、宽 3 mm 的槽外壳 GND 焊盘保留 0.25 mm 净距。 +# RIB_X 保持从 x=24.5 起，与主干重叠 0.75 mm，并继续避开 x=33 的 GND 针。 +BUS_W = (15.5, 18.75, 25.25, BH - 0.5) +RIB_X = (24.5, 32.4) + + +def rib_rects(): + u"""五个插槽的 12V 分段铜墙。 + + 下排是 x=30/31/32，上排是 x=31/32；上排 x=30 紧邻 GND，槽心 x=27 + 还有巨大的外壳 GND 盘。所以不能再用「整条走廊顶天立地」的矩形。 + 每排用窄指覆盖电源脚，再在排外用宽帽接回西侧干道。 + """ + out = [] + c = 0.25 + row_o = PAD_ROW_DY + PAD_W / 2 + row_i = PAD_ROW_DY - PAD_W / 2 + x_lower = round(pin_x(-16.5) - PAD_L / 2 - 0.05, 3) # x=30 焊盘左侧 + x_upper = round(pin_x(-15.5) - PAD_L / 2 - 0.05, 3) # x=31 焊盘左侧 + for i in range(1, SLOT_N + 1): + cy = slot_y(i) + cap_lo = round(cy - row_o - RIB_OVER, 3) + cap_hi = round(cy - row_o - c, 3) + # 最南宽帽直接接到主干，并停在 J38 外壳 GND 的净距边界以内。 + if i == 1: + cap_lo = BUS_W[1] + top_hi = round(cy + row_o + RIB_OVER, 3) + # 北移后的 J34 靠近 C734；北帽只需覆盖针排并接到主干，不再向北多伸。 + if i == SLOT_N: + top_hi = round(cy + row_o + 0.9, 3) + out += [ + (RIB_X[0], cap_lo, RIB_X[1], cap_hi), + (x_lower, round(cy - row_o - c - 0.05, 3), RIB_X[1], + round(cy - row_i + c + 0.05, 3)), + (x_upper, round(cy + row_i - c - 0.05, 3), RIB_X[1], + round(cy + row_o + c + 0.05, 3)), + (RIB_X[0], round(cy + row_o + c, 3), RIB_X[1], top_hi), + ] + return out + + +def bus_rects(): + return [BUS_W] + rib_rects() + + +# ── +3V3 铜墙（M9b，2026-09-10 用户拍板）─────────────────────────────────── +# `+3V3` 是全板最大的网（47 只脚），A* 当一棵树布 ⇒ **整网崩**（M9 实测 46/47 没布通）。 +# 办法与 12V 同：把脚位那一段直接做成铜，脚从 A* 里摘掉。 +# +# ⛔ 但 3V3 的墙**不能像 12V 那样顶天立地**，因为它不在东缘尽头，而在信号中间： +# 南排 … EN(70) 3V3(71) 3V3(72) NC(73) NC(74) NC(75) NC(76) GND(77) 12V(78,79) … +# 北排 … INT#(70) NC(71) NC(72) 3V3(73) GND(74) SDA(75) SCL(76) GND(77) 12V(78~80) +# 每个槽的 `SDA_i`/`SCL_i` 在**北排 x 75/76**，要一路往西去 `U35`(x≈10~16) —— +# 任何一条从 x>73 一直连到 x<70 的**顶层**南北向铜，都会把这十根线拦腰截断。 +# ⇒ 墙只在**槽体那一段**（顶层，够着三只脚），走廊那一段**走底层桥**（0.8 mm + 两个过孔）。 +# 代价是地平面上多五道 9.5 mm 长的窄缝（都在 x≈72，D± 全在 x<66，不碰 §6.2 第 1 条）。 +# +# ⛔ 墙的 x 是**逐排不同的**（同一个矩形盖不住两排）： +# 南排的 3V3 在 71/72、北排的在 73，而它们各自旁边就是**没有网的 NC 针** +# （南排 73、北排 71/72）。一个 70.6~73.4 的方块会同时压上 NC 针 —— +# 铺铜会绕开它们、把墙在排上切碎，而铺铜管理器和 DRC 都只说「有铜」。 +# ⇒ 拆成「南窄 / 中宽 / 北窄」三段同网矩形（同网重叠是允许的，12V 那几块也是这么接的）。 +W3V3_CLR = 0.25 # 到异网针的净距（规则底线 0.20，留 0.05） +W3V3_OVER = 1.4 # 墙伸进走廊多少：给底层桥的过孔留地方 +W3V3_BRIDGE_W = 0.8 # 走廊底层桥的线宽（3V3 全板 ~0.3 A，0.8 够 2 A） +W3V3_VIA_DY = 5.4 # 过孔离槽心多远（针排外沿 4.6 + 0.55 环 + 余量） + + +def wall3v3_rects(): + u"""五块 `+3V3` 槽墙，每块三段（南窄 / 中宽 / 北窄）+ 两块走廊帽。 + + x 的来历（全部从 `PIN_U` 算，不手抄）： + 西边界 = `EN` 针右沿 + 净距；东边界 = `GND(74)` 针左沿 − 净距； + 南段东界 = 南排 NC(73) 针左沿 − 净距；北段西界 = 北排 NC(72) 针右沿 − 净距。 + """ + c = W3V3_CLR + # 新方向是旧铜墙相对槽心的水平镜像。 + x_w = round(SLOT_CX - 9.9, 3) + x_e = round(SLOT_CX - 7.1, 3) + x_s_e = round(SLOT_CX - 9.1, 3) + x_n_w = round(SLOT_CX - 8.9, 3) + row_o = PAD_ROW_DY + PAD_W / 2 # 针排外沿 4.6 + row_i = PAD_ROW_DY - PAD_W / 2 # 针排内沿 2.6 + out = [] + for i in range(1, SLOT_N + 1): + cy = slot_y(i) + out += [ + # 走廊帽（排外，没有任何针）：整宽，给桥的过孔一个圆整的落点 + (x_w, round(cy - row_o - W3V3_OVER, 3), x_e, round(cy - row_o - c, 3)), + # 南段：从走廊穿过南排（盖住 71/72）进到两排之间 + (x_w, round(cy - row_o - c - 0.05, 3), x_s_e, round(cy - row_i + c + 0.05, 3)), + # 中段：两排之间那 5.2 mm，整宽 + (x_w, round(cy - row_i + c, 3), x_e, round(cy + row_i - c, 3)), + # 北段：穿过北排（盖住 73） + (x_n_w, round(cy + row_i - c - 0.05, 3), x_e, round(cy + row_o + c + 0.05, 3)), + (x_w, round(cy + row_o + c, 3), x_e, round(cy + row_o + W3V3_OVER, 3)), + ] + return out + + +def wall3v3_bridges(): + u"""走廊里的**底层**桥：[(x, y0, y1, 宽)]，以及两端的过孔 [(x, y)]。 + + 只连相邻两块槽墙（4 段）。北端到 `U19`/`L2` 那一段交给 A*： + 它是一条普通的短网，不像槽脚那样被十根 I²C 挡着。 + """ + x = round(SLOT_CX - 8.5, 3) # 38.0，新方向的 3V3 墙中心 + segs, vias = [], [] + for i in range(1, SLOT_N): + y0 = round(slot_y(i) + W3V3_VIA_DY, 3) + y1 = round(slot_y(i + 1) - W3V3_VIA_DY, 3) + segs.append((x, y0, y1, W3V3_BRIDGE_W)) + vias += [(x, y0), (x, y1)] + return segs, vias + + +# ── D± 竖向扇出通道（西区）：`U32` 在西区中部，五对沿 y 散开再往东进走廊 ──── +# ⛔ 这条带里**一件都不许放**（同 M8 的 FANOUT，理由一样：排布器会把去耦塞满， +# 然后布线器报「某一对布了 0 段」，而摆位自检 / DRC / 几何验证一条都不响）。 +DP_CHAN = (67.5, PROJ[0], 81.0, PROJ[1]) +# Hub USB6 -> ESP32 原生 USB 的北向短通道。U20/U32 是端点，其他元件不得进入。 +USB6_CHAN = (80.5, 78.0, 84.8, 107.2) + +# ⛔ 阵列**北边**还要留一条 4 mm 的过道：最北那个槽（槽 5）的 D± 焊盘在它的北排， +# 北侧走廊就是风扇带本身。不留的话逃逸落点会掉进风扇块里 —— +# 实测 `J38.launch` 起步格点 **0**，现象是「差分对 USB5 布了 0 段」。 +DP_N_LANE = (MID[0], PROJ[1], BW, PROJ[1] + 4.0) + + +# ── 走廊「喉口」：西区器件与 D± 通道之间那一段，**一件都不许放** ──────────── +# ⛔ 2026-09-09 用户看出来的：`R605~R608` / `C9` / `C731` 那一窝落在走廊 2 的 +# y 段、x 20~28 上 —— 那正是西区**所有**去往槽 2 的信号（含它那一对 D±） +# 往东挤进通道的唯一喉口。堵在这儿的后果是布线器报「出不来 / 没布通」， +# 而摆位自检、DRC、几何校验一条都不会响。 +# ⇒ 每条内走廊在 x 17~29 这一段设成摆位禁区（器件退到槽体那几段 y 上去）。 +# ⚠ 宽度是权衡出来的：17~29（12 mm）会把西区挤爆（去耦平均从 22.9 涨到 33.3 mm）， +# 而喉口只要够信号穿过去就行 —— 6 mm 在 0.5 间距下可过十根线，够一条走廊的量。 +THROAT_X = (DP_CHAN[2], 87.0) + + +# `U32` 东沿到 D± 通道之间那条**逃逸扇形带**：十根 0.15 的细线从 QFN 脚扇到车道， +# 一件都不许放（放了就是 DRC「焊盘到导线」，实测 22 条压在 C602/C607 上）。 +HUB_ESC = (DP_CHAN[2], 55.0, 86.0, 78.0) + + +def throat_rects(): + out = [] + for k in range(1, SLOT_N): + c = corridor(k) + out.append((THROAT_X[0], c[1], THROAT_X[1], c[3])) + return out + + +def keepout_rects(): + u"""摆位禁区（不是铺铜禁区）：12V 高速路 + 铜墙 + 3V3 槽墙 + D± 竖向通道 + 天线缺口。""" + return (bus_rects() + wall3v3_rects() + + [DP_CHAN, USB6_CHAN, DP_N_LANE, ANT_NOTCH, HUB_ESC] + throat_rects()) + + +# ── ESP32 天线缺口（西板边）──────────────────────────────────────────────── +# 见 §28.14：`U20` 转 rot=90 天线朝西、天线那 7.5 mm 下方板材整块挖掉。 +# 新布局里 `U20` 挪到西北（靠近风扇带的 FAN_*/NTC 和 J33），缺口跟着走。 +ANT_NOTCH = (BW - 7.5, 86.0, BW, 108.0) + + +def notch_rect(): + return ANT_NOTCH + + +# ── 安装孔（M3 尼龙立柱，NPTH）──────────────────────────────────────── +HOLE_D = 3.2 +HOLE_KEEP = 3.2 +HOLE_INSET = 4.0 +MOUNT_HOLES = { + 'H1': (HOLE_INSET, HOLE_INSET), + 'H2': (BW - HOLE_INSET, HOLE_INSET), + 'H3': (HOLE_INSET, BH - HOLE_INSET), + 'H4': (BW - HOLE_INSET, BH - HOLE_INSET), +} + +# ── 下游脚本要的空壳 ───────────────────────────────────────────────────── +FLEX_W = {} +SLOT_Y = None +PHONE_ORG = None +PHONE_WH = None + + +def phone_holes(): + u"""两层都不许压的孔：四个 M3 安装孔（它们是 `pcb_PrimitivePad`，不在 pads.json 里）。""" + return dict(MOUNT_HOLES) + + +def mill_cuts(): + return [] + + +def notch_break(): + return None + + +def corner(cx, cy, a0, a1): + pts = [] + for k in range(CORNER_SEG + 1): + a = math.radians(a0 + (a1 - a0) * k / CORNER_SEG) + pts.append((cx + CORNER_R * math.cos(a), cy + CORNER_R * math.sin(a))) + return pts + + +def outline_pts(): + u"""板框点列（逆时针，从底边左端 (r,0) 起，闭合回 (r,0)）。东边带天线缺口。""" + r = CORNER_R + pts = [(r, 0.0), (BW - r, 0.0)] + pts += corner(BW - r, r, 270, 360) + pts += [(BW, ANT_NOTCH[1]), (ANT_NOTCH[0], ANT_NOTCH[1]), + (ANT_NOTCH[0], ANT_NOTCH[3]), (BW, ANT_NOTCH[3]), + (BW, BH - r)] + pts += corner(BW - r, BH - r, 0, 90) + pts += [(r, BH)] + pts += corner(r, BH - r, 90, 180) + pts += [(0.0, r)] + pts += corner(r, r, 180, 270) + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + assert abs(out[0][0] - out[-1][0]) < 1e-9 and abs(out[0][1] - out[-1][1]) < 1e-9, u'板框点列没有闭合' + return out + + +def outline_polygon(): + return outline_pts() + + +def zone_of(y): + for k, z in ZONES.items(): + if z[1] <= y < z[3]: + return k + return None + + +def height_ok(y, h, x=None): + u"""该位置允许 h mm 高的件吗（刀片投影是二维硬碰撞）。""" + in_y = PROJ[0] <= y <= PROJ[1] + in_x = x is None or BLADE_X0 <= x <= BLADE_X0 + BLADE_W + return not (in_x and in_y and h > H_PROJ) + + +def selfcheck(): + bad = [] + ys = slot_ys() + # 阵列必须居中、间距是机械定死的 20.32 + for a, b in zip(ys, ys[1:]): + if abs((b - a) - SLOT_PITCH) > 1e-6: + bad.append(u'槽间距 %.3f != %.2f' % (b - a, SLOT_PITCH)) + if abs((ys[0] + ys[-1]) / 2.0 - ARRAY_CY) > 1e-6: + bad.append(u'阵列没居中: %s' % ys) + # 槽体不许出板边（南北两头） + if ys[0] - SLOT_BODY_W / 2 < 2.0 or ys[-1] + SLOT_BODY_W / 2 > BH - 2.0: + bad.append(u'槽体贴板边太近: %.2f / %.2f' + % (ys[0] - SLOT_BODY_W / 2, ys[-1] + SLOT_BODY_W / 2)) + # 槽体长轴不许出板边（东西两头），且要给东区高速路让出地方 + if SLOT_CX - SLOT_BODY_L / 2 < WEST[1] - 1e-6 or SLOT_CX + SLOT_BODY_L / 2 > EAST[0] + 1e-6: + bad.append(u'槽体 x %.1f~%.1f 越过了西/东区边界 %.1f / %.1f' + % (SLOT_CX - SLOT_BODY_L / 2, SLOT_CX + SLOT_BODY_L / 2, WEST[1], EAST[0])) + # 走廊必须首尾相接、铺满板 + cs = corridors() + for a, b in zip(cs, cs[1:]): + if a[3] > b[1] + 1e-6: + bad.append(u'走廊重叠: %s / %s' % (a, b)) + if abs(cs[0][1]) > 1e-6 or abs(cs[-1][3] - BH) > 1e-6: + bad.append(u'走廊没铺满 0~%.1f' % BH) + for k in range(1, SLOT_N): + w = cs[k][3] - cs[k][1] + if abs(w - (SLOT_PITCH - SLOT_BODY_W)) > 1e-6: + bad.append(u'走廊 %d 净宽 %.2f != %.2f' % (k, w, SLOT_PITCH - SLOT_BODY_W)) + # 分区必须首尾相接 + ks = sorted(ZONES, key=lambda k: ZONES[k][1]) + for a, b in zip(ks, ks[1:]): + if abs(ZONES[a][3] - ZONES[b][1]) > 1e-6: + bad.append(u'分区 %s 顶 %.1f != %s 底 %.1f' % (a, ZONES[a][3], b, ZONES[b][1])) + if abs(ZONES[ks[0]][1]) > 1e-6 or abs(ZONES[ks[-1]][3] - BH) > 1e-6: + bad.append(u'分区没铺满 0~%.1f' % BH) + if abs(PROJ[0] - ZONES['input'][3]) > 1e-6 or abs(PROJ[1] - ZONES['fan'][1]) > 1e-6: + bad.append(u'刀片投影 %s 与 input/fan 带边界对不上' % (PROJ,)) + # ⛔ 这条是新布局能成立的**判据本身**：x > RIB_X[0] 只许有 +12V。 + # 别的网只要有一只脚落到铜墙的 x 区间里，那堵墙就不能顶天立地了。 + for tag, (u0, u1) in PIN_U.items(): + if tag == '+12V': + continue + for u in (u0, u1): + if pin_x(u) < RIB_X[1] + 0.5: + bad.append(u'%s 的针落在 x=%.1f，侵入 12V 铜墙区（x<%.1f 只许有 +12V）' + % (tag, pin_x(u), RIB_X[1])) + # 12V 铜墙要够得着 12V 针 + if not (RIB_X[0] < pin_x(PIN_U['+12V'][0]) < RIB_X[1]): + bad.append(u'12V 铜墙 x %.1f~%.1f 够不着 12V 针 x=%.1f' + % (RIB_X[0], RIB_X[1], pin_x(PIN_U['+12V'][0]))) + # 东缘高速路净宽（1 oz 外层 9 A ΔT20K 要 ≥8 mm） + if BUS_W[2] - BUS_W[0] < 8.0: + bad.append(u'西缘 12V 高速路只有 %.1f mm，9 A 要 ≥8' % (BUS_W[2] - BUS_W[0])) + if [USB_SLOT_REF[i] for i in range(1, SLOT_N + 1)] != ['J34', 'J35', 'J36', 'J37', 'J38']: + bad.append(u'USB -> 插槽位号映射被改坏') + for i in range(1, SLOT_N + 1): + c = usb_corridor(i) + if c[0] >= c[2] or c[1] >= c[3]: + bad.append(u'USB%d 的南侧走廊无效: %s' % (i, c)) + # 安装孔：不许出板 / 压槽体 / 被圆角切 / 落进天线缺口 + for n, (hx, hy) in MOUNT_HOLES.items(): + if not (HOLE_KEEP < hx < BW - HOLE_KEEP and HOLE_KEEP < hy < BH - HOLE_KEEP): + bad.append(u'安装孔 %s 出板或贴边: (%.1f, %.1f)' % (n, hx, hy)) + for i in range(1, SLOT_N + 1): + b0, b1, b2, b3 = slot_body(i) + if b0 - HOLE_KEEP < hx < b2 + HOLE_KEEP and b1 - HOLE_KEEP < hy < b3 + HOLE_KEEP: + bad.append(u'安装孔 %s 压到槽 %d' % (n, i)) + for cx, cy in ((CORNER_R, CORNER_R), (BW - CORNER_R, CORNER_R), + (CORNER_R, BH - CORNER_R), (BW - CORNER_R, BH - CORNER_R)): + out_x = hx < cx if cx < BW / 2 else hx > cx + out_y = hy < cy if cy < BH / 2 else hy > cy + if out_x and out_y and math.hypot(hx - cx, hy - cy) > CORNER_R - HOLE_KEEP: + bad.append(u'安装孔 %s 被 R%.0f 圆角切到' % (n, CORNER_R)) + if (ANT_NOTCH[0] - HOLE_KEEP < hx < ANT_NOTCH[2] + HOLE_KEEP and + ANT_NOTCH[1] - HOLE_KEEP < hy < ANT_NOTCH[3] + HOLE_KEEP): + bad.append(u'安装孔 %s 落进 ESP32 天线缺口 (%.1f, %.1f)' % (n, hx, hy)) + sep = chr(10) + ' ' + assert not bad, u'底板自检不过:' + sep + sep.join(bad) + return True + + +# ── 下发 ────────────────────────────────────────────────────────────── +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def mil(v): + return round(v * MIL, 4) + + +def polygon_src(pts): + a = [mil(pts[0][0]), mil(pts[0][1])] + for q in pts[1:]: + a += ['L', mil(q[0]), mil(q[1])] + if pts[0] != pts[-1]: + a += ['L', mil(pts[0][0]), mil(pts[0][1])] + return a + + +def push_outline(): + u"""板框 = 一条闭合折线；顺带删掉建工程时留下的 4 条层 11 **导线**（§27.3 的坑）。""" + src = polygon_src(outline_polygon()) + js = ("await eda.dmt_EditorControl.openDocument('%s');" % PCB + + "await new Promise(r=>setTimeout(r,2500));" + + "const oldL = (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11)" + ".map(l=>l.primitiveId);" + + "if (oldL.length) await eda.pcb_PrimitiveLine.delete(oldL);" + + "const oldP = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).map(p=>p.getState_PrimitiveId());" + + "if (oldP.length) await eda.pcb_PrimitivePolyline.delete(oldP);" + + "const poly = await eda.pcb_MathPolygon.createPolygon(%s);" % json.dumps(src) + + "const r = await eda.pcb_PrimitivePolyline.create('', 11, poly, %s);" % mil(OUTLINE_W) + + "await eda.pcb_Document.save();" + + "return {delLine: oldL.length, delPoly: oldP.length, made: !!r," + " now: (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).length," + " line11: (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11).length};") + r = call(js, timeout=300) + print(u'板框折线: %s（删旧导线 %d / 旧折线 %d）；层 11 现有折线 %d / 导线 %d' + % (u'建好' if r['made'] else u'失败', r['delLine'], r['delPoly'], r['now'], r['line11'])) + if not r['made'] or r['now'] != 1: + raise SystemExit(u'!! 板框没画成') + return r + + +PUSH_HOLES_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const H = %s, D = %s; +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const num = p.getState_PadNumber(); + if (typeof num === 'string' && /^H[1-9]$/.test(num)) + await eda.pcb_PrimitivePad.delete(p.getState_PrimitiveId()); +} +let k = 0; +for (const [name, x, y] of H) { + // layer 12 = 多层；末位 metallization=false ⇒ NPTH。参数位序照抄 pcb_blade.push_holes + await eda.pcb_PrimitivePad.create(12, name, x, y, 0, ['ELLIPSE', D, D], '', + ['ROUND', D], 0, 0, 0, false); + k++; +} +await eda.pcb_Document.save(); +return {made: k, now: (await eda.pcb_PrimitivePad.getAll()) + .filter(p => /^H[1-9]$/.test(String(p.getState_PadNumber()))).length}; +""" + + +def push_holes(): + arr = [[k, mil(v[0]), mil(v[1])] for k, v in sorted(MOUNT_HOLES.items())] + r = call(PUSH_HOLES_JS % (PCB, json.dumps(arr), mil(HOLE_D)), timeout=300) + print(u'安装孔: 下发 %d / 读回 %d，NPTH Φ%.1f（M3 尼龙立柱）' % (r['made'], r['now'], HOLE_D)) + for k, v in sorted(MOUNT_HOLES.items()): + print(u' %-3s (%6.2f, %6.2f)' % (k, v[0], v[1])) + return r + + +def verify(): + r = call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "const ps = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11);" + "const line11 = (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>l.layer===11).length;" + "const holes = (await eda.pcb_PrimitivePad.getAll())" + ".filter(p=>/^H[1-9]$/.test(String(p.getState_PadNumber())))" + ".map(p=>[String(p.getState_PadNumber()), p.getState_X(), p.getState_Y()]);" + "return {n: ps.length, poly: ps.length ? ps[0].getState_Polygon() : null," + " line11, holes, comps: (await eda.pcb_PrimitiveComponent.getAll()).length};" % PCB, + timeout=180) + bad = [] + if r['n'] != 1: + bad.append(u'层 11 上有 %d 条折线（应为 1）' % r['n']) + if r['line11']: + bad.append(u'层 11 上还有 %d 条**导线**（板框画成铜的老坑，§27.3）' % r['line11']) + pts = [] + src = r['poly'] + if isinstance(src, dict): + src = src.get('pointArr') or src.get('points') or src.get('polygon') or src + if isinstance(src, list): + i = 0 + while i < len(src): + if src[i] in ('L', 'l'): + i += 1 + continue + if isinstance(src[i], (int, float)) and i + 1 < len(src) and isinstance(src[i + 1], (int, float)): + pts.append((src[i] / MIL, src[i + 1] / MIL)) + i += 2 + else: + i += 1 + if pts: + xs = [p[0] for p in pts] + ys = [p[1] for p in pts] + if abs(min(xs)) > 0.01 or abs(max(xs) - BW) > 0.01 or \ + abs(min(ys)) > 0.01 or abs(max(ys) - BH) > 0.01: + bad.append(u'外接矩形 %.2f~%.2f x %.2f~%.2f != 0~%.0f x 0~%.0f' + % (min(xs), max(xs), min(ys), max(ys), BW, BH)) + if abs(pts[0][0] - pts[-1][0]) > 0.01 or abs(pts[0][1] - pts[-1][1]) > 0.01: + bad.append(u'折线首尾不重合: %s vs %s' % (pts[0], pts[-1])) + if abs(len(pts) - len(outline_polygon())) > 1: + bad.append(u'点数 %d != %d' % (len(pts), len(outline_polygon()))) + print(u'读回板框折线 1 条 / %d 点，外接 %.2f~%.2f x %.2f~%.2f；层 11 遗留导线 %d' + % (len(pts), min(xs), max(xs), min(ys), max(ys), r['line11'])) + else: + bad.append(u'读不回折线点列（原始值 %s）' % str(r['poly'])[:120]) + got = {h[0]: (round(h[1] / MIL, 3), round(h[2] / MIL, 3)) for h in r['holes']} + for n, (hx, hy) in sorted(MOUNT_HOLES.items()): + if n not in got: + bad.append(u'安装孔 %s 没打' % n) + elif abs(got[n][0] - hx) > 0.02 or abs(got[n][1] - hy) > 0.02: + bad.append(u'安装孔 %s 位置 %s != (%.1f, %.1f)' % (n, got[n], hx, hy)) + print(u'安装孔读回 %d 个；板上元件 %d 件' % (len(got), r['comps'])) + if bad: + print(u'[X] 校验不过:') + for b in bad: + print(u' ' + b) + else: + print(u'[OK] 板框是一条闭合折线、外接矩形对上、安装孔齐') + return bad + + +if __name__ == '__main__': + selfcheck() + print(u'底板 %.0f x %.0f，四角 R%.0f；PCB=%s' % (BW, BH, CORNER_R, PCB)) + print(u'槽阵 5 槽 @%.2f（沿 y 堆叠，长轴沿 x，rot %d）: %s' + % (SLOT_PITCH, SLOT_ROT, u' / '.join('%.2f' % y for y in slot_ys()))) + print(u'槽体 x %.1f~%.1f；刀片投影 y %.1f~%.1f（带内元件 ≤ %.0f mm）' + % (MID[0], MID[1], PROJ[0], PROJ[1], H_PROJ)) + print(u'西区 x %.0f~%.0f | D± 通道 %.0f~%.0f | 中区 %.0f~%.0f | 东区 %.0f~%.0f' + % (WEST[0], WEST[1], DP_CHAN[0], DP_CHAN[2], MID[0], MID[1], EAST[0], EAST[1])) + print(u'12V：Rs6 单独接入 → 西缘高速路 %s → %d 堵铜墙' + % (BUS_W, len(rib_rects()))) + if '--outline' in sys.argv: + push_outline() + verify() + elif '--holes' in sys.argv: + push_holes() + verify() + elif '--verify' in sys.argv: + verify() diff --git a/.claude/r2/archive_base2L/place_base.py b/.claude/r2/archive_base2L/place_base.py new file mode 100644 index 0000000..a818f85 --- /dev/null +++ b/.claude/r2/archive_base2L/place_base.py @@ -0,0 +1,1267 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 摆位（M8c）。 + + /c/Python314/python .claude/r2/place_base.py # 只算 + 自检，不下发 + /c/Python314/python .claude/r2/place_base.py --push # 下发摆位 + /c/Python314/python .claude/r2/place_base.py --verify # 读回校验（含朝向断言） + /c/Python314/python .claude/r2/place_base.py --dump # 重抓焊盘坐标 _base_pads.json + /c/Python314/python .claude/r2/place_base.py --bbox # 重抓封装外框 _base_bbox.json + /c/Python314/python .claude/r2/place_base.py --adopt-live --verify + # 采用 EasyEDA 当前 138 件布局 + +算法照搬刀片 M7 那一版（方案 §27.5）：**大件先挑「离目标最近的空位」**， +目标点精确到对端焊盘；不是「按面积自下而上塞」。 + +## 五条带（`pcb_base.ZONES`） + +| 带 | y | 放什么 | 为什么 | +|---|---|---|---| +| input | 0~15.5 | A1-INPUT 全部 + `J23` USB-C | **投影带外**，唯一能放 Φ8 直立电解 / DC 座的地方 | +| hub | 15.5~43.5 | A4-HUB | `U32` 顶着槽阵南沿，D± 一出脚就往北 | +| slots | 43.5~85.5 | 只有 `J34~J38` | 走廊要留给 12 根/条的信号，**一件都不放** | +| ctrl | 85.5~113.5 | A3-CTRL + A2-AUX + 风扇小件 | 全部 ≤8 mm，压在刀片投影下没问题 | +| fan | 113.5~125 | `J26/J27` 风扇座 + `J33` 应急口 | **投影带外**，TH 立式 11 mm 高只能在这 | + +## ⛔ 三条「几何验证抓不到、错了就整板报废」的朝向 + +1. **`U32` rot=270**：下行口 pin1~16 在封装原生朝向是**西边**（实测 dx=-4.45）， + 转 270° 才朝北正对槽阵。转 90° 会朝南 —— 五对 D± 得从芯片底下绕出来。 +2. **插槽物理顺序是反的：西 → 东 = `J38 J37 J36 J35 J34`**。 + `U32` 转 270° 之后北排的 x 顺序是 **USB1 在东、USB5 在西**（pin1 dy=+3.75 → x=+3.75）。 + 若按位号自然顺序把 `J34` 摆在西边，五对 D± 会**互相交叉**；两层板上交叉 = 打过孔换到 + L2 = 在 D± 走廊正下方割地平面，正是方案 §6.2 第 1 条明令禁止的那件事。 + ⇒ 宁可位号顺序看着别扭。丝印上会写清楚。 +3. **插槽 rot=90**：封装原生长边沿 x、A 排在 +y。转 90°（逆时针）之后 + A1/B1 落在**南**（y=48）、A 排在**西**列、B 排在**东**列。 + 于是 `+12V`（A2/A3/B1~B3，y 48~50）正对南边的入口链， + `D±`（B14/B15，y 63/64）在东列 —— 与上面第 2 条一起决定了走廊分工。 + ⚠ 旋转方向（顺/逆）是**推导 + 读回校验**的：`verify()` 里三条断言就是干这个的， + 断言不过说明本机客户端的 rot 语义与假设相反，把 90/270 对调即可。 + +## D± 长度：最远一路 ~70 mm，是**已知并接受**的（2026-09-09 用户拍板） + +方案 §6.3 预估 41 mm，前提是 §6.2 第 3 条「D± 排在靠 Hub 那一端的针位」。 +但 M2d 定稿的针位表把 `USB_DP/DM` 放在 **B14/B15**，换算到底板 y=63/64 —— +**正好在 42 mm 长插槽的正中**。Hub 只能坐在槽阵南边，于是每一路都要 +「出脚 → 沿 y≈41 走 x → 拐进走廊 → 北上 20 mm」。端槽 x 距离 40.6 mm 是几何定死的。 +⇒ 最远 ~70 / 最近 ~30。仍远短于 R1 载板的 92 mm，全程 L2 完整地平面做参考， + 且 `J39~J43` 五个 D± 退路座（D12）本来就是为这一条留的。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +BBOX = os.path.join(HERE, '_base_bbox.json') +NETS = os.path.join(HERE, '_base_pcb_nets.json') +PADS = os.path.join(HERE, '_base_pads.json') +POS_JSON = os.path.join(HERE, '_base_place.json') +ROT_JSON = os.path.join(HERE, '_base_rotations.json') +PRE_FLIP_POS = os.path.join(HERE, '_base_place_pre_slot_flip.json') +LIVE_POS_JSON = os.path.join(HERE, '_base_place_live.json') + +GAP = 0.6 # 件间净距（装配下限，自检按它判重叠） +PACK_GAP = 1.5 # 排布器摆放节距（刀片 M7 用 1.8；底板件多、板面紧，1.5） +EDGE_KEEP = 1.0 # 件离板边 +STEP = 0.5 # 候选格点步长 +SNAP = 0.25 # 布线网格 + +# ── 高度表（mm）：投影带（y 15.5~113.5）内**硬上限 8**，方案 §6.6 ────────── +HEIGHT = { + 'J1': 11.0, # DC-005 桶身 + 'C2': 12.0, 'C3': 12.0, # Φ8 直立电解 470 µF + 'J26': 11.0, 'J27': 11.0, # 2510 4P 立式 + 'J33': 11.5, # 2.54 排针立式 + 'J23': 3.3, # USB-C 沉板座 + 'U20': 3.1, 'L3': 4.5, 'L2': 4.0, 'F1': 2.0, +} +H_DEFAULT = 2.0 + +# ── 焊盘外框量不到本体的件：给真实本体（mm）。⛔ 不给的话自检会让小件贴到 +# 直立电解的肚子上 / 排针的塑壳里 —— 焊盘框只有 5.1×1.6，本体是 Φ8。 +BODY = { + 'J1': (14.5, 9.0), # DC-005 桶身（桶口朝板边，见 EDGE_PARTS） + 'C2': (8.0, 8.0), 'C3': (8.0, 8.0), # Φ8 直立电解 470 µF + 'J23': (9.0, 7.5), # USB-C 沉板座本体 + 'J26': (10.2, 5.0), 'J27': (10.2, 5.0), # 2510 4P 带卡扣 + 'J33': (12.7, 2.54), # 2.54 排针塑座 + 'L3': (7.6, 6.5), # 焊盘只量到 3.4，本体 6.5 + 'U20': (19.0, 19.0), # 焊盘外框实测 19.002 × 18.99；天线那 7.5 mm 另有 antenna_keepout 管 +} +# 本体相对**焊盘质心**的偏移（本体不居中的件）。R1 §pcb1_place 实测： +# DC-005 的本体在 x −10.68~+3.92 ⇒ 中心偏 −3.38，桶口朝 −X（rot 0）。 +BODY_OFF = { + 'J1': (-3.38, 0.0), + 'J23': (0.0, -1.5), # USB-C 焊盘在里、口在外 +} +# 本体越过板边是**对的**那几个（接口件）：不判「出板」，改判「够不够得着板边」。 +# 值 = 开口朝哪条边。⚠ 朝向靠 rot 换算：DC-005 桶口原生朝 −X ⇒ 朝南要 rot 90。 +EDGE_PARTS = {'J1': 'S', 'J23': 'S'} + +# 2026-09-10 用户在 EasyEDA 客户端定稿的输入链（截图读回坐标）。 +# 它们是机械/热布局锚点，不再进行 0.25 mm 自动吸附。 +USER_INPUT = { + 'J1': (20.83, 10.79, 90), + 'F1': (31.08, 3.63, 0), + 'Q1': (37.08, 6.63, 0), + 'D1': (44.08, 5.13, 0), + 'C1': (35.77, 1.25, 0), + 'R1': (38.27, 1.25, 0), + 'DZ1': (43.31, 1.78, 180), + 'C4': (36.96, 12.83, 0), + 'C5': (46.08, 13.13, 0), + 'C6': (33.27, 11.56, 0), + 'C2': (68.12, 4.30, 270), + 'C3': (68.12, 13.19, 90), + 'Rs6': (75.99, 8.74, 90), + 'U13': (76.71, 16.89, 180), + 'RT602': (32.07, 9.16, 0), + 'C11': (87.95, 37.72, 270), +} + +# M12 路由预检确认这两颗 0402 横断 U32 -> U20 的 USB6 唯一顶层通道。 +ROUTE_FIX = { + 'J34': (46.50, 107.14, 0), + 'J35': (46.50, 86.82, 0), + 'J36': (46.50, 66.50, 0), + 'J37': (46.50, 46.18, 0), + 'J38': (46.50, 25.86, 0), + 'C7': (55.75, 120.75, 90), + 'C731': (49.25, 117.50, 270), + 'C10': (69.00, 122.50, 0), + 'R610': (76.50, 116.25, 0), + 'R722': (76.50, 118.00, 180), + 'C737': (85.50, 67.00, 270), + 'R9C': (88.50, 13.4266, 0), + 'R9D': (88.50, 17.9266, 180), + 'R9E': (88.50, 22.4266, 0), + 'Rs6': (63.75, 4.00, 0), + 'U13': (63.75, 10.50, 180), + 'U29': (67.00, 13.00, 180), + 'DZ1': (31.00, 1.65, 0), + # C1/R1 在 34.0/36.0 时 C1 本体离 DZ1 仅 0.22 mm（装配净距要 0.6）；东移 0.5 后自检无新增冲突。 + # R1 翻 180°：GATE 脚朝西、与 C1.2 相邻直连；GND 脚朝东，落在 GATE 缺口里的地铜上。 + 'C1': (34.50, 1.20, 0), + 'R1': (36.50, 1.20, 180), +} + + +def route_fix_moves(): + u"""ROUTE_FIX 相对 EasyEDA 实测布局还没落地的改位：{ref: (实测, 目标, 转角)}。""" + live = json.load(io.open(LIVE_POS_JSON, encoding='utf-8')) + out = {} + for ref, t in ROUTE_FIX.items(): + if ref not in live: + raise RuntimeError(u'实测布局快照缺少 %s，不能计算路由坐标' % ref) + o = live[ref] + dr = (int(round(t[2])) - int(round(o[2]))) % 360 + if abs(t[0] - o[0]) > 1e-9 or abs(t[1] - o[1]) > 1e-9 or dr: + out[ref] = (o, t, dr) + return out + + +def route_fixed_pads(pads): + u"""把焊盘换算到 ROUTE_FIX 的计划位置，返回 (pads, 改位说明)。原地改。 + + 布线（`route_base`）和铺铜（`pour_base`）**必须用同一份**：以前铺铜读实测焊盘、 + 布线读改位后的，DZ1 一挪，两边算出来的 VIN_FUSED/VIN_SW 分界差 2.4 mm。 + 180° 翻转：焊盘相对器件原点的偏移取反，长宽不变。90°/270° 要交换焊盘长宽， + 离线模型不做 —— 先下发再重抓。板端下发并 `--adopt-live --dump` 之后改位量归零， + 这里就是恒等变换。 + """ + moved = [] + for ref, (o, t, dr) in sorted(route_fix_moves().items()): + if dr not in (0, 180): + raise RuntimeError(u'%s 的 ROUTE_FIX 转了 %d°；离线模型只支持平移与 180° 翻转' + % (ref, dr)) + sgn = -1.0 if dr == 180 else 1.0 + for p in pads: + if p[0] == ref: + p[2] = round(t[0] + sgn * (p[2] - o[0]), 4) + p[3] = round(t[1] + sgn * (p[3] - o[1]), 4) + moved.append(u'%s(%+.2f,%+.2f%s)' % (ref, t[0] - o[0], t[1] - o[1], + u',翻180°' if dr else u'')) + return pads, moved + + +# ── 手排件：位置有理由的都钉死，其余交给排布器 ──────────────────────────── +def hand(): + u"""{位号: (x, y, rot)}。每一条都写清楚为什么在这。M9 布局见 `pcb_base` 文件头。""" + H = {} + # ── 5 个插槽：长轴沿 x、**A1 端朝东**（rot 180），沿 y 从南到北 ──────── + # ⛔ 位号顺序不是随便排的：`U32` rot=180（下行口朝东）之后，USB1 在**南**、 + # USB5 在**北**（rot 270→180 是 −90°，原来朝东的 USB1 转到朝南）。 + # 照着排 ⇒ 五对 D± 从 Hub 到各槽单调、互不交叉；排反了会全部交叉， + # 而两层板上交叉 = 打过孔换层 = 在 D± 底下割地平面（方案 §6.2 明令禁止）。 + # **这条几何验证抓不到**，靠下面 verify() 的读回断言钉死。 + for i, ref in enumerate(SLOT_ORDER, start=1): + H[ref] = (B.SLOT_CX, B.slot_y(i), B.SLOT_ROT) + # ── Hub：西区正中，下行口朝东正对槽阵 ──────────────────────────────── + # y 取阵列中心 ⇒ 五对 D± 往南北各散两条，任一 y 上最多 3 对并行（通道 8 mm 够）。 + # x 取 20：本体 9.75 ⇒ 15.1~24.9，东边留 4 mm 给逃逸扇形接进 D± 通道（29~37）。 + # y 取 66 不是阵列中心 62.5：D± 焊盘在各槽的 +3.6 那一排，取中心会让最北一路 + # 比最南一路长 7 mm（实测 72 / 79）。挪到 66 之后两头都是 ~75，压在验收线上。 + H['U32'] = (20.0, 67.0, 180) + # 晶振贴着 XTAL1/2。rot 180 之后那两只脚在**南**边（x 21.8/22.2, y 62.5）。 + # ⛔ 原来放 (20,53) 离脚 **14 mm** —— 负载电容贴上去了、晶振本体却拉在外面，等于白贴。 + # x 取 24：让开南边 `USB6`/上行的逃逸扇形（x 18.25~21.25，往南走到 y=57.5）。 + # 晶振挪到南沿**西端**：南沿净空只有 3.2 mm（U32 本体 62.1 到走廊2 的 58.9）， + # 晶振本体 2.9 一放，VDD18PLL/RBIAS 那两颗就没地方了 ⇒ 让出脚正下方给它们。 + H['Y1'] = (17.5, 60.0, 0) # 本体 15.7~19.3 / 58.55~61.45，离 XTAL 脚 4.7 + # 负载电容要贴**晶振**（不是芯片脚）—— 排布器只认芯片当锚，会把 C741 摆到 5.3 mm 外。 + H['C740'] = (14.0, 60.0, 0) # 贴 Y1 西侧（Y1 本体 3.6 宽 ⇒ 边到边 0.6） + H['C741'] = (21.0, 59.0, 0) # 贴 Y1 东南（让开 C743 那一列） + # ⛔ 用户 2026-09-09 指出这两颗摆错：`C743`（VDD18PLL 去耦）在 5.6 mm 外， + # `R708`（RBIAS 基准电阻）坐在 `U32` 东边那条 D± 逃逸窄缝里（x 24.4~29）。 + # RBIAS 是 Hub 的电流基准，去耦是内部 LDO 的 —— 两颗都要贴着自己那只脚， + # 而且都不能占那条缝（十根 D± 从那儿往东扇出）。⇒ 一起放到南沿脚正下方。 + H['C743'] = (22.75, 61.0, 0) # VDD18PLL 脚在 (22.75, 62.55) ⇒ 1.55 mm + H['R708'] = (25.3, 61.0, 0) # RBIAS 脚在 (23.25, 62.55) ⇒ 2.7 mm，且让开逃逸缝 + # ── ESP32：西区北部，天线朝西伸进板框缺口（ANT_NOTCH y 86~108）──────── + # 焊盘框 19×19 ⇒ x 7.5~26.5，天线段 x 0~7.5 悬在缺口里；东边到 D± 通道还有 2.5 mm。 + H['U20'] = (17.0, 97.0, 90) + # ── 上行 USB-C：南带**西头**板沿（M8 在东头，那是因为 Hub 在板中；现在 Hub 在西） + H['J23'] = (20.0, 5.25, 0) + # ── 入口链：南带，西 → 东（电流方向 +x），末端接东缘高速路 ────────────── + # 整条手排的理由同 M8：全板电流最大（9 A），形状决定断面，不能交给通用排布器。 + H['J1'] = (44.0, 10.00, 90) # DC-005，rot 90 = 桶口朝南；本体 y −0.6~13.9 + # ⚠ 上沿 17.25 卡着槽 1 的槽体（17.26），别再往北挪 + # ⚠ 南带只有 17.26 高，桶身 14.5 ⇒ y 只能在 7.3~8.5 之间 + H['F1'] = (51.5, 14.0, 0) # 1206 保险，卧着放，电流顺着 +x 直穿 + H['Q1'] = (57.5, 11.0, 0) # SOP-8 P-MOS 防反接 + H['D1'] = (64.5, 12.5, 0) # SMBJ13A TVS + H['C2'] = (73.0, 11.0, 0) # Φ8 直立电解 470 µF（南带 17.26 高，放得下） + H['C3'] = (82.5, 11.0, 0) + H['C4'] = (59.5, 4.5, 0) # 0805 VIN_SW 旁路 + H['C5'] = (66.5, 4.5, 0) + H['C6'] = (51.5, 5.0, 0) # 100nF 高频旁路，贴 F1 南边 + H['Rs6'] = (91.0, 11.0, 0) # 2512 5 mΩ 检流，接东缘高速路的南头 + H['U13'] = (91.0, 5.5, 0) # INA226 贴着 Rs6 走 Kelvin + # ── 风墙：两只风扇座 + 应急串口，全在北带（投影外，可高）─────────────── + H['J26'] = (13.0, 118.5, 0) # 别压 H3 螺钉头（4,121） + H['J27'] = (26.0, 118.5, 0) + H['J33'] = (39.5, 118.5, 0) + # ── 两个 Buck 的环路**必须手排** ──────────────────────────────────── + # ⛔ 交给排布器的实测下场：`U19`→`L2`（SW 节点）隔 **18.4 mm**， + # 自举电容 `C8` 落在 **69 mm** 外；`U30`→`L3` 隔 31 mm、`C733` 29 mm。 + # SW 和 BST 是开关电源里最吵的两个网，拉这么长直接变 EMI 源， + # 而 DRC / 几何自检 / 布线器**一个都不会响**（它们只看得见「连上了没有」）。 + # 摆法：IC → 电感紧邻（SW 最短）→ 自举电容贴 IC → FB 分压贴 FB 脚。 + H['U19'] = (51.5, 116.5, 0) # 3V3 Buck（西侧留给 FB，东侧紧贴电感） + H['C8'] = (51.5, 112.5, 0) # BST/SW 跨接，放 U19 南侧避开北边出脚 + H['L2'] = (57.0, 116.5, 0) # SW → +3V3，紧邻 + H['R2'] = (47.25, 118.25, 0) # FB 分压贴 U19 西侧 pin4 + H['R3'] = (47.25, 115.75, 0) + H['U30'] = (64.5, 116.5, 0) # 5V Buck + H['C733'] = (64.5, 120.5, 0) # BST，贴着 U30 + H['L3'] = (71.5, 116.5, 0) # SW → +5V，紧邻（本体 7.6×6.5，别贴穿 U30） + H['R706'] = (61.0, 118.25, 0) # FB 分压贴 U30 西侧 pin4 + H['R707'] = (61.0, 115.75, 0) + # ── 泄放块：五颗 2512 串联链排成一列，U29 / 分压贴着 Q3 ──────────── + # 它们只在回灌瞬态导通，占空比极低；排成列是为了让 `$1N114…$1N129` 那串 + # 短接线不要横跨半块板（实测 R9A~R9E 摊在 30 mm 上）。 + # ⛔ 泄放整块放在**槽体那一段 y**（38.6~47.8），不能放走廊：走廊 x17~29 是喉口， + # 西区所有去槽的信号都从那儿过（用户 2026-09-09 指出「电阻挡住通道」）。 + H['Q3'] = (25.0, 43.0, 0) # D-PAK 4.38×7.57 + H['R9A'] = (4.0, 14.0, 90) # 五颗 2512 转 90° 排成一行（转后 3.46×7.42，间距 4.5） + H['R9B'] = (8.5, 14.0, 90) + H['R9C'] = (13.0, 14.0, 90) + H['R9D'] = (17.5, 14.0, 90) + H['R9E'] = (22.0, 14.0, 90) + H['U29'] = (20.0, 43.5, 0) + H['R4'] = (18.0, 40.5, 0) + H['R5'] = (18.0, 46.0, 0) + H['R6'] = (5.0, 40.5, 0) # U35 本体 7.55×7.7，让开 + # ── mux / DAC：西区中南部，就近喂槽阵的 SCL/SDA 与 VDAC ──────────────── + H['U35'] = (12.0, 45.0, 0) # I²C mux + H['U6'] = (12.0, 35.0, 0) # DAC 1/2/4 + H['U7'] = (12.0, 25.0, 0) # DAC 3/5 + # DAC 参考/去耦不许由排布器挤到芯片另一侧。 + H['C608'] = (16.25, 37.75, 0) # U6.13 + H['C611'] = (16.25, 27.75, 0) # U7.13 + H['C612'] = (9.25, 28.0, 0) # U7.16 + # ESP32 ADC/EN 的 RC 贴模组南北排；三颗都低于刀片投影限高。 + H['C603'] = (10.75, 85.5, 0) # EN，贴 U20.3 + H['C736'] = (9.5, 108.0, 0) # NTC1，贴 U20.39 + H['C739'] = (11.5, 108.0, 0) # NTC2，贴 U20.38 + # 两只风扇座共用的储能电容，放在两座中间的出脚空档。 + H['C738'] = (18.25, 122.5, 0) + # ⚠ `U31`（AMS1117）交给排布器：它跟着 U32 走，母线一改就得跟着改。 + # 插槽翻转后功能分区整体水平镜像：12V 去西侧，控制/USB 去东侧。 + for ref, (x, y, rot) in list(H.items()): + if ref in SLOT_ORDER: + continue + H[ref] = (round(B.BW - x, 3), y, (180 - rot) % 360) + H['J23'] = (B.BW - 20.0, 5.25, 0) # 接口仍朝南板边 + H['U20'] = (B.BW - 17.0, 97.0, 270) # 天线朝东，伸入新的东边缺口 + # 水平镜像后多引脚器件的脚侧会变，关键 RC/去耦按读回脚位重新钉位。 + H['C603'] = (99.5, 108.0, 0) # ESP32 EN，贴 U20.3 + H['C736'] = (100.5, 85.5, 0) # NTC1，贴 U20.39 + H['C739'] = (98.5, 85.5, 0) # NTC2，贴 U20.38 + H['C742'] = (88.5, 61.0, 0) # U32 VDD18，贴南排 pin25，让开晶振 + H['C743'] = (87.25, 73.5, 0) # U32 VDD18PLL，贴北排 pin62 + H['C608'] = (95.0, 31.0, 180) # U6.13 参考/去耦，信号端朝芯片 + H['C609'] = (101.0, 32.0, 0) # U6.16 + H['R615'] = (101.0, 38.5, 0) # U6.5 + H['C611'] = (95.0, 20.5, 180) # U7.13，信号端朝芯片 + H['C612'] = (101.0, 22.0, 0) # U7.16 + H['R617'] = (101.0, 28.5, 0) # U7.5 + # 5V Buck 输出电容回到 U30/L3 功率环；Hub LDO 的输入/输出电容贴 U31。 + H['C734'] = (31.0, 114.0, 0) + H['C735'] = (31.0, 119.0, 0) + H['C737'] = (82.0, 17.5, 0) + H['C752'] = (85.5, 27.5, 0) + H['C753'] = (89.0, 27.5, 0) + H['C10'] = (69.0, 110.5, 0) # 3V3 Buck 输出储能，位于北侧功率带 + H['C7'] = (63.0, 110.25, 0) # U19 12V 输入去耦 + H['C731'] = (54.0, 112.0, 0) + H['C732'] = (45.5, 112.0, 0) # U30 12V 输入去耦 + H['C9'] = (50.0, 122.5, 0) # U19/L2 3V3 输出储能 + H['DZ1'] = (47.0, 17.0, 0) # Q1 GATE/VIN_FUSED RC 紧贴芯片北西侧 + H['C1'] = (50.5, 17.0, 0) + H['R1'] = (53.0, 17.0, 0) + H['R614'] = (103.0, 33.5, 0) # U6.16 的参考 RC + H['C601'] = (96.5, 111.0, 0) # ESP32 22uF + H['C602'] = (98.5, 108.0, 0) # ESP32 100nF + H['R601'] = (96.5, 108.0, 0) # EN 上拉 + H['C603'] = (100.5, 108.0, 0) # EN 复位 RC，贴 U20.3 + H['R609'] = (87.5, 108.0, 0) # PRSNT4# + H['R608'] = (89.75, 108.0, 0) # PRSNT3# + H['R607'] = (92.0, 108.0, 0) # PRSNT2# + H['R606'] = (94.25, 108.0, 0) # PRSNT1# + H['R610'] = (82.0, 95.0, 0) # PRSNT5#，贴 U20 西侧 pin22 + H['R604'] = (90.0, 85.5, 0) # INT# 上拉 + H['R605'] = (92.5, 85.5, 0) # INA_ALERT 上拉 + H['R611'] = (95.0, 85.5, 0) # MUX_RST# 上拉 + H['R710'] = (102.0, 65.5, 0) # U32 strap 电阻列 + H['R711'] = (102.0, 67.0, 0) + H['R712'] = (102.0, 68.5, 0) + H['R720'] = (102.0, 70.0, 0) + H['R716'] = (102.0, 72.0, 0) # HUB_RST 上拉 + H['C604'] = (104.0, 42.0, 0) # U35 VCC 去耦 + H['R602'] = (104.0, 39.0, 0) # SDA 上拉 + H['R603'] = (104.0, 45.0, 0) # SCL 上拉 + H['C607'] = (98.0, 30.0, 0) # U6 电源去耦 + H['C610'] = (98.0, 19.0, 0) # U7 电源去耦 + H['R616'] = (103.0, 24.5, 0) # U7.16 的参考 RC + # USB2517I 的八颗 3V3_HUB 去耦沿 U32 右侧就近排列。 + H['C744'] = (97.0, 63.0, 0) + H['C745'] = (97.0, 64.5, 0) + H['C746'] = (97.0, 66.0, 0) + H['C747'] = (99.0, 66.0, 0) + H['C748'] = (99.0, 67.5, 0) + H['C749'] = (99.0, 69.0, 0) + H['C750'] = (99.0, 70.5, 0) + H['C751'] = (98.0, 74.0, 0) + # 北边只放两只风扇座。J33 是 ESP32 应急串口，用户在客户端定位到 + # 右板边侧向接插；这里按实测坐标固化，避免后续 --push 把它拉回北边。 + H['J27'] = (70.0, 118.5, 180) + H['J26'] = (83.0, 118.5, 180) + H['J33'] = (107.06, 76.83, 270) + H['D2'] = (76.5, 113.5, 180) + H['R755'] = (64.5, 113.5, 180) + H['R757'] = (68.0, 113.5, 180) + H['R753'] = (71.75, 113.5, 180) + H['R748'] = (81.25, 113.5, 180) + # 两路板温传感器放到最高热密度点： + # RT601 监测 Hub LDO U31（最坏约 0.71 W）；RT602 监测超额定的 DC-005/J1 接触热。 + H['RT601'] = (92.0, 24.5, 270) # pin1/NTC1 朝北，贴 U31 右侧 + H['RT602'] = (72.5, 10.0, 180) # pin1/NTC2 朝东，贴 J1 右侧 + H['U13'] = (19.0, 5.5, 0) # INA226 采样脚 8/9/10 朝上正对 Rs6 + # 北侧风扇小信号组：Q6 靠风扇 PWM 座，Q10 靠 U20 FAN_TACH_OUT。 + H['Q6'] = (72.5, 113.5, 180) + H['R733'] = (68.0, 113.5, 180) + H['R734'] = (76.0, 113.5, 180) + H['D2'] = (84.0, 113.5, 180) + H['R753'] = (78.5, 113.5, 180) + H['R748'] = (88.5, 113.5, 180) + H['Q10'] = (98.0, 114.5, 90) + H['R754'] = (91.5, 113.5, 180) + H['R755'] = (94.0, 113.5, 180) + H['R756'] = (96.5, 118.0, 180) + H['R757'] = (99.0, 118.0, 180) + H['R747'] = (101.5, 118.0, 180) # Q7 gate 网紧贴 Q7.1 + H['R748'] = (88.75, 113.5, 180) + H['R660'] = (101.0, 80.25, 180) # NTC1 上臂回到 U20 ADC 滤波组 + H['R661'] = (103.25, 80.25, 180) # NTC2 上臂 + H.update(USER_INPUT) + return H + + +# 西 → 东。见文件头第 2 条。 +# 南 → 北。`U32` rot=180 之后 USB1 在南、USB5 在北 ⇒ 位号顺序跟着来， +# 五对 D± 才不会互相交叉（见 hand() 里那段）。 +SLOT_ORDER = ['J38', 'J37', 'J36', 'J35', 'J34'] + + +def corridor_y(k): + u"""走廊 k（0 = 阵列最南那条）的中心 y。""" + c = B.corridor(k) + return round((c[1] + c[3]) / 2.0, 3) + + +# ── 分区：谁进哪个区（M9 新布局）────────────────────────────────────────── +# 纵向三条：西区（器件）/ 中区（槽体）/ 东区（12V）；横向两头：南带 / 北带（可放高件）。 +# ⇒ 器件只有三个去处：**西区**、**南带**、**北带**。东区留给 12V 铜，不放件。 +PAGE_REGION = { + 'A1-INPUT': 'input', 'A4-HUB': 'west', 'A5-SLOTS': 'slots', 'A5B-SLOTS': 'west', + 'A3-CTRL': 'west', 'A2-AUX': 'west', 'A6-FAN': 'fan', +} +REGION_OVERRIDE = { + 'J23': 'input', + 'J33': 'fan', +} +for _r in ('U29', 'Q3', 'R4', 'R5', 'R6', 'C11', 'R9A', 'R9B', 'R9C', 'R9D', 'R9E'): + REGION_OVERRIDE[_r] = 'west' +for _r in ('DZ1', 'C1', 'R1'): + REGION_OVERRIDE[_r] = 'west' +# 两颗 Buck 和储能：12V 从**东缘高速路的北头**过来 ⇒ 放北带东侧 +for _r in ('U19', 'U30', 'L2', 'L3', 'C8', 'C733', 'R706', 'R707', 'R2', 'R3'): + REGION_OVERRIDE[_r] = 'fan' +OVERFLOW = {'fan': 'west', 'west': 'fan', 'input': 'west'} + + +def regions(): + u"""排布器可用矩形。**东区不给**：那儿从 x=72 起全是 12V 铜墙和高速路。""" + k = EDGE_KEEP + return { + 'input': (k, k, B.BW - k, B.PROJ[0] - 0.2), + 'fan': (k, B.PROJ[1] + 0.2, B.BW - k, B.BH - k), + 'west': (B.EAST[0], B.PROJ[0] + 0.2, B.BW - k, B.PROJ[1] - 0.2), + } + + +# ── 数据 ───────────────────────────────────────────────────────────────── +def sizes(): + d = json.load(io.open(BBOX, encoding='utf-8')) + out = {} + for k, v in d.items(): + bw, bh = BODY.get(k, (0.0, 0.0)) + out[k] = (max(v['w'], bw, 0.6), max(v['h'], bh, 0.6)) + return out + + +def page_of(): + u"""{位号: 页名}，从原理图 BOM 反查。""" + bom = json.load(io.open(os.path.join(HERE, '_base_sch_bom.json'), encoding='utf-8')) + return {r['d']: pg for pg, rows in bom.items() for r in rows} + + +def net_pins(): + u"""{网名: [(位号, 脚号)]}，去掉 GND 这种到处都是的。""" + nets = json.load(io.open(NETS, encoding='utf-8')) + out = {} + for ref, pads in nets.items(): + for pn, net in pads: + if net: + out.setdefault(net, []).append((ref, str(pn))) + return out + + +BIG_NETS = {'GND', '+12V', '+3V3', '+5V', '+3V3_HUB'} + + +def peers(): + u"""{位号: [对端位号]}，只算「小网」（≤6 只脚），大网不带方向信息。""" + out = {} + for net, pins in net_pins().items(): + if net in BIG_NETS or len(pins) > 6: + continue + refs = sorted(set(r for r, _ in pins)) + for a in refs: + out.setdefault(a, []).extend(b for b in refs if b != a) + return out + + +def wh(ref, rot, sz): + w, h = sz[ref] + return (h, w) if rot % 180 else (w, h) + + +def body_rect(ref, x, y, rot, sz): + u"""本体矩形（板坐标）。偏移要跟着 rot 转 —— 不转的话 DC 座的桶身会算到反方向去。""" + w, h = wh(ref, rot, sz) + ox, oy = BODY_OFF.get(ref, (0.0, 0.0)) + t = math.radians(rot % 360) + dx = ox * math.cos(t) - oy * math.sin(t) + dy = ox * math.sin(t) + oy * math.cos(t) + cx, cy = x + dx, y + dy + return (cx - w / 2, cy - h / 2, cx + w / 2, cy + h / 2) + + +def height(ref): + return HEIGHT.get(ref, H_DEFAULT) + + +def overlaps(r, rects): + for q in rects: + if r[0] < q[2] and q[0] < r[2] and r[1] < q[3] and q[1] < r[3]: + return True + return False + + +def blockers(sz): + u"""固定障碍：四个螺钉头避让圈 + 板角 R5 之外的地方 + `U20` 的天线净空。""" + out = [] + k = B.HOLE_KEEP + for _n, (hx, hy) in B.MOUNT_HOLES.items(): + out.append((hx - k, hy - k, hx + k, hy + k)) + # ESP32 天线净空（跟着 rot 转；rot=90 时在模组**西边**，正对板框缺口） + out.append(antenna_keepout(sz)) + # ⛔ 12V 母线 + D± 扇出带是摆位禁区。往母线上塞件，铜面被挖成细条而断面校核 + # 只看得到「有铜」；往扇出带塞件，五对 D± 直接布不出来。 + # ⚠ 缺口不只是「不许压上去」：那儿没板材，件还要离**新的板边** EDGE_KEEP + n = B.notch_rect() + out.append((n[0] - EDGE_KEEP, n[1] - EDGE_KEEP, n[2] + EDGE_KEEP, n[3] + EDGE_KEEP)) + out += list(B.keepout_rects()) + return out + + +ANT_LEN = 7.5 # 天线段：本体 25.5 − (焊盘框 19.0 − 每边出脚 0.5) = 7.0，留 0.5 +ANT_SIDE = 0.5 # 天线两侧各留 + + +def antenna_keepout(sz): + u"""`U20` 天线净空：两层都不许铺铜、不许走线、不许放件。 + + ⛔ **必须跟着 rot 转**。天线在封装的 +y 那一头；rot 是 CCW ⇒ 90° 之后朝西。 + 写死成「焊盘北沿之外那一块」的下场：模组转过去了、净空还留在北边， + 于是铺铜照样把铜铺到天线底下 —— 而摆位自检 / DRC / 几何校验**一条都不会响** + （这一版就是这么来的：模组在板中央、天线尖前 1 mm 一整块地平面）。 + """ + ax, ay, rot = hand()['U20'] + w, h = wh('U20', rot, sz) + r = int(round(rot)) % 360 + if r == 0: # 天线朝北 + return (ax - w / 2 - ANT_SIDE, ay + h / 2, + ax + w / 2 + ANT_SIDE, ay + h / 2 + ANT_LEN) + if r == 90: # 天线朝西 + return (ax - w / 2 - ANT_LEN, ay - h / 2 - ANT_SIDE, + ax - w / 2, ay + h / 2 + ANT_SIDE) + if r == 180: # 天线朝南 + return (ax - w / 2 - ANT_SIDE, ay - h / 2 - ANT_LEN, + ax + w / 2 + ANT_SIDE, ay - h / 2) + if r == 270: # 天线朝东 + return (ax + w / 2, ay - h / 2 - ANT_SIDE, + ax + w / 2 + ANT_LEN, ay + h / 2 + ANT_SIDE) + raise ValueError(u'U20 只支持 0/90/180/270，拿到 %s' % rot) + + +# ── 排布 ───────────────────────────────────────────────────────────────── +# ── 外围件的「紧迫度」与目标脚（2026-09-09 用户提出：外围器件摆放不合理）────── +# ⛔ 原来的顺序是**按面积从大到小**，于是直立电解 / 电感 / 座子先把 IC 周围的空位抢光， +# 0402 的去耦最后只能落在 20 mm 外。实测 `U32` 那一窝：30 件平均离芯片 **21.2 mm**， +# 22 件 > 15 mm —— 晶振负载电容 `C740/C741` 拉到 **17~18 mm**（起振风险）， +# `+3V3_HUB` 八颗去耦 20~28 mm（等于没有去耦）。 +# 这类错 **DRC 不报、几何自检不报、布线器只会报「出不来」**（症状不是病因）。 +# ⇒ 改成按「离得越近越要紧」分级摆，并且目标点取**它自己那只脚**而不是芯片质心。 +CLS_XTAL, CLS_DECAP, CLS_NEAR, CLS_REST = 0, 1, 2, 3 +CLS_MAX = {CLS_XTAL: 5.0, CLS_DECAP: 4.0, CLS_NEAR: 20.0, CLS_REST: 1e9} +PLANE_NETS = ('GND',) +BIG_NETS = ('+3V3', '+12V', '+5V', '+3V3_HUB') # 遍布全板，不能当「对端脚」看 + + +def _pad_index(): + u"""{位号: [(网, x, y), …]}，从 `_base_pads.json` 读。手排的 IC 不动， + 所以它们的脚坐标在重排之间是稳定的 —— 这正是我们要瞄的目标。""" + out = {} + try: + d = json.load(io.open(PADS, encoding='utf-8')) + except Exception: + return out + for p in d: + if p[7]: + out.setdefault(p[0], []).append((p[7], p[2], p[3])) + return out + + +def sat_class(ref, px): + u"""这件有多「怕远」。""" + nets = set(n for n, _x, _y in px.get(ref, [])) + if any(n.startswith('XTAL') for n in nets): + return CLS_XTAL + if len(px.get(ref, [])) <= 2 and 'GND' in nets and len(nets) == 2: + return CLS_DECAP + return CLS_NEAR if nets else CLS_REST + + +def sat_target(ref, px, pos, sz): + u"""目标点 = **同网对端芯片上那只脚**（不是芯片质心）。 + + 去耦要贴的是电源脚，不是芯片中心；QFN 四条边都有脚时这两者能差 5 mm 以上。 + """ + nets = [n for n, _x, _y in px.get(ref, []) if n not in PLANE_NETS] + small = [n for n in nets if n not in BIG_NETS] or nets + best = None + for other, lst in px.items(): + if other == ref or other not in pos: + continue + if sz.get(other, (0, 0))[0] * sz.get(other, (0, 0))[1] <= 12.0: + continue # 只认芯片当锚 + for n, x, y in lst: + if n in small: + pri = 0 if n not in BIG_NETS else 1 + if best is None or pri < best[0]: + best = (pri, x, y) + return (best[1], best[2]) if best else None + + +def target_point(ref, pr, pos, sz, fallback): + u"""目标点 = 已定位的对端件的质心（有芯片对端时只认芯片）。""" + ps = [p for p in pr.get(ref, []) if p in pos] + if not ps: + return fallback + chips = [p for p in ps if sz.get(p, (0, 0))[0] * sz.get(p, (0, 0))[1] > 12.0] + use = chips or ps + return (sum(pos[p][0] for p in use) / len(use), sum(pos[p][1] for p in use) / len(use)) + + +def plan(): + sz = sizes() + pg = page_of() + pos = dict(hand()) + # 非手排件使用旋转前已通过碰撞检查的布局做水平镜像， + # 保留原理图页的功能聚类，不让通用排布器把模块重新打散。 + if B.SLOT_ROT == 0 and os.path.exists(PRE_FLIP_POS): + old = json.load(io.open(PRE_FLIP_POS, encoding='utf-8')) + for ref, v in old.items(): + if ref in sz and ref not in pos: + pos[ref] = (round(B.BW - float(v[0]), 3), float(v[1]), + (180 - int(round(v[2]))) % 360) + live_layout = os.path.exists(LIVE_POS_JSON) + if live_layout: + live = json.load(io.open(LIVE_POS_JSON, encoding='utf-8')) + for ref, v in live.items(): + if ref in sz: + pos[ref] = (float(v[0]), float(v[1]), int(round(v[2])) % 360) + pos.update(ROUTE_FIX) + rects = list(blockers(sz)) + for ref, (x, y, r) in pos.items(): + w, h = wh(ref, r, sz) + rects.append((x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2)) + + R = regions() + todo = {} + for ref in sz: + if ref in pos: + continue + reg = REGION_OVERRIDE.get(ref) or PAGE_REGION[pg[ref]] + todo.setdefault(reg, []).append(ref) + + pr = peers() + px = _pad_index() + unplaced = [] + order = ['input', 'west', 'fan'] # M9 只有三个可放件的区 + for reg in order: + # ⛔ 顺序有两条，缺一不可： + # ① **锚（芯片/电感/座子这些大件）必须排在它的卫星件前面**。 + # 反了的话，摆卫星件时锚还不在板上，目标点退回「区中心」—— + # 实测 `C8`（Buck 输出电容）因此飞到离 `L2` **57.8 mm** 的地方， + # 一个开关电源的环路就这么散了，而没有任何一道检查会响。 + # ② 锚之后**按「怕远」的级别**排，再按面积。只按面积的下场： + # 大件先把 IC 周围抢光，0402 去耦落在 20 mm 外（`U32` 那一窝实测 21.2 mm）。 + def _ord(r): + big = sz[r][0] * sz[r][1] > 12.0 + return (0 if big else 1, 0 if big else sat_class(r, px), -sz[r][0] * sz[r][1], r) + + refs = sorted(todo.get(reg, []), key=_ord) + for ref in refs: + placed = False + chain = [reg] + nxt = OVERFLOW.get(reg) + while nxt and nxt not in chain: + chain.append(nxt) + nxt = OVERFLOW.get(nxt) + for rg in chain: + x0, y0, x1, y1 = R[rg] + w, h = sz[ref][0] + PACK_GAP, sz[ref][1] + PACK_GAP + t = (sat_target(ref, px, pos, sz) + or target_point(ref, pr, pos, sz, ((x0 + x1) / 2.0, (y0 + y1) / 2.0))) + best = None + yy = y0 + while yy + h <= y1 + 1e-9: + xx = x0 + while xx + w <= x1 + 1e-9: + r = (xx, yy, xx + w, yy + h) + if not overlaps(r, rects): + cx, cy = xx + w / 2, yy + h / 2 + key = (math.hypot(cx - t[0], cy - t[1]), yy, xx) + if best is None or key < best[0]: + best = (key, r, cx, cy) + xx += STEP + yy += STEP + if best is not None: + _k, r, cx, cy = best + rects.append(r) + pos[ref] = (round(cx, 3), round(cy, 3), 0) + placed = True + break + if not placed: + unplaced.append((ref, reg)) + if not live_layout: + snap(pos, sz, rects) + nf = 0 if live_layout or B.SLOT_ROT == 0 else orient_sats(pos, px, sz) + if nf: + print(u'两脚件朝向：翻转 %d 件（信号脚朝锚、GND 脚朝外）' % nf) + return pos, rects, unplaced, sz + + +# ⛔ **插槽不许吸网格**：两列焊盘相距 7.2 mm（= 28.8 格），两列不可能同时落在 0.25 上， +# 而吸一下就把 20.32 的槽距打成 20.25/20.5 交替 —— 3D 打印导轨是按 20.32 等距做的。 +# ⇒ 槽距的精确值比焊盘对格重要，插槽整体排除。 +NO_SNAP = set(SLOT_ORDER) | {'J33'} | set(USER_INPUT) + + +def snap(pos, sz, rects): + u"""把件吸到 0.25 布线网格上；破了 GAP 的退回去（刀片 M7 §27.9 的做法）。""" + before = dict(pos) + for ref, (x, y, r) in list(pos.items()): + if ref in NO_SNAP: + continue + pos[ref] = (round(round(x / SNAP) * SNAP, 3), round(round(y / SNAP) * SNAP, 3), r) + for _ in range(6): + bad = set() + items = sorted(pos) + for i, a in enumerate(items): + wa, ha = wh(a, pos[a][2], sz) + ra = (pos[a][0] - wa / 2, pos[a][1] - ha / 2, pos[a][0] + wa / 2, pos[a][1] + ha / 2) + for b in items[i + 1:]: + wb, hb = wh(b, pos[b][2], sz) + rb = (pos[b][0] - wb / 2, pos[b][1] - hb / 2, pos[b][0] + wb / 2, pos[b][1] + hb / 2) + if ra[0] < rb[2] + GAP and rb[0] < ra[2] + GAP and \ + ra[1] < rb[3] + GAP and rb[1] < ra[3] + GAP: + bad.add(a if pos[a] != before[a] else b) + bad = {r for r in bad if pos[r] != before[r]} + if not bad: + break + for ref in bad: + pos[ref] = before[ref] + return pos + + +# ── 自检 ───────────────────────────────────────────────────────────────── +def selfcheck(pos, unplaced, sz): + bad = [] + if unplaced: + bad.append(u'排不下 %d 件: %s' % (len(unplaced), ' '.join(r for r, _ in unplaced))) + items = sorted(pos) + keep = antenna_keepout(sz) + for i, a in enumerate(items): + x, y, r = pos[a] + w, h = wh(a, r, sz) + # 板内 + 离板边。⚠ 接口件本体越过板边是对的，改判「够得着板边」 + if a in EDGE_PARTS: + br = body_rect(a, x, y, r, sz) + if abs(br[1]) > 1.0: + bad.append(u'%s 是接口件，本体南沿 y=%.2f 没贴到板边（差 %.2f）' + % (a, br[1], abs(br[1]))) + if not (EDGE_KEEP - 0.01 <= x - w / 2 and x + w / 2 <= B.BW - EDGE_KEEP + 0.01): + bad.append(u'%s 东西向出板: x=%.2f w=%.2f' % (a, x, w)) + edge_keep = 0.25 if a in USER_INPUT else EDGE_KEEP + if a not in EDGE_PARTS and not ( + edge_keep - 0.01 <= x - w / 2 and x + w / 2 <= B.BW - edge_keep + 0.01 and + edge_keep - 0.01 <= y - h / 2 and y + h / 2 <= B.BH - edge_keep + 0.01): + bad.append(u'%s 出板或贴边: (%.2f,%.2f) %.2fx%.2f' % (a, x, y, w, h)) + # ⛔ ESP32 天线缺口那一块**没有板材**：谁伸进去谁悬空 + # （`U20` 除外 —— 它的天线本来就该悬在那儿，这是这个缺口存在的理由） + if a != 'U20': + nk = B.notch_rect() + if (x + w / 2 > nk[0] - EDGE_KEEP + 0.01 and x - w / 2 < nk[2] + EDGE_KEEP - 0.01 and + y + h / 2 > nk[1] - EDGE_KEEP + 0.01 and y - h / 2 < nk[3] + EDGE_KEEP - 0.01): + bad.append(u'%s 伸进了 ESP32 天线缺口（那儿没板材）: (%.2f,%.2f)' % (a, x, y)) + # 刀片投影内不许放高件（硬碰撞） + if not B.height_ok(y, height(a), x): + bad.append(u'%s 高 %.1f mm 落在刀片投影 y=%.1f 上（上限 %.0f）' + % (a, height(a), y, B.H_PROJ)) + # 螺钉头 + for n, (hx, hy) in B.MOUNT_HOLES.items(): + if abs(x - hx) < w / 2 + B.HOLE_KEEP and abs(y - hy) < h / 2 + B.HOLE_KEEP: + bad.append(u'%s 压在螺钉 %s 的头下' % (a, n)) + # 天线净空 + if x + w / 2 > keep[0] and keep[2] > x - w / 2 and y + h / 2 > keep[1] and keep[3] > y - h / 2: + if a != 'U20': + bad.append(u'%s 进了 U20 的天线净空' % a) + # ⛔ 谁都不许压在槽体上，也不许进 D± 竖向通道 + if a not in SLOT_ORDER: + # ⚠ 循环变量不能叫 i —— 外面那层 `enumerate(items)` 也在用 i， + # 覆盖掉之后 `items[i+1:]` 就错位了（现象是「C736 与 C736 挨太近」）。 + for si in range(1, B.SLOT_N + 1): + b0, b1, b2, b3 = B.slot_body(si) + if x + w / 2 > b0 and b2 > x - w / 2 and y + h / 2 > b1 and b3 > y - h / 2: + bad.append(u'%s 压在槽 %d 的槽体上' % (a, si)) + d = B.DP_CHAN + if a != 'U13' and x + w / 2 > d[0] and d[2] > x - w / 2 and \ + y + h / 2 > d[1] and d[3] > y - h / 2: + bad.append(u'%s 进了 D± 竖向通道 x %.0f~%.0f' % (a, d[0], d[2])) + d = B.USB6_CHAN + if a not in ('U20', 'U32') and x + w / 2 > d[0] and d[2] > x - w / 2 and \ + y + h / 2 > d[1] and d[3] > y - h / 2: + bad.append(u'%s 进了 U32→U20 的 USB6 专用通道' % a) + for b in items[i + 1:]: + x2, y2, r2 = pos[b] + ra = body_rect(a, x, y, r, sz) + rb = body_rect(b, x2, y2, r2, sz) + if ra[0] < rb[2] + GAP and rb[0] < ra[2] + GAP and \ + ra[1] < rb[3] + GAP and rb[1] < ra[3] + GAP: + bad.append(u'%s 与 %s 挨太近（净距 < %.1f）' % (a, b, GAP)) + return bad + + +# ── 下发 / 读回 ─────────────────────────────────────────────────────────── +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + + +def call(js, timeout=300): + r = run(OPEN + js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:700]) + sys.exit(1) + return r['result'] + + +def push(pos): + arr = [[k, round(v[0] * MIL, 4), round(v[1] * MIL, 4), v[2]] for k, v in sorted(pos.items())] + r = call(""" +const P = %s; +const by = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) by[c.designator] = c; +let k = 0, miss = []; +for (const [d, x, y, rot] of P) { + const c = by[d]; + if (!c) { miss.push(d); continue; } + await eda.pcb_PrimitiveComponent.modify(c.getState_PrimitiveId(), + {x: x, y: y, rotation: rot}); + k++; +} +await eda.pcb_Document.save(); +return {moved: k, miss: miss}; +""" % json.dumps(arr), timeout=600) + print(u'摆位下发 %d 件%s' % (r['moved'], (u'；板上没有: %s' % r['miss']) if r['miss'] else u'')) + return r + + +def rotate_slots_only(): + u"""只旋转 J34~J38，不触碰其他 133 件。用于机械朝向已确定后的定点修改。""" + refs = SLOT_ORDER + js = u""" +const refs=%s, out={}, by={}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) by[c.designator]=c; +for (const ref of refs) { + const c=by[ref]; + if (!c) { out[ref]='missing'; continue; } + // modify() 会把数值 0 当成“未传”；传 360 由客户端归一到 0°。 + await eda.pcb_PrimitiveComponent.modify(c.getState_PrimitiveId(), {rotation:%d}); +} +await eda.pcb_Document.save(); +for (const ref of refs) { + const c=by[ref]; + out[ref]=c ? ((c.rotation||0)%%360) : 'missing'; +} +return out; +""" % (json.dumps(refs), 360 if B.SLOT_ROT == 0 else B.SLOT_ROT) + got = call(js, timeout=300) + bad = [r for r in refs if got.get(r) != B.SLOT_ROT] + print(u'插槽旋转读回: %s' % ' '.join('%s=%s°' % (r, got.get(r)) for r in refs)) + if bad: + raise SystemExit(u'插槽旋转未生效: ' + ' '.join(bad)) + dump_pads() + counts = call("return {lines:(await eda.pcb_PrimitiveLine.getAll()||[]).filter(x=>x.layer===1||x.layer===2).length," + "vias:(await eda.pcb_PrimitiveVia.getAll()||[]).length," + "pours:(await eda.pcb_PrimitivePour.getAll()||[]).length};") + print(u'底板铜图元: 导线 %(lines)d / 过孔 %(vias)d / 铜面 %(pours)d' % counts) + + +BBOX_JS = u""" +const MIL = %s; +const out = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + let x0=1e9, y0=1e9, x1=-1e9, y1=-1e9; + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let poly = false; + if (String(pad[0])==='POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v=>typeof v==='number'); + let mnx=1e9,mny=1e9,mxx=-1e9,mxy=-1e9; + for (let k=0;k+1 45 && prot < 135) { const t=w; w=h; h=t; } + x0=Math.min(x0,p.x-w/2); x1=Math.max(x1,p.x+w/2); + y0=Math.min(y0,p.y-h/2); y1=Math.max(y1,p.y+h/2); + } + out[c.designator] = {n: ps.length, w: (x1-x0)/MIL, h: (y1-y0)/MIL, rot: c.rotation, + fp: (c.footprint && c.footprint.name) ? c.footprint.name : c.footprint}; +} +return out; +""" % MIL + + +def dump_bbox(): + u"""抓封装外框 → `_base_bbox.json`。 + + ⛔ **必须按 rot 反转回封装自身的朝向**：板上读回来的是**板坐标**的外框， + 件转了 90° 之后 42×9.2 会记成 9.2×42。而 `wh()` 又会按 rot 再转一次 —— + 转两次等于没转，自检立刻报「插槽互相重叠 / 出板」。 + （第一版就是这么翻车的：摆位下发之后重抓一次 bbox，五个插槽全变成 44×7.9。） + """ + d = call(BBOX_JS, timeout=600) + for k, v in d.items(): + if int(v.get('rot') or 0) % 180 == 90: + v['w'], v['h'] = v['h'], v['w'] + v['w'] = round(v['w'], 3) + v['h'] = round(v['h'], 3) + io.open(BBOX, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False, indent=0)) + print(u'已写 _base_bbox.json：%d 件（已按 rot 反转回封装朝向）' % len(d)) + return d + + +DUMP_JS = u""" +const MIL = %s; +const out = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let cx = p.x, cy = p.y, poly = false; + if (String(pad[0]) === 'POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v => typeof v === 'number'); + const pts = []; + for (let k=0; k+1q[1]))].sort((a,b)=>a-b); + for (let b2=0; b2+1a-b); + for (let k=0; k+1 45 && rot < 135) { const t=w; w=h; h=t; } + out.push([c.designator, String(p.padNumber), Math.round(cx/MIL*1000)/1000, + Math.round(cy/MIL*1000)/1000, Math.round(w/MIL*1000)/1000, + Math.round(h/MIL*1000)/1000, p.layer, p.net||'', String(pad[0])]); + } +} +return out; +""" % MIL + + +def dump_pads(): + d = call(DUMP_JS, timeout=600) + io.open(PADS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) + rots = call("const o={}; for (const c of await eda.pcb_PrimitiveComponent.getAll())" + " o[c.designator]=(c.rotation||0)%360; return o;") + io.open(ROT_JSON, 'w', encoding='utf-8').write( + json.dumps(rots, ensure_ascii=False, sort_keys=True)) + print(u'已写 _base_pads.json：%d 个焊盘' % len(d)) + return d + + +def dump_live_positions(): + u"""将 EasyEDA 当前底板布局固化为后续计算的最高优先级输入。""" + d = call("const o={}; for(const c of await eda.pcb_PrimitiveComponent.getAll())" + " o[c.designator]=[c.x/%s,c.y/%s,(c.rotation||0)%%360,c.layer]; return o;" + % (MIL, MIL)) + if len(d) != 138: + raise SystemExit(u'当前板上读到 %d 件，应为 138；拒绝覆盖 LIVE 快照' % len(d)) + out = {ref: [round(float(v[0]), 4), round(float(v[1]), 4), int(round(v[2])) % 360, v[3]] + for ref, v in sorted(d.items())} + io.open(LIVE_POS_JSON, 'w', encoding='utf-8').write( + json.dumps(out, ensure_ascii=False, indent=2)) + print(u'已采用 EasyEDA 当前布局：%d 件 → %s' % (len(out), LIVE_POS_JSON)) + return out + + +def verify(pos, sz): + u"""读回坐标逐件对账 + **三条朝向断言**（几何验证抓不到的那三条）。""" + d = dump_pads() + got = {} + for ref, pn, x, y, _w, _h, _lay, net, _sh in d: + got.setdefault(ref, {})[pn] = (x, y, net) + bad = [] + r = call("const o={}; for (const c of await eda.pcb_PrimitiveComponent.getAll())" + " o[c.designator]=[c.x/%s, c.y/%s, c.rotation]; return o;" % (MIL, MIL)) + for ref, (x, y, rot) in sorted(pos.items()): + if ref not in r: + bad.append(u'%s 板上没有' % ref) + continue + gx, gy, grot = r[ref] + if abs(gx - x) > 0.02 or abs(gy - y) > 0.02 or (grot or 0) % 360 != rot % 360: + bad.append(u'%s 读回 (%.2f,%.2f,%s) != (%.2f,%.2f,%s)' % (ref, gx, gy, grot, x, y, rot)) + + def pad(ref, pn): + return got.get(ref, {}).get(pn) + + # 断言 1：新分区里 U32 在东侧，下行口朝西对着槽阵。 + p1, p11 = pad('U32', '2'), pad('U32', '12') # USB1_DP / USB5_DP + if not p1 or not p11: + bad.append(u'U32 的 USB1_DP/USB5_DP 焊盘没读到') + else: + if p1[0] >= pos['U32'][0] or p11[0] >= pos['U32'][0]: + bad.append(u'U32 下行口没朝西（USB1_DP x=%.2f，芯片中心 x=%.2f）⇒ rot 反了' + % (p1[0], pos['U32'][0])) + if p1[1] <= p11[1]: + bad.append(u'U32 西排顺序不对：USB1 y=%.2f 应该在 USB5 y=%.2f 的**北**边' + % (p1[1], p11[1])) + # 断言 2：插槽经用户要求再转 180°，+12V 脚在西，D± 仍在长轴中部。 + for ref in SLOT_ORDER: + p2, p46, p47 = pad(ref, '2'), pad(ref, '46'), pad(ref, '47') # A2=+12V / B14,B15=D± + cx, cy = pos[ref][0], pos[ref][1] + if not p2 or not p46: + bad.append(u'%s 的 2/46 脚没读到' % ref) + continue + if p2[0] > cx: + bad.append(u'%s 的 +12V 脚（A2）在东边 x=%.2f，用户要求旋转后应在西 ⇒ 插槽应为 rot 0' + % (ref, p2[0])) + if abs(p46[0] - B.pin_x(-1.5)) > 1.0: + bad.append(u'%s 的 D± 不在长轴中部：x=%.2f，应 ≈%.1f' % (ref, p46[0], B.pin_x(-1.5))) + if abs(p46[0] - p47[0]) > 1.2 or abs(p46[1] - p47[1]) > 0.1: + bad.append(u'%s 的 D± 两只脚不在同一排' % ref) + # 断言 3：五对 D± 从 U32 到各槽**不交叉**（按 y 单调） + ys = [] + for i, ref in enumerate(SLOT_ORDER, start=1): + pn = {'J34': '2', 'J35': '4', 'J36': '7', 'J37': '9', 'J38': '12'}[ref] # U32 侧 DP 脚 + pu = pad('U32', pn) + ps = pad(ref, '46') + if pu and ps: + ys.append((pu[1], ps[1], ref)) + for a, b in zip(ys, ys[1:]): + if not (a[0] < b[0] and a[1] < b[1]): + bad.append(u'D± 扇出会交叉：%s(U32 y=%.2f→槽 y=%.2f) 与 %s(%.2f→%.2f)' + % (a[2], a[0], a[1], b[2], b[0], b[1])) + # 断言 4：`U20` 的天线朝**东**且整段落在板框缺口里 + # ⛔ 这一条是 2026-09-09 补的：天线朝向 rot 一改就全变，而 + # 摆位自检只看焊盘外框（19×19，天线那 7 mm 根本不在模型里）、 + # DRC 只看铜、`board_check` 只看连通性 —— 没有一道能看出天线埋在板里。 + # 判据用**板上读回的焊盘**：pin1 / pin40 是紧挨天线那一头的两只脚。 + pa, pb = pad('U20', '1'), pad('U20', '40') + if not pa or not pb: + bad.append(u'U20 的 1/40 脚没读到，天线朝向无法判定') + else: + mx, my = (pa[0] + pb[0]) / 2.0, (pa[1] + pb[1]) / 2.0 + cx, cy = pos['U20'][0], pos['U20'][1] + if mx < cx + 5.0: + bad.append(u'U20 天线没朝东：pin1/40 中点 x=%.2f，模组中心 x=%.2f ' + u'⇒ rot 不是 270 或 rot 语义相反' % (mx, cx)) + nk = B.notch_rect() + tip = mx + ANT_LEN + # tip = 天线尖；判据是「尖落在缺口的深度里 + 那一头的焊盘还在板上 + y 在缺口里」 + if not (nk[0] - 0.01 <= tip <= nk[2] + 0.01 and mx < nk[0] and + nk[1] <= my <= nk[3]): + bad.append(u'U20 天线尖 x=%.2f (y=%.2f) 没落在板框缺口 x %.1f~%.1f / y %.1f~%.1f 里 ' + u'⇒ 天线又埋回板子里了' % (tip, my, nk[0], nk[2], nk[1], nk[3])) + if bad: + print(u'[X] 读回校验 %d 条不过:' % len(bad)) + for t in bad[:25]: + print(u' ' + t) + else: + print(u'[OK] %d 件坐标/角度逐件对上；四条朝向断言全过' % len(pos) + + u'（U32 下行口朝西且 USB1 在北、插槽 +12V 在西 / D± 在长轴中部、' + u'五对 D± 不交叉、U20 天线朝东且落在板框缺口里）') + return bad + + +def orient_sats(pos, px, sz): + u"""两脚件的**朝向**：让信号脚朝着它的锚，GND 脚朝外。 + + ⛔ 2026-09-09 用户指出的 `R710/R711/R719/R720`（`U32` 西沿那四颗下拉）就是反的： + 信号脚在西、GND 脚在东 —— 信号要**绕过整个电阻体**才够得着芯片， + 而 GND 脚正横在中间。0402 只有 1 mm，可板上一共几十颗这样的件， + 每颗都逼布线器多绕一次、多占一格。 + **DRC 不报、几何自检不报、体检也不报**（距离没变），只有人眼看得出来。 + ⇒ 判据能算：两只脚里哪一只离锚近，就把它转到朝锚那一侧（只在 0/180 之间选， + 竖着摆的件在 90/270 之间选），不动位置。 + """ + n = 0 + try: + current_rot = json.load(io.open(ROT_JSON, encoding='utf-8')) + except Exception: + current_rot = {} + for ref, (x, y, rot) in list(pos.items()): + ps = px.get(ref) or [] + if len(ps) != 2: + continue + gnd = [q for q in ps if q[0] == 'GND'] + sig = [q for q in ps if q[0] != 'GND'] + if len(gnd) != 1 or len(sig) != 1: + continue + t = sat_target(ref, px, pos, sz) + if t is None: + continue + # 焊盘是板上**当前**姿态，而 pos 是本轮的计划坐标。偏移必须先相对 + # 板上两盘中心求，不能相对新坐标求；目标角度也要从板上当前角度推导。 + cx = (sig[0][1] + gnd[0][1]) / 2.0 + cy = (sig[0][2] + gnd[0][2]) / 2.0 + ds = (sig[0][1] - cx, sig[0][2] - cy) + d_now = math.hypot(x + ds[0] - t[0], y + ds[1] - t[1]) + d_flip = math.hypot(x - ds[0] - t[0], y - ds[1] - t[1]) + base = int(round(current_rot.get(ref, rot))) % 360 + if d_flip < d_now - 0.05: + pos[ref] = (x, y, (base + 180) % 360) + n += 1 + else: + pos[ref] = (x, y, base) + return n + + +def report_sat(pos, sz): + u"""外围件体检：每颗芯片的卫星件离**它自己那只脚**有多远。 + + ⛔ 这一条是 2026-09-09 用户看出来的：`U32` 那一窝 30 件平均 **21.2 mm**、 + 22 件 > 15 mm，晶振负载电容拉到 17~18 mm（起振风险）。 + **DRC 不报、几何自检不报、布线器只报「出不来」**（症状不是病因）， + 所以判据必须固化在这里，每次摆位都打出来。 + """ + px = _pad_index() + hd = set(hand()) + chips = [r for r in pos if sz.get(r, (0, 0))[0] * sz.get(r, (0, 0))[1] > 12.0] + print(u'') + print(u'外围件体检（卫星件 → 它自己那只脚的距离）:') + nm = {CLS_XTAL: u'晶振类', CLS_DECAP: u'去耦/两脚', CLS_NEAR: u'一般外围'} + rows = [] + for ref, (x, y, _r) in pos.items(): + if ref in hd or ref not in px or len(px[ref]) > 4: + continue + c = sat_class(ref, px) + if c == CLS_REST: + continue + t = sat_target(ref, px, pos, sz) + if t is None: + continue + # ⚠ 只在**同一个带**里比才有意义：风扇带的件离 `U20` 90 mm 是对的 + # （它是风扇块的件），拿来当「摆得不合理」是误报。 + own = _owner(ref, px, pos, sz) + if own is None or B.zone_of(pos[own][1]) != B.zone_of(y): + continue + rows.append((c, math.hypot(x - t[0], y - t[1]), ref)) + for c in (CLS_XTAL, CLS_DECAP, CLS_NEAR): + v = sorted(t for t in rows if t[0] == c) + if not v: + continue + over = [t for t in v if t[1] > CLS_MAX[c]] + print(u' %-9s %2d 件 平均 %5.1f 最远 %5.1f(%s) 超 %.0f mm 的 %d 件%s' + % (nm[c], len(v), sum(t[1] for t in v) / len(v), v[-1][1], v[-1][2], + CLS_MAX[c], len(over), + u': ' + u' '.join('%s(%.0f)' % (t[2], t[1]) for t in over[:8]) if over else u'')) + print(u' 按芯片看（卫星件的平均距离）:') + for ch in sorted(chips): + v = [d for c, d, r in rows + if sat_target(r, px, pos, sz) and _owner(r, px, pos, sz) == ch] + if v: + print(u' %-6s %2d 件 平均 %.1f mm 最远 %.1f' % (ch, len(v), sum(v) / len(v), max(v))) + + +def _owner(ref, px, pos, sz): + u"""这件的「主人」芯片（同网、非平面网、面积够大的那颗，最近的一只脚）。""" + nets = [n for n, _x, _y in px.get(ref, []) if n not in PLANE_NETS] + small = [n for n in nets if n not in BIG_NETS] or nets + best = None + for other, lst in px.items(): + if other == ref or other not in pos: + continue + if sz.get(other, (0, 0))[0] * sz.get(other, (0, 0))[1] <= 12.0: + continue + for n, x, y in lst: + if n in small: + d = math.hypot(pos[ref][0] - x, pos[ref][1] - y) + if best is None or d < best[0]: + best = (d, other) + return best[1] if best else None + + +def report(pos, sz): + print(u'') + print(u'带内件数:') + cnt = {} + for ref, (x, y, _r) in pos.items(): + cnt.setdefault(B.zone_of(y) or '?', []).append(ref) + for k in ('input', 'array', 'fan'): + v = cnt.get(k, []) + z = B.ZONES[k] + area = (z[2] - z[0]) * (z[3] - z[1]) + used = sum(sz[r][0] * sz[r][1] for r in v) + print(u' %-6s %3d 件 焊盘外框 %5.0f / %5.0f mm² (%.0f%%)' + % (k, len(v), used, area, 100.0 * used / area)) + print(u'') + print(u'插槽（南 → 北）与走廊:') + for i, ref in enumerate(SLOT_ORDER, start=1): + print(u' 槽%d %s y=%.2f 南侧走廊中心 y=%.2f / 北侧 %.2f' + % (i, ref, pos[ref][1], corridor_y(i - 1), corridor_y(i))) + print(u'') + print(u'D± 估算长度（曼哈顿，U32 西排 → 走廊 → 槽针 x=%.1f）:' % B.pin_x(-1.5)) + ux, uy = pos['U32'][0] - sz['U32'][0] / 2, pos['U32'][1] + for i in range(1, B.SLOT_N + 1): + ref = B.USB_SLOT_REF[i] + sy = pos[ref][1] - B.PAD_ROW_DY + L = abs(B.pin_x(-1.5) - ux) + abs(sy - uy) + print(u' USB%d %s ≈ %.0f mm' % (i, ref, L)) + + +if __name__ == '__main__': + if '--slots-only' in sys.argv: + rotate_slots_only() + sys.exit(0) + if '--bbox' in sys.argv: + dump_bbox() + sys.exit(0) + if '--dump' in sys.argv: + dump_pads() + sys.exit(0) + if '--adopt-live' in sys.argv: + dump_live_positions() + pos, rects, unplaced, sz = plan() + bad = selfcheck(pos, unplaced, sz) + print(u'底板摆位：%d 件（手排 %d + 排布 %d）' % (len(pos), len(hand()), len(pos) - len(hand()))) + if bad: + print(u'[X] 自检 %d 条不过:' % len(bad)) + for t in bad[:30]: + print(u' ' + t) + else: + print(u'[OK] 自检全过（不出板 / 不重叠 / 投影带限高 / 螺钉头 / 槽带空 / 天线净空）') + report(pos, sz) + report_sat(pos, sz) + io.open(POS_JSON, 'w', encoding='utf-8').write( + json.dumps({k: list(v) for k, v in pos.items()}, ensure_ascii=False, indent=0)) + if '--push' in sys.argv: + if bad: + print(u'!! 自检不过，不下发') + sys.exit(1) + push(pos) + verify(pos, sz) + elif '--verify' in sys.argv: + verify(pos, sz) diff --git a/.claude/r2/archive_base2L/pour_base.py b/.claude/r2/archive_base2L/pour_base.py new file mode 100644 index 0000000..4ae878d --- /dev/null +++ b/.claude/r2/archive_base2L/pour_base.py @@ -0,0 +1,889 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 的缝合过孔 + 铺铜 + 断面校核（M8e）。 + + /c/Python314/python .claude/r2/pour_base.py # 只算 + 自检 + 断面校核 + /c/Python314/python .claude/r2/pour_base.py --stitch # 打 GND 缝合过孔 + /c/Python314/python .claude/r2/pour_base.py --push # 清旧铜面 + 重建 + 重填 + /c/Python314/python .claude/r2/pour_base.py --rebuild # 只重填 + +⛔ **顺序**（刀片 M7 §27.10 的结论，两层板同样成立）： + 摆位 → 布线 → 下发 → **缝合过孔** → 斜切 → **铺铜**。 + 重跑布线器要把缝合过孔和斜切一起重跑。 + +## 叠层（方案 §6.1） + +| 设计 | EasyEDA | id | 内容 | +|---|---|---|---| +| L1 | Top Layer | 1 | 全部元件 + 全部信号 + 12V 宽铜 + GND 底填 | +| L2 | Bottom Layer | 2 | **完整地平面**（D± 走廊下方一刀不许割，§6.2 第 1 条）| + +## 两个只有这块板才有的约束 + +1. **`U20` 天线净空**：ESP32-S3-WROOM-1 的天线那一头（焊盘北沿外 7.5 mm） + **两层都不许有铜**。铜面不能带洞（`createComplexPolygon` 传多个环会把客户端挂死， + 刀片 §24 的坑），⇒ 用**若干块单环矩形**绕开它，同网接壤会自然连成一片。 +2. **入口链 9 A 靠铺铜**：`VIN_RAW`/`VIN_FUSED`/`VIN_SW`/`+12V` 在 input 带里各自 + 铺一块顶层铜（优先级比 GND 高，先占地盘），断面要 ≥ 方案 §6.4 的要求。 + ⚠ 这四个是**串联的四段**，不是一个网 —— 每段各铺各的，中间隔着 F1 / Q1 / Rs6。 + +## 断面校核（`--cuts`，办法沿用 R1 `pcb1_pour.py`） + +在铺铜上画一条断面线，数「这条线上属于本网、且没有被别人的焊盘/过孔/导线占掉」的 +长度。⚠ 它算的是**计划的铜面**，不是板上填出来的铜 —— 填的时候还会被反焊盘再吃掉一点， +所以判据留了 15% 余量。真正的判据仍是「铺完截图 + DRC」。 +""" +import io +import json +import math +import os +import sys +import time + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 +import place_base as PL # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +L_TOP, L_BOT = 1, 2 + +INSET = 0.5 # 铜面离板边 +CLR = 0.25 # 断面校核里别人的铜要让开多少 +VIA_D, VIA_HOLE = 0.6, 0.3 +STITCH_PITCH = 4.0 +STITCH_CLR = 0.5 # 缝合过孔到任何焊盘 / 导线的净距 +PADS = os.path.join(HERE, '_base_pads.json') +ROUTES = os.path.join(HERE, '_base_routes.json') +ROUTE_SCHEMA = 7 + +# 入口链四段的铺铜：从各自的焊盘外框算，不手抄坐标（摆位一改就跟着走） +POWER_NETS = [('VIN_RAW', 1), ('VIN_FUSED', 2), ('VIN_SW', 3)] +# ⚠ `+12V` **不按焊盘外框算** —— 它不是入口链里的一段，是遍布全板的母线。 +# 三段几何写在 `pcb_base.BUS_IN/BUS_UP/BUS_SLOT`（那里是唯一事实来源， +# `place_base` 也拿它当摆位禁区）。 +# ⛔ 入口链的铜只能从 y=6.3 往上：**输入带最南那 5 mm 归 12V 横脊**（`pcb_base.SPINE`）。 +# 两者同层不同网，搭上就把 `Rs6` 短路了。 +# M9：南带整条都归入口链（横脊没了 —— 12V 不再需要穿过 D±，它全在东缘） +POWER_BAND = (0.0, 0.8, B.BW, B.ZONES['input'][3]) +POWER_GROW = {'VIN_RAW': 1.2, 'VIN_FUSED': 1.2, 'VIN_SW': 1.2} + +# Q1 栅极网络（DZ1 钳位 / C1 栅源电容 / R1 下拉）。它们的焊盘**不撑大**入口链铜面 +# （和 U13.10 同理：不是 9 A 主电流焊盘），而且整团从铜面里挖出一个缺口给 GATE 走线。 +# ⛔ 不挖的话 Q1.4 北、西、南三面是 VIN_FUSED、东面是 VIN_SW，中间只剩 0.25 mm 的缝 —— +# 布线器报「GATE: Q1.4 出不来」，看着像拥塞，其实是铜面把栅极脚封死了。 +GATE_PARTS = ('DZ1', 'C1', 'R1') +NOTCH_CLR = 0.3 # 缺口在 GATE 焊盘外框外再让多少 +NOTCH_HEAD = 1.5 # 缺口在栅极件北侧留多高：GATE 要从 C1 北边绕过去 + +# 落在硬功率铜面里 / GATE 缺口里的 **GND 贴片焊盘**：(位号, 脚, 过孔在哪一侧, 是否挖地岛)。 +# ⛔ GND 不走线、只靠铺铜 + 过孔。这几只脚四周全是 VIN_SW 铜（或是缺口里的一小块孤立地铜）， +# 没有专用过孔的话它们根本接不到地 —— D1 是 TVS，浪涌电流全靠这一只脚回地。 +# 通孔地脚（C2/C3 的电解、J1）自己穿到底层地平面，不在此列。 +# 地岛从铜面里挖一条缝通到铜面外（S = 向南到板边，N = 向北出 VIN_SW 顶边），过孔排在开口那一侧。 +GND_PAD_VIAS = [('D1', '2', 'S', True), ('C5', '1', 'N', True), ('R1', '1', 'N', False)] +ISL_M = 0.6 # 地岛在焊盘外框外让多少 +ISL_VIA_GAP = 0.25 # 过孔铜边到焊盘边（别让焊锡流进孔里） +ISL_VIA_PITCH = 0.9 # 同排过孔中心距（≥ 0.6 的同网孔距） + +# 断面校核（方案 §6.4）。入口链电流方向是 +x ⇒ 断面是**竖直**的，量 y 方向的净铜高， +# 而且要取沿途的**最小值**（第一版取了最大值，等于没查）。 +# (名字, 网, 是否强制) +# (铜面名, 标签, 网, 沿哪个轴流 'x'/'y', 要求净铜, 是否强制) +CUTS = [ + ('PWR-VIN_RAW', u'J1→F1 入口', 'VIN_RAW', 'x', 8.0, False), + ('PWR-VIN_FUSED', u'F1→Q1', 'VIN_FUSED', 'x', 8.0, False), + # ⚠ `VIN_SW` 的最窄点在 `Rs6`/`U13` 那一头（Kelvin 要求它们贴在一起）。 + # 6.5 mm 在 9 A 下 ΔT≈25 K 而不是 20 K，只有分流电阻前后 2~3 mm 一小段，可接受。 + ('PWR-VIN_SW', u'Q1→储能→Rs6', 'VIN_SW', 'x', 6.5, True), + # 西缘高速路的电流是**沿 y** 流的 ⇒ 断面是水平的，量 x 方向净铜宽。 + # 写成 'x' 的话量到的是它 105 mm 的长度，永远「通过」，等于没查。 + ('PWR-12V-0', u'12V 西缘高速路', '+12V', 'y', 8.0, True), +] +CUT_MIN_W = 8.0 # IPC-2221 1 oz 外层 9 A ΔT20K ⇒ ≥8 mm 净铜宽 + +# ── 低压轨的「软铺铜」（2026-09-09 用户拍板：先按分布把电源网铺铜）──────────── +# ⛔ **为什么单独一类、名字不叫 `PWR-`**： +# `PWR-` 是**硬铺铜** —— 几何算出来、要过断面校核，而且会当障碍喂给布线器 +# （`route_base.pour_blocks()`），别的网一律不许穿过去。12V 母线被一根信号线 +# 切断 = 9 A 没了，而铺铜管理器 / DRC / 连通性三个都只说「有铜」。 +# `RAIL-` 是**软铺铜**：只是「这一带的余铜归这个网」，铺铜时自然绕开已布的信号线， +# **不喂给布线器** —— 喂了的话 ctrl 带 57 个件的信号一根都出不去。 +# 判据也换一个：硬铺铜看断面，软铺铜看 **`board_check` 从板上读回来的连通性**， +# 因为它被信号切碎成孤岛是完全可能的，而那只有读铜才看得见。 +# +# 依据是 `_base_pads.json` 实测的分布，不是画出来的（见 §28.15）： +# `+3V3` 47 只脚里 **26 只**在 ctrl 带 x 28~86 / y 86~112（其余 15 只在槽上、4 只在风扇带） +# `+3V3_HUB` 21 只脚分成 U32/去耦组与 U31/C737 两簇 +# `+5V` ctrl 带东头 2 只（`R706` / `L3`，5V Buck 那一窝）；槽上那 10 只要走走廊，不在这 +# ⚠ 三块互不重叠（不同网同层重叠 = 短路），`selfcheck()` 会查。 +# ⚠ M9 暂时清空：`+3V3` 与 `+3V3_HUB` 的脚在西区互相穿插（排布器按「离目标最近」摆的）， +# 两个网划不出互不重叠的矩形。新拓扑没有 M8 那道墙，先让布线器直接布， +# 看失败分布再决定要不要为它们改摆位 + 加软铺铜。 +RAILS = [ + # U31 与 U32 相距较远，分成两块局部软铜，中间由 A* 明确连接。 + # 这比一块 24x60 mm 大面更不容易被控制信号切成孤岛。 + # M12 采用当前手工布局后旧坐标已失效：U31 移到 y=73.6，U32 移到 y=52.9。 + ('RAIL-3V3HUB-LDO', '+3V3_HUB', (77.8, 71.5, 90.2, 75.7)), + ('RAIL-3V3HUB-HUB', '+3V3_HUB', (84.0, 47.8, 102.0, 60.7)), + # ⛔ **`+3V3` 试过铺两块，反而更差**（45 → 58 条）：软铺铜会逼每只**区外**的脚 + # 各自去够铜面，而原来布线器可以把它们串成一条链。 + # ⇒ 判据：软铺铜只在「大部分脚都在区内」时划算（`+3V3_HUB` 21 只脚全在西区 ⇒ 值）， + # `+3V3` 47 只脚里 15 只在槽上、6 只在风扇带 ⇒ 不值，留给布线器。 +] +# ⚠ `VIN_RAW` / `VIN_FUSED` 两段**不强制**：它们的瓶颈是 DC-005 的三只脚和 1206 保险 +# 本身（座子额定 2~5 A、这块板要过 9 A，是用户 2026-09-08 明确接受的已知风险， +# 设计文档 §22.6）。板上再宽的铜也救不了插头内芯与弹片的接触面。 +# 真正必须够的是它们之间那两段长铜：`VIN_SW`（储能到检流）和 `+12V`（母线）。 + + +def mil(v): + return round(v * MIL, 4) + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + + +_PADS = [None] + + +def pads(): + u"""底板焊盘，**按 `place_base.ROUTE_FIX` 的计划位置**（与 `route_base` 的路由模型一致）。 + + ⛔ 以前这里读的是实测焊盘，而布线器读的是改位后的：DZ1 从 x=38.6 挪到 29.3 之后， + 实测算出的 VIN_FUSED/VIN_SW 分界是 32.9，改位后算出的是 30.5（VIN_SW 盖住 Q1.3）—— + 布线器看到的铜面和摆位下发后真正铺出来的对不上，而且哪一边都不报错。 + """ + if _PADS[0] is None: + _PADS[0], _moved = PL.route_fixed_pads(json.load(io.open(PADS, encoding='utf-8'))) + return _PADS[0] + + +def routes(): + if not os.path.exists(ROUTES): + return [], [] + c = json.load(io.open(ROUTES, encoding='utf-8')) + if c.get('schema') != ROUTE_SCHEMA or c.get('slot_rot') != B.SLOT_ROT: + return [], [] + return c['segs'], c['vias'] + + +# ── 铜面几何 ───────────────────────────────────────────────────────────── +def keepouts(): + u"""两层都不许铺铜的地方：`U20` 天线净空 + **天线缺口** + 四个 M3 安装孔。 + + ⛔ 缺口那一块**板材是挖掉的**，而这份脚本的铜面几何是按 `BW × BH` 的矩形算的 + （`tiles()` 只认矩形，不认板框折线）。不把缺口喂进来，GND 瓦片会照样铺到 + 板外的空气里 —— 板框对不上铜面，DRC 报「铜到板边」，而铺铜管理器不报。 + """ + sz = PL.sizes() + n = B.notch_rect() + out = [PL.antenna_keepout(sz), + (n[0] - INSET, n[1] - INSET, n[2] + INSET, n[3] + INSET)] + r = B.HOLE_D / 2.0 + 0.6 + for (hx, hy) in B.MOUNT_HOLES.values(): + out.append((hx - r, hy - r, hx + r, hy + r)) + return out + + +def tiles(x0, y0, x1, y1, cuts): + u"""把矩形按 `cuts` 切成若干块**单环**矩形。 + + ⛔ 不能用带洞的复杂多边形：`createComplexPolygon()` 传多个环会把客户端挂死 + （刀片 §24，请求 30 s 超时、进度恒 0/0，和「按钮失灵」分不清）。 + 同网的矩形接壤会自然连成一片铜，效果一样。 + """ + xs = sorted(set([x0, x1] + [v for c in cuts for v in (c[0], c[2]) + if x0 < v < x1])) + out = [] + for xa, xb in zip(xs, xs[1:]): + if xb - xa < 0.6: + continue + # ⛔ **禁区的 y 区间必须先合并再配对**。原来是「按 c[1] 排序后把 + # [起, 止] 一对一对塞进 ys，再 `zip(ys[0::2], ys[1::2])`」—— + # 那套只在禁区互不重叠时成立。天线缺口 (84.5~107.5) 和天线净空 (86~106) + # 是**嵌套**的，塞进去就变成 [.., 84.5, 107.5, 86.0, 106.0, ..]， + # 奇偶配对当场错位 ⇒ 瓦片照样盖住缺口，而**只有 `selfcheck` 那一条 + # 「压进净空区」看得出来**（铺铜管理器和 DRC 都不会响）。 + iv = [] + for c in cuts: + if c[0] < xb - 1e-9 and xa < c[2] - 1e-9: + iv.append([max(y0, c[1]), min(y1, c[3])]) + iv.sort() + merged = [] + for a, b in iv: + if merged and a <= merged[-1][1] + 1e-9: + merged[-1][1] = max(merged[-1][1], b) + else: + merged.append([a, b]) + cur = y0 + for a, b in merged + [[y1, y1]]: + if a - cur > 0.6: + out.append((round(xa, 3), round(cur, 3), round(xb, 3), round(a, 3))) + cur = max(cur, b) + return out + + +def power_rect(net): + u"""入口链某一段的铜面：这个网在 input 带里全部焊盘的外框 + `POWER_GROW`。""" + z = POWER_BAND + xs, ys = [], [] + for p in pads(): + if p[7] != net or not (z[1] <= p[3] <= z[3]): + continue + # U13.10 是 Rs6 上游的 Kelvin/监测脚，不是 9 A 主电流焊盘。 + # 把它纳入包围盒会让 VIN_SW 铜面跨过 Rs6 的 +12V 端。 + if net == 'VIN_SW' and p[0] == 'U13': + continue + if p[0] in GATE_PARTS: + continue + xs += [p[2] - p[4] / 2, p[2] + p[4] / 2] + ys += [p[3] - p[5] / 2, p[3] + p[5] / 2] + if not xs: + return None + g = POWER_GROW[net] + return (max(INSET, min(xs) - g), max(z[1] + INSET, min(ys) - g), + min(B.BW - INSET, max(xs) + g), min(z[3], max(ys) + g)) + + +def clip_chain(chain): + u"""入口链四段是**串联**的（中间隔着 F1 / Q1 / Rs6），铜面搭上就把器件短路了。 + + `chain` = [(net, rect)]，已按 x 排好。相邻两段重叠时竖切一刀，两边各退 CLR/2。 + ⛔ 刀口**按焊盘空隙定，不按重叠区中点**：在两块铜 y 方向重叠的那一带里，取 + 「西段网最东的焊盘」与「东段网最西的焊盘」之间的中点。 + 取重叠区中点的旧写法在 Q1 这里是错的 —— Q1 是南北两排脚（南排源极、北排漏极）， + VIN_SW 的外框又被北边的 C4/C6 拉到 x=25.8，中点直接落进 Q1 里面（x=30.6， + VIN_SW 盖住 Q1.3）。以前没出事，只是因为 DZ1 旧位置把 VIN_FUSED 撑到了 x=40。 + ⚠ 不能靠铺铜优先级解决：优先级只保证「低的那块被让开」，让出来的形状是不可预期的 + 细条，断面校核就没意义了。 + """ + out = [r for _n, r in chain] + ps = pads() + + def band(net, y0, y1): + return [p for p in ps if p[7] == net and p[0] not in GATE_PARTS + and not (net == 'VIN_SW' and p[0] == 'U13') + and p[3] - p[5] / 2 < y1 and p[3] + p[5] / 2 > y0] + + for i in range(len(out) - 1): + a, b = out[i], out[i + 1] + if a[2] <= b[0]: + continue + y0, y1 = max(a[1], b[1]), min(a[3], b[3]) + pa, pb = band(chain[i][0], y0, y1), band(chain[i + 1][0], y0, y1) + ea = max([p[2] + p[4] / 2 for p in pa] or [None]) + wb = min([p[2] - p[4] / 2 for p in pb] or [None]) + if ea is not None and wb is not None and ea < wb: + m = (ea + wb) / 2.0 + else: + m = (a[2] + b[0]) / 2.0 # 没有干净的焊盘空隙时退回旧规则 + out[i] = (a[0], a[1], round(min(a[2], m - CLR / 2), 3), a[3]) + out[i + 1] = (round(max(b[0], m + CLR / 2), 3), b[1], b[2], b[3]) + return out + + +def gate_notch(): + u"""GATE 缺口（矩形列表，喂给 `tiles()`）。 + + 主块：GATE 焊盘 + 三颗栅极件的外框，向外让 NOTCH_CLR、北侧留 NOTCH_HEAD，南到板边。 + 竖条：比主块更高的 GATE 焊盘（Q1.4 是 2 mm 长的 SOIC 脚）整只让出来 —— + 只挖主块的话 Q1.4 北半截仍在 VIN_FUSED 铜面里，模型里等于异网铜压在焊盘上。 + """ + ps = pads() + g = [p for p in ps if p[7] == 'GATE' and p[3] <= POWER_BAND[3]] + sm = [p for p in ps if p[0] in GATE_PARTS] + if not g or not sm: + return [] + y1 = round(max(p[3] + p[5] / 2 for p in sm) + NOTCH_HEAD, 3) + out = [(round(min(p[2] - p[4] / 2 for p in g) - NOTCH_CLR, 3), 0.0, + round(max(p[2] + p[4] / 2 for p in g + sm) + NOTCH_CLR, 3), y1)] + for p in g: + if p[3] + p[5] / 2 + NOTCH_CLR > y1: + out.append((round(p[2] - p[4] / 2 - NOTCH_CLR, 3), 0.0, + round(p[2] + p[4] / 2 + NOTCH_CLR, 3), + round(p[3] + p[5] / 2 + NOTCH_CLR, 3))) + return out + + +def gnd_pad_vias(): + u"""`GND_PAD_VIAS` 的几何：(要从入口链铜面里挖掉的地岛矩形, 专用 GND 过孔坐标)。""" + ps = pads() + islands, vias = [], [] + for ref, pin, side, cut in GND_PAD_VIAS: + hit = [p for p in ps if p[0] == ref and str(p[1]) == pin and p[6] == L_TOP] + if len(hit) != 1 or hit[0][7] != 'GND': + raise RuntimeError(u'%s.%s 应是唯一的顶层 GND 贴片焊盘' % (ref, pin)) + p = hit[0] + x0, y0 = p[2] - p[4] / 2, p[3] - p[5] / 2 + x1, y1 = p[2] + p[4] / 2, p[3] + p[5] / 2 + n = int((x1 - x0) / ISL_VIA_PITCH) + 1 + vy = y0 - ISL_VIA_GAP - VIA_D / 2 if side == 'S' else y1 + ISL_VIA_GAP + VIA_D / 2 + for k in range(n): + vias.append((round(p[2] + (k - (n - 1) / 2.0) * ISL_VIA_PITCH, 3), round(vy, 3))) + if cut: + # 缝一直通到板边 / 板顶：`tiles()` 只拿它切入口链那几块铜，切不到别的东西 + islands.append((round(x0 - ISL_M, 3), 0.0 if side == 'S' else round(y0 - ISL_M, 3), + round(x1 + ISL_M, 3), round(y1 + ISL_M, 3) if side == 'S' else B.BH)) + return islands, vias + + +def drain_piece(outs): + u"""Q1 漏极排（北排四脚，VIN_SW）的铜面。 + + ⛔ 入口链是按 x 串起来切的，而 Q1 是**南北两排**：南排源极归 VIN_FUSED，北排漏极 + 在 VIN_SW 那块的西边界之外 —— 9 A 只能靠 A* 的 2 mm 走线从四只漏极脚爬进铜面 + （2 mm 1 oz 外层只带 ~4 A）。这里按漏极排外框补一块，东头与 VIN_SW 已有的块搭接， + 南沿让开 VIN_FUSED。西沿只让 CLR：再往西是死头，断面校核会把它量成瓶颈。 + """ + ps = [p for p in pads() if p[0] == 'Q1' and p[7] == 'VIN_SW'] + if not ps: + return None + g = POWER_GROW['VIN_SW'] + x0 = min(p[2] - p[4] / 2 for p in ps) - CLR + x1 = max(p[2] + p[4] / 2 for p in ps) + g + y0 = min(p[3] - p[5] / 2 for p in ps) - g + y1 = max(p[3] + p[5] / 2 for p in ps) + g + vf = [r for (_n, net, _l, r, _p) in outs if net == 'VIN_FUSED' and r[0] < x1 and x0 < r[2]] + y0 = max([y0] + [r[3] + CLR for r in vf]) + sw = [r for (_n, net, _l, r, _p) in outs + if net == 'VIN_SW' and r[1] < y1 and y0 < r[3] and r[0] >= x0] + if sw: + x1 = max(x1, min(r[0] for r in sw) + 0.6) # 保证与已有 VIN_SW 块搭接 + return (round(x0, 3), round(y0, 3), round(x1, 3), round(y1, 3)) + + +def plan(): + u"""[(name, net, layer, rect, priority)]，priority 小的先铺、先占地盘。""" + outs = [] + chain = [(net, prio, power_rect(net)) for net, prio in POWER_NETS] + chain = [c for c in chain if c[2]] + chain.sort(key=lambda c: (c[2][0] + c[2][2]) / 2.0) + clipped = clip_chain([(c[0], c[2]) for c in chain]) + cuts = gate_notch() + gnd_pad_vias()[0] + for (net, prio, _r), r in zip(chain, clipped): + parts = tiles(r[0], r[1], r[2], r[3], cuts) if cuts else [r] + # 最大一块沿用原名（CUTS 按名找），其余加序号；check_cuts 会把同名前缀的块一起算 + parts.sort(key=lambda t: -(t[2] - t[0]) * (t[3] - t[1])) + for k, t in enumerate(parts): + outs.append(('PWR-%s%s' % (net.strip('+'), '-%d' % k if k else ''), + net, L_TOP, t, prio)) + dp = drain_piece(outs) + if dp: + outs.append(('PWR-VIN_SW-Q1', 'VIN_SW', L_TOP, dp, dict(POWER_NETS)['VIN_SW'])) + for k, r in enumerate(B.bus_rects()): + outs.append(('PWR-12V-%d' % k, '+12V', L_TOP, r, 4)) + # `+3V3` 五块槽墙（几何与判据见 `pcb_base.wall3v3_rects` / `wall_check`）。 + # 与 12V 同为**硬铺铜**：喂给布线器当障碍，且脚从 A* 里摘掉。 + for k, r in enumerate(B.wall3v3_rects()): + outs.append(('PWR-3V3-%d' % k, '+3V3', L_TOP, r, 4)) + # 低压轨的软铺铜：排在硬铺铜之后、GND 之前 + for name, net, r in RAILS: + outs.append((name, net, L_TOP, r, 5)) + # ⚠ `PWR-12V-*` 里 0=输入带母线 1=横脊 2~7=五根齿（3 号槽那根是两块拼的 L） + ko = keepouts() + d = INSET + for tag, lay in (('TOP', L_TOP), ('BOT', L_BOT)): + for k, t in enumerate(tiles(d, d, B.BW - d, B.BH - d, ko)): + outs.append(('GND-%s-%d' % (tag, k), 'GND', lay, t, 9)) + return outs + + +def rrect_src(x0, y0, x1, y1): + pts = [(x0, y0), (x1, y0), (x1, y1), (x0, y1), (x0, y0)] # ⚠ 必须显式闭合 + a = [mil(pts[0][0]), mil(pts[0][1])] + for p in pts[1:]: + a += ['L', mil(p[0]), mil(p[1])] + return a + + +def wall_check(): + u"""`+3V3` 槽墙的判据（几何算不出来，只有拿实测焊盘表比才算数）。 + + ⛔ 三条都要过，缺一条墙就是白做： + ① **15 只槽脚全被盖住** —— 与 12V 那条「10 排焊盘全被盖住」同理： + 少盖一只，铺铜管理器和 DRC 都只说「有铜」，而那只脚是断的。 + ② **一只异网针都不许压到**（`NC` 空网也算异网）：南排 NC(73)、北排 NC(71/72) + 就贴在 3V3 针旁边，方块一大就压上去，铺铜会绕开它们**把墙在针排上切碎**。 + ③ **桥的过孔要落在墙里**，否则过孔与铜面之间靠铺铜「碰巧」相接。 + """ + bad = [] + rects = B.wall3v3_rects() + ps = pads() + c = B.W3V3_CLR - 0.05 # 判据比构造留的净距松 0.05 + + def inside(x0, y0, x1, y1): + return any(r[0] - 1e-6 <= x0 and x1 <= r[2] + 1e-6 and + r[1] - 1e-6 <= y0 and y1 <= r[3] + 1e-6 for r in rects) + + own = 0 + for p in ps: + px0, py0 = p[2] - p[4] / 2, p[3] - p[5] / 2 + px1, py1 = p[2] + p[4] / 2, p[3] + p[5] / 2 + if p[7] == '+3V3': + if inside(px0, py0, px1, py1): + own += 1 + continue + for r in rects: + if px0 - c < r[2] and r[0] < px1 + c and py0 - c < r[3] and r[1] < py1 + c: + bad.append(u'3V3 槽墙压到异网针 %s.%s(%s) @%.2f,%.2f' + % (p[0], p[1], p[7] or 'NC', p[2], p[3])) + break + slots = set(PL.SLOT_ORDER) + slot_own = sum(1 for p in ps if p[7] == '+3V3' and p[0] in slots) + if own != slot_own: + bad.append(u'3V3 槽脚 %d 只，墙只盖住 %d 只' % (slot_own, own)) + _segs, vias = B.wall3v3_bridges() + for (vx, vy) in vias: + r = VIA_D / 2.0 + if not inside(vx - r, vy - r, vx + r, vy + r): + bad.append(u'3V3 桥的过孔 (%.2f, %.2f) 不在墙里' % (vx, vy)) + return bad, own, slot_own + + +def bus_check(): + u"""12V 干道/铜墙必须覆盖全部槽脚，且不能压到异网焊盘。""" + rects = B.bus_rects() + ps = pads() + slots = set(B.USB_SLOT_REF.values()) + clear = CLR - 0.05 + + def inside(p): + x0, y0 = p[2] - p[4] / 2, p[3] - p[5] / 2 + x1, y1 = p[2] + p[4] / 2, p[3] + p[5] / 2 + return any(r[0] - 1e-6 <= x0 and x1 <= r[2] + 1e-6 and + r[1] - 1e-6 <= y0 and y1 <= r[3] + 1e-6 for r in rects) + + own = [p for p in ps if p[0] in slots and p[7] == '+12V'] + missed = [p for p in own if not inside(p)] + bad = [u'12V 铜墙没盖住 %s.%s @%.2f,%.2f' % (p[0], p[1], p[2], p[3]) + for p in missed] + for p in ps: + if p[7] == '+12V': + continue + px0, py0 = p[2] - p[4] / 2, p[3] - p[5] / 2 + px1, py1 = p[2] + p[4] / 2, p[3] + p[5] / 2 + if any(px0 - clear < r[2] and r[0] < px1 + clear and + py0 - clear < r[3] and r[1] < py1 + clear for r in rects): + bad.append(u'12V 干道/铜墙压到异网针 %s.%s(%s) @%.2f,%.2f' + % (p[0], p[1], p[7] or 'NC', p[2], p[3])) + return bad, len(own) - len(missed), len(own) + + +def selfcheck(ps): + bad = [] + ko = [k for k in keepouts() if k not in B.bus_rects()] + for name, net, lay, r, _p in ps: + if r[2] - r[0] < 0.6 or r[3] - r[1] < 0.6: + bad.append(u'%s 太小: %s' % (name, r)) + if r[0] < INSET - 1e-6 or r[1] < INSET - 1e-6 or \ + r[2] > B.BW - INSET + 1e-6 or r[3] > B.BH - INSET + 1e-6: + bad.append(u'%s 出了内缩线: %s' % (name, r)) + for k in ko: + if r[0] < k[2] - 1e-6 and k[0] < r[2] - 1e-6 and \ + r[1] < k[3] - 1e-6 and k[1] < r[3] - 1e-6: + bad.append(u'%s 压进净空区 %s' % (name, tuple(round(v, 1) for v in k))) + # 入口链各段不许互相重叠（同层，靠 F1/Q1/Rs6 断开）。 + # ⚠ **只判不同网**：`+12V` 自己那几块（母线 / 横脊）是故意相接的，重叠才对。 + pw = [(n, net, r) for (n, net, _l, r, _p) in ps + if n.startswith('PWR-') or n.startswith('RAIL-')] + for i, (na, na_net, a) in enumerate(pw): + for (nb, nb_net, b) in pw[i + 1:]: + if na_net == nb_net: + continue + if a[0] < b[2] and b[0] < a[2] and a[1] < b[3] and b[1] < a[3]: + bad.append(u'%s(%s) 与 %s(%s) 在顶层重叠 —— 串联的两段铜搭上就把器件短路了' + % (na, na_net, nb, nb_net)) + return bad + + +# ── 断面校核 ───────────────────────────────────────────────────────────── +def cut_height(net, rect, x): + u"""在 x 处竖切一刀，`rect` 这块铜面上属于 `net` 的**最宽一段**连续净铜高（mm）。 + + 别人的焊盘 / 过孔 / 导线按 `CLR` 膨胀之后从这条线上扣掉。 + ⚠ 取「最宽一段」而不是总和：被挖成两条 4 mm 的铜带，不等于一条 8 mm 的。 + """ + if not (rect[0] <= x <= rect[2]): + return 0.0 + spans = [(rect[1], rect[3])] + blocks = [] + for p in pads(): + if p[7] == net or p[6] not in (1, 12): + continue + if p[2] - p[4] / 2 - CLR <= x <= p[2] + p[4] / 2 + CLR: + blocks.append((p[3] - p[5] / 2 - CLR, p[3] + p[5] / 2 + CLR)) + segs, vias = routes() + for s in segs: + if s[6] == net or s[0] != 1: + continue + x0, x1 = sorted((s[1], s[3])) + hw = s[5] / 2.0 + CLR + if x0 - hw <= x <= x1 + hw: + y0, y1 = sorted((s[2], s[4])) + blocks.append((y0 - hw, y1 + hw)) + for v in vias: + if len(v) > 2 and v[2] == net: + continue + r = VIA_D / 2.0 + CLR + if abs(v[0] - x) <= r: + blocks.append((v[1] - r, v[1] + r)) + for (b0, b1) in blocks: + nxt = [] + for (a0, a1) in spans: + if b1 <= a0 or b0 >= a1: + nxt.append((a0, a1)) + continue + if b0 > a0: + nxt.append((a0, b0)) + if b1 < a1: + nxt.append((b1, a1)) + spans = nxt + return max([q[1] - q[0] for q in spans] or [0.0]) + + +def cut_width_y(net, rect, y): + u"""在 y 处横切一刀，最宽一段连续净铜宽（mm）。""" + if not (rect[1] <= y <= rect[3]): + return 0.0 + spans = [(rect[0], rect[2])] + blocks = [] + for p in pads(): + if p[7] == net or p[6] not in (1, 12): + continue + if p[3] - p[5] / 2 - CLR <= y <= p[3] + p[5] / 2 + CLR: + blocks.append((p[2] - p[4] / 2 - CLR, p[2] + p[4] / 2 + CLR)) + segs, vias = routes() + for q in segs: + if q[6] == net or q[0] != 1: + continue + y0, y1 = sorted((q[2], q[4])) + hw = q[5] / 2.0 + CLR + if y0 - hw <= y <= y1 + hw: + x0, x1 = sorted((q[1], q[3])) + blocks.append((x0 - hw, x1 + hw)) + for v in vias: + if len(v) > 2 and v[2] == net: + continue + rr = VIA_D / 2.0 + CLR + if abs(v[1] - y) <= rr: + blocks.append((v[0] - rr, v[0] + rr)) + for (b0, b1) in blocks: + nxt = [] + for (a0, a1) in spans: + if b1 <= a0 or b0 >= a1: + nxt.append((a0, a1)); continue + if b0 > a0: + nxt.append((a0, b0)) + if b1 < a1: + nxt.append((b1, a1)) + spans = nxt + return max([q[1] - q[0] for q in spans] or [0.0]) + + +def series_windows(net): + u"""这个网自己串联元件占的坐标窗口（本体的焊盘外框）。 + + ⛔ 断面校核**必须跳过这些窗口**：最窄的一刀永远落在串联元件身上 + （2512 分流电阻自己就只有 3.2 mm 宽、DC 座三只脚挤在 5 mm 里）， + 量到的是元件的宽度不是铜的宽度，判据就没意义了。 + 元件本身的载流由选型保证（`Rs6` 是 2512 3 W、`F1` 是 12 A 保险）， + 这里要查的是**元件之间那段铜**。 + """ + # ⛔ 窗口要按**整颗器件**的焊盘外框算，不是只按它属于本网的那只脚。 + # 只按那只脚的话，`D1`（TVS：一端 VIN_SW、一端 GND）只有阴极那半边被跳过， + # 阳极的 GND 盘照样把断面掐断 —— 实测 `VIN_SW` 被判成 4.35 mm。 + # 物理上电流是**穿过器件**的，整颗器件占的那一段本来就不该算铜宽。 + ps = pads() + own = set(p[0] for p in ps if p[7] == net) + by = {} + for p in ps: + if p[0] not in own: + continue + b = by.setdefault(p[0], [1e9, 1e9, -1e9, -1e9]) + b[0] = min(b[0], p[2] - p[4] / 2); b[2] = max(b[2], p[2] + p[4] / 2) + b[1] = min(b[1], p[3] - p[5] / 2); b[3] = max(b[3], p[3] + p[5] / 2) + return by + + +def check_cuts(ps): + print(u'') + print(u'载流断面校核（逐刀切，取**最窄**一刀，跳过串联元件本身）:') + bad = [] + byname = {} + for (n, _net, _l, r, _p) in ps: + byname.setdefault(n, []).append(r) + for key, label, net, axis, need, must in CUTS: + # 挖了 GATE 缺口之后一段铜会被切成几块（`PWR-X`、`PWR-X-1`…）：每一刀取包含它的那块 + rs = [r for n, v in byname.items() if n == key or n.startswith(key + '-') for r in v] + if not rs: + print(u' %-18s %-9s [X] 这一段没有铜面' % (label, net)) + bad.append(label) + continue + r = (min(q[0] for q in rs), min(q[1] for q in rs), + max(q[2] for q in rs), max(q[3] for q in rs)) + skip = [] + for ref, b in series_windows(net).items(): + if b[0] > r[2] or b[2] < r[0] or b[1] > r[3] or b[3] < r[1]: + continue + skip.append((ref, (b[0] - CLR, b[2] + CLR) if axis == 'x' else (b[1] - CLR, b[3] + CLR))) + lo, hi = (r[0], r[2]) if axis == 'x' else (r[1], r[3]) + hs = [] + t = lo + 0.25 + while t <= hi - 0.25: + if not any(a <= t <= b for _ref, (a, b) in skip): + f = cut_height if axis == 'x' else cut_width_y + hs.append((max(f(net, q, t) for q in rs), t)) + t += 0.25 + worst = min(hs) if hs else (0.0, 0.0) + ok = worst[0] >= need + print(u' %-18s %-9s 铜面 %5.1f×%5.1f 最窄 %5.2f mm (%s=%.2f，要 %.1f) %s' + % (label, net, r[2] - r[0], r[3] - r[1], worst[0], axis, worst[1], need, + u'[OK]' if ok else (u'[X] 不够' if must else u'[~] 瓶颈在连接器，不强制'))) + if skip: + print(u' （跳过串联元件 %s）' % ' '.join(sorted(ref for ref, _w in skip))) + if not ok and must: + bad.append(u'%s %s 最窄只有 %.2f mm' % (label, net, worst[0])) + return bad + + +# ── 缝合过孔 ───────────────────────────────────────────────────────────── +def board_tracks(): + return call(OPEN + "return (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>l.layer===1||l.layer===2)" + ".map(l=>[l.startX/%s,l.startY/%s,l.endX/%s,l.endY/%s," + "l.lineWidth/%s,String(l.net||'')]);" % (MIL, MIL, MIL, MIL, MIL), + timeout=300) + + +def _seg_d(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L = dx * dx + dy * dy + t = 0.0 if L < 1e-12 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L)) + return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + + +def stitch_points(tracks=None): + u"""GND 缝合过孔的坐标。 + + ⛔ **顶层的地铜被信号切成很多块岛，每块岛至少要有一个缝合过孔**， + 否则「移除孤岛」把它整块删掉 —— 而 `rebuildCopperRegion()` / + 铺铜管理器 / DRC **三个地方都不报错**（刀片 §24.4）。 + 4 mm 网格是为了让最小的岛也有机会摊上一个。 + """ + d = pads() + if tracks is None: + tracks = board_tracks() + r = VIA_D / 2.0 + STITCH_CLR + ko = keepouts() + # ⛔ **硬功率铜面里不打缝合孔**：那里顶层没有地铜，GND 孔只会在 9 A 铜上掏洞 + # （4 mm 网格一刀能掏掉 3~4 mm 净铜），而断面校核看不到缝合孔。 + ko += [rr for (n, _net, _l, rr, _p) in plan() if n.startswith('PWR-')] + # 专用 GND 过孔（地岛 / 缺口里的地脚）永远在，网格点让开它们 + own = gnd_pad_vias()[1] + out = list(own) + ko += [(vx - VIA_D, vy - VIA_D, vx + VIA_D, vy + VIA_D) for (vx, vy) in own] + y = INSET + 2.0 + while y <= B.BH - INSET - 2.0: + x = INSET + 2.0 + while x <= B.BW - INSET - 2.0: + ok = True + for k in ko: + if k[0] - r < x < k[2] + r and k[1] - r < y < k[3] + r: + ok = False + break + if ok: + for p in d: + # ⛔ **通孔地脚不能当「自己人」跳过**：缝合过孔落在它身上, + # DRC 报「钻孔到钻孔 0 mil」（实测 J1_3 / C2_2 / J33_1 三处）。 + # 同网也要留钻孔间距，这是工艺规则不是电气规则。 + pass + if p[2] - p[4] / 2 - r < x < p[2] + p[4] / 2 + r and \ + p[3] - p[5] / 2 - r < y < p[3] + p[5] / 2 + r: + ok = False + break + if ok: + for t in tracks: + if t[5] == 'GND': + continue + if _seg_d(x, y, t[0], t[1], t[2], t[3]) < r + t[4] / 2.0: + ok = False + break + if ok: + out.append((round(x, 3), round(y, 3))) + x += STITCH_PITCH + y += STITCH_PITCH + return out + + +def stitch(): + pts = stitch_points() + print(u'GND 缝合过孔 %d 个（%g mm 网格）' % (len(pts), STITCH_PITCH)) + JS = OPEN + u""" +const MIL = %s, P = %s, D = %s, H = %s; +let old = 0; +for (const v of (await eda.pcb_PrimitiveVia.getAll()||[])) + if (String(v.net) === 'GND') { await eda.pcb_PrimitiveVia.delete(v.primitiveId); old++; } +let n = 0; +for (const p of P) { + try { await eda.pcb_PrimitiveVia.create('GND', p[0]*MIL, p[1]*MIL, H*MIL, D*MIL); n++; } + catch (e) {} +} +await eda.pcb_Document.save(); +return {deleted: old, made: n, now: (await eda.pcb_PrimitiveVia.getAll()||[]).length}; +""" % (MIL, json.dumps(pts), VIA_D, VIA_HOLE) + print(call(JS, timeout=900)) + + +# ── 下发铺铜 ───────────────────────────────────────────────────────────── +JS_DEL = OPEN + u""" +let n = 0; +for (const old of await eda.pcb_PrimitivePour.getAll()) { + await eda.pcb_PrimitivePour.delete(old.primitiveId); n++; } +await eda.pcb_Document.save(); +return {deleted: n}; +""" + +JS_MAKE = OPEN + u""" +const PLAN = %s; +for (const p of PLAN) { + const poly = await eda.pcb_MathPolygon.createComplexPolygon([p.src]); + if (!poly) continue; + try { await eda.pcb_PrimitivePour.create(p.net, p.layer, poly, 'solid', false, + p.name, p.prio, 10); } catch (e) {} +} +return {made: (await eda.pcb_PrimitivePour.getAll()) + .map(x => String(x.pourName || '').toUpperCase())}; +""" + +JS_REBUILD = OPEN + u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +const leaf = (txt) => { for (const el of document.querySelectorAll('*')) + if (el.children.length===0 && (el.textContent||'').trim()===txt) return el; return null; }; +const btn = (txt) => { for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()===txt && b.offsetParent!==null) return b; return null; }; +if (!fire(leaf('工具'))) return {err: 'no 工具'}; +await sleep(900); +if (!fire(leaf('铺铜管理器...'))) return {err: 'no 铺铜管理器'}; +await sleep(2500); +const b = btn('重建所有'); +if (!b) return {err: 'no 重建所有'}; +return {fired: fire(b)}; +""" + +JS_POLL = u"return {poured: (await eda.pcb_PrimitivePoured.getAll()).length};" + +JS_DONE = u""" +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +let ok = null; +for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()==='确认' && b.offsetParent!==null) { ok = b; break; } +if (ok) fire(ok); +await new Promise(r => setTimeout(r, 1500)); +await eda.pcb_Document.save(); +return {poured: (await eda.pcb_PrimitivePoured.getAll()).length, + pour: (await eda.pcb_PrimitivePour.getAll()).length}; +""" + + +def rebuild(): + print(u'重建所有铺铜（走 GUI —— `rebuildCopperRegion()` 是坏的，刀片 §24 已查清）…') + print(call(JS_REBUILD, timeout=180)) + last, same = -1, 0 + for _ in range(40): + time.sleep(6) + n = call(JS_POLL, timeout=120)['poured'] + print(u' 已填 %d 块' % n) + same = same + 1 if n == last else 0 + last = n + if same >= 2 and n > 0: + break + print(call(JS_DONE, timeout=180)) + + +def push(ps): + print(call(JS_DEL, timeout=300)) + arr = [{'name': n, 'net': net, 'layer': l, 'prio': p, 'src': rrect_src(*r)} + for (n, net, l, r, p) in ps] + made = [] + for k in range(0, len(arr), 12): + made += call(JS_MAKE % json.dumps(arr[k:k + 12], ensure_ascii=False), timeout=600)['made'] + want = set(n.upper() for (n, _net, _l, _r, _p) in ps) + got = set(made) + print(u'铜面建了 %d / %d 块' % (len(want & got), len(want))) + if want - got: + print(u' [!] 没建上: %s' % ' '.join(sorted(want - got))) + rebuild() + + +if __name__ == '__main__': + # 铜面按 ROUTE_FIX 的计划位置算（见 pads()）；板端还没挪件就铺，铜和件对不上。 + if ('--push' in sys.argv or '--stitch' in sys.argv) and PL.route_fix_moves(): + sys.exit(u'!! ROUTE_FIX 还有 %d 件没下发到板端（%s）；先 place_base --push 再 ' + u'--adopt-live --dump，然后才能铺铜' % (len(PL.route_fix_moves()), + ' '.join(sorted(PL.route_fix_moves())))) + if '--clear' in sys.argv: + print(call(JS_DEL, timeout=300)) + sys.exit(0) + ps = plan() + bad = selfcheck(ps) + print(u'计划建 %d 块铜面：' % len(ps)) + for name, net, lay, r, prio in ps: + if not name.startswith('GND-') or name.endswith('-0'): + print(u' %-12s net=%-9s L%d x %6.2f~%6.2f y %6.2f~%6.2f prio=%d' + % (name, net, lay, r[0], r[2], r[1], r[3], prio)) + print(u' （GND 瓦片 %d 块，绕开天线净空与四个 M3 孔）' + % sum(1 for p in ps if p[0].startswith('GND-'))) + if bad: + print(u'[X] 自检 %d 条不过:' % len(bad)) + for t in bad: + print(u' ' + t) + else: + print(u'[OK] 自检全过（不出内缩线 / 不压净空 / 入口链四段互不重叠）') + wbad, wown, wtot = wall_check() + bs, bv = B.wall3v3_bridges() + print(u'3V3 槽墙：%d 块矩形，盖住 %d/%d 只槽脚；走廊底层桥 %d 段 / 过孔 %d' + % (len(B.wall3v3_rects()), wown, wtot, len(bs), len(bv))) + if wbad: + print(u'[X] 3V3 槽墙自检 %d 条不过:' % len(wbad)) + for t in wbad: + print(u' ' + t) + bad += wbad + else: + print(u'[OK] 3V3 槽墙：槽脚全盖住 / 不压异网针 / 桥的过孔都在墙里') + bbad, bown, btot = bus_check() + print(u'12V 干道/铜墙：盖住 %d/%d 只插槽电源脚' % (bown, btot)) + if bbad: + print(u'[X] 12V 干道/铜墙自检 %d 条不过:' % len(bbad)) + for t in bbad: + print(u' ' + t) + bad += bbad + else: + print(u'[OK] 12V 干道/铜墙：槽脚全盖住 / 不压异网针') + cbad = check_cuts(ps) + bad += cbad + if '--stitch' in sys.argv: + stitch() + if '--push' in sys.argv: + if bad: + sys.exit(u'!! 自检不过，不下发') + push(ps) + elif '--rebuild' in sys.argv: + rebuild() diff --git a/.claude/r2/archive_base2L/remote_route.ps1 b/.claude/r2/archive_base2L/remote_route.ps1 new file mode 100644 index 0000000..bac1d44 --- /dev/null +++ b/.claude/r2/archive_base2L/remote_route.ps1 @@ -0,0 +1,163 @@ +param( + [string]$Server = '10.5.5.13', + [int]$Passes = 1, + [switch]$PriorityCache, + [switch]$DpOnly, + # 服务器并行试算：每个元素是一组额外参数（如 '--repair --bot-pen-w 1'）， + # 各自在独立副本里跑，取未完成最少的那个走下面同一套校验 / 接受逻辑。 + [string[]]$Variants = @(), + [int]$PollSec = 60, + # 服务器上跑布线的解释器；PyPy 见 PROGRESS（纯 Python 的 A*，JIT 通常快数倍） + [string]$Interp = 'python3' +) + +$ErrorActionPreference = 'Stop' +$Here = Split-Path -Parent $MyInvocation.MyCommand.Path +$Repo = Resolve-Path (Join-Path $Here '..\..') +$Python = 'C:\Python314\python.exe' +$Ssh = 'C:\Windows\System32\OpenSSH\ssh.exe' +$Scp = 'C:\Windows\System32\OpenSSH\scp.exe' +# 临时文件带 PID：允许同时起两批（快的单轮变体 + 慢的拆线重布），互不覆盖 +$Archive = Join-Path ([System.IO.Path]::GetTempPath()) "dcdc-remote-route-$PID.tgz" +$RunScript = Join-Path ([System.IO.Path]::GetTempPath()) "dcdc-remote-run-$PID.sh" +$RemoteArchive = Split-Path -Leaf $Archive +$Incoming = Join-Path $Here "_base_routes.server.$PID.json" +$Cache = Join-Path $Here '_base_routes.json' +$Backup = Join-Path $Here '_base_routes.pre-server.json' +$Rejected = Join-Path $Here '_base_routes.rejected.json' +$remoteRoot = $null + +if ($Passes -lt 1) { + throw 'Passes must be at least 1.' +} +if ($DpOnly -and $Variants.Count -gt 0) { + throw '-DpOnly cannot be combined with -Variants.' +} + +Push-Location $Repo +try { + & $Python '.claude\r2\route_base.py' --snapshot-vias + if ($LASTEXITCODE -ne 0) { throw 'Failed to refresh board-via snapshot.' } + + $remoteRoot = (& $Ssh $Server 'mktemp -d /tmp/dcdc-route.XXXXXX').Trim() + if ($LASTEXITCODE -ne 0 -or $remoteRoot -notmatch '^/tmp/dcdc-route\.[A-Za-z0-9]+$') { + throw "Unexpected remote work directory: $remoteRoot" + } + + & tar.exe --exclude=*.png --exclude=*.bak --exclude=__pycache__ ` + --exclude=_remote_route.tgz -czf $Archive ` + '.claude\r2' '.claude\eda.py' '.claude\pcb_pour.py' '.claude\eda-parts.json' + if ($LASTEXITCODE -ne 0) { throw 'Failed to build routing bundle.' } + + & $Scp $Archive "${Server}:${remoteRoot}/" + if ($LASTEXITCODE -ne 0) { throw 'Failed to upload routing bundle.' } + & $Ssh $Server "tar -xzf ${remoteRoot}/${RemoteArchive} -C ${remoteRoot}" + if ($LASTEXITCODE -ne 0) { throw 'Failed to extract routing bundle.' } + + $priority = if ($PriorityCache) { ' --priority-cache' } else { '' } + $scope = if ($DpOnly) { ' --dp-only' } else { '' } + $timeFmt = "/usr/bin/time -f 'REMOTE_TIME=%e sec CPU=%P RSS=%M KB'" + $remoteResult = "${remoteRoot}/.claude/r2/_base_routes.json" + + if ($Variants.Count -eq 0) { + $command = "DCDC_ROUTE_SERVER=1 $timeFmt $Interp " + + "${remoteRoot}/.claude/r2/route_base.py --offline --replan --passes $Passes$priority$scope" + & $Ssh $Server $command + if ($LASTEXITCODE -ne 0) { throw 'Remote routing failed.' } + } + else { + # 变体各自一份副本（缓存文件同名，不能共用目录），脱离 ssh 会话在后台跑： + # 拆线重布可能要跑很久，ssh 断线不能把计算带走。 + $lines = @('#!/bin/bash', "cd ${remoteRoot}") + for ($k = 0; $k -lt $Variants.Count; $k++) { + $v = $Variants[$k] + $lines += "mkdir -p v$k && cp -r .claude v$k/" + $lines += "( DCDC_ROUTE_SERVER=1 $timeFmt $Interp ${remoteRoot}/v$k/.claude/r2/route_base.py " + + "--offline --replan --passes $Passes$priority $v > v$k.log 2>&1; echo `$? > v$k.rc ) &" + } + $lines += 'wait' + $lines += 'touch done' + [System.IO.File]::WriteAllText($RunScript, (($lines -join "`n") + "`n")) + & $Scp $RunScript "${Server}:${remoteRoot}/run.sh" + if ($LASTEXITCODE -ne 0) { throw 'Failed to upload run script.' } + & $Ssh $Server "setsid nohup bash ${remoteRoot}/run.sh > /dev/null 2>&1 < /dev/null &" + if ($LASTEXITCODE -ne 0) { throw 'Failed to start remote variants.' } + for ($k = 0; $k -lt $Variants.Count; $k++) { Write-Host "v${k}: $($Variants[$k])" } + + $start = Get-Date + $poll = 0 + while ($true) { + Start-Sleep -Seconds $PollSec + $poll++ + $state = (& $Ssh $Server "test -f ${remoteRoot}/done && echo DONE || echo RUN").Trim() + if ($state -eq 'DONE') { break } + if ($poll % 5 -eq 0) { + $mins = [int]((Get-Date) - $start).TotalMinutes + Write-Host "--- $mins min ---" + & $Ssh $Server "cd ${remoteRoot} && for f in v*.log; do echo `"`$f: `$(tail -n 1 `$f)`"; done" + } + } + + $summary = & $Ssh $Server ("cd ${remoteRoot} && for k in `$(seq 0 $($Variants.Count - 1)); do " + + "echo `"v`$k rc=`$(cat v`$k.rc) `$(python3 -c 'import json,sys; d=json.load(open(sys.argv[1])); " + + "print(len(d[\`"logs\`"]), len(d[\`"segs\`"]), len(d[\`"vias\`"]))' " + + "v`$k/.claude/r2/_base_routes.json 2>/dev/null || echo NA)`"; done") + $best = $null + foreach ($row in $summary) { + Write-Host $row + if ($row -match '^v(\d+) rc=0 (\d+) (\d+) (\d+)$') { + $cand = @{ K = [int]$Matches[1]; Logs = [int]$Matches[2]; Vias = [int]$Matches[4] } + if (-not $best -or $cand.Logs -lt $best.Logs -or + ($cand.Logs -eq $best.Logs -and $cand.Vias -lt $best.Vias)) { + $best = $cand + } + } + } + for ($k = 0; $k -lt $Variants.Count; $k++) { + Write-Host "===== v${k}: $($Variants[$k]) =====" + & $Ssh $Server "grep -E '拆线重布|第 [0-9]+ 轮|REMOTE_TIME|Traceback|Error' ${remoteRoot}/v$k.log | tail -n 25" + } + if (-not $best) { throw 'No remote variant finished successfully.' } + Write-Host "Best variant: v$($best.K) ($($Variants[$best.K])) with $($best.Logs) unfinished." + $remoteResult = "${remoteRoot}/v$($best.K)/.claude/r2/_base_routes.json" + } + + if ($DpOnly) { + Write-Host 'Server-side D+/- diagnostic completed; local route cache was not changed.' + } + else { + & $Scp "${Server}:${remoteResult}" $Incoming + if ($LASTEXITCODE -ne 0) { throw 'Failed to download routing result.' } + $result = Get-Content -LiteralPath $Incoming -Raw | ConvertFrom-Json + if ($result.schema -ne 7 -or $result.slot_rot -ne 0 -or + $result.usb_slot_ref.'1' -ne 'J34' -or $result.usb_slot_ref.'5' -ne 'J38') { + throw 'Downloaded routing cache failed topology validation.' + } + $current = if (Test-Path -LiteralPath $Cache) { + Get-Content -LiteralPath $Cache -Raw | ConvertFrom-Json + } else { $null } + if ($current -and $result.logs.Count -gt $current.logs.Count) { + Move-Item -LiteralPath $Incoming -Destination $Rejected -Force + Write-Host "Rejected worse server result: $($result.logs.Count) unfinished > current $($current.logs.Count)." + } + else { + if ($current) { + Copy-Item -LiteralPath $Cache -Destination $Backup -Force + } + Move-Item -LiteralPath $Incoming -Destination $Cache -Force + Write-Host "Accepted server result: $($result.segs.Count) segments, $($result.vias.Count) vias, $($result.logs.Count) unfinished." + } + } +} +finally { + Pop-Location + foreach ($f in @($Archive, $RunScript)) { + if (Test-Path -LiteralPath $f) { Remove-Item -LiteralPath $f -Force } + } + if ($remoteRoot -and $remoteRoot -match '^/tmp/dcdc-route\.[A-Za-z0-9]+$') { + # ⛔ 模式里的 `(v[0-9]+/)?[.]claude` 是故意的：直接写目录串的话，执行这条命令的 + # 远程 shell 命令行里也含这个串，pkill 先把自己杀了（ssh 返回 255），后面的 rm + # 根本不执行。按路径匹配而不是按 `python3`，换成 pypy3 也杀得到。 + & $Ssh $Server "pkill -f '${remoteRoot}/(v[0-9]+/)?[.]claude/r2/route_base' ; rm -rf -- '${remoteRoot}'" + } +} diff --git a/.claude/r2/archive_base2L/route_base.py b/.claude/r2/archive_base2L/route_base.py new file mode 100644 index 0000000..0b82d5d --- /dev/null +++ b/.claude/r2/archive_base2L/route_base.py @@ -0,0 +1,1340 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 布线（M8d）。 + + /c/Python314/python .claude/r2/route_base.py # 算 + 落盘缓存，不下发 + /c/Python314/python .claude/r2/route_base.py --replan # 强制重算（默认吃缓存） + /c/Python314/python .claude/r2/route_base.py --dp-only # 只算七对 D±，不改缓存 + /c/Python314/python .claude/r2/route_base.py --push # 下发导线 + 过孔 + /c/Python314/python .claude/r2/route_base.py --clear # 清掉全部布线 + +**引擎复用刀片那一份 `router.py`**（0.25 网格 + 8 邻接 A*，见它的文件头）， +这里只做三件事：把板级常量换成底板的、加两条两层板独有的约束、写自己的主流程。 + +## 两层板独有的两条约束（刀片上没有） + +1. **底层（L2）是完整地平面 —— 走一格就是在平面上割一刀。** + ⇒ 底层全层收「过路费」`BOT_PEN`：不封死（方案 §6.2 允许 D± 走廊之外跳线）， + 但只有当顶层要绕远 `BOT_PEN` 倍以上时才划算。短跳线照走，长干线不会跑下去。 + ⛔ 过路费必须**每次 `pen_pads` 之后重新打**：`pen_pads` 头一句就是 `reset_pen()`， + 直接写 `g.pen` 会被它清掉，而且**不报错** —— 现象是底层突然多出一堆长线。 + +2. **D± 走廊下方一刀不许割**（§6.2 第 1 条，这是 2 层方案成立的前提）。 + ⇒ 分两相布： + **第一相**七对 D± **只准走顶层**（`TOP_ONLY`，底层整层封死）； + **第二相**把第一相的铜按 `DIFF_KEEP` 膨胀，在底层**封死**，再布其余所有网。 + 于是任何跳线都不可能钻到 D± 底下。 + +## 差分对：靠「贴着走」的过路费成对 + +`router.py` 是逐网布的，不认识差分对。做法：`DP` 布完之后，给整个顶层打一层 +过路费、只把 `DP` 铜周围 `HUG_BAND` 内的格点留成 0，`DM` 自然就贴着 `DP` 走。 +实测中心距落在网格的 1.5 mm（= 1.2 线宽 + 0.3 缝），Zdiff 比方案 §6.3 那张表 +（1.2/0.2 → 94 Ω）略高，仍在 USB 2.0 的 90 Ω ±15% 窗口里。首板不勾阻抗控制。 + +## `GND` 不布线 + +333 只地脚全靠**两层铺铜 + 缝合过孔**（`pour_base.py`）。底层本来就是整块地平面， +顶层的地铜面被信号切成多块岛 —— **每块岛至少要有一个缝合过孔**， +否则会被当孤岛整块删掉，而 `rebuildCopperRegion()` / 铺铜管理器 / DRC **三个都不报错** +（刀片 M4c 的教训，方案 §24.4）。`pour_base --check` 就是查这一条的。 + +## `+12V` 的 9 A 靠铺铜，不靠这里的线宽 + +这里给 `+12V` 1.5 mm（= 单槽 1.5 A 的要求）、`VIN_*` 2.0 mm。 +入口链那段 9 A 要 ≥8 mm 净铜宽（§6.4），由 `pour_base` 在顶层铺一块 `+12V` 铜面 + +**断面校核**保证（办法沿用 R1 `pcb1_pour.py` 的 `CUTS`）。 +⇒ 只看这份脚本的线宽会以为入口链严重欠载流，别慌，看铺铜那一步。 +""" +import io +import json +import math +import os +import sys + +# `--hash-seed N`：固定字符串哈希（网名集合的遍历顺序 → 直连 / 排网的平局先后）。 +# **只对 CPython 有意义**：CPython 的集合按哈希序遍历、字符串哈希按进程随机， +# 固定之后结果可复现，也可以扫几个种子取最好的。 +# ⚠ PyPy 的集合一律按**插入序**遍历，哈希值不影响结果 —— 实测 8 个种子输出逐字节相同。 +# 哈希种子只能在解释器启动前设，所以带着环境变量重启自己。 +if '--hash-seed' in sys.argv: + _seed = sys.argv[sys.argv.index('--hash-seed') + 1] + if os.environ.get('PYTHONHASHSEED') != _seed: + os.execve(sys.executable, [sys.executable] + sys.argv, + dict(os.environ, PYTHONHASHSEED=_seed)) + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +import pcb_base as B # noqa: E402 +import router as RT # noqa: E402 +import rules_base as RB # noqa: E402 + +# 用户明确要求所有布线运算都放到 10.5.5.13。快照、缓存报告和下发仍可在本机做， +# 但任何会启动 A* / 差分对试算的入口必须由 remote_route.ps1 在服务器上显式解锁。 +_COMPUTE_FLAGS = ('--replan', '--dp-only') +if any(flag in sys.argv for flag in _COMPUTE_FLAGS) and os.environ.get('DCDC_ROUTE_SERVER') != '1': + sys.exit(u'!! 布线运算禁止在本机执行；请使用 .claude/r2/remote_route.ps1（服务器 10.5.5.13）') + +# ── 把 router 的板级常量换成底板的 ──────────────────────────────────────── +RT.B = B +RT.PCB = B.PCB +RT.NX = int(round(B.BW / RT.G)) + 1 +RT.NY = int(round(B.BH / RT.G)) + 1 +RT.PADS = os.path.join(HERE, '_base_pads.json') +RT.FINGER_KEEP_Y = 0.0 # 底板没有金手指区 +RT.KELVIN = [] +RT.KELVIN_PADS = set() +RT.CLR = 0.21 # 设计规则是 0.20，留一点给网格吸附 +RT.W_DEFAULT = 0.2 # 两层板走 JLC 标准工艺，信号 0.2 +RT.EDGE_CLR = 0.4 +# ⛔ **两层正交那条约定在底板上要关掉**。刀片上是「器件面纵向、另一面横向」 +# （方案 §25.6），做法是逆着方向走贵 `CROSS_COST=3` 倍。底板只有**顶层**能布信号 +# （底层是完整地平面），于是「顶层偏好横向」变成「每往北走一格贵 3 倍」—— +# 而 D± 全都是南北向的。实测现象：`USB5` 一对布出 **37 段**的锯齿路径， +# 把扇出带占满，紧接着 `USB4` 一段都布不出来。看着像拥塞，其实是**代价函数**。 +# `LAYER_DIR` 留空 ⇒ `_along()` 一律返回 True，八个方向同价。 +RT.LAYER_DIR = {} +CACHE = os.path.join(HERE, '_base_routes.json') +CACHE_SCHEMA = 7 # v7: live-layout D±, rail bridge, and revised 12V trunk +BOARD_VIAS = os.path.join(HERE, '_base_board_vias.json') + + +class _NoNotch(object): + u"""`build_grid` 要 `pcb_pour.notch_cut()`（金手指防呆缺口）—— 底板没有。 + + 给一个板外的退化矩形，比在 `router.py` 里加 if 干净（那份是刀片的事实来源）。 + """ + + @staticmethod + def notch_cut(): + return (-10.0, -10.0, -9.0, -9.0) + + +RT.P = _NoNotch + + +def _rule_min(net, auto): + u"""线宽下限：查底板自己的 `rules_base.NET_TRACK`，不是刀片那份。""" + cls = RB.NET_TRACK.get(net) + if cls is None: + return 0.15 + return RB.TRACK_RULES[cls]['strokeWidthMin'] + + +RT.rule_min = _rule_min + + +# ⛔ **通孔焊盘（layer 12）**：刀片是全贴片的，`router.py` 里一句 +# `if lay not in LAY: continue` 就把它们从占用图里漏掉了 —— 底板有 DC 座 / +# 两个风扇座 / 应急排针 / 两颗直立电解，漏掉的后果是布线器直接从通孔焊盘上压过去。 +# 而 `pad_nodes` 又会拿 `g.own[12]` 去查，直接 KeyError（这次是**响**的，算运气好）。 +# ⇒ 拆成两条记录：顶层那条参与布线，底层那条只当障碍（脚号加后缀，`bypad` 里滤掉）。 +BOT_SUFFIX = '#b' + + +# ⛔ **通孔焊盘要额外膨胀**：`J1`（DC 座）和 `J23`（USB-C）的孔是 **SLOT（长槽）**， +# 槽比焊盘大，而布线器只按矩形焊盘建模 ⇒ 线贴着焊盘走就压在槽上， +# DRC 报「挖槽区域 到 导线 0 mil」（实测 22 条，全是 `VIN_FUSED` 贴着 J1）。 +TH_GROW = 0.6 + + +def split_th(pads): + out = [] + for p in pads: + if p[6] == 12: + a = list(p); a[6] = 1; a[4] += TH_GROW; a[5] += TH_GROW + b = list(p); b[6] = 2; b[1] = str(p[1]) + BOT_SUFFIX + b[4] += TH_GROW; b[5] += TH_GROW + out += [a, b] + else: + out.append(p) + return out + + +def apply_route_fix(pads): + u"""在板端尚未重抓焊盘时，把 ROUTE_FIX 平移到计划位置。 + + `_base_pads.json` 是 EasyEDA 当前板端的读回值；M12 的两颗让路电阻已经写进 + `place_base.ROUTE_FIX`，但桥接中断时无法立即重抓。这里用同一份 live 布局快照 + 算平移量，使离线路由能先验证新位置。板端移动并重新 `--adopt-live --dump` 后， + live 坐标等于目标坐标，平移量自然归零，不会重复移动。 + """ + import place_base as PL + pads, moved = PL.route_fixed_pads(pads) # 与 pour_base 共用同一份换算 + if moved: + print(u' 路由预检计划改位：' + ' '.join(moved)) + return pads + + +def load_board_vias(): + u"""读取板端既有过孔；`--offline` 时使用本地快照供计算服务器复现。""" + if '--offline' in sys.argv: + if not os.path.exists(BOARD_VIAS): + raise RuntimeError(u'离线计算缺少 _base_board_vias.json；先在 EDA 可达机器运行一次预检') + return [tuple(v) for v in json.load(io.open(BOARD_VIAS, encoding='utf-8'))] + vias = RT.load_vias() + io.open(BOARD_VIAS, 'w', encoding='utf-8').write( + json.dumps(vias, ensure_ascii=False, indent=2)) + return vias + +# ── 线宽 ───────────────────────────────────────────────────────────────── +DP_NETS = [] +for _name, _dp, _dm in RB.PAIRS: + DP_NETS += [_dp, _dm] +DIFF_W = 1.0 # 试：1.0/0.2 ⇒ ~100 Ω（USB 窗口 76.5~103.5 内） + +RT.WIDTH = { + 'VIN_RAW': 2.0, 'VIN_FUSED': 2.0, 'VIN_SW': 2.0, + '+12V': 1.5, # 单槽 1.5 A；干路 9 A 由铺铜断面保证 + 'FAN_12V_SW': 0.8, + '+5V': 0.6, '+3V3': 0.5, '+3V3_HUB': 0.5, +} +for _n in DP_NETS: + RT.WIDTH[_n] = DIFF_W +RT.WIDTH_AUTO = {} +# 七对 D± + 全部电源网都不按焊盘封顶（见 router.NO_CAP）。 +# ⛔ 封顶对电源网是**静默降载**：`route_groups` 按「这个网最小的那只脚」封顶， +# 实测把 `+12V` 从 1.5 压到 **0.30**、`VIN_SW` 从 2.0 压到 0.30 —— 0.30 mm 1 oz +# 外层只带 0.65 A，而槽支路要 1.5 A。铺铜只盖到母线，**支路那一段没有铜面兜底**。 +# 缩颈交给 `stub_w`（只缩引出脚，不缩干线）。 +RT.NO_CAP = tuple(DP_NETS) + ('VIN_RAW', 'VIN_FUSED', 'VIN_SW', + '+12V', '+5V', '+3V3', '+3V3_HUB') + +# ── 两层板独有的两条约束 ───────────────────────────────────────────────── +BOT_PEN = 6 # 底层每格的过路费（顶层 0）。见文件头第 1 条 +BOT_PEN_W = 2 # 东西功能区的底层过路费：那里不在 D± 干线下方 +if '--bot-pen-w' in sys.argv: # 服务器变体试算用：东西两区底层跳线的价格 + BOT_PEN_W = int(sys.argv[sys.argv.index('--bot-pen-w') + 1]) +DIFF_KEEP = 1.5 # D± 铜两侧多少 mm 内，底层不许有铜 +HUG_BAND = 2.2 # DM 贴着 DP 走的自由带半宽 +DIFF_GUIDE_W = 3.2 # 「导引线」宽度：够两根 1.2 并排（1.41 + 2×0.81） +GUIDE_BAND = 1.6 # 两根真线只许在导引线中心线 ±1.6 里走 +HUG_PEN = 12 + +TOP_ONLY = [False] # 第一相：底层整层封死 +_HUG = [None] # [(x0,y0,x1,y1), ...] 或 None +_LANE = [None] # (lane_y, [riser x 窗口]) 或 None + +# ── M9：每对 D± 一条**专属车道**（通道里竖着一条 + 目标走廊里横着一条）───── +# 新拓扑下 D± 的路是三段：`U32` 东沿 → 逃逸扇形散到 x=29 → **D± 通道**（x 29~37） +# 里竖着走到目标槽的**北侧走廊** → 走廊里横着往东到 x≈59.5 的槽针。 +# ⛔ 通道只有 8 mm，一对占 2.7 ⇒ 必须分道，否则先布的那一对会把通道占满 +# （M8 实测：不分道时后布的那一对「布了 0 段」，而 DRC / 几何验证一条都不响）。 +# 南北两边的对**不重叠**（`U32` 在 y=67，槽 1/2/3 在南、4/5 在北）⇒ 1&5、2&4 可以共用车道。 +# ⛔ **车道要按「逃逸斜线有多长」分，不是按槽号**。扇形里外侧的脚要斜爬 ~6.5 mm +# 才到自己的 y，斜线终点 x≈32；把它分到 31.25 那条道，等于让斜线落在道外， +# 而它会从别人的起跑点上压过去 —— 实测 `USB5_DP` 的斜线正好压在 `USB5_DM` +# 的落点 (29.85, 73) 上，占用图那一格变 255（两个网碰过 = 谁也不能进）， +# 现象是「一对里只进得去一根」，换五种办法都救不回来。 +# ⇒ 斜线最长的（USB1/USB5）分最东那条道，最短的（USB3）分最西。 +# ⛔ **车道顺序按「扇形横线不许横穿别人的竖段」定，不是按斜线长短**（上一版搞反了， +# DRC 报 USB1/USB2 之间 0 mil）。推导：南行的 USB1 扇出 y 最南、竖段只到自己以南， +# 所以它的横线必须**最先停**（最西的道）；USB2 的扇出 y 在它北边，横线可以更往东。 +# 北行同理反过来：USB5 扇出 y 最北 → 最西的道，USB3 → 最东。 +DP_LANE_X = {1: 78.75, 2: 74.25, 3: 69.75, 4: 74.25, 5: 78.75} +LANE_HALF = 2.25 # 车道 4.5：一对要 2.63，再被一根 0.25 逃逸线横穿 + # （吃掉 1.67）仍剩 2.83 ⇒ 装得下 +# 逃逸扇形的落点区（所有对共用，靠扇形本身分开）。10 只脚 × 2.0 间距 = 20 mm 跨度， +# 以 U32 的 D± 脚中点（y≈66）为中心 ⇒ 56~76，两头各留 1。 +U32_BOX = (73.0, 55.0, 82.0, 77.0) + +RISER_U32 = None # M8 遗留，M9 不用 +RISER_HALF = None +LANE_LO = LANE_HI = None +LANE_Y = {} + +_orig_build = RT.build_grid +_orig_pen_pads = RT.pen_pads +_DIFF_SEGS = [] # 第一相布出来的 D± 铜，第二相用来封底层 + + +def _extra_pen(g): + u"""底层过路费 + D± 走廊底层封死 + DM 的贴合带。**每次 reset_pen 之后都要重打。**""" + # ⛔ 底层过路费**分区收**（M9 起）：D± 只在「西通道 x29~37 + 各走廊」里跑， + # 西区（x<29，Hub/ESP32/DAC 那一窝，最挤）的底层其实不在任何 D± 底下， + # 对它收满价等于白白把唯一的跳线层封掉。M8 全板降价（6→2）之所以更差 + # （173→178），是因为那时 D± 横贯全板，降价换来的跳线全落在它底下。 + if BOT_PEN: + # D± 从槽针 x=45 到东侧通道，这一带下方的地平面最珍贵。 + g.penalize(2, B.MID[0], -1, B.DP_CHAN[2], B.BH + 1, BOT_PEN) + g.penalize(2, -1, -1, B.MID[0], B.BH + 1, BOT_PEN_W) + g.penalize(2, B.DP_CHAN[2], -1, B.BW + 1, B.BH + 1, BOT_PEN_W) + if _HUG[0] is not None: + pen = g.pen[1] + for k in range(len(pen)): + if pen[k] < HUG_PEN: + pen[k] = HUG_PEN + for (x0, y0, x1, y1) in _HUG[0]: + i0 = max(0, int(math.floor(x0 / RT.G))) + i1 = min(RT.NX - 1, int(math.ceil(x1 / RT.G))) + j0 = max(0, int(math.floor(y0 / RT.G))) + j1 = min(RT.NY - 1, int(math.ceil(y1 / RT.G))) + for j in range(j0, j1 + 1): + base = j * RT.NX + for i in range(i0, i1 + 1): + pen[base + i] = 0 + + +def pour_blocks(): + u"""顶层电源铜面 → 布线器的障碍（**按各自的网**标归属）。 + + ⛔ 不喂进去的话，布线器会大大方方从 12V 高速路 / 铜墙中间穿过去 —— + 铺铜时那根线把 9 A 的干道**整段切断**，而铺铜管理器 / DRC / 连通性 + 三个都只说「有铜」。 + """ + import pour_base as PB + return [(net, r) for (n, net, lay, r, _p) in PB.plan() + if lay == 1 and n.startswith('PWR-')] + + +_POURS = [None] + + +_DSIDE = [None] # 当前布的是一对里的哪一根：-1 = DM(西半道)，+1 = DP(东半道) + + +def dp_block_rects(i, side=None): + u"""布第 i 对 D± 时，顶层要封死的地方（除了它自己的车道和目标走廊）。 + + ⛔ 通道里**不能整条封**：那一对还要在目标走廊那一段**往东拐出去**。 + 第一版按「通道里除本车道全封」写，结果只有 USB3 通（它的走廊正好和 + `U32` 出口区重叠），其余四对全是「布了 0 段」—— 看着像通道太窄， + 其实是出口被自己封死了。⇒ 通道的封锁按 y 取补集： + 放行 `U32` 出口区 + 目标走廊那两段。 + """ + # ⛔ **一对里的两根各占半条道**。共用整条道的下场：先布的那根自己蜿蜒占掉 3.5 mm + # （实测车道 4.5 只剩 1~2 格），第二根「没布通」。分半之后各 2.25， + # 一根 1.0 的线只要 2×0.71 = 1.42 ⇒ 都装得下，而且天然并排、耦合。 + lane = DP_LANE_X[i] + if side: + lane = lane + side * (LANE_HALF / 2.0) + cor = B.usb_corridor(i) # 新针向：D± 焊盘在槽的南排 + y0, y1 = B.PROJ[0], B.PROJ[1] + py = B.slot_y(B.USB_SLOT_POS[i]) - B.PAD_ROW_DY + hi = max(cor[3], py + 1.6) # 走廊上沿往上探到槽内的南排焊盘 + keep = sorted([(U32_BOX[1], U32_BOX[3]), (cor[1], hi)]) + # 合并重叠区间，再取补集 + merged = [] + for a, b in keep: + if merged and a <= merged[-1][1]: + merged[-1][1] = max(merged[-1][1], b) + else: + merged.append([a, b]) + gaps, cur = [], y0 + for a, b in merged + [[y1, y1]]: + if a - cur > 0.2: + gaps.append((cur, a)) + cur = max(cur, b) + out = [] + # ① D± 通道里不属于本对的 x 段（只在放行区间之外才封） + half = LANE_HALF / 2.0 if side else LANE_HALF + for (a, b) in ((B.DP_CHAN[0], lane - half), (lane + half, B.DP_CHAN[2])): + if b - a > 0.2: + for (ga, gb) in gaps: + out.append((a, ga, b, gb)) + # ② 中区里不属于目标走廊的部分（别让它钻进别的走廊） + if cor[1] - y0 > 0.2: + out.append((B.MID[0], y0, B.MID[1], cor[1])) + if y1 - hi > 0.2: + out.append((B.MID[0], hi, B.MID[1], y1)) + return out + + +_DPI = [None] # 当前在布第几对（1~5），None = 不限 + + +def _block_lane(g): + if _DPI[0] is None: + return + for (a, b, c, d) in dp_block_rects(_DPI[0], _DSIDE[0]): + g.block_both(1, a, b, c, d, 0.0, net='#lane') + + +def ant_blocks(halfw): + u"""ESP32 天线：**缺口（没板材）+ 净空（不许有铜）**，两层都封死。 + + ⛔ 这一条以前是漏的：`place_base`（摆位）认净空、`pour_base`（铺铜）认净空， + **布线器一个字都不知道** ⇒ A* 可以大大方方从天线底下穿线过去， + 而 DRC / `board_check` / 几何校验一条都不响（设计文档 §PCB 要点写着 + 「天线区域下方禁止铺铜、**禁止走线**」，后半条从来没人执行）。 + ⚠ 净空**只往外膨胀**，朝模组那一侧不膨胀：净空自带 0.5 侧余量， + 再往模组里吃 halfw 会把最靠里那几只脚的出口封死。 + """ + import place_base as PL + k = PL.antenna_keepout(PL.sizes()) + n = B.notch_rect() + e = RT.EDGE_CLR + halfw + ax = PL.hand()['U20'][2] + kk = {90: (k[0] - halfw, k[1] - halfw, k[2], k[3] + halfw), + 270: (k[0], k[1] - halfw, k[2] + halfw, k[3] + halfw), + 0: (k[0] - halfw, k[1], k[2] + halfw, k[3] + halfw), + 180: (k[0] - halfw, k[1] - halfw, k[2] + halfw, k[3])}[int(round(ax)) % 360] + return [kk, (n[0] - e, n[1] - e, n[2] + e, n[3] + e)] + + +def build_grid(pads, halfw, vias=()): + g = _orig_build(pads, halfw, vias) + for (a, b, c, d) in ant_blocks(halfw): + for l in (1, 2): + g.block_both(l, a, b, c, d, 0.0, net='#ant') + if _POURS[0] is None: + _POURS[0] = pour_blocks() + for (net, r) in _POURS[0]: + g.block_both(1, r[0], r[1], r[2], r[3], 0.0, net=net) + _block_lane(g) + if TOP_ONLY[0]: + g.block_both(2, -1, -1, B.BW + 1, B.BH + 1, 0.0, net='#topOnly') + else: + for (l, x0, y0, x1, y1, ww, nn) in _DIFF_SEGS: + k = DIFF_KEEP + ww / 2.0 + halfw + RT.block_track(g, 2, x0, y0, x1, y1, k, '#diffKeep') + _extra_pen(g) + return g + + +def pen_pads(g, pads, halfw): + _orig_pen_pads(g, pads, halfw) + _extra_pen(g) + + +RT.build_grid = build_grid +RT.pen_pads = pen_pads + + +# ⛔ 0.25 不行：十根线一起走 45°，相邻两条的**垂直**间距只有 0.5×cos45 = 0.354， +# 减去线宽剩 0.104，而规则要 0.2（DRC 实测报「距离 4mil，应 ≥7.9mil」一大片）。 +# 0.15 ⇒ 0.204，刚好过；JLC 两层最小线宽 0.127，做得了。 +ESC_W = 0.15 # 逃逸段线宽（贴着 0.5 mm 脚距走） +ESC_STUB = 0.6 # 出脚先直着走多长再拐 45°（短一点，斜线才来得及收） +ESC_X = 81.0 # U32 西排逃逸的终点 x（= D± 通道东沿） +# ⛔ **不能取 1.5**（= 1.2 干线 + 0.3 缝）。占用图里一根已布的干线往两侧各膨胀 +# `halfw + ww/2 = 0.81 + 0.6 = 1.41`，1.5 只剩 **0.09 mm** 余量 ⇒ +# 每对里第一根（DP）布完之后，第二根（DM）在起跑点**一个格点都找不到**。 +# 实测现象整整齐齐：七对里六对都是「DP 通、DM 出不来」，看着像板子太挤。 +ESC_PITCH = 1.6 # 散开之后的线距（≥1.41 的膨胀量即可；越大斜线越长） +ESC_S_Y = 57.5 # 南排（USB6 / 上行）逃逸的终点 y +ESC_SLOT = 1.8 # 槽针 / 模组脚逃逸出去多深（够干线起步即可； + # 太深会把横跑段顶出走廊，见 dp_build 里那段） + + +def _pair_of(net): + u"""`USB3_DP` → 3；不是编号对（USB6 / 上行）返回 None。""" + if net.startswith('USB') and net[3].isdigit() and int(net[3]) <= B.SLOT_N: + return int(net[3]) + return None + + +def pair_run_y(i, net): + u"""编号 D± 在目标槽走廊内的横向干线 y。""" + # USB3 的 DM 等长蛇形紧邻槽端地脚；整对南移 0.8 mm 留足 0.2 mm 净距。 + extra = 0.8 if i == 3 else 0.0 + return round(B.usb_corridor(i)[3] - (3.2 if net.endswith('_DP') else 1.2) - extra, 3) + + +def hub_escape(pads): + u"""`U32` **西沿**十只下行 D± 脚的逃逸扇形 + 虚拟起跑点。 + + ⛔ **1.2 mm 的干线没法从 0.5 mm 间距的 QFN 脚上起步**（M8 §28 的教训，换布局照样成立）： + 十根线要从 0.5 的脚距散到 1.5，光斜着散开就要 4 mm。现象不是短路而是「布了 0 段」—— + `pad_nodes` 在焊盘四周一个可起步的格点都找不到，看着像板子太挤。 + ⇒ 先用 0.25 mm 细线把十只脚扇开到 1.5 间距（0.5 脚距下净距 0.25，过 DRC 的 0.20）， + 扇到东侧 D± 通道的各自车道，在那儿放虚拟焊盘当干线起跑点。 + """ + esc, launch = [], {} + want = set() + for nm, dp, dm in RB.PAIRS: + if nm not in ('USB6', 'USBUP'): + want.add(dp) + want.add(dm) + ds = [q for q in pads if q[0] == 'U32' and q[7] in want] + ds.sort(key=lambda q: q[3]) + if len(ds) != 10: + print(u' [!] U32 西排找到 %d 只 D± 脚（应为 10）' % len(ds)) + return [], {} + mid = (ds[0][3] + ds[-1][3]) / 2.0 + for i, q in enumerate(ds): + px, py = q[2] - q[4] / 2.0, q[3] + ty = round(mid + (i - (len(ds) - 1) / 2.0) * ESC_PITCH, 3) + # ⛔ **每一对扇到自己的车道 x 上**，不要都停在同一条竖线（x=29）。 + # 停在同一条线上的话，先布的那对横穿「出口区」时就把后面几对的 + # 起跑点堵死 —— 实测五对里三对报「U32.launch 出不来」， + # 而换车道宽度 / 换先后顺序 / 加导引线三种办法都救不回来。 + # 扇线本身在不同的 y 上，互相不交叉；南边的对去南边的槽、北边的去北边， + # 脚序（USB1 最南 … USB5 最北）与槽序同向，所以横穿也不会撞上别人的干线。 + net = q[7] + # 一对里的两根在车道内**左右分开 1.5**（DP 在东、DM 在西）： + # 共用一条竖线的话，先布的那根会压过后布那根的起跑点（实测「出不来」）。 + # 1.5 > 占用图要求的 1.41，正好是差分对该有的中心距。 + tx = DP_LANE_X.get(_pair_of(net), ESC_X) + # ⛔ **DP 在西、DM 在东**（不是反过来）。构造出来的路径是「竖 → 横 → 竖」： + # DM 走靠焊盘那条横线（南）、DP 走外面那条（北）。要不交叉，走南边横线的 + # 那一根必须在通道里**靠东**，否则它往东跑时会横穿伙伴的竖段 + # （自查实测 `USB5_DM 与 USB5_DP 净距 −0.001`）。 + # 方向不同，左右要反过来：构造出来的路径是「竖 → 横 → 竖」， + # **先转弯的那一根必须在通道里靠西**，否则它向槽端横跑时会切过 + # 伙伴尚未结束的竖段。方向必须按当前脚的实际起跑点和目标横线判断； + # 不能再用固定 y 阈值，U32 随手工布局移动后 USB3 会被误判并自交叉。 + _i = _pair_of(net) + _yr = pair_run_y(_i, net) + _north = _yr > ty + _east = (net.endswith('_DP')) if not _north else (net.endswith('_DM')) + tx += 0.75 if _east else -0.75 + x1 = px - ESC_STUB + x2 = round(x1 - abs(ty - py), 3) + esc.append((1, px, py, x1, py, ESC_W, net)) + if abs(ty - py) > 1e-6: + esc.append((1, x1, py, x2, ty, ESC_W, net)) + if abs(tx - x2) > 1e-6: + esc.append((1, x2, ty, tx, ty, ESC_W, net)) + launch.setdefault(net, []).append(['U32', 'launch', round(tx, 3), ty, + 0.3, 0.3, 1, net, 'RECT']) + return esc, launch + + +def hub_escape_aux(pads): + u"""`U32` **北沿**四只脚（`USB6_DP/DM` + 上行 `UP_DP/DM`）的逃逸扇形。""" + esc, launch = [], {} + want = set() + for nm, dp, dm in RB.PAIRS: + if nm in ('USB6', 'USBUP'): + want.add(dp) + want.add(dm) + cy32 = None + for q in pads: + if q[0] == 'U32' and str(q[1]) == '65': + cy32 = q[3] + ds = [q for q in pads if q[0] == 'U32' and q[7] in want + and (cy32 is None or q[3] > cy32)] + ds.sort(key=lambda q: q[2]) + if len(ds) != 4: + print(u' [!] U32 北排找到 %d 只 D± 脚（应为 4）' % len(ds)) + return [], {} + mid = (ds[0][2] + ds[-1][2]) / 2.0 + for i, q in enumerate(ds): + px, py = q[2], q[3] + q[5] / 2.0 + tx = round(mid + (i - (len(ds) - 1) / 2.0) * ESC_PITCH, 3) + y1 = py + ESC_STUB + y2 = round(y1 + abs(tx - px), 3) + net = q[7] + esc.append((1, px, py, px, y1, ESC_W, net)) + if abs(tx - px) > 1e-6: + esc.append((1, px, y1, tx, y2, ESC_W, net)) + # 从当前焊盘几何推导 Hub 北沿。旧版固定写成 y=79，是 M9 布局遗留； + # U32 移到 y=52.903 后会凭空多走约 20 mm，并把 USB6/上行对拉进控制区。 + aux_y = round(max(p[3] + p[5] / 2.0 for p in ds) + 2.0, 3) + if abs(y2 - aux_y) > 1e-6: + esc.append((1, tx, y2, tx, aux_y, ESC_W, net)) + launch.setdefault(net, []).append(['U32', 'launch', tx, aux_y, + 0.3, 0.3, 1, net, 'RECT']) + return esc, launch + + +def aux_hub_escape(pads): + u"""U32 北沿辅助对逃逸；上行对用一小段底层完成与 USB6 的局部换序。""" + def pad(net): + hit = [q for q in pads if q[0] == 'U32' and q[7] == net] + if len(hit) != 1: + raise RuntimeError(u'U32 %s 焊盘数为 %d' % (net, len(hit))) + q = hit[0] + return (q[2], q[3] + q[5] / 2.0) + + esc, launch, vias = [], {}, [] + usb = { + 'USB6_DP': [(90.2, 60.0)], + 'USB6_DM': [(91.8, 60.0)], + } + for net, tail in usb.items(): + s = pad(net) + pts = [s, (s[0], s[1] + 0.6), tail[0]] + esc += _poly(net, pts, ESC_W) + launch[net] = [['U32', 'launch', tail[0][0], tail[0][1], + 0.3, 0.3, 1, net, 'RECT']] + + # 顶层从 0.5 mm 脚距散开，过孔下到底层；两根底线保持 1.6 mm 中心距。 + spec = { + 'UP_DP': ([(87.8, 59.2)], [(93.2, 61.5)]), + 'UP_DM': ([(87.8, 60.8)], [(93.2, 63.1)]), + } + for net, (a, b) in spec.items(): + s = pad(net) + esc += _poly(net, [s, (s[0], s[1] + 0.6), a[0]], ESC_W) + esc += [(2, a[0][0], a[0][1], b[0][0], b[0][1], DIFF_W, net)] + vias += [(a[0][0], a[0][1], net), (b[0][0], b[0][1], net)] + launch[net] = [['U32', 'launch', b[0][0], b[0][1], + 0.3, 0.3, 1, net, 'RECT']] + return esc, launch, vias + + +def _slot_refs(): + return [B.USB_SLOT_REF[i] for i in range(1, B.SLOT_N + 1)] + + +SLOT_REFS = _slot_refs() + + +def topology_check(pads): + u"""用实测焊盘验证新拓扑。这些条件不成立时，坐标调得再好也不能下发。""" + bad = [] + + def one(ref, net): + return [q for q in pads if q[0] == ref and q[7] == net] + + ep = [q for q in pads if q[0] == 'U32' and str(q[1]) == '65'] + if not ep: + bad.append(u'U32 EP 焊盘不存在') + return bad + cx = ep[0][2] + spans = [] + for i in range(1, B.SLOT_N + 1): + ref = B.USB_SLOT_REF[i] + hp = one('U32', 'USB%d_DP' % i) + sp = one(ref, 'USB%d_DP' % i) + if len(hp) != 1 or len(sp) != 1: + bad.append(u'USB%d 端点不唯一：U32=%d / %s=%d' % (i, len(hp), ref, len(sp))) + continue + if hp[0][2] >= cx: + bad.append(u'USB%d 在 U32 上没有朝西出脚' % i) + if not (B.DP_CHAN[0] < DP_LANE_X[i] < B.DP_CHAN[2]): + bad.append(u'USB%d 车道 x=%.2f 超出 D± 通道' % (i, DP_LANE_X[i])) + c = B.usb_corridor(i) + if not (c[1] <= sp[0][3] - ESC_SLOT <= c[3]): + bad.append(u'USB%d 槽端向南逃逸后没有落入目标走廊' % i) + spans.append((i, hp[0][3], sp[0][3])) + # 两端 y 顺序必须一致，否则平面内一定交叉。 + for a, b in zip(spans, spans[1:]): + if (a[1] - b[1]) * (a[2] - b[2]) <= 0: + bad.append(u'USB%d/USB%d 两端 y 顺序相反，D± 必然交叉' % (a[0], b[0])) + return sorted(set(bad)) + + +def pair_escape(pads, refs, out_dir): + u"""给**任何一端脚距太密的 D± 焊盘**接一段 0.25 mm 逃逸，末端放虚拟起跑点。 + + ⛔ 这一条 M9 是必须的：槽针是 **1.0 mm 脚距**（盘 0.7 宽）， + 而 D± 干线 1.2 mm + 净距 0.21 ⇒ 半宽 0.81，`pad_nodes` 在焊盘四周 + **一个可起步的格点都找不到**（实测 `J34.46` = 0 个）， + 现象是「差分对 USB1 布了 0 段」，看着像通道太挤，其实是起不了步。 + M8 侥幸能布是因为那时槽转 90°、焊盘长边（2.0）正好顺着走线方向； + M9 转过来之后长边朝南北，这条侥幸就没了。 + + `out_dir`: 'N'/'S'/'E'/'W'，焊盘往哪一侧逃。 + """ + esc, launch = [], {} + D = {'N': (0.0, 1.0), 'S': (0.0, -1.0), 'E': (1.0, 0.0), 'W': (-1.0, 0.0)}[out_dir] + for ref, nets in refs.items(): + depth = 3.2 if ref in ('U20', 'J23') else ESC_SLOT + ax = 0 if D[0] == 0 else 1 # 0 = 按 x 排，1 = 按 y 排 + by = {} + for q in pads: + if q[0] == ref and q[7] in nets: + by.setdefault(q[7], []).append(q) + if len(by) != 2: + print(u' [!] %s 上只找到 %d 个 D± 网' % (ref, len(by))) + continue + # Type-C 的 A6/B6 与 A7/B7 是交错四脚。J23 必须选 A6/A7 这组： + # 它们的 DP/DM 左右顺序与 U32 一致；选“分得最开”的 B7/B6 会把 + # 顺序反过来，两根线在单层平面内必然交叉。B6/B7 会在主流程里 + # 保留为独立目标，不得像旧版那样静默丢掉。 + na, nb = sorted(by) + if ref == 'J23': + prefer = {'UP_DP': 'A6', 'UP_DM': 'A7'} + qa = next(q for q in by[na] if str(q[1]) == prefer[na]) + qb = next(q for q in by[nb] if str(q[1]) == prefer[nb]) + best = (abs(qa[2 + ax] - qb[2 + ax]), qa, qb) + else: + best = None + for qa in by[na]: + for qb in by[nb]: + d0 = abs(qa[2 + ax] - qb[2 + ax]) + if best is None or d0 > best[0]: + best = (d0, qa, qb) + ps = sorted([best[1], best[2]], key=lambda q: q[2 + ax]) + mid = (ps[0][2 + ax] + ps[1][2 + ax]) / 2.0 + for k, q in enumerate(ps): + half = (q[5] / 2.0) if D[1] else (q[4] / 2.0) + sx = q[2] + D[0] * half + sy = q[3] + D[1] * half + t = round(mid + (k - 0.5) * ESC_PITCH, 3) # 散到 1.5 间距 + # 先直着走 ESC_STUB，再 45° 斜到目标位，最后直着走到 ESC_SLOT 深度 + x1, y1 = sx + D[0] * ESC_STUB, sy + D[1] * ESC_STUB + d = abs((t - (sx if ax == 0 else sy))) + x2, y2 = (t, y1 + D[1] * d) if ax == 0 else (x1 + D[0] * d, t) + x3, y3 = (x2, sy + D[1] * depth) if ax == 0 else (sx + D[0] * depth, y2) + net = q[7] + esc.append((1, sx, sy, x1, y1, ESC_W, net)) + if d > 1e-6: + esc.append((1, x1, y1, x2, y2, ESC_W, net)) + if abs((x3 - x2) + (y3 - y2)) > 1e-6: + esc.append((1, x2, y2, x3, y3, ESC_W, net)) + launch.setdefault(net, []).append([ref, 'launch', round(x3, 3), round(y3, 3), + 0.3, 0.3, 1, net, 'RECT']) + return esc, launch + + +def hug_rects(segs, band=HUG_BAND): + out = [] + for (l, x0, y0, x1, y1, _w, _n) in segs: + if l != 1: + continue + out.append((min(x0, x1) - band, min(y0, y1) - band, + max(x0, x1) + band, max(y0, y1) + band)) + return out + + +def rail_absorb(bypad): + u"""软铺铜（`pour_base.RAILS`）盖住的脚不再交给 A*。 + + ⛔ 不做这一步的实测后果：`+3V3` 一个网 47 只脚、A* 把它当一棵树布， + 摆位一动就崩（168 条里它一个网占 45）。这些脚本来就该靠铜面连，不该有线。 + + ⛔ **一个网有多块铜时必须一起处理**（第一版是按块逐个跑的，踩了两个坑）： + ① 第二块在**第一块已经加过虚拟落点的表**上再跑一遍 ⇒ 落点指数膨胀 + （47 只脚变成 126 个目标），实测直接炸到 239 条； + ② 两块铜之间**没有连接** —— 同网不同岛，铺完还是断的， + 而铺铜管理器 / DRC 都只说「有铜」。 + ⇒ 现在：先按网归并所有块 → 区内的脚一次性摘掉 → 区外的脚**每只只给一个**落点 + （落在离它最近的那块上）→ 再给块与块之间各加一对落点，逼布线器把它们接起来。 + + ⚠ 判据不在这里。软铺铜可能被信号切成孤岛 —— + **唯一判据是 `board_check --base` 从板上读回铜做并查集**（方案 §27.7 ④）。 + """ + import pour_base as PB + byn = {} + for name, net, r in PB.RAILS: + byn.setdefault(net, []).append((name, r)) + bridges = [] + for net, rects in byn.items(): + ps = bypad.get(net) + if not ps: + continue + + def inside(q, r): + return r[0] <= q[2] <= r[2] and r[1] <= q[3] <= r[3] + + ins = [q for q in ps if any(inside(q, r) for _n, r in rects)] + out = [q for q in ps if q not in ins] + if not ins: + continue + virt = [] + for q in out: + best = None + for _n, r in rects: + vx = min(max(q[2], r[0] + 1.0), r[2] - 1.0) + vy = min(max(q[3], r[1] + 1.0), r[3] - 1.0) + d = (vx - q[2]) ** 2 + (vy - q[3]) ** 2 + if best is None or d < best[0]: + best = (d, vx, vy) + virt.append(['RAIL', 'rail', round(best[1], 3), round(best[2], 3), + 0.6, 0.6, 1, net, 'RECT']) + # 块与块之间也要接起来（同网不同岛，铺铜自己不会连）。几何是已知的， + # 直接构造固定铜桥；把两端伪装成焊盘交给 A* 会在铜区中心判成「出不来」。 + for i in range(len(rects) - 1): + ra, rb = rects[i][1], rects[i + 1][1] + ax = min(max((rb[0] + rb[2]) / 2.0, ra[0] + 1.0), ra[2] - 1.0) + ay = min(max((rb[1] + rb[3]) / 2.0, ra[1] + 1.0), ra[3] - 1.0) + bx = min(max(ax, rb[0] + 1.0), rb[2] - 1.0) + by = min(max(ay, rb[1] + 1.0), rb[3] - 1.0) + bridges.append((1, round(ax, 3), round(ay, 3), round(bx, 3), round(by, 3), + RT.WIDTH.get(net, RT.W_DEFAULT), net)) + if out: + bypad[net] = out + virt + else: + bypad.pop(net, None) + print(u' 软铺铜 %-9s %d 块 吸收 %2d 只脚，区外 %2d 只（每只一个落点）+ %d 条固定铜桥' + % (net, len(rects), len(ins), len(out), len(rects) - 1)) + return bridges + + +def wall_build(): + u"""`+3V3` 槽墙之间的**底层桥**：按构造画，不走 A*。 + + ⛔ 为什么必须是底层：每个槽的 `SDA_i`/`SCL_i` 在北排 x 75/76，要一路往西去 `U35`， + 十根线全都要横穿 x 70.6~73.4 那一条。顶层连墙 = 把它们拦腰截断， + 而**布线器只会报「没布通」，DRC 与铺铜管理器一个字都不说**。 + ⚠ 缝在地平面上：每段 9.5 mm、宽 0.8，都在 x=72。D± 全在 x<66， + 不碰方案 §6.2 第 1 条「D± 走廊下方一刀不许割」。 + """ + bs, vs = B.wall3v3_bridges() + segs = [(2, x, y0, x, y1, w, '+3V3') for (x, y0, y1, w) in bs] + vias = [(x, y, '+3V3') for (x, y) in vs] + return segs, vias + + +TAP_W = 0.30 # PWR9A 规则下限；这一脚只走栅极电容的充放电电流 +TAP_Y = 0.70 # 贴板边：边距 0.4 + 半线宽 0.15 + 0.15 余量 + + +def gate_tap(pads): + u"""`C1.1`（VIN_FUSED）→ `DZ1.1` 的固定细线：沿板边从 DZ1 正下方穿过去。 + + ⛔ 为什么不交给 A*： + ① `VIN_FUSED` 是 2.0 mm 的 9 A 网，0402 的焊盘周围找不到一个能起步的格点 + （实测「VIN_FUSED: C1.1 出不来」）；而这一脚本来只需要细线。 + ② 板边那条缝在 0.25 网格上表示不出来：板边膨胀到 0.76、DZ1 下沿膨胀到 0.87， + 格点 0.75 / 1.0 两头都被判死，而真实几何下 0.30 的线放在 y=0.70 两边都有余量。 + 拓扑：GATE 从 Q1.4 向南接 DZ1.2，再**绕 C1 北侧**接 C1.2 / R1.2；这根线在南侧， + 两者不相交，于是 C1.1 不会被 GATE 围在板边（单层平面上唯一的解）。 + """ + def pad(ref, pin): + hit = [q for q in pads if q[0] == ref and str(q[1]) == pin and q[6] == 1] + if len(hit) != 1 or hit[0][7] != 'VIN_FUSED': + raise RuntimeError(u'%s.%s 应是唯一的顶层 VIN_FUSED 焊盘' % (ref, pin)) + return hit[0] + + c, d = pad('C1', '1'), pad('DZ1', '1') + segs = _poly('VIN_FUSED', [(c[2], c[3]), (c[2], TAP_Y), (d[2], TAP_Y), (d[2], d[3])], TAP_W) + bad = dp_obstacle_check(segs, pads, nets=('VIN_FUSED',)) + for s in segs: + if min(s[2], s[4]) - s[5] / 2.0 < RT.EDGE_CLR - 1e-6: + bad.append(u'VIN_FUSED 细线离南板边不足 %.2f' % RT.EDGE_CLR) + for n, (hx, hy) in B.MOUNT_HOLES.items(): + e = (1, hx, hy, hx, hy, 0, '#') + if _seg_dist(s, e) - B.HOLE_D / 2.0 - s[5] / 2.0 < 0.3: + bad.append(u'VIN_FUSED 细线压到安装孔 %s' % n) + if bad: + raise RuntimeError(u'C1.1 固定细线几何校验不过：' + u'；'.join(bad)) + return segs, c + + +def wall_absorb(bypad): + u"""`+3V3` 槽墙盖住的 15 只槽脚从 A* 摘掉，墙外的脚每只给一个落点。 + + ⛔⛔ 落点的位号必须是 `WALL`（`router.PRE_WIRED`）：那才是「这几个落点已经被铜 + 连在一起了」的意思，Prim 会把它们**全部当种子**，一只脚就近接到墙上就完事。 + 不带这个标记的话（`rail_absorb` 那种普通落点），Prim 把落点也当普通节点， + **逼 A* 在墙上再布线把落点串起来** —— 实测 `+3V3` 从最北那个落点一路蜿蜒到 + 板子最南（100 mm，横穿五条走廊，压在 I²C 的出脚道上），而布线器只报「布通了」。 + ⚠ 十个落点（每块墙的南北两个走廊帽）：走廊帽整宽 2.8 mm，出口最多； + 针排那三段窄，落点放上去会「挑得出来、引出脚发不出来」。 + """ + ps = bypad.get('+3V3') + if not ps: + return + rects = B.wall3v3_rects() + + def inside(q): + return any(r[0] <= q[2] <= r[2] and r[1] <= q[3] <= r[3] for r in rects) + + ins = [q for q in ps if inside(q)] + out = [q for q in ps if not inside(q)] + if not ins: + return + caps = [r for r in rects if r[2] - r[0] > 2.0 and r[3] - r[1] < 2.0] + virt = [['WALL', 'wall', round((r[0] + r[2]) / 2.0, 3), round((r[1] + r[3]) / 2.0, 3), + 0.6, 0.6, 1, '+3V3', 'RECT'] for r in caps] + bypad['+3V3'] = out + virt + print(u' 3V3 槽墙 %d 块 吸收 %2d 只槽脚，墙外 %2d 只 + %d 个 WALL 落点（互相不布线）' + % (len(rects), len(ins), len(out), len(virt))) + + +def bus_absorb(bypad): + u"""12V 干道已连成一块铜：覆盖的插槽脚不再参与 A*。""" + ps = bypad.get('+12V') + if not ps: + return + rects = B.bus_rects() + + def inside(q): + x0, y0 = q[2] - q[4] / 2.0, q[3] - q[5] / 2.0 + x1, y1 = q[2] + q[4] / 2.0, q[3] + q[5] / 2.0 + return any(r[0] <= x0 and x1 <= r[2] and r[1] <= y0 and y1 <= r[3] for r in rects) + + ins = [q for q in ps if inside(q)] + out = [q for q in ps if q not in ins] + r = B.BUS_W + landing = ['WALL', '12v-bus', round((r[0] + r[2]) / 2.0, 3), + round(r[1] + 2.0, 3), 0.8, 0.8, 1, '+12V', 'RECT'] + bypad['+12V'] = out + [landing] + print(u' 12V 干道 %d 块 吸收 %2d 只槽脚，干道外 %2d 只 + 1 个 WALL 落点' + % (len(rects), len(ins), len(out))) + + +def balance_numbered_pairs(segs, esc, pairs=None, prefer_horizontal=False): + u"""在较短线的专属车道内加 45° 微蛇形，将对内长差压到 1 mm 以内。 + + 优先使用最长的直线段；若竖向段容不下（当前 USB3 只有 3 mm），就使用 + 横向干线。补偿始终朝远离伴线的一侧展开，避免侵入两线之间的耦合间隙。 + """ + tol = RB.DIFF['differentailPairLenTolerMax'] if hasattr(RB, 'DIFF') else 1.0 + + def length(net): + return sum(math.hypot(s[3] - s[1], s[4] - s[2]) + for s in list(esc) + segs if s[6] == net) + + targets = pairs or [('USB%d_DP' % i, 'USB%d_DM' % i) + for i in range(1, B.SLOT_N + 1)] + for dp, dm in targets: + ld, lm = length(dp), length(dm) + short, delta = (dp, lm - ld) if ld < lm else (dm, ld - lm) + if delta <= tol: + continue + # 只补到 0.25 mm 余量，避免网格/小数误差又越过 1 mm。 + need = delta - 0.25 + total_a = need / (2.0 * (math.sqrt(2.0) - 1.0)) + amps = [] + left = total_a + while left > 1e-6: + a = min(0.70, left) + amps.append(a) + left -= a + used = 2.0 * sum(amps) + # 两端各留 0.2 mm 直线，避免补偿尖点正好落在转角上。 + cand = [] + for k, s in enumerate(segs): + if s[6] != short: + continue + dx, dy = abs(s[3] - s[1]), abs(s[4] - s[2]) + span = max(dx, dy) + if min(dx, dy) < 1e-6 and span >= used + 0.4: + axis = 0 if dy > dx else 1 + preferred = 1 if prefer_horizontal else 0 + cand.append((0 if axis == preferred else 1, -span, axis, k, s)) + if not cand: + raise RuntimeError(u'%s 没有可容纳 %.2f mm 等长段的直线车道' % (short, used)) + _pref, neg_span, _axis, k, s = min(cand) + _span = -neg_span + partner = dm if short == dp else dp + repl = [] + if _axis == 0: # 竖向主线，补偿在 x 方向展开 + pp = [(abs(q[4] - q[2]), q[1]) for q in segs + if q[6] == partner and abs(q[3] - q[1]) < 1e-6] + partner_coord = max(pp)[1] if pp else s[1] + away = 1.0 if s[1] > partner_coord else -1.0 + sign = 1.0 if s[4] > s[2] else -1.0 + x, y = s[1], s[2] + sign * ((_span - used) / 2.0) + if abs(y - s[2]) > 1e-6: + repl.append((s[0], x, s[2], x, y, s[5], s[6])) + for a in amps: + y2 = y + sign * a + repl.append((s[0], x, y, x + away * a, y2, s[5], s[6])) + y3 = y2 + sign * a + repl.append((s[0], x + away * a, y2, x, y3, s[5], s[6])) + y = y3 + if abs(y - s[4]) > 1e-6: + repl.append((s[0], x, y, s[3], s[4], s[5], s[6])) + else: # 横向主线，补偿在 y 方向展开 + pp = [(abs(q[3] - q[1]), q[2]) for q in segs + if q[6] == partner and abs(q[4] - q[2]) < 1e-6] + partner_coord = max(pp)[1] if pp else s[2] + away = 1.0 if s[2] > partner_coord else -1.0 + sign = 1.0 if s[3] > s[1] else -1.0 + x, y = s[1] + sign * ((_span - used) / 2.0), s[2] + if abs(x - s[1]) > 1e-6: + repl.append((s[0], s[1], y, x, y, s[5], s[6])) + for a in amps: + x2 = x + sign * a + repl.append((s[0], x, y, x2, y + away * a, s[5], s[6])) + x3 = x2 + sign * a + repl.append((s[0], x2, y + away * a, x3, y, s[5], s[6])) + x = x3 + if abs(x - s[3]) > 1e-6: + repl.append((s[0], x, y, s[3], s[4], s[5], s[6])) + segs[k:k + 1] = repl + + +def dp_build(bypad, esc=()): + u"""**按构造**画五对编号 D±（不走 A*）。 + + ⛔ 为什么不用 A*：换了七种办法（车道宽度 3.2/4.5、先后顺序、导引线、分道扇出、 + 半条道、降线宽、去掉 HUG）都是「一对里只进得去一根」。读占用图看到的真相是： + **先布的那一根自己蜿蜒**，4.5 mm 的车道被它占掉 3.5，第二根再也挤不进去； + 而 A* 没有「贴着伙伴走」的概念。 + ⇒ 几何已经完全规则（通道空、走廊空、每对一条车道），路径本来就是一个 L： + `U32` 落点 →（车道里竖着走）→（走廊里横着走）→ 槽侧落点。直接画。 + ⚠ DM 走靠焊盘那条横线（+1.5）、DP 走外面那条（+3.0）；通道里谁东谁西由 + `hub_escape` 按走向定（后转弯的靠西），两者配合才不交叉。 + """ + segs = [] + for i in range(1, B.SLOT_N + 1): + cor = B.usb_corridor(i) + for suf in ('_DP', '_DM'): + net = 'USB%d%s' % (i, suf) + ps = bypad.get(net) or [] + a = [q for q in ps if q[0] == 'U32'] + b = [q for q in ps if q[0] == B.USB_SLOT_REF[i]] + if not a or not b: + print(u' [!] %s 少了落点（U32 %d / 槽 %d）' % (net, len(a), len(b))) + continue + x0, y0 = a[0][2], a[0][3] + x1, y1 = b[0][2], b[0][3] + # ⛔ 横跑段的 y 必须**从走廊南沿算**，不能从逃逸落点往上加： + # 落点一深（ESC_SLOT）就顶出过道 —— 实测 USB5 跑到 y 113.4/114.9， + # 而给它留的 `DP_N_LANE` 只有 108.74~112.74，直接从风扇块 + # （C738 / R3 / L2 / L3）身上压过去，DRC 报 34 条「焊盘到导线 0 mil」。 + # 两条横线间距 2.0：DM 的末段竖线顶到落点（走廊南沿 + ESC_SLOT）， + # DP 的横线必须比它再高 1.2 才够净距（实测 2.7 时只有 0.9，差 0.3）。 + yr = pair_run_y(i, net) + w = DIFF_W + if abs(yr - y0) > 1e-6: + segs.append((1, x0, y0, x0, yr, w, net)) + if abs(x1 - x0) > 1e-6: + segs.append((1, x0, yr, x1, yr, w, net)) + if abs(y1 - yr) > 1e-6: + segs.append((1, x1, yr, x1, y1, w, net)) + balance_numbered_pairs(segs, esc) + bad = dp_selfcheck(segs + [e for e in esc]) + if bad: + raise RuntimeError(u'构造出来的 D± 净距不过：' + u'；'.join(bad[:8])) + return segs + + +def _poly(net, pts, width): + return [(1, a[0], a[1], b[0], b[1], width, net) + for a, b in zip(pts, pts[1:]) + if abs(a[0] - b[0]) + abs(a[1] - b[1]) > 1e-9] + + +def aux_dp_build(bypad): + u"""按空走廊构造 USB6 与上行 USB，不再让单网 A* 抢占伙伴的通道。""" + def point(net, ref, pin=None): + hit = [q for q in bypad.get(net, []) + if q[0] == ref and (pin is None or str(q[1]) == pin)] + if len(hit) != 1: + raise RuntimeError(u'%s 的 %s.%s 端点数为 %d' % (net, ref, pin or '*', len(hit))) + return (hit[0][2], hit[0][3]) + + out = [] + u6dp0, u6dp1 = point('USB6_DP', 'U32'), point('USB6_DP', 'U20') + u6dm0, u6dm1 = point('USB6_DM', 'U32'), point('USB6_DM', 'U20') + # U31/RT601 从中间挡住直线；两根线成对绕其东侧，再从 U20 西侧空带北上。 + p = [(90.5, 60.75), (90.5, 69.5), (91.0, 70.0), (92.5, 72.0), + (92.5, 75.5), (90.0, 78.0), (82.0, 78.0), (80.75, 79.25), + (80.75, 110.1), (85.22, 110.1)] + m = [(92.1, 60.75), (92.1, 68.9), (92.6, 69.4), (94.1, 71.5), + (94.1, 75.5), (91.6, 79.6), (83.6, 79.6), (82.35, 80.85), + (82.35, 111.7), (85.80, 111.7)] + out += _poly('USB6_DP', [u6dp0, p[0]], 0.3) + _poly('USB6_DP', p, DIFF_W) + out += _poly('USB6_DP', [p[-1], u6dp1], 0.3) + out += _poly('USB6_DM', [u6dm0, m[0]], 0.3) + _poly('USB6_DM', m, DIFF_W) + out += _poly('USB6_DM', [m[-1], (86.82, 111.7), u6dm1], 0.3) + + updp0, updp1 = point('UP_DP', 'J23', 'launch'), point('UP_DP', 'U32') + updm0, updm1 = point('UP_DM', 'J23', 'launch'), point('UP_DM', 'U32') + # 上行对沿东板边走，避开 Hub 去耦列；两次 90 度转弯保持 1.6 mm 中心距。 + p = [(94.5, 12.5), (103.2, 12.5), (103.2, 61.5)] + m = [(96.1, 14.1), (104.8, 14.1), (104.8, 63.1)] + out += _poly('UP_DP', [updp0, p[0]], 0.3) + _poly('UP_DP', p, DIFF_W) + out += _poly('UP_DP', [p[-1], updp1], 0.3) + out += _poly('UP_DM', [updm0, m[0]], 0.3) + _poly('UP_DM', m, DIFF_W) + out += _poly('UP_DM', [m[-1], updm1], 0.3) + + # Type-C 的 B6/B7 也要并回同名网络。DP 从焊盘北侧绕，DM 从南侧绕，互不交叉。 + b6 = point('UP_DP', 'J23', 'B6') + b7 = point('UP_DM', 'J23', 'B7') + out += _poly('UP_DP', [b6, (95.321, 8.547), (96.5, 9.25), + (96.5, 10.25), (96.25, 12.5), (94.5, 12.5)], 0.3) + out += _poly('UP_DM', [b7, (93.823, 6.3), (94.821, 6.3), + (94.821, 7.597)], ESC_W) + return out + + +def _seg_dist(a, b): + u"""两段线段之间的最短距离。""" + import math as _m + + def p2s(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0.0 if L2 < 1e-12 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2)) + return _m.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + + return min(p2s(a[1], a[2], b[1], b[2], b[3], b[4]), p2s(a[3], a[4], b[1], b[2], b[3], b[4]), + p2s(b[1], b[2], a[1], a[2], a[3], a[4]), p2s(b[3], b[4], a[1], a[2], a[3], a[4])) + + +def dp_selfcheck(segs, clr=0.2): + u"""构造出来的 D± 之间**净距自查**。 + + ⛔ 按构造画的东西**没有 A* 的占用图兜底**，几何必须自己查：第一版画完直接下发， + DRC 才发现不同对之间 0 mil（车道顺序排反、扇形横线横穿别人的竖段）。 + """ + bad = [] + for i in range(len(segs)): + a = segs[i] + for j in range(i + 1, len(segs)): + b = segs[j] + if a[6] == b[6] or a[0] != b[0]: + continue + need = clr + a[5] / 2.0 + b[5] / 2.0 + d = _seg_dist(a, b) + if d < need - 1e-6: + bad.append(u'%s(%.2f,%.2f→%.2f,%.2f) 与 %s(%.2f,%.2f→%.2f,%.2f) 净距 %.3f < %.3f' + % (a[6], a[1], a[2], a[3], a[4], + b[6], b[1], b[2], b[3], b[4], + d - a[5] / 2.0 - b[5] / 2.0, clr)) + return bad + + +def _seg_rect_dist(s, r): + if ((r[0] <= s[1] <= r[2] and r[1] <= s[2] <= r[3]) or + (r[0] <= s[3] <= r[2] and r[1] <= s[4] <= r[3])): + return 0.0 + edges = [(1, r[0], r[1], r[2], r[1], 0, '#'), + (1, r[2], r[1], r[2], r[3], 0, '#'), + (1, r[2], r[3], r[0], r[3], 0, '#'), + (1, r[0], r[3], r[0], r[1], 0, '#')] + return min(_seg_dist(s, e) for e in edges) + + +def dp_obstacle_check(segs, pads, clr=0.2, nets=None): + u"""构造线没有 A* 占用图兜底，必须显式检查焊盘和硬功率铜。`nets` 缺省 = 七对 D±。""" + bad = [] + for s in segs: + if s[6] not in (nets or DP_NETS): + continue + for q in pads: + if q[6] != s[0] or q[7] == s[6]: + continue + r = (q[2] - q[4] / 2.0, q[3] - q[5] / 2.0, + q[2] + q[4] / 2.0, q[3] + q[5] / 2.0) + d = _seg_rect_dist(s, r) - s[5] / 2.0 + if d < clr - 1e-6: + bad.append(u'%s(%.2f,%.2f→%.2f,%.2f) vs %s.%s(%s) 净距 %.3f' % + (s[6], s[1], s[2], s[3], s[4], + q[0], q[1], q[7] or 'NC', d)) + for net, r in pour_blocks(): + if net == s[6]: + continue + d = _seg_rect_dist(s, r) - s[5] / 2.0 + if d < clr - 1e-6: + bad.append(u'%s 切入 %s 功率铜（净距 %.3f）' % (s[6], net, d)) + return sorted(set(bad)) + + +# ── 主流程 ─────────────────────────────────────────────────────────────── +def plan_all(priority=()): + pads = apply_route_fix(split_th(RT.load_pads())) + tb = topology_check(pads) + if tb: + raise RuntimeError(u'底板拓扑自检不过：' + u'；'.join(tb)) + board_vias = load_board_vias() + th = sum(1 for p in pads if str(p[1]).endswith(BOT_SUFFIX)) + print(u'板上已有过孔 %d 个；通孔焊盘 %d 只（已拆成两层）' % (len(board_vias), th)) + bypad = {} + for p in pads: + if not p[7] or p[7] in RT.SKIP or str(p[1]).endswith(BOT_SUFFIX): + continue + bypad.setdefault(p[7], []).append(p) + rail_segs = rail_absorb(bypad) + bus_absorb(bypad) + wall_absorb(bypad) + segs, vias, logs = list(rail_segs), [], [] + # `+3V3` 槽墙之间的底层桥：**最先画**，好让后面所有网都把它当障碍绕开 + wsegs, wvias = wall_build() + segs += wsegs + vias += wvias + # C1.1 → DZ1.1 的固定细线：同样最先画、不许拆，C1.1 从 A* 里摘掉（见 gate_tap） + tsegs, tpad = gate_tap(pads) + segs += tsegs + bypad['VIN_FUSED'] = [q for q in bypad.get('VIN_FUSED', []) + if not (q[0] == tpad[0] and str(q[1]) == str(tpad[1]))] + print(u' C1.1 → DZ1.1：板边固定细线 %d 段 %.2f mm' % (len(tsegs), TAP_W)) + # 地岛 / GATE 缺口里 GND 贴片脚的专用过孔（pour_base.GND_PAD_VIAS）：布线器必须先看见它们， + # 否则信号线会从孔位上压过去，缝合那一步再把孔打上就是短路 + import pour_base as PB + gv = [(x, y, 'GND') for (x, y) in PB.gnd_pad_vias()[1]] + vias += gv + print(u' GND 贴片脚专用过孔 %d 个（D1.2 / C5.1 / R1.1）' % len(gv)) + + # `U32` 的十四只 D± 脚换成虚拟起跑点（西排 10 + 北排 4）。 + esc, launch = hub_escape(pads) + aux_esc, aux_launch, aux_vias = aux_hub_escape(pads) + esc += aux_esc + vias += aux_vias + for k, v in aux_launch.items(): + launch.setdefault(k, []).extend(v) + # 槽针 / U20 / USB-C 那三处脚距太密的，也各接一段逃逸（见 pair_escape） + slot_refs = {} + for i, ref in enumerate(SLOT_REFS, start=1): + slot_refs[ref] = {'USB%d_DP' % i, 'USB%d_DM' % i} + more = [pair_escape(pads, slot_refs, 'S'), + pair_escape(pads, {'U20': {'USB6_DP', 'USB6_DM'}}, 'N'), + pair_escape(pads, {'J23': {'UP_DP', 'UP_DM'}}, 'N')] + for e2, l2 in more: + esc += e2 + for k, v in l2.items(): + launch.setdefault(k, []).extend(v) + segs += esc + j23_escape_pin = {'UP_DP': 'A6', 'UP_DM': 'A7'} + for net in DP_NETS: + drop = {'U32'} | set(SLOT_REFS) | {'U20', 'J23'} + keep = [q for q in bypad.get(net, []) if q[0] not in drop] + # Type-C 同名的另一只 D± 脚也必须接上；只摘掉已经由 + # pair_escape 连到 launch 的 A6/A7，保留 B6/B7 给 A* 做局部交叉。 + if net in j23_escape_pin: + keep += [q for q in bypad.get(net, []) + if q[0] == 'J23' and str(q[1]) != j23_escape_pin[net]] + bypad[net] = keep + launch.get(net, []) + print(u' U32 逃逸扇形：%d 段 %.2f mm 细线（西排 10 只进东侧车道，北排 4 只向北）' + % (len(esc), ESC_W)) + + # ⛔ **第一相把「焊盘过路费」降到 2**（默认 10）：D± 是第一批布的，没有「后面的网」 + # 要保护，收下来只会让它们绕开满板的焊盘光环而蜿蜒（M8 实测一对布出 40 段）。 + _pad_pen = RT.PAD_PEN + RT.PAD_PEN = 2 + + # ── 第一相：七对 D± 全部按构造画，避免逐网 A* 抢占伙伴通道 ───────────── + dpb = dp_build(bypad, esc) + segs += dpb + print(u' 五对编号 D±：按构造画了 %d 段（不走 A*，见 dp_build）' % len(dpb)) + aux = aux_dp_build(bypad) + balance_numbered_pairs(aux, esc, + [('USB6_DP', 'USB6_DM'), ('UP_DP', 'UP_DM')], + prefer_horizontal=True) + segs += aux + print(u' USB6/上行 D±：按构造画了 %d 段（不走单网 A*）' % len(aux)) + dbad = dp_selfcheck([s for s in segs if s[6] in DP_NETS]) + dbad += dp_obstacle_check([s for s in segs if s[6] in DP_NETS], pads) + if dbad: + raise RuntimeError(u'构造 D± 几何校验不过（%d 条）：%s' % + (len(dbad), u'；'.join(dbad[:80]))) + RT.PAD_PEN = _pad_pen + _DIFF_SEGS[:] = [s for s in segs if s[0] == 1] + print(u'第一相：D± %d 段，底层 D± 走廊封死 %.1f mm' % (len(segs), DIFF_KEEP)) + + if '--dp-only' in sys.argv: + return segs, vias, logs + + # ── 第二相：其余全部 ─────────────────────────────────────────────── + rest = set(bypad) - set(DP_NETS) + RT.AUTO_CACHE.clear() + blocked = list(pour_blocks()) + blocked += [('#ant', r) for r in ant_blocks(0.0)] + # 有优先集时只处理上一版失败网；给已成功网络提前铺短铜只会占掉共享通道。 + direct_nets = rest & set(priority) if priority else rest + local_map = {net: bypad[net] for net in direct_nets} + dsegs, merged = RT.direct_links(pads, local_map, segs, vias, blocked_rects=blocked) + segs += dsegs + for net, groups in merged.items(): + drop = set() + for group in groups: + drop |= set(list(group)[1:]) + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) not in drop] + print(u' 普通信号短直连：%d 段 / %d 个网络（硬功率铜与天线禁区已参与判定）' + % (len(dsegs), len(merged))) + fixed_s, fixed_v = len(segs), len(vias) + logs += RT.route_groups(bypad, pads, segs, vias, board_vias, {}, + priority=priority, only=rest) + if logs and '--repair' in sys.argv: + print(u' 首轮 %d 条没搞定，进入拆线重布' % len(logs)) + segs, vias, logs = rip_repair(bypad, pads, segs, vias, logs, board_vias, + rest, fixed_s, fixed_v) + return segs, vias, logs + + +def pour_nets(): + u"""靠铜面 / 铜墙成网的网络：它们的焊盘本来就没有线，几何连通性判据不适用。""" + import pour_base as PB + out = {net for (_n, net, _r) in PB.RAILS} + out |= {net for (net, _r) in pour_blocks()} + return out | {'+12V', '+3V3'} + + +def rip_repair(bypad, pads, segs, vias, logs, board_vias, rest, fixed_s, fixed_v): + u"""把 `router.repair`（拆线重布）接到底板上。 + + ⛔ 不能直接把整张 `bypad` 交给它，有两处会静默出错： + ① D± 七对也在 `bypad` 里（落点形式）。它们的铜是第一相按构造画的、在固定段里， + 一旦被选为「挡路的网」，repair 会用 A* 在落点之间**再布一遍** —— 板上多出 + 一根同名线，净距自查不会报（同网）。⇒ 只交 `rest`。 + ② repair 用 `check_connected` 验收，它按「每只焊盘都要有线端」判。 + 铜面 / 铜墙网（+3V3、+12V、各 RAIL）的焊盘本来就没线，会被判断线 —— + 只会让重布更难被接受，不会放进坏结果，但等于这些网永远拆不动。 + ⇒ 验收时去掉铜面网、通孔焊盘的底层副本和单脚网。 + 前 `fixed_s` / `fixed_v` 条（槽墙桥、逃逸扇形、D±、直连）一根都不拆。 + """ + import time + sub = {n: bypad[n] for n in rest if n in bypad} + skip = pour_nets() | set(DP_NETS) + cnt = {} + for q in pads: + cnt[q[7]] = cnt.get(q[7], 0) + 1 + chk_pads = [q for q in pads if q[7] in sub and q[7] not in skip and cnt[q[7]] >= 2 + and not str(q[1]).endswith(BOT_SUFFIX)] + orig_chk, orig_rg = RT.check_connected, RT.route_groups + t0, n = time.time(), [0] + + def chk(_pads, s, v): + return orig_chk(chk_pads, s, v) + + def rg(*a, **k): + n[0] += 1 + out = orig_rg(*a, **k) + print(u' 拆线重布 #%d：重布 %d 个网，失败 %d 条（累计 %.0f s）' + % (n[0], len(k.get('only') or ()), len(out), time.time() - t0)) + sys.stdout.flush() + return out + + RT.check_connected, RT.route_groups = chk, rg + try: + return RT.repair(sub, pads, segs, vias, logs, board_vias, {}, fixed_s, fixed_v) + finally: + RT.check_connected, RT.route_groups = orig_chk, orig_rg + + +def report(segs, vias, logs): + tot = sum(math.hypot(s[3] - s[1], s[4] - s[2]) for s in segs) + bot = sum(math.hypot(s[3] - s[1], s[4] - s[2]) for s in segs if s[0] == 2) + print(u'导线 %d 段 / 总长 %.1f mm（底层 %.1f mm = %.0f%%）/ 过孔 %d' + % (len(segs), tot, bot, 100.0 * bot / max(tot, 1e-9), len(vias))) + nets = set(s[6] for s in segs) + print(u'涉及 %d 个网络' % len(nets)) + # D± 长度：每个网自己的铜有多长 + print(u'差分对实测铜长:') + for name, dp, dm in RB.PAIRS: + for n in (dp, dm): + L = sum(math.hypot(s[3] - s[1], s[4] - s[2]) for s in segs if s[6] == n) + nb = sum(1 for s in segs if s[6] == n and s[0] == 2) + print(u' %-9s %6.1f mm%s' % (n, L, u' ⚠ 有 %d 段在底层' % nb if nb else u'')) + if logs: + print(u'[!] %d 条没搞定:' % len(logs)) + for m in logs[:40]: + print(u' ' + m) + + +if __name__ == '__main__': + if '--clear' in sys.argv: + RT.clear_mine() + sys.exit(0) + if '--snapshot-vias' in sys.argv: + print(u'底板既有过孔快照：%d 个 -> %s' % (len(load_board_vias()), BOARD_VIAS)) + sys.exit(0) + c = json.load(io.open(CACHE, encoding='utf-8')) if os.path.exists(CACHE) else {} + cache_ok = (c.get('schema') == CACHE_SCHEMA and c.get('slot_rot') == B.SLOT_ROT and + c.get('usb_slot_ref') == {str(k): v for k, v in B.USB_SLOT_REF.items()}) + if '--replan' not in sys.argv and cache_ok: + segs, vias, logs = [tuple(s) for s in c['segs']], [tuple(v) for v in c['vias']], c['logs'] + print(u'（用缓存 _base_routes.json）') + else: + if os.path.exists(CACHE) and not cache_ok: + print(u'（忽略 rot=180 / 西侧 D± 旧缓存，按当前拓扑重算）') + best, prio = None, set() + # 用上一轮的失败网络给新一轮排序，避免为了得到第二轮 + # 优先级而重算一遍完全相同的首轮。 + if '--priority-cache' in sys.argv and os.path.exists(CACHE): + old = json.load(io.open(CACHE, encoding='utf-8')) + prio = set(RT._msg_net(m) for m in old.get('logs', [])) + print(u'（用上轮 %d 条失败记录优先排网）' % len(old.get('logs', []))) + # `--passes N`：改动布线模型时先跑一轮拿信号，别一上来就等四轮（一轮 ~20 min） + if '--passes' in sys.argv: + RT.PASSES = int(sys.argv[sys.argv.index('--passes') + 1]) + for it in range(RT.PASSES): + segs, vias, logs = plan_all(prio) + print(u' 第 %d 轮：%d 条没搞定' % (it + 1, len(logs))) + if best is None or len(logs) < len(best[2]): + best = (segs, vias, logs) + if not logs: + break + prio |= set(RT._msg_net(m) for m in logs) + segs, vias, logs = best + if '--dp-only' not in sys.argv: + io.open(CACHE, 'w', encoding='utf-8').write(json.dumps({ + 'schema': CACHE_SCHEMA, 'slot_rot': B.SLOT_ROT, + 'usb_slot_ref': B.USB_SLOT_REF, + 'segs': segs, 'vias': vias, 'logs': logs}, ensure_ascii=False)) + report(segs, vias, logs) + if '--push' in sys.argv: + if logs: + sys.exit(u'!! 仍有 %d 条未布通，拒绝下发不完整路由' % len(logs)) + RT.push(segs, vias) diff --git a/.claude/r2/archive_base2L/router.py b/.claude/r2/archive_base2L/router.py new file mode 100644 index 0000000..fdb89bb --- /dev/null +++ b/.claude/r2/archive_base2L/router.py @@ -0,0 +1,2118 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 的**自建布线器**（M4c-4）。 + + /c/Python314/python .claude/r2/router.py # 只算 + 打印，不下发 + /c/Python314/python .claude/r2/router.py --push # 下发导线 + 过孔 + /c/Python314/python .claude/r2/router.py --clear # 清掉本脚本布的线（保留 GND 缝合过孔） + +## 为什么要自己写 + +嘉立创 EDA 的自动布线在这台客户端上**跑不出一根铜**（方案 §24.6）： +`pcb_Document.autoRouting` 这个 API 根本不存在；GUI 的对话框能开能配， +点「运行」之后立刻关闭、铜线数 0，不报错不弹进度。⇒ 只能自己布。 + +## 做法 + +**0.25 mm 网格 + 8 邻接 A\\***，两层（L1 顶 / L4 底），换层收过孔代价。 + +- 网格选 0.25 是因为**金手指 1.0 mm 间距正好落在格点上**（32.5 / 0.25 = 130）， + 64 根指的扇出不用做特殊处理。 +- 障碍按「导线半宽 + 净距」膨胀 ⇒ 一条 0.2 mm 的线会把 0.25 外的相邻格点也占掉， + 自动保证平行线中心距 ≥ 0.5 mm。**不用另外写间距检查**。 +- 焊盘中心大多不在格点上（摆位是 0.001 精度），所以每个焊盘先出一小段 + **引出脚**（pad 中心 → 最近的可用格点），再交给 A\\*。 + +## ⛔ 三条硬约束（写死在代码里，不是注释） + +1. **只准布 L1 / L4**。L2 是「完整地平面，不许割断」（§7.1），L3 是 `VO_P` / `+12V` 的岛。 +2. **金手指区（y < 6.0）除了 J1 自己的引出脚，一根线都不许有** —— + 那一带外层铜的邻居是 0.3 mm 间距的指，蹭上就是短路，而 DRC 只报间距不报"接错了指"。 +3. **缺口（防呆键）四周 0.5 mm 内不许有铜**，缺口本身是铣穿的。 + +## `GND` / `VO_P` / `+12V` 不走 A\\*，走铜面 + +- `GND`：顶/底/L2/L3 四块铜面 + 196 个缝合过孔已经接好；**只有 J1 的 39 根地指** + 在铜面下沿（y=11.5）以下够不着，给它们各出一段引出脚 + 一个过孔。 +- `VO_P`：L3 上有整块 `VO-L3` 岛（4 A 走平面，比走线好）。每个 `VO_P` 焊盘 + 出一小段引出脚 + 一个过孔扎进岛里。 +- `+12V`：`V12-L3` 岛在功率列上半段，够不着金手指。金手指那五根 + F1 之间 + 用底层一条 0.8 mm 的走廊连过去，两端各一个过孔。 +""" +import heapq +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 +import fp_edge # noqa: E402 +import pcb_pour as P # noqa: E402 +import b4_edge # noqa: E402 针位表的唯一事实来源 + +PCB = B.PCB +MIL = B.MIL +PADS = os.path.join(HERE, '_blade_pads.json') + +G = 0.25 # 网格（mm） +NX = int(round(B.BW / G)) + 1 +NY = int(round(B.BH / G)) + 1 +# 布线用的净距。设计规则是 0.15；这里留一点余量给网格吸附。 +# ⚠ 0.18 -> 0.16：通道宽度 = 线宽 + 2×净距，0.2+0.36=0.56 在这块板上处处卡壳， +# 0.15+0.32=0.47 才挤得过去。仍高于规则的 0.15。 +CLR = 0.16 +STUB_CLR = 0.15 # 引出脚（缩窄段）用规则值本身，见 pad_nodes +EDGE_CLR = 0.35 # 到板边 / 缺口 +# ⚠ M6（2026-09-09）0.6/0.3 -> 0.5/0.25：细间距扇出的过孔要能塞进 0.5 mm 节距的 +# 引出脚之间（0.5 − 0.25 − 0.075 = 0.175 ≥ 0.15）。规则下限 0.3/0.2，嘉立创四层做得出。 +VIA_D, VIA_HOLE = 0.6, 0.3 # `--viafan` 那一版用过 0.5/0.25，默认仍 0.6/0.3（与缓存一致） +# 换层代价（格）。⚠ 2026-09-08 器件翻面之后这条注释反过来了： +# 现在 **73 件在底层、顶层几乎全空**，换层代价定高了等于逼所有线挤在底层。 +# 12 格 = 3 mm 还是太贵，降到 8（= 2 mm）。 +VIA_COST = 8 +# 焊盘周围的「过路费」：半径（mm）与代价（格）。见 build_grid 末尾的说明。 +PAD_PEN_R = 0.55 +PAD_PEN = 10 +LAY = (1, 2) # 只准这两层 +FINGER_KEEP_Y = 6.0 # 金手指区上沿：A* 不许进 + +# 线宽（mm）—— 和 pcb_rules.py 的规则表对齐 +# 信号线宽。⚠ 0.2 -> 0.15：这块板的信号全是逻辑 / I²C，0.15 载流绰绰有余， +# 而 0.05 的差在 0.5~0.65 mm 间距的封装周围就是「过得去」和「过不去」的分界。 +# 规则里 PWR1A 的下限就是 0.15，嘉立创四层能做到 0.09。 +W_DEFAULT = 0.15 +WIDTH = {'+12V': 0.8, '+12V_F': 0.8, 'VO': 1.5, 'VO_P': 1.5, + '+5V': 0.6, 'VBUS': 0.6, '+3V3': 0.4} +WIDTH_AUTO = {'SW': 2.0, 'VO_F': 1.5} # 自动命名网，按 pcb_rules 的探针反查 + +# ⛔ **全局最优先布的网**（跨线宽档，比宽线还先）。 +# `priority` 只在同一档宽度里排序，对「这一档整个被前面几档挤没了」无能为力； +# `FIRST_NETS` 是真的第一个布。BOOT 当初就是靠它解决的。 +# ⇒ 把**已知难布的**全放进来：难的先挑路，容易的绕着走。 +FIRST_NETS = ( + '$1N138', '$1N126', # BOOT / FB：Buck 的命门 + # ⛔ M6（2026-09-09）：这五个网的焊盘会被**自家邻脚的引出脚**封死 —— + # U2.15 被 EFUSE_EN 的孔 (89.5,31) 卡到只剩 0.04 mm、U2.17 被 $1N158 的斜线拦、 + # U2.2 被 $1N164 的孔拦；R16.1 / R8.2 四面是别的网的过孔。手工绕都绕不出来 + # （+3V3 的 y=30.75 母线加缝合孔那一排把口袋封死）。只能让它们**最先**布。 + # ⇒ 试过把它们排到最前面：这五个通了，但换来 20 处别的没通（EFUSE_EN/$1N164/ +# $1N158 的 U2 脚、KEY_VUP/VDN 的 U4 脚反过来被封死）。**不是顺序问题，是 U2/U4 +# 周围一共就那么几个出口**。默认不排前（留着这行注释别再试一遍）。 + # ⚠ M7：`KEY_PWR/VUP/VDN` 三根挨着排最前面。它们接的是 `U4`(TSSOP-24) 北排 + # **相邻的三只脚**（p4/p5/p6，0.65 mm 间距，不是 0.25 网格的整数倍）， + # 三根引出脚互相挤，谁后布谁出不来（实测「KEY_VUP: U4.5 没布通」）。 + 'KEY_PWR', 'KEY_VUP', 'KEY_VDN', + 'VBUS_EN', 'EFUSE_EN', '$1N164', 'USB_DPJ', '$1N151', 'SCL', + 'INT#', 'PRSNT#', '+3V3', 'VBUS', 'EFUSE_FLT', 'EFUSE_PG', + 'SDA', 'INA_ALERT', 'BUCK_PG', 'USB_DP', 'USB_THERM', 'EDL_EN', + '$1N147', '$1N158', '$1N173', '$1N136', +) +PLANE_VIA_NETS = ('VO_P',) # 靠 L3 的岛成网，只需要每个焊盘一个过孔 +ISLAND_NETS = ('VO_P', '+12V') # 连通性判据里不按「一整块铜」要求的网（靠 L3 岛） + +# ⛔ **Kelvin 取样**（方案 §7.2 第四条）：INA226 的两个取样脚必须用**专线**落到 +# `Rs1` 的两个焊盘上，不许「就近扎个孔进 VO_P 平面」—— +# 走平面的话，取样点变成了平面上的某一处，量到的是「分流电阻 + 一段铜箔」的压降， +# 电流读数会随铜箔温度漂，而**DRC / 连通性检查全过**，只有实测才发现。 +# 所以这两条在所有网络之前单独布，布完再让 VO_P 的平面过孔接管大电流。 +KELVIN = [(('U3', '9'), ('Rs1', '1'), 0.3), + (('U3', '10'), ('Rs1', '2'), 0.3)] +KELVIN_PADS = set() +for _a, _b, _w in KELVIN: + KELVIN_PADS.add(_a) + KELVIN_PADS.add(_b) +SKIP = ('GND',) # 地靠铜面，只单独处理 J1 的地指 +# ⛔ **不按焊盘封顶线宽**的网。默认空（刀片一直是全封顶的）。 +# 底板的七对 D± 必须保持 1.2 mm 的干线口径 —— 阻抗是按线宽算的（方案 §6.3）， +# 被 U32 那颗 0.5 mm 间距 QFN 的 0.30 焊盘封顶就等于把阻抗方案作废， +# 而 DRC / 连通性 / 几何四道判据**一条都不会响**。缩颈交给 `stub_w`（只缩引出脚）。 +NO_CAP = () + + +def call(js, timeout=300): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def load_pads(): + d = json.load(io.open(PADS, encoding='utf-8')) + for p in d: + if not p[4]: + p[4] = 2.2 + if not p[5]: + p[5] = 2.2 + return d + + +# ── 网格 ────────────────────────────────────────────────────────────── +def gx(x): + return int(round(x / G)) + + +def gy(y): + return int(round(y / G)) + + +def wx(i): + return round(i * G, 4) + + +def wy(j): + return round(j * G, 4) + + +class Grid(object): + u"""两层占用图。每个格点记**一个字节的归属**：0=空闲，1..250=只被这个网占着，255=被两个以上的网占着。 + + ⛔ **第一版是「blk 位图 + own 集合」，判据写错了**： + `free()` 里「本网占过」优先于「被别人占着」，而**膨胀区也算本网占过** —— + 于是一个离本网焊盘 0.93 mm、同时**落在别人焊盘正中**的格点被判成可进， + A* 就在 `U2` 的散热焊盘上打了个过孔。自算净距 −0.300，DRC 报「过孔到焊盘」。 + 换成「归属字节」之后，只要有第二个网碰过这个格点就永久变 255，谁也进不去。 + + 两套：`blk/own` 按导线半宽膨胀，`blkv/ownv` 按过孔半径膨胀（换层判据）。 + ⚠ 只有一套的话，A* 会在「线过得去、过孔过不去」的格点上换层， + DRC 报「钻孔到焊盘」，而路径本身看着完全正常。 + """ + + def __init__(self): + self.own = {l: bytearray(NX * NY) for l in LAY} + self.ownv = {l: bytearray(NX * NY) for l in LAY} + # 「过路费」层：不封死，只是让 A* 别贴着焊盘走（见 build_grid 的 PAD_PEN） + self.pen = {l: bytearray(NX * NY) for l in LAY} + # 协商式拥塞（PathFinder）用：occ = 当前有几个网压在这一格，hist = 历史拥塞代价。 + # 两者**跨宽度档共享**（它们只跟格点有关，跟线宽无关），所以是外面挂进来的引用。 + self.occ = None + self.hist = None + self._id = {} + + def nid(self, net): + u"""网名 -> 1..250 的归属号。超出就并到 250（当成同一个「其它」，偏保守）。""" + if net is None: + net = '#' + v = self._id.get(net) + if v is None: + v = len(self._id) + 1 + # ⛔ 饱和是**静默**的：溢出之后不同的网共用一个号， + # 彼此判成「同一个网」，可以随便叠着走，而检查器之外没人会报。 + if v > 250: + raise RuntimeError(u'归属号超过 250 个（%d 个不同的网/障碍），' + u'占用图会静默失效' % v) + self._id[net] = v + return v + + def idx(self, i, j): + return j * NX + i + + def _mark(self, arr, l, x0, y0, x1, y1, k, exact=False): + # ⚠ 边界默认用 floor/ceil，不用 round：round 最坏会**少封半格（0.125 mm）**， + # 那正好是 1.5 mm 宽的两根线互相压 0.02~0.19 mm 的来源。 + # + # ⛔ 但 `exact=True`（**只给焊盘用**）必须按「格点中心落在框里才算被占」： + # floor/ceil 最坏多封**一整格 0.25 mm**，而 0.65 mm 间距的 TSSOP + # 邻脚之间本来就只剩 0.34 mm 的缝 —— 多封一格这条缝就没了， + # 于是「空板上出口数 = 0」，报「U4.5 出不来」，看着像板子太挤。 + # 焊盘框传进来时**已经膨胀了 halfw（半线宽 + 净距）**，所以 + # 「中心在框外」= 线放这儿合法，不需要再留保守量。 + # 走线 / 过孔 / 板边仍然保守 —— 那几类是沿途扫描的，少封半格会真的压上。 + if exact: + i0 = max(0, int(math.ceil(x0 / G - 1e-9))) + i1 = min(NX - 1, int(math.floor(x1 / G + 1e-9))) + j0 = max(0, int(math.ceil(y0 / G - 1e-9))) + j1 = min(NY - 1, int(math.floor(y1 / G + 1e-9))) + a = arr[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + o = base + i + v = a[o] + a[o] = k if v == 0 else (v if v == k else 255) + return + i0 = max(0, int(math.floor(x0 / G))) + i1 = min(NX - 1, int(math.ceil(x1 / G))) + j0 = max(0, int(math.floor(y0 / G))) + j1 = min(NY - 1, int(math.ceil(y1 / G))) + a = arr[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + cur = a[base + i] + if cur == 0: + a[base + i] = k + elif cur != k: + a[base + i] = 255 + + def block_rect(self, l, x0, y0, x1, y1, net=None, via=False): + self._mark(self.ownv if via else self.own, l, x0, y0, x1, y1, self.nid(net)) + + def block_both(self, l, x0, y0, x1, y1, extra, net=None, exact=False): + u"""同一个障碍，分别按导线口径和过孔口径打进两张图。""" + k = self.nid(net) + self._mark(self.own, l, x0, y0, x1, y1, k, exact) + self._mark(self.ownv, l, x0 - extra, y0 - extra, x1 + extra, y1 + extra, k, exact) + + def penalize(self, l, x0, y0, x1, y1, val): + u"""给一片格点加「过路费」（不是封死）。""" + i0 = max(0, int(math.floor(x0 / G))) + i1 = min(NX - 1, int(math.ceil(x1 / G))) + j0 = max(0, int(math.floor(y0 / G))) + j1 = min(NY - 1, int(math.ceil(y1 / G))) + a = self.pen[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + o = base + i + if a[o] < val: + a[o] = val + + def reset_pen(self): + for l in LAY: + self.pen[l] = bytearray(NX * NY) + + def cost(self, l, i, j): + o = j * NX + i + c = self.pen[l][o] + if self.occ is not None: + c += PF_PRESENT[0] * self.occ[l][o] + PF_HIST_W * self.hist[l][o] + return c + + def free(self, l, i, j, net): + if i < 0 or j < 0 or i >= NX or j >= NY: + return False + v = self.own[l][self.idx(i, j)] + return v == 0 or v == self.nid(net) + + def free_via(self, i, j, net): + u"""两层都要按过孔口径让得开，才准在这里换层。""" + if i < 0 or j < 0 or i >= NX or j >= NY: + return False + k = self.nid(net) + for l in LAY: + v = self.ownv[l][self.idx(i, j)] + if v != 0 and v != k: + return False + return True + + +def load_vias(): + u"""读回板上已有的过孔（主要是 196 个 GND 缝合过孔）。 + + ⚠ **不读的话它们就不在占用图里**，A* 会直接从过孔身上压过去 —— + DRC 报「导线到过孔」，而路径看上去完全正常。 + """ + return call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" + "return (await eda.pcb_PrimitiveVia.getAll()||[])" + " .map(v=>[v.x/%s, v.y/%s, String(v.net||''), (v.diameter||%s)/%s]);" + % (PCB, MIL, MIL, VIA_D * MIL, MIL), timeout=300) + + +def build_grid(pads, halfw, vias=()): + u"""halfw = 本次布线的「线半宽 + 净距」，障碍按它膨胀； + + 同时按过孔口径（VIA_D/2 + CLR）再膨胀一份，供换层判据用。""" + g = Grid() + extra = max(0.0, VIA_D / 2.0 + CLR - halfw) + # 板边（四条带）+ 金手指区，都归到 '#edge' 这个归属号上 + for l in LAY: + m = EDGE_CLR + halfw + for (a, b, c, d) in ((-1, -1, B.BW + 1, m), + (-1, B.BH - m, B.BW + 1, B.BH + 1), + (-1, -1, m, B.BH + 1), + (B.BW - m, -1, B.BW + 1, B.BH + 1), + (-1, -1, B.BW + 1, FINGER_KEEP_Y)): + g.block_both(l, a, b, c, d, extra, net='#edge') + # 缺口 + nx0, _a, nx1, ny1 = P.notch_cut() + for l in LAY: + g.block_both(l, nx0 - halfw, 0, nx1 + halfw, ny1 + halfw, extra) + # 焊盘 + for p in pads: + ref, num, x, y, w, h, lay, net = p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7] + if lay not in LAY: + continue + # ⛔ 只按**网**标归属，别按「网+位号+脚号」—— + # 361 个焊盘会把 250 个归属号占满，之后所有网并到同一号上， + # 互相判成「同一个网」，整块板的线就叠着走了（自算净距一次报 319 条）。 + g.block_both(lay, x - w / 2 - halfw, y - h / 2 - halfw, + x + w / 2 + halfw, y + h / 2 + halfw, extra, net=net, exact=True) + # ⛔ 排线穿板槽：铣穿的内槽，两层都不许进（还要给铜到板边的净距） + for (a, b, c2, d2) in B.mill_cuts(): + k = EDGE_CLR + halfw + for l in LAY: + g.block_both(l, a - k, b - k, c2 + k, d2 + k, extra, net='#edge') + # ⛔ 主板定位孔（NPTH）：两层都不许压。孔壁到铜按 HOLE_D/2 + 净距。 + for (hx, hy) in B.phone_holes().values(): + r = B.HOLE_D / 2.0 + halfw + 0.15 + for l in LAY: + g.block_both(l, hx - r, hy - r, hx + r, hy + r, extra) + # 已有过孔（通孔，两层都占） + for (vx, vy, vnet, vd) in vias: + r = vd / 2.0 + halfw + for l in LAY: + g.block_both(l, vx - r, vy - r, vx + r, vy + r, extra, net=vnet) + # ⛔ **焊盘周围收「过路费」**。这是 28 处接不上的真正解法： + # 把失败那一刻的占用图打出来看，每个「出不来」的脚周围**全是别的网的铜** —— + # 先布的干线贴着焊盘走，顺手把后面那些脚的出口全占了。封死不行（有些线 + # 本来就得从焊盘边过），所以改成加钱：贴着焊盘走要多花 PAD_PEN， + # A* 于是优先绕开焊盘阵，把出口留给它们自己的脚。 + pen_pads(g, pads, halfw) + return g + + +def pen_pads(g, pads, halfw): + u"""给这些焊盘周围收「过路费」（先清空再打）。""" + g.reset_pen() + for p in pads: + if p[6] not in LAY: + continue + r = PAD_PEN_R + halfw + g.penalize(p[6], p[2] - p[4] / 2 - r, p[3] - p[5] / 2 - r, + p[2] + p[4] / 2 + r, p[3] + p[5] / 2 + r, PAD_PEN) + + +def block_track(g, l, x0, y0, x1, y1, halfw, net, extra=0.0): + u"""把一段已布的线打进占用图（两张都打）。""" + steps = int(max(abs(x1 - x0), abs(y1 - y0)) / (G / 2)) + 1 + for k in range(steps + 1): + t = k / float(steps) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + g.block_both(l, x - halfw, y - halfw, x + halfw, y + halfw, extra, net=net) + + +_NB8 = [(1, 0, 1.0), (-1, 0, 1.0), (0, 1, 1.0), (0, -1, 1.0), + (1, 1, 1.414), (1, -1, 1.414), (-1, 1, 1.414), (-1, -1, 1.414)] +# 每层的**优选走线方向**：'v' = 纵向（沿 y），'h' = 横向（沿 x） +LAYER_DIR = {2: 'v', 1: 'h'} # 2 = 底层 = 器件面（纵向）；1 = 顶层（横向） +CROSS_COST = 3.0 # 逆着优选方向走的倍率（斜线按分量算） + + +def _along(l, di, dj): + u"""这一步是不是顺着本层的优选方向。斜线两个分量各占一半，算「半顺」。""" + d = LAYER_DIR.get(l) + if d is None: + return True + if di and dj: # 斜线：一半顺、一半逆 + return False + return (dj != 0) if d == 'v' else (di != 0) + + +def astar(g, starts, goals, net, halfw): + u"""8 邻接 A*，两层。starts/goals 是 [(layer, i, j)]。返回 [(layer,i,j)] 路径。""" + goalset = set(goals) + if not goalset: + return None + gj = [(l, i, j) for (l, i, j) in goals] + + def h(n): + _l, i, j = n + return min(max(abs(i - a[1]), abs(j - a[2])) + + 0.414 * min(abs(i - a[1]), abs(j - a[2])) for a in gj) + + open_ = [] + gsc = {} + came = {} + for s in starts: + if not g.free(s[0], s[1], s[2], net): + continue + gsc[s] = 0.0 + heapq.heappush(open_, (h(s), s)) + # ⛔ **两层正交**：器件面（底层 L4，73 件都在这儿）**纵向**、 + # 另一面（顶层 L1，几乎空着）**横向**。2026-09-08 用户定的， + # 和 R1「顶层横向、底层纵向」是同一条约定。 + # 做法是**加钱不是封死** —— 逆着方向走要贵 `CROSS_COST` 倍， + # 于是拐弯自然变成「换层拐」，两层互补，拥塞大幅下降； + # 但引出脚那种非横即竖走不了的地方仍然出得去。 + nb = {l: [(di, dj, c * (1.0 if _along(l, di, dj) else CROSS_COST)) + for (di, dj, c) in _NB8] for l in LAY} + seen = set() + while open_: + _f, cur = heapq.heappop(open_) + if cur in seen: + continue + seen.add(cur) + if cur in goalset: + path = [cur] + while path[-1] in came: + path.append(came[path[-1]]) + return path[::-1] + l, i, j = cur + base = gsc[cur] + for di, dj, c in nb[l]: + n = (l, i + di, j + dj) + if n in seen or not g.free(l, i + di, j + dj, net): + continue + ng = base + c + g.cost(l, i + di, j + dj) + if ng < gsc.get(n, 1e18): + gsc[n] = ng + came[n] = cur + heapq.heappush(open_, (ng + h(n), n)) + other = LAY[1] if l == LAY[0] else LAY[0] + n = (other, i, j) + if n not in seen and g.free(other, i, j, net) and g.free_via(i, j, net): + ng = base + VIA_COST + if ng < gsc.get(n, 1e18): + gsc[n] = ng + came[n] = cur + heapq.heappush(open_, (ng + h(n), n)) + return None + + +def to_segments(path): + u"""路径 -> [(layer, x0,y0, x1,y1)] + 过孔 [(x,y)]，合并共线段。""" + segs, vias = [], [] + run_start = path[0] + prev = path[0] + for cur in path[1:]: + if cur[0] != prev[0]: # 换层 + if run_start != prev: + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + vias.append((wx(prev[1]), wy(prev[2]))) + run_start = cur + prev = cur + continue + d1 = (prev[1] - run_start[1], prev[2] - run_start[2]) + d2 = (cur[1] - prev[1], cur[2] - prev[2]) + if run_start != prev and (d1[0] * d2[1] - d1[1] * d2[0] != 0 or + (d1[0] * d2[0] + d1[1] * d2[1]) <= 0): + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + run_start = prev + prev = cur + if run_start != prev: + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + return segs, vias + + +# ── 焊盘引出脚 ──────────────────────────────────────────────────────── +def pad_rect(p, inf=0.0): + return (p[2] - p[4] / 2 - inf, p[3] - p[5] / 2 - inf, + p[2] + p[4] / 2 + inf, p[3] + p[5] / 2 + inf) + + +def seg_hits_rect(x0, y0, x1, y1, r): + u"""线段是否与矩形相交（粗判：采样）。""" + n = max(2, int(math.hypot(x1 - x0, y1 - y0) / 0.05)) + for k in range(n + 1): + t = k / float(n) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + if r[0] <= x <= r[2] and r[1] <= y <= r[3]: + return True + return False + + +def pad_nodes(g, p, halfw, others, stub_half=None, gt=None): + # ⚠ `others` 必须按 **CLR + 引出脚半宽** 膨胀过再传进来。第一版按 0.05 膨胀， + # 于是引出脚可以贴着隔壁焊盘 0.05 mm 走过去 —— DRC「贴片焊盘到导线」一次报 158 条。 + u"""这个焊盘可以起步的格点，按「离盘心近 + 引出脚不蹭别的盘」排序。""" + lay, net = p[6], p[7] + # ⛔ `others` 传进来的是**未膨胀**的焊盘框，在这里按**引出脚**的口径膨胀。 + # 用干线口径（1.5 mm 线 → 0.93）膨胀的话，隔壁焊盘的膨胀区会把 + # 0.5 mm 间距 QFN 的所有出口堵死 —— 报「出不来」，看着像拥塞， + # 其实是拿干线的宽度去量那一小段缩窄的引出脚。 + if stub_half is None: + stub_half = W_DEFAULT / 2.0 + # ⚠ 引出脚用**规则净距 0.15**，不用干线那个留了余量的 CLR=0.18。 + # 那 0.03 的余量是给 A* 干线的；最后 0.5 mm 缩窄段上再留， + # 0.35 mm 间距的连接器就一个出口都没有了。router_check 判的也是 0.15。 + inf = STUB_CLR + stub_half + # ⛔ **自身焊盘按「同一个矩形」排除，不能按「谁包住我的盘心」排除。** + # 膨胀之后，0.35 mm 间距的 `J4` 隔壁脚的框正好把本脚盘心吞进去 + # （50.01 那只脚膨胀后是 49.64~50.38，本脚盘心 49.66 在里面）， + # 于是**隔壁脚被当成自己跳过**，引出脚就贴着它走了 —— 净距 0.047， + # 而 pad_nodes 全程不报错。这一条 2026-09-08 实测踩到两次（USB_THERM / CC1）。 + own = pad_rect(p) + others = [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) for r in others + if max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + for ring in range(0, 5): # 一圈找不到就往外扩，最多 4 圈（1 mm） + out = _pad_nodes_ring(g, p, halfw + ring * G, others, lay, net, gt, stub_half) + if out: + return out + return [] + + +def _oth_inflated(p, others, stub_half): + u"""把同层焊盘框按**引出脚口径**膨胀，并剔掉本盘自己那一个（按矩形本身，不是按包住盘心）。""" + inf = STUB_CLR + stub_half + own = pad_rect(p) + return [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) for r in others + if max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + + +def _axis_exit(p, stub_half): + u"""沿焊盘**长轴**向外的两个出口点（本盘自己的「车道」，两侧没有邻盘）。""" + d = STUB_CLR + stub_half + if p[5] >= p[4]: + r = p[5] / 2.0 + d + return [(p[2], p[3] + r), (p[2], p[3] - r)] + r = p[4] / 2.0 + d + return [(p[2] + r, p[3]), (p[2] - r, p[3])] + + +def stub_path(p, X, Y, oth, stub_half, g=None, net=None): + u"""盘心 → 落点的引出脚折线；走不通返回 None。 + + ⛔ **先直线，走不通再走 L 形**：`J4`（0.35 mm 间距、盘 0.18 宽）盘心到邻盘边 + 只有 0.26 mm，任何斜着出去的引出脚都会蹭上邻盘（实测 0.047 mm）， + 于是「一个出口都找不到」。但**沿着焊盘长轴直着出去**是安全的 —— + 那是本盘自己的车道，两侧的邻盘在左右不在前后。出了盘阵再拐就没事了。 + `U1`/`U2`/`U7` 那几只内侧脚同理。 + + ⛔ **候选还要过占用图那一关**（`g` / `net`，2026-09-09 M7 补）： + 这里原来只判「蹭没蹭到别的**焊盘**」，不判过孔和已布的铜 —— + 于是 L 形的拐点可以正好贴在别人的过孔边上：实测 `U2.15`($1N147) 的引出脚 + 离 `EFUSE_EN` 的孔净距 **−0.204**、`U2.2`(EFUSE_PG) 离 `$1N164` 的孔同样， + DRC 报「导线到过孔 0 mil」四条，而 A*、线与线、引出脚自己那三关全过。 + """ + def ok(pts, strict): + for a, b in zip(pts, pts[1:]): + if any(seg_hits_rect(a[0], a[1], b[0], b[1], r) for r in oth): + return False + if strict and g is not None and not _stub_clear( + g, p[6], a[0], a[1], b[0], b[1], + net if net is not None else p[7], pad_rect(p)): + return False + return True + + cand = [[(p[2], p[3]), (X, Y)]] + for (ex, ey) in _axis_exit(p, stub_half): + cand.append([(p[2], p[3]), (ex, ey), (X, Y)]) + # ⛔ 占用图那一关只用来**排序**，不用来否决：拿它当硬条件的话， + # 「落点挑得出来（`pad_nodes` 也用 `gt`）、引出脚却发不出来」， + # 实测多报 3~4 个脚「一根铜都没有」——**丢一只脚比蹭 0.05 mm 严重得多**。 + # ⇒ 先要「既不蹭盘也不蹭孔」的；没有的话退回老判据（只不蹭盘）。 + for strict in (True, False): + for pts in cand: + if ok(pts, strict): + return pts + return None + + +def stub_emit(p, X, Y, others, stub_half, w, net, g=None): + u"""发引出脚的线段（1 段或 L 形 2 段）。判据和 `stub_path` 是同一个，不许各写一份。 + + ⚠ 宽度不能低于**规则下限**：引出脚缩窄是为了从细间距里挤出来，但 DRC 不认这个理由 + （`SWNODE` 下限 0.3，而 `U1` 的 SW 脚只有 0.279，按脚缩就报「物理错误」）。 + 比焊盘宽一点点只是稍微出头，间距还够。 + + ⚠ `g` 传进来就顺带过一遍占用图（避过孔 / 已布的铜），不传就退回「只避焊盘」。 + **真正落到板上的那一次调用一定要传**，见 `plan_all` 里的注释。 + """ + w = max(w, rule_min(net, AUTO_CACHE)) + pts = stub_path(p, X, Y, _oth_inflated(p, others, stub_half), stub_half, g, net) + if pts is None: + pts = [(p[2], p[3]), (X, Y)] + out = [] + for a, b in zip(pts, pts[1:]): + if math.hypot(b[0] - a[0], b[1] - a[1]) > 1e-6: + out.append((p[6], a[0], a[1], b[0], b[1], w, net)) + return out + + +def _stub_clear(g, lay, px, py, qx, qy, net, own=None): + u"""引出脚沿途的格点必须对本网可进。 + + ⛔ `own` = 本焊盘自己的框：**落在自己盘里的采样点要跳过**。 + 引出脚从盘心出发，而盘心那一格常常被隔壁那根线的避让区盖住 + （`U1.13` 旁边 0.5 mm 就是 2 mm 宽的 SW 直连段）—— 于是**第一个采样点** + 就判死，报「出不来」，而它左边明明整片是空的。 + 焊盘里本来就有铜，这一段不该参与净距判断。 + """ + n = max(2, int(math.hypot(qx - px, qy - py) / (G / 2.0))) + for k in range(n + 1): + t = k / float(n) + x, y = px + (qx - px) * t, py + (qy - py) * t + if own is not None and own[0] <= x <= own[2] and own[1] <= y <= own[3]: + continue + if not g.free(lay, gx(x), gy(y), net): + return False + return True + + +def _pad_nodes_ring(g, p, halfw, others, lay, net, gt=None, stub_half=0.1): + x0, y0, x1, y1 = pad_rect(p, halfw) + out = [] + for j in range(max(0, gy(y0)), min(NY - 1, gy(y1)) + 1): + for i in range(max(0, gx(x0)), min(NX - 1, gx(x1)) + 1): + if not g.free(lay, i, j, net): + continue + X, Y = wx(i), wy(j) + # ⚠ 自己的焊盘框已经在 pad_nodes 里**按矩形本身**剔掉了。 + # 直线走不通还要试 L 形（见 stub_path），否则细间距的脚全报「出不来」。 + if stub_path(p, X, Y, others, stub_half) is None: + continue + # ⛔ 引出脚还要躲**已经布好的铜**。只查焊盘的话，引出脚会从先布的 + # 导线/过孔身上压过去（自算净距报 `USB_DP` 的指脚 vs `VBUS` −0.097）。 + # ⚠ 只拿**已布的铜**那张图查，不能拿主占用图查： + # 细间距器件上相邻焊盘的膨胀区互相重叠，格点会变成 + # 255（多网占用），连自己的引出脚都进不去，整网报「出不来」。 + # 焊盘那一层已经由上面的 `others` 按引出脚口径管过了。 + if gt is not None and not _stub_clear(gt, lay, p[2], p[3], X, Y, net, + pad_rect(p)): + continue + out.append((math.hypot(X - p[2], Y - p[3]), (lay, i, j))) + out.sort() + return [n for _d, n in out] + + +def stub_w(p, width): + u"""引出脚宽度按焊盘尺寸封顶。 + + ⛔ 不封顶的话，`SWNODE` 2.0 mm 的线要接进 `U1`（0.5 mm 间距 QFN）和 `C5`（0402）， + 引出脚直接盖住隔壁两个脚 —— 自算净距 −0.73，DRC 报「贴片焊盘到导线」。 + 干线仍然是全宽（A* 的路径离别人的焊盘有 halfw 的余量），**只有最后接进焊盘 + 那一小段缩窄**，这也是手工布板的做法。 + + ⚠ 下限 **0.15，不是 0.2**：`J4`（BM24-50DS）下排 0.35 mm 间距、焊盘 0.18 宽， + 盘心到隔壁盘边只有 0.26 mm。要 0.15 的净距，引出脚半宽就得 ≤ 0.11 —— + 0.2 宽的脚（半宽 0.1 + 规则 0.15 = 0.25）**只剩 0.01 余量**， + grid 一吸附就蹭上（实测 USB_THERM 对 J4.16 只有 0.047）。 + 0.15 宽 ⇒ 0.15 + 0.075 = 0.225，余 0.035。嘉立创四层线宽下限 0.09，做得出来。 + """ + return round(max(0.15, min(width, p[4], p[5])), 3) + + +# 「已经被铜连在一起」的虚拟落点：位号是这些的，`route_net` 把它们**全部当种子** +# （多源 Prim），彼此之间不布线。目前只有底板的 `+3V3` 槽墙（方案 R2 §30）。 +PRE_WIRED = ('WALL',) + + +def _is_launch(p): + u"""扇出/金手指扇出留下的**虚拟焊盘**（落点）。""" + return str(p[1]).startswith('fan:') or p[1] in ('launch', 'wall') + + +def route_net(g, net, pads_of_net, halfw, width, others_by_layer, log, gt=None, mutate=True): + u"""对一个网络做 Prim：逐个把还没连上的焊盘接进来。 + + ⚠ **落点（虚拟焊盘）不做「引出脚别蹭邻盘」那道检查**：落点就在焊盘阵的边上， + 邻盘膨胀后的框必然把它包住，于是每个候选格点都被判死 —— 报「出不来」， + 而它明明已经是扇出阶段验证过的合法落点了。 + """ + + def _oth(p): + return [] if _is_launch(p) else others_by_layer.get(p[6], []) + segs, vias, stubs = [], [], [] + if len(pads_of_net) < 2: + return segs, vias, stubs + todo = list(pads_of_net) + # 种子挑**出口最多**的那个焊盘（最自由），不是第一个碰到的 + cand = [] + for k, p in enumerate(todo): + ns = pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt) + if ns: + cand.append((len(ns), k, ns)) + if not cand: + log.append(u'%s: 一个焊盘都出不来' % net) + return segs, vias, stubs + cand.sort(reverse=True) + _n, seed, starts = cand[0] + seedpad = todo.pop(seed) + # ⛔ **种子的引出脚必须画到 A* 真正起步的那个出口上**，不能画到 `starts[0]`。 + # 下面 `src` 放的是种子的**全部**出口（那是对的，只放一个会自锁）； + # 可引出脚只画一条 —— A* 从别的出口起步时，铜就和焊盘**断开**了， + # 而布线器只看「路找到没有」，**一个字都不会报**。 + # `KPAD_PWR` 就是这么断的：K1 的引出脚停在 (7.75,34.25)， + # 干线却从 (8.75,33.25) 起步，中间 1.4 mm 是空的。 + # ⇒ 改成**惰性**：谁真被用上了，就给谁补一条引出脚。 + seed_nodes = set(starts) + stubbed = set() + + def note_seed(node): + if node not in seed_nodes or node in stubbed: + return + stubbed.add(node) + stubs.append((seedpad, node, stub_w(seedpad, width))) + if mutate: + for (_l, ax, ay, bx, by, sw, _n) in stub_emit( + seedpad, wx(node[1]), wy(node[2]), _oth(seedpad), + stub_w(seedpad, width) / 2.0, stub_w(seedpad, width), net): + block_track(g, seedpad[6], ax, ay, bx, by, halfw + sw / 2.0, net) + # ⛔ 种子集合要放**全部出口**，不能只放第一个。 + # 只放一个的话，后面每个焊盘都得 A* 到那一个格点；它一旦被先布的线围住， + # 整个网就全线报「没布通」（`+3V3` 14 个脚里 11 个失败就是这么来的）， + # 而看上去像是板子太挤。 + src = set(starts) + # ⛔ **多源种子**：`PRE_WIRED` 的落点落在**同一块已经存在的铜**上（3V3 槽墙那种）， + # 它们彼此之间不需要一根线。全部一次性进 `src` 并从 `todo` 里摘掉。 + # 不这么做的话，Prim 会把「落点」当普通节点，逼 A* 在铜上再布一条线把它们串起来 + # —— 实测 `+3V3` 因此从最北那个落点一路蜿蜒到板子最南（100 mm，横穿五条走廊， + # 正好压在 I²C 的出脚道上），而**布线器只报「布通了」**。 + # ⇒ 一只脚就近接到墙上，这才是「铜墙」的本意。 + for p in list(todo): + if p[0] in PRE_WIRED: + for n in pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt): + src.add(n) + todo.remove(p) + todo.sort(key=lambda q: math.hypot(q[2] - seedpad[2], q[3] - seedpad[3])) + done, fail = set(), {} + # 走两遍：第二遍时 src 已经长大，第一遍够不着的往往就通了 + for p in todo + [q for q in todo]: + if id(p) in done: + continue + goals = pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt) + if not goals: + fail[id(p)] = u'%s: %s.%s 出不来' % (net, p[0], p[1]) + continue + path = astar(g, list(src), goals[:24], net, halfw) + if not path: + fail[id(p)] = u'%s: %s.%s 没布通' % (net, p[0], p[1]) + continue + s, v = to_segments(path) + note_seed(path[0]) # 这条路真正用的是哪个种子出口 + segs += [(l, a, b, c, d, width, net) for (l, a, b, c, d) in s] + vias += [(x, y, net) for (x, y) in v] + stubs.append((p, path[-1], stub_w(p, width))) + # ⚠ 回填占用图要按 **halfw + 本线半宽**，不能只按 halfw： + # halfw 已经含了「后来那根线的半宽 + 净距」，但**这根线自己也有宽度**。 + # 只按 halfw 填的话，同一档宽度里两根 1.5 mm 的线会被排到中心距 1.5， + # 实际净距 0 —— DRC 一口气报出 598 条，全是宽线互相压。 + keep = halfw + width / 2.0 + done.add(id(p)) + for n in path: + src.add(n) + if mutate: + g.block_rect(n[0], wx(n[1]) - keep, wy(n[2]) - keep, + wx(n[1]) + keep, wy(n[2]) + keep, net=net) + for (l, a, b, c, d) in s: + if mutate: + block_track(g, l, a, b, c, d, keep, net, + extra=max(0.0, VIA_D / 2.0 + CLR - keep)) + if gt is not None: + block_track(gt, l, a, b, c, d, CLR + W_DEFAULT / 2.0 + width / 2.0, net) + for (vx, vy) in v: # 自己刚打的过孔 + # ⛔ 净距那一项不能漏：`VIA_D/2 + halfw` 只保证「铜刚好挨上」， + # 后布的线就能贴到过孔边（DRC：导线到过孔 0 mil，实测 12 条）。 + r = VIA_D / 2.0 + CLR + halfw + if mutate: + for l2 in LAY: + g.block_both(l2, vx - r, vy - r, vx + r, vy + r, + max(0.0, VIA_D / 2.0 + CLR - halfw), net=net) + # ⛔ **刚打的过孔也要进 `gt`（引出脚校验图）**。`gt` 是每一轮开头建一次的， + # 只含开轮时已有的过孔 —— 同一轮里先布的网打的孔，对后布的网的引出脚 + # 就是隐形的。实测两处：`U2.15`($1N147) 的引出脚贴到 `EFUSE_EN` 的孔上 + # （净距 −0.204），`U2.2`(EFUSE_PG) 贴到 `$1N164` 的孔上。 + # 线与线、A* 那几关全过，只有 DRC 的「导线到过孔」报得出来。 + if gt is not None: + rt = VIA_D / 2.0 + CLR + W_DEFAULT / 2.0 + for l2 in LAY: + gt.block_rect(l2, vx - rt, vy - rt, vx + rt, vy + rt, net=net) + # 引出脚（盘心 -> 第一个格点，可能是 L 形）也要占位， + # 否则后面的线会从它身上压过去 + if mutate: + for (_l, ax, ay, bx, by, sw, _n) in stub_emit( + p, wx(path[-1][1]), wy(path[-1][2]), _oth(p), + stub_w(p, width) / 2.0, stub_w(p, width), net, g): + block_track(g, p[6], ax, ay, bx, by, halfw + sw / 2.0, net) + # ⛔ **失败必须往外报**。这个 `fail` 字典以前收完就扔了 —— 于是 + # 「某个脚没布通」全程静默：网上只剩一小段引出脚（`BUCK_PG` 0.02 mm）， + # 脚本打印「0 条没搞定」，`getNetLength()` 也非 0（有那一小段）， + # 只有 EasyEDA 的连接性 DRC 会报，而那一支平时被当成「还没布线」忽略掉。 + # 2026-09-08 就是这么漏掉 20 多个连接的。 + for p in todo: + if id(p) in done: + continue + log.append(fail.get(id(p), u'%s: %s.%s 没接上' % (net, p[0], p[1]))) + return segs, vias, stubs + + +# ── J1 金手指扇出（不走 A*，几何是确定的）─────────────────────────────── +BUS_Y = {1: 7.0, 2: 8.2} # 顶层地母线 / 底层地母线（错开，过孔互不挡） +LAUNCH_Y = 11.75 # 信号指爬到这一行，交给 A*（要落在 0.25 网格上） +STUB_Y0 = 4.0 # 引出脚从指的中段起（压在焊盘上） +BUS_W, STUB_W = 0.4, 0.2 +FINGER_W = {'+12V': 0.35, '+5V': 0.3} + + +def finger_geom(): + u"""返回 (pin -> (x, layer, net))。x 直接用封装的事实来源。""" + out = {} + # ⚠ 针位表在 `b4_edge.PIN_NET`（原理图那一份），几何在 `fp_edge`（封装那一份）。 + # 两份各是各的事实来源，**不许在这里抄第三份**。 + for pin, net in b4_edge.PIN_NET.items(): + row = pin[0] + out[pin] = (round(B.J1_X + fp_edge.PIN_X[pin], 4), fp_edge.LAYER[row], net) + return out + + +def gnd_runs(fg): + u"""每一排里连续的地指分段。""" + runs = {} + for row, lay in (('A', 2), ('B', 1)): + cur = [] + for n in range(1, 33): + pin = '%s%d' % (row, n) + if fg[pin][2] == 'GND': + cur.append(pin) + else: + if cur: + runs.setdefault(lay, []).append(cur) + cur = [] + if cur: + runs.setdefault(lay, []).append(cur) + return runs + + +def finger_escape(): + u"""地指走母线 + 过孔；信号指直上到 LAUNCH_Y。 + + ⚠ **过孔只能打在「另一排同 x 是地或悬空」的位置**：过孔是通孔， + 打在信号指正上方会把另一层那根信号的引出脚堵死。 + 这一条不写进代码的话，`B14/B15`（USB D±）和 `A16`（VDAC）会被地过孔挡住， + 而 DRC 只会报「这根线没布通」，指不到根因。 + """ + fg = finger_geom() + other = {} + for n in range(1, 33): + other['A%d' % n] = fg['B%d' % n][2] + other['B%d' % n] = fg['A%d' % n][2] + segs, vias, launch = [], [], {} + # 地指 + for lay, runs in sorted(gnd_runs(fg).items()): + y = BUS_Y[lay] + for run in runs: + xs = [fg[p][0] for p in run] + x0, x1 = min(xs), max(xs) + ok = [fg[p][0] for p in run if other[p] in ('GND', 'NC')] + if not ok: # 整段都被对排的信号占着 -> 母线往外伸 1 mm + x1 = x1 + 1.0 + ok = [x1] + segs.append((lay, x0, y, x1, y, BUS_W, 'GND')) + for p in run: + segs.append((lay, fg[p][0], STUB_Y0, fg[p][0], y, STUB_W, 'GND')) + for k, vx in enumerate(ok): + if k % 2 == 0 or len(ok) <= 2: # 每隔一根打一个，够用 + vias.append((vx, y, 'GND')) + # 信号指：爬到 LAUNCH_Y 之后**立刻换到空的那一面**。 + # ⛔ M5 时代这句是「换到**底层**」，理由是「83 件全在 A 面，底层是空的」—— + # **M6 把 83 件全翻到了 B 面（底层）之后这句就反了**，而注释没跟着改： + # 于是 19 根金手指信号全被灌进器件面，跟 78 个件的焊盘抢那几条通道， + # A* 布不出来就退化成「直连段」——直接一条铜横穿金手指区， + # 压在 16 根地指的引出脚上（DRC：`PRSNT#` 到 `GND` 净距 0，16 条）。 + # ⚠ **试过反过来（换到顶层）：更差**，20 条没搞定（原来 6 条）—— + # 78 个件的焊盘全在底层，信号换到顶层之后每根线都要再换回来， + # 每根多两个过孔，扇出区先堵死。⇒ 仍然换到底层， + # `PRSNT#` 那条横穿金手指区的铜另找原因（它是 A* 失败后的退化直连）。 + # ⚠ 例外：同一个 x 上 A/B 两排都是**不同网的信号**时不能换 —— + # 通孔会把另一排那根线在底层的去路堵死。这样的位置只有两个 + # （1 号针 A1=PRSNT# / B1=+12V，11 号针 A11=EFUSE_EN / B11=INT#）， + # 让 B 排那根留在顶层，交给 A* 自己想办法。 + sig = lambda n: n not in ('GND', 'NC') + for pin, (x, lay, net) in sorted(fg.items()): + if not sig(net): + continue + w = FINGER_W.get(net, STUB_W) + segs.append((lay, x, STUB_Y0, x, LAUNCH_Y, w, net)) + onet = other[pin] + clash = sig(onet) and onet != net + if lay == 1 and not clash: + vias.append((x, LAUNCH_Y, net)) + launch.setdefault(net, []).append((2, x, LAUNCH_Y)) + else: + launch.setdefault(net, []).append((lay, x, LAUNCH_Y)) + return segs, vias, launch + + +# ── 主流程 ──────────────────────────────────────────────────────────── +def rule_width(net, auto): + if net in WIDTH: + return WIDTH[net] + for k, n in auto.items(): + if n == net: + return WIDTH_AUTO.get(k, W_DEFAULT) + return W_DEFAULT + + +# 各线宽规则的**下限**（和 pcb_rules.TRACK_RULES 的 strokeWidthMin 对齐）。 +# ⛔ 低于下限 DRC 报「物理错误：线宽 x mil，应该在 y ~ z」—— 直连段按焊盘取宽 +# （`U1` 的 SW 脚只有 0.279）和过孔合并的连接段（固定 0.2）都会踩到。 +RULE_MIN = {'PWR12V': 0.25, 'SWNODE': 0.30, 'PWR4A': 0.30, + 'PWR5V': 0.20, 'PWR1A': 0.15} + + +def rule_min(net, auto): + u"""这个网的线宽下限。查不到就按默认 0.15。""" + import pcb_rules as R + cls = R.NET_TRACK.get(net) + if cls is None: + for name, (c, probe, chk) in R.AUTO_TRACK.items(): + if auto.get(name) == net: + cls = c + break + return RULE_MIN.get(cls, 0.15) + + +def width_of(net, auto, pads_of_net=()): + u"""线宽 = 规则宽度，但**被这个网最小的焊盘封顶**。 + + ⛔ 不封顶的后果不是「线太粗」，是**根本出不来**：找出口那张占用图是按干线宽度 + 建的，1.5 mm 的网去接 `U2`（0.5 mm 间距 WQFN，焊盘 0.3×0.9）时， + 隔壁焊盘按 0.93 mm 膨胀，把所有出口全堵死 —— 报的是「出不来」不是「没布通」， + 一眼看上去像拥塞，其实是自己把自己关在焊盘里了。 + + 这块板上这么封顶不损失载流：几个宽网要么本身就是**多脚并联的短连接** + （`$1N165` 是 eFuse 五个 OUT 脚 → `Rs1`，每脚 0.8 A，跨度 4 mm）， + 要么走的是 L3 的铜面（`VO_P` / `+12V`）。 + """ + # ⚠ 2026-09-08：**撤掉了按焊盘封顶**。那是绕开「出不来」的权宜之计， + # 代价是把 4 A 的 `SWNODE`/`PWR4A` 干路压到 0.48 mm（外层 1 oz 只带 ~2.2 A）， + # 拿载流换布通率，不能这么换。真正的根因在 `pad_nodes` 的 `others` 膨胀口径， + # 已经修好；干线保持规则宽度，只有**引出脚**按焊盘缩窄（`stub_w`）。 + return rule_width(net, auto) + + +def route_groups(bypad, pads, segs, vias, board_vias, auto, priority=(), only=None): + u"""按线宽分档把 `bypad` 里的网布完；`only` 给拆线重布用（只重布这几个网）。 + + 直接**原地**往 `segs` / `vias` 里追加，返回没搞定的日志。 + """ + logs = [] + # 其余按线宽分档，宽的先布 + groups = {} + capped = [] + for net, ps in bypad.items(): + if only is not None and net not in only: + continue + w = width_of(net, auto, ps) + # ⚠ 直连之后**才**按焊盘封顶：4 A 的干线已经由直连段承担（宽度=焊盘本身， + # IC 的脚有多宽就有多宽，再宽也没意义），剩下要 A* 的都是小脚上的支路 + # （BOOT 电容、FB 抽头）。不封顶的话，2 mm 的口径在 0.5 mm 间距的 + # QFN 上一个出口都找不到 —— 报「出不来」，看着像拥塞。 + small = w if net in NO_CAP else min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [w]) + # ⚠ 封顶不能低于**规则下限**，否则 DRC 报「物理错误：线宽不足」。 + # `SWNODE` 下限 0.3，而 `U1` 的 SW 脚只有 0.279 —— 按脚封顶就踩线了。 + w = max(W_DEFAULT, rule_min(net, auto), min(w, small)) + if w < rule_width(net, auto) - 1e-9: + capped.append(u'%s %.2f→%.2f' % (net, rule_width(net, auto), w)) + groups.setdefault(w, []).append(net) + if capped: + print(u'线宽被焊盘封顶: ' + ' '.join(capped)) + for w in sorted(groups, reverse=True): + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + # ⚠ 已布的铜要**按它自己的网名**打进占用图，不能统一记成 '#done'： + # 记成 '#done' 的话，一个网自己的金手指引出脚会把自己的落脚点堵死， + # 现象是「J1.launch 出不来」——，而且看上去像是拥塞，其实是自锁。 + for (l, a, b, c, d, ww, nn) in segs: # 已布的铜 + # ⛔ `extra` 不能用默认的 0：`block_both` 的第二张图（`ownv`）是**换层判据**， + # 不给额外膨胀的话，别人的过孔可以直接落在这根线上 —— + # DRC 报「导线到过孔 0 mil」，实测两处（`EFUSE_EN` 的孔压 `$1N147`、 + # `$1N164` 的孔压 `EFUSE_PG`），而线与线那一支干干净净，很难看出来是谁的错。 + block_track(g, l, a, b, c, d, halfw + ww / 2.0, nn, + extra=max(0.0, VIA_D / 2.0 + CLR - (halfw + ww / 2.0))) + for (vx, vy, nn) in vias: + # ⛔ 同上：少了 `CLR` 的话，后布的线会贴着别人的过孔走。 + rv = VIA_D / 2.0 + CLR + halfw + for l in LAY: + g.block_rect(l, vx - rv, vy - rv, vx + rv, vy + rv, net=nn) + # 只装已布铜的占用图，供引出脚校验用（按引出脚口径 + 那根线自己的半宽膨胀） + gt = Grid() + stub_half = W_DEFAULT / 2.0 + for (l, a, b, c, d, ww, nn) in segs: + block_track(gt, l, a, b, c, d, CLR + stub_half + ww / 2.0, nn) + for (vx, vy, nn) in vias: + r = VIA_D / 2.0 + CLR + stub_half + for l in LAY: + gt.block_rect(l, vx - r, vy - r, vx + r, vy + r, net=nn) + others = {1: [], 2: []} + for p in pads: + if p[6] in others: + others[p[6]].append(pad_rect(p)) + # 跨度大的先布：短线随便绕，长线一旦被占住走廊就真的没路了 + def span(n): + ps = bypad[n] + return -(max(q[2] for q in ps) - min(q[2] for q in ps) + + max(q[3] for q in ps) - min(q[3] for q in ps)) + + # ⛔ 但**排在跨度前面的是「引出脚有多少条路」**。 + # 只按跨度排，细间距 IC 的**内侧引脚**必然吃亏：邻脚是长线、先布， + # 两边一占，内侧那只脚就再也出不来了。实测现象是 + # 「INA_ALERT: 一个焊盘都出不来」（U4 TSSOP-24 底排第 15 脚 + U3 MSOP-10 第 3 脚）， + # 看着像拥塞，其实是**顺序**问题 —— 同样的摆位，先布它就通。 + # 判据用「在这一档刚建好的占用图上，这个网最紧的那只脚有几个可起步格点」， + # 少的先布。空 = 0，直接排最前面。 + def escapes(n): + m = 99 + for q in bypad[n]: + if q[0] == 'J1': + continue + m = min(m, len(pad_nodes(g, q, halfw, others.get(q[6], []), + w / 2.0, gt))) + return m + seq = sorted(groups[w], + key=lambda n: (0 if n in priority else 1, + escapes(n), span(n), n)) + # ⛔ **过路费只对「还没布的脚」收**。静态收费（所有焊盘一视同仁）已经把 + # 28 条降到 16 条；但布完的网还继续收费，等于白白把已经用不着的出口 + # 也围起来，后面的线被迫绕远、反而去挤别人的出口。 + # 改成每布一个网之前重算一次：**只围还没轮到的那些脚**。 + todo_nets = list(seq) + [n for ww2 in groups if ww2 != w for n in groups[ww2]] + for k, net in enumerate(seq): + left = set(todo_nets[k:]) + pen_pads(g, [q for nn in left for q in bypad.get(nn, []) + if q[0] != 'J1'], halfw) + s, v, st = route_net(g, net, bypad[net], halfw, w, others, logs, gt) + segs += s + vias += v + for (q, node, ww) in st: + # ⚠ 这里发的才是**真正落到板上的**引出脚（上面那两处只是往占用图里占位）。 + # `g` 一定要传：不传就退回「只避焊盘」的老判据， + # L 形拐点会贴到别人的过孔上（见 stub_path 的说明）。 + # ⚠ 传的是 `gt`（引出脚口径的占用图）不是 `g`（干线口径）： + # `pad_nodes` 挑落点时用的就是 `gt`，两边判据必须**同一张图** —— + # 用 `g` 更严，会出现「落点挑得出来、引出脚发不出来」， + # 实测多报 4 个脚「一根铜都没有」（U2.2 / U2.15 / U2.20 / C9.1）。 + segs += stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net, gt) + return logs + + +# 拆线半径（mm）。⚠ 2.5 太小：实测挡住失败焊盘的网**不都在它旁边** —— +# 空占用图上这些脚全都出得来，一旦别的网从三五毫米外压过来就出不来了。 +RIP_R = 6.0 +RIP_MAX = 15 # 一次最多拆几个网 +RIP_ROUNDS = 4 + + +def _seg_pt_dist(sg, x, y): + return _pt_seg(x, y, sg[1], sg[2], sg[3], sg[4]) + + +def _pt_seg(px, py, ax, ay, bx, by): + dx, dy = bx - ax, by - ay + L = dx * dx + dy * dy + t = 0.0 if L == 0 else max(0.0, min(1.0, ((px - ax) * dx + (py - ay) * dy) / L)) + return math.hypot(px - (ax + t * dx), py - (ay + t * dy)) + + +def _msg_net(m): + u"""从日志里取网名。⚠ 连通性那几条带 `[连通性] ` 前缀，不剥掉的话 + 优先队列里塞的是「[连通性] +12V_F」这种鬼名字，等于**这些网从来没被重试过**。""" + if m.startswith(u'[连通性] '): + m = m[len(u'[连通性] '):] + return m.split(':', 1)[0].strip() + + +def repair(bypad, pads, segs, vias, logs, board_vias, auto, fixed_s=0, fixed_v=0): + u"""**拆线重布**：把挡在失败焊盘出口附近的几个网拆掉，先布失败的那个，再把拆掉的补回去。 + + ⛔ 到这一步为止试过的所有招（顺序、扇出、过路费、L 形引出脚、正交方向）都 + 只能把失败数从 42 压到 13 —— 因为**剩下的全是「轮到它时出口已经被占了」**， + 而这个布线器没有回退。把占位的那几根拆掉重来，是唯一还剩的办法。 + + 判据是**总数变少才接受**：重布之后如果失败反而更多，整批回滚。 + """ + padmap = {} + for q in pads: + padmap[(q[0], str(q[1]))] = q + for rnd in range(RIP_ROUNDS): + if not logs: + break + before = len(logs) + for msg in list(logs): + if msg not in logs: + continue + net = _msg_net(msg) + if net not in bypad: + continue + q = None + try: + ref_pin = msg.split(':', 1)[1].strip().split()[0] + q = padmap.get(tuple(ref_pin.split('.'))) + except Exception: + q = None + if q is None: + # 「铜分成 N 块」这种没指名焊盘：拿这个网自己的焊盘当中心 + cand2 = [x for x in bypad[net] if x[0] != 'J1'] + if not cand2: + continue + q = cand2[0] + near = {} + for sg in segs: + if sg[6] == net or sg[6] in SKIP or sg[6] not in bypad: + continue + d = _seg_pt_dist(sg, q[2], q[3]) + if d < RIP_R: + near[sg[6]] = min(near.get(sg[6], 99), d) + victims = [n for _d, n in sorted((d, n) for n, d in near.items())][:RIP_MAX] + if not victims: + continue + redo = set(victims) | {net} + # ⛔ **前 fixed_s / fixed_v 条是前置阶段（Kelvin / VO_P 过孔 / 直连）的铜， + # 一根都不许拆** —— `route_groups` 只跑 A*，拆了它**重建不回来**， + # 而且拆掉的那些焊盘早已从 `bypad` 里摘掉了，于是**失败计数看不出来**： + # 板子断了，脚本还报「好了」。`$1N138` 只剩一段 0.06 mm 的残桩就是这么来的。 + keep_s = segs[:fixed_s] + [sg for sg in segs[fixed_s:] if sg[6] not in redo] + keep_v = vias[:fixed_v] + [v for v in vias[fixed_v:] if v[2] not in redo] + keep_logs = [m for m in logs if _msg_net(m) not in redo] + ns, nv = list(keep_s), list(keep_v) + new_logs = route_groups(bypad, pads, ns, nv, board_vias, auto, + priority=(net,), only=redo) + # ⚠ 重布完要**按几何**再查一遍：A* 说「布通了」不等于铜真的连上 + # （见 route_net 里种子引出脚那条注释）。 + for m2 in check_connected(pads, ns, nv): + if _msg_net(m2) in redo: + new_logs.append(u'[连通性] ' + m2) + # ⚠ **打平也接受**：不接受打平就会一直卡在同一个平台上 + # （12~16 来回跳）。换一组同样多的失败出来，下一轮就可能解开。 + if len(keep_logs) + len(new_logs) <= len(logs): + segs[:] = ns + vias[:] = nv + logs[:] = keep_logs + new_logs + print(u' 拆线重布第 %d 轮：%d -> %d' % (rnd + 1, before, len(logs))) + if len(logs) >= before: + break + return segs, vias, logs + + +def check_connected(pads, segs, vias): + u"""**真正的连通性判据**：按几何做并查集，看每个网的焊盘是不是真的连成一片。 + + ⛔ 为什么非要有：布线器报「0 条没搞定」只说明**它自己**觉得布完了。 + 拆线重布一旦把前置阶段的铜（直连 / Kelvin / VO_P 过孔）删掉， + 那些焊盘早就不在 `bypad` 里，于是**没人再检查它们** —— 板子断了、脚本报好。 + 这里不看布线器的账本，只看铜。 + """ + par = {} + + def find(a): + while par.get(a, a) != a: + par[a] = par.get(par[a], par[a]) + a = par[a] + return a + + def uni(a, b): + ra, rb = find(a), find(b) + if ra != rb: + par[ra] = rb + + def key(l, x, y): + return (l, round(x, 2), round(y, 2)) + + for sg in segs: + l, x0, y0, x1, y1 = sg[0], sg[1], sg[2], sg[3], sg[4] + par.setdefault(key(l, x0, y0), key(l, x0, y0)) + par.setdefault(key(l, x1, y1), key(l, x1, y1)) + uni(key(l, x0, y0), key(l, x1, y1)) + for (vx, vy, _n) in vias: + a1, b1 = key(LAY[0], vx, vy), key(LAY[1], vx, vy) + par.setdefault(a1, a1) + par.setdefault(b1, b1) + uni(a1, b1) + # 焊盘：盘框内的所有端点并到一起 + bad = [] + bynet = {} + for q in pads: + bynet.setdefault(q[7], []).append(q) + ends = {} + for k in list(par): + ends.setdefault(k[0], []).append(k) + for net, ps in bynet.items(): + if not net or net in SKIP: + continue + roots, naked = [], [] + for q in ps: + if q[0] == 'J1': # 金手指自己有扇出，另算 + continue + r = pad_rect(q, 0.05) + hit = [k for k in ends.get(q[6], []) + if r[0] <= k[1] <= r[2] and r[1] <= k[2] <= r[3]] + if not hit: + naked.append('%s.%s' % (q[0], q[1])) + continue + for h2 in hit[1:]: + uni(hit[0], h2) + roots.append(find(hit[0])) + if naked: + bad.append(u'%s: %s 一根铜都没有' % (net, ' '.join(naked[:4]))) + elif len(set(roots)) > 1 and net not in ISLAND_NETS: + # ⚠ `VO_P` / `+12V` 靠 L3 的整块铜岛成网（每个焊盘扎一个过孔进去）， + # 铜在几何上**本来就是分开的几块**，不是断线。 + bad.append(u'%s: 铜分成 %d 块' % (net, len(set(roots)))) + return bad + + +def plan_all(priority=()): + u"""`priority` 里的网络在同一档宽度里**排最前面** —— 给失败重试用。""" + import pcb_rules as R + auto = R.resolve_auto() + pads = load_pads() + board_vias = load_vias() + print(u'板上已有过孔 %d 个' % len(board_vias)) + fsegs, fvias, launch = finger_escape() + + segs = list(fsegs) + vias = list(fvias) + logs = [] + + # J1 的焊盘不再参与 A*（已经爬到 LAUNCH_Y），改成「虚拟焊盘」 + bypad = {} + for p in pads: + if p[0] == 'J1': + continue + if not p[7] or p[7] in SKIP: + continue + bypad.setdefault(p[7], []).append(p) + for net, pts in launch.items(): + for (lay, x, y) in pts: + bypad.setdefault(net, []).append(['J1', 'launch', x, y, 0.3, 0.3, lay, net, 'RECT']) + + # ── Kelvin 专线（必须在所有别的线之前）── + halfk = 0.3 / 2.0 + CLR + gk = build_grid(pads, halfk, board_vias) + for (l, a, b, c, d, ww, nn) in segs: + block_track(gk, l, a, b, c, d, halfk + ww / 2.0, nn) + padmap = {(q[0], q[1]): q for q in pads} + othersk = {1: [pad_rect(q) for q in pads if q[6] == 1], + 2: [pad_rect(q) for q in pads if q[6] == 2]} + for (aa, bb, w) in KELVIN: + pa, pb = padmap.get(aa), padmap.get(bb) + if not pa or not pb: + logs.append(u'Kelvin: 找不到 %s / %s' % (aa, bb)) + continue + na = pad_nodes(gk, pa, halfk, othersk.get(pa[6], []), w / 2.0) + nb = pad_nodes(gk, pb, halfk, othersk.get(pb[6], []), w / 2.0) + path = astar(gk, na[:12], nb[:12], pa[7], halfk) + if not path: + logs.append(u'Kelvin: %s.%s -> %s.%s 没布通' % (aa + bb)) + continue + sg, vv = to_segments(path) + segs += [(l, x0, y0, x1, y1, w, pa[7]) for (l, x0, y0, x1, y1) in sg] + vias += [(x, y, pa[7]) for (x, y) in vv] + segs += stub_emit(pa, wx(path[0][1]), wy(path[0][2]), + othersk.get(pa[6], []), w / 2.0, w, pa[7]) + segs += stub_emit(pb, wx(path[-1][1]), wy(path[-1][2]), + othersk.get(pb[6], []), w / 2.0, w, pb[7]) + + # ⚠ Kelvin 那两条已经把 `U3.9/10` 接到 `Rs1` 上了，**要把 U3 那两只脚从 + # bypad 里摘掉** —— 不摘的话 A* 会再去接一遍（`$1N165: U3.10 出不来`）， + # 而它本来就已经连上了。 + for (aa, _bb, _w) in KELVIN: + for net in list(bypad): + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) != aa] + + # VO_P：靠 L3 的岛，每个焊盘扎一个过孔就够（4 A 走平面，比走线好）。 + # ⚠ **过孔位置必须过占用图**：第一版是「往右 0.9 mm 找个点就打」， + # 于是 `U3.8`（0.5 mm 间距的 MSOP-10）的 1.5 mm 引出脚直接压住隔壁两个脚， + # DRC 一口气报 400 条「导线到导线 0 mil」。判据换成 pad_nodes + 岛的范围。 + halfv = VIA_D / 2.0 + CLR + gv = build_grid(pads, halfv, board_vias) + for (l, a, b, c, d, ww, nn) in segs: + block_track(gv, l, a, b, c, d, halfv + ww / 2.0, nn) + othersv = {1: [pad_rect(q) for q in pads if q[6] == 1], + 2: [pad_rect(q) for q in pads if q[6] == 2]} + isls = (P.VO_ISLAND, P.VO_LOBE) # M6：岛是 L 形，两块矩形任一块里都能落孔 + vo = [q for q in bypad.pop('VO_P', []) if (q[0], q[1]) not in KELVIN_PADS] + for p in vo: + if p[0] == 'J1': + continue + # ⚠ 下限是 **0.3 = PWR4A 规则的最小线宽**，不是 0.25。 + # `U3` 的 8/9 脚（VBUS 采样 / IN+）只有 0.28 宽，按焊盘缩到 0.28 就 + # 低于规则下限，DRC 报「物理错误：线宽 11mil，应该 >= 11.8mil」。 + # 0.3 的线接 0.28 的盘只是稍微出头，间距还剩 0.36-0.30=0.06，是够的。 + w = min(WIDTH['VO_P'], max(0.30, min(p[4], p[5]))) + # ⚠ 落的是**通孔**，两层都要让得开 —— 只查自己那一层的话会撞上另一面的焊盘 + # （实测 VO_P 的孔压在顶层 `C60` 的 GND 盘上，净距 0.125，DRC 报「焊盘到过孔」）。 + cand = [n for n in pad_nodes(gv, p, halfv, othersv.get(p[6], []), w / 2.0) + if any(isl[0] + 0.6 < wx(n[1]) < isl[2] - 0.6 + and isl[1] + 0.6 < wy(n[2]) < isl[3] - 0.6 for isl in isls) + and gv.free_via(n[1], n[2], 'VO_P')] + if not cand: + logs.append(u'VO_P: %s.%s 找不到落过孔的地方' % (p[0], p[1])) + continue + n = cand[0] + vx, vy = wx(n[1]), wy(n[2]) + segs += stub_emit(p, vx, vy, othersv.get(p[6], []), w / 2.0, w, 'VO_P') + vias.append((vx, vy, 'VO_P')) + keep = halfv + w / 2.0 + block_track(gv, p[6], p[2], p[3], vx, vy, keep, 'VO_P') + for l in LAY: + gv.block_rect(l, vx - keep, vy - keep, vx + keep, vy + keep, net='VO_P') + board_vias.append([vx, vy, 'VO_P', VIA_D]) + + # ── 直连：**焊盘对焊盘、中间没别人**的短连接，不走 A* ──────────────── + AUTO_CACHE.clear() + AUTO_CACHE.update(auto) + dsegs, merged = direct_links(pads, bypad, segs, vias) + segs += dsegs + if dsegs: + print(u'直连 %d 段（焊盘贴焊盘，A* 的干线口径进不去）' % len(dsegs)) + for net, groups in merged.items(): + drop = set() + for gset in groups: + drop |= set(list(gset)[1:]) # 每一簇只留一个代表 + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) not in drop] + + # ── 过孔扇出（M6，`--viafan`）：细间距 IC 每只信号脚先打一个过孔上顶层 ── + if '--viafan' in sys.argv: + fs, fv, fl = via_fanout(pads, bypad, segs, vias, auto) + segs += fs + vias += fv + n_fan = 0 + for net, items in fl.items(): + for (q, vx, vy) in items: + bypad[net] = [o for o in bypad[net] if o is not q] + bypad[net].append([q[0], 'fan:%s' % q[1], vx, vy, 0.3, 0.3, 1, net, 'RECT']) + n_fan += 1 + print(u'过孔扇出 %d 只脚（%s），落点全在顶层' % (n_fan, ' '.join(FANOUT_REFS))) + + # ── 关键网络优先：在**所有**别的网之前布 ──────────────────────────── + # ⛔ `$1N126`(FB) 和 `$1N138`(BOOT) 是 Buck 的命门：少了 BOOT 高侧管不开， + # 少了 FB 环路不闭合。它们都在 `U1` 最挤的那一圈上，按线宽分档的话排在 + # 最后一档、又被别的网占完出口 —— 所以给它们一条绝对优先的通道。 + for net in FIRST_NETS: + if net not in bypad or not bypad[net]: + continue + ps = bypad[net] + w = max(W_DEFAULT, rule_min(net, auto), + min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [W_DEFAULT])) + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a1, b1, c1, d1, ww, nn) in segs: + block_track(g, l, a1, b1, c1, d1, halfw + ww / 2.0, nn) + gt = Grid() + for (l, a1, b1, c1, d1, ww, nn) in segs: + block_track(gt, l, a1, b1, c1, d1, CLR + W_DEFAULT / 2.0 + ww / 2.0, nn) + others = {1: [], 2: []} + for q in pads: + if q[6] in others: + others[q[6]].append(pad_rect(q)) + s2, v2, st2 = route_net(g, net, ps, halfw, w, others, logs, gt) + segs += s2 + vias += v2 + for (q, node, ww) in st2: + segs += stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net, gt) + bypad.pop(net, None) + + # ⚠ **独立的扇出阶段试过，反而更差**（30 -> 40 条没接上），代码留在 `fanout()` + # 里备查，默认不跑。原因：提前把每只脚的引出脚铺成铜，等于在还不知道干线 + # 往哪走的时候先占地盘；更要命的是干线从此**只能从那一个落点起步**， + # 而原来 `pad_nodes` 能给 A* 24 个候选起点。少了这份自由度，得不偿失。 + + fixed_s, fixed_v = len(segs), len(vias) + if '--pf' in sys.argv: + # 协商式拥塞布线：所有干线交给它，不再走「一次布死」那条路 + logs += pf_solve(bypad, pads, segs, vias, board_vias, auto, fixed_s, fixed_v) + else: + logs += route_groups(bypad, pads, segs, vias, board_vias, auto, priority) + if logs: + segs, vias, logs = repair(bypad, pads, segs, vias, logs, board_vias, auto, + fixed_s, fixed_v) + segs, vias = dedupe_vias(segs, vias) + for m in check_connected(pads, segs, vias): + if m not in logs: + logs.append(u'[连通性] ' + m) + return segs, vias, logs + + +PUSH_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const MIL = %s, S = %s, V = %s, H = %s, D = %s; +let ls = 0, vs = 0; +for (const s of S) { + try { await eda.pcb_PrimitiveLine.create(s[6], s[0], s[1]*MIL, s[2]*MIL, + s[3]*MIL, s[4]*MIL, s[5]*MIL); ls++; } catch (e) {} +} +for (const v of V) { + try { await eda.pcb_PrimitiveVia.create(v[2], v[0]*MIL, v[1]*MIL, H*MIL, D*MIL); vs++; } catch (e) {} +} +return {ls, vs}; +""" + + +def push(segs, vias): + n = 0 + for k in range(0, len(segs), 120): + r = call(PUSH_JS % (PCB, MIL, json.dumps(segs[k:k + 120]), + json.dumps(vias if k == 0 else []), VIA_HOLE, VIA_D), + timeout=600) + n += r['ls'] + print(u' 下发 %d 段 / %d 过孔' % (r['ls'], r['vs'])) + call("await eda.pcb_Document.save(); return 1;") + print(u' 共 %d 段' % n) + + +def clear_mine(): + print(call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" + "const ls = (await eda.pcb_PrimitiveLine.getAll()||[])" + " .filter(l=>l.layer===1||l.layer===2).map(l=>l.primitiveId);" + "if (ls.length) await eda.pcb_PrimitiveLine.delete(ls);" + "const vs = (await eda.pcb_PrimitiveVia.getAll()||[]).map(v=>v.primitiveId);" + "if (vs.length) await eda.pcb_PrimitiveVia.delete(vs);" + "await eda.pcb_Document.save();" + "return {lines: ls.length, vias: vs.length};" % PCB, timeout=600)) + + +FAN_RING = 10 # 扇出找落点最多往外扫几圈（× G = 2.5 mm） +FAN_PITCH = 1.0 # 只给「邻脚中心距 < 这个值」的密脚做扇出 + + +def _pad_axis(pads_of_comp, q): + u"""焊盘的**出线方向**：沿长轴、背对本封装的重心。""" + cx = sum(p[2] for p in pads_of_comp) / float(len(pads_of_comp)) + cy = sum(p[3] for p in pads_of_comp) / float(len(pads_of_comp)) + if q[5] >= q[4]: # 竖着的盘 -> 上下出 + return (0.0, 1.0 if q[3] >= cy else -1.0) + return (1.0 if q[2] >= cx else -1.0, 0.0) + + +FANOUT_REFS = ('U2', 'U4', 'U3') # WQFN-20 0.5 / TSSOP-24 0.65 / MSOP-10 0.5 +FAN_NEAR, FAN_FAR = 0.55, 1.15 # 过孔中心离焊盘端的距离，相邻脚交替（两排） +FAN_MAX_W = 0.4 # 只扇信号（含 +3V3）；VO/$1N165 那种粗线靠直连的铜条 + + +def via_fanout(pads, bypad, segs, vias, auto): + u"""**交错两排的过孔扇出**（手工布细间距 IC 的标准做法）。 + + 每只信号脚沿焊盘长轴直着伸出一段 0.15 的引出脚，末端打一个 Ø0.5 的过孔上顶层； + 相邻脚一近一远交替（0.55 / 1.15），于是同一排过孔的节距是脚距的两倍、 + 远排的引出脚正好从近排两个过孔中间穿过（0.5 节距：0.5 − 0.25 − 0.075 = 0.175）。 + 干线从此全在**几乎是空的顶层**起步，细间距 IC 周围的底层不再是抢出口的战场。 + + ⚠ 与 `fanout()`（同层落点、已废）的区别就在「换层」：同层落点只是把地盘 + 提前占了，干线还是要从那一堆脚中间挤出去。 + + 落点冲突（别的网的焊盘 / 已有铜 / 已有过孔）就换另一排；两排都不行的脚原样交给 A*。 + 返回 (引出脚线段, 过孔, {网: [(原焊盘, vx, vy)]})。 + """ + bycomp = {} + for q in pads: + bycomp.setdefault(q[0], []).append(q) + laid = list(segs) + fan_vias = list(vias) # (x, y, net) + out_s, out_v, out_l = [], [], {} + r_via = VIA_D / 2.0 + want = {} + for net, ps in bypad.items(): + if rule_width(net, auto) > FAN_MAX_W + 1e-9: + continue + for q in ps: + if q[0] in FANOUT_REFS and not _is_launch(q) and (q[0], q[1]) not in KELVIN_PADS: + want[(q[0], q[1])] = (q, net) + for ref in FANOUT_REFS: + comp = bycomp.get(ref, []) + sides = {} + for q in comp: + if (q[0], q[1]) not in want: + continue + ax, ay = _pad_axis(comp, q) + key = (int(round(ax)), int(round(ay))) + sides.setdefault(key, []).append((q, ax, ay)) + for key, items in sides.items(): + # 沿着这一边排序：竖排按 y，横排按 x + items.sort(key=lambda t: t[0][3] if key[0] else t[0][2]) + for k, (q, ax, ay) in enumerate(items): + net = want[(q[0], q[1])][1] + half_len = (q[5] if abs(ay) > 0.5 else q[4]) / 2.0 + sw = stub_w(q, W_DEFAULT) + order = (FAN_NEAR, FAN_FAR) if k % 2 == 0 else (FAN_FAR, FAN_NEAR) + placed = None + for dist in order: + vx = q[2] + ax * (half_len + dist) + vy = q[3] + ay * (half_len + dist) + ok = True + # 别的网的焊盘（两层都要让：通孔） + for o in pads: + if o[7] == net: + continue + r = pad_rect(o) + d = math.hypot(max(r[0] - vx, 0.0, vx - r[2]), max(r[1] - vy, 0.0, vy - r[3])) + if d < r_via + CLR: + ok = False + break + # 引出脚本身也不许蹭到同层别的盘 + if o[6] == q[6] and seg_hits_rect(q[2], q[3], vx, vy, + (r[0] - CLR - sw / 2, r[1] - CLR - sw / 2, + r[2] + CLR + sw / 2, r[3] + CLR + sw / 2)): + ok = False + break + if not ok: + continue + for (l, a1, b1, c1, d1, ww, nn) in laid + out_s: + if nn == net: + continue + if _pt_seg_d(vx, vy, a1, b1, c1, d1) < r_via + ww / 2.0 + CLR: + ok = False + break + if l == q[6] and _seg_seg_d((q[2], q[3], vx, vy), (a1, b1, c1, d1)) < sw / 2.0 + ww / 2.0 + CLR: + ok = False + break + if not ok: + continue + for (ox, oy, on) in fan_vias: + if on == net: + continue + if math.hypot(ox - vx, oy - vy) < 2 * r_via + CLR + 0.05: + ok = False + break + if _pt_seg_d(ox, oy, q[2], q[3], vx, vy) < r_via + sw / 2.0 + CLR: + ok = False + break + if ok: + placed = (vx, vy) + break + if placed is None: + continue + vx, vy = placed + out_s.append((q[6], q[2], q[3], round(vx, 3), round(vy, 3), sw, net)) + out_v.append((round(vx, 3), round(vy, 3), net)) + fan_vias.append((vx, vy, net)) + out_l.setdefault(net, []).append((q, round(vx, 3), round(vy, 3))) + return out_s, out_v, out_l + + +def _pt_seg_d(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0.0 if L2 == 0 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2)) + return math.hypot(px - (x0 + dx * t), py - (y0 + dy * t)) + + +def _seg_seg_d(a, b): + (x0, y0, x1, y1), (u0, v0, u1, v1) = a, b + r = (x1 - x0, y1 - y0); s2 = (u1 - u0, v1 - v0) + den = r[0] * s2[1] - r[1] * s2[0] + if abs(den) > 1e-12: + t = ((u0 - x0) * s2[1] - (v0 - y0) * s2[0]) / den + u = ((u0 - x0) * r[1] - (v0 - y0) * r[0]) / den + if 0 <= t <= 1 and 0 <= u <= 1: + return 0.0 + return min(_pt_seg_d(x0, y0, *b), _pt_seg_d(x1, y1, *b), _pt_seg_d(u0, v0, *a), _pt_seg_d(u1, v1, *a)) + + +def fanout(pads, bypad, segs, vias, board_vias, auto): + u"""**扇出阶段**：布任何干线之前，先把每只焊盘的引出脚铺成真铜。 + + ⛔ 为什么必须独立成一阶段：出口是**抢**的。谁先布谁把邻脚的格点占掉， + 细间距 IC 的内侧脚必然最后一个布、也必然抢不到 —— 一轮下来 29~42 处 + 报「出不来」，而同样的摆位单独看每只脚**都是出得来的**（空占用图上 + `U4.5` 有 7 个出口，`U2.14` 有 4 个）。这就是手工布板「先做扇出、再拉干线」 + 的顺序，不是优化，是**必须**。 + + 两段式引出脚（细间距连接器靠它）：**先沿焊盘长轴直着出去**到本盘自己的 + 「车道」尽头，再拐到格点。`J4`（0.35 mm 间距、盘 0.18 宽）只有这一条路 —— + 盘心到邻盘边只有 0.26 mm，任何斜着走的引出脚都会蹭上邻盘（实测 0.047 mm）。 + + 返回 (引出脚线段, {网: [落点虚拟焊盘]}, 没出来的日志)。 + """ + bycomp = {} + for q in pads: + bycomp.setdefault(q[0], []).append(q) + laid = list(segs) # 已经有铜的（金手指扇出 / Kelvin / 直连） + launched, logs = {}, [] + # 宽的先扇出：它的落点要求最苛刻 + order = sorted(bypad, key=lambda n: -width_of(n, auto, bypad[n])) + for net in order: + ps = [q for q in bypad[net] if q[0] != 'J1'] + if not ps: + continue + w = width_of(net, auto, ps) + w = max(W_DEFAULT, min(w, min(min(q[4], q[5]) for q in ps))) + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a1, b1, c1, d1, ww, nn) in laid: + block_track(g, l, a1, b1, c1, d1, halfw + ww / 2.0, nn) + others = [pad_rect(q) for q in pads] + out = [] + # ⚠ **只扇密脚**。把每只脚都提前铺一段引出脚，等于在还不知道干线往哪走的时候 + # 就占地盘 —— 实测反而从 30 处涨到 40 处没接上。真正抢不到出口的只有 + # 细间距 IC 的内侧脚（邻脚中心距 < 1 mm），其余交给 A* 自己找更好。 + for q in ps: + near = min([math.hypot(q[2] - o[2], q[3] - o[3]) + for o in bycomp[q[0]] if o is not q] or [99]) + if near >= FAN_PITCH: + out.append(q) # 原样交给 A* + continue + sw = stub_w(q, w) + inf = STUB_CLR + sw / 2.0 + own = pad_rect(q) + oth = [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) + for r, p2 in zip(others, pads) + if p2[6] == q[6] and p2[7] != net + and max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + oth_pads = [o for o in ps if o is not q] + tx = (sum(o[2] for o in oth_pads) / len(oth_pads)) if oth_pads else q[2] + ty = (sum(o[3] for o in oth_pads) / len(oth_pads)) if oth_pads else q[3] + ax, ay = _pad_axis(bycomp[q[0]], q) + reach = (q[5] if ay else q[4]) / 2.0 + inf + ex, ey = q[2] + ax * reach, q[3] + ay * reach + best = None + for ring in range(1, FAN_RING + 1): + r = ring * G + cand = [] + for j in range(gy(ey - r), gy(ey + r) + 1): + for i in range(gx(ex - r), gx(ex + r) + 1): + X, Y = wx(i), wy(j) + if not g.free(q[6], i, j, net): + continue + if any(seg_hits_rect(q[2], q[3], ex, ey, o) for o in oth): + continue + if any(seg_hits_rect(ex, ey, X, Y, o) for o in oth): + continue + if not _stub_clear(g, q[6], q[2], q[3], X, Y, net): + continue + # ⚠ 落点**朝目的地挑**，不是挑离焊盘最近的： + # 引出脚指错方向，后面干线要绕回来，还把路占了。 + cand.append((math.hypot(X - tx, Y - ty), + math.hypot(X - ex, Y - ey), i, j)) + if cand: + cand.sort() + best = cand[0] + break + if best is None: + logs.append(u'%s: %s.%s 扇不出来' % (net, q[0], q[1])) + continue + _d, _d2, i, j = best + X, Y = wx(i), wy(j) + if math.hypot(ex - q[2], ey - q[3]) > 1e-6: + laid.append((q[6], q[2], q[3], ex, ey, sw, net)) + laid.append((q[6], ex, ey, X, Y, sw, net)) + block_track(g, q[6], q[2], q[3], ex, ey, halfw + sw / 2.0, net) + block_track(g, q[6], ex, ey, X, Y, halfw + sw / 2.0, net) + out.append([q[0], 'fan:' + str(q[1]), X, Y, 0.3, 0.3, q[6], net, 'RECT']) + if out: + launched[net] = out + return laid[len(segs):], launched, logs + + +LINK_MAX = 2.2 # 直连允许的最大焊盘净距 + + +def _pad_gap(a, b): + dx = max(abs(a[2] - b[2]) - (a[4] + b[4]) / 2.0, 0.0) + dy = max(abs(a[3] - b[3]) - (a[5] + b[5]) / 2.0, 0.0) + return math.hypot(dx, dy) + + +AUTO_CACHE = {} + + +def direct_links(pads, bypad, segs, vias, blocked_rects=()): + u"""**焊盘对焊盘**的短连接直接画一段铜，不交给 A*。 + + ⛔ 为什么非要有这一步：A* 的占用图是按**干线宽度**建的。`SWNODE` 是 2.0 mm ⇒ + 半宽 + 净距 = 1.18 mm，于是 `U1` 的 SW 脚（0.5 mm 间距）周围**一个格点都不空**， + 报「$1N137: U1.11 出不来」。可这条连接根本不需要 A* —— 摆位时就是 + **焊盘正对焊盘、净距 0.65 mm**，人手画就是一段直铜。 + 同一类的还有 `VO`(L1→C6)、`$1N165`(U2→Rs1)、`+12V_F`(Cin→U1)。 + + 宽度取**两个焊盘在垂直于连线方向上的较小者** —— 再宽也没用， + 电流的瓶颈就是 IC 自己的脚。 + + 判据：同层、同网、净距 ≤ `LINK_MAX`，且连线走廊里没有第三个焊盘、 + 没有已布的铜、没有过孔。 + """ + out, merged = [], {} + others = {} + for q in pads: + others.setdefault(q[6], []).append(q) + for net, ps in sorted(bypad.items()): + cand = [q for q in ps if q[0] != 'J1'] + groups = [] + for i in range(len(cand)): + for j in range(i + 1, len(cand)): + a, b = cand[i], cand[j] + if a[6] != b[6]: + continue + if _pad_gap(a, b) > LINK_MAX: + continue + # 垂直于连线方向的可用宽度 + dx, dy = abs(a[2] - b[2]), abs(a[3] - b[3]) + wa = a[5] if dx >= dy else a[4] + wb = b[5] if dx >= dy else b[4] + w = round(max(rule_min(net, AUTO_CACHE), min(wa, wb)), 3) + if w < 0.15: + continue + inf = CLR + w / 2.0 + bad = False + for owner, rr in blocked_rects: + if owner == net: + continue + r = (rr[0] - inf, rr[1] - inf, rr[2] + inf, rr[3] + inf) + if seg_hits_rect(a[2], a[3], b[2], b[3], r): + bad = True + break + for q in others.get(a[6], []): + # ⚠ **同网的焊盘不算障碍** —— 压上去也是同一个节点。 + # 漏了这一条，`U1` 的两只 SW 脚会互相判死：11 脚要接 L1， + # 12 脚（同网、隔 0.5 mm）挡在旁边，于是「U1.11 出不来」。 + if q[7] == net or (q[0], q[1]) in ((a[0], a[1]), (b[0], b[1])): + continue + r = pad_rect(q, inf) + if seg_hits_rect(a[2], a[3], b[2], b[3], r): + bad = True + break + if not bad: + for (l, x0, y0, x1, y1, ww, nn) in segs: + if l != a[6] or nn == net: + continue + if seg_seg_dist(a[2], a[3], b[2], b[3], x0, y0, x1, y1) < inf + ww / 2.0: + bad = True + break + if not bad: + for (vx, vy, nn) in vias: + if nn == net: + continue + if seg_hits_rect(a[2], a[3], b[2], b[3], + (vx - VIA_D / 2 - inf, vy - VIA_D / 2 - inf, + vx + VIA_D / 2 + inf, vy + VIA_D / 2 + inf)): + bad = True + break + if bad: + continue + out.append((a[6], a[2], a[3], b[2], b[3], w, net)) + ka, kb = (a[0], a[1]), (b[0], b[1]) + ga = next((g for g in groups if ka in g), None) + gb = next((g for g in groups if kb in g), None) + if ga is None and gb is None: + groups.append({ka, kb}) + elif ga is None: + gb.add(ka) + elif gb is None: + ga.add(kb) + elif ga is not gb: + ga |= gb + groups.remove(gb) + if groups: + merged[net] = groups + return out, merged + + +def seg_seg_dist(x1, y1, x2, y2, x3, y3, x4, y4): + u"""两条线段的最小距离（够用的粗算：端点到线段 + 采样）。""" + def pt_seg(px, py, ax, ay, bx, by): + dx, dy = bx - ax, by - ay + L = dx * dx + dy * dy + t = 0.0 if L == 0 else max(0.0, min(1.0, ((px - ax) * dx + (py - ay) * dy) / L)) + return math.hypot(px - (ax + t * dx), py - (ay + t * dy)) + return min(pt_seg(x1, y1, x3, y3, x4, y4), pt_seg(x2, y2, x3, y3, x4, y4), + pt_seg(x3, y3, x1, y1, x2, y2), pt_seg(x4, y4, x1, y1, x2, y2)) + + +VIA_MIN_D = VIA_D # 同网过孔的最小中心距 = 钻孔间距 0.3 + 钻孔径 0.3 + + +def dedupe_vias(segs, vias): + u"""同一个网上**挨得太近的过孔**合成一个。 + + ⛔ 占用图是「按网可进」的，所以同一个网的两条支路可以各自在几乎同一个点换层 —— + 几何上不冲突，但**钻孔到钻孔**的规则不认网：DRC 报 + 「钻孔 (SCL) 到 钻孔 (SCL) 距离为 0 mil，应该 >= 11.8 mil」。 + 自算净距那一支也抓不到（`router_check` 只判铜与铜，钻孔那一支归 EasyEDA）。 + + 合并判据：同网、中心距 < `VIA_MIN_D`(=0.6 mm)。这时两个过孔的**焊盘本来就重叠**， + 所以补一小段两层导线把被删的那个点接回保留点，不会伸出原来的铜之外。 + """ + keep, drop = [], {} + for (x, y, net) in vias: + hit = None + for (kx, ky, kn) in keep: + if kn == net and math.hypot(kx - x, ky - y) < VIA_MIN_D - 1e-9: + hit = (kx, ky) + break + if hit is None: + keep.append((x, y, net)) + else: + drop[(round(x, 4), round(y, 4), net)] = hit + if drop: + print(u'同网过孔合并 %d 个（中心距 < %.2f mm）' % (len(drop), VIA_MIN_D)) + for (x, y, net), (kx, ky) in drop.items(): + w = max(0.2, rule_min(net, AUTO_CACHE)) + for l in LAY: + segs.append((l, x, y, kx, ky, w, net)) + return segs, keep + + +PASSES = 4 # 失败重试轮数（拆线重布接手之后不必太多） +CACHE = os.path.join(HERE, '_blade_routes.json') + + +# ══════════════════════════════════════════════════════════════════════ +# 协商式拥塞布线（PathFinder） +# ══════════════════════════════════════════════════════════════════════ +# ⛔ 为什么非要换算法：这个「一次布死、不回退」的 A* 到 23 条就不动了。 +# 试过顺序、扇出、过路费、L 形引出脚、正交方向、拆线重布、难的先布 —— 全在 +# 12~23 之间打转。根因是**它没有让路机制**：谁先占住走廊，后来的就只能报失败。 +# +# PathFinder 的做法（Nair 1987 / McMurchie-Ebeling 1995）： +# 1. 每一轮**所有网都重新布一遍**，允许暂时压在别人身上（不是硬障碍，是加钱）； +# 2. 一轮结束后，把**被多个网压着的格点**的「历史代价」加一档； +# 3. 下一轮大家再抢，历史贵的地方自然有人让开 —— 谁绕路代价小谁让。 +# 反复若干轮直到没有格点被两个网同时占。这就是「协商」。 +# ⚠ 调度是 PathFinder 的命门。第一版「每轮翻倍、封顶 64」**不收敛** —— +# 冲突 1790→1062 之后在 1200 附近震荡：当前代价涨得太快，网被推得来回横跳， +# 历史代价还没来得及把「谁该让」这件事沉淀下来。 +# 改成教科书的慢涨（×1.25），并让历史按**超用量**累加。 +PF_PRESENT = [1.0] # 当前拥塞权重，每轮 ×PF_GROW +PF_GROW = 1.25 +PF_HIST_W = 4 # 历史拥塞权重 +PF_ITERS = 30 + + +def _route_cells(segs_of_net, halfw): + u"""一条线占的格点。 + + ⛔ 膨胀量是 **线半宽 + 净距/2**，不是 `halfw + w/2`（= 线宽 + 净距）。 + 两条线各膨胀「半宽 + 净距/2」之后**刚好在净距处相切** —— 这才是 + 「再近一点就违规」的判据。按 `halfw + w/2` 膨胀的话，两根**正好隔着 + 合法净距**的线也会共占格点，于是 PF 一直在追逐根本不存在的冲突， + 冲突数卡在 800 上下永远收敛不了（实测 2678→823 就不动了）。 + """ + out = set() + for (l, x0, y0, x1, y1, w, _n) in segs_of_net: + r = w / 2.0 + CLR / 2.0 + steps = int(max(abs(x1 - x0), abs(y1 - y0)) / (G / 2)) + 1 + for k in range(steps + 1): + t = k / float(steps) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + for j in range(gy(y - r), gy(y + r) + 1): + for i in range(gx(x - r), gx(x + r) + 1): + if 0 <= i < NX and 0 <= j < NY: + out.add((l, i, j)) + return out + + +def _pf_mark(occ, cells, d): + for (l, i, j) in cells: + o = j * NX + i + v = occ[l][o] + d + occ[l][o] = max(0, min(250, v)) + + +def _exact_conflicts(cur, pads): + u"""按**精确几何**找出真正压在一起的网（判据同 router_check：净距 < MIN_CLR）。 + + ⚠ **过孔那一支不能漏**：只查线与线的话，会漏掉「过孔压在另一面的焊盘上」 + 和「两个不同网的过孔叠在一起」—— 实测漏掉了 `PRSNT#` 的孔压在 `J2.5`(GND) + 盘上（净距 −0.300）和 `+12V_F` / `$1N131` 两个孔叠了 0.041。 + 通孔是穿两层的，所以焊盘那一支**两层都要查**。 + """ + MIN = 0.15 + items = [] + allv = [] + for net, (s2, v2, _c) in cur.items(): + for t in s2: + items.append((t[0], t[1], t[2], t[3], t[4], t[5], net)) + for (vx, vy, _q) in v2: + allv.append((vx, vy, net)) + # 按 y 粗分桶，避免 O(n^2) 全比 + bad = set() + n = len(items) + for i in range(n): + a = items[i] + ay0, ay1 = min(a[2], a[4]), max(a[2], a[4]) + ax0, ax1 = min(a[1], a[3]), max(a[1], a[3]) + for j in range(i + 1, n): + b = items[j] + if b[6] == a[6] or b[0] != a[0]: + continue + if min(b[2], b[4]) > ay1 + 1.0 or max(b[2], b[4]) < ay0 - 1.0: + continue + if min(b[1], b[3]) > ax1 + 1.0 or max(b[1], b[3]) < ax0 - 1.0: + continue + d = seg_seg_dist(a[1], a[2], a[3], a[4], b[1], b[2], b[3], b[4]) + if d - a[5] / 2.0 - b[5] / 2.0 < MIN - 1e-9: + bad.add(a[6]) + bad.add(b[6]) + # 过孔 vs 焊盘（两层都查，通孔穿透） + for (vx, vy, net) in allv: + for q in pads: + if q[7] == net: + continue + dx = max(q[2] - q[4] / 2 - vx, 0.0, vx - (q[2] + q[4] / 2)) + dy = max(q[3] - q[5] / 2 - vy, 0.0, vy - (q[3] + q[5] / 2)) + if math.hypot(dx, dy) - VIA_D / 2.0 < MIN - 1e-9: + bad.add(net) + break + # 过孔 vs 过孔（异网） + for i in range(len(allv)): + for j in range(i + 1, len(allv)): + if allv[i][2] == allv[j][2]: + continue + if math.hypot(allv[i][0] - allv[j][0], allv[i][1] - allv[j][1]) - VIA_D < MIN - 1e-9: + bad.add(allv[i][2]) + bad.add(allv[j][2]) + return bad + + +def pf_solve(bypad, pads, segs, vias, board_vias, auto, fixed_s, fixed_v): + u"""对 `bypad` 里所有网做协商式拥塞布线。原地改 segs/vias，返回没搞定的日志。""" + occ = {l: bytearray(NX * NY) for l in LAY} + hist = {l: bytearray(NX * NY) for l in LAY} + base_s, base_v = segs[:fixed_s], vias[:fixed_v] + + # 每个网一份线宽 / 半宽；硬障碍图按宽度分档建一次就够 + wof, hard = {}, {} + for net, ps in bypad.items(): + w = width_of(net, auto, ps) + small = w if net in NO_CAP else min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [w]) + wof[net] = max(W_DEFAULT, rule_min(net, auto), min(w, small)) + for w in sorted(set(wof.values())): + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a, b, c, d, ww, nn) in base_s: # 前置阶段的铜是硬障碍 + # ⛔ `extra` 不能用默认的 0：`block_both` 的第二张图（`ownv`）是**换层判据**， + # 不给额外膨胀的话，别人的过孔可以直接落在这根线上 —— + # DRC 报「导线到过孔 0 mil」，实测两处（`EFUSE_EN` 的孔压 `$1N147`、 + # `$1N164` 的孔压 `EFUSE_PG`），而线与线那一支干干净净，很难看出来是谁的错。 + block_track(g, l, a, b, c, d, halfw + ww / 2.0, nn, + extra=max(0.0, VIA_D / 2.0 + CLR - (halfw + ww / 2.0))) + for (vx, vy, nn) in base_v: + for l in LAY: + g.block_rect(l, vx - VIA_D / 2 - halfw, vy - VIA_D / 2 - halfw, + vx + VIA_D / 2 + halfw, vy + VIA_D / 2 + halfw, net=nn) + g.occ, g.hist = occ, hist + hard[w] = g + + others = {1: [], 2: []} + for p in pads: + if p[6] in others: + others[p[6]].append(pad_rect(p)) + + cur = {} # net -> (segs, vias, cells) + order = sorted(bypad, key=lambda n: -wof[n]) + logs = [] + best = None + for it in range(PF_ITERS): + logs = [] + for net in order: + old = cur.pop(net, None) + if old: + _pf_mark(occ, old[2], -1) + w = wof[net] + g = hard[w] + halfw = w / 2.0 + CLR + s2, v2, st2 = route_net(g, net, bypad[net], halfw, w, others, logs, + None, mutate=False) + for (q, node, ww) in st2: + s2 = s2 + stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net) + cells = _route_cells(s2, halfw) + _pf_mark(occ, cells, +1) + cur[net] = (s2, v2, cells) + # 一轮结束：给被多个网压着的格点按**超用量**加历史代价 + bad = 0 + for l in LAY: + oc, hi = occ[l], hist[l] + for o in range(NX * NY): + if oc[o] > 1: + bad += 1 + hi[o] = min(250, hi[o] + oc[o] - 1) + print(u' PF 第 %d 轮：冲突格点 %d，没布通 %d（present=%.1f）' + % (it + 1, bad, len(logs), PF_PRESENT[0])) + if best is None or (bad, len(logs)) < best[0]: + best = ((bad, len(logs)), {n: (list(a2), list(b2), set(c2)) + for n, (a2, b2, c2) in cur.items()}, list(logs)) + if bad == 0 and not logs: + break + PF_PRESENT[0] *= PF_GROW + # 取**冲突最少的那一轮**，不是最后一轮 + if best is not None: + cur, logs = best[1], list(best[2]) + + # ⛔ **格点冲突 ≠ 真违规**。0.25 mm 的格子表示不了 0.35 mm 间距的分离， + # 所以 PF 的冲突数里混着大量**量化假象**（卡在 ~895 下不去就是这个原因）。 + # 真正的判据是**精确几何**（和 router_check 同一套）。这里按精确距离筛一遍， + # 只把**真的**压在一起的网拿去重布。 + real = _exact_conflicts(cur, pads) + if real: + print(u' 精确几何：真违规涉及 %d 个网 —— %s' + % (len(real), ' '.join(sorted(real)[:10]))) + base_cells = {} + for n2, (s2, v2, c2) in cur.items(): + if n2 not in real: + base_cells[n2] = (s2, v2, c2) + ns = list(base_s) + [t for n2 in base_cells for t in base_cells[n2][0]] + nv = list(base_v) + [(x, y, n2) for n2 in base_cells + for (x, y, _q) in base_cells[n2][1]] + sub = route_groups(bypad, pads, ns, nv, board_vias, auto, + priority=tuple(real), only=set(real)) + logs += sub + del segs[fixed_s:] + del vias[fixed_v:] + segs += ns[len(base_s):] + vias += nv[len(base_v):] + return logs + # ⛔ **绝不能把还有冲突的解下发**（那是真短路）。还剩冲突就逐个丢掉 + # 「压着别人最多」的那个网，直到干净为止，丢掉的如实报成没布通。 + while True: + occ2 = {l: bytearray(NX * NY) for l in LAY} + for _n, (_s, _v, c2) in cur.items(): + _pf_mark(occ2, c2, +1) + blame = {} + for net, (_s, _v, c2) in cur.items(): + k = sum(1 for (l, i, j) in c2 if occ2[l][j * NX + i] > 1) + if k: + blame[net] = k + if not blame: + break + worst = max(blame, key=lambda n: (blame[n], wof[n])) + del cur[worst] + logs.append(u'%s: 让路（协商后仍有冲突，整条丢弃）' % worst) + del segs[fixed_s:] + del vias[fixed_v:] + for net, (s2, v2, _c) in cur.items(): + segs += s2 + vias += [(x, y, net) for (x, y, _n) in v2] + return logs + + +if __name__ == '__main__': + if '--clear' in sys.argv: + clear_mine() + sys.exit(0) + # 算一次要好几分钟，结果落盘；--push 默认吃缓存，加 --replan 才重算。 + if '--replan' not in sys.argv and os.path.exists(CACHE): + c = json.load(io.open(CACHE, encoding='utf-8')) + segs, vias, logs = c['segs'], c['vias'], c['logs'] + print(u'（用缓存 _blade_routes.json）') + else: + # ⛔ **一轮布不完是正常的**：谁先布谁占走廊，后布的就没路。 + # 没有 rip-up 的话，最有效的补救是「**这一轮没接上的，下一轮排最前面**」， + # 跑几轮取最好的一轮。实测 30 -> 个位数。 + best, prio = None, set() + for it in range(1 if '--pf' in sys.argv else PASSES): + segs, vias, logs = plan_all(prio) + print(u' 第 %d 轮：%d 条没搞定' % (it + 1, len(logs))) + if best is None or len(logs) < len(best[2]): + best = (segs, vias, logs) + if not logs: + break + prio |= set(_msg_net(m) for m in logs) + segs, vias, logs = best + io.open(CACHE, 'w', encoding='utf-8').write( + json.dumps({'segs': segs, 'vias': vias, 'logs': logs}, ensure_ascii=False)) + tot = sum(math.hypot(s[3] - s[1], s[4] - s[2]) for s in segs) + print(u'导线 %d 段 / 总长 %.1f mm / 过孔 %d' % (len(segs), tot, len(vias))) + nets = {} + for s in segs: + nets[s[6]] = nets.get(s[6], 0) + 1 + print(u'涉及 %d 个网络' % len(nets)) + if logs: + print(u'[!] %d 条没搞定:' % len(logs)) + for m in logs[:40]: + print(u' ' + m) + if '--push' in sys.argv: + push(segs, vias) diff --git a/.claude/r2/archive_base2L/rules_base.py b/.claude/r2/archive_base2L/rules_base.py new file mode 100644 index 0000000..7eebcd9 --- /dev/null +++ b/.claude/r2/archive_base2L/rules_base.py @@ -0,0 +1,359 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 的设计规则（M8b）。 + + /c/Python314/python .claude/r2/rules_base.py # 只反查 + 打印，不下发 + /c/Python314/python .claude/r2/rules_base.py --dump # 重抓「位号.引脚 → 网名」 + /c/Python314/python .claude/r2/rules_base.py --push # 下发规则 + 差分对 + 网络指派 + /c/Python314/python .claude/r2/rules_base.py --audit # 读回审计 + +做法与 `pcb_rules.py`（刀片）同源，**那一份的文件头是唯一的说明书**，四个坑一个没变： + + · `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装 + · `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状** + · 下发之后**别再去 GUI 换「配置」下拉框** —— 换一次整套重置，网络指派全部悬空 + · `overwriteNetRules` / `overwriteNetByNetRules` 都是**整表覆盖**，先读回再合并 + +## 和刀片那份不同的四处 + +1. **两层板**，当前配置是 `JLCPCB Capability(Two Layers Board)`： + `Track` / `Safe Spacing` 下只有 `copperThickness1oz` / `2oz` 两条， + **没有内层条目**，所以刀片那段「补 0.5 oz 内层」整块删掉。 + +2. **入口链是 9 A**（方案 §6.4），不是刀片的 1.45 A。线宽规则给到 + `strokeWidthMax = 12`，真正的载流靠 `pour_base` 的断面校核保证，不靠 DRC。 + +3. **七对差分**：五个槽 + ESP32 原生 USB（D13）+ 上行 USB-C。 + 刀片那组 `W 0.28 / S 0.18` 是**四层薄介质**的数，两层 1.6 mm 板照搬会变成 ~137 Ω。 + 按方案 §6.3 取 **W 1.2 / S 0.2 ⇒ ~94 Ω**。 + ⚠ `min` 必须留到 0.25：1.2 的线接不进 U32 那颗 0.5 mm 间距 QFN-64 的焊盘， + 末端一定要缩颈，min 卡在 1.2 会把整条线判成违规。 + +4. **自动命名网一个都不指派**：底板上 22 个 `$xNyy` 全是小信号 + （泄放电阻串、Buck 反馈、DAC 的 RC、风扇 MOS 栅极），走默认线宽即可。 + ⇒ 没有「按位号.引脚反查自动网名」那一步，也就没有那一类静默失效。 +""" +import io +import json +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +PCB = B.PCB +LAYERS = 2 +NETS_FILE = os.path.join(HERE, '_base_pcb_nets.json') + +# ── 线宽规则（mm，外层 1 oz）──────────────────────────────────────────── +# 载流靠灌铜断面保证、不靠 DRC；min 一律压到 0.15~0.3，否则 0402 焊盘扇不出去。 +TRACK_RULES = { + 'PWR9A': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.30, 'strokeWidthMax': 12.0}, + 'PWR12V': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.30, 'strokeWidthMax': 12.0}, + 'FAN12V': {'strokeWidthDefault': 0.8, 'strokeWidthMin': 0.25, 'strokeWidthMax': 3.0}, + 'PWR5V': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.20, 'strokeWidthMax': 3.0}, + 'PWR3V3': {'strokeWidthDefault': 0.5, 'strokeWidthMin': 0.15, 'strokeWidthMax': 3.0}, +} + +# ── 有名字的网络 → 线宽规则 ──────────────────────────────────────────── +# ⚠ `+12V` 是**一个网**：从 Rs6 下游一路到 5 个槽的 12V 针（43 只脚）。 +# 干路 9 A 那一段和「母线 → 单槽」1.5 A 那一段线宽不同，DRC 只能按一条规则判 ⇒ +# 取干路的 `PWR9A`（default 2.0 只是画线的起手宽度），断面由 `pour_base` 逐段校核。 +NET_TRACK = { + 'VIN_RAW': 'PWR9A', # J1 中心极 → F1 + 'VIN_FUSED': 'PWR9A', # F1 → Q1 反接保护 + 'VIN_SW': 'PWR9A', # Q1 → 储能 → Rs6 上游 + '+12V': 'PWR9A', # Rs6 下游 → 母线 → 5 槽 + 两颗 Buck + 风扇 + 'FAN_12V_SW': 'FAN12V', # 风扇下管开关点（R1 §22.6 定的 0.8） + '+5V': 'PWR5V', # U30 → 5 槽（每槽给刀片 U5 TPS22918） + '+3V3': 'PWR3V3', # U19 → ESP32 / mux / DAC / 5 槽逻辑 + '+3V3_HUB': 'PWR3V3', # U31 AMS1117 → U32（与 +3V3 只共地） +} + +# ── 铺铜焊盘全连接（理由同刀片：不是怕十字花烧，是**铺完之后断面要量得准**）── +PLANE_RULE = 'PLANE-DIRECT' +PLANE_CONNECT_DIRECT = 1 +PLANE_NETS = ['VIN_RAW', 'VIN_FUSED', 'VIN_SW', '+12V'] + +# ── 差分对（mm）── 方案 §6.3：两层 1.6 mm 微带，W 1.2 / S 0.2 ⇒ ~94 Ω ── +DIFF = {'strokeWidthDefault': 1.2, 'strokeWidthMin': 0.25, 'strokeWidthMax': 1.6, + 'differentailPairSpacingDefault': 0.20, 'differentailPairSpacingMin': 0.15, + 'differentailPairLenTolerMax': 1.0} # intra-pair skew 目标 ≤1 mm（§6.3） +PAIR_RULE = 'USBPAIR' +PAIR_CLEARANCE = 0.20 +PAIRS = [('USB1', 'USB1_DP', 'USB1_DM'), + ('USB2', 'USB2_DP', 'USB2_DM'), + ('USB3', 'USB3_DP', 'USB3_DM'), + ('USB4', 'USB4_DP', 'USB4_DM'), + ('USB5', 'USB5_DP', 'USB5_DM'), + ('USB6', 'USB6_DP', 'USB6_DM'), # D13：Hub 第 6 口 → ESP32 原生 USB + ('USBUP', 'UP_DP', 'UP_DM')] # J23 USB-C → U32 上行 + +# ⚠ 0.2，不是刀片的 0.15。两层板走 JLC 标准工艺（0.2/0.2）最便宜， +# 而底板上最紧的封装是 U32 QFN-64（0.5 间距）与 J23 USB-C，实测都过得去。 +# 真刷出「贴片焊盘到贴片焊盘」的假错（全落在某个买来的封装内部）再降到 0.15。 +MIN_CLEARANCE = 0.20 + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" % PCB) + + +def call(body, timeout=300): + r = run(OPEN + body, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def dump_nets(): + u"""重抓「位号.引脚 → 网名」。**每次导入变更之后必跑**。""" + r = call("const out = {};" + "for (const c of await eda.pcb_PrimitiveComponent.getAll()) {" + " const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(" + " c.getState_PrimitiveId());" + " out[c.designator] = ps.map(p=>[p.padNumber, p.net]); }" + "return out;") + io.open(NETS_FILE, 'w', encoding='utf-8').write(json.dumps(r, ensure_ascii=False)) + print(u'已写 _base_pcb_nets.json：%d 件' % len(r)) + return r + + +def nets(): + if not os.path.exists(NETS_FILE): + return dump_nets() + return json.load(io.open(NETS_FILE, encoding='utf-8')) + + +def check_names(): + u"""下发前先确认：要指派的网名在板上真的存在（写错名字 = 规则悬空，DRC 不报）。""" + have = set() + for _ref, pads in nets().items(): + for _pn, net in pads: + if net: + have.add(net) + miss = [n for n in sorted(set(list(NET_TRACK) + PLANE_NETS)) if n not in have] + pmiss = [p for t in PAIRS for p in t[1:] if p not in have] + if miss or pmiss: + print(u' [!!] 板上没有这些网，**不下发**：线宽/铺铜 %s；差分 %s' % (miss, pmiss)) + sys.exit(1) + return True + + +CAP_JS = u""" +const D = eda.pcb_Drc; +const cur = await D.getCurrentRuleConfiguration(); +const c = JSON.parse(JSON.stringify(cur.config)); +const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s; +const PLANERULE = %s, PLANEMODE = %s; + +const setTrack = (e, mn, df, mx) => { + for (const k of Object.keys(e.form.data)) + Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx}); +}; +const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing']; + +setTrack(T['copperThickness1oz'], 0.127, 0.254, 2.54); +Object.assign(c['Physics']['Via Size']['viaSize'].form, + {viaOuterdiameterMin: 0.4, viaInnerdiameterMin: 0.3}); +for (const name of Object.keys(TRACKS)) { + const f = TRACKS[name]; + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = name; e.isSetDefault = false; e.unit = 'mm'; + setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax); + T[name] = e; +} +const dp = c['Physics']['Differential Pair']['differentialPair'].form; +for (const k of Object.keys(dp.strokeWidthTables.data)) + Object.assign(dp.strokeWidthTables.data[k], + {minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault, + maxValue: DW.strokeWidthMax}); +for (const k of Object.keys(dp.diffPairSpacingTables.data)) + Object.assign(dp.diffPairSpacingTables.data[k], + {minValue: DW.differentailPairSpacingMin, + defaultValue: DW.differentailPairSpacingDefault}); +dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax; +if (!SS[PAIRRULE]) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = PAIRRULE; e.isSetDefault = false; + for (const tk of Object.keys(e.tables || {})) + for (const row of (e.tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number') row[i] = PAIRC; + SS[PAIRRULE] = e; +} +// 安全间距全表**归一到 MINC**：≤0.2 的格子一律赋值成 MINC（不是「只抬不降」）； +// 0.254 / 0.3 那几格是孔/板边相关的，不动。 +let bumped = 0; +for (const key of Object.keys(SS)) + if (key !== PAIRRULE) + for (const tk of Object.keys(SS[key].tables || {})) + for (const row of (SS[key].tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number' && row[i] <= 0.2001 && + Math.abs(row[i] - MINC) > 1e-6) { row[i] = MINC; bumped++; } +const CZ = c['Plane']['Copper Zone']; +if (!CZ[PLANERULE]) { + const e = JSON.parse(JSON.stringify(CZ['copperRegion'])); + e.editName = PLANERULE; e.isSetDefault = false; + CZ[PLANERULE] = e; +} +for (const m of ['singleLayerPadModel', 'multiLayerPadModel']) + for (const k of Object.keys(CZ[PLANERULE].form[m].data)) + CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE; + +const ok = await D.overwriteCurrentRuleConfiguration(c); +return {ok: ok === true, bumped: bumped, name: cur.name, + track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)}; +""" + + +def push(): + check_names() + r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE, + json.dumps(PAIR_RULE), PAIR_CLEARANCE, + json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT)) + if not r.get('ok'): + print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效') + sys.exit(1) + print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track'])) + print(u' 安全间距归一 %d 格 → %.2f mm；配置名 "%s"' % (r['bumped'], MIN_CLEARANCE, r['name'])) + + n = call(""" +const P = %s; +let k = 0; +for (const d of await eda.pcb_Drc.getAllDifferentialPairs()) + await eda.pcb_Drc.deleteDifferentialPair(d.name); +for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; } +return k; +""" % json.dumps(PAIRS)) + print(u' 差分对 %d / %d 对' % (n, len(PAIRS))) + if n != len(PAIRS): + print(u' [!!] 有对没建上 —— 网络名在这块板上不存在') + + n = call(""" +const T = %s, PN = %s, PR = %s; +const pset = new Set(PN); +const rules = await eda.pcb_Drc.getNetRules(); +let k = 0, p = 0; +const seen = []; +for (const r of rules) { + if (r.type !== 'net') continue; + if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); } + if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; } +} +await eda.pcb_Drc.overwriteNetRules(rules); +return {track: k, plane: p, seen: seen}; +""" % (json.dumps(NET_TRACK, ensure_ascii=False), json.dumps(PLANE_NETS, ensure_ascii=False), + json.dumps(PLANE_RULE))) + print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(NET_TRACK))) + if n['track'] != len(NET_TRACK): + print(u' [!!] 板上找不到: %s' % ' '.join(sorted(set(NET_TRACK) - set(n['seen'])))) + print(u' 铺铜全连接指派 %d / %d（%s）' % (n['plane'], len(PLANE_NETS), ' '.join(PLANE_NETS))) + + n = call(""" +const PAIRS = %s, RULE = %s; +const cur = await eda.pcb_Drc.getNetByNetRules(); +const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : []; +const key = e => [e.net1.name, e.net2.name].sort().join('|'); +const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|'))); +const list = []; +let dropped = 0; +for (const e of old) { + if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; } + list.push(e); +} +const have = new Set(list.map(key)); +let k = 0; +for (const [name, dp, dm] of PAIRS) { + const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm}, + rule: RULE, copperRuleName: null, planeRuleName: null}; + if (have.has(key(e))) continue; + list.push(e); k++; +} +const ok = await eda.pcb_Drc.overwriteNetByNetRules( + {'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []}); +const back = await eda.pcb_Drc.getNetByNetRules(); +return {added: k, dropped: dropped, ok: ok === true, + now: (back['Safe Spacing'] || []).length}; +""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE))) + print(u' 对内间距：新增 %d / 清掉过期 %d，现共 %d 条（%s = %.2f mm）' + % (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE)) + + call("await eda.pcb_Document.save(); return 1;") + print(u' 已保存') + print(u'') + print(u'⚠ 别去 GUI 的 设计 → 设计规则… 里换「配置」下拉框：换一次整套重置，') + print(u' %d 个网络的线宽指派立刻悬空，而 DRC 不会报错。' % len(NET_TRACK)) + print(u'⚠ 再导入一次变更之后顺序是：--dump → --push，少跑 --dump 就是拿旧网名指派。') + + +AUDIT_JS = u""" +const c = await eda.pcb_Drc.getCurrentRuleConfiguration(); +const rules = await eda.pcb_Drc.getNetRules(); +const nbn = await eda.pcb_Drc.getNetByNetRules(); +return { + cfgName: c && c.name, + layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(), + track: Object.keys(c.config.Physics['Track']), + pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(), + assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default') + .map(r => [r.name, r['Track']]).sort(), + planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default') + .map(r => [r.name, r['Copper Zone']]).sort(), + nbn: ((nbn && nbn['Safe Spacing']) || []).length, +}; +""" + + +def audit(): + r = call(AUDIT_JS) + bad = [] + + def chk(cond, good, msg): + print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg)) + if not cond: + bad.append(msg) + + print(u'──── 审计（配置 "%s"）────' % r['cfgName']) + chk(r['layers'] == LAYERS, u'铜层数 %d' % LAYERS, u'铜层数是 %s，应为 %d' % (r['layers'], LAYERS)) + miss = [k for k in TRACK_RULES if k not in r['track']] + chk(not miss, u'%d 条线宽条目都在' % len(TRACK_RULES), u'缺线宽条目 %s' % miss) + got = dict(r['assigned']) + wrong = [(n, got.get(n), v) for n, v in sorted(NET_TRACK.items()) if got.get(n) != v] + chk(not wrong, u'%d 个网络的线宽指派全对' % len(NET_TRACK), u'指派不对: %s' % wrong[:6]) + chk(sorted(r['pairs']) == sorted([p[0] for p in PAIRS]), + u'差分对 %d 对: %s' % (len(r['pairs']), ' '.join(r['pairs'])), + u'差分对是 %s，应为 %s' % (r['pairs'], [p[0] for p in PAIRS])) + chk(r['nbn'] == len(PAIRS), u'对内间距 %d 条' % r['nbn'], + u'对内间距 %d 条，应为 %d' % (r['nbn'], len(PAIRS))) + gotp = dict(r['planeAssigned']) + missp = [n for n in PLANE_NETS if gotp.get(n) != PLANE_RULE] + chk(not missp, u'铺铜全连接 %d 个网络' % len(PLANE_NETS), u'没指派上: %s' % missp) + print(u' ' + (u'[OK] 全部通过' if not bad else u'[X] %d 条不过' % len(bad))) + return bad + + +if __name__ == '__main__': + print(u'底板 PCB=%s（%d 层）' % (PCB, LAYERS)) + if '--dump' in sys.argv: + dump_nets() + if '--push' in sys.argv: + push() + audit() + elif '--audit' in sys.argv: + audit() + elif '--dump' not in sys.argv: + check_names() + print(u'线宽规则:') + for k, v in sorted(TRACK_RULES.items()): + print(u' %-8s 默认 %.2f 最小 %.2f 最大 %.2f' + % (k, v['strokeWidthDefault'], v['strokeWidthMin'], v['strokeWidthMax'])) + print(u'网络指派:') + for k, v in sorted(NET_TRACK.items()): + print(u' %-12s → %s' % (k, v)) + print(u'差分对 %d：%s' % (len(PAIRS), ' '.join(p[0] for p in PAIRS))) + print(u'安全间距 %.2f；铺铜全连接 %s' % (MIN_CLEARANCE, ' '.join(PLANE_NETS))) diff --git a/.claude/r2/b1_power.py b/.claude/r2/b1_power.py new file mode 100644 index 0000000..78d60c7 --- /dev/null +++ b/.claude/r2/b1_power.py @@ -0,0 +1,403 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 **B1-POWER** 页：12V 入口保护 → Buck → eFuse → 检流 → `VO_P`。 + + /c/Python314/python .claude/r2/b1_power.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/b1_power.py --push # 清页 + 重画（幂等） + +## 版图从哪来 + +**不是重新排的** —— 直接搬 R1 已经验证过六项的 `P2-CHANNEL` +（`.claude/r2/dump_page.py` 读回的 `_p2_live.json`：40 元件 / 213 段导线 / +29 旗 / 12 端口），只做三件事： + +1. **位号映射**（`DES`）：`C1xx→Cx` / `R1xx→Rx` / `Rs101→Rs1` / `L101→L1` / + `Q101→Q1` / `Q102→Q2`；芯片按 R2 刀片的编号 `U1` Buck / **`U8→U3`** INA226 / + **`U14→U2`** eFuse。刀片只有一路，不再需要「通道号 = 位号百位」那套规则。 +2. **网络名去掉通道后缀**（`NET`）：`VO1→VO`、`VDAC1→VDAC`、`EFUSE_EN1→EFUSE_EN` … + `GND` / `+3V3` / `BUCK_PG` / `INA_ALERT` / `SDA` / `SCL` 原样。 +3. **新增 12V 入口保护块**（方案文档 D10）：`+12V`(金手指) → `F1` 2A 慢断 → + `+12V_F`（刀片内部 12V 轨）→ Buck；`D1` TVS 从 `+12V_F` 钳到地。 + 原来那两个 `+12V` 电源旗因此改叫 `+12V_F`。 + +## ⚠️ 跨工程重放必须断言引脚坐标 + +skill §6b/§6c/§8d：`create()` 的 rotation 语义**同一个料号在不同页都能不一样**， +方向表一张都别信。所以放完之后逐个元件把 `getAllPins()` 读回来， +和 `_p2_live.json` 里 R1 的引脚坐标**逐脚比对**，差一个单位就终止 —— +坐标一致才能保证照搬过来的 213 段导线还落在引脚上。 + +## ✅ T7 已结（2026-09-08）：F1 = `F1206SB2000V063TM`（`C310998`） + +原来这里写「库里搜不到 2A 的 1206 保险丝，`lib_Device.search` 只回 38 条」—— +**那个结论是错的**：`search` 的完整签名是 +`search(key, libraryUuid, classification, symbolType, itemsOfPage, page)`， +**带上 `itemsOfPage` / `page` 就能翻页**（单次请求仍受桥接 30 s 限制，一个关键词最多翻 3 页）。 +翻页之后 AEM 的 `F1206` 全系都在库里，型号规则是 `F1206` + 系列 + 电流 + `V` + 耐压 + `TM`： + +| 系列 | 含义 | 2A 那一颗 | +|---|---|---| +| **`SB`** | **Slow Blow（慢断）** | **`F1206SB2000V063TM` = `C310998`，63V / 分断 50A / I²t 0.63** ✅ 本页用它 | +| `HI` | High Inrush（耐涌，也是延时型）| `F1206HI2000V063TM` = `C246768`，I²t 0.8 | +| `FA` | Fast Acting（快断）| —— D10 要慢断，不能用 | +| `HC` | High Current | 占位用过的 10A（`C310989`）、底板 F1 的 12A（`C310990`）就是这一系 | + +⚠ **封装 uuid 和占位件不一样**（`bceff889…` vs `66116fae…`，10A/150A 分断那颗焊盘更大）。 +刀片 PCB 还没布（M4），所以没有影响；原理图这一侧的导线本来就是**按读回的引脚坐标**算的，自动跟随。 + +⚠ **裕量只有一档**：刀片满载约 1.45 A（16 W 手机 ÷ 92% ÷ 12 V）= 额定的 73%， +正压在保险丝「连续 ≤ 75%」的降额线上，机箱内 40~50 ℃ 还要再降。 +要更大裕量就换 `F1206SB2500V032TM`（`C310999`，2.5A / 32V / I²t 0.9）—— 改 `FUSE` 一个常量即可。 +""" +import io +import json +import os +import sys +import time + +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +PAGE = '5338949298dcff35' # BLADE / B1-POWER +PAGE_NAME = 'B1-POWER' +PROJ = '05a65c22f14846b8b95360ef8d3c1e2e' +SRC = os.path.join(HERE, '_p2_live.json') +PARTS = json.load(io.open(os.path.join(os.path.dirname(HERE), 'eda-parts.json'), + encoding='utf-8'))['parts'] + +# ── 1. 位号映射 ─────────────────────────────────────────────────────── +CHIP = {'U1': 'U1', 'U8': 'U3', 'U14': 'U2'} + + +def des(d): + if d in CHIP: + return CHIP[d] + pre = 'Rs' if d.startswith('Rs') else d[0] + num = d[len(pre):] + assert num.isdigit() and len(num) == 3 and num[0] == '1', d + return '%s%d' % (pre, int(num[1:])) + + +# ── 2. 网络名映射 ───────────────────────────────────────────────────── +NET = { + 'VO1': 'VO', 'VO1_P': 'VO_P', 'VDAC1': 'VDAC', + 'EFUSE_EN1': 'EFUSE_EN', 'EFUSE_FLT1': 'EFUSE_FLT', 'EFUSE_PG1': 'EFUSE_PG', + '+12V': '+12V_F', # Buck 侧吃的是保险丝之后那一段 +} + +# ── 3. 新增：12V 入口保护块 ─────────────────────────────────────────── +# 位置选在 y 200~340 / x 480~960 那片空地（R1 页上唯一一块连片的空区， +# 标题栏占 x>455 且 y<192，所以主线放 y=250、TVS 朝上挂）。 +F1_XY = (580, 250) +D1_XY = (680, 290) +IN_PORT = (520, 250) # '+12V' 端口引脚 +NODE_X = 680 # +12V_F 节点的竖线 x +FLAG_X = 760 # +12V_F 电源旗 +GND_Y = 335 # TVS 上方的地旗（rot 180：符号在上、引脚在下） + +FUSE = 'C310998' # F1206SB2000V063TM：2A 慢断（AEM SB 系列），1206/63V，T7 已结 +TVS = 'C163651' # SMBJ13A + + +def lcsc_of(name): + u"""器件名 -> 立创编号。R1 页上的名字带 `_C8545` 这种后缀，去掉再比。""" + base = name.split('_C')[0] if '_C' in name else name + for k, v in PARTS.items(): + if v['name'] == name or v['name'] == base: + return k + raise SystemExit(u'eda-parts.json 里找不到器件 %r' % name) + + +def plan(): + src = json.load(io.open(SRC, encoding='utf-8')) + pts = src['wires'] + segs = [(tuple(pts[i]), tuple(pts[i + 1])) for i in range(0, len(pts), 2)] + + place, want_pins = [], {} + for p in src['parts']: + d0, name, _sub, x, y, rot, mir = p[0], p[1], p[2], p[3], p[4], p[5], p[6] + k = lcsc_of(name) + d = des(d0) + place.append([d, PARTS[k]['uuid'], x, y, rot, PARTS[k]['lib'], bool(mir)]) + want_pins[d] = {str(q[0]): (q[2], q[3]) for q in p[9]} + + # 新增两件 + place.append(['F1', PARTS[FUSE]['uuid'], F1_XY[0], F1_XY[1], 0, PARTS[FUSE]['lib'], False]) + # ⚠ create(90) 实测让 pin1(K) 落在上方 —— TVS 的 K 要朝下接 +12V_F，所以用 270。 + # （entry_block() 里有硬断言，方向反了直接终止，见 skill §6c） + place.append(['D1', PARTS[TVS]['uuid'], D1_XY[0], D1_XY[1], 270, PARTS[TVS]['lib'], False]) + + W = [[int(round(a[0])), int(round(a[1])), int(round(b[0])), int(round(b[1]))] + for a, b in segs] + # 旗的符号名读回来是 'Ground-GND' / 'Power-5V'，而 createNetFlag 的第一个参数 + # 只认 'Ground' / 'Power' —— 取前缀。（'Power-5V' 里的 5V 只是符号默认网络名， + # 见 skill §3b：移动电源旗会掉回这个默认值。） + # ⚠️ rot=180 的旗/端口读回来带浮点尾巴（789.9999999999999），必须先取整 —— + # 否则「坐标必须是 5 的倍数」和「必须落在导线端点」两道自检全部误报。 + F = [[f[0].split('-')[0], NET.get(f[1], f[1]), int(round(f[2])), int(round(f[3])), f[4]] + for f in src['flags']] + PT = [[p[0].replace('Netport-', ''), NET.get(p[1], p[1]), int(round(p[2])), int(round(p[3])), p[4]] + for p in src['ports']] + return place, want_pins, W, F, PT + + +def entry_block(pins, pnames): + u"""按读回的真实引脚坐标补出入口保护块的导线 / 旗 / 端口。""" + f = pins['F1'] + assert len(f) == 2, u'F1 应该是 2 脚，实测 %s' % (f,) + (fa, fb) = sorted(f.values()) # 左脚、右脚 + assert fa[1] == fb[1] == F1_XY[1], u'F1 两脚必须同 y（横放），实测 %s' % (f,) + + d = pins['D1'] + assert sorted(d) == ['1', '2'], u'D1 应该是 2 脚，实测 %s' % (d,) + assert d['1'][0] == d['2'][0] == D1_XY[0], u'D1 两脚必须同 x（竖放），实测 %s' % (d,) + # ⚠️ 极性件按**脚名**认，不按脚号（skill §6c：方向表一张都别信）。 + # SMBJ13A 实测脚名是 'C'(阴极) / 'A'(阳极)，阴极要朝下接 +12V_F。 + nm = pnames['D1'] + kk = [n for n in d if nm.get(n, '').startswith(('C', 'K'))] + aa = [n for n in d if nm.get(n, '').startswith('A')] + assert len(kk) == 1 and len(aa) == 1, u'D1 脚名认不出阴阳极：%s' % (nm,) + dk, da = d[kk[0]], d[aa[0]] + assert dk[1] < da[1], \ + u'D1 是 TVS，阴极必须在下（接 +12V_F），实测 K=%s A=%s ⇒ 把 rot 翻 180 重放' % (dk, da) + + W = [ + [IN_PORT[0], IN_PORT[1], fa[0], fa[1]], # 端口 → F1 左脚 + [fb[0], fb[1], NODE_X, F1_XY[1]], # F1 右脚 → 节点 + [NODE_X, F1_XY[1], FLAG_X, F1_XY[1]], # 节点 → +12V_F 旗 + [NODE_X, F1_XY[1], dk[0], dk[1]], # 节点 → D1 阴极 + [da[0], da[1], NODE_X, GND_Y], # D1 阳极 → 地旗 + ] + F = [['Power', '+12V_F', FLAG_X, F1_XY[1], 0], + ['Ground', 'GND', NODE_X, GND_Y, 180]] + PT = [['IN', '+12V', IN_PORT[0], IN_PORT[1], 0]] + return W, F, PT + + +TEXTS = [ + (185, 785, u'B1-POWER 刀片功率级：12V 入口保护 → Buck → eFuse → 检流 → VO_P（5 片刀片完全相同）', 16), + (480, 212, u'【12V 入口保护 · 方案 R2 §D10】金手指 +12V → F1 2A 慢断 → +12V_F 刀片内部轨；D1 TVS 钳位', 11), + (60, 170, u'TPS54622: Vref 0.6V, fsw 480kHz(R3=100k), Vout = 4.222 - 0.2813*Vd', 11), + (60, 150, u'TPS25940A: OVP 4.36V(R9/R10), ILIM 4.45A(R11), dVdT 33nF -> 0.36V/ms', 11), + (60, 130, u'缓启动 11.5ms / 涌流 0.8A ; INA226 五片刀片同址 A1=A0=GND -> 0x40（靠底板 TCA9548A 分通道）', 11), + (60, 110, u'放电互锁: EFUSE_EN 低 -> Q1 截止 -> Q2 导通 -> R19 10R 泄放手机侧 2200uF', 11), + (60, 90, u'✅ T7 已结：F1 = F1206SB2000V063TM (C310998) 2A 慢断 1206/63V；满载 1.45A = 额定 73%，裕量只有一档', 11), + (60, 70, u'⚠ EFUSE_EN 走金手指专用针直连底板 ESP32 GPIO，不经 PCA9555（安全链第三层）', 11), +] + + +def selfcheck(W, F, PT, pins): + bad = [] + for a, b, c, e in W: + if (a == c) == (b == e): + bad.append(u'导线不是横平竖直或零长度: %s' % ((a, b, c, e),)) + for v in (a, b, c, e): + if v % 5: + bad.append(u'导线坐标不是 5 的倍数: %s' % ((a, b, c, e),)) + for it in F + PT: + if it[2] % 5 or it[3] % 5: + bad.append(u'旗/端口坐标不是 5 的倍数: %s' % (it,)) + # 旗 / 端口的引脚必须落在某条导线段的**端点**（skill §8a-2） + ends = set() + for a, b, c, e in W: + ends.add((a, b)); ends.add((c, e)) + for it in F + PT: + if (it[2], it[3]) not in ends: + bad.append(u'旗/端口不在导线端点上: %s' % (it,)) + # 每个元件引脚必须落在某条导线段上 + def on(p, s): + (px, py), (ax, ay, bx, by) = p, s + if ax == bx: + return px == ax and min(ay, by) <= py <= max(ay, by) + return py == ay and min(ax, bx) <= px <= max(ax, bx) + for d, ps in sorted(pins.items()): + for n, xy in sorted(ps.items()): + if not any(on(xy, s) for s in W): + bad.append(u'悬空引脚 %s.%s @%s' % (d, n, (xy,))) + return bad + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise SystemExit(json.dumps(r, ensure_ascii=False)[:600]) + return r['result'] + + +READ_PINS_JS = """ +const out = {}; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + if (c.getState_ComponentType() !== 'part') continue; + out[c.getState_Designator()] = (await c.getAllPins()).map( + p => [p.getState_PinNumber(), (p.getState_PinName ? p.getState_PinName() : ''), + Math.round(p.getState_X()), Math.round(p.getState_Y())]); +} +return out; +""" + +FLIP_JS = """ +const P = %s; +const by = {}; +for (const c of await eda.sch_PrimitiveComponent.getAll()) + if (c.getState_ComponentType() === 'part') by[c.getState_Designator()] = c; +for (const [d, x, y, r] of P) { + const c = by[d]; if (!c) continue; + await c.toAsync().setState_Rotation(r).done(); + await c.toAsync().setState_X(x).setState_Y(y).done(); +} +return P.length; +""" + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,1800));" + "const cur=await eda.dmt_Schematic.getCurrentSchematicPageInfo();" + "if(!cur||cur.name!=='%s') throw new Error('打错页了: '+(cur&&cur.name));" + % (PAGE, PAGE_NAME)) + + +def main(): + push = '--push' in sys.argv + place, want, W0, F0, PT0 = plan() + + if not push: + print(u'元件 %d（含新增 F1/D1） 导线 %d 旗 %d 端口 %d 文字 %d' + % (len(place), len(W0) + 5, len(F0) + 2, len(PT0) + 1, len(TEXTS))) + nets = sorted({f[1] for f in F0} | {p[1] for p in PT0} | {'+12V', '+12V_F'}) + print(u'网络名: ' + ' '.join(nets)) + print(u'位号: ' + ' '.join(p[0] for p in place)) + print(u'（只算不下发。要下发加 --push）') + return + + call("await eda.dmt_Project.openProject('%s');" + "await new Promise(r=>setTimeout(r,2500)); return 1;" % PROJ) + + # 清页（幂等） + call(OPEN + """ + for (const c of await eda.sch_PrimitiveComponent.getAll()) + await eda.sch_PrimitiveComponent.delete(c.getState_PrimitiveId()); + for (const w of await eda.sch_PrimitiveWire.getAll()) + await eda.sch_PrimitiveWire.delete(w.getState_PrimitiveId()); + for (const t of await eda.sch_PrimitiveText.getAll()) + await eda.sch_PrimitiveText.delete(t.getState_PrimitiveId()); + return 1; + """) + + for it in place: + assert len(it) == 7 and it[1] and it[5], u'放置表字段不全: %s' % (it,) + + call(OPEN + """ +globalThis.__pl = {done: 0, err: null, n: %d}; +(async () => { + for (const [d, uuid, x, y, rot, lib, mir] of %s) { + try { await eda.sch_PrimitiveComponent.create({libraryUuid: lib, uuid}, x, y, undefined, rot, mir, true, true); } + catch (e) { globalThis.__pl.err = d + ': ' + String(e).slice(0, 150); } + globalThis.__pl.done++; + } +})(); +return 'fired'; +""" % (len(place), json.dumps(place))) + for _ in range(120): + st = call("return globalThis.__pl;") + if st['err']: + raise SystemExit(u'放置失败: %s' % st['err']) + if st['done'] >= st['n']: + break + time.sleep(2) + else: + raise SystemExit(u'放置超时 %d/%d' % (st['done'], st['n'])) + + # ⚠️ `create()` 会把元件坐标吸附（实测吸到 5 的倍数）—— + # R1 页上 679/639/654/589 这些位置放下去会差 1~2 个单位，而整页 213 段导线 + # 是按 R1 的坐标算的，差 1 就全断。skill §3 只说了旗/端口会吸附，元件也会。 + # ⇒ 认领位号按**就近**匹配（容差 3），认完再 setState_X/Y 拉回精确坐标。 + # （移动元件是安全的；不安全的是移动旗/端口 §3b、和 setState_Rotation §6b。） + named = call(""" +const P = %s; +let k = 0, moved = 0; +const cs = (await eda.sch_PrimitiveComponent.getAll()).filter(c => c.getState_ComponentType() === 'part'); +const used = new Set(); +for (const [d, x, y] of P) { + let best = null, bd = 4; + for (const c of cs) { + const id = c.getState_PrimitiveId(); + if (used.has(id)) continue; + const dd = Math.abs(Math.round(c.getState_X()) - x) + Math.abs(Math.round(c.getState_Y()) - y); + if (dd < bd) { bd = dd; best = c; } + } + if (!best) continue; + used.add(best.getState_PrimitiveId()); + await best.toAsync().setState_Designator(d).done(); + if (bd > 0) { await best.toAsync().setState_X(x).setState_Y(y).done(); moved++; } + k++; +} +return k; +""" % json.dumps([[p[0], p[2], p[3]] for p in place])) + if named != len(place): + raise SystemExit(u'只认领到 %d/%d 个位号' % (named, len(place))) + + raw = call(READ_PINS_JS) + pins = {k: {str(n): (x, y) for n, _nm, x, y in v} for k, v in raw.items()} + pnames = {k: {str(n): (_nm or '').upper() for n, _nm, x, y in v} for k, v in raw.items()} + + # ⚠️ 与 R1 逐脚比对（§6b/§6c：rotation 语义不可推，只能读回来断言） + # 实测这一页 42 件里有 27 件的 rot=270 与 R1 语义相反： + # · 25 件是两脚对称件（0402 R/C），只有引脚**编号**互换，坐标集相同； + # · **C10 / C14 两颗 33nF 是 +20/−15 的不对称跨距**，翻过来坐标真的差 5， + # 照 R1 的坐标画线会**断在那两颗上** —— 正是 skill §8d 那条「跨距同族也不统一」。 + # ⇒ 对不上就 setState_Rotation(rot+180) 再回读，直到逐脚（含编号）与 R1 一致。 + tgt = {q[0]: [q[2], q[3], q[4]] for q in place} + for _round in range(4): + miss = [d for d, wp in want.items() + if pins.get(d) != {n: tuple(xy) for n, xy in wp.items()}] + if not miss: + break + flip = [] + for d in sorted(miss): + tgt[d][2] = (tgt[d][2] + 180) % 360 + flip.append([d, tgt[d][0], tgt[d][1], tgt[d][2]]) + # ⚠️ 第一轮往往「看起来没生效」：create(270) 与 setState_Rotation(270) + # 差 180°（skill §6b），所以要翻两次才落到 R1 的语义上。别以为卡住了。 + print(u' 翻转 %d 件重试：%s' % (len(flip), ' '.join(f[0] for f in flip))) + call(FLIP_JS % json.dumps(flip)) + raw = call(READ_PINS_JS) + pins = {k: {str(n): (x, y) for n, _nm, x, y in v} for k, v in raw.items()} + pnames = {k: {str(n): (_nm or '').upper() for n, _nm, x, y in v} for k, v in raw.items()} + + bad = [] + for d, wp in sorted(want.items()): + got = pins.get(d) + if not got: + bad.append(u'%s 没放上' % d); continue + for n, xy in sorted(wp.items()): + if got.get(n) != tuple(xy): + bad.append(u'%s.%s 期望 %s 实测 %s' % (d, n, tuple(xy), got.get(n))) + if bad: + raise SystemExit(u'引脚坐标与 R1 对不上（%d 处）：\n ' % len(bad) + '\n '.join(bad[:20])) + + W1, F1_, PT1 = entry_block(pins, pnames) + W, F, PT = W0 + W1, F0 + F1_, PT0 + PT1 + + err = selfcheck(W, F, PT, pins) + if err: + raise SystemExit(u'本地自检失败（%d 条）：\n ' % len(err) + '\n '.join(err[:25])) + + def batch(items, size, js): + for i in range(0, len(items), size): + call(OPEN + js % json.dumps(items[i:i + size], ensure_ascii=False)) + + batch(W, 40, "for (const s of %s) await eda.sch_PrimitiveWire.create(s); return 1;") + batch(PT, 25, "for (const p of %s) await eda.sch_PrimitiveComponent.createNetPort(p[0],p[1],p[2],p[3],p[4],false); return 1;") + batch(F, 25, "for (const f of %s) await eda.sch_PrimitiveComponent.createNetFlag(f[0],f[1],f[2],f[3],f[4],false); return 1;") + batch([list(t) for t in TEXTS], 15, + "for (const t of %s) await eda.sch_PrimitiveText.create(t[0],t[1],t[2],0,null,null,t[3],false,false,false,0); return 1;") + print(u'%s: 元件 %d 导线 %d 旗 %d 端口 %d 文字 %d' + % (PAGE_NAME, len(place), len(W), len(F), len(PT), len(TEXTS))) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/b2-nc.json b/.claude/r2/b2-nc.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/.claude/r2/b2-nc.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/.claude/r2/b2_ctrl.py b/.claude/r2/b2_ctrl.py new file mode 100644 index 0000000..9f8fd31 --- /dev/null +++ b/.claude/r2/b2_ctrl.py @@ -0,0 +1,444 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 **B2-CTRL** 页：PCA9555 + 侧键 MOS ×3 + 本槽 I²C 上拉。 + + /c/Python314/python .claude/r2/b2_ctrl.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/b2_ctrl.py --push # 清页 + 重画（幂等） + +## 这一页画什么 + +| 位号 | 器件 | 作用 | +|---|---|---| +| `U4` | PCA9555PW（0x20）| 3 个侧键 + `EDL_EN` + `VBUS_EN` 输出；4 路状态输入 | +| `Q3/Q4/Q5` | 2N7002 | 侧键低边 MOS（R1 §13.3 原样：1k 串阻 + 100k 栅极下拉）| +| `R40/R41` | 4.7k | 本槽 mux 分支的 I²C 上拉（每片刀片各自一套）| +| `R42~R47` | 1k ×3 + 100k ×3 | 三个栅极的串阻与下拉 | +| `C40` | 100nF | PCA9555 去耦 | + +## ⚠️ 2026-09-08 改：**DAC 挪到底板**（推翻 D11 的「一片刀片一颗」） + +原来这一页还有 `U4 DAC63204`（只用 CH0）。用户拍板改成**底板 2 颗 DAC63204 喂 5 路** +—— 就是 R1 的 U6/U7 那套原样搬，固件 A4 驱动、NVM 预置 0.548V、 +§4.5 的三条外围硬要求、通道映射表全部现成，不引入任何新料。 + +**为什么敢让 `VDAC` 跨连接器**（设计文档 §4.4 的失效表已经算过）： + +| 故障 | Vd | Vout | +|---|---|---| +| 金手指断了 / 空槽 | 悬空 | **3.890 V** ✅ 正好是目标值 | +| 对地短路 | 0 V | 4.010 V ✅ | +| 短到 +3V3 | 3.3 V | 3.35 V ✅ 安全侧（手机关机）| + +注入增益只有 **0.2007**，线上噪声和两板之间的地差到输出都**衰减 5 倍**； +而 §4.5 要求的 `R8 1k + C12 10nF` 低通留在刀片上（Rinj 的 DAC 侧）， +正好把长线拾到的东西全滤掉 —— **B1-POWER 一个字节不用改**。 + +⇒ 位号顺移：PCA9555 从 `U5` 变 **`U4`**，B3-PHONE 的 TPS22918 / TS5A3157 + 相应变成 `U5` / `U6`（方案 §7.2b 已同步）。 + +## 本页不放的四样（别在这里找） + +- **DAC** -> 底板 `A3-CTRL`（2 × DAC63204，0x4A / 0x4B） +- `EDL_EN` / `VBUS_EN` 的 100k 下拉 -> **B3-PHONE**（贴各自的负载，R1 R741/R701 就在那边） +- `INT#` 的上拉 -> **底板 A3-CTRL**（五槽 wire-OR 共用一颗 10k，刀片上放会并成 2k） +- `EFUSE_EN` -> **不经 PCA9555**，走金手指专用针直连底板 ESP32（方案 §7.3 的框） + +## 几何约定 + +skill §6b/§6c：`create()` 的 rotation 语义同一个料号在不同页都可能相反， +所以放完逐个 `getAllPins()` 读回、和 `EXPECT` 比对，对不上就翻 180 重试（最多 3 轮）。 +两脚件按**坐标集合**比（非极性件翻转只换脚号，无害）。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +PAGE = '4f458d678c50f7a4' # BLADE / B2-CTRL +PAGE_NAME = 'B2-CTRL' +PARTS = json.load(io.open(os.path.join(os.path.dirname(HERE), 'eda-parts.json'), + encoding='utf-8'))['parts'] + +PCA, MOS = 'C2688893', 'C8545' +R4K7, R1K, R100K, C100N = 'C25900', 'C11702', 'C25741', 'C1525' + +U4 = (420, 640) # PCA9555，rot 0：输出在左、输入与 I²C 在右 +PU = [(700, 'SDA'), (770, 'SCL')] # 两颗 4.7k 上拉的 x +BX = [250, 550, 850] # 三路侧键 MOS 的中心 x +KEYS = ['PWR', 'VUP', 'VDN'] + +# ── 引脚期望（相对中心的偏移，来自 R1 P3B-EXPAND / C4-SITE1 实测）────────── +PCA_REL = dict([(str(i + 1), (-50, 55 - 10 * i)) for i in range(12)] + + [(str(13 + i), (50, -55 + 10 * i)) for i in range(12)]) +MOS_REL = {'1': (-20, 0), '2': (10, -20), '3': (10, 20)} # G / S / D + +NC = {} # 本页没有有意不接的脚 + +ALLOW_SPLIT = set(['GND', '+3V3', 'SDA', 'SCL'] + + ['KEY_' + k for k in KEYS]) # 靠端口连起来的 + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:900]) + return r['result'] + + +def plan(): + W, F, PT = [], [], [] + + def w(net, *pts): + for a, b in zip(pts, pts[1:]): + if a != b: + W.append((a, b, net)) + + def gnd(x, y, rot): + F.append(['Ground', 'GND', x, y, rot]) + + def pwr(x, y, rot): + F.append(['Power', '+3V3', x, y, rot]) + + def port(d, net, x, y, rot): + PT.append([d, net, x, y, rot]) + + # ── I²C 上拉（本槽 mux 分支各自一套；INA226 在 B1-POWER，也吃这两颗）── + for x, net in PU: + w(net, (x, 700), (x, 675)) + port('BI', net, x, 675, 0) + w('+3V3', (x, 740), (x, 765)) + pwr(x, 765, 0) + + # ── U4 PCA9555 ─────────────────────────────────────────────────────── + px, py = U4 + PL, PR = px - 50, px + 50 + + w('INT#', (PL, py + 55), (330, py + 55), (330, 745)) # 1 INT# + port('OUT', 'INT#', 330, 745, 0) + w('GND', (PL, py + 45), (300, py + 45)) # 2 A1 + w('GND', (PL, py + 35), (300, py + 35)) # 3 A2 + w('GND', (300, py + 35), (300, 725)) + gnd(300, 725, 180) + OUTS = [('KEY_PWR', 25), ('KEY_VUP', 15), ('KEY_VDN', 5), + ('EDL_EN', -5), ('VBUS_EN', -15)] # IO0_0 ~ IO0_4 + for net, dy in OUTS: + w(net, (PL, py + dy), (300, py + dy)) + port('OUT', net, 300, py + dy, 180) + for dy in (-25, -35, -45, -55): # IO0_5~7 + VSS + w('GND', (PL, py + dy), (320, py + dy)) + w('GND', (320, py - 25), (320, 555)) + gnd(320, 555, 0) + + INS = [('EFUSE_FLT', -55), ('BUCK_PG', -45), + ('INA_ALERT', -35), ('EFUSE_PG', -25)] # IO1_0 ~ IO1_3 + for net, dy in INS: + w(net, (PR, py + dy), (510, py + dy)) + port('IN', net, 510, py + dy, 180) + for dy in (-15, -5, 5, 15, 25): # IO1_4~7 + A0 + w('GND', (PR, py + dy), (570, py + dy)) + w('GND', (570, py - 15), (570, 720)) + gnd(570, 720, 180) + w('SCL', (PR, py + 35), (490, py + 35)) + port('BI', 'SCL', 490, py + 35, 0) + w('SDA', (PR, py + 45), (490, py + 45)) + port('BI', 'SDA', 490, py + 45, 0) + w('+3V3', (PR, py + 55), (520, py + 55)) # 24 VDD -> C40 下脚 + w('+3V3', (490, py + 55), (490, 730)) + pwr(490, 730, 0) + w('GND', (520, 735), (520, 760)) + gnd(520, 760, 180) + + # ── 侧键 MOS ×3（R1 §13.3：栅极 1k 串阻 + 100k 下拉，源极接地）──────── + for k, bx in enumerate(BX): + g, kg = 'KEY_' + KEYS[k], 'KG_' + KEYS[k] + w(kg, (bx - 20, 400), (bx - 60, 400)) # 栅极 + w(kg, (bx - 60, 420), (bx - 60, 400)) # 1k 下脚 + w(kg, (bx - 60, 380), (bx - 60, 400)) # 100k 上脚 + w(g, (bx - 60, 460), (bx - 60, 500)) # 1k 上脚 -> 端口 + port('IN', g, bx - 60, 500, 0) + w('GND', (bx - 60, 340), (bx - 60, 315)) + gnd(bx - 60, 315, 0) + w('GND', (bx + 10, 380), (bx + 10, 340)) # 源极 + gnd(bx + 10, 340, 0) + w('KPAD_' + KEYS[k], (bx + 10, 420), (bx + 10, 465)) # 漏极 -> 中框焊盘 + port('OUT', 'KPAD_' + KEYS[k], bx + 10, 465, 0) + + TX = [ + (45, 790, u'【B2-CTRL】刀片控制页：PCA9555 + 侧键 MOS ×3（DAC 已挪到底板）', 14), + (45, 275, u'U4 PCA9555（A0/A1/A2 全接地 ⇒ 0x20）：P0.0~P0.2 三个侧键 / P0.3 EDL_EN / ' + u'P0.4 VBUS_EN 为输出；P1.0~P1.3 收 EFUSE_FLT / BUCK_PG / INA_ALERT / EFUSE_PG。', 10), + (45, 257, u'⚠ 备用脚 P0.5~P0.7 / P1.4~P1.7 直接接地：固件严禁把它们配成输出，' + u'否则输出高电平直接对地短路（R1 §17.2 同款约束）。', 10), + (45, 239, u'⚠ 复位安全（D9）：PCA9555 上电为高阻输入 + 栅极 100k 下拉 ⇒ ' + u'三个侧键必然松开、VBUS 必然断开，不依赖任何软件动作。', 10), + (45, 221, u'2026-09-08 改：DAC63204 挪到底板（2 颗喂 5 路，沿用 R1 的 U6/U7 与通道映射表）。' + u'VDAC 从金手指进来，直接去 B1-POWER 的 R8/C12 低通 + Rinj。', 10), + (45, 203, u'⚠ VDAC 跨连接器是安全的（设计文档 §4.4）：断线 = Rinj 悬空 = 3.890V；对地短路 = 4.010V。' + u'注入增益 0.2007，线上噪声与两板地差到输出衰减 5 倍。', 10), + (45, 185, u'⚠ EDL_EN / VBUS_EN 的 100k 下拉在 B3-PHONE；INT# 的上拉在底板（五槽 wire-OR）。', 10), + (45, 167, u'⚠ EFUSE_EN 不经 PCA9555，直连底板 ESP32（方案 §7.3）。', 10), + (45, 149, u'4.7k I²C 上拉每片刀片自带；INA226 仍在 B1-POWER。', 10), + ] + + # 文字越界自检（skill §12 的宽度经验值 + §8c 的标题栏范围）—— + # 这一条几何验证抓不到：文字压在标题栏上，六项检查全过，只有截图看得见。 + for x, y, s, size in TX: + cjk = sum(1 for ch in s if ord(ch) > 0x2E7F) + right = x + size * (cjk + 0.5 * (len(s) - cjk)) + limit = 455 if y < 192 else 1145 + assert right <= limit, u'文字右边界 %.0f 越过 %d（y=%d）: %s' % (right, limit, y, s[:24]) + + # ── 下发前的几何断言（skill §3 / §6d / §8a-2b）──────────────────────── + for a, b, net in W: + assert (a[0] == b[0]) != (a[1] == b[1]), u'%s 段不是横平竖直: %s->%s' % (net, a, b) + for v in (a[0], a[1], b[0], b[1]): + assert v % 5 == 0, u'%s 坐标 %d 不是 5 的倍数' % (net, v) + for it in F + PT: + assert it[2] % 5 == 0 and it[3] % 5 == 0, u'旗/端口 %s 坐标不是 5 的倍数' % (it[1],) + assert 20 <= it[2] <= 1145 and 10 <= it[3] <= 812, u'旗/端口 %s 出框' % (it[1],) + return W, F, PT, TX + + +# ── 本地几何自检（skill §10b）───────────────────────────────────────────── +def _on(p, a, b): + if a[0] == b[0]: + return p[0] == a[0] and min(a[1], b[1]) <= p[1] <= max(a[1], b[1]) + return p[1] == a[1] and min(a[0], b[0]) <= p[0] <= max(a[0], b[0]) + + +def netcheck(W, F, PT, pins): + errs = [] + n = len(W) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2, _ = W[i] + b1, b2, _ = W[j] + if _on(a1, b1, b2) or _on(a2, b1, b2) or _on(b1, a1, a2) or _on(b2, a1, a2): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + grp = defaultdict(list) + for i in range(n): + grp[find(i)].append(i) + pieces = defaultdict(int) + for root, idx in grp.items(): + names = sorted(set(W[i][2] for i in idx)) + if len(names) > 1: + errs.append(u'短路: ' + ' + '.join(names) + u' :: ' + + ' | '.join('%s%s-%s' % (W[i][2], W[i][0], W[i][1]) for i in idx[:6])) + pieces[names[0]] += 1 + for name, cnt in sorted(pieces.items()): + if cnt > 1 and name not in ALLOW_SPLIT: + errs.append(u'网络 %s 被拆成 %d 块（漏连）' % (name, cnt)) + + for d, pd in pins.items(): + for num, xy in pd.items(): + if num in NC.get(d, []): + continue + if not any(_on(tuple(xy), s[0], s[1]) for s in W): + errs.append(u'悬空引脚: %s.%s @ %s' % (d, num, tuple(xy))) + + # 旗/端口：必须落在导线**端点**，且不能是合并后母线的中段（skill §8a-2 / §8a-3） + for kind, lst in ((u'旗', F), (u'端口', PT)): + for it in lst: + p = (it[2], it[3]) + through = any((s[0][0] == s[1][0] and p[0] == s[0][0] + and min(s[0][1], s[1][1]) < p[1] < max(s[0][1], s[1][1])) + or (s[0][1] == s[1][1] and p[1] == s[0][1] + and min(s[0][0], s[1][0]) < p[0] < max(s[0][0], s[1][0])) + for s in W) + ends = [s for s in W if s[0] == p or s[1] == p] + if through: + errs.append(u'%s %s @ %s 压在导线中段' % (kind, it[1], p)) + elif not ends: + errs.append(u'%s %s @ %s 不在任何导线端点上' % (kind, it[1], p)) + else: + ax = set(('V' if s[0][0] == s[1][0] else 'H') for s in ends) + if len(ends) > 1 and len(ax) == 1: + errs.append(u'%s %s @ %s 两段共线，合并后会变成中段' % (kind, it[1], p)) + return errs + + +def crossings(W): + out = [] + for i in range(len(W)): + for j in range(i + 1, len(W)): + a1, a2, na = W[i] + b1, b2, nb = W[j] + if na == nb: + continue + ha, hb = a1[1] == a2[1], b1[1] == b2[1] + if ha == hb: + continue + h, v = ((a1, a2), (b1, b2)) if ha else ((b1, b2), (a1, a2)) + y, x = h[0][1], v[0][0] + if (min(h[0][0], h[1][0]) < x < max(h[0][0], h[1][0]) + and min(v[0][1], v[1][1]) < y < max(v[0][1], v[1][1])): + out.append((na, nb, x, y)) + return out + + +def placement(): + px, py = U4 + out = [['U4', PCA, px, py, 0], ['C40', C100N, 520, 715, 270], + ['R40', R4K7, PU[0][0], 720, 270], ['R41', R4K7, PU[1][0], 720, 270]] + for k, bx in enumerate(BX): + out += [['Q%d' % (k + 3), MOS, bx, 400, 0], + ['R%d' % (42 + 2 * k), R1K, bx - 60, 440, 270], + ['R%d' % (43 + 2 * k), R100K, bx - 60, 360, 270]] + return out + + +def expect(place): + u"""期望引脚坐标。IC 逐脚；两脚件只比坐标集合（非极性件翻转只换脚号）。""" + exp = {} + for d, lcsc, x, y, rot in place: + if lcsc == PCA: + exp[d] = dict((k, (x + dx, y + dy)) for k, (dx, dy) in PCA_REL.items()) + elif lcsc == MOS: + exp[d] = dict((k, (x + dx, y + dy)) for k, (dx, dy) in MOS_REL.items()) + else: + exp[d] = {'?': set([(x, y + 20), (x, y - 20)])} + return exp + + +def main(): + push = '--push' in sys.argv + place = placement() + for it in place: + assert it[1] in PARTS, u'eda-parts.json 里没有 %s' % it[1] + exp = expect(place) + + pins = {} + for d, want in exp.items(): + if '?' in want: + a, b = sorted(want['?']) + pins[d] = {'1': a, '2': b} + else: + pins[d] = dict(want) + + W, F, PT, TX = plan() + errs = netcheck(W, F, PT, pins) + print(u'元件 %d 导线 %d 旗 %d 端口 %d 文字 %d' + % (len(place), len(W), len(F), len(PT), len(TX))) + xs = crossings(W) + print(u'交叉点（不相连，供人工确认）: %d %s' % (len(xs), xs if xs else '')) + if errs: + print(u'本地自检 %d 条问题：' % len(errs)) + for e in errs: + print(u' ! ' + e) + raise SystemExit(1) + print(u'本地自检通过（短路 0 / 漏连 0 / 悬空 0 / 旗端口全在端点）') + if not push: + return + + n = call(""" + await eda.dmt_EditorControl.openDocument('%s'); await new Promise(r=>setTimeout(r,1200)); + const nm=(await eda.dmt_Schematic.getCurrentSchematicPageInfo()).name; + if (nm!=='%s') throw new Error('page='+nm); + let k=0; + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()==='sheet') continue; + await eda.sch_PrimitiveComponent.delete(c.getState_PrimitiveId()); k++; + } + for (const w of await eda.sch_PrimitiveWire.getAll()) await eda.sch_PrimitiveWire.delete(w.getState_PrimitiveId()); + for (const t of await eda.sch_PrimitiveText.getAll()) await eda.sch_PrimitiveText.delete(t.getState_PrimitiveId()); + return k; + """ % (PAGE, PAGE_NAME)) + print(u'%s 已清空（删掉 %d 个图元）' % (PAGE_NAME, n)) + + put = [[d, PARTS[l]['uuid'], x, y, rot, PARTS[l]['lib']] for d, l, x, y, rot in place] + for it in put: + assert len(it) == 6 and it[5], u'placement 少了 libraryUuid: %s' % (it,) # skill §9c-2 + for i in range(0, len(put), 4): + call(""" + for (const [d,uuid,x,y,rot,lib] of %s){ + await eda.sch_PrimitiveComponent.create({libraryUuid:lib, uuid}, x, y, undefined, rot, false, true, true); + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + if (Math.round(c.getState_X())!==x || Math.round(c.getState_Y())!==y) continue; + await c.toAsync().setState_Designator(d).done(); + } + } + return 1; + """ % json.dumps(put[i:i + 4])) + print(u'已放置 %d 个元件' % len(put)) + + READ = """ + const out={}; + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + out[c.getState_Designator()] = (await c.getAllPins()).map( + p=>[p.getState_PinNumber(), Math.round(p.getState_X()), Math.round(p.getState_Y())]); + } + return out; + """ + rots = dict((d, rot) for d, _l, _x, _y, rot in place) + for rnd in range(4): + got = call(READ) + bad = [] + for d, want in exp.items(): + if d not in got: + raise SystemExit(u'读不到元件 %s' % d) + have = dict((p, (x, y)) for p, x, y in got[d]) + if '?' in want: + if set(have.values()) != want['?']: + bad.append((d, sorted(want['?']), sorted(have.values()))) + else: + for p, xy in sorted(want.items()): + if have.get(p) != xy: + bad.append((d, p, xy, have.get(p))) + break + if not bad: + print(u'引脚坐标逐个核对通过（%d 个元件）' % len(exp)) + break + if rnd == 3: + raise SystemExit(u'引脚坐标对不上：\n ' + + '\n '.join(repr(b) for b in bad)) + names = sorted(set(b[0] for b in bad)) + print(u'第 %d 轮：翻转 %d 件重试 %s' % (rnd + 1, len(names), names)) + call(""" + for (const [d,rot] of %s){ + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + if (c.getState_Designator()!==d) continue; + await c.toAsync().setState_Rotation(rot).done(); + } + } + return 1; + """ % json.dumps([[d, (rots[d] + 180 * (rnd + 1)) % 360] for d in names])) + + def batch(items, size, js): + for i in range(0, len(items), size): + call(js % json.dumps(items[i:i + size], ensure_ascii=False)) + + batch([[a[0], a[1], b[0], b[1]] for a, b, _ in W], 40, + "for (const s of %s) await eda.sch_PrimitiveWire.create(s); return 1;") + batch(PT, 25, "for (const p of %s) await eda.sch_PrimitiveComponent.createNetPort(p[0],p[1],p[2],p[3],p[4],false); return 1;") + batch(F, 25, "for (const f of %s) await eda.sch_PrimitiveComponent.createNetFlag(f[0],f[1],f[2],f[3],f[4],false); return 1;") + batch([list(t) for t in TX], 12, + "for (const t of %s) await eda.sch_PrimitiveText.create(t[0],t[1],t[2],0,null,null,t[3],false,false,false,0); return 1;") + json.dump(NC, io.open(os.path.join(HERE, 'b2-nc.json'), 'w', encoding='utf-8'), + ensure_ascii=False, indent=1) + print(u'推送完成；接着跑 verify_sch.py --nets') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/b3-nc.json b/.claude/r2/b3-nc.json new file mode 100644 index 0000000..bdfb540 --- /dev/null +++ b/.claude/r2/b3-nc.json @@ -0,0 +1 @@ +{"U6": ["3"]} \ No newline at end of file diff --git a/.claude/r2/b3_phone.py b/.claude/r2/b3_phone.py new file mode 100644 index 0000000..e98a22e --- /dev/null +++ b/.claude/r2/b3_phone.py @@ -0,0 +1,190 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 **B3-PHONE** 页：手机侧机械接口 —— 电池排线 + 阻尼组 + 侧键焊盘 + EDL。 + + /c/Python314/python .claude/r2/b3_phone.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/b3_phone.py --push # 清页 + 重画（幂等） + +## ⚠️ M2c 拆成两页 + +R1 把同样的内容铺在**四页**上（`C4-SITE1` 电池/阻尼/顶针/EDL、`C5-J1401A` 尾插座、 +`C5-AUX` ESD/Rp/口温、`C3-USB` VBUS 开关）。塞进一张 A4 会挤到没法看，所以拆成： + +| 页 | 内容 | +|---|---| +| **`B3-PHONE`**（本页）| `J5` 电池排线 4 焊盘 + 阻尼电容组 + `K1~K4` 侧键中框焊盘 + EDL（`J3` + `U6`）| +| **`B3B-USB`** | `J4` BM24-50DS 尾插座 + `U7` USBLC6 ESD + Rp/口温 + `U5` TPS22918 VBUS 开关 | + +## 位号（方案 §7.2b，D11b 之后 U 序顺移） + +| 位号 | 器件 | 出处 | +|---|---|---| +| `J5` | MI8-BAT-FPC-4P（个人库自建，4 焊盘直焊排线）| R1 §13.5 的 `J81` | +| `R60/R61` | 10k TEMP→GND / 68k ID→GND | R1 的 `R781/R791`，阻值抄保护板实测 | +| `C60~C65` | 2200µF + 100µF×2 + 22µF×2 + 100nF | R1 §6.3 阻尼组 `C801~C806` 原样 | +| `K1~K3` | 侧键中框焊盘（Ø1.5 裸铜盘，`MI8-KEY-PAD`）| R1 §22.3e：顶针取消，螺丝把主板压在焊盘上 | +| `K4` | 侧键**公共地**焊盘（手机 J604）| 同上 | +| `J3` `U6` `R63` `C69` | EDL 1.25mm 2P 座 + TS5A3157 模拟开关 + 100k 下拉 + 去耦 | R1 §22.4 的 `J61/U41/R741/C761` | + +## 两条要紧的 + +1. **`P+`/`P−` 接的是保护板输出侧**（R1 §13.5）：排线从保护板焊点处剪断， + 4 个焊盘 `1=P+ 2=P− 3=TEMP 4=ID`，`TEMP`/`ID` 都是**对 P− 的**， + 按「对负极线」量会得出「三个都不通」的假结论。 +2. **`EDL_EN` 的 100k 下拉（`R63`）放在本页**（贴 `U6` 的 `IN` 脚）， + B2-CTRL 上没有 —— PCA9555 复位时是高阻输入，全靠这颗保证模拟开关断开。 +""" +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, two_pin, by_rel, pins_of # noqa: E402 + +PAGE, NAME = 'cf32a688430fc2d1', 'B3-PHONE' + +FPC, KEYPAD, EDLJ, SW = 'MI8-BAT-FPC-4P', 'MI8-KEY-PAD', 'C225104', 'C353034' +C2200U, C100U, C22U, C100N = 'C3828985', 'C15008', 'C12891', 'C1525' +R10K, R68K, R100K = 'C25744', 'C36871', 'C25741' + +# 引脚偏移（R1 实测，见 _c4s1_live.json）；rot 270 按 (x,y)->(y,-x) 推，放完断言 +FPC_REL = {'1': (-20, 15), '2': (-20, 5), '3': (-20, -5), '4': (-20, -15)} +EDLJ_R270 = {'1': (5, 25), '2': (-5, 25), '3': (25, 25), '4': (-25, 25)} +SW_R270 = {'1': (10, 35), '2': (0, 35), '3': (-10, 35), + '4': (-10, -35), '5': (0, -35), '6': (10, -35)} +KEY_REL = {'1': (-15, 0)} + +NC = {'U6': ['3']} # NC 脚不接（R1 的 U41.3 也是空的） +ALLOW_SPLIT = set(['GND', '+3V3']) + +RAIL_Y = 760 # VO_P 母线 +CAPS = [('C60', C2200U, 320, 20), ('C61', C100U, 400, 15), ('C62', C100U, 480, 15), + ('C63', C22U, 560, 15), ('C64', C22U, 640, 15), ('C65', C100N, 720, 20)] +KEYS = [('K1', 'KPAD_PWR', 700), ('K2', 'KPAD_VUP', 640), ('K3', 'KPAD_VDN', 580)] + +J5 = (260, 700) +J3 = (200, 340) +U6 = (620, 340) + + +def placement(): + out = [['J5', FPC, J5[0], J5[1], 0], + ['R60', R10K, 170, 640, 270], ['R61', R68K, 220, 600, 270], + ['J3', EDLJ, J3[0], J3[1], 270], ['U6', SW, U6[0], U6[1], 270], + ['R63', R100K, 760, 310, 270], ['C69', C100N, 1000, 300, 270]] + for des, lcsc, x, half in CAPS: + out.append([des, lcsc, x, RAIL_Y - 10 - half, 270]) + for des, _net, y in KEYS: + out.append([des, KEYPAD, 1100, y, 0]) + out.append(['K4', KEYPAD, 1100, 520, 0]) + return out + + +def expect(): + exp = {'J5': by_rel(J5[0], J5[1], FPC_REL), + 'J3': by_rel(J3[0], J3[1], EDLJ_R270), + 'U6': by_rel(U6[0], U6[1], SW_R270), + 'R60': two_pin(170, 640), 'R61': two_pin(220, 600), + 'R63': two_pin(760, 310), 'C69': two_pin(1000, 300)} + for des, _l, x, half in CAPS: + cy = RAIL_Y - 10 - half + if des == 'C60': + # ⚠ C60 是 2200µF **电解**：pin1(+) 必须在上（接 VO_P 母线）。 + # 只比坐标集合是不够的 —— skill §6c：同一个料号在不同页 rot 语义能相反， + # 本页实测 rot 270 给出的就是「pin1 在下」，第一次推下去极性是反的， + # 而几何验证、DRC 全过，只有网表里「C60.2 在 VO_P」能看出来。 + exp[des] = {'1': (x, cy + half), '2': (x, cy - half)} + else: + exp[des] = two_pin(x, cy, half) + for des, _net, y in KEYS: + exp[des] = by_rel(1100, y, KEY_REL) + exp['K4'] = by_rel(1100, 520, KEY_REL) + return exp + + +def build(): + s = Sheet(PAGE, NAME) + + # ── 1. 电池排线 + 阻尼组 ───────────────────────────────────────── + # 四个脚都朝左出，越靠下的脚拐得越靠右，往下走时才不会撞上面几行的横线 + px = J5[0] - 20 + s.w('VO_P', (px, 715), (200, 715), (200, RAIL_Y)) # 1 P+ + s.w('GND', (px, 705), (120, 705), (120, 660)) # 2 P− + s.gnd(120, 660, 0) + s.w('BAT_TEMP', (px, 695), (170, 695), (170, 660)) # 3 TEMP -> R60 + s.w('GND', (170, 620), (170, 595)) + s.gnd(170, 595, 0) + s.w('BAT_ID', (px, 685), (220, 685), (220, 620)) # 4 ID -> R61 + s.w('GND', (220, 580), (220, 555)) + s.gnd(220, 555, 0) + + s.w('VO_P', (200, RAIL_Y), (800, RAIL_Y)) # 母线 + s.port('IN', 'VO_P', 800, RAIL_Y, 180) + for _des, _l, x, half in CAPS: + cy = RAIL_Y - 10 - half + s.w('VO_P', (x, RAIL_Y), (x, cy + half)) + s.w('GND', (x, cy - half), (x, 685)) + s.gnd(x, 685, 0) + + # ── 2. 侧键中框焊盘 ────────────────────────────────────────────── + for _des, net, y in KEYS: + s.w(net, (1085, y), (1000, y)) + s.port('IN', net, 1000, y, 0) + s.w('GND', (1085, 520), (1040, 520), (1040, 495)) # K4 公共地 + s.gnd(1040, 495, 0) + + # ── 3. EDL：J3 两根信号经 U6 串在中间，EDL_EN 高 = 短接 ────────── + # J3 rot270 四个脚都朝上。排线顺序（从左到右）= 4 / 2 / 1 / 3： + # 外侧两个固定脚(4/3)就近入地、拐得比信号低；内侧两个信号往上翻出去， + # 这样「外侧先拐、内侧后拐」就不产生交叉（U6.COM 是下排脚，只能从下面绕过去）。 + s.w('GND', (175, 365), (175, 385), (135, 385), (135, 340)) # 4 固定脚 + s.gnd(135, 340, 0) + s.w('GND', (225, 365), (225, 405), (285, 405), (285, 430)) # 3 固定脚 + s.gnd(285, 430, 180) + s.w('EDL_A', (205, 365), (205, 510), (630, 510), (630, 375)) # 1 -> U6.NO（上排） + s.w('EDL_B', (195, 365), (195, 400), (100, 400), # 2 -> U6.COM（下排） + (100, 245), (610, 245), (610, 305)) + + s.w('GND', (620, 375), (620, 400), (580, 400), (580, 425)) # U6.2 GND + s.gnd(580, 425, 180) + # V+ 从下排出来往右走 y=265 这条道：它在 COM 那条横线(245)之上、 + # 又在 EDL_EN 那几根竖线(275 起)之下，是唯一一条不产生交叉的高度 + s.w('+3V3', (620, 305), (620, 265), (960, 265), (960, 290)) # U6.5 V+ + s.pwr('+3V3', 960, 290, 0) + s.w('+3V3', (960, 280), (1000, 280)) # -> C69 下脚 + s.w('GND', (1000, 320), (1000, 345)) + s.gnd(1000, 345, 180) + s.w('EDL_EN', (630, 305), (630, 275), (860, 275)) # U6.6 IN + s.w('EDL_EN', (760, 275), (760, 290)) # -> R63 下脚 + s.w('GND', (760, 330), (760, 355)) # R63 上脚 -> 地 + s.gnd(760, 355, 180) + s.w('EDL_EN', (860, 275), (900, 275), (900, 320)) + s.port('IN', 'EDL_EN', 900, 320, 0) + + # ── 4. 文字 ───────────────────────────────────────────────────── + s.txt(45, 795, u'【B3-PHONE】手机侧接口：电池排线 4 焊盘 + 阻尼组 + 侧键中框焊盘 ×3 + EDL', 14) + s.txt(60, 200, u'J5 = 小米8 电池排线剪断后的 4 焊盘（R1 §13.5）：1=P+ 2=P− 3=TEMP 4=ID。', 10) + s.txt(60, 182, u'⚠ 接的是保护板输出侧 P+/P−，不是 B+/B−；TEMP 与 ID 都是对 P− 的，', 10) + s.txt(60, 164, u' 按「对负极线」量会得出「三个都不通」的假结论。保护板整块不装。', 10) + s.txt(60, 146, u'R60 10k 代替原 NTC（固定模拟 25°C）、R61 68k 复制原 BATT_ID。', 10) + s.txt(60, 128, u'K1~K3 中框式裸铜焊盘，K4 是三键公共地（J604）；顶针已取消（§22.3e）。', 10) + return s + + +def main(): + push = '--push' in sys.argv + place = placement() + exp = expect() + s = build() + s.assert_grid() + errs = s.netcheck(pins_of(exp), NC, ALLOW_SPLIT) + s.report(len(place), errs) + if not push: + return + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets --nc .claude/r2/b3-nc.json') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/b3b-nc.json b/.claude/r2/b3b-nc.json new file mode 100644 index 0000000..93c507b --- /dev/null +++ b/.claude/r2/b3b-nc.json @@ -0,0 +1,38 @@ +{ + "J4": [ + "3", + "5", + "7", + "9", + "10", + "11", + "13", + "15", + "17", + "18", + "20", + "21", + "25", + "26", + "27", + "28", + "30", + "31", + "32", + "33", + "34", + "35", + "36", + "38", + "39", + "40", + "42", + "43", + "44", + "45", + "46", + "48", + "49", + "50" + ] +} \ No newline at end of file diff --git a/.claude/r2/b3b_usb.py b/.claude/r2/b3b_usb.py new file mode 100644 index 0000000..e5a36c6 --- /dev/null +++ b/.claude/r2/b3b_usb.py @@ -0,0 +1,298 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 **B3B-USB** 页：尾插座 + D± ESD + Rp/口温 + VBUS 负载开关。 + + /c/Python314/python .claude/r2/b3b_usb.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/b3b_usb.py --push # 清页 + 重画（幂等） + +M2c 的第二页（拆页理由见 `b3_phone.py` 的表头）。R1 把这些铺在 +`C5-J1401A`（尾插座）、`C5-AUX`（ESD + Rp + 口温）、`C3-USB`（VBUS 开关）三页上。 + +| 位号 | 器件 | 出处 | +|---|---|---| +| `J4` | BM24-50DS/2-0.35V，个人库自建封装（**Hirose 奇偶行编号**，立创那个是 DIP 绕圈，错的）| R1 `J71` | +| `U7` | USBLC6-2SC6，D± ESD | R1 `U51` | +| `R64` | 56k `CC1 → VBUS` 的 Rp（Default USB 档）| R1 `R761`，见 §23.3 | +| `R65` | 100k 口温 → GND | R1 `R771` | +| `U5` `C66~C68` `R62` | TPS22918 + 2.2µF CIN + 100nF COUT + 100pF CT + 100k ON 下拉 | R1 `U24/C701/C711/C721/R701`，§18.2 | + +## ⚠️ `J4` 的脚号 → 网络**照抄 R1**，不要自己按 §13.4 推 + +R1 §24 那一轮把「手机 J1401 的 Hirose 脚号」经原厂排线映射到座子焊盘号， +中间隔着一次实测（§24「已实测确认的三件事」）。本页的 `PIN_NET` 表是从 +R1 `C5-J1401A` 的 `J71` **原样读回来的**（`_c5j1401a_live.json`），脚本启动时 +拿它和源页比对，对不上直接终止 —— 按 §13.4 的表重推一遍必然错位。 + +## 三条与 R1 相同、这里再记一次的 + +1. **`U7` 是「1/6 内部同一个 I/O1、3/4 同一个 I/O2」的直通器件**， + 原理图上天然是两段（skill §8b）：手机侧 `USB_D*J`、上游侧 `USB_D*`。 + ⇒ PCB 上走线必然串在两个焊盘中间，不会偷偷从旁边绕过去只搭一个脚。 +2. **`R64` 这颗 Rp 不能省**：手机的 PMI8998 靠 CC 上看到 Rp 才判定「有 DFP 插入」。 + R1 §23.2 的坑是「Rp 藏在 USB-A 转 C 线的 C 头里」，而这里没有那根线。 +3. **`R62` 100k 是 `VBUS_EN` 的下拉**（datasheet 明令 ON 脚不得悬空）： + PCA9555 复位时高阻，全靠它保证 VBUS 默认断开（D9 复位安全的一半）。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, two_pin, by_rel, pins_of # noqa: E402 + +PAGE, NAME = '4ce5bfe35e90e560', 'B3B-USB' + +BM24, ESD, LSW = 'BM24-HRS-PIN', 'C2687116', 'C131941' +R56K, R100K, C2U2, C100N, C100P = 'C25796', 'C25741', 'C377773', 'C1525', 'C1546' + +# ── J4 的脚号 -> 网络：从 R1 C5-J1401A 的 J71 原样搬（去掉通道后缀）────── +PIN_NET = {'51': 'VBUS', '4': 'USB_DMJ', '6': 'USB_DPJ', + '14': 'USB_THERM', '22': 'CC1'} +GND_PINS = ['1', '2', '8', '12', '16', '19', '23', '24', '29', '37', '41', '47', '52'] +SRC = os.path.join(HERE, '_c5j1401a_live.json') +SRC_MAP = {'VBUS1': 'VBUS', 'USB1_DMJ': 'USB_DMJ', 'USB1_DPJ': 'USB_DPJ', + 'THERM_1': 'USB_THERM', 'CC1_1': 'CC1'} + +J4 = (940, 580) +U7 = (330, 420) +U5 = (700, 420) + +ESD_R270 = {'1': (10, 45), '2': (0, 45), '3': (-10, 45), + '4': (-10, -45), '5': (0, -45), '6': (10, -45)} +# ⚠ skill §6c 又一例：同一个料号（TPS22918 SOT-23-6），R1 的 C3-USB 上 +# create(270) 得到「1/2/3 在上排」，本页实测是**在下排**。三种角度都量过： +# rot 0 1(-60,+10) … 6(+60,+10) rot 90 1(+10,+60) … +# rot 270 1(-10,-60) 2(0,-60) 3(+10,-60) / 4(+10,+60) 5(0,+60) 6(-10,+60) +# 所以下面这张表是**本页实测**，不是从 R1 抄的；放完仍然逐脚断言。 +LSW_R270 = {'1': (-10, -60), '2': (0, -60), '3': (10, -60), + '4': (10, 60), '5': (0, 60), '6': (-10, 60)} + + +def bm24_rel(n): + u"""BM24 符号：1~25 左列自上而下，26~50 右列自下而上，51/52 在正中上下。""" + if n == 51: + return (0, 140) + if n == 52: + return (0, -140) + if n <= 25: + return (-30, 120 - 10 * (n - 1)) + return (30, -120 + 10 * (n - 26)) + + +BM24_REL = dict((str(n), bm24_rel(n)) for n in range(1, 53)) +USED = set(PIN_NET) | set(GND_PINS) +NC = {'J4': [str(n) for n in range(1, 53) if str(n) not in USED]} +ALLOW_SPLIT = set(['GND', 'VBUS', 'CC1', 'USB_THERM', + 'USB_DPJ', 'USB_DMJ', 'USB_DP', 'USB_DM']) + +LBUS, PORTX, RBUS = J4[0] - 200, J4[0] - 70, J4[0] + 90 + + +def check_source(): + u"""和 R1 源页逐脚对账：脚号→网络必须一模一样，对不上就别画。""" + if not os.path.exists(SRC): + print(u'⚠ 找不到 %s，跳过与 R1 的对账（重新 dump_page.py 一次更稳）' % SRC) + return + d = json.load(io.open(SRC, encoding='utf-8')) + pts = d['wires'] + segs = [((int(round(pts[i][0])), int(round(pts[i][1]))), + (int(round(pts[i + 1][0])), int(round(pts[i + 1][1])))) + for i in range(0, len(pts), 2)] + segs = [s for s in segs if s[0] != s[1]] + + par = {} + + def find(a): + par.setdefault(a, a) + while par[a] != a: + par[a] = par[par[a]] + a = par[a] + return a + + def uni(a, b): + ra, rb = find(a), find(b) + if ra != rb: + par[ra] = rb + + def on(p, s): + (x1, y1), (x2, y2) = s + if x1 == x2: + return p[0] == x1 and min(y1, y2) <= p[1] <= max(y1, y2) + return p[1] == y1 and min(x1, x2) <= p[0] <= max(x1, x2) + + for s in segs: + uni(s[0], s[1]) + for s in segs: + for t in segs: + if on(s[0], t): + uni(s[0], t[0]) + if on(s[1], t): + uni(s[1], t[0]) + name = {} + for kind, net, x, y, _rot in d['flags'] + d['ports']: + p = (int(round(x)), int(round(y))) + for s in segs: + if on(p, s): + name.setdefault(find(s[0]), set()).add( + 'GND' if kind.startswith('Ground') else net) + break + src = None + for p in d['parts']: + if p[0] == 'J71': + src = p + assert src, u'源页里找不到 J71' + got = {} + for q in src[9]: + pn, x, y = str(q[0]), int(round(q[2])), int(round(q[3])) + for s in segs: + if on((x, y), s): + nm = sorted(name.get(find(s[0]), [])) + if nm: + got[pn] = SRC_MAP.get(nm[0], nm[0]) + break + want = dict(PIN_NET) + for pn in GND_PINS: + want[pn] = 'GND' + if got != want: + diff = [(k, want.get(k), got.get(k)) + for k in sorted(set(want) | set(got), key=int) + if want.get(k) != got.get(k)] + raise SystemExit(u'J4 脚号→网络与 R1 的 J71 对不上：%s' % diff) + print(u'J4 脚号→网络与 R1 的 J71 逐脚一致（%d 个脚）' % len(want)) + + +def placement(): + return [['J4', BM24, J4[0], J4[1], 0], + ['U7', ESD, U7[0], U7[1], 270], + ['U5', LSW, U5[0], U5[1], 270], + ['R62', R100K, 760, 295, 270], + ['R64', R56K, 920, 300, 270], + ['R65', R100K, 1030, 300, 270], + ['C66', C2U2, 600, 280, 0], # 2.2µF/0805：rot 0 才是竖的（§8d） + ['C67', C100N, 640, 550, 270], + ['C68', C100P, 560, 640, 270]] + + +def expect(): + return {'J4': by_rel(J4[0], J4[1], BM24_REL), + 'U7': by_rel(U7[0], U7[1], ESD_R270), + 'U5': by_rel(U5[0], U5[1], LSW_R270), + 'R62': two_pin(760, 295), 'R64': two_pin(920, 300), + 'R65': two_pin(1030, 300), 'C66': two_pin(600, 280), + 'C67': two_pin(640, 550), 'C68': two_pin(560, 640, 15)} + + +def build(): + s = Sheet(PAGE, NAME) + jx, jy = J4 + + # ── 1. J4 BM24-50DS（版图照搬 R1 C5-J1401A：地母线甩到最左/最右， + # 信号端口排在母线与引脚之间，两者永不交叉）────────────────── + left = [n for n in GND_PINS if int(n) <= 25 or n == '52'] + for n in [x for x in GND_PINS if int(x) <= 25]: + y = jy + bm24_rel(int(n))[1] + s.w('GND', (jx - 30, y), (LBUS, y)) + s.w('GND', (LBUS, jy - 110), (LBUS, jy + 160)) + s.gnd(LBUS, jy + 160, 180) + for n in [x for x in GND_PINS if 26 <= int(x) <= 50]: + y = jy + bm24_rel(int(n))[1] + s.w('GND', (jx + 30, y), (RBUS, y)) + s.w('GND', (RBUS, jy - 90), (RBUS, jy + 110)) + s.gnd(RBUS, jy + 110, 180) + s.w('GND', (jx, jy - 140), (jx, jy - 170)) # 52 电源触点 G1 + s.gnd(jx, jy - 170, 0) + s.w('VBUS', (jx, jy + 140), (jx, jy + 170), (jx + 70, jy + 170)) # 51 = G2 + s.port('BI', 'VBUS', jx + 70, jy + 170, 0) + for n, net in sorted(PIN_NET.items(), key=lambda kv: -int(kv[0])): + if n == '51': + continue + y = jy + bm24_rel(int(n))[1] + s.w(net, (jx - 30, y), (PORTX, y)) + s.port('BI', net, PORTX, y, 180) + assert len(left) == len([x for x in GND_PINS if int(x) <= 25]) + 1 + + # ── 2. U7 USBLC6：中间那个 GND 直着走，两边的信号朝相反方向拐开 ──── + ux, uy = U7 + s.w('USB_DMJ', (ux + 10, uy + 45), (ux + 10, 505), (420, 505)) + s.port('BI', 'USB_DMJ', 420, 505, 0) + s.w('USB_DPJ', (ux - 10, uy + 45), (ux - 10, 505), (240, 505)) + s.port('BI', 'USB_DPJ', 240, 505, 180) + s.w('GND', (ux, uy + 45), (ux, 545)) + s.gnd(ux, 545, 180) + s.w('USB_DM', (ux + 10, uy - 45), (ux + 10, 335), (420, 335)) + s.port('BI', 'USB_DM', 420, 335, 0) + s.w('USB_DP', (ux - 10, uy - 45), (ux - 10, 335), (240, 335)) + s.port('BI', 'USB_DP', 240, 335, 180) + s.w('VBUS', (ux, uy - 45), (ux, 295)) + s.port('BI', 'VBUS', ux, 295, 0) + + # ── 3. U5 TPS22918（rot270 实测：VIN/GND/ON 在下排，VOUT/QOD/CT 在上排）── + vx, vy = U5 + s.w('+5V', (vx - 10, vy - 60), (vx - 10, 320), (560, 320)) # 1 VIN + s.port('IN', '+5V', 560, 320, 180) + s.w('+5V', (600, 320), (600, 300)) # -> C66 上脚 + s.w('GND', (600, 260), (600, 235)) + s.gnd(600, 235, 0) + s.w('GND', (vx, vy - 60), (vx, 300)) # 2 GND 直着下来 + s.gnd(vx, 300, 0) + s.w('VBUS_EN', (vx + 10, vy - 60), (vx + 10, 330), (800, 330)) # 3 ON + s.port('IN', 'VBUS_EN', 800, 330, 180) + s.w('VBUS_EN', (760, 330), (760, 315)) # -> R62 上脚 + s.w('GND', (760, 275), (760, 250)) + s.gnd(760, 250, 0) + s.w('VBUS', (vx, vy + 60), (vx, 560)) # 5 QOD + s.port('BI', 'VBUS', vx, 560, 0) + s.w('VBUS', (vx - 10, vy + 60), (vx - 10, 520), (vx, 520)) # 6 VOUT -> QOD + s.w('VBUS', (vx, 530), (640, 530)) # -> C67 下脚 + s.w('GND', (640, 570), (640, 595)) + s.gnd(640, 595, 180) + s.w('CT', (vx + 10, vy + 60), (vx + 10, 620), (560, 620)) # 4 CT + s.w('CT', (560, 620), (560, 625)) + s.w('GND', (560, 655), (560, 680)) + s.gnd(560, 680, 180) + + # ── 4. Rp 与口温 ───────────────────────────────────────────────── + s.w('VBUS', (920, 320), (920, 345)) + s.port('BI', 'VBUS', 920, 345, 0) + s.w('CC1', (920, 280), (920, 255)) + s.port('BI', 'CC1', 920, 255, 0) + s.w('USB_THERM', (1030, 320), (1030, 345)) + s.port('BI', 'USB_THERM', 1030, 345, 0) + s.w('GND', (1030, 280), (1030, 255)) + s.gnd(1030, 255, 0) + + # ── 5. 文字 ───────────────────────────────────────────────────── + s.txt(45, 795, u'【B3B-USB】尾插座 BM24-50DS + D± ESD + Rp/口温 + VBUS 负载开关', 14) + s.txt(60, 265, u'J4 的脚号→网络照抄 R1 的 J71（隔着一次排线映射实测，§24），', 10) + s.txt(60, 247, u' 脚本每次都和 C5-J1401A 逐脚对账，对不上直接终止。', 10) + s.txt(60, 229, u'⚠ 51/52 是两个大电源触点：51 = G2 = USB_VBUS，52 = G1 = 真地。', 10) + s.txt(60, 211, u' 接反就是 5V 对地短路 —— 打样前用表笔在排线自由端确认一次。', 10) + s.txt(60, 193, u'⚠ R64 56k 是 CC1 上拉到 VBUS 的 Rp：手机靠它判定「有主机插入」。', 10) + s.txt(60, 175, u' R1 里这颗藏在 USB-A 转 C 线的 C 头中，本方案没有那根线，必须自己放。', 10) + s.txt(60, 157, u'⚠ R62 100k：ON 脚不得悬空（datasheet），PCA9555 复位时高阻 ⇒ VBUS 默认断。', 10) + s.txt(60, 139, u'U7 的 1/6、3/4 内部各自短接，图上是两段：手机侧 *_DPJ/DMJ、上游侧 *_DP/DM。', 10) + return s + + +def main(): + push = '--push' in sys.argv + check_source() + place = placement() + exp = expect() + s = build() + s.assert_grid() + errs = s.netcheck(pins_of(exp), NC, ALLOW_SPLIT) + s.report(len(place), errs) + if not push: + return + s.clear() + s.place(place, exp) + s.push_geometry() + json.dump(NC, io.open(os.path.join(HERE, 'b3b-nc.json'), 'w', encoding='utf-8'), + ensure_ascii=False, indent=1) + print(u'接着跑 verify_sch.py --nets --nc .claude/r2/b3b-nc.json') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/b4-nc.json b/.claude/r2/b4-nc.json new file mode 100644 index 0000000..2f76312 --- /dev/null +++ b/.claude/r2/b4-nc.json @@ -0,0 +1,10 @@ +{ + "J1": [ + "A5", + "A6", + "A7", + "A8", + "B9", + "B10" + ] +} \ No newline at end of file diff --git a/.claude/r2/b4_edge.py b/.claude/r2/b4_edge.py new file mode 100644 index 0000000..2192260 --- /dev/null +++ b/.claude/r2/b4_edge.py @@ -0,0 +1,266 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 **B4-EDGE** 页：PCI-E x4 金手指 + PRSNT# 短接 + D± 退路座。 + + /c/Python314/python .claude/r2/b4_edge.py # 只算 + 本地自检 + /c/Python314/python .claude/r2/b4_edge.py --push # 清页 + 重画（幂等） + +M2 的最后一页（前四页见 b1_power / b2_ctrl / b3_phone / b3b_usb）。 + +## T4 已核（2026-09-08）：针位表对着 PCI-E CEM 逐脚核过，方案文档 §5.2 有两处是错的 + +| 针 | 方案文档（凭记忆写的） | CEM 实际 | 后果 | +|---|---|---|---| +| **B3** | 「RSVD，拿来做 +5V」 | **+12V**（B1/B2/B3 三针都是） | 刀片误插进真 PC：主板把 12 V 灌进刀片的 +5V 轨，U5 TPS22918（6V abs max）与手机 VBUS 全灭 | +| B12 | 「RSVD」 | CEM 1.x = RSVD，2.0 起 = CLKREQ# | 不能当自由针用（真主板上有 3.3V 上拉、真卡上是开漏输出）| + +⇒ **+5V 改挂 A19 / A32** —— 这两针在 CEM 1.x~5.0 每一版里都是 RSVD， + 真主板上不接、真卡上也不接，是两个方向都安全的仅有选择。 + 代价：两针都在 A 排，图上是两个同名 `+5V` 端口（见下面 ALLOW_SPLIT）。 + +其余针位与 §5.2 一致：+12V=B1/B2/B3/A2/A3、+3V3=B8/A9/A10、SCL=B5(SMCLK)、 +SDA=B6(SMDAT)、INT#=B11(WAKE#)、EFUSE_EN=A11(PERST#)、D±=B14/B15(PET0，两侧 B13/B16 天然夹地)、 +PRSNT#=A1↔B31（x4 全长在位；B17 那个是 x1 用的，本板当地用）。 + +**VDAC 定在 A16**（PERp0）：上下两针 A15 / A17 都是地，是全连接器夹得最干净的一个位置。 +方案文档原来写「预留差分对 A16/A17」—— 那对差分在刀片上没有对端，留着也用不了， +让给需要屏蔽的模拟量更划算。 + +## 悬空的 6 根针（`b4-nc.json`） + +`A5~A8`（JTAG TCK/TDI/TDO/TMS）、`B9`（JTAG TRST#）、**`B10`（+3.3Vaux）**。 +⚠ B10 是必须悬空的那一根：真卡插进底板槽时，底板若在这针上给了 5V 会直接打穿它的 aux 域。 + +其余用不上的针（B12 CLKREQ# / B17 PRSNT#2(x1) / B30 PWRBRK# / 全部 lane 针）一律接地： +两个方向都无害（主板侧要么开漏、要么 AC 耦合），换来 39 根地针的回流面积。 + +## 版图：地母线甩到最左/最右，信号端口排在母线与引脚之间 + +抄 `b3b_usb` 的 J4（50 脚 BM24）那一套 —— 地是长横线一路拉到母线，信号是短横线接端口， +两者 y 不同所以永不交叉。竖线只在同一网络的几针之间用，且都躲在母线之外的空白区。 + +## ⚠ ALLOW_SPLIT 放宽了，补一层更硬的判据 + +连接器页天然靠同名端口/旗成网，不是靠导线：`GND`（三段梳子）、`+12V`（A/B 两排）、 +`+3V3`（A/B 两排）、`+5V`（A19/A32 两针）、`USB_DP/DM`（金手指 + 退路座）都是分块的。 +放宽 ALLOW_SPLIT 会让「漏连」这条检查失效，所以本脚本额外做一件事： +逐脚断言「这根针踩着的那段导线，声明的网络名 == PIN_NET 里写的」（`check_pin_nets`）。 +少接一根、接错一根都会当场报出来。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +from schcheck import Sheet, by_rel # noqa: E402 + +PAGE, NAME = 'c8f10dbd1286853b', 'B4-EDGE' + +EDGE, WV4 = 'PCIE-X4-EDGE-64P', 'C225106' + +# ── 版面常量 ───────────────────────────────────────────────────────── +J1 = (620, 470) # 金手指符号中心；A 排引脚 x=585，B 排 x=655 +AX, BX = J1[0] - 35, J1[0] + 35 +ABUS, BBUS = 340, 900 # 左/右地母线 +APORT, BPORT = 490, 760 # 信号端口列 +J2 = (1000, 700) # D± 退路座（1.25mm 4P），引脚朝左 + + +def row(n): + u"""金手指第 n 号针的 y（A/B 两排同高，pitch 10）。""" + return J1[1] + 155 - 10 * (n - 1) + + +# ── 64 根针的网络分配（T4 已核，出处见表头）────────────────────────── +PIN_NET = {} +for _n, _net in [(1, 'PRSNT#'), (2, '+12V'), (3, '+12V'), (4, 'GND'), + (5, 'NC'), (6, 'NC'), (7, 'NC'), (8, 'NC'), + (9, '+3V3'), (10, '+3V3'), (11, 'EFUSE_EN'), + (12, 'GND'), (13, 'GND'), (14, 'GND'), (15, 'GND'), + (16, 'VDAC'), (17, 'GND'), (18, 'GND'), (19, '+5V'), + (32, '+5V')]: + PIN_NET['A%d' % _n] = _net +for _n in range(20, 32): # A20~A31 全部接地 + PIN_NET['A%d' % _n] = 'GND' +for _n, _net in [(1, '+12V'), (2, '+12V'), (3, '+12V'), (4, 'GND'), + (5, 'SCL'), (6, 'SDA'), (7, 'GND'), (8, '+3V3'), + (9, 'NC'), (10, 'NC'), (11, 'INT#'), + (12, 'GND'), (13, 'GND'), (14, 'USB_DP'), (15, 'USB_DM'), + (31, 'PRSNT#'), (32, 'GND')]: + PIN_NET['B%d' % _n] = _net +for _n in range(16, 31): # B16~B30 全部接地 + PIN_NET['B%d' % _n] = 'GND' +assert len(PIN_NET) == 64, len(PIN_NET) + +NC = {'J1': [p for p, n in PIN_NET.items() if n == 'NC']} +assert sorted(NC['J1']) == sorted(['A5', 'A6', 'A7', 'A8', 'B9', 'B10']), NC['J1'] + +# 地母线要按「连续成段」切：中间隔着信号针的地方断开，每一段自带一面地旗。 +AGND = [n for n in range(1, 33) if PIN_NET['A%d' % n] == 'GND'] +BGND_MAIN = [n for n in range(1, 33) + if PIN_NET['B%d' % n] == 'GND' and n != 32] + +# 同名端口/旗成网、导线上天然分块的网络（判据换成 check_pin_nets，见表头） +ALLOW_SPLIT = set(['GND', '+12V', '+3V3', '+5V', 'USB_DP', 'USB_DM']) + +EDGE_REL = {} +for _n in range(1, 33): + EDGE_REL['A%d' % _n] = (-35, 155 - 10 * (_n - 1)) + EDGE_REL['B%d' % _n] = (35, 155 - 10 * (_n - 1)) +# A1251WV-S-4P rot 0 实测：1~4 自上而下、5/6 是两个固定脚，全部朝左出 +WV4_REL = {'1': (-25, 15), '2': (-25, 5), '3': (-25, -5), '4': (-25, -15), + '5': (-25, 35), '6': (-25, -35)} + + +def placement(): + return [['J1', EDGE, J1[0], J1[1], 0], + ['J2', WV4, J2[0], J2[1], 0]] + + +def expect(): + return {'J1': by_rel(J1[0], J1[1], EDGE_REL), + 'J2': by_rel(J2[0], J2[1], WV4_REL)} + + +def build(): + s = Sheet(PAGE, NAME) + + # ── 1. 地：左右两把梳子 ────────────────────────────────────────── + for n in AGND: + s.w('GND', (AX, row(n)), (ABUS, row(n))) + s.w('GND', (ABUS, row(AGND[0])), (ABUS, 625)) # 母线往上甩出去挂旗 + s.w('GND', (ABUS, row(AGND[0])), (ABUS, row(AGND[-1]))) + s.gnd(ABUS, 625, 180) + + for n in BGND_MAIN: + s.w('GND', (BX, row(n)), (BBUS, row(n))) + # ⚠ 母线在 B8(+3V3) 那一行故意断开：B9/B10 悬空、这一段是全页唯一 + # 能让 +3V3 横穿到母线以东挂电源旗的通道（否则右半边被梳子封死）。 + s.w('GND', (BBUS, row(4)), (BBUS, 625)) + s.w('GND', (BBUS, row(4)), (BBUS, row(7))) + s.gnd(BBUS, 625, 180) + s.w('GND', (BBUS, row(12)), (BBUS, row(30))) + s.w('GND', (BBUS, row(30)), (BBUS, 310)) + s.gnd(BBUS, 310, 0) + # B32 单独一根（下面就是 PRSNT# 的过桥，梳子伸不下去） + s.w('GND', (BX, row(32)), (BX, 290)) + s.gnd(BX, 290, 0) + + # ── 2. +12V：A2/A3 与 B1/B2/B3，各自并起来出一个端口 ───────────── + s.w('+12V', (AX, row(2)), (520, row(2))) + s.w('+12V', (AX, row(3)), (520, row(3))) + s.w('+12V', (520, 650), (520, row(3))) + s.w('+12V', (520, 650), (470, 650)) + s.port('OUT', '+12V', 470, 650, 0) + for n in (1, 2, 3): + s.w('+12V', (BX, row(n)), (720, row(n))) + s.w('+12V', (720, row(1)), (720, row(3))) + s.w('+12V', (720, row(1)), (720, 660)) + s.w('+12V', (720, 660), (790, 660)) + s.port('OUT', '+12V', 790, 660, 180) + + # ── 3. +3V3：A9/A10 一面旗，B8 横穿母线缺口到东边一面旗 ────────── + s.w('+3V3', (AX, row(9)), (450, row(9))) + s.w('+3V3', (AX, row(10)), (450, row(10))) + s.w('+3V3', (450, row(9)), (450, row(10))) + s.w('+3V3', (450, row(9)), (450, 570)) + s.pwr('+3V3', 450, 570, 0) + s.w('+3V3', (BX, row(8)), (1000, row(8))) + s.w('+3V3', (1000, row(8)), (1000, 580)) + s.pwr('+3V3', 1000, 580, 0) + + # ── 4. +5V：A19 / A32 两根 RSVD 针，各一个同名端口 ─────────────── + for n in (19, 32): + s.w('+5V', (AX, row(n)), (APORT, row(n))) + s.port('OUT', '+5V', APORT, row(n), 0) + + # ── 5. A 排信号 ───────────────────────────────────────────────── + s.w('EFUSE_EN', (AX, row(11)), (APORT, row(11))) + s.port('OUT', 'EFUSE_EN', APORT, row(11), 0) + s.w('VDAC', (AX, row(16)), (APORT, row(16))) + s.port('OUT', 'VDAC', APORT, row(16), 0) + + # ── 6. B 排信号 ───────────────────────────────────────────────── + for n, net, d in ((5, 'SCL', 'BI'), (6, 'SDA', 'BI'), (11, 'INT#', 'IN'), + (14, 'USB_DP', 'BI'), (15, 'USB_DM', 'BI')): + s.w(net, (BX, row(n)), (BPORT, row(n))) + s.port(d, net, BPORT, row(n), 180) + + # ── 7. PRSNT#：A1 ↔ B31，从符号上方绕到下方（x4 全长在位）──────── + s.w('PRSNT#', (AX, row(1)), (AX, 680)) + s.w('PRSNT#', (AX, 680), (290, 680)) + s.w('PRSNT#', (290, 680), (290, 245)) + s.w('PRSNT#', (290, 245), (700, 245)) + s.w('PRSNT#', (700, 245), (700, row(31))) + s.w('PRSNT#', (700, row(31)), (BX, row(31))) + # 这个端口在刀片上没有对端（PRSNT# 只在金手指内部短接），纯粹为了给网络起名 —— + # 不放的话 EasyEDA 会给它一个 $4N... 默认名，PCB 侧脚本按名字就认不出来。 + # xpage.py 的 NAMING_ONLY 里已加了它。 + s.w('PRSNT#', (620, 245), (620, 215)) + s.port('OUT', 'PRSNT#', 620, 215, 0) + + # ── 8. J2 D± 退路座（1=+5V 2=DP 3=DM 4/5/6=GND）────────────────── + jx, jy = J2 + for dy, net, d in ((15, '+5V', 'OUT'), (5, 'USB_DP', 'BI'), (-5, 'USB_DM', 'BI')): + s.w(net, (jx - 25, jy + dy), (890, jy + dy)) + s.port(d, net, 890, jy + dy, 0) + for dy in (35, -15, -35): # 4 = 地，5/6 = 固定脚 + s.w('GND', (jx - 25, jy + dy), (1030, jy + dy)) + s.w('GND', (1030, jy + 35), (1030, jy - 35)) + s.w('GND', (1030, jy + 35), (1030, jy + 60)) + s.gnd(1030, jy + 60, 180) + + # ── 9. 文字 ───────────────────────────────────────────────────── + s.txt(45, 795, u'【B4-EDGE】PCI-E x4 金手指（只借机械与针位语义，不是 PCIe）+ D± 退路座', 14) + s.txt(45, 230, u'⚠ NOT PCIe —— 底板插槽旁必须丝印「PhoneRail blade only」。', 11) + s.txt(45, 212, u'T4 已核 CEM 引脚表：B1/B2/B3 都是 +12V（不是 RSVD），', 10) + s.txt(45, 194, u' 所以 +5V 挪到 A19 / A32 —— 每一版 CEM 里它俩都是 RSVD。', 10) + s.txt(45, 176, u'⚠ B10 = +3.3Vaux 必须悬空；B12/B17/B30 与全部 lane 针接地。', 10) + s.txt(45, 158, u'PRSNT# = A1 ↔ B31 短接（x4 全长在位判据）。', 10) + s.txt(45, 140, u'J2 = D± 退路座：PCB 上金手指到 J2 之间留割断位（D12）。', 10) + return s + + +def check_pin_nets(s): + u"""逐脚断言「针踩着的那段导线声明的网络」== PIN_NET。ALLOW_SPLIT 放宽之后靠这条兜底。""" + from schcheck import _on + errs = [] + pins = dict((p, (AX if p[0] == 'A' else BX, row(int(p[1:])))) + for p in PIN_NET) + for p, xy in sorted(pins.items()): + want = PIN_NET[p] + got = sorted(set(seg[2] for seg in s.W if _on(xy, seg[0], seg[1]))) + if want == 'NC': + if got: + errs.append(u'%s 应当悬空，却踩在 %s 上' % (p, got)) + elif got != [want]: + errs.append(u'%s 应当是 %s，实际踩着 %s' % (p, want, got or u'（空）')) + return errs + + +def main(): + push = '--push' in sys.argv + place = placement() + exp = expect() + s = build() + s.assert_grid() + pins = dict((d, dict((k, tuple(v)) for k, v in want.items())) + for d, want in exp.items()) + errs = s.netcheck(pins, NC, ALLOW_SPLIT) + check_pin_nets(s) + ngnd = len([1 for p, n in PIN_NET.items() if n == 'GND']) + print(u'金手指 64 针：地 %d / 悬空 %d / 有名信号 %d' + % (ngnd, len(NC['J1']), 64 - ngnd - len(NC['J1']))) + s.report(len(place), errs) + with io.open(os.path.join(HERE, 'b4-nc.json'), 'w', encoding='utf-8') as f: + f.write(json.dumps(NC, ensure_ascii=False, indent=1)) + if not push: + return + s.clear() + s.place(place, exp) + s.push_geometry() + print(u'接着跑 verify_sch.py --nets --nc .claude/r2/b4-nc.json') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/board_check.py b/.claude/r2/board_check.py new file mode 100644 index 0000000..d1bf894 --- /dev/null +++ b/.claude/r2/board_check.py @@ -0,0 +1,210 @@ +# -*- coding: utf-8 -*- +u"""**从板上读回铜**，按真实几何判每个网通没通（M7）。 + + /c/Python314/python .claude/r2/board_check.py # 全部网络 + /c/Python314/python .claude/r2/board_check.py --net SDA # 只看一个 + +## 为什么不能用现成的那几个 + +| 判据 | 问题 | +|---|---| +| `router.py` 的连通性 | 判的是**缓存里的几何**，手工改过板（挪过孔、改线）之后就过期了 | +| `router_check.py` | 同上，而且只判净距不判连通 | +| `pcb_route.py --check`（`getNetLength`）| 客户端重载之后一律返回 0，读不出来 | +| EasyEDA 的连接性 DRC | 计数在重载前后能差 5 倍（52 → 237），而且读不回明细 | + +⇒ 这里只信一件事：**板上读回来的线段 / 过孔 / 焊盘**，按「铜挨着铜就是连着」 +做并查集。判据是「同一个网的所有焊盘落在同一块铜里」。 + +## 平面网另算 + +`GND` / `VO_P` / `+12V` 靠铜面 + 缝合过孔成网，铜面不在这个检查里（读不回填充多边形）， +所以它们只报「有几只脚一根铜都不挨」——那种才是真漏。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +# ⚠ `--base` 切到底板（`pcb_base` + `_base_pads.json`）；不带就是刀片，行为一字未变。 +if '--base' in sys.argv: + import pcb_base as B # noqa: E402 + PADS_JSON = os.path.join(HERE, '_base_pads.json') +else: + import pcb_blade as B # noqa: E402 + PADS_JSON = os.path.join(HERE, '_blade_pads.json') + +MIL = B.MIL +PLANE = ('GND', 'VO_P', '+12V', '+12V_F', '+3V3') +# ⚠ `+3V3` 从 M9b 起也是**铜面网**（五块槽墙，方案 §30）：15 只槽脚一根线都不接， +# 靠铺铜盖住。⇒ 它和 12V 一样，只能判「脚是不是至少挨着一根铜」， +# 而**被计划中的铜面盖住的脚要先摘掉**（下面 `covered()`），否则每次都刷一堆假漏。 +# 槽脚真正的判据是 `pour_base.wall_check()`（盖没盖住）+ DRC + 截图。 +TOUCH = 0.02 # 判「挨着」的容差（mm） + +JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const L=(await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>[1,2,15,16].includes(l.layer)) + .map(l=>[l.net,l.layer,l.startX,l.startY,l.endX,l.endY,l.lineWidth]); +const V=(await eda.pcb_PrimitiveVia.getAll()||[]).map(v=>[v.net,v.x,v.y,v.diameter]); +return {L, V}; +""" % B.PCB + + +def seg_dist(px, py, x1, y1, x2, y2): + dx, dy = x2 - x1, y2 - y1 + L2 = dx * dx + dy * dy + if L2 < 1e-12: + return math.hypot(px - x1, py - y1) + t = max(0.0, min(1.0, ((px - x1) * dx + (py - y1) * dy) / L2)) + return math.hypot(px - (x1 + t * dx), py - (y1 + t * dy)) + + +def seg_seg(a, b): + u"""两段的最近距离（够用的近似：四个端点到对方线段 + 相交判定）。""" + (x1, y1, x2, y2), (x3, y3, x4, y4) = a, b + d1 = (x2 - x1, y2 - y1) + d2 = (x4 - x3, y4 - y3) + den = d1[0] * d2[1] - d1[1] * d2[0] + if abs(den) > 1e-12: + t = ((x3 - x1) * d2[1] - (y3 - y1) * d2[0]) / den + s = ((x3 - x1) * d1[1] - (y3 - y1) * d1[0]) / den + if -1e-9 <= t <= 1 + 1e-9 and -1e-9 <= s <= 1 + 1e-9: + return 0.0 + return min(seg_dist(x1, y1, x3, y3, x4, y4), seg_dist(x2, y2, x3, y3, x4, y4), + seg_dist(x3, y3, x1, y1, x2, y2), seg_dist(x4, y4, x1, y1, x2, y2)) + + +class UF(object): + def __init__(self): + self.p = {} + + def find(self, a): + self.p.setdefault(a, a) + while self.p[a] != a: + self.p[a] = self.p[self.p[a]] + a = self.p[a] + return a + + def union(self, a, b): + ra, rb = self.find(a), self.find(b) + if ra != rb: + self.p[ra] = rb + + +_PLAN = [None] + + +def covered(net, ref): + u"""这只脚是不是整只落在**计划中的同网铜面**里（12V 铜墙 / 3V3 槽墙那种）。 + + ⛔ 填出来的多边形读不回来（见文件头那张表），所以这里只能拿**计划**当依据； + 计划与板上对不对得上，由 `pour_base --push` 之后的 DRC + 截图判。 + """ + if '--base' not in sys.argv: + return False + if _PLAN[0] is None: + import pour_base as PB + _PLAN[0] = [(n, r) for (_nm, n, lay, r, _p) in PB.plan() if lay in (1, 2)] + des, pin = ref.split('.', 1) + for p in json.load(io.open(PADS_JSON, encoding='utf-8')): + if p[0] != des or str(p[1]) != pin: + continue + x0, y0 = p[2] - p[4] / 2, p[3] - p[5] / 2 + x1, y1 = p[2] + p[4] / 2, p[3] + p[5] / 2 + return any(n == net and r[0] <= x0 and x1 <= r[2] and r[1] <= y0 and y1 <= r[3] + for n, r in _PLAN[0]) + return False + + +def main(): + only = None + if '--net' in sys.argv: + only = sys.argv[sys.argv.index('--net') + 1] + r = run(JS, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:400]) + lines = [(a[0], a[1], a[2] / MIL, a[3] / MIL, a[4] / MIL, a[5] / MIL, a[6] / MIL) + for a in r['result']['L']] + vias = [(a[0], a[1] / MIL, a[2] / MIL, a[3] / MIL) for a in r['result']['V']] + pads = json.load(io.open(PADS_JSON, encoding='utf-8')) + + bad, ok = [], 0 + nets = sorted(set(p[7] for p in pads if p[7])) + for net in nets: + if only and net != only: + continue + np_ = [p for p in pads if p[7] == net] + if len(np_) < 2: + continue + segs = [l for l in lines if l[0] == net] + vs = [v for v in vias if v[0] == net] + uf = UF() + items = [] # (kind, layer, geom) + for i, l in enumerate(segs): + items.append(('s', l[1], (l[2], l[3], l[4], l[5]), l[6] / 2.0, ('s', i))) + for i, v in enumerate(vs): # 过孔穿两层，层记 None + items.append(('v', None, (v[1], v[2]), v[3] / 2.0, ('v', i))) + for i, p in enumerate(np_): + # ⚠ 通孔焊盘（layer 12）两层都有铜，和过孔一样层记 None —— 不这么记的话， + # 接在 L4 上的线被判成「不挨着」（底板 J1 / C2 / C3 / J26 / J27 / J33 全部误报孤立） + items.append(('p', None if p[6] == 12 else p[6], (p[2], p[3], p[4], p[5]), 0.0, ('p', i))) + for i in range(len(items)): + for j in range(i + 1, len(items)): + a, b = items[i], items[j] + if a[1] is not None and b[1] is not None and a[1] != b[1]: + continue + d = None + if a[0] == 's' and b[0] == 's': + d = seg_seg(a[2], b[2]) - a[3] - b[3] + elif a[0] == 's' and b[0] in 'vp' or b[0] == 's' and a[0] in 'vp': + s, o = (a, b) if a[0] == 's' else (b, a) + if o[0] == 'v': + d = seg_dist(o[2][0], o[2][1], *s[2]) - s[3] - o[3] + else: # 焊盘：按矩形近似，取盘心到线段的距离减半对角 + d = (seg_dist(o[2][0], o[2][1], *s[2]) - s[3] + - max(o[2][2], o[2][3]) / 2.0) + else: # 过孔/焊盘之间 + ax = a[2][0] if a[0] == 'v' else a[2][0] + ay = a[2][1] if a[0] == 'v' else a[2][1] + bx, by = b[2][0], b[2][1] + ra = a[3] if a[0] == 'v' else max(a[2][2], a[2][3]) / 2.0 + rb = b[3] if b[0] == 'v' else max(b[2][2], b[2][3]) / 2.0 + d = math.hypot(ax - bx, ay - by) - ra - rb + if d is not None and d <= TOUCH: + uf.union(a[4], b[4]) + roots = set(uf.find(('p', i)) for i in range(len(np_))) + alone = [np_[i][0] + '.' + np_[i][1] for i in range(len(np_)) + if uf.find(('p', i)) == ('p', i) + and not any(uf.find(x) == ('p', i) for x in uf.p if x != ('p', i))] + if net in PLANE: + alone = [a for a in alone if not covered(net, a)] + if alone: + bad.append((net, u'靠铜面成网，但这些脚一根铜都不挨：' + ' '.join(alone))) + else: + ok += 1 + elif len(roots) > 1: + bad.append((net, u'铜分成 %d 块（%d 只脚）%s' + % (len(roots), len(np_), + u'；孤立脚: ' + ' '.join(alone) if alone else ''))) + else: + ok += 1 + print(u'板上读回：%d 段铜 / %d 过孔；判了 %d 个网' % (len(lines), len(vias), ok + len(bad))) + print(u'[OK] 全连通 %d 个' % ok) + if bad: + print(u'[X] 没连通 %d 个：' % len(bad)) + for n, m in bad: + print(u' %-10s %s' % (n, m)) + else: + print(u'[OK] **所有网络在板上都是一整块铜**') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/dev_edge.py b/.claude/r2/dev_edge.py new file mode 100644 index 0000000..453d391 --- /dev/null +++ b/.claude/r2/dev_edge.py @@ -0,0 +1,118 @@ +# -*- coding: utf-8 -*- +u"""建「PCI-E x4 金手指」器件（R2 刀片的 `J1`）。 + +金手指不是买来的连接器，是**刀片 PCB 板边本身**： + · 符号借用系统库 `PCIE-064-02-F-D-TH`（Samtec x4 插座）的 64 脚符号 —— + 脚号正好就是 `A1~A32` / `B1~B32`，和 CEM 的命名一一对应，不用自己画。 + · 封装是**自建金手指**（64 个板边焊盘，1.0 mm 间距，正反两面）， + ⛔ **还没画**，属于 M4 的活 —— 但 **T3 已定（2026-09-08）**：做斜边 20°/1.0 mm、 + 金手指区**电镀硬金**（不是 ENIG）、板厚 1.6 mm，所以前置条件已经清空。 + ⚠ 斜边吃掉手指前端约 1.0 mm 的镀层 ⇒ 金手指长度按 PCIe CEM 画，别自己缩短。 + · 不进 BOM（没有东西可买），进 PCB（要出板边焊盘）。 + +用法: + /c/Python314/python .claude/r2/dev_edge.py # 只查 + /c/Python314/python .claude/r2/dev_edge.py --push # 建器件 + 写回 eda-parts.json +""" +import io +import json +import os +import sys +import time + +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +LIB_ME = '543725e8f0454017a5691e7e570aeef6' # 个人库 +LIB_SYS = '0819f05c4eef4c71ace90d822a990e87' # 立创系统库 +DEV_NAME = 'PCIE-X4-EDGE-64P' +SYM_SRC = '55d057aaabd3475584df3055eba749d6' # PCIE-064-02-F-D-TH 的符号（A1~A32/B1~B32） +PARTS_JSON = os.path.join(os.path.dirname(HERE), 'eda-parts.json') + +DESC = (u'PCI-E x4 金手指（刀片板边，非采购件）。符号借用 Samtec PCIE-064-02-F-D-TH，' + u'脚号 A1~A32/B1~B32 对齐 PCIe CEM。封装待建（M4）。') + + +def call(js, timeout=120): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:600]) + return r['result'] + + +def find_dev(retries=6): + for _i in range(retries): + r = call("const r = await eda.lib_Device.search('%s', '%s', undefined, undefined, 20, 1);" + "return (r||[]).map(d => [d.uuid, d.name, d.libraryUuid]);" % (DEV_NAME, LIB_ME)) + for u, n, _l in r: + if n == DEV_NAME: + return u + time.sleep(2) + return None + + +def push(): + dev = find_dev(retries=2) + if not dev: + # ⚠️ create() 返回 undefined 但器件已建（skill §9y），判据是 search + call("try { await eda.lib_Device.create('%s', '%s', undefined, " + "{symbol: {uuid: '%s', libraryUuid: '%s'}}, %s); } catch (e) {}" + "return 1;" % (LIB_ME, DEV_NAME, SYM_SRC, LIB_SYS, + json.dumps(DESC, ensure_ascii=False)), timeout=60) + dev = find_dev() + assert dev, u'器件建了但搜不到' + print(u'器件已建: %s %s' % (DEV_NAME, dev)) + else: + print(u'器件已存在: %s %s' % (DEV_NAME, dev)) + + prop = {'name': DEV_NAME, 'designator': 'J?', + 'addIntoBom': 'no', 'addIntoPcb': 'yes', + 'manufacturer': '-', 'manufacturerId': 'PCB edge finger', + 'otherProperty': {'Note': u'刀片板边金手指，不采购；封装待建（M4）'}} + call("try { await eda.lib_Device.modify('%s', '%s', undefined, undefined, undefined, undefined, %s); }" + "catch (e) {} return 1;" + % (dev, LIB_ME, json.dumps(prop, ensure_ascii=False)), timeout=60) + + g = call("const d = await eda.lib_Device.get('%s', '%s'); return {assoc: d.association, prop: d.property};" + % (dev, LIB_ME)) + a, p = g['assoc'], g['prop'] + sym = (a.get('symbol') or {}).get('uuid') + print(u'读回：符号 %s / 封装 %s / designator %s / BOM %s / PCB %s' + % (sym, (a.get('footprint') or {}).get('uuid'), + p.get('designator'), p.get('addIntoBom'), p.get('addIntoPcb'))) + # ⚠ create() 会把系统库符号**复制一份进个人库**（uuid 变了，不是引用）， + # 所以判据是「有符号 + 放下去 64 个脚对得上」，不是「uuid 等于源符号」。 + assert sym, u'符号没挂上' + if sym != SYM_SRC: + print(u' （符号已复制进个人库：%s ← %s）' % (sym, SYM_SRC)) + if p.get('addIntoBom') != 'no': + print(u'⚠ addIntoBom 仍是 %s —— 和 MI8-KEY-PAD 一样，BOM 字段 API 改不动，' + u'要在客户端手工改（否则 BOM 里会多一颗买不到的东西）' % p.get('addIntoBom')) + + d = json.load(io.open(PARTS_JSON, encoding='utf-8')) + d['parts'][DEV_NAME] = { + 'name': DEV_NAME, 'uuid': dev, 'lib': LIB_ME, + 'lib_note': u'个人库，不是系统库 —— 放元件时 libraryUuid 要用这个', + 'symbol': sym, + 'role': (u'R2 刀片 J1：PCI-E x4 金手指（板边本身，不采购）。符号借自系统库 ' + u'PCIE-064-02-F-D-TH，脚号 A1~A32 在左列（自上而下，pitch 10）、' + u'B1~B32 在右列，与 PCIe CEM 命名一一对应。' + u'⛔ 封装还没建（64 个板边焊盘，1.0 mm 间距，正反两面），等 T3 定了斜边再画，属 M4。'), + } + with io.open(PARTS_JSON, 'w', encoding='utf-8') as f: + f.write(json.dumps(d, ensure_ascii=False, indent=1)) + print(u'已写回 eda-parts.json') + return dev + + +if __name__ == '__main__': + if '--push' in sys.argv: + push() + else: + print(u'当前: %s' % find_dev(retries=1)) diff --git a/.claude/r2/dump_page.py b/.claude/r2/dump_page.py new file mode 100644 index 0000000..a007fa2 --- /dev/null +++ b/.claude/r2/dump_page.py @@ -0,0 +1,89 @@ +# -*- coding: utf-8 -*- +u"""把一页原理图的全部图元读回成 JSON（跨工程搬版图用）。 + + /c/Python314/python .claude/r2/dump_page.py + +读回的六类： + parts [位号, 器件名, 子部件, x, y, rot, mirror, uuid, libraryUuid, 引脚] + 引脚 = [[脚号, 脚名, x, y], ...] ← 跨工程重放时的断言基准（§6c：方向表一张都别信） + wires [[x1,y1],[x2,y2]] ← **按 §5 的端点对解析**，不是折线 + flags [种类, 网名, x, y, rot] 种类 = Power / Ground（按符号名判） + ports [dir, 网名, x, y, rot] dir 来自 getState_Component().name（§8b 尾） + texts [x, y, 内容, rot, 字号] + rects/polys 只数个数（本项目 P2 没有） + +⚠️ 只读，不写。切工程会改变客户端的活动工程，跑完记得切回去。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +JS = u""" +await eda.dmt_Project.openProject('%(proj)s'); +await new Promise(r => setTimeout(r, 2500)); +await eda.dmt_EditorControl.openDocument('%(page)s'); +await new Promise(r => setTimeout(r, 2500)); +const cur = await eda.dmt_Schematic.getCurrentSchematicPageInfo(); + +const parts = [], flags = [], ports = []; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + const t = c.getState_ComponentType(); + const x = c.getState_X(), y = c.getState_Y(), r = c.getState_Rotation(); + const comp = c.getState_Component() || {}; + if (t === 'part') { + const pins = (await c.getAllPins()).map(p => [p.getState_PinNumber(), + (p.getState_PinName ? p.getState_PinName() : ''), + Math.round(p.getState_X()), Math.round(p.getState_Y())]); + parts.push([c.getState_Designator(), comp.name, c.getState_SubPartName(), + x, y, r, !!c.getState_Mirror(), comp.uuid, comp.libraryUuid, pins]); + } else if (t === 'netflag') { + flags.push([comp.name, c.getState_Net(), x, y, r]); + } else if (t === 'netport') { + ports.push([comp.name, c.getState_Net(), x, y, r]); + } +} + +const wires = []; +for (const w of await eda.sch_PrimitiveWire.getAll()) { + const p = w.getState_Line(); + for (let i = 0; i + 1 < p.length; i += 2) wires.push([p[i], p[i + 1]]); +} + +const texts = []; +for (const t of await eda.sch_PrimitiveText.getAll()) { + texts.push([t.getState_X(), t.getState_Y(), t.getState_Content(), + t.getState_Rotation(), t.getState_FontSize()]); +} + +return {page: cur && cur.name, parts, flags, ports, wires, texts, + nRect: (await eda.sch_PrimitiveRectangle.getAll()).length, + nPoly: (await eda.sch_PrimitivePolygon.getAll()).length}; +""" + + +def main(): + proj, page, out = sys.argv[1], sys.argv[2], sys.argv[3] + r = run(JS % {'proj': proj, 'page': page}, timeout=300) + if not r.get('success'): + raise SystemExit(json.dumps(r, ensure_ascii=False)[:600]) + d = r['result'] + io.open(out, 'w', encoding='utf-8').write( + json.dumps(d, ensure_ascii=False, indent=1)) + print(u'页 %s：元件 %d / 导线段 %d / 旗 %d / 端口 %d / 文字 %d / 矩形 %d / 多边形 %d' + % (d['page'], len(d['parts']), len(d['wires']), len(d['flags']), + len(d['ports']), len(d['texts']), d['nRect'], d['nPoly'])) + print(u'-> ' + out) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/fp_edge.py b/.claude/r2/fp_edge.py new file mode 100644 index 0000000..318ce34 --- /dev/null +++ b/.claude/r2/fp_edge.py @@ -0,0 +1,373 @@ +# -*- coding: utf-8 -*- +u"""自建「PCI-E x4 金手指」封装 —— R2 刀片 `J1`（`PCIE-X4-EDGE-64P`）的板边本身。 + + /c/Python314/python .claude/r2/fp_edge.py # 只打印几何 + 自检 + /c/Python314/python .claude/r2/fp_edge.py --push # 建/重画封装 + 挂到器件上 + 读回校验 + +## 几何出处（**不是凭记忆写的**，M2d 的教训） + +主源：KiCad 官方封装库 `Connector_PCBEdge.pretty/BUS_PCIexpress_x4.kicad_mod` +（其 descr 注明摘自 PCI-E CEM 的 add-in card edge-finger 图）。逐条交叉核对过： + +| 项 | 本封装 | 交叉核对 | +|---|---:|---| +| 间距 | **1.00 mm** | CEM / 立创资料 / KiCad 一致 | +| 手指宽 | **0.70 mm**（净距 0.30） | 同上 | +| 手指长 | **4.30 mm** | 中文资料常写 4.0，KiCad 4.3，同量级 | +| 指尖到板边 | **1.30 mm** | multi-cb 给 PCIe 推荐 1.4；另一处给 0.6~1.5 窗口 ⇒ 1.3 在窗口内 | +| 缺口（key） | 11 与 12 号针之间，宽 **1.9**，深 **7.45**，口部两个 0.5×45° 导入角 | KiCad x1 / x4 两个封装完全一致 | +| A1 / B31 短指 | 长 **3.2**，指尖再退 **1.10** | CEM 的 PRSNT# 语义：**最后接触**，插到底才认在位 | +| A 排 / B 排 | A = **底层**，B = **顶层** | 同 KiCad | + +⚠ **A1 / B31 必须是短指**：本方案的在位检测就是靠它俩（底板 A1=GND、B31=PRSNT{n}#， + 刀片上短接）。做成等长指，刀片插一半就报「已插入」，而这一类错误功能测试测不出来。 + +## ⛔ T3 的「20° 斜边」在嘉立创下不了单 + +嘉立创《金手指斜边设计注意事项》写明**只有 30° 和 45°，并建议优先 30°**。 +20° 是 PCI/PCIe 的行业标准角（德系板厂 multi-cb 给的就是 20°），但**这一版要在嘉立创打**， +⇒ 方案文档 §5.3 / §21.3 的「20°/1.0 mm」改成 **30°**，深度由板厂按指长配。 +指尖留了 1.30 mm 裸边，30° 斜边吃不到镀层（这正是那 1.3 mm 的用途）。 + +嘉立创另外两条硬要求，本封装已满足 / 已记： + · **金手指处必须开通窗**（阻焊开窗）—— 焊盘自带开窗，且本封装不在指区放任何丝印。 + · 斜边板单片长宽 ≥ 50 mm —— 刀片 98×76，过。 + +## 板框：缺口画在封装里，刀片外框在 M4 的 PCB 里画 + +封装在 **BOARD_OUTLINE(11)** 层只出**缺口那一段**（两条竖线 + 顶部半圆 + 口部两个导入角）， +刀片 98×76 的外框在 PCB 文档里画，**底边要在缺口口部断开**，两段拼成一个闭合外框。 +⇒ 缺口忘不掉（跟着封装走），而外框尺寸仍归 PCB。断点坐标从本模块的 `notch_mouth()` 取， +不要手抄。 + +## 坐标系 + +原点 = **金手指阵列 X 中心 × 卡的底边**。手指在 **+Y 方向**（板边 y=0，往板内长）。 +⚠ 实测：EasyEDA PCB / 封装编辑器里 **y 向上为正**，所以 +Y 就是「板内」。截图为证（§M4a）。 +`PIN_X[n]`（mm）是相对原点的 X；板边是 y=0。 +""" +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +LIB_ME = '543725e8f0454017a5691e7e570aeef6' # 个人库 +FP_NAME = 'EDGE-64P-P1.00_PCIE-X4-GF' +DEV_NAME = 'PCIE-X4-EDGE-64P' +MIL = 39.3700787401575 + +# ── 几何常量（mm，出处见表头）──────────────────────────────────────── +PITCH = 1.0 +FW = 0.7 # 手指宽 +LONG_L, SHORT_L = 4.3, 3.2 +EDGE_CLR = 1.3 # 指尖到卡底边 +SHORT_BACK = LONG_L - SHORT_L # 短指指尖再退 1.1 +NOTCH_W, NOTCH_D = 1.9, 7.45 # 缺口宽 / 深（自板边算） +LEAD_IN = 0.5 # 缺口口部 45° 导入角 +N_PER_SIDE = 32 +SHORT_PINS = ('A1', 'B31') # PRSNT#：最后接触 +GAP_AFTER = 11 # 11 号针之后空两格（缺口） +ARC_SEG = 12 # 缺口顶部半圆用几段折线近似（见 outline_segments 的说明） + + +def _x_raw(n): + u"""第 n 号针在「以 1 号针为 0」的原始坐标（mm）。""" + return (n - 1) + (2.0 if n > GAP_AFTER else 0.0) + + +X_CENTER = (_x_raw(1) + _x_raw(N_PER_SIDE)) / 2.0 # 16.5 +PIN_X = dict() +for _n in range(1, N_PER_SIDE + 1): + PIN_X['A%d' % _n] = PIN_X['B%d' % _n] = round(_x_raw(_n) - X_CENTER, 4) + +NOTCH_CX = round((_x_raw(GAP_AFTER) + _x_raw(GAP_AFTER + 1)) / 2.0 - X_CENTER, 4) # -5.0 +LAYER = {'A': 2, 'B': 1} # A 排 = 底层，B 排 = 顶层 + + +def pad_geom(pin): + u"""(x, y_center, w, h) mm。**y 为正 = 往板内**（实测：PCB 编辑器里 y 向上为正， + 见 §M4a 的截图判据；板边在 y=0，手指从板边往板内长）。""" + h = SHORT_L if pin in SHORT_PINS else LONG_L + tip = EDGE_CLR + (SHORT_BACK if pin in SHORT_PINS else 0.0) + return PIN_X[pin], (tip + h / 2.0), FW, h + + +def notch_mouth(): + u"""缺口在板边(y=0)上的两个断点 x（mm）—— 刀片外框底边要在这两点断开。""" + half = NOTCH_W / 2.0 + LEAD_IN + return round(NOTCH_CX - half, 4), round(NOTCH_CX + half, 4) + + +def outline_segments(): + u"""缺口的板框线段 [(x1,y1,x2,y2), ...] + 半圆 (cx, cy, r)。""" + hw = NOTCH_W / 2.0 + ml, mr = notch_mouth() + yl = LEAD_IN # 导入角结束的高度 + top = NOTCH_D - hw # 顶部圆弧的圆心 y + segs = [(ml, 0.0, NOTCH_CX - hw, yl), # 左导入角 + (NOTCH_CX - hw, yl, NOTCH_CX - hw, top), + (mr, 0.0, NOTCH_CX + hw, yl), # 右导入角 + (NOTCH_CX + hw, yl, NOTCH_CX + hw, top)] + # 顶部半圆用 ARC_SEG 段折线近似 —— **不用 pcb_PrimitiveArc**： + # 实测它 create() 返回成功、画面上也画出来了，但 getAll()/getAllPrimitiveId() 一律 + # 返回空 ⇒ 既读不回来校验、也删不掉（重画时会越堆越多）。折线弦高误差 + # r*(1-cos(90/ARC_SEG deg)) < 0.01 mm，机械上无所谓，换来「可读回、可幂等重画」。 + pts = [] + for k in range(ARC_SEG + 1): + a = math.pi * k / ARC_SEG # 0..pi，从右到左 + pts.append((NOTCH_CX + hw * math.cos(a), top + hw * math.sin(a))) + for k in range(ARC_SEG): + segs.append((pts[k][0], pts[k][1], pts[k + 1][0], pts[k + 1][1])) + return segs + + +def selfcheck(): + assert len(PIN_X) == 64, len(PIN_X) + assert PIN_X['A1'] == -16.5 and PIN_X['A32'] == 16.5, (PIN_X['A1'], PIN_X['A32']) + assert PIN_X['A11'] == -6.5 and PIN_X['A12'] == -3.5, u'11/12 之间必须空两格' + assert NOTCH_CX == -5.0, NOTCH_CX + ml, mr = notch_mouth() + assert round(mr - ml, 4) == 2.9, (ml, mr) + # 缺口的直段（不含口部导入角）到相邻两指的铜边距。口部的 45° 导入角在 y=0~+0.5， + # 而指尖在 y=+1.3 才开始，两者在 Y 上错开 0.8 ⇒ 只需校核直段的 X 间距。 + hw = NOTCH_W / 2.0 + cl = round(NOTCH_CX - hw - (PIN_X['A11'] + FW / 2.0), 4) + cr = round((PIN_X['A12'] - FW / 2.0) - (NOTCH_CX + hw), 4) + assert cl == cr == 0.2, u'缺口到 11/12 号指的铜边距变了: %s / %s' % (cl, cr) + assert EDGE_CLR - LEAD_IN >= 0.8, u'口部导入角会切进指尖' + for p in SHORT_PINS: + x, y, w, h = pad_geom(p) + # 远端（板内那头）必须和长指齐平，指尖（板边那头）必须比长指退 SHORT_BACK + assert abs((y + h / 2.0) - (EDGE_CLR + LONG_L)) < 1e-9, u'%s 的远端没对齐' % p + assert abs((y - h / 2.0) - (EDGE_CLR + SHORT_BACK)) < 1e-9, p + # 长指本身 + x, y, w, h = pad_geom('B1') + assert abs((y - h / 2.0) - EDGE_CLR) < 1e-9, u'长指指尖不在 1.3' + # 缺口比手指深，否则插槽的防呆筋顶到板子 + assert NOTCH_D > EDGE_CLR + LONG_L, u'缺口比手指还浅' + return True + + +def mil(v): + return round(v * MIL, 4) + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def _find_once(name=FP_NAME): + r = call("const r = await eda.lib_Footprint.search('%s', '%s', undefined, 20, 1);" + "return (r||[]).map(f => [f.uuid, f.name]);" % (name, LIB_ME)) + for u, n in r: + if n == name: + return u + return None + + +def find_fp(retries=6): + import time + for _i in range(retries): + u = _find_once() + if u: + return u + time.sleep(2) + return None + + +def body_js(): + u"""画封装的 JS 语句串。""" + js = [] + # 64 个手指。助焊(锡膏)扩展给一个大负数，想让钢网在金手指区不开口。 + # ⚠ 实测客户端把它**夹到 -1.37795 mil（-0.035 mm）**，关不死 ⇒ 光靠封装做不到， + # 「金手指区钢网不开口」必须在下单时另外说明（同 fp_keypad.py 那颗接触盘）。 + paste = "{topPasteMask:%s,bottomPasteMask:%s}" % (mil(-FW / 2.0), mil(-FW / 2.0)) + for row in ('A', 'B'): + for n in range(1, N_PER_SIDE + 1): + pin = '%s%d' % (row, n) + x, y, w, h = pad_geom(pin) + js.append("await eda.pcb_PrimitivePad.create(%d,'%s',%s,%s,0,['RECT',%s,%s,0]," + "undefined,null,undefined,undefined,undefined,undefined,undefined," + "undefined,%s);" + % (LAYER[row], pin, mil(x), mil(y), mil(w), mil(h), paste)) + # 板框层：缺口（含顶部折线半圆） + segs = outline_segments() + for x1, y1, x2, y2 in segs: + js.append("await eda.pcb_PrimitiveLine.create('',11,%s,%s,%s,%s,%s);" + % (mil(x1), mil(y1), mil(x2), mil(y2), mil(0.15))) + # 文档层：卡底边基准线（板框由 PCB 画，这里只给一条看得见的线） + ml, mr = notch_mouth() + js.append("await eda.pcb_PrimitiveLine.create('',13,%s,%s,%s,%s,%s);" + % (mil(-X_CENTER - 2), 0, mil(ml), 0, mil(0.1))) + js.append("await eda.pcb_PrimitiveLine.create('',13,%s,%s,%s,%s,%s);" + % (mil(mr), 0, mil(X_CENTER + 2), 0, mil(0.1))) + # 顶/底装配层：手指区外框，摆位时看得见 + yb = EDGE_CLR + LONG_L + for lay in (9, 10): + for x1, y1, x2, y2 in [(-X_CENTER - FW / 2, yb, X_CENTER + FW / 2, yb), + (-X_CENTER - FW / 2, yb, -X_CENTER - FW / 2, 0), + (X_CENTER + FW / 2, yb, X_CENTER + FW / 2, 0)]: + js.append("await eda.pcb_PrimitiveLine.create('',%d,%s,%s,%s,%s,%s);" + % (lay, mil(x1), mil(y1), mil(x2), mil(y2), mil(0.1))) + # 丝印：只准放在手指区**上方**（指区里一点丝印都不能有） + # create(layer, x, y, text, fontFamily, fontSize, lineWidth, ...) + js.append("await eda.pcb_PrimitiveString.create(3,%s,%s,'NOT PCIe - PhoneRail blade'," + "undefined,%s,%s);" + % (mil(-X_CENTER), mil(yb + 1.6), mil(1.0), mil(0.15))) + return ''.join(js) + + +def push(): + fp = find_fp(retries=2) + if not fp: + desc = (u'PCI-E x4 金手指（刀片板边，非采购件）。64 指 / 1.0mm / 0.7 宽 / 长指 4.3 / ' + u'指尖离板边 1.3 / A1,B31 短指 3.2。缺口在板框层。' + u'斜边 30 度（嘉立创只有 30/45）、电镀硬金、板厚 1.6。') + call("await eda.lib_Footprint.create('%s','%s',undefined,%s);return 1;" + % (LIB_ME, FP_NAME, json.dumps(desc, ensure_ascii=False))) + fp = find_fp() + assert fp, u'封装建了但搜不到' + print(u'封装已建: %s %s' % (FP_NAME, fp)) + else: + print(u'封装已存在: %s %s，重画' % (FP_NAME, fp)) + + r = call("await eda.lib_Footprint.openInEditor('%s','%s');" + "await new Promise(r=>setTimeout(r,2500));" + "for (const k of ['pcb_PrimitivePad','pcb_PrimitiveLine','pcb_PrimitiveArc'," + " 'pcb_PrimitiveString','pcb_PrimitiveRegion']) {" + " const o = await eda[k].getAllPrimitiveId(); if (o && o.length) await eda[k].delete(o); }" + "%s" + "await eda.pcb_Document.save();" + "return {pads:(await eda.pcb_PrimitivePad.getAllPrimitiveId()).length," + " lines:(await eda.pcb_PrimitiveLine.getAllPrimitiveId()).length," + " arcs:(await eda.pcb_PrimitiveArc.getAllPrimitiveId()||[]).length};" + % (fp, LIB_ME, body_js()), timeout=300) + print(u'已画: %s' % r) + return fp + + +def verify(fp=None): + fp = fp or find_fp() + assert fp, u'找不到封装' + v = call("await eda.lib_Footprint.openInEditor('%s','%s');" + "await new Promise(r=>setTimeout(r,2000));" + "return {pads:(await eda.pcb_PrimitivePad.getAll()||[]).map(p=>({n:p.padNumber," + " x:p.x,y:p.y,layer:p.layer,pad:p.pad,exp:p.solderMaskAndPasteMaskExpansion}))," + " lines:(await eda.pcb_PrimitiveLine.getAll()||[]).map(l=>({layer:l.layer," + " x:l.startX,y:l.startY,x2:l.endX,y2:l.endY}))," + " arcs:(await eda.pcb_PrimitiveArc.getAll()||[]).map(a=>({layer:a.layer," + " x:a.startX,y:a.startY,x2:a.endX,y2:a.endY,ang:a.arcAngle}))," + " strs:(await eda.pcb_PrimitiveString.getAll()||[]).map(s=>({layer:s.layer," + " x:s.x,y:s.y,t:s.text}))};" + % (fp, LIB_ME), timeout=180) + bad = [] + got = {} + for p in v['pads']: + got[p['n']] = (round(p['x'] / MIL, 3), round(p['y'] / MIL, 3), p['layer'], p['pad']) + if len(got) != 64: + bad.append(u'焊盘数 %d != 64' % len(got)) + for row in ('A', 'B'): + for n in range(1, N_PER_SIDE + 1): + pin = '%s%d' % (row, n) + if pin not in got: + bad.append(u'缺 %s' % pin) + continue + gx, gy, glay, gpad = got[pin] + ex, ey, ew, eh = pad_geom(pin) + if abs(gx - ex) > 0.01 or abs(gy - ey) > 0.01: + bad.append(u'%s 坐标 (%.3f,%.3f) != (%.3f,%.3f)' % (pin, gx, gy, ex, ey)) + if glay != LAYER[row]: + bad.append(u'%s 在 layer %s，应为 %d' % (pin, glay, LAYER[row])) + gw, gh = round(gpad[1] / MIL, 3), round(gpad[2] / MIL, 3) + if abs(gw - ew) > 0.01 or abs(gh - eh) > 0.01: + bad.append(u'%s 尺寸 %.2fx%.2f != %.2fx%.2f' % (pin, gw, gh, ew, eh)) + nout = len([l for l in v['lines'] if l['layer'] == 11]) + want = 4 + ARC_SEG + if nout != want: + bad.append(u'板框层线段 %d != %d' % (nout, want)) + # 板框缺口必须是一条首尾相接的开口折线：只有口部两个端点落在 y=0 + ends = {} + for l in v['lines']: + if l['layer'] != 11: + continue + for kx, ky in ((l['x'], l['y']), (l['x2'], l['y2'])): + k = (round(kx / MIL, 3), round(ky / MIL, 3)) + ends[k] = ends.get(k, 0) + 1 + loose = sorted([k for k, c in ends.items() if c == 1]) + ml, mr = notch_mouth() + if len(loose) != 2 or abs(loose[0][0] - ml) > 0.01 or abs(loose[1][0] - mr) > 0.01 or abs(loose[0][1]) > 0.01 or abs(loose[1][1]) > 0.01: + bad.append(u'缺口折线不闭合/端点不在板边: %s' % (loose,)) + # 丝印一个字都不许落进指区（0 <= y <= EDGE_CLR+LONG_L 就是指区）。 + # 封装名那一条是编辑器自带的属性串，不算丝印。 + for st in v.get('strs', []): + sy = st['y'] / MIL + if st.get('t') in (FP_NAME, None): + continue + if st['layer'] in (3, 4) and -0.01 <= sy <= EDGE_CLR + LONG_L + 0.01: + bad.append(u'丝印 "%s" 落进金手指区 (y=%.2f)' % (st.get('t'), sy)) + ys = [got[p][1] for p in got] + print(u'读回: %d 焊盘 / %d 线 / %d 弧 / %d 丝印串；y 范围 %.2f ~ %.2f' + % (len(got), len(v['lines']), len(v['arcs']), len(v.get('strs', [])), + min(ys), max(ys))) + for st in v.get('strs', []): + print(u' 串: layer=%s (%.2f,%.2f) "%s"' + % (st['layer'], st['x'] / MIL, st['y'] / MIL, st.get('t'))) + if bad: + print(u'[X] 校验不过:') + for b in bad[:20]: + print(u' ' + b) + else: + print(u'[OK] 六十四指逐脚对上（坐标 / 层 / 尺寸），板框缺口 %d 段折线、端点落在板边' % want) + return bad + + +def bind(): + u"""把封装挂到器件 PCIE-X4-EDGE-64P 上。""" + fp = find_fp() + dev = call("const r = await eda.lib_Device.search('%s','%s',undefined,undefined,20,1);" + "return (r||[]).map(d=>[d.uuid,d.name]);" % (DEV_NAME, LIB_ME)) + du = None + for u, n in dev: + if n == DEV_NAME: + du = u + assert du, u'找不到器件 %s' % DEV_NAME + # ⚠ modify 的位置参数是 (uuid, lib, name, classification, association, description, property) + # —— 早先 dev_edge.py 把 association 写到了第 6 位（description），所以「改不动」。 + call("await eda.lib_Device.modify('%s','%s',undefined,undefined," + "{footprint:{uuid:'%s',libraryUuid:'%s'}});return 1;" + % (du, LIB_ME, fp, LIB_ME), timeout=120) + # 顺手把「进 BOM」关掉：property.addIntoBom 是 **boolean**，dev_edge.py 传的是字符串 'no' + call("await eda.lib_Device.modify('%s','%s',undefined,undefined,undefined,undefined," + "{addIntoBom:false,addIntoPcb:true});return 1;" % (du, LIB_ME), timeout=120) + g = call("const d = await eda.lib_Device.get('%s','%s');" + "return {fp:(d.association&&d.association.footprint)||null," + " sym:(d.association&&d.association.symbol)||null," + " bom:(d.property&&d.property.addIntoBom)};" % (du, LIB_ME)) + print(u'器件关联: %s' % json.dumps(g, ensure_ascii=False)) + return g + + +if __name__ == '__main__': + selfcheck() + print(u'自检过。X 中心 %.2f，缺口中心 %.2f，口部断点 %s' % (X_CENTER, NOTCH_CX, notch_mouth())) + for p in ('A1', 'B1', 'A11', 'A12', 'B31', 'A32'): + print(u' %-4s x=%7.3f y=%7.3f %.2fx%.2f' % ((p,) + pad_geom(p))) + if '--push' in sys.argv: + fp = push() + verify(fp) + bind() + elif '--verify' in sys.argv: + verify() diff --git a/.claude/r2/grid_snap.py b/.claude/r2/grid_snap.py new file mode 100644 index 0000000..7dcf879 --- /dev/null +++ b/.claude/r2/grid_snap.py @@ -0,0 +1,143 @@ +# -*- coding: utf-8 -*- +u"""把每个器件微调 ≤ ±0.125 mm，让它的焊盘尽量落在 **0.25 mm 布线网格**上（M7）。 + + /c/Python314/python .claude/r2/grid_snap.py # 从板上抓焊盘，写 _blade_pad_offsets.json + /c/Python314/python .claude/r2/grid_snap.py --report # 只看现状（板上有多少焊盘在格点上） + +## 为什么值得做 + +`router.py` 是 0.25 mm 网格 A*，焊盘中心几乎都不在格点上，所以每个焊盘要先长一段 +**引出脚**（pad 中心 → 最近的可用格点）再交给 A*。M6 欠的 5 只脚全是 +**「出口被自家邻脚的引出脚封死」**（方案 §26.6）—— 引出脚是斜的、占的格点比线本身多， +0402 挨着 0402 时两根引出脚就能把中间那条通道堵死。 + +焊盘落在格点上 ⇒ 引出脚长度为 0 ⇒ 这一类堵塞直接消失。 + +## 能对齐到什么程度（不是所有封装都行） + +单个器件只有一个 (dx, dy) 可调，所以**只有焊盘间距是 0.25 的整数倍时才能全部对齐**： + +| 封装 | 焊盘间距 | 能否全对齐 | +|---|---|---| +| 0402 / 0603 / 0805 两脚件 | 两脚，间距任意 | **能**（两脚共线，一个 dx 就够）| +| QFN 0.5 / SOT-23 0.95×2 | 0.5 的倍数 | **能** | +| TSSOP-24（`U4`）| 0.65 | **不能**，只能让一排里每隔 5 只脚对齐一次（0.65×5 = 3.25）| +| BM24-50DS（`J4`）| 0.4 | 不能（0.4 不是 0.25 的倍数），取残差最小 | + +所以判据不是「全部对齐」，而是**「对齐的焊盘数显著变多、残差总和显著变小」**。 + +## ⛔ 不许动的件 + +`K1~K4`（位置由小米8 主板弹片决定，Ø1.5 的盘只容 0.5 mm 误差）、 +`J5` / `J4`（排线穿槽的落点）、`J1`（金手指，1.0 mm 间距本来就在格点上）。 +这几件的焊盘对不齐就对不齐 —— 机械优先于布线。 + +## 用法上的约定 + +存的是**焊盘相对本体中心的局部偏移**（`_blade_pad_offsets.json`），不是绝对微调量 —— +件在 `pcb_place` 里还会被「按连线就近落位」挪到别的货架位置去，绝对量当场过期， +局部偏移只跟封装和旋转角有关。`pcb_place.plan()` 最后一步拿它现算 (dx, dy)。 +**改了旋转角要重跑这个脚本**（换了位置不用）。 +""" +import io +import json +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 +import pcb_place as PL # noqa: E402 + +G = 0.25 # 和 router.py 的 G 必须一致 +MAX_D = G / 2.0 # 单件最多挪半格 +OUT = os.path.join(HERE, '_blade_pad_offsets.json') +PADS = os.path.join(HERE, '_blade_pads.json') +# 机械锚定，不许为了布线挪 +FROZEN = set(PL.TOP_ONLY) | {'J5', 'J4'} + + +def board_pos(): + u"""从板上读回每个器件的中心（mm）—— 焊盘的局部偏移要拿它来减。""" + r = run("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "return (await eda.pcb_PrimitiveComponent.getAll()).map(" + " c=>[c.designator, c.x, c.y, c.rotation, c.layer]);" % B.PCB, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + return {a[0]: (a[1] / B.MIL, a[2] / B.MIL) for a in r['result']} + + +def pads_by_ref(): + d = json.load(io.open(PADS, encoding='utf-8')) + out = {} + for p in d: + out.setdefault(p[0], []).append((p[2], p[3])) + return out + + +def resid(v, d): + u"""v 挪 d 之后离最近格点的距离。""" + t = (v + d) / G + return abs(t - round(t)) * G + + +def best_delta(vals): + u"""在 [-MAX_D, MAX_D] 里扫一个偏移，使这一列坐标的残差和最小。 + + ⚠ 用扫描不用解析解：焊盘间距不是 0.25 倍数时（TSSOP 0.65 / BM24 0.4） + 没有解析最优，扫描 1 µm 一步在这里足够快（83 件 × 251 步）。 + """ + best, bd = None, 0.0 + n = int(round(MAX_D * 1000)) + for k in range(-n, n + 1): + d = k / 1000.0 + s = sum(resid(v, d) for v in vals) + if best is None or s < best - 1e-9: + best, bd = s, d + return round(bd, 3), best + + +def on_grid(v, tol=0.02): + t = v / G + return abs(t - round(t)) * G <= tol + + +def main(): + u"""把每个器件的焊盘**局部偏移**（相对本体中心）算出来存盘。 + + ⚠ 存的是**局部偏移**不是绝对微调量：`pcb_place` 里件还会被 + 「按连线就近落位」挪到别的货架位置去，绝对微调量当场就过期了， + 而局部偏移只跟封装和旋转角有关，挪到哪儿都还成立。 + """ + pads = pads_by_ref() + pos = board_pos() + n_before = sum(1 for ps in pads.values() for p in ps if on_grid(p[0]) and on_grid(p[1])) + n_tot = sum(len(ps) for ps in pads.values()) + print(u'现状：%d / %d 个焊盘在 0.25 网格上' % (n_before, n_tot)) + if '--report' in sys.argv: + return + out = {} + for ref, ps in sorted(pads.items()): + if ref in FROZEN or ref not in pos: + continue + cx, cy = pos[ref] + out[ref] = [[round(x - cx, 4), round(y - cy, 4)] for x, y in ps] + io.open(OUT, 'w', encoding='utf-8').write(json.dumps(out, ensure_ascii=False)) + gain = 0 + for ref, offs in out.items(): + cx, cy = pos[ref] + dx = best_delta([cx + o[0] for o in offs])[0] + dy = best_delta([cy + o[1] for o in offs])[0] + gain += (sum(1 for o in offs if on_grid(cx + o[0] + dx) and on_grid(cy + o[1] + dy)) + - sum(1 for o in offs if on_grid(cx + o[0]) and on_grid(cy + o[1]))) + print(u'已写 %s（%d 件的局部焊盘偏移）；按当前摆位估算能把对齐焊盘从 %d 提到 %d' + % (os.path.basename(OUT), len(out), n_before, n_before + gain)) + print(u'⇒ `pcb_place.plan()` 会用它现算微调量（只调货架排布器摆的件），重跑 --push 生效') + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/hand_check.py b/.claude/r2/hand_check.py new file mode 100644 index 0000000..142abf9 --- /dev/null +++ b/.claude/r2/hand_check.py @@ -0,0 +1,120 @@ +# -*- coding: utf-8 -*- +u"""手工补线的净距校验：给一组 (layer, x0,y0,x1,y1, w, net) 段和 (x,y,net) 孔， +按 `_m6_board_copper.json` + `_blade_pads.json` 算精确净距（判据 0.15）。 + from hand_check import check; check(segs, vias) +""" +import io, json, math, os +HERE = os.path.dirname(os.path.abspath(__file__)) +CLR = 0.15 +VIA_R = 0.3 +PADS = json.load(io.open(os.path.join(HERE, '_blade_pads.json'), encoding='utf-8')) +CP = json.load(io.open(os.path.join(HERE, '_m6_board_copper.json'), encoding='utf-8')) +SEGS = [tuple(s) for s in CP['segs']] +VIAS = [tuple(v) for v in CP['vias']] + + +def d_pt_seg(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0 if L2 == 0 else max(0, min(1, ((px - x0) * dx + (py - y0) * dy) / L2)) + return math.hypot(px - (x0 + dx * t), py - (y0 + dy * t)) + + +def d_seg_seg(a, b): + (x0, y0, x1, y1), (u0, v0, u1, v1) = a, b + # 相交？ + def cross(ax, ay, bx, by): return ax * by - ay * bx + r = (x1 - x0, y1 - y0); s = (u1 - u0, v1 - v0) + den = cross(r[0], r[1], s[0], s[1]) + if abs(den) > 1e-12: + t = cross(u0 - x0, v0 - y0, s[0], s[1]) / den + u = cross(u0 - x0, v0 - y0, r[0], r[1]) / den + if 0 <= t <= 1 and 0 <= u <= 1: + return 0.0 + return min(d_pt_seg(x0, y0, *b), d_pt_seg(x1, y1, *b), d_pt_seg(u0, v0, *a), d_pt_seg(u1, v1, *a)) + + +def d_seg_rect(seg, rc): + u"""线段到轴对齐矩形的距离（近似：矩形四边）。""" + x0, y0, x1, y1 = rc + if d_pt_seg((x0 + x1) / 2, (y0 + y1) / 2, *seg) < 1e-9: + return 0.0 + edges = [(x0, y0, x1, y0), (x1, y0, x1, y1), (x1, y1, x0, y1), (x0, y1, x0, y0)] + d = min(d_seg_seg(seg, e) for e in edges) + # 线段端点在矩形内？ + for (px, py) in ((seg[0], seg[1]), (seg[2], seg[3])): + if x0 <= px <= x1 and y0 <= py <= y1: + return 0.0 + return d + + +def pad_rect(p): + return (p[2] - p[4] / 2, p[3] - p[5] / 2, p[2] + p[4] / 2, p[3] + p[5] / 2) + + +def check(new_segs, new_vias, extra_segs=(), extra_vias=(), ignore_segs=()): + u"""返回违规清单。extra_* 是同批次里别的新线（互相也要查）；ignore_segs 是准备删掉的旧线（按坐标匹配）。""" + bad = [] + old_segs = [s for s in SEGS if not any(abs(s[1]-g[1])<1e-3 and abs(s[2]-g[2])<1e-3 and abs(s[3]-g[3])<1e-3 and abs(s[4]-g[4])<1e-3 for g in ignore_segs)] + old_vias = list(VIAS) + allsegs = old_segs + list(extra_segs) + allvias = old_vias + list(extra_vias) + for ns in new_segs: + l, x0, y0, x1, y1, w, net = ns + seg = (x0, y0, x1, y1) + for s in allsegs: + if s[0] != l or s[6] == net: + continue + d = d_seg_seg(seg, s[1:5]) - w / 2 - s[5] / 2 + if d < CLR - 1e-6: + bad.append(u'段 %s L%d 与线 %s (%.2f,%.2f)-(%.2f,%.2f) 净距 %.3f' % (net, l, s[6], s[1], s[2], s[3], s[4], d)) + for v in allvias: + if v[2] == net: + continue + d = d_pt_seg(v[0], v[1], *seg) - VIA_R - w / 2 + if d < CLR - 1e-6: + bad.append(u'段 %s L%d 与孔 %s (%.2f,%.2f) 净距 %.3f' % (net, l, v[2], v[0], v[1], d)) + for p in PADS: + if p[6] != l or p[7] == net: + continue + d = d_seg_rect(seg, pad_rect(p)) - w / 2 + if d < CLR - 1e-6: + bad.append(u'段 %s L%d 与焊盘 %s.%s(%s) 净距 %.3f' % (net, l, p[0], p[1], p[7], d)) + for nv in new_vias: + vx, vy, net = nv + for s in allsegs: + if s[6] == net: + continue + d = d_pt_seg(vx, vy, *s[1:5]) - VIA_R - s[5] / 2 + if d < CLR - 1e-6: + bad.append(u'孔 %s (%.2f,%.2f) 与线 %s L%d (%.2f,%.2f)-(%.2f,%.2f) 净距 %.3f' % (net, vx, vy, s[6], s[0], s[1], s[2], s[3], s[4], d)) + for v in allvias: + if v[2] == net and abs(v[0]-vx) < 1e-6 and abs(v[1]-vy) < 1e-6: + continue + d = math.hypot(v[0] - vx, v[1] - vy) - 2 * VIA_R + if d < CLR - 1e-6: + bad.append(u'孔 %s (%.2f,%.2f) 与孔 %s (%.2f,%.2f) 净距 %.3f' % (net, vx, vy, v[2], v[0], v[1], d)) + for p in PADS: + if p[7] == net: + continue + r = pad_rect(p) + d = math.hypot(max(r[0] - vx, 0, vx - r[2]), max(r[1] - vy, 0, vy - r[3])) - VIA_R + if d < CLR - 1e-6: + bad.append(u'孔 %s (%.2f,%.2f) 与焊盘 %s.%s(%s) L%d 净距 %.3f' % (net, vx, vy, p[0], p[1], p[7], p[6], d)) + return bad + + +def corridor(l, x0, y0, x1, y1, w, net, margin=1.0): + u"""列出一条候选线周围 margin 内的一切（帮忙找路）。""" + seg = (x0, y0, x1, y1) + out = [] + for s in SEGS: + if s[0] == l and s[6] != net and d_seg_seg(seg, s[1:5]) < margin: + out.append(u'线 %s (%.2f,%.2f)-(%.2f,%.2f) w%.2f' % (s[6], s[1], s[2], s[3], s[4], s[5])) + for v in VIAS: + if v[2] != net and d_pt_seg(v[0], v[1], *seg) < margin: + out.append(u'孔 %s (%.2f,%.2f)' % (v[2], v[0], v[1])) + for p in PADS: + if p[6] == l and p[7] != net and d_seg_rect(seg, pad_rect(p)) < margin: + out.append(u'盘 %s.%s(%s) (%.2f,%.2f) %.2fx%.2f' % (p[0], p[1], p[7], p[2], p[3], p[4], p[5])) + return out diff --git a/.claude/r2/loop_check.py b/.claude/r2/loop_check.py new file mode 100644 index 0000000..a618caf --- /dev/null +++ b/.claude/r2/loop_check.py @@ -0,0 +1,163 @@ +# -*- coding: utf-8 -*- +u"""§7.2 四条关键回路的**机器判据**（在真实焊盘坐标上算，不看图）。 + + /c/Python314/python .claude/r2/loop_check.py + +## 为什么要有这个 + +§7.2 的四条回路（Buck 输入环路 / SW 面积 / FB 远离 SW / Kelvin 取样） +以前只能「布完线截图人眼看」。但**摆位阶段就已经决定了这四条能不能成立** —— +布线器再聪明也救不回「Cin 离 U1 12 mm」。M4c 第一版就是这么过的关： +几何自检（重叠 / 越框 / 禁布区）全绿，四条回路破了三条，**没有任何一条检查报错**。 + +⇒ 这里把四条写成数：读 `_blade_pads.json`（`pcb_route.py --dump` 抓的真实焊盘）， +按网络名找到相关焊盘，算距离 / 面积 / 线段是否交叉。**摆位一改就跑一次。** + +⚠ 判据只覆盖**摆位**。布完线还要跑 `pcb_route.py --check`（Kelvin 那条的走线判据） + 和 `router_check.py`（净距），三个不互相替代。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +PADS = os.path.join(HERE, '_blade_pads.json') + +SW = '$1N137' # U1 的开关节点 +FB = '$1N126' # 反馈节点（R1/R2 分压 + U1 p7） +VIN = '+12V_F' # 保险之后的 12V +CIN = ['C4', 'C1', 'C2', 'C3'] # 输入电容，由近到远 + + +def pads(): + d = json.load(io.open(PADS, encoding='utf-8')) + out = [] + for r in d: + out.append({'ref': r[0], 'pin': str(r[1]), 'x': r[2], 'y': r[3], + 'w': r[4], 'h': r[5], 'layer': r[6], 'net': r[7]}) + return out + + +def sel(ps, ref=None, net=None): + return [p for p in ps + if (ref is None or p['ref'] == ref) and (net is None or p['net'] == net)] + + +def gap(a, b): + u"""两个矩形焊盘的**净距**（边到边，重叠算 0）。""" + dx = max(abs(a['x'] - b['x']) - (a['w'] + b['w']) / 2.0, 0.0) + dy = max(abs(a['y'] - b['y']) - (a['h'] + b['h']) / 2.0, 0.0) + return math.hypot(dx, dy) + + +def dist(a, b): + return math.hypot(a['x'] - b['x'], a['y'] - b['y']) + + +def cross(p1, p2, p3, p4): + u"""线段 p1p2 与 p3p4 是否相交。""" + def s(a, b, c): + return (b[0] - a[0]) * (c[1] - a[1]) - (b[1] - a[1]) * (c[0] - a[0]) + d1, d2 = s(p3, p4, p1), s(p3, p4, p2) + d3, d4 = s(p1, p2, p3), s(p1, p2, p4) + return ((d1 > 0) != (d2 > 0)) and ((d3 > 0) != (d4 > 0)) + + +def main(): + ps = pads() + bad, note = [], [] + + # ── 1. Buck 输入环路：Cin 的两个焊盘各自到 U1 最近的 VIN / GND 脚 ── + u1_vin = sel(ps, 'U1', VIN) + u1_gnd = [p for p in sel(ps, 'U1', 'GND') if p['w'] < 2] # 去掉散热焊盘 + for ref in CIN: + hot = sel(ps, ref, VIN) + gnd = sel(ps, ref, 'GND') + if not hot or not gnd: + bad.append(u'%s 找不到 %s/GND 焊盘' % (ref, VIN)) + continue + a = min(gap(hot[0], q) for q in u1_vin) + b = min(gap(gnd[0], q) for q in u1_gnd) + note.append(u' 输入环路 %-3s: VIN 边 %.2f + GND 边 %.2f = **%.2f mm**' + % (ref, a, b, a + b)) + if ref == CIN[0] and a + b > 3.0: + bad.append(u'最近的输入电容 %s 环路 %.2f mm > 3.0（§7.2 第一条）' % (ref, a + b)) + + # ── 2. SW 面积：所有 SW 焊盘的外接矩形 ── + sw = sel(ps, net=SW) + if sw: + x0 = min(p['x'] - p['w'] / 2 for p in sw) + x1 = max(p['x'] + p['w'] / 2 for p in sw) + y0 = min(p['y'] - p['h'] / 2 for p in sw) + y1 = max(p['y'] + p['h'] / 2 for p in sw) + area = (x1 - x0) * (y1 - y0) + refs = sorted(set(p['ref'] for p in sw)) + note.append(u' SW 节点: %s，外接矩形 %.1f×%.1f = **%.1f mm²**' + % ('/'.join(refs), x1 - x0, y1 - y0, area)) + u1sw = sel(ps, 'U1', SW) + l1sw = sel(ps, 'L1', SW) + if u1sw and l1sw: + g = min(gap(a, b) for a in u1sw for b in l1sw) + note.append(u' U1 的 SW 脚到 L1 的 1 脚: 焊盘净距 **%.2f mm**' % g) + if g > 2.0: + bad.append(u'U1→L1 的 SW 焊盘净距 %.2f mm > 2.0（§7.2 第二条）' % g) + if area > 60: + bad.append(u'SW 铜面积 %.1f mm² 偏大（§7.2 第二条）' % area) + + # ── 3. FB 远离 SW ── + fb = sel(ps, net=FB) + if fb and sw: + g = min(gap(a, b) for a in fb for b in sw) + who = min(((gap(a, b), a['ref']) for a in fb for b in sw))[1] + note.append(u' FB(%s) 最近的一脚到 SW: **%.2f mm**（%s）' % (FB, g, who)) + if g < 2.0: + bad.append(u'FB 离 SW 只有 %.2f mm < 2.0（§7.2 第三条）' % g) + + # ── 4. Kelvin：U3 的 9/10 脚 → Rs1 的两端，不许交叉 ── + rs = {p['pin']: p for p in sel(ps, 'Rs1')} + u3 = {p['pin']: p for p in sel(ps, 'U3')} + if '9' in u3 and '10' in u3 and '1' in rs and '2' in rs: + # 9 脚接 VO_P 那端（Rs1.1），10 脚接 $1N165 那端（Rs1.2） + assert u3['9']['net'] == rs['1']['net'], (u3['9']['net'], rs['1']['net']) + assert u3['10']['net'] == rs['2']['net'], (u3['10']['net'], rs['2']['net']) + a = (u3['9']['x'], u3['9']['y']) + b = (rs['1']['x'], rs['1']['y']) + c = (u3['10']['x'], u3['10']['y']) + d = (rs['2']['x'], rs['2']['y']) + la, lb = math.dist(a, b), math.dist(c, d) + note.append(u' Kelvin: U3.9→Rs1.1 %.2f mm / U3.10→Rs1.2 %.2f mm，%s' + % (la, lb, u'交叉' if cross(a, b, c, d) else u'不交叉')) + if cross(a, b, c, d): + bad.append(u'Kelvin 两条取样线交叉 —— 一交叉就得打过孔，§7.2 第四条明令不许') + if max(la, lb) > 8.0: + bad.append(u'Kelvin 取样线 %.2f mm 偏长' % max(la, lb)) + if abs(la - lb) > 2.0: + bad.append(u'Kelvin 两条取样线长度差 %.2f mm（应对称）' % abs(la - lb)) + + # ── 5. 顺带：输出链的两处 4 A 接口 ── + for (r1, n1, r2, n2, lim) in (('L1', 'VO', 'C6', 'VO', 3.0), + ('U2', '$1N165', 'Rs1', '$1N165', 4.0)): + a, b = sel(ps, r1, n1), sel(ps, r2, n2) + if a and b: + g = min(gap(p, q) for p in a for q in b) + note.append(u' 4 A 接口 %s(%s)→%s: 焊盘净距 **%.2f mm**' % (r1, n1, r2, g)) + if g > lim: + bad.append(u'%s→%s 的 4 A 接口 %.2f mm > %.1f' % (r1, r2, g, lim)) + + print(u'§7.2 关键回路（摆位阶段判据）') + for n in note: + print(n) + if bad: + print(u'[X] %d 条不过:' % len(bad)) + for b in bad: + print(u' ' + b) + return 1 + print(u'[OK] 四条关键回路全部达标') + return 0 + + +if __name__ == '__main__': + sys.exit(main()) diff --git a/.claude/r2/miter.py b/.claude/r2/miter.py new file mode 100644 index 0000000..fa45380 --- /dev/null +++ b/.claude/r2/miter.py @@ -0,0 +1,250 @@ +# -*- coding: utf-8 -*- +u"""把板上所有**直角走线**改成 45° 斜切（M7 收尾）。 + + /c/Python314/python .claude/r2/miter.py # 只算 + 报告，不下发 + /c/Python314/python .claude/r2/miter.py --push # 下发（自动跑到没有直角为止） + /c/Python314/python .claude/r2/miter.py --check # 下发后复查还剩几个直角 + +## 为什么可以放心做 + +45° 斜切是**只去铜、不加铜**：新的斜边完全落在原来那个直角的三角形里面， +所以任何「铜到铜」的净距只会变大不会变小 —— 不需要重跑布线器，也不会引入新的 DRC。 +（真正会变的只有线长，短一点点。） + +## 判据（哪些拐点**不**动） + +| 情形 | 为什么不动 | +|---|---| +| 拐点上坐着**过孔**或**焊盘** | 两段是各自接到孔/盘上的，切角会把它们从孔/盘上拽下来 | +| 拐点的两条腿有一条**太短** | 切角要各退 `d`，`d` 超过腿长的一半就把腿吃没了 | +| 拐点连着的段不是**恰好两条** | 三岔口（干线上挂支路）切角会切断其中一支 | +| 两段的**线宽不一样** | 斜边该用哪个宽度没有唯一答案，宽的那条会被缩窄 | + +`d` 取 `min(腿长/2, max(MIN_D, K × 线宽))` —— 线越宽切得越多，但不超过腿长的一半。 + +## ⚠ 和布线器的关系 + +`router.py --replan/--push` 会按缓存重画，**斜切会被覆盖**。 +顺序是：布线 → 下发 → 缝合过孔 → **斜切** → 铺铜。重跑布线器就要重跑这一步。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +# ⚠ `--base` 切到底板（`pcb_base` + `_base_pads.json`）；不带就是刀片，行为一字未变。 +if '--base' in sys.argv: + import pcb_base as B # noqa: E402 + PADS_JSON = os.path.join(HERE, '_base_pads.json') +else: + import pcb_blade as B # noqa: E402 + PADS_JSON = os.path.join(HERE, '_blade_pads.json') + +MIL = B.MIL +CU = (1, 2, 15, 16) +K = 1.5 # 切角深度 = K × 线宽 +MIN_D = 0.25 # 但不小于这个（mm） +W_MIX_MAX = 0.45 # 宽窄不同的拐角：两边都 <= 这个宽度才切（斜边取窄的） +EPS = 0.02 # 端点归并容差（mm） +NEAR_PAD = 0.05 # 拐点离孔/盘多近就算「坐在上面」 + +FETCH = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const L=(await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>[1,2,15,16].includes(l.layer)) + .map(l=>[l.primitiveId,l.net,l.layer,l.startX,l.startY,l.endX,l.endY,l.lineWidth]); +const V=(await eda.pcb_PrimitiveVia.getAll()||[]).map(v=>[v.x,v.y]); +return {L, V}; +""" % B.PCB + + +def fetch(): + r = run(FETCH, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:400]) + segs = [{'id': a[0], 'net': a[1], 'lay': a[2], + 'a': (a[3] / MIL, a[4] / MIL), 'b': (a[5] / MIL, a[6] / MIL), + 'w': a[7] / MIL} for a in r['result']['L']] + vias = [(a[0] / MIL, a[1] / MIL) for a in r['result']['V']] + return segs, vias + + +_REP = {} # 端点归并：代表点 -> 代表点自己（空间哈希） + + +def key(p, reset=False): + u"""端点归并成「顶点」。 + + ⛔ **不能写成 `round(x / EPS)`**：那是把坐标切成固定的桶，相差 0.011 的两个点 + 会掉进相邻的两个桶里。实测后果：同一个拐角被看成「两个各只连一条线的点」， + 两条腿各自被当成独立的段 —— 于是同一个角**切了两次**，板上留下 + 0.125 mm 的小碎块（用户在 `KPAD_VUP` / `$2N139` 那一带一眼看到）。 + ⇒ 改成**空间哈希 + 就近归并**：在 3×3 的相邻桶里找已有代表点， + 距离 <= EPS 就用它，否则自己当代表点。 + """ + global _REP + if reset: + _REP = {} + b = (int(math.floor(p[0] / EPS)), int(math.floor(p[1] / EPS))) + for dx in (-1, 0, 1): + for dy in (-1, 0, 1): + for q in _REP.get((b[0] + dx, b[1] + dy), ()): + if math.hypot(p[0] - q[0], p[1] - q[1]) <= EPS: + return q + q = (round(p[0], 4), round(p[1], 4)) + _REP.setdefault(b, []).append(q) + return q + + +def ang(p, q): + return math.atan2(q[1] - p[1], q[0] - p[0]) + + +def corners(segs, vias, pads): + u"""找出所有可切的直角拐点 -> [(拐点, 段i, 段j, d)]。""" + key((0.0, 0.0), reset=True) # 每次重建归并表（同一进程里可能跑两轮） + inc = {} + for i, s in enumerate(segs): + if s['lay'] not in CU: + continue + for p in (s['a'], s['b']): + inc.setdefault((s['lay'], key(p)), []).append(i) + blocked = set() + for (x, y) in vias: + blocked.add(key((x, y))) + for p in pads: + blocked.add(key((p[2], p[3]))) + out, stats = [], {'via_pad': 0, 'short': 0, 'branch': 0, 'width': 0, 'not90': 0} + for (lay, k), idxs in sorted(inc.items()): + if len(idxs) != 2: + if len(idxs) > 2: + stats['branch'] += 1 + continue + i, j = idxs + si, sj = segs[i], segs[j] + if si['net'] != sj['net']: + continue + # 拐点坐标（取两段共有的那一端） + pi = si['a'] if key(si['a']) == k else si['b'] + oi = si['b'] if key(si['a']) == k else si['a'] + oj = sj['b'] if key(sj['a']) == k else sj['a'] + d1 = math.hypot(oi[0] - pi[0], oi[1] - pi[1]) + d2 = math.hypot(oj[0] - pi[0], oj[1] - pi[1]) + if d1 < 1e-6 or d2 < 1e-6: + continue + da = (ang(pi, oi) - ang(pi, oj)) % (2 * math.pi) + deg = min(abs(math.degrees(da)), abs(360 - math.degrees(da))) + if abs(deg - 90.0) > 1.0: # 只切 90°（135° 已经是斜的） + stats['not90'] += 1 + continue + if k in blocked: + stats['via_pad'] += 1 + continue + w = min(si['w'], sj['w']) + if abs(si['w'] - sj['w']) > 1e-6 and max(si['w'], sj['w']) > W_MIX_MAX: + # ⛔ 宽窄不同的拐角只在**两边都不粗**时才切，斜边取**窄**的那个宽度： + # 取宽的会在窄腿两侧多出 (W−w)/2 的铜（那是**加铜**，可能破净距）； + # 取窄的等于把拐角缩到窄腿的口径 —— 对 0.8 mm 的 12V 干线就是掐脖子。 + # 实测这一档只剩金手指那 9 个「地指(0.2) 接地母线(0.4)」和一个 +3V3 引出， + # 都是小电流，缩到 0.2 无所谓。 + stats['width'] += 1 + continue + d = min(d1 / 2.0, d2 / 2.0, max(MIN_D, K * w)) + if d < 0.1: + stats['short'] += 1 + continue + out.append((pi, i, j, d, oi, oj, w)) + return out, stats + + +def apply(segs, cuts): + u"""算出改动：{段 id: 新端点} + 新增的斜边。""" + newend = {} + add = [] + for (p, i, j, d, oi, oj, w) in cuts: + s1, s2 = segs[i], segs[j] + u1 = ((oi[0] - p[0]) / math.hypot(*(oi[0] - p[0], oi[1] - p[1])), + (oi[1] - p[1]) / math.hypot(*(oi[0] - p[0], oi[1] - p[1]))) + u2 = ((oj[0] - p[0]) / math.hypot(*(oj[0] - p[0], oj[1] - p[1])), + (oj[1] - p[1]) / math.hypot(*(oj[0] - p[0], oj[1] - p[1]))) + q1 = (round(p[0] + u1[0] * d, 4), round(p[1] + u1[1] * d, 4)) + q2 = (round(p[0] + u2[0] * d, 4), round(p[1] + u2[1] * d, 4)) + newend.setdefault(i, {})[key(p)] = q1 + newend.setdefault(j, {})[key(p)] = q2 + add.append((s1['net'], s1['lay'], q1, q2, w)) + return newend, add + + +# ⚠ 不用 `modify`：它的入参形状没实测过；`delete` + `create` 是这个项目里已经用熟的路子。 +# 网名/层/线宽全从 Python 侧带过来，**不回读**（少一次 RPC，也不怕 get() 不存在）。 +PUSH = u""" +const MIL=%s, MOD=%s, ADD=%s; +let nd=0, na=0; +for (const m of MOD) { + await eda.pcb_PrimitiveLine.delete(m[0]); + await eda.pcb_PrimitiveLine.create(m[1], m[2], m[3]*MIL, m[4]*MIL, m[5]*MIL, m[6]*MIL, m[7]*MIL); + nd++; +} +for (const a of ADD) { await eda.pcb_PrimitiveLine.create(a[0], a[1], a[2]*MIL, a[3]*MIL, a[4]*MIL, a[5]*MIL, a[6]*MIL); na++; } +await eda.pcb_Document.save(); +return {mod:nd, add:na}; +""" + + +def main(): + u"""⚠ `--push` 会**自动跑多轮**：切完一轮之后，新加的两条 45° 斜边之间 + 可能又是一个直角（NE 接 NW 就是 90°），实测要 3 轮才收敛到 0。 + """ + for rnd in range(1, 8): + if not one_pass(rnd): + break + + +def one_pass(rnd=1): + segs, vias = fetch() + pads = json.load(io.open(PADS_JSON, encoding='utf-8')) + cuts, stats = corners(segs, vias, pads) + print(u'[第 %d 轮] 板上铜 %d 段 / 过孔 %d 个' % (rnd, len(segs), len(vias))) + print(u'可切的直角拐点：%d 个' % len(cuts)) + print(u'跳过：坐在孔/盘上 %d，三岔口 %d，两段线宽不同 %d，腿太短 %d（非直角拐点 %d 个不算错）' + % (stats['via_pad'], stats['branch'], stats['width'], stats['short'], stats['not90'])) + if '--push' not in sys.argv: + print(u'（没加 --push，没有下发）') + return False + if not cuts: + return False + newend, add = apply(segs, cuts) + MOD = [] + for i, ends in sorted(newend.items()): + s = segs[i] + a = list(s['a']) + b = list(s['b']) + if key(s['a']) in ends: + a = list(ends[key(s['a'])]) + if key(s['b']) in ends: + b = list(ends[key(s['b'])]) + MOD.append([s['id'], s['net'], s['lay'], a[0], a[1], b[0], b[1], s['w']]) + ADD = [[n, l, q1[0], q1[1], q2[0], q2[1], w] for (n, l, q1, q2, w) in add] + done = {'mod': 0, 'add': 0} + STEP = 40 + for k in range(0, max(len(MOD), len(ADD)), STEP): + js = PUSH % (MIL, json.dumps(MOD[k:k + STEP], ensure_ascii=False), + json.dumps(ADD[k:k + STEP], ensure_ascii=False)) + r = run(js, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:400]) + done['mod'] += r['result']['mod'] + done['add'] += r['result']['add'] + print(u' 改 %d / 加 %d' % (done['mod'], done['add'])) + print(u'第 %d 轮完成：改了 %d 段、加了 %d 段斜边' % (rnd, done['mod'], done['add'])) + return True + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/pcb_base.py b/.claude/r2/pcb_base.py new file mode 100644 index 0000000..1a5b48b --- /dev/null +++ b/.claude/r2/pcb_base.py @@ -0,0 +1,554 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB（M5，**4 层 98 × 98**，D15）：板框 + 槽阵 + 背面分区 + 安装孔 + L1 的 12V 铜。 + + /c/Python314/python .claude/r2/pcb_base.py # 只算 + 自检 + /c/Python314/python .claude/r2/pcb_base.py --outline # 画/重画板框（幂等） + /c/Python314/python .claude/r2/pcb_base.py --holes # 打安装孔 + /c/Python314/python .claude/r2/pcb_base.py --verify # 读回校验 + +2 层版（110 × 125，12V 西干道 / 3V3 槽墙 / D± 竖通道 / 刀片投影限高）整份存档在 +`archive_base2L/pcb_base.py`，那一套在这里**全部删掉**，下游引用到的会直接 AttributeError。 + +## 坐标系 + +**板左下角 = (0, 0)，x 向右、y 向上**，两面**同一套坐标、都按从上往下看**。 +x = 槽长方向，y = 五片刀片堆叠方向（J38 最南 … J34 最北）。 + +## 叠层（D15） + + L1 插槽面 —— 只有 J34~J38 五个插槽（手焊）+ 西侧 12V 大铺铜 + 每排 12V 脚一根指 + L2 +3V3 —— 整层 +3V3，不布线（2026-09-10 由 GND 改，D15） + L3 GND —— 整层地，不布线（L4 上全部器件与 D± 的参考） + L4 器件面 —— 其余 133 件（工厂只贴这一面）+ 全部信号 + D±（参考 L3）+ 3V3/5V 局部铜 + +## ⛔ 板框必须是**折线**不是导线 + +`pcb_PrimitiveLine` 在嘉立创里是**导线（铜）**：渲染、DRC、几何校验全过，客户端就是不认板框 +（方案 §27.3）。`push_outline()` 只用 `pcb_PrimitivePolyline`，并删掉层 11 上遗留的导线。 + +## 12V 指头的 x 为什么停在 34.95（不是分区草图写的 35.1） + +槽针实测（`PIN_ROWS`，J36 读回）：两排 12V 右边紧挨着的 x=35.5 是 **GND**， +焊盘左沿 35.15；35.1 只剩 0.05 mm。北排 12V 左边 x=32.5 也是 **GND**， +所以北排的指头只能从排外绕进来（L 形），不能像南排那样整块横穿。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本，先插 .claude 会 import 到 R1 那一份且不报错。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import fp_edge # noqa: E402 + +PCB = '7b9524b6aaf6f235' # BASE-PCB（r2-uuids.json） +MIL = fp_edge.MIL +LAYERS = 4 +TOP, BOTTOM = 1, 2 # EPCB_LayerId：器件只能在这两层 + +# ── 板框（mm，D15）───────────────────────────────────────────────────── +BW, BH = 98.0, 98.0 # 硬上限 98（100 正压嘉立创特价档边界，同 D14） +CORNER_R = 5.0 +CORNER_SEG = 10 +OUTLINE_W = 0.15 +EDGE_KEEP = 0.5 # 铜 / 器件到板边 + +# ── 槽阵：五槽居中，长轴沿 x，rot 0 ─────────────────────────────────────── +SLOT_PITCH = 20.32 # 刀片堆叠间距，机械定死 +SLOT_N = 5 +SLOT_ROT = 0 +SLOT_CX = 49.0 +ARRAY_CY = 49.0 +SLOT_BODY_L = 42.0 # 槽体沿 x（`PCIE-64P11L` 焊盘外框） +SLOT_BODY_W = 9.2 # 槽体沿 y +PAD_ROW_DY = 3.6 # 两排焊盘 y = 槽心 ± 3.6 +PAD_L, PAD_W = 0.7, 2.0 # 单盘 0.7(x) × 2.0(y)，脚距 1.0 +SHELL_U, SHELL_L, SHELL_W = 19.5, 3.0, 5.0 # 两端外壳 GND 盘：u = ±19.5，3(x) × 5(y) +SLOT_REFS = ('J34', 'J35', 'J36', 'J37', 'J38') + +# 针位表（u = 距槽心，板上 x = SLOT_CX + u；2026-09-10 从 J36 实测焊盘读回）。 +# S = 南排（焊盘 33~64，y = 槽心 − 3.6），N = 北排（焊盘 1~32，y = 槽心 + 3.6）。 +# 每排 32 针：u −16.5 … −6.5（11 针）+ 键位缺口 + u −3.5 … +16.5（21 针）。 +_U = [-16.5 + k for k in range(11)] + [-3.5 + k for k in range(21)] +_S = ('12V 12V 12V GND SCL SDA GND 3V3 NC NC INT ' + 'GND GND DP DM ' + 'GND ' * 15 + 'PRSNT GND').split() +_N = ('GND 12V 12V GND NC NC NC NC 3V3 3V3 EN ' + 'GND GND GND GND VDAC GND GND 5V ' + 'GND ' * 12 + '5V').split() +PIN_ROWS = {'S': dict(zip(_U, _S)), 'N': dict(zip(_U, _N))} +ROW_SIGN = {'S': -1, 'N': +1} + + +def pin_x(u): + return round(SLOT_CX + u if SLOT_ROT == 0 else SLOT_CX - u, 3) + + +def slot_y(i): + u"""槽 i（1 = 最南 = J38）的中心 y。""" + return round(ARRAY_CY + (i - (SLOT_N + 1) / 2.0) * SLOT_PITCH, 3) + + +def slot_ys(): + return [slot_y(i) for i in range(1, SLOT_N + 1)] + + +def slot_body(i): + y = slot_y(i) + return (SLOT_CX - SLOT_BODY_L / 2, y - SLOT_BODY_W / 2, + SLOT_CX + SLOT_BODY_L / 2, y + SLOT_BODY_W / 2) + + +def pad_rect(i, row, u): + u"""槽 i 某排 u 处那只针的焊盘外框。""" + x, y = pin_x(u), slot_y(i) + ROW_SIGN[row] * PAD_ROW_DY + return (x - PAD_L / 2, y - PAD_W / 2, x + PAD_L / 2, y + PAD_W / 2) + + +def shell_rects(i): + y = slot_y(i) + return [(pin_x(s * SHELL_U) - SHELL_L / 2, y - SHELL_W / 2, + pin_x(s * SHELL_U) + SHELL_L / 2, y + SHELL_W / 2) for s in (-1, 1)] + + +# 逻辑 USB 号 → 插槽位号 / 物理槽位（南起 1..5）。USB1 = J34 = 最北。 +USB_SLOT_REF = {1: 'J34', 2: 'J35', 3: 'J36', 4: 'J37', 5: 'J38'} +USB_SLOT_POS = {i: SLOT_N + 1 - i for i in range(1, SLOT_N + 1)} + + +def side_of(ref): + u"""器件放哪一面：五个插槽在 L1（TOP），其余一律 L4（BOTTOM）。""" + return TOP if ref in SLOT_REFS else BOTTOM + + +# ── 走廊：槽体之间那 11.12 mm，外加阵列两头 ──────────────────────────────── +def corridor(k): + u"""走廊 k（0 = 阵列最南，5 = 最北），整板宽。""" + y0 = 0.0 if k == 0 else slot_y(k) + SLOT_BODY_W / 2 + y1 = BH if k == SLOT_N else slot_y(k + 1) - SLOT_BODY_W / 2 + return (0.0, round(y0, 3), BW, round(y1, 3)) + + +def corridors(): + return [corridor(k) for k in range(SLOT_N + 1)] + + +def usb_corridor(i): + u"""USB i 的 D± 所在走廊：D± 在每槽**南排**，所以是槽体南侧那条。""" + return corridor(USB_SLOT_POS[i] - 1) + + +# ── 背面 L4 分区（用户 2026-09-10 确认，见 M14-4L-floorplan.png）────────────── +# 槽体正下方（`slot_body` 投影）是过孔带：槽脚在 L1，GND 打孔下 L2/L3、信号打孔下 L4，不放件。 +# 槽区 x 28~70 的走廊里只有 A4 两块，其余两条走廊留给布线。 +# ⛔ 与草图不同：**Hub 在中间槽正南（走廊 2）、mux/DAC 在正北（走廊 3）**（2026-09-10 用户拍板）。 +# U32 在底层只能 rot 270（口朝北），南去的几对要绕 U32 东侧；Hub 在走廊 3 时要绕三对、 +# 最远 D± ≈ 80 mm，放走廊 2 只绕两对、最远 ≈ 58 mm。详见 place_base 文件头。 +_C = corridors() +ZONES = { + 'A1': (0.5, 0.5, 27.5, 56.0), # 输入链 J1 F1 Q1 D1 C2/C3 Rs6 U13 + 'A2': (0.5, 57.5, 27.5, 74.0), # 辅助降压 U19 U30 L2 L3 + 'A6': (0.5, 75.5, 27.5, 97.5), # 风扇 J26 J27 + 驱动 + 'A3': (70.5, 40.0, 97.5, 97.5), # 控制 U20 ESP32 J33 … + 'A5': (70.5, 0.5, 97.5, 38.5), # 上行 J23 USB-C + U31 LDO + 'A4H': (28.5, _C[2][1], 69.5, _C[2][3]), # Hub U32 + Y1 + 去耦（走廊 2） + 'A4M': (28.5, _C[3][1], 69.5, _C[3][3]), # U35 mux + U6/U7 DAC（走廊 3） +} +H_BOTTOM = 14.0 # 背面限高：底板下 ≥ 15 mm 铜柱（C2/C3 直立电解 12 mm） + +# D± 在 L4 沿 x≈48 竖向成束（参考 L3）；I²C / VDAC 沿 x≈37。只是布线意图，这里不做禁区。 +DP_TRUNK_X = 48.0 +I2C_TRUNK_X = 37.0 + + +def via_bands(): + u"""槽体正下方的过孔带（背面摆位禁区）。""" + return [slot_body(i) for i in range(1, SLOT_N + 1)] + + +# ── ESP32 天线缺口（东板边，暂定：U20 摆位后按天线实际位置调）────────────────── +ANT_NOTCH = (90.5, 58.0, BW, 80.0) + + +def notch_rect(): + return ANT_NOTCH + + +# ── 安装孔（M3，NPTH）──────────────────────────────────────────────── +HOLE_D = 3.2 +HOLE_KEEP = 3.2 +HOLE_INSET = 4.0 +MOUNT_HOLES = { + 'H1': (HOLE_INSET, HOLE_INSET), + 'H2': (BW - HOLE_INSET, HOLE_INSET), + 'H3': (HOLE_INSET, BH - HOLE_INSET), + 'H4': (BW - HOLE_INSET, BH - HOLE_INSET), +} + + +def keepout_rects(): + u"""背面摆位禁区：过孔带 + 天线缺口（安装孔另按 HOLE_KEEP 判）。""" + return via_bands() + [ANT_NOTCH] + + +# ── L1 的 +12V 铜（9 A 干路，§6.4 断面 ≥ 8 mm）───────────────────────────── +# 主块贴西板边，东沿停在外壳 GND 盘（x 28~31）以西；每槽每排一根指头去够 12V 针。 +# 南排 12V 在 u −16.5/−15.5/−14.5，左右都没有异网针挡着（西边是外壳盘，只要不碰它的 y 段） +# ⇒ 从主块横着伸过去，上沿停在外壳盘下沿以南 V12_CLR。 +# 北排 12V 在 u −15.5/−14.5，左边 u −16.5 是 GND ⇒ 帽子在排外横过去，再从东边下一颗牙。 +V12_CLR = 0.20 # 到异网铜（规则底线 0.15，留 0.05） +V12_OUT = 2.0 # 指头伸出针排外沿多少（进走廊） +V12_MAIN = (EDGE_KEEP, EDGE_KEEP, None, BH - EDGE_KEEP) # 东沿在 l1_12v_rects() 里算 + + +def l1_12v_rects(): + u"""L1 +12V 铜：[主块] + 每槽 [南指, 北帽, 北牙]。全部同网，重叠处由铺铜合并。""" + c = V12_CLR + shell_x0 = pin_x(-SHELL_U) - SHELL_L / 2 # 外壳盘西沿 28.0 + x_main = round(shell_x0 - c, 3) + out = [(V12_MAIN[0], V12_MAIN[1], x_main, V12_MAIN[3])] + row_o = PAD_ROW_DY + PAD_W / 2 # 针排外沿 4.6 + x_e = round(pin_x(-13.5) - PAD_L / 2 - c, 3) # 东界：u −13.5 那只 GND 左沿 − 净距 + x_tooth = round(pin_x(-16.5) + PAD_L / 2 + c, 3) # 北牙西界：北排 u −16.5 GND 右沿 + 净距 + for i in range(1, SLOT_N + 1): + cy = slot_y(i) + y_shell = SHELL_W / 2 + c # 外壳盘上下沿 + 净距 + out += [ + (x_main - 0.3, round(cy - row_o - V12_OUT, 3), x_e, round(cy - y_shell, 3)), + (x_main - 0.3, round(cy + row_o + c, 3), x_e, round(cy + row_o + V12_OUT, 3)), + (x_tooth, round(cy + y_shell, 3), x_e, round(cy + row_o + c + 0.05, 3)), + ] + return out + + +# ── 下游脚本要的空壳 ───────────────────────────────────────────────────── +FLEX_W = {} +SLOT_Y = None +PHONE_ORG = None +PHONE_WH = None + + +def phone_holes(): + u"""所有层都不许压的孔：四个 M3 安装孔（`pcb_PrimitivePad`，不在 pads.json 里）。""" + return dict(MOUNT_HOLES) + + +def mill_cuts(): + return [] + + +def notch_break(): + return None + + +def corner(cx, cy, a0, a1): + pts = [] + for k in range(CORNER_SEG + 1): + a = math.radians(a0 + (a1 - a0) * k / CORNER_SEG) + pts.append((cx + CORNER_R * math.cos(a), cy + CORNER_R * math.sin(a))) + return pts + + +def outline_pts(): + u"""板框点列（逆时针，从底边左端 (r,0) 起，闭合回 (r,0)）。东边带天线缺口。""" + r = CORNER_R + pts = [(r, 0.0), (BW - r, 0.0)] + pts += corner(BW - r, r, 270, 360) + pts += [(BW, ANT_NOTCH[1]), (ANT_NOTCH[0], ANT_NOTCH[1]), + (ANT_NOTCH[0], ANT_NOTCH[3]), (BW, ANT_NOTCH[3]), + (BW, BH - r)] + pts += corner(BW - r, BH - r, 0, 90) + pts += [(r, BH)] + pts += corner(r, BH - r, 90, 180) + pts += [(0.0, r)] + pts += corner(r, r, 180, 270) + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + assert abs(out[0][0] - out[-1][0]) < 1e-9 and abs(out[0][1] - out[-1][1]) < 1e-9, \ + u'板框点列没有闭合' + return out + + +def outline_polygon(): + return outline_pts() + + +def zone_of(x, y): + for k, z in ZONES.items(): + if z[0] <= x <= z[2] and z[1] <= y <= z[3]: + return k + return None + + +def height_ok(h): + u"""背面限高（正面只有插槽）。""" + return h <= H_BOTTOM + + +def _overlap(a, b): + return a[0] < b[2] and b[0] < a[2] and a[1] < b[3] and b[1] < a[3] + + +def _gap(a, b): + u"""两个矩形的最小距离（重叠为 0）。""" + dx = max(b[0] - a[2], a[0] - b[2], 0.0) + dy = max(b[1] - a[3], a[1] - b[3], 0.0) + return math.hypot(dx, dy) + + +def selfcheck(): + bad = [] + ys = slot_ys() + for a, b in zip(ys, ys[1:]): + if abs((b - a) - SLOT_PITCH) > 1e-6: + bad.append(u'槽间距 %.3f != %.2f' % (b - a, SLOT_PITCH)) + if abs((ys[0] + ys[-1]) / 2.0 - ARRAY_CY) > 1e-6: + bad.append(u'阵列没居中: %s' % ys) + for i in range(1, SLOT_N + 1): + b = slot_body(i) + if b[0] < 2 or b[1] < 2 or b[2] > BW - 2 or b[3] > BH - 2: + bad.append(u'槽 %d 槽体 %s 贴板边 < 2 mm' % (i, b)) + # 针位表：每排 32 针，12V 共 5 针（南 3 北 2），D± 在南排 + for row in 'SN': + if len(PIN_ROWS[row]) != 32: + bad.append(u'%s 排 %d 针 != 32' % (row, len(PIN_ROWS[row]))) + n12 = [(r, u) for r in 'SN' for u, t in PIN_ROWS[r].items() if t == '12V'] + if len(n12) != 5: + bad.append(u'12V 针 %d 只 != 5' % len(n12)) + # 12V 铜：每只 12V 针都被某块指头盖到；到任何异网针 / 外壳盘 ≥ V12_CLR + rects = l1_12v_rects() + for i in range(1, SLOT_N + 1): + for row in 'SN': + for u, t in PIN_ROWS[row].items(): + p = pad_rect(i, row, u) + if t == '12V': + if not any(_overlap(p, r) for r in rects): + bad.append(u'槽 %d %s 排 u=%.1f 的 12V 针没被铜盖到' % (i, row, u)) + else: + g = min(_gap(p, r) for r in rects) + if g < V12_CLR - 1e-6: + bad.append(u'12V 铜离槽 %d %s 排 u=%.1f（%s）只有 %.3f' + % (i, row, u, t, g)) + for s in shell_rects(i): + g = min(_gap(s, r) for r in rects) + if g < V12_CLR - 1e-6: + bad.append(u'12V 铜离槽 %d 外壳盘只有 %.3f' % (i, g)) + main = rects[0] + if main[2] - main[0] < 8.0: + bad.append(u'L1 12V 主块只有 %.1f mm 宽，9 A 要 ≥ 8' % (main[2] - main[0])) + # 走廊铺满、净宽对 + cs = corridors() + for a, b in zip(cs, cs[1:]): + if a[3] > b[1] + 1e-6: + bad.append(u'走廊重叠: %s / %s' % (a, b)) + for k in range(1, SLOT_N): + w = cs[k][3] - cs[k][1] + if abs(w - (SLOT_PITCH - SLOT_BODY_W)) > 1e-6: + bad.append(u'走廊 %d 净宽 %.2f' % (k, w)) + # 背面分区：在板内、两两不重叠、不压过孔带 + zs = sorted(ZONES.items()) + for k, z in zs: + if z[0] < EDGE_KEEP - 1e-6 or z[1] < EDGE_KEEP - 1e-6 or \ + z[2] > BW - EDGE_KEEP + 1e-6 or z[3] > BH - EDGE_KEEP + 1e-6: + bad.append(u'分区 %s 出板: %s' % (k, z)) + for j, vb in enumerate(via_bands(), 1): + if _overlap(z, vb): + bad.append(u'分区 %s 压到槽 %d 过孔带' % (k, j)) + for n, (ka, za) in enumerate(zs): + for kb, zb in zs[n + 1:]: + if _overlap(za, zb): + bad.append(u'分区 %s / %s 重叠' % (ka, kb)) + if [USB_SLOT_REF[i] for i in range(1, SLOT_N + 1)] != list(SLOT_REFS): + bad.append(u'USB -> 插槽位号映射被改坏') + # 安装孔：不出板 / 不压槽体 / 不被圆角切 / 不落天线缺口 + for n, (hx, hy) in MOUNT_HOLES.items(): + if not (HOLE_KEEP < hx < BW - HOLE_KEEP and HOLE_KEEP < hy < BH - HOLE_KEEP): + bad.append(u'安装孔 %s 出板或贴边: (%.1f, %.1f)' % (n, hx, hy)) + hr = (hx - HOLE_KEEP, hy - HOLE_KEEP, hx + HOLE_KEEP, hy + HOLE_KEEP) + for i in range(1, SLOT_N + 1): + if _overlap(hr, slot_body(i)): + bad.append(u'安装孔 %s 压到槽 %d' % (n, i)) + for cx, cy in ((CORNER_R, CORNER_R), (BW - CORNER_R, CORNER_R), + (CORNER_R, BH - CORNER_R), (BW - CORNER_R, BH - CORNER_R)): + out_x = hx < cx if cx < BW / 2 else hx > cx + out_y = hy < cy if cy < BH / 2 else hy > cy + if out_x and out_y and math.hypot(hx - cx, hy - cy) > CORNER_R - HOLE_KEEP: + bad.append(u'安装孔 %s 被 R%.0f 圆角切到' % (n, CORNER_R)) + if _overlap(hr, ANT_NOTCH): + bad.append(u'安装孔 %s 落进天线缺口' % n) + sep = chr(10) + ' ' + assert not bad, u'底板自检不过:' + sep + sep.join(bad) + return True + + +# ── 下发 ────────────────────────────────────────────────────────────── +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def mil(v): + return round(v * MIL, 4) + + +def polygon_src(pts): + a = [mil(pts[0][0]), mil(pts[0][1])] + for q in pts[1:]: + a += ['L', mil(q[0]), mil(q[1])] + if pts[0] != pts[-1]: + a += ['L', mil(pts[0][0]), mil(pts[0][1])] + return a + + +def push_outline(): + u"""板框 = 一条闭合折线；顺带删掉层 11 上遗留的**导线**（§27.3 的坑）。""" + src = polygon_src(outline_polygon()) + js = ("await eda.dmt_EditorControl.openDocument('%s');" % PCB + + "await new Promise(r=>setTimeout(r,2500));" + + "const oldL = (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11)" + ".map(l=>l.primitiveId);" + + "if (oldL.length) await eda.pcb_PrimitiveLine.delete(oldL);" + + "const oldP = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).map(p=>p.getState_PrimitiveId());" + + "if (oldP.length) await eda.pcb_PrimitivePolyline.delete(oldP);" + + "const poly = await eda.pcb_MathPolygon.createPolygon(%s);" % json.dumps(src) + + "const r = await eda.pcb_PrimitivePolyline.create('', 11, poly, %s);" % mil(OUTLINE_W) + + "await eda.pcb_Document.save();" + + "return {delLine: oldL.length, delPoly: oldP.length, made: !!r," + " now: (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).length," + " line11: (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11).length};") + r = call(js, timeout=300) + print(u'板框折线: %s（删旧导线 %d / 旧折线 %d）；层 11 现有折线 %d / 导线 %d' + % (u'建好' if r['made'] else u'失败', r['delLine'], r['delPoly'], r['now'], r['line11'])) + if not r['made'] or r['now'] != 1: + raise SystemExit(u'!! 板框没画成') + return r + + +PUSH_HOLES_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const H = %s, D = %s; +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const num = p.getState_PadNumber(); + if (typeof num === 'string' && /^H[1-9]$/.test(num)) + await eda.pcb_PrimitivePad.delete(p.getState_PrimitiveId()); +} +let k = 0; +for (const [name, x, y] of H) { + // layer 12 = 多层；末位 metallization=false ⇒ NPTH。参数位序照抄 pcb_blade.push_holes + await eda.pcb_PrimitivePad.create(12, name, x, y, 0, ['ELLIPSE', D, D], '', + ['ROUND', D], 0, 0, 0, false); + k++; +} +await eda.pcb_Document.save(); +return {made: k, now: (await eda.pcb_PrimitivePad.getAll()) + .filter(p => /^H[1-9]$/.test(String(p.getState_PadNumber()))).length}; +""" + + +def push_holes(): + arr = [[k, mil(v[0]), mil(v[1])] for k, v in sorted(MOUNT_HOLES.items())] + r = call(PUSH_HOLES_JS % (PCB, json.dumps(arr), mil(HOLE_D)), timeout=300) + print(u'安装孔: 下发 %d / 读回 %d，NPTH Φ%.1f' % (r['made'], r['now'], HOLE_D)) + for k, v in sorted(MOUNT_HOLES.items()): + print(u' %-3s (%6.2f, %6.2f)' % (k, v[0], v[1])) + return r + + +def verify(): + r = call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "const ps = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11);" + "const line11 = (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>l.layer===11).length;" + "const holes = (await eda.pcb_PrimitivePad.getAll())" + ".filter(p=>/^H[1-9]$/.test(String(p.getState_PadNumber())))" + ".map(p=>[String(p.getState_PadNumber()), p.getState_X(), p.getState_Y()]);" + "return {n: ps.length, poly: ps.length ? ps[0].getState_Polygon() : null," + " line11, holes, layers: await eda.pcb_Layer.getTheNumberOfCopperLayers()," + " comps: (await eda.pcb_PrimitiveComponent.getAll()).length};" % PCB, + timeout=180) + bad = [] + if r['layers'] != LAYERS: + bad.append(u'铜层数 %s != %d' % (r['layers'], LAYERS)) + if r['n'] != 1: + bad.append(u'层 11 上有 %d 条折线（应为 1）' % r['n']) + if r['line11']: + bad.append(u'层 11 上还有 %d 条**导线**（板框画成铜的老坑，§27.3）' % r['line11']) + pts = [] + src = r['poly'] + if isinstance(src, dict): + src = src.get('pointArr') or src.get('points') or src.get('polygon') or src + if isinstance(src, list): + i = 0 + while i < len(src): + if src[i] in ('L', 'l'): + i += 1 + continue + if isinstance(src[i], (int, float)) and i + 1 < len(src) and isinstance(src[i + 1], (int, float)): + pts.append((src[i] / MIL, src[i + 1] / MIL)) + i += 2 + else: + i += 1 + if pts: + xs = [p[0] for p in pts] + ys = [p[1] for p in pts] + if abs(min(xs)) > 0.01 or abs(max(xs) - BW) > 0.01 or \ + abs(min(ys)) > 0.01 or abs(max(ys) - BH) > 0.01: + bad.append(u'外接矩形 %.2f~%.2f x %.2f~%.2f != 0~%.0f x 0~%.0f' + % (min(xs), max(xs), min(ys), max(ys), BW, BH)) + if abs(pts[0][0] - pts[-1][0]) > 0.01 or abs(pts[0][1] - pts[-1][1]) > 0.01: + bad.append(u'折线首尾不重合: %s vs %s' % (pts[0], pts[-1])) + if abs(len(pts) - len(outline_polygon())) > 1: + bad.append(u'点数 %d != %d' % (len(pts), len(outline_polygon()))) + print(u'读回板框折线 1 条 / %d 点，外接 %.2f~%.2f x %.2f~%.2f；层 11 遗留导线 %d' + % (len(pts), min(xs), max(xs), min(ys), max(ys), r['line11'])) + else: + bad.append(u'读不回折线点列（原始值 %s）' % str(r['poly'])[:120]) + got = {h[0]: (round(h[1] / MIL, 3), round(h[2] / MIL, 3)) for h in r['holes']} + for n, (hx, hy) in sorted(MOUNT_HOLES.items()): + if n not in got: + bad.append(u'安装孔 %s 没打' % n) + elif abs(got[n][0] - hx) > 0.02 or abs(got[n][1] - hy) > 0.02: + bad.append(u'安装孔 %s 位置 %s != (%.1f, %.1f)' % (n, got[n], hx, hy)) + print(u'铜层 %s；安装孔读回 %d 个；板上元件 %d 件' % (r['layers'], len(got), r['comps'])) + if bad: + print(u'[X] 校验不过:') + for b in bad: + print(u' ' + b) + else: + print(u'[OK] 4 层、板框是一条闭合折线、外接矩形对上、安装孔齐') + return bad + + +if __name__ == '__main__': + selfcheck() + print(u'底板 %.0f x %.0f，%d 层，四角 R%.0f；PCB=%s' % (BW, BH, LAYERS, CORNER_R, PCB)) + print(u'槽阵 5 槽 @%.2f（长轴沿 x，rot %d，槽心 x %.1f）: y = %s' + % (SLOT_PITCH, SLOT_ROT, SLOT_CX, u' / '.join('%.2f' % y for y in slot_ys()))) + print(u'走廊: %s' % u' | '.join('%.2f~%.2f' % (c[1], c[3]) for c in corridors())) + print(u'背面分区（限高 %.0f mm）:' % H_BOTTOM) + for k, z in sorted(ZONES.items()): + print(u' %-4s (%5.1f, %5.1f)-(%5.1f, %5.1f) %6.0f mm²' + % (k, z[0], z[1], z[2], z[3], (z[2] - z[0]) * (z[3] - z[1]))) + r = l1_12v_rects() + print(u'L1 +12V：主块 x %.2f~%.2f（宽 %.1f）+ %d 块指头，指头东界 x=%.2f' + % (r[0][0], r[0][2], r[0][2] - r[0][0], len(r) - 1, r[1][2])) + if '--outline' in sys.argv: + push_outline() + verify() + elif '--holes' in sys.argv: + push_holes() + verify() + elif '--verify' in sys.argv: + verify() diff --git a/.claude/r2/pcb_blade.py b/.claude/r2/pcb_blade.py new file mode 100644 index 0000000..52282dd --- /dev/null +++ b/.claude/r2/pcb_blade.py @@ -0,0 +1,504 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB（M4）：板框 + 分区参考 + 摆位常量。 + + /c/Python314/python .claude/r2/pcb_blade.py # 只算 + 自检 + /c/Python314/python .claude/r2/pcb_blade.py --outline # 画/重画板框（幂等） + /c/Python314/python .claude/r2/pcb_blade.py --verify # 读回校验板框 + 挖槽区域 + /c/Python314/python .claude/r2/pcb_blade.py --slots # 只重画两条排线槽（layer 12 填充） + +## 坐标系 + +**板左下角 = (0, 0)，x 向右、y 向上**（EasyEDA PCB 里 y 向上为正，见方案 §22.5）。 +这正好是方案 §3.1 那张分区图的坐标，图里的数可以直接抄。 + +``` +y 76 ┬──────────────────────────────────┬──────────────┐ + │ │ 功率列 26mm │ + │ 小米8 主板 67.09 × 44.66 │ Buck/L/Cin │ +y 29 ┼──── 接口边 ───────────────────────┤ eFuse/Rs │ + │ 服务带 18mm C60/TP/EDL/BM24/K1~4 │ INA/PCA9555 │ +y 11 ┼──────────────────────────────────┴──────────────┤ + │ 金手指区 11mm（槽体 ~9mm 要让开，这一带不许放件） │ +y 0 ┴───────────────── 板边（卡边）─────────────────────┘ + x 0 3 ──── 手机主板 ──── 70.09 72 ─ 功率列 ─ 98 +``` + +## 板框的底边是**断开**的 + +金手指的防呆缺口画在封装 `EDGE-64P-P1.00_PCIE-X4-GF` 的板框层里（方案 §22.3）， +所以这里画的底边必须在缺口口部让开一段：断点 x 由 `fp_edge.notch_mouth()` + `J1_X` 算出， +**不要手抄**。两段拼起来才是一个闭合板框；拼不上 DRC 会报开口。 + +## ⛔ 不用 pcb_PrimitiveArc + +实测（方案 §22.4）：`pcb_PrimitiveArc.create()` 在**封装编辑器里画得出但读不回、删不掉**， +在 **PCB 文档里干脆什么都不画**（返回值仍然是成功的）。⇒ 四角 R2 用折线近似， +弦高误差 < 0.01 mm。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import fp_edge # noqa: E402 + +PCB = '3b9c4e39c8d164db' # BLADE-PCB +MIL = fp_edge.MIL + +# ── 板框（mm，出处 方案 §3.1）───────────────────────────────────────── +BW, BH = 98.0, 76.0 +CORNER_R = 2.0 +CORNER_SEG = 8 # 每个 R2 圆角用几段折线 +OUTLINE_W = 0.15 + +# 金手指阵列中心。**居中**：刀片 98 宽、插槽体只有 39，居中让两侧悬臂等长 +# （左边是手机主板、右边是功率列，两头都不轻）。⚠ 底板的 5 个插槽必须按同一个数摆。 +J1_X, J1_Y, J1_ROT = BW / 2.0, 0.0, 0 + +# ── 小米8 主板的落点 + 定位孔（板级事实，摆位/布线/铺铜都从这里取）──────── +# 主板 67.09 × 44.66，长边水平、**接口边（v=0，J600/J1401/侧键都在上面）朝下**。 +PHONE_ORG = (3.0, 29.0) +PHONE_WH = (67.09, 44.66) + +# ⛔ **主板定位孔**。整个 §3.2 的高度预算 / §21.1 的槽距结论都建立在 +# 「螺丝把主板压在刀片上、螺柱间隙 1.0 mm」（R1 §22.3e 的中框式焊盘）之上 —— +# 没有这几个孔，`K1~K4` 那四个裸铜盘就没有压力，整套接触方式不成立。 +# 孔位是实测值（`.claude/mi8_mech.json` 的 `holes`，u/v 本体坐标）。 +# 直径沿用 R1 已经定稿的一组（`pcb2_place.py`）： +# 主板自己的孔 **Φ2.0**（用户卡尺）⇒ 配 **M1.6 尼龙立柱**（M2 螺杆塞 Φ2.0 没余量）， +# 刀片这一侧是螺钉过孔，取 M1.6 的通孔 **Φ1.8 NPTH**。 +# ⚠ R1 载板上 `H5` 没打（撞 EDL 座），**刀片上七个孔全都够得开**（实测最近焊盘 3.06 mm +# 是 H1 到 K2），所以七个全打。 +HOLE_D = 1.8 +HOLE_KEEP = 2.2 # 螺钉头避让（M1.6 尼龙螺钉头 Ø3.2 + 余量） +HOLE_VIA_KEEP = 1.5 # 孔到过孔/铜的最小中心距（孔半径 0.9 + 过孔半径 0.3 + 净距） + + +def phone_holes(): + u"""{名字: (x, y)}，刀片坐标。""" + m = json.load(io.open(os.path.join(os.path.dirname(HERE), 'mi8_mech.json'), + encoding='utf-8')) + return {k: (round(PHONE_ORG[0] + u, 3), round(PHONE_ORG[1] + v, 3)) + for k, (u, v) in m['holes'].items()} + + +# ── 排线穿板槽（2026-09-09 用户拍板：屏蔽窗去掉、器件全到 B 面、给两条排线开槽）── +# ⛔ **屏蔽罩避让窗已删**。它是「屏蔽罩轮廓没实测所以全挖」的保守项，而 R1 §22.3e 的 +# 定稿是「载板不挖空：用户实测贴合面元件全低于 1 mm」。去掉之后 L2 地平面整块、 +# 板子恢复刚度，B 面手机投影 67×44 全部可放件（高度预算见 pcb_place.H_B_*）。 +# +# **排线走法**（照搬 R1 `pcb2_place.SLOTS`，2026-09-06 实测排线：电池 8×38、尾插 18×55）： +# J600/J1401 在主板朝上那一面 → 朝接口边（y=29）走 → 翻过板边落到刀片 A 面 +# → 到接口边外侧 2.7 mm 的槽 → 穿板 → **U 形折回，贴着 B 面往 +y 走**到手机投影下方的 +# `J5` / `J4`。折回是绕 x 轴翻 180°：x 不变、y 镜像 —— 而立创底层正是「先 y 镜像再转」 +# （方案 §25.3），所以 `J5`/`J4` 在底层 **rot 0** 就是对的（R1 §25.16 v4 同一结论）。 +# ⚠ 槽是 **layer 12 (MULTI) 的填充 = 挖槽区域**（`pcb_PrimitiveFill`），不是板框内环。 +# DRC 认它（「挖槽区域 到 导线」），内层铺铜也会给它让反焊盘。 +# ⚠ J1401 的 x 取设计文档 §22.3b 的**本体中心 53.58**（±0.3），不是 `mi8_mech.json` +# `contacts_up.J1401 = 48.76` —— 那是座子西端（两者差 4.82 ≈ 半本体 6.1 − 1.3）。 +# TP1204/1205 两份数据吻合到 0.1，说明坐标系相同、只是 J1401 取的点不同。 +# 按 53.58 定，尾插车道西沿 47.6 正好让开 H4 螺钉头 (44.9 + 2.2)，与 R1 自洽。 +J600_U = 23.77 # 电池座中心（两份数据一致；§22.3b 标 ±2，槽放宽到 12） +J1401_U = 53.58 # 尾插座本体中心（§22.3b，±0.3） +SLOT_Y = (24.8, 27.8) # 槽的 y 区间：接口边外侧 1.2~4.2，中心离边 2.7（R1 同） +SLOT_W = {'BAT': 12.0, 'TAIL': 20.0} # 排线 8 / 18，各留余量 +FLEX_W = {'BAT': 8.0, 'TAIL': 18.0} +SLOT_R = 1.0 # 槽内圆角（铣刀半径，嘉立创内槽最小 R0.5） + + +def flex_x(): + u"""两条排线的中心 x（刀片坐标）。""" + return {'BAT': round(PHONE_ORG[0] + J600_U, 3), 'TAIL': round(PHONE_ORG[0] + J1401_U, 3)} + + +def flex_slots(): + u"""{名字: (x0, y0, x1, y1)}，刀片坐标，铣穿。""" + out = {} + for k, cx in flex_x().items(): + w = SLOT_W[k] + out[k] = (round(cx - w / 2, 3), SLOT_Y[0], round(cx + w / 2, 3), SLOT_Y[1]) + return out + + +def mill_cuts(): + u"""板上全部铣穿的内槽 [(x0,y0,x1,y1)] —— 布线 / 铺铜 / 摆位都从这里取障碍。""" + return list(flex_slots().values()) + + +def slot_check(): + u"""槽不许啃到螺钉孔避让圈，两条槽之间要留肋，槽不许进手机投影。""" + bad = [] + for k, w in flex_slots().items(): + for hn, (hx, hy) in phone_holes().items(): + dx = max(w[0] - hx, 0.0, hx - w[2]) + dy = max(w[1] - hy, 0.0, hy - w[3]) + if math.hypot(dx, dy) < HOLE_KEEP: + bad.append(u'槽 %s 离螺钉孔 %s 只有 %.2f < %.1f' % (k, hn, math.hypot(dx, dy), HOLE_KEEP)) + if w[3] > PHONE_ORG[1]: + bad.append(u'槽 %s 顶 %.1f 进了手机投影（接口边 %.1f）' % (k, w[3], PHONE_ORG[1])) + if w[1] < ZONES['finger'][3] + 1.0: + bad.append(u'槽 %s 底 %.1f 压到金手指区' % (k, w[1])) + s = flex_slots() + rib = s['TAIL'][0] - s['BAT'][2] + if rib < 3.0: + bad.append(u'两槽之间只剩 %.1f mm 肋（要 >= 3）' % rib) + return bad + + +# 分区（只是参考矩形，画在文档层，摆位脚本从这里取） +ZONES = { + 'finger': (0.0, 0.0, BW, 11.0), # 金手指区：不许放件（槽体 ~9mm） + 'service': (0.0, 11.0, 72.0, 29.0), # 服务带：C60 / TP / EDL / BM24 / K1~K4 + 'phone': (3.0, 29.0, 3 + 67.09, 29.0 + 44.66), # 小米8 主板投影 + 'power': (72.0, 11.0, BW, BH), # 功率列 +} + + +def corner(cx, cy, a0, a1): + u"""圆角折线点列（角度 deg，逆时针）。""" + pts = [] + for k in range(CORNER_SEG + 1): + a = math.radians(a0 + (a1 - a0) * k / CORNER_SEG) + pts.append((cx + CORNER_R * math.cos(a), cy + CORNER_R * math.sin(a))) + return pts + + +def outline_pts(): + u"""板框点列（逆时针，从底边左端 (r,0) 起，回到 (r,0) 闭合）。 + + ⚠ 相邻重合点必须去掉：圆角的首点和前一条直边的终点是同一个点，留着就会生成 + 一条**零长度线段**，编辑器会静默把它吃掉（下发 41 段读回 37 段）， + 于是「读回条数 != 期望」变成一个没完没了的假警报。这正是 CLAUDE.md 里 + 原理图那条「零长度导线」坑的 PCB 版。 + """ + r = CORNER_R + pts = [(r, 0.0), (BW - r, 0.0)] + pts += corner(BW - r, r, 270, 360) # 右下 + pts += [(BW, BH - r)] + pts += corner(BW - r, BH - r, 0, 90) # 右上 + pts += [(r, BH)] + pts += corner(r, BH - r, 90, 180) # 左上 + pts += [(0.0, r)] + pts += corner(r, r, 180, 270) # 左下，收回 (r,0) + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + assert abs(out[0][0] - out[-1][0]) < 1e-9 and abs(out[0][1] - out[-1][1]) < 1e-9, u'板框点列没有闭合' + return out + + +def notch_break(): + u"""底边要断开的区间（板坐标 mm）。""" + ml, mr = fp_edge.notch_mouth() + return round(J1_X + ml, 4), round(J1_X + mr, 4) + + +def segments(): + u"""板框全部线段。底边在缺口口部断开。""" + pts = outline_pts() + segs = [] + for a, b in zip(pts, pts[1:]): + segs.append((a[0], a[1], b[0], b[1])) + # 第一段是底边 (r,0)->(BW-r,0)，切成两段 + bl, br = notch_break() + x0, y0, x1, y1 = segs[0] + assert (y0, y1) == (0.0, 0.0) and x0 < bl < br < x1, u'底边不是第一段或断点跑出去了' + segs[0:1] = [(x0, 0.0, bl, 0.0), (br, 0.0, x1, 0.0)] + # ⚠ 排线槽**不在这里**：它们是 layer 12 的填充（挖槽区域），见 push_slots() + return segs + + +def notch_pts(): + u"""缺口的点列（板坐标），**自左向右**：口部左 → 导入角 → 左壁 → 顶半圆 → 右壁 → 口部右。 + + 几何仍然只有 `fp_edge` 一个出处，这里只做「封装坐标 + J1_X」的平移和顺序调整。 + """ + hw = fp_edge.NOTCH_W / 2.0 + ml, mr = notch_break() + cx = J1_X + fp_edge.NOTCH_CX + top = fp_edge.NOTCH_D - hw + pts = [(ml, 0.0), (cx - hw, fp_edge.LEAD_IN), (cx - hw, top)] + for k in range(fp_edge.ARC_SEG, -1, -1): # 半圆从左（π）走到右（0） + a = math.pi * k / fp_edge.ARC_SEG + pts.append((cx + hw * math.cos(a), top + hw * math.sin(a))) + pts += [(cx + hw, fp_edge.LEAD_IN), (mr, 0.0)] + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + return out + + +def outline_polygon(): + u"""**一条闭合折线**的完整板框点列：圆角矩形 + 底边中间的金手指防呆缺口。 + + ⛔ 为什么不用 `segments()` 那 37 段线（2026-09-09，M7）： + `pcb_PrimitiveLine` 在嘉立创里是**导线（铜）**，不是图形线 —— 选中它属性面板写的是 + 「导线」，还带网络 / 网络长度，`图层` 那一格 `data-value=11` 但**显示是空的** + （下拉里只有铜层，板框层不在选项里）。渲染成品红、DRC 也不报， + 所以四道几何校验全过，而**客户端根本不把它当板框**： + 自动布线一路弹「请先绘制板框！」。板框要用 `pcb_PrimitivePolyline`（折线）画。 + """ + pts = outline_pts() # 闭合，第一段是底边 (r,0)->(BW-r,0) + bl, br = notch_break() + assert pts[0][1] == 0.0 and pts[1][1] == 0.0 and pts[0][0] < bl < br < pts[1][0], u'底边不是第一段或断点跑出去了' + return [pts[0]] + notch_pts() + list(pts[1:]) + + +def polygon_src(pts): + u"""点列 -> pcb_MathPolygon.createPolygon 的源数组（mil，显式闭合）。""" + a = [mil(pts[0][0]), mil(pts[0][1])] + for q in pts[1:]: + a += ['L', mil(q[0]), mil(q[1])] + if pts[0] != pts[-1]: + a += ['L', mil(pts[0][0]), mil(pts[0][1])] + return a + + +def rrect_pts(x0, y0, x1, y1, r, seg=6): + u"""圆角矩形闭合点列。内槽必须圆角：铣刀下不去直角，嘉立创内槽最小 R0.5。""" + pts = [] + for cx, cy, a0 in ((x1 - r, y0 + r, 270), (x1 - r, y1 - r, 0), + (x0 + r, y1 - r, 90), (x0 + r, y0 + r, 180)): + for k in range(seg + 1): + a = math.radians(a0 + 90.0 * k / seg) + pts.append((cx + r * math.cos(a), cy + r * math.sin(a))) + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + out.append(out[0]) + return out + + +def selfcheck(): + bl, br = notch_break() + assert round(br - bl, 4) == 2.9, (bl, br) + # 金手指必须整个落在板内，且不侵占服务带 + for pin in ('A1', 'A32'): + x, y, w, h = fp_edge.pad_geom(pin) + ax = J1_X + x + assert 0.5 < ax < BW - 0.5, u'%s 跑出板外: x=%.2f' % (pin, ax) + top = fp_edge.EDGE_CLR + fp_edge.LONG_L + assert top < ZONES['finger'][3], u'手指顶到服务带' + assert fp_edge.NOTCH_D < ZONES['finger'][3], u'缺口比金手指区还深' + # 分区不许互相重叠（除了 finger/service 只共边） + z = ZONES + assert z['service'][3] == z['phone'][1] == 29.0 + assert z['phone'][2] <= z['power'][0], u'手机投影压进功率列' + assert z['service'][2] <= z['power'][0], u'服务带压进功率列' + assert z['phone'][3] <= BH, u'手机投影超出板顶' + bad = slot_check() + assert not bad, u'排线槽校核不过: %s' % bad + return True + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def mil(v): + return round(v * MIL, 4) + + +def push_outline(): + u"""画板框：**一条闭合折线**（`pcb_PrimitivePolyline`），含金手指缺口。 + + 顺带把层 11 上遗留的**导线**全删掉 —— M4b~M6 一直是用 `pcb_PrimitiveLine` + 画的，那是铜，客户端不认（见 `outline_polygon()` 的说明）。 + """ + src = polygon_src(outline_polygon()) + js = ("await eda.dmt_EditorControl.openDocument('%s');" % PCB + + "await new Promise(r=>setTimeout(r,2500));" + + "const oldL = (await eda.pcb_PrimitiveLine.getAll()||[]).filter(l=>l.layer===11)" + ".map(l=>l.primitiveId).filter(i=>i.length<=20);" + + "if (oldL.length) await eda.pcb_PrimitiveLine.delete(oldL);" + + "const oldP = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).map(p=>p.getState_PrimitiveId());" + + "if (oldP.length) await eda.pcb_PrimitivePolyline.delete(oldP);" + + "const poly = await eda.pcb_MathPolygon.createPolygon(%s);" % json.dumps(src) + + "const r = await eda.pcb_PrimitivePolyline.create('', 11, poly, %s);" % mil(OUTLINE_W) + + "await eda.pcb_Document.save();" + + "return {delLine: oldL.length, delPoly: oldP.length, made: !!r," + " now: (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11).length};") + r = call(js, timeout=300) + print(u'板框折线: 建 %s（删旧导线 %d / 旧折线 %d）；层 11 上现有折线 %d 条' + % (u'成功' if r['made'] else u'失败', r['delLine'], r['delPoly'], r['now'])) + if not r['made'] or r['now'] != 1: + raise SystemExit(u'!! 板框没画成') + return r + + +PUSH_SLOTS_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const S = %s; +let del = 0; +for (const f of await eda.pcb_PrimitiveFill.getAll()) + if (f.getState_Layer() === 12) { await eda.pcb_PrimitiveFill.delete(f.getState_PrimitiveId()); del++; } +let made = 0, fail = []; +for (const [name, src] of S) { + const poly = await eda.pcb_MathPolygon.createPolygon(src); + const r = await eda.pcb_PrimitiveFill.create(12, poly); + if (r) made++; else fail.push(name); +} +await eda.pcb_Document.save(); +const now = (await eda.pcb_PrimitiveFill.getAll()).filter(f => f.getState_Layer() === 12).length; +return {del, made, fail, now}; +""" + + +def slot_src(x0, y0, x1, y1): + u"""圆角矩形 -> pcb_MathPolygon 的点列源（mil，显式闭合）。照抄 R1 pcb2_place.slot_poly。""" + pts = rrect_pts(x0, y0, x1, y1, SLOT_R) + a = [mil(pts[0][0]), mil(pts[0][1])] + for p in pts[1:]: + a += ['L', mil(p[0]), mil(p[1])] + return a + + +def push_slots(): + S = [[k, slot_src(*w)] for k, w in sorted(flex_slots().items())] + r = call(PUSH_SLOTS_JS % (PCB, json.dumps(S)), timeout=300) + print(u'排线槽（layer 12 挖槽区域）: 建 %d / 失败 %s（删旧 %d）；板上现有 %d 个' + % (r['made'], r['fail'] or u'无', r['del'], r['now'])) + for k, w in sorted(flex_slots().items()): + print(u' %-5s x %.2f~%.2f y %.2f~%.2f (%.1f × %.1f，排线 %.0f 宽)' + % (k, w[0], w[2], w[1], w[3], w[2] - w[0], w[3] - w[1], FLEX_W[k])) + if r['now'] != len(S): + raise SystemExit(u'!! 槽没建全') + return r + + +def verify(): + u"""读回板框折线，逐点和 `outline_polygon()` 对账 + 校验闭合与外接矩形。""" + r = call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "const ps = (await eda.pcb_PrimitivePolyline.getAll()||[])" + ".filter(p=>p.getState_Layer()===11);" + "const line11 = (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>l.layer===11).length;" + "const fills = (await eda.pcb_PrimitiveFill.getAll()).filter(f=>f.getState_Layer()===12).length;" + "return {n: ps.length, poly: ps.length ? ps[0].getState_Polygon() : null," + " line11, fills};" % PCB, timeout=180) + bad = [] + if r['n'] != 1: + bad.append(u'层 11 上有 %d 条折线（应为 1 条）' % r['n']) + # ⚠ 层 11 上**允许**留 16 条导线：那是 J1 金手指封装内部的缺口线（fp_edge 画的）， + # 删不掉也不必删 —— 板框已经由折线自己闭合，它们只是重复的图形。 + if r['line11'] not in (0, 16): + bad.append(u'层 11 上还有 %d 条导线（只该剩 J1 封装那 16 条或 0 条）' % r['line11']) + if r['fills'] != len(flex_slots()): + bad.append(u'layer 12 挖槽区域 %d 个 != %d' % (r['fills'], len(flex_slots()))) + pts = [] + src = r['poly'] + if isinstance(src, dict): + src = src.get('pointArr') or src.get('points') or src.get('polygon') or src + if isinstance(src, list): + i, cur = 0, None + while i < len(src): + if src[i] == 'L' or src[i] == 'l': + i += 1 + continue + if isinstance(src[i], (int, float)) and i + 1 < len(src) and isinstance(src[i + 1], (int, float)): + pts.append((src[i] / MIL, src[i + 1] / MIL)) + i += 2 + else: + i += 1 + want = outline_polygon() + if pts: + xs = [p[0] for p in pts] + ys = [p[1] for p in pts] + if abs(min(xs)) > 0.01 or abs(max(xs) - BW) > 0.01 or abs(min(ys)) > 0.01 or abs(max(ys) - BH) > 0.01: + bad.append(u'板框外接矩形 %.2f~%.2f x %.2f~%.2f != 0~%.1f x 0~%.1f' + % (min(xs), max(xs), min(ys), max(ys), BW, BH)) + if abs(pts[0][0] - pts[-1][0]) > 0.01 or abs(pts[0][1] - pts[-1][1]) > 0.01: + bad.append(u'折线首尾不重合：%s vs %s' % (pts[0], pts[-1])) + if abs(len(pts) - len(want)) > 1: + bad.append(u'点数 %d != %d' % (len(pts), len(want))) + print(u'读回板框折线 1 条 / %d 点，外接 %.2f~%.2f x %.2f~%.2f；' + u'层 11 遗留导线 %d 条；挖槽区域 %d 个' + % (len(pts), min(xs), max(xs), min(ys), max(ys), r['line11'], r['fills'])) + else: + bad.append(u'读不回折线点列（原始值 %s）' % str(r['poly'])[:120]) + if bad: + print(u'[X] 校验不过:') + for b in bad: + print(u' ' + b) + else: + print(u'[OK] 板框是一条闭合折线（缺口在里面），外接矩形对上，挖槽区域齐') + return bad + + +PUSH_HOLES_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const H = %s, D = %s; +for (const p of await eda.pcb_PrimitivePad.getAll()) { + const num = p.getState_PadNumber(); + if (typeof num === 'string' && /^H[1-7]$/.test(num)) + await eda.pcb_PrimitivePad.delete(p.getState_PrimitiveId()); +} +let k = 0; +for (const [name, x, y] of H) { + // layer 12 = 多层；metallization=false ⇒ NPTH。参数位序照抄 R1 pcb2_place.py + await eda.pcb_PrimitivePad.create(12, name, x, y, 0, ['ELLIPSE', D, D], '', + ['ROUND', D], 0, 0, 0, false); + k++; +} +await eda.pcb_Document.save(); +return {made: k, now: (await eda.pcb_PrimitivePad.getAll()) + .filter(p => /^H[1-7]$/.test(String(p.padNumber))).length}; +""" + + +def push_holes(): + hs = phone_holes() + arr = [[k, round(v[0] * MIL, 4), round(v[1] * MIL, 4)] for k, v in sorted(hs.items())] + r = call(PUSH_HOLES_JS % (PCB, json.dumps(arr), round(HOLE_D * MIL, 4)), timeout=300) + print(u'主板定位孔: 下发 %d 个 / 读回 %d 个，NPTH Φ%.1f（⚠ 必须配 M1.6 尼龙立柱）' + % (r['made'], r['now'], HOLE_D)) + return r + + +if __name__ == '__main__': + selfcheck() + if '--holes' in sys.argv: + push_holes() + for k, v in sorted(phone_holes().items()): + print(u' %-3s (%6.2f, %6.2f)' % (k, v[0], v[1])) + sys.exit(0) + bl, br = notch_break() + print(u'刀片 %.0f x %.0f，四角 R%.1f；金手指中心 x=%.2f' % (BW, BH, CORNER_R, J1_X)) + print(u'底边断点: %.2f ~ %.2f（缺口口部）' % (bl, br)) + print(u'金手指跨度: x %.2f ~ %.2f，指顶 y=%.2f，缺口顶 y=%.2f' + % (J1_X + fp_edge.PIN_X['A1'] - fp_edge.FW / 2, + J1_X + fp_edge.PIN_X['A32'] + fp_edge.FW / 2, + fp_edge.EDGE_CLR + fp_edge.LONG_L, fp_edge.NOTCH_D)) + for k, z in ZONES.items(): + print(u' %-8s x %6.2f~%6.2f y %6.2f~%6.2f' % (k, z[0], z[2], z[1], z[3])) + for k, w in sorted(flex_slots().items()): + print(u' 槽 %-5s x %6.2f~%6.2f y %6.2f~%6.2f' % (k, w[0], w[2], w[1], w[3])) + if '--outline' in sys.argv: + push_outline() + push_slots() + verify() + elif '--slots' in sys.argv: + push_slots() + verify() + elif '--verify' in sys.argv: + verify() diff --git a/.claude/r2/pcb_import.py b/.claude/r2/pcb_import.py new file mode 100644 index 0000000..b23b7ab --- /dev/null +++ b/.claude/r2/pcb_import.py @@ -0,0 +1,203 @@ +# -*- coding: utf-8 -*- +u"""R2「从原理图导入变更」（刀片 / 底板通用）。 + + /c/Python314/python .claude/r2/pcb_import.py --bom 逐页抓原理图 BOM（对账基准） + /c/Python314/python .claude/r2/pcb_import.py --probe 开对话框、把变更行读出来 + /c/Python314/python .claude/r2/pcb_import.py --apply 真的点「应用修改」（先取消「包含设计规则」） + /c/Python314/python .claude/r2/pcb_import.py --verify PCB 元件表 ↔ 原理图 BOM 逐件对账 + 加 --base 就对底板做同一套事（默认是刀片）。 + +做法照搬 R1 的 `.claude/pcb1_import.py`（那一份是唯一的说明书，两个坑都在它头上）： +**没有可用的 API**，只能驱动 GUI。⚠ `pcb_Document.importChanges()` 这个 API 在本机 +客户端上**一律返回 false、对话框都不弹**（2026-09-08 实测，刀片 PCB 上试过带/不带 +schematic uuid 两种），别再浪费时间试它。 + +⚠ 改过原理图就要**先 `--bom` 再 `--verify`**，否则是拿新 PCB 和旧 BOM 对账。 +""" +import io +import json +import os +import re +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, HERE) +sys.path.insert(0, os.path.dirname(HERE)) +from eda import run # noqa: E402 + +U = json.load(io.open(os.path.join(HERE, 'r2-uuids.json'), encoding='utf-8')) +BASE = '--base' in sys.argv +BOARD = 'BASE' if BASE else 'BLADE' +PCB = U['boards'][BOARD]['pcb']['uuid'] +PAGES = U['boards'][BOARD]['pages'] +TAG = 'base' if BASE else 'blade' +BOM_FILE = '_%s_sch_bom.json' % TAG +COMPS_FILE = '_%s_pcb_comps.json' % TAG +ROWS_FILE = '_%s_import_rows.json' % TAG + +HELPERS = u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const p=propsOf(t); if(p&&typeof p.onClick==='function'){p.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +const nat = b => { const o={bubbles:true,cancelable:true,view:window,button:0}; + for (const t of ['pointerdown','mousedown','pointerup','mouseup','click']) + b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o)); }; +const leaf = (txt) => { for (const el of document.querySelectorAll('*')) if (el.children.length===0 && (el.textContent||'').trim()===txt && el.offsetParent!==null) return el; return null; }; +""" + +JS_PROBE = HELPERS + u""" +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(2000); +const out = {}; +fire(leaf('设计')); await sleep(900); +out.opened = fire(leaf('从原理图导入变更')); +await sleep(9000); +let sc = null; +for (const el of document.querySelectorAll('div')) + if (el.scrollHeight > el.clientHeight + 20 && /移除元件|增加元件|修改/.test(el.innerText || '')) + if (!sc || el.innerText.length < sc.innerText.length) sc = el; +const seq = []; +if (sc) { + sc.scrollTop = 0; await sleep(400); + let last = -1; + for (let i = 0; i < 200; i++) { + seq.push({top: sc.scrollTop, txt: sc.innerText}); + if (sc.scrollTop === last) break; + last = sc.scrollTop; + if (sc.scrollTop + sc.clientHeight >= sc.scrollHeight - 2) break; + sc.scrollTop += Math.max(40, sc.clientHeight / 2); + await sleep(260); + } +} +out.seq = seq; +out.buttons = [...document.querySelectorAll('button')].filter(b => b.offsetParent !== null).map(b => (b.innerText||'').trim()).filter(Boolean); +return out; +""" % PCB + +JS_APPLY = HELPERS + u""" +const out = {}; +let ruleBox = null, ruleTxt = null; +for (const el of document.querySelectorAll('*')) { + if (el.children.length === 0 && /设计规则/.test((el.textContent||'').trim()) && el.offsetParent !== null) { + ruleTxt = (el.textContent||'').trim(); + let r = el; + for (let i = 0; i < 6 && r; i++) { const cb = r.querySelector && r.querySelector('input[type=checkbox]'); if (cb) { ruleBox = cb; break; } r = r.parentElement; } + break; + } +} +out.ruleTxt = ruleTxt; out.ruleChecked = ruleBox ? ruleBox.checked : null; +if (ruleBox && ruleBox.checked) { nat(ruleBox); await sleep(500); out.ruleAfter = ruleBox.checked; } +const btn = [...document.querySelectorAll('button')].find(b => b.offsetParent !== null && (b.innerText||'').trim() === '应用修改'); +if (!btn) return Object.assign(out, {err: 'no 应用修改'}); +nat(btn); +await sleep(15000); +for (const b of document.querySelectorAll('button')) if (b.offsetParent !== null && /^(确定|确认|是)$/.test((b.innerText||'').trim())) { nat(b); await sleep(4000); out.confirmed = (b.innerText||'').trim(); } +await sleep(5000); +await eda.pcb_Document.save(); +out.n = (await eda.pcb_PrimitiveComponent.getAll()||[]).length; +return out; +""" + +JS_DUMP = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 2000)); +const cs = await eda.pcb_PrimitiveComponent.getAll(); +const out = []; +for (const c of (cs||[])) out.push({d: c.designator, x: c.x, y: c.y, rot: c.rotation, lay: c.layer, + fp: (c.footprint && c.footprint.name) ? c.footprint.name : (c.footprint || null)}); +return out; +""" % PCB + +JS_BOM = u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(1500); +const cur = String((await eda.dmt_Schematic.getCurrentSchematicPageInfo()).name || ''); +if (cur.toUpperCase() !== '%s') return {err: 'openDocument 打到了 ' + cur}; +const list = []; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + if (c.getState_ComponentType() !== 'part') continue; + let fp = null; + try { const f = c.getState_Footprint(); if (f) fp = {name: String(f.name || f)}; } catch (e) {} + list.push({d: String(c.getState_Designator ? c.getState_Designator() : ''), + uuid: c.getState_PrimitiveId(), fp: fp}); +} +return {list: list}; +""" + + +def call(js, timeout=300): + r = run(js, timeout=timeout) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:800]) + return r['result'] + + +def refresh_bom(): + u"""一页一个请求 —— eda.py 会把返回截到 20000 字符，整本 BOM 装不下。""" + bom, bad = {}, [] + for name, uuid in PAGES.items(): + r = run(JS_BOM % (uuid, name.upper()), timeout=300) + if not r.get('success'): + bad.append(u'%s: %s' % (name, json.dumps(r, ensure_ascii=False)[:160])) + continue + res = r['result'] + if res.get('err'): + bad.append(u'%s: %s' % (name, res['err'])) + continue + bom[name] = res['list'] + print(u' %-12s %3d 件' % (name, len(res['list']))) + if bad: + print(u'[X] 这几页没抓到，**没有写缓存**：') + for b in bad: + print(u' · ' + b) + sys.exit(1) + io.open(os.path.join(HERE, BOM_FILE), 'w', encoding='utf-8').write( + json.dumps(bom, ensure_ascii=False)) + print(u'已写 %s：%d 页 / %d 件' % (BOM_FILE, len(bom), sum(len(v) for v in bom.values()))) + + +def verify(): + cs = call(JS_DUMP) + io.open(os.path.join(HERE, COMPS_FILE), 'w', encoding='utf-8').write( + json.dumps(cs, ensure_ascii=False)) + bom = json.load(io.open(os.path.join(HERE, BOM_FILE), encoding='utf-8')) + sch = {} + for pg, v in bom.items(): + for c in v: + d = c.get('d') + if d and re.match(r'^[A-Za-z]+\d', d): + sch[d] = ((c.get('fp') or {}).get('name'), pg) + pcb = {c['d']: c for c in cs} + miss = sorted(set(sch) - set(pcb)) + extra = sorted(set(pcb) - set(sch)) + bad = [(d, pcb[d]['fp'], sch[d][0]) for d in sorted(set(sch) & set(pcb)) + if pcb[d]['fp'] != sch[d][0]] + print(u'原理图 %d 件 / PCB %d 件' % (len(sch), len(pcb))) + if miss: + print(u'[X] 原理图有、PCB 没有 (%d): %s' % (len(miss), ' '.join(miss[:30]))) + if extra: + print(u'[X] PCB 有、原理图没有 (%d): %s' % (len(extra), ' '.join(extra[:30]))) + for d, a, b in bad[:20]: + print(u'[X] %s 封装不一致: PCB=%s 原理图=%s' % (d, a, b)) + if not (miss or extra or bad): + print(u'[OK] %d 件逐件对上（位号 + 封装）' % len(sch)) + return miss, extra, bad + + +if __name__ == '__main__': + print(u'板: %s PCB=%s %d 页' % (BOARD, PCB, len(PAGES))) + if '--bom' in sys.argv: + refresh_bom() + if '--probe' in sys.argv: + r = call(JS_PROBE, timeout=420) + io.open(os.path.join(HERE, ROWS_FILE), 'w', encoding='utf-8').write( + json.dumps(r, ensure_ascii=False, indent=1)) + txt = '\n'.join(s['txt'] for s in r.get('seq', [])) + print(u'对话框: opened=%s 按钮=%s' % (r.get('opened'), r.get('buttons'))) + print(txt[:3000]) + if '--apply' in sys.argv: + print(call(JS_APPLY, timeout=420)) + if '--verify' in sys.argv: + verify() diff --git a/.claude/r2/pcb_pinswap.py b/.claude/r2/pcb_pinswap.py new file mode 100644 index 0000000..1559d42 --- /dev/null +++ b/.claude/r2/pcb_pinswap.py @@ -0,0 +1,65 @@ +# -*- coding: utf-8 -*- +u"""把 `pinmap_base.py` 在原理图上做的 EFUSE/PRSNT 换脚**同步到 PCB 的焊盘网名**。 + + /c/Python314/python .claude/r2/pcb_pinswap.py # 只读回对比 + /c/Python314/python .claude/r2/pcb_pinswap.py --push # 改焊盘网名 + 读回校验 + +⚠ 为什么不走「从原理图导入变更」对话框：那条路会按内部通道 ID 重新配对， + R1 §交接二 踩过一次（配错一格，把一个本来正确的风扇块打乱），修起来要 + `pcb1_uid_sync.py`。这里只有 8 只脚换名、元件身份一个没动，**定点改焊盘更安全**， + 判据也简单：读回这 8 只脚的网名逐个对上。 +""" +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +WANT = {'8': 'PRSNT1#', '9': 'PRSNT2#', '10': 'PRSNT3#', '11': 'PRSNT4#', + '17': 'EFUSE_EN1', '18': 'EFUSE_EN2', '19': 'EFUSE_EN3', + '20': 'EFUSE_EN4', '21': 'EFUSE_EN5'} + +JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 2000)); +const WANT = %s, PUSH = %s; +const out = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + if (c.designator !== 'U20') continue; + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + for (const p of ps) { + const n = String(p.getState_PadNumber()); + if (!(n in WANT)) continue; + const before = String(p.net || ''); + if (PUSH && before !== WANT[n]) { try { p.toAsync().setState_Net(WANT[n]).done(); } catch (e) {} } + out.push([n, before, WANT[n]]); + } +} +if (PUSH) { await eda.pcb_Document.save(); await new Promise(r => setTimeout(r, 800)); } +return out; +""" + + +def call(push): + r = run(JS % (B.PCB, json.dumps(WANT, ensure_ascii=False), 'true' if push else 'false'), + timeout=300) + assert r.get('success'), json.dumps(r, ensure_ascii=False)[:400] + return r['result'] + + +if __name__ == '__main__': + push = '--push' in sys.argv + rows = call(push) + rows.sort(key=lambda t: int(t[0])) + for n, before, want in rows: + flag = u'' if before == want else u' ← 改' + print(u' pin%-3s %-11s → %-11s%s' % (n, before or '(空)', want, flag)) + if push: + after = {t[0]: t[1] for t in call(False)} + bad = [n for n, w in WANT.items() if after.get(n) != w] + print(u'[%s] 读回校验%s' % ('OK' if not bad else 'X', + u'9 只脚逐个对上' if not bad else u' 不过: %s' % bad)) diff --git a/.claude/r2/pcb_place.py b/.claude/r2/pcb_place.py new file mode 100644 index 0000000..8b8a9c4 --- /dev/null +++ b/.claude/r2/pcb_place.py @@ -0,0 +1,1080 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 摆位（M4c-2；2026-09-08 改成**双面**：器件在手机的另一面）。 + + /c/Python314/python .claude/r2/pcb_place.py # 只算 + 自检（不下发） + /c/Python314/python .claude/r2/pcb_place.py --push # 下发摆位 + /c/Python314/python .claude/r2/pcb_place.py --verify # 读回校验 + +## ⛔ 分面：**手机在 A 面，器件全部在 B 面**（2026-09-09 用户拍板） + +小米8 主板压在 **A 面**（顶层）。A 面**只剩 `K1~K4` 四个裸铜盘**（主板弹片直接压， +物理上只能在这一面）和两面都是指的 `J1`；**其余 78 件全部在 B 面**。 + +`J600` 的电池排线和 `J1401` 的尾插排线从接口边翻下来，落到 A 面服务带后**穿板** +（`pcb_blade.flex_slots()`，接口边外侧 y 24.8~27.8 的两条铣穿槽），U 形折回 B 面， +贴着 B 面往 +y 走到**手机投影下方**的 `J5` / `J4` —— 和 R1 的 J8n / J7n 一模一样。 +排线在 B 面占的车道 `LANES` 里**一件不放**。 + +**高度预算分两段**（槽距 20.32，板厚 1.6，螺柱间隙 1.0）： + +| B 面区域 | 对面是什么 | 净空 | 落地 | +|---|---|---|---| +| 服务带 y 12~28 | 隔壁刀片的 A 面服务带，**现在是空的** | 20.32 − 1.6 = **18.7** | `C60`(10.5) / `J2` / `J3`(5) 只能放这里 | +| 手机投影 y ≥ 29 | 隔壁刀片的手机主板 | 20.32 − 1.6 − 1.0 − 7.6 = **10.1**（h_phone 取物理上限）| `J4` BM24 + 排线、`L1` 3.0 都够 | + +⚠ 以前「B 面只有 3.0」是把 `L1` 的高度当预算写的，不是净空；净空一直有 10 mm。 +`HEIGHT` 里登记的超高件禁止进手机投影，自检会拦。 + +**`J5` / `J4` 的朝向**：排线穿槽折回是绕 x 轴翻 180°（x 不变、y 镜像），立创底层 +正是「先 y 镜像再转 rot」（方案 §25.3）⇒ **底层 rot 0**，pin1 仍在西边（`J5.1 = P+` +在 −x，与 §13.5 用户实测「P+ 在左」一致）。⚠ 这是推导 + R1 §25.16 同一结论， +**装配首件仍要两点通断复核**，几何校验抓不到接反。 + +## 三类件，三种定位方式 + +1. **机械锚定件**（位置由小米8 主板决定，不许挪）：`K1~K4` 侧键触点盘、 + `J5` 电池排线焊盘、`J4` BM24 尾插座。坐标从 **`.claude/mi8_mech.json`** 换算， + 不手抄。手机主板在刀片上的落点是 `PHONE_ORG`（方案 §3.1：x 3~70.09 / y 29~73.66， + 长边水平、**接口边朝下**）。 +2. **手工钉死件**：`J1` 金手指（`pcb_blade.J1_X`）、`C60` Ø10.3 的 2200 µF、 + `J2` D± 退路座、`J3` EDL 座 —— 各有各的理由，见 `ANCHORS` 的注释。 +3. **其余 73 件**：按功能分组、按「电流流向」排序，塞进六个区（`REGIONS`）， + 用一个简单的货架式排布器摆。**顺序是设计意图，坐标不是** —— + 要改布局改 `GROUPS` 里的顺序和区，不要去改具体坐标。 + +## 分区（方案 §3.1，坐标见 `pcb_blade.py`；除 K1~K4 外全部是 B 面） + +| 区 | 范围 | 放什么 | +|---|---|---| +| 金手指区 | y 0~11 | **只有 J1，其余一件不放**（插槽体 ~9 mm 要让开），两面都不放 | +| 排线槽 + 车道 | BAT x 20.8~32.8 / TAIL x 46.6~66.6，y 24.8 → J5/J4 顶 | **铣穿 + 排线平贴，一件不放** | +| `KEY` | x 0.6~13 / y 22~38 | 侧键 MOS + 栅极电阻，`K1~K4` 的正背面 | +| `DIS` | x 21~34.2 / y 12~24 | `VO_P` 泄放，电池槽下方（VO-L3 岛内） | +| `CTRL` | x 54~63 / y 47~56 | I²C 上拉，跟着 `U4` 走（M7 起在板中央） | +| `SVC_M` | x 33~42.5 / y 29~50 | `VO_P` 阻尼组，电池车道东侧、`J5` 旁边（H4 螺钉头以西） | +| `SVC_R` | x 47.5~65.5 / y 35.5~46 | 尾插 USB + VBUS 开关，`J4` **北边（插头背后）** | +| `SVC_E` | x 66.6~72.5 / y 36.4~50 | EDL 模拟开关，尾插车道与功率列之间的走廊，`J3` 正北 | +| 功率列 | x 72.3~97.5 / y 12~74 | Buck / eFuse / 检流，**按「离手机越远越吵」内外分两条** | + +功率列内部：外条（x 86~97.5，靠板边）放 SW 节点、电感、Cin —— 最吵的； +内条（x 72~84，贴手机）放 FB 分压、DAC 低通、INA226、eFuse 外围 —— 最怕吵的。 +这是方案 §3.1 的「按离手机越远越吵排」和风险 R-12。 + +## M7（2026-09-09）：为「先自动布线」重排 B 面 + +用户拍板「B 面全部重排 → 先跑 EDA 自动布线 → 再优化」。这一版**动的是拥塞，不是拓扑** +—— §7.2 那四条关键回路（输入环路 / SW 面积 / FB 远离 SW / Kelvin）靠的是功率链手排， +一个数都没改；机械锚定件（`K1~K4` / `J5` / `J4` / `J1` / 七个孔）同样一个数没改。改的是： + +| 改动 | 为什么 | +|---|---| +| 排布器节距 1.1 → **1.8** | M6 欠的 5 只脚全是「出口被自家邻脚封死」。1.1 只够过一根线；板面占用率才 6%，加节距是白捡的 | +| `U4` PCA9555 从 (76.3, 18.5) 挪到 **(48, 52)** | 它 8×8 的本体卡在「功率列内条 × 金手指北岸」那个口袋里，五只不通的脚全在它周边一圈 | +| `EFUSE_AUX` 从 9.5×11.5 扩到 **11.7×16**，东沿退到 84.0 | 给 `U2` 西边留 2.55 的扇出通道（M6 只有 1.55） | +| `U2` 上下的缝 1.8 → **2.6 / 2.4**，`U1_Y` 49.5 → **50.9** | WQFN-20 上下两排脚要横着爬出去；抬 U1 是为了不把链尾 `U3` 顶到金手指禁布区上 | +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 + +MIL = B.MIL +PCB = B.PCB +BBOX = os.path.join(HERE, '_blade_bbox.json') +MECH = os.path.join(os.path.dirname(HERE), 'mi8_mech.json') + +GAP = 0.6 # 件间净距（mm）：**装配**下限，自检按它判重叠 +# ⛔ 排布器的**摆放节距**要比装配下限大得多 —— 0.6 的缝里塞不进一根线： +# 0.2 的线要 0.2 + 2×0.18(净距) = **0.56**，再加上 0.25 的网格吸附， +# 实际上等于没有通道。实测 0.6 排下来，17 处「出不来」里大半在 **0402 电阻**上 +# （不是细间距 IC），布线器怎么调顺序都是 28~30 条接不上。 +# 1.1 能过一根线还剩余量；区里都有空地（`EFUSE_AUX` 12 件只占了 79 mm² 中的 45）。 +PACK_GAP = 1.8 # 排布器的摆放节距（M7 从 1.1 加到 1.8，见下） +# ⛔ **M7（2026-09-09）把节距从 1.1 加到 1.8**：1.1 只够过**一根** 0.2 的线 +# （0.2 + 2×0.18 = 0.56，加 0.25 网格吸附实际剩不到一根的余量），而 M6 欠的 +# 5 只脚全是「出口被自家邻脚封死」——不是没地方走线，是**脚出不来**。 +# 1.8 能并排走两根线还剩余量。板子一点都不挤：83 件本体面积加起来 ~430 mm²， +# 板面 7448 mm²，占用率 6%，加节距是白捡的。 +# 个别区可以覆盖（值 = 该区的节距）。 +PACK_GAP_BY_REGION = { + 'BUCK_FB': 1.4, # U1 右边只有 6 mm 宽的缝，1.8 会退化成单列 +} +MILL_KEEP = 0.5 # 器件离铣穿内槽的净距 +# 排线在 B 面占的车道：从槽顶到连接器顶沿，宽 = 排线宽 + 2×0.5。**一件不放**（排线要平贴）。 +LANE_TOP = {'BAT': 34.5, 'TAIL': 35.0} + +# 手机主板在刀片上的落点：本体 (u,v) -> 板 (x,y) = (PHONE_ORG + (u,v)) +# 方案 §3.1：主板 67.09 × 44.66，长边水平、**接口边（v=0 那条，J600/J1401/侧键都在上面）朝下**。 +# ⚠ 事实来源在 pcb_blade（板级），这里只做别名，不要抄第二份 +PHONE_ORG = B.PHONE_ORG +PHONE_WH = B.PHONE_WH + +# 焊盘外框量不到本体的几个件：给真实本体尺寸（mm） +BODY = { + 'C60': (11.0, 11.0), # Ø10.3 铝电解，2200 µF（T2 = 高 10.5） + 'L1': (7.6, 7.0), # SPM6530T-4R7M + 'J4': (13.2, 3.6), # BM24-50DS + 'U4': (8.0, 8.0), +} + +# ── 分面 ─────────────────────────────────────────────────────────────── +# **A 面（顶层）只留这 10 件**，其余全部 B 面。理由逐条写在模块头的表里。 +TOP_ONLY = ['J1', 'K1', 'K2', 'K3', 'K4'] + +# 装配高度（mm）。只登记**可能超手机投影预算**的件 —— 放进 B 面手机投影会顶到 +# 隔壁槽的手机主板，而**几何自检和 DRC 一条都不报**。 +HEIGHT = { + 'C60': 10.5, # Ø10.3 铝电解（T2 实测） + 'J2': 5.0, # 1.25 mm 4P 线座（估） + 'J3': 5.0, # 1.25 mm 2P 线座（估） + 'L1': 3.0, # SPM6530T +} +H_B_PHONE = 20.32 - 1.6 - 1.0 - 7.6 # B 面手机投影下的净空（h_phone 取物理上限）= 10.12 +H_B_SVC = 20.32 - 1.6 # B 面服务带的净空（对面 A 面服务带是空的）= 18.72 + + +def phone(u, v): + return (round(PHONE_ORG[0] + u, 3), round(PHONE_ORG[1] + v, 3)) + + +def lanes(): + u"""排线在 B 面的车道 {名字: (x0, y0, x1, y1)}：槽顶 → 连接器顶沿，一件不放。""" + out = {} + for k, cx in B.flex_x().items(): + hw = B.FLEX_W[k] / 2.0 + 0.5 + out[k] = (round(cx - hw, 3), B.SLOT_Y[1], round(cx + hw, 3), LANE_TOP[k]) + return out + + +def anchors(): + u"""机械锚定 + 手工钉死的件 -> (x, y, rot)。K1~K4 在 A 面，其余 B 面。""" + m = json.load(io.open(MECH, encoding='utf-8')) + sk = m['side_key_contacts'] + fx = B.flex_x() + a = {} + # ── 侧键触点盘：主板自己的弹片直接压在这四个裸铜盘上（R1 §22.3e 中框式）── + # 位置**完全由主板决定**，Ø1.5 的盘只容许 0.50 mm 位置误差（pcb2_place 的算账）。 + for ref, key in (('K1', 'PWR'), ('K2', 'VUP'), ('K3', 'VDN'), ('K4', 'GND')): + a[ref] = phone(*sk[key]) + (0,) + # ── 电池排线焊盘 J5：B 面、电池槽正北、手机投影下方（排线穿槽后折回 +y）── + # y 由排线长度定：J600→接口边 4.6 + 绕边 5 + 到槽心 2.7 + 穿板 1.6 + 背面 (y−26.3) + # ≈ 19.6 ≤ 35（实长 38）。焊盘 4 高，底沿 30 离槽顶 27.8 有 2.2。**底层 rot 0**（见模块头）。 + a['J5'] = (fx['BAT'], 32.0, 0) + # ── BM24 尾插座 J4：B 面、尾插槽正北。2.48 + 5 + 2.7 + 1.6 + 6.7 ≈ 18.5 ≤ 50（实长 55）。 + # 本体 2.6 高 → 31.7~34.3；H4 (44.9,30.9) 在西边 5.4 mm 外。**底层 rot 0**。 + a['J4'] = (fx['TAIL'], 33.0, 0) + # ── C60：Ø10.3 / 高 10.5，只能在服务带（B 面净空 18.7）。夹在两条槽之间： + # 电池槽东沿 32.77 / 尾插槽西沿 46.58，本体 11 → 中心 40.0，西余 1.7 / 东余 1.1。 + # 顶 24.0 离槽底 24.8 有 0.8 ≥ MILL_KEEP。 + a['C60'] = (40.0, 18.5, 0) + # ── J2：D± 退路座，靠金手指 D± 针（B14/B15，x≈62/63）；下沿 12.6 让开 LAUNCH_Y 11.75。 + # 竖放沿用 2026-09-09 的决定，出线朝西（服务带里 DIS 与 J2 之间是空的）。 + # ⚠ 底层是「先 y 镜像再转」：读回实测 rot 90 把信号盘放到了**东**边（63.25）， + # rot 270 才回到西边（60.35）—— 本项目约定出线 = 信号盘那一侧（§25.x J2 的记法）。 + # 本体 5.2×10.8 → x 59.2~64.4 / y 12.6~23.4，顶离尾插槽 1.4。 + a['J2'] = (61.8, 18.0, 270) + # ── J3：EDL 座。两根飞线要去主板朝上面的 TP1204/1205 (48.4/45.6, 34.6)， + # 只能**跟着尾插排线穿尾插槽**（R1 同一做法），所以座子摆在尾插车道东侧的走廊里、 + # 出线朝南对着槽：底层 rot 0 读回信号盘在南（y 镜像后），本体 8.35×5.2 → + # x 66.2~74.6 / y 30.4~35.6；离车道东沿 66.08 有 0.1，离 EFUSE_AUX 区 0.9。 + # 高 5 < 手机投影下净空 10.1。⚠ 出线侧的约定见 J2 那条，装配时确认。 + a['J3'] = (70.4, 33.0, 0) + return a + + +# ── 功率级：**手排**，不交给排布器 ──────────────────────────────────── +# ⛔ 上一版把功率级也交给货架排布器，结果 §7.2 的四条关键回路**破了三条**： +# Cin 离 U1 **12.4 mm**（输入环路）、SW 从 U1 绕到 L1 走了 ~7 mm（SW 面积）、 +# FB 分压压在 SW 那一带。货架算法只会「按面积塞满」，它不认识回路。 +# +# **`U1` 转 90° 是这一版的关键一步**：TPS54622 的 VIN/GND 在一条长边、SW 在对边， +# 不转的话 Cin 和电感必然分居左右两侧 —— 而 §3.1 要求 SW / 电感 / Cin **同时** +# 靠板外边（x 88~98，离手机最远）。转成横放之后 VIN/GND 朝上、SW 朝下， +# 于是竖着堆成一条：**D1/F1 → Cin ×4 → U1 → L1 → Cout → eFuse → 分流 → INA**， +# 电流自上而下，出口 `VO_P` 正好落在 `VO-L3` 岛（y ≤ 28.8）里。 +# +# 三条回路各自的落地判据（改坐标前先想清楚会破哪一条）： +# · **输入环路**：`C4/C1/C2/C3` 正压在 U1 的 VIN/GND 引脚上方，最近一颗环路 ~1.0 mm； +# · **SW 面积**：`L1` 转 90° 让 1 号脚朝上，和 U1 的 SW 脚**焊盘对焊盘 0.6 mm**， +# SW 铜就是那一小块 3.4 mm 宽的方块，绕不出去； +# · **Kelvin**：`U3` 转 180° 让 9/10 脚朝上正对 `Rs1` —— **不转就是交叉** +# （9 脚在 10 脚右边，却要接左边那个焊盘），一交叉就得打过孔，§7.2 明令不许。 +STACK_GAP = 0.65 # 手排竖直堆叠的件间净距 + +# (位号, rot, dx)：dx = 相对功率列中心线 PWR_X 的横向偏移；y 由 stack() 自上而下算 +PWR_X = 89.0 +# 功率链的锚：U1 的中心 y。⚠ 抬高 2.5 mm 是**布线逼出来的**：链尾的 `U3`(INA226) +# 底边五个 0.5 mm 间距的脚要朝下扇出到金手指那一侧，原来只剩 1.0 mm 净空， +# 布线器报「INA_ALERT 一个焊盘都出不来」。抬完剩 3.5 mm，五根线排得开。 +U1_Y = 50.9 # ⚠ M7 从 49.5 抬到 50.9：U2 上下的缝各加了 0.8/0.6， +# 整条链会往下顺移同样多，而链尾 `U3`(INA226) 底边那五个 0.5 mm 间距的脚 +# 离金手指禁布区只剩 1.67 mm —— 正是 M4c 当初抬高 2.5 mm 要解决的那件事。 +# 抬 1.4 抵掉，U3 底沿回到 14.07（禁布区 11），扇出仍有 3.0 mm。 +STACK_UP = [ # U1 往上：Cin 由近到远，再是保险/TVS + ('C4', 180, 0.0), # 0402 HF，压在 VIN/GND 脚正上方 + ('C1', 180, 0.0), + ('C2', 180, 0.0), + ('C3', 180, 0.0), + ('F1', 90, 0.0), # rot=90 ⇒ p1(+12V) 朝上接 V12-L3 岛、p2(+12V_F) 朝下 +] +# 第 4 个字段 = 这一件和上一件之间的净距（缺省 STACK_GAP）。 +# ⚠ `U2` 上下要留 1.8：它是 WQFN-20，四条边都有脚，**上下两排要从 0.65 mm 的 +# 缝里横着爬出去** —— 实测这一带堵掉了 eFuse 的 6 个信号（$1N147/$1N151/ +# $1N164/EFUSE_EN/EFUSE_PG/EFUSE_FLT）。功率链在 y 上有 15 mm 富余，加得起。 +STACK_DN = [ # U1 往下：电感 → 输出电容 → eFuse → 分流 → INA + # ⚠ 这个 1.5 不是随便给的：U1 底边除了 SW(11/12) 还有 p9/p10/p13(BOOT)， + # 贴到 0.65 等于把整条边封死，那三只脚**只能横着爬**而两侧都是焊盘 —— + # 实测 `$1N136`/`$1N138` 死活出不来。1.5 给它们让出一条通道， + # SW 焊盘净距从 0.65 变 1.5，仍远小于 §7.2 的 2.0 判据。 + ('L1', 270, -0.25, 1.5), # p1(SW) 朝上正对 U1 的 SW 脚 + ('C6', 0, -0.25), + ('C7', 0, -0.25), + ('C8', 0, -0.25), # 输出 HF，接着 C6/C7 排在同一条线上 + # ⚠ M7 从 1.8 加到 2.6 / 2.4：U2 是 WQFN-20，上下两排脚要横着爬出去， + # M6 欠的 5 只脚里有 3 只（U2.15 / U2.17 / U2.2）就死在这两条缝里。 + # 功率链在 y 上还有 ~14 mm 富余（U3 底 14.06 vs 禁布区 11），加得起。 + ('U2', 180, 0.0, 2.6), # rot=180 ⇒ VO 从上边进、$1N165 从下边出 + ('Rs1', 0, -4.2, 2.4), # p2(右) 接 U2 的输出、p1(左) = VO_P 出岛 + ('U3', 180, -4.95, 1.4), # rot=180 ⇒ 9/10 脚朝上，正对 Rs1 两端（不交叉） +] +# 不进竖直堆叠、但位置由引脚决定的几件 +HAND = { + # BOOT 电容：BOOT 脚（p13）在 U1 下边、SW 也在下边，但正下方被 L1 占满了。 + # ⇒ 摆到 L1 左侧，`SW` 那一脚接 **L1 的 1 号焊盘**（同一个节点，不必绕回 U1）。 + 'C5': (PWR_X - 5.3, U1_Y - 6.3, 0), + # U1 的 p9($1N135) 旁路：p9 在下边偏右，摆到 U1 右下角外 + 'C9': (PWR_X + 3.45, U1_Y - 1.72, 0), # 和 p9 同一条水平线，2.0 mm + # TVS：竖在 Cin 堆左侧，p1(+12V_F) 朝上，和保险的出线端同一节点 + # ⚠ M7：从 U1_Y+2.5 挪到 +3.1（北移 0.6），给 `R3` 让出 U1 西边那个口袋（见下）。 + 'D1': (PWR_X - 4.2, U1_Y + 3.1, 90), + # ── 尾插那两颗（U7 ESD / U5 VBUS 开关）：J4 现在也在 B 面，排线从南边来， + # 它们只能在 J4 **北边**（插头背后）—— 交给 SVC_R 区的排布器，U7 排第一个 + # 落在区的西南角（离 J4 的 D± 脚最近）。 + # ── PCA9555：TSSOP-24，两排各 12 只脚 0.65 mm 间距 ──────────────────── + # **M7 用户拍板：挪到左下角**（原来 M7 第一版放板中央 (48,52)，更早在功率列 + # 那个拥塞口袋 (76.3,18.5)）。左下角这块 x 4~20 / y 11.6~21 本来是空的， + # 四面净空都 ≥ 2 mm，而且离侧键 MOS（`Q3~Q5` 在 x 2~5.5 / y 26~30）最近 —— + # `KEY_PWR/VUP/VDN` 三根从 M6 到现在一直是布不通的钉子户，这一挪从 70 mm 变 12 mm。 + # ⛔ **y 不能照用户拖的 10.67**：本体 8×8 ⇒ 下沿会落到 **6.67**， + # 而 y < 11 是**金手指区**，PCIe 插槽体（~9 mm 高）要从两面夹住这一段板 —— + # 放件进去装不上，几何自检会拦（`侵入金手指区`）。抬到 15.6：下沿 11.6， + # 离禁布区 0.6，离 KEY 区下沿（22）2.4。 + # ⚠ 用户拖过来时是 rot 180，**改成 rot 0**：两者都是「南北两排」， + # 差别在哪一排朝哪边 —— rot180 时 `p1~p12`（`KEY_PWR/VUP/VDN`、`INT#`、 + # `EDL_EN`、`VBUS_EN`）朝**南**，而侧键 MOS `Q3~Q5` 在**北**边（y 26~30）； + # 同时 `p13~p24`（`SDA/SCL/+3V3` + 四路状态）朝北，而金手指在**南**边。 + # 两排正好各自背对自己的去向，等于每根线都要绕整颗芯片一圈 —— M6 在功率列 + # 上就是这么丢掉 4 处的（原 `HAND` 注释里那段「转 180」说的是同一件事）。 + 'U4': (12.5, 15.6, 0), + # PCA9555 去耦 + I²C 上拉：**跟着 U4 走**，坐标由 `pin_xy()` 从板上读回的 + # U4 引脚位置现算（见该函数的说明），不手抄。 + # ⛔ `R3`（EN 分压的下臂，`$1N128`）**必须在 U1 西边**：`U1.1`(EN) 和 `p14`(BUCK_PG) + # 都在西短边，而 `BUCK_FB` 区在 U1 **东**边（那是给 FB/COMP 的，见 REGIONS 注释）。 + # 摆在东边的话这根线要绕整颗芯片 —— 布线器就是这么报「$1N128: U1.1 没布通」的， + # `place_audit.py` 也把它列在「摆错边」里。 + # 口袋是 L1 顶(47.2) / U1 西沿(86.875) / D1 南沿(50.6，已北移让路) 夹出来的那一小块。 + 'R3': (85.95, 48.8, 90), + # INA226 的 +3V3 旁路，摆在 U3 右侧（U3 上下两排脚都被 Kelvin / I2C 占着） + 'C13': (86.8, 18.0, 0), + # EDL 模拟开关：跟着 J3 走，交给 SVC_E 区排布器（U6 排第一个） + # ── 侧键 MOS：转 90° 让 3 脚（接触点盘那一路）朝上，排在 K1~K4 正下方 ── + 'Q3': (5.5, 29.9, 90), + 'Q4': (2.0, 29.9, 90), + 'Q5': (5.5, 26.1, 90), +} + + +def stack(pos, sz): + u"""把 STACK_UP / STACK_DN 按 bbox 高度自 U1 向两头堆开，返回补进去的坐标。 + + ⚠ 只用 bbox 高度 + `STACK_GAP` 算 —— 不手抄 y。改一颗件的封装， + 整条链自动重排，不会留下一个「当初算好、现在对不上」的常数。 + """ + out = {'U1': (PWR_X, U1_Y, 270)} + y = U1_Y + sz['U1'][1] / 2.0 + for item in STACK_UP: + ref, rot, dx = item[:3] + gap = item[3] if len(item) > 3 else STACK_GAP + h = sz[ref][0] if rot % 180 else sz[ref][1] + y += gap + h / 2.0 + out[ref] = (round(PWR_X + dx, 3), round(y, 3), rot) + y += h / 2.0 + y = U1_Y - sz['U1'][1] / 2.0 + for item in STACK_DN: + ref, rot, dx = item[:3] + gap = item[3] if len(item) > 3 else STACK_GAP + h = sz[ref][0] if rot % 180 else sz[ref][1] + y -= gap + h / 2.0 + out[ref] = (round(PWR_X + dx, 3), round(y, 3), rot) + y -= h / 2.0 + return out + + +# ── 分组：**顺序 = 电流/信号流向**，排布器按这个顺序摆 ────────────────── +GROUPS = [ + # (区, 组名, [位号...]) + # 功率链本体已经手排（STACK_*/HAND），这里只剩「跟着某颗 IC 走」的外围。 + ('CTRL', u'I2C 上拉 + 去耦（正常情况下由 ctrl_hand 钉在 U4 脚上）', ['C40', 'R40', 'R41']), + # ⚠ `VO_P` 泄放支路（R19 10Ω/1W + Q2）挪到**服务带左段**：它接的是 `VO_P`， + # 而 `VO_P` 在 L3 上是整块岛（服务带全覆盖），放哪一头都一样近； + # 放这里把功率列内条腾出来给 U4 的扇出带。 + ('DIS', u'VO_P 泄放支路', ['R19', 'Q2']), + # ⛔ M7 三版拆成东西两组。`U2` 是 WQFN-20，**四条边都有脚**，而 M7 二版把 12 件 + # 全塞在它西边 —— 接东边 `p17~p20`（`$1N156`/`$1N158`/`$1N151`/`EFUSE_FLT`）的 + # 四件要绕整颗芯片才够得着，U2 周围本来就只有那么几个出口，一绕就把别人也堵死 + # （M6/M7 一直布不通的 `$1N156: U2.17` 就是这么来的）。 + ('EFUSE_E', u'eFuse 东侧（p17~p20）', ['R11', 'C14', 'R12', 'R13']), + ('EFUSE_AUX', u'eFuse 西侧 + 北侧', ['R9', 'R10', 'R16', 'R17', + 'R15', 'R14', 'Q1', 'R18']), + # ⚠ FB / 补偿**必须在这个区**：它贴着 U1 的左边（FB/COMP 脚都在左长边）， + # 同时离 SW（x 87~94、y 34~42 那一块）≥ 2 mm —— §7.2 第三条「FB 远离 SW」。 + ('BUCK_FB', u'FB 分压 + 补偿 + DAC 低通', ['R1', 'R2', 'R7', 'R8', 'C12', + 'R4', 'R5', 'R6', 'C10', 'C11']), # R3 见 HAND + # ⚠ 侧键组：三颗 MOS 已手排在 K1~K4 正下方，这里只剩栅极电阻，跟着 MOS 走。 + ('KEY', u'侧键栅极电阻', ['R42', 'R43', 'R44', 'R45', 'R46', 'R47']), + ('SVC_M', u'VO_P 阻尼组 + 电池外围', ['C61', 'C62', 'C63', 'C64', 'C65', + 'R60', 'R61']), + ('SVC_R', u'尾插 USB + VBUS 外围', ['U7', 'U5', 'C66', 'C67', 'C68', 'R62', 'R64', 'R65']), + ('SVC_E', u'EDL 模拟开关', ['U6', 'R63', 'C69']), +] + +# ── 区（x0, y0, x1, y1），排布器在里面自下而上、自左而右铺 ──────────────── +# ⚠ 三个服务带小区各自贴着自己那件连接器： +# SVC_M ↔ J5(26.8,32)，SVC_R ↔ J4(56.6,33) 北边，SVC_E ↔ J3(69.9,33) 北边。 +# 区改小是故意的：范围给大了货架排布器会把件铺到离连接器 15 mm 外去。 +# ⚠ KEY 区上沿 36.6 = H1 螺钉头(4.4,38.9) 让 2.2。 +REGIONS = { + # ⚠ M7：跟着 U4 搬到板中央，落在 U4 东列（x 51.0）外侧 —— SDA/SCL 上拉 + # 就地接到 p22/p23 上，不用绕。北边到 H5(60.4,70.2) 还有 14 mm。 + # ⚠ M7 二版：跟着 U4 挪到左下角，占 U4 东边那条 4 mm 宽的缝（DIS 区从 x 21 起）。 + 'CTRL': (17.2, 12.0, 20.8, 20.5), + # ⚠ 必须落在 VO-L3 岛（x ≥ 20）里：R19 的 VO_P 脚要就地扎过孔进岛， + # 放到岛外面布线器会报「找不到落过孔的地方」。东沿 34.2 贴 C60 本体西沿 34.5。 + # ⚠ M7 上沿从 18.8 抬到 24.0（= 电池铣槽下沿 24.8 让 0.8）：节距加到 1.8 之后 + # R19(7.4×3.5) + Q2 在 6.8 高的带子里排不下第二行。 + 'DIS': (21.0, 12.0, 34.2, 24.0), + # ⚠ M7 大改：U4 搬走腾出的整块口袋都给它（原来 9.5×11.5 塞 12 件，节距 1.1）。 + # 南沿 13.0 = 金手指禁布区 11 让 2.0；东沿 84.0 给 U2 西边留 2.55 的扇出通道 + # （U2 本体西沿 86.55），M6 就是这条通道只有 1.55 才把 R11/R16 憋死的。 + # ⚠ 南沿定在 20.0 而不是 13.0：货架排布器是**自下而上**填的，y0 给到 13 + # 会把 12 件全堆到离 U2(y 27.2~31.1) 最远的那一头，ILIM/dV-dt 这些 + # 本该贴着芯片的件跑到 12 mm 外。y 13~20 那块留空，正好是 U3 底排 + # 五只 0.5 mm 间距脚往金手指方向扇出的地方。 + # `U2` 东边（本体东沿 91.45）到板边之间那条缝。上沿 33.5 让开 `C8`(y 32.3~32.9) 所在的 + # 功率链中心线；下沿 23.5 让开 `Rs1`(y 19.9~23.4)。4 件一列，顺序由「按连线就近落位」 + # 自动排成 p17→p20 的顺序（目标点精确到焊盘）。 + # ⚠ 北沿放到 36.0：目标驱动的排布器会为了靠近自己那只脚把件排在非对齐的 y 上， + # 5.4×10 的框里 4 件就可能塞不下（实测 `R13` 放不下）。东边这一条本来就是空的。 + 'EFUSE_E': (92.0, 23.0, 97.4, 36.0), + 'EFUSE_AUX': (72.3, 20.0, 84.0, 36.0), + # ⚠ FB / 补偿在 U1 的**右短边**（转 270 之后 p7=FB、p8=COMP 都在 x=+1.72 那一侧）， + # 所以这个区在 U1 右边、板边那一条 6 mm 的缝里 —— 离 SW（x 87~90）≥ 2 mm。 + # ⚠ M7 只把 y 拉长（1.4 的节距下 6.1 宽刚好两列），不动 x：再往东就是板边。 + 'BUCK_FB': (91.3, U1_Y - 8.0, 97.4, U1_Y + 15.0), + # ⚠ M7 东沿从 8.5 拉到 13.0：K1~K4 四个盘 + 三颗 MOS 已经占掉了西边这一条， + # 1.8 节距下六只栅极电阻排不进去（x 9~13 这一带本来就是空的）。 + 'KEY': (0.6, 22.0, 13.0, 38.0), + # 电池车道东沿 31.77+0.5 → 33；H4 (44.9,30.9) 螺钉头西沿 42.7。 + # ⚠ M7 三版：北沿 **45.5**（不是 50）—— `VO-L3` 岛的北叶只到 **y=46** + # （`pcb_pour.VO_LOBE`），排到 48.8 的那颗阻尼电容 `VO_P` 脚就地扎不了过孔， + # 布线器报「找不到落过孔的地方」。而且阻尼组本来就该贴着 `J5`(26.8,32)， + # 越往北越没意义。少的高度往横里补：东沿 42.5 → 44.5（H4 螺钉头的避让圈 + # 由 blockers() 兜着）。 + 'SVC_M': (33.0, 29.0, 44.5, 45.5), + # J4 北边：本体顶 34.3 + 0.6。⚠ M7 北沿收到 42.0（给 U4 的南面让出 6 mm 扇出净空）， + # 东沿从 66 收到 64.5（尾插车道东沿 66.08 之内），少的高度靠 1.8 节距下仍够 8 件。 + 'SVC_R': (47.5, 35.5, 65.5, 46.0), + # J3 正北、尾插车道（东沿 65.58）与功率列（72）之间的走廊；手机投影下（高度都 < 2） + 'SVC_E': (66.6, 36.4, 72.5, 50.0), +} + +# ⛔ 排布器的障碍**要分面**。A 面的 `J4` / `J5` / `C60` / `J2` / `J3` 挡的是 A 面， +# 把它们当成 B 面的障碍，「USB 组落在 J4 正背面」这条设计意图就永远实现不了 +# （排布器会绕开 J4 的本体框，把件推到 5 mm 以外）。 +# ⇒ 只有下面这几件对**两面**都算障碍： +# · `K1~K4`：Ø1.5 裸铜盘，B 面要在旁边扎过孔把漏极引下来，正背面得空着； +# 而且手机弹片压在上面，底下不摆件也让受力干净。 +# · `J1`：金手指，两面都是指。 +BLOCK_BOTH = ('J1', 'K1', 'K2', 'K3', 'K4') + + +def bottom_refs(pos=None): + u"""B 面件 = 全部 - TOP_ONLY。""" + d = json.load(io.open(BBOX, encoding='utf-8')) + return [r for r in (pos or d) if r not in TOP_ONLY] + + +def sizes(): + d = json.load(io.open(BBOX, encoding='utf-8')) + out = {} + for ref, v in d.items(): + w, h = BODY.get(ref, (v['w'], v['h'])) + out[ref] = (max(w, 0.6), max(h, 0.6)) + return out + + +def overlaps(r, rects): + for q in rects: + if r[0] < q[2] and q[0] < r[2] and r[1] < q[3] and q[1] < r[3]: + return True + return False + + +def blockers(): + u"""排布器的**固定障碍**：铣穿的排线槽 + 排线车道 + 七个定位孔的螺钉头避让圈。 + + ⛔ 不把它们喂进排布器，货架算法照样会往里塞件，然后自检报一堆错 —— + 窗里那几件是**摆在空气里**（内槽铣穿），孔那几件是被螺钉头压着。 + """ + out = [] + for (a, b, c, d) in B.mill_cuts(): + out.append((a - MILL_KEEP, b - MILL_KEEP, c + MILL_KEEP, d + MILL_KEEP)) + out += list(lanes().values()) + for (hx, hy) in B.phone_holes().values(): + out.append((hx - B.HOLE_KEEP, hy - B.HOLE_KEEP, + hx + B.HOLE_KEEP, hy + B.HOLE_KEEP)) + return out + + +def wh(ref, rot, sz): + u"""转 90/270 之后 bbox 的宽高要对调。**手排件全靠这一步**—— + 忘了对调，`L1`(7.6×7.0 转 90) 和 `D1`(6.8×2.2 转 90) 的占位就是错的， + 而错的方向是「看起来更小」，于是重叠检查放行、截图上却压在一起。""" + w, h = sz[ref] + return (h, w) if rot % 180 else (w, h) + + +def plan(): + u"""返回 {位号: (x, y, rot)} 和占位矩形表。""" + sz = sizes() + pos = dict(anchors()) + pos['J1'] = (B.J1_X, B.J1_Y, B.J1_ROT) + pos.update(stack(pos, sz)) # 功率链（手排，竖直堆叠） + pos.update(HAND) # 其余按引脚钉死的手排件 + pos.update(ctrl_hand(pos, sz)) # C40/R40/R41 跟着 U4 的引脚现算 + # 排布器只摆 B 面的件 ⇒ 障碍表里只放「对 B 面也成立」的东西（见 BLOCK_BOTH） + # ⛔ M7 修掉一个 M5 遗留：这里原来把 `anchors()`（J2/J3/J4/J5/C60）从障碍表里 + # 排除掉，理由是「它们在 A 面，挡的是 A 面」—— 但 M6 已经把它们全翻到 B 面了， + # 排除条件没跟着改。M6 没暴露是因为当时没有哪个区压到连接器上；M7 的 + # EFUSE_AUX 一往西扩就把 Q1 摆进了 J3 的本体里（自检那一关拦下来的）。 + # ⇒ 只要不在 TOP_ONLY 里，就是 B 面的固定障碍。 + fixed = list(BLOCK_BOTH) + sorted(set(pos) - set(TOP_ONLY)) + rects = list(blockers()) + for ref in fixed: + x, y, r = pos[ref] + w, h = wh(ref, r, sz) + rects.append((x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2)) + + # 每个区一个 y 游标：**一个组占一条完整的横带**，下一组从带子上沿重新开始。 + # 不这么做的话小件会回填到前面组的空隙里，功能级在 y 上互相咬 —— + # 后面 L3 要按「哪一段是 12V、哪一段是 VO」切铜面就切不出来了。 + cursor = {k: v[1] for k, v in REGIONS.items()} + unplaced = [] + slots = {} # {(区, 尺寸类): [(位号, (x,y))]} + peers0 = net_peers() + STEP = 0.5 # 候选格点的步长（和老版扫描一致） + for region, _name, refs in GROUPS: + x0, _y0, x1, y1 = REGIONS[region] + gap = PACK_GAP_BY_REGION.get(region, PACK_GAP) + y0 = cursor[region] + todo = [r for r in refs if r not in pos] + if not todo: + continue + # ⛔ **挑「离目标最近的空位」，不是「自下而上第一个空位」**。 + # 老版按面积从下往上塞，位置和这件连到哪儿毫无关系 —— 用户一眼看出来 + # 「没摆顺」（`U2` 东边四只脚的外围件全被塞到西边去了）。 + # 目标点由 `target_point()` 精确到**对端焊盘**给出。 + # 大件先挑（它们的目标最硬、可选位置最少），同尺寸按位号稳定排序。 + order = sorted(todo, key=lambda r: (-sz[r][0] * sz[r][1], r)) + band_top = y0 + for ref in order: + w, h = sz[ref][0] + gap, sz[ref][1] + gap + t = target_point(ref, peers0, pos, ((x0 + x1) / 2.0, (y0 + y1) / 2.0)) + best = None + yy = y0 + while yy + h <= y1 + 1e-9: + xx = x0 + while xx + w <= x1 + 1e-9: + r = (xx, yy, xx + w, yy + h) + if not overlaps(r, rects): + cx, cy = xx + w / 2, yy + h / 2 + key = ((math.hypot(cx - t[0], cy - t[1]) if t else 0.0), yy, xx) + if best is None or key < best[0]: + best = (key, r, cx, cy) + xx += STEP + yy += STEP + if best is None: + unplaced.append((ref, region)) + continue + _key, r, cx, cy = best + rects.append(r) + pos[ref] = (round(cx, 3), round(cy, 3), 0) + slots.setdefault((region, size_class(sz[ref])), []).append((ref, (round(cx, 3), round(cy, 3)))) + band_top = max(band_top, r[3]) + cursor[region] = band_top + 0.4 + peers = net_peers() + if peers: + # ⚠ 迭代 3 轮：同一组里的件互为目标点（`C68` 要贴 `U5`，而 `U5` 自己也是 + # 排布器摆的），一轮收敛不了 —— 第一轮 `C68` 按 `U5` 的**初始货架位**去靠， + # 而 `U5` 那一轮也在动。实测第 2 轮就基本不动了，第 3 轮兜底。 + for _ in range(3): + if not reassign(pos, slots, peers): + break + # ⚠ 网格微调**所有件**（含手排的功率链）：0.5 mm 间距的 QFN 不落在 0.25 格点上时， + # 相邻两只脚的出线只能挤到 0.25，比净距（0.15+0.16）还窄，布线器就报「出不来」。 + # `U2.19` / `U1.1` 都是这么卡住的。挪完再逐对校核净距，破了 GAP 的**退回去**。 + before = dict(pos) + grid_snap(pos) + # ⚠ 退回要**迭代到不动为止**：退回 A 会让它和「已经挪过、没退回」的 B 之间重新变窄 + # （实测 C1 退回、C2 没退，缝从 0.65 变 0.55，自检报重叠）。 + done = set() + for _ in range(6): + bad = snap_conflicts(pos, sz) - done + if not bad: + break + for ref in bad: + pos[ref] = before[ref] + done |= bad + return pos, rects, unplaced, sz + + +def u4_local_pins(): + u"""从 `_blade_pads.json` 读回 `U4` 24 只脚**相对质心**的局部偏移 {脚号: (dx, dy)}。 + + TSSOP 两排脚对称 ⇒ 质心就是本体中心，不需要另外知道当初摆在哪。 + ⚠ 这份文件是**上一次下发之后 dump 的**：改了 `U4` 的旋转角要先 + `pcb_route.py --dump` 再重跑一次 `--push`（两趟收敛），否则下面 + `ctrl_hand()` 会认出「排布方向对不上」并退回给货架排布器。 + """ + if not os.path.exists(PADS_JSON): + return {} + d = [r for r in json.load(io.open(PADS_JSON, encoding='utf-8')) if r[0] == 'U4'] + if len(d) != 24: + return {} + cx = sum(r[2] for r in d) / len(d) + cy = sum(r[3] for r in d) / len(d) + return {r[1]: (round(r[2] - cx, 3), round(r[3] - cy, 3)) for r in d} + + +def ctrl_hand(pos, sz=None): + u"""`C40` / `R40` / `R41` 跟着 `U4` 的引脚现算位置 —— 不手抄坐标。 + + · `C40` 100nF 去耦要贴 `p24(+3V3)` / `p21(GND)`：交给货架排布器它会落到区角上、 + 离电源脚 5 mm 以上，去耦离得远等于没有。 + · `R40` / `R41` I²C 上拉贴 `p22(SCL)` / `p23(SDA)`。 + + ⛔ 三件不能各自贴各自的脚：`p22/p23/p24` 相邻只差 **0.65 mm**，而 0402 加装配净距 + 要 2 mm 才排得下 —— 第一版就是这么写的，自检直接报三处重叠。 + ⇒ 排成**一排**，间距 `ROW_PITCH`，整排贴在 `U4` 本体那一侧的外面 + （`本体半宽 + GAP + 件的半高`，从 `BODY['U4']` 现算，不写死）。 + + 排布方向（南北两排 / 东西两列）从局部偏移反推，和计划的 rot 对不上就返回空， + 让这三件回到 `CTRL` 区由排布器摆（下一趟 `--dump` + `--push` 自动归位）。 + """ + lp = u4_local_pins() + if not lp or 'U4' not in pos: + return {} + ux, uy, urot = pos['U4'] + rows = len(set(round(v[1], 2) for v in lp.values())) == 2 # 南北两排 + if rows != (urot % 180 == 0): + print(u' [!] _blade_pads.json 里 U4 还是上一版的朝向，C40/R40/R41 先交给排布器；' + u'跑一次 pcb_route.py --dump 再 --push 就归位') + return {} + ROW_PITCH = 2.2 + sz = sz or sizes() + half_u = (BODY['U4'][1] if rows else BODY['U4'][0]) / 2.0 + items = [('C40', '24'), ('R41', '23'), ('R40', '22')] # 顺序 = 脚的顺序 + pins = [lp[q] for _r, q in items if q in lp] + if len(pins) != len(items): + return {} + out = {} + # 整排放在这几只脚所在的那一侧外面；件转 90°（长边垂直于本体边），半高 0.67 + side = 1.0 if (pins[0][1] if rows else pins[0][0]) > 0 else -1.0 + # ⚠ 半高要按**转 90° 之后**的 bbox 取（0402 转 90 是 0.54 宽 × 1.43 高，半高 0.715）—— + # 写死 0.67 的那一版差 0.045 mm，自检报「R41 和 U4 重叠」。 + half_sat = max(wh(r, 90 if rows else 0, sz)[1 if rows else 0] + for r, _q in (('C40', '24'), ('R41', '23'), ('R40', '22'))) / 2.0 + # ⚠ 试过「贴引脚排而不是本体框」（想把这三件塞到 U4 南边、脚的正下方）：**不行**。 + # TSSOP 的焊盘本身长 ~1.5 mm，脚心 ±3.02 加上焊盘就是 ±3.8，再加净距和件的半高， + # 南边那一排会落到 y≈11.3 —— 而金手指禁布区上沿是 11.0，等于贴着禁区边缘， + # 自检直接报「和 U4 重叠」。⇒ 仍按**本体框**让开，靠下面的退路走西边。 + off = half_u + GAP + half_sat + ctr = sum((q[0] if rows else q[1]) for q in pins) / len(pins) + # 首选：贴着这三只脚所在的那条边，排成一排。 + cand = [] + for k, (ref, _q) in enumerate(items): + t = ctr + (k - (len(items) - 1) / 2.0) * ROW_PITCH + cand.append((ref, (round(ux + t, 3), round(uy + side * off, 3), 90) if rows + else (round(ux + side * off, 3), round(uy + t, 3), 0))) + # ⛔ 但这一排可能落进禁区：U4 挪到左下角之后，`p13~p24` 那条边朝南， + # 往南 5.3 mm 就是**金手指区**（y < 11，插槽体要夹住）。 + # ⇒ 退到**垂直的那条边**（离板边近的一侧），y 对齐引脚排，横着堆。 + lim = B.ZONES['finger'][3] + 0.3 + if rows and min(c[1][1] for c in cand) - 0.72 < lim: + sx = -1.0 if ux < B.BW / 2.0 else 1.0 + py = uy + (pins[0][1] if rows else 0.0) # 引脚排的 y + cand = [(ref, (round(ux + sx * off, 3), + round(py + k * ROW_PITCH, 3), 0)) + for k, (ref, _q) in enumerate(items)] + return dict(cand) + + +# ── M7：按连线就近落位（货架排完之后，在**同尺寸**的位置之间重排）──────── +PADS_JSON = os.path.join(HERE, '_blade_pads.json') +SNAP_JSON = os.path.join(HERE, '_blade_pad_offsets.json') +GRID = 0.25 # 和 router.py 的网格一致 +# 平面网 / 巨网：不参与「往哪儿靠」的计算 +# GND / VO_P / +12V 走铜面（`router.py` 的 SKIP / PLANE_VIA_NETS / ISLAND_NETS）， +# 把它们算进去等于把所有件都往铜面中心拽，没有意义。 +PLANE_NETS = ('GND', 'VO_P', '+12V', '+12V_F') + + +def size_class(wh_): + u"""重排时哪些件可以互换位置。 + + ⛔ 不能按「尺寸完全相同」分类：`C14`(1.88×0.54) 和 `R12`(1.43×0.54) 差 0.45 mm + 就换不了位置了，于是 `U2` 东侧那一列排成 p17→p19→p18→p20，两根线白白交叉一次。 + ⇒ 只要都是**小贴片**（≤ 2.5 × 1.5）就归一类：货架格子是按 1.8 的节距留的 + （1.43 + 1.8 = 3.23），塞个 1.88 的件进去仍有 1.35 的富余， + 而真挤到了自检那一关（同面重叠，净距 0.6）会拦下来。 + """ + w, h = wh_ + if w <= 2.5 and h <= 1.5: + return 'SMALL' + if h <= 2.5 and w <= 1.5: + return 'SMALL90' + return wh_ + + +def net_peers(): + u"""{位号: [(网名, [(对端位号, 焊盘局部偏移 dx, dy), ...])]}，从 `_blade_pads.json` 反查。 + + ⚠ 存的是**对端焊盘相对它自己本体中心的偏移**，不是绝对坐标 —— 焊盘表是上一次 + 下发之后 dump 的，绝对坐标会过期；局部偏移只跟封装和旋转角有关。本体中心用 + 该件所有焊盘的**质心**近似（两排对称的封装上就是精确值）。 + + ⛔ 为什么非要精确到**焊盘**：按「器件中心」算目标点的话，`U2` 周围那 12 个外围件 + 的目标点全是同一个点，谁摆哪儿都一样 —— 排出来就是「没摆顺」：接东边 + `p17~p20` 的件被扔到西边去，线要绕整颗芯片一圈。精确到焊盘之后 + `R11`→`p17`、`C14`→`p18`、`R12`→`p19`、`R13`→`p20`，一列排下来顺序自然就对。 + """ + if not os.path.exists(PADS_JSON): + return {} + d = json.load(io.open(PADS_JSON, encoding='utf-8')) + cen = {} + for row in d: + cen.setdefault(row[0], []).append((row[2], row[3])) + npin = {r: len(ps) for r, ps in cen.items()} + cen = {r: (sum(p[0] for p in ps) / len(ps), sum(p[1] for p in ps) / len(ps)) + for r, ps in cen.items()} + bynet = {} + for row in d: + ref, net = row[0], row[7] + if not net or net in PLANE_NETS: + continue + cx, cy = cen[ref] + bynet.setdefault(net, []).append((ref, round(row[2] - cx, 3), round(row[3] - cy, 3), + npin[ref])) + out = {} + for net, items in bynet.items(): + for r in set(it[0] for it in items): + others = [it for it in items if it[0] != r] + if others: + out.setdefault(r, []).append((net, others)) + return out + + +def target_point(ref, peers, pos, ref_pt=None): + u"""这个件「该往哪儿去」：每个网取**离参考点最近的那个对端焊盘**，再按网平均。 + + 对端焊盘位置 = 对端件在本次方案里的中心 + 它的焊盘局部偏移 ⇒ 不吃过期坐标。 + + ⛔ 不用「同网所有对端焊盘的质心」：`C66` 是 `U5` 的 `+5V` 输入电容，而 `+5V` 这个网上 + 还挂着金手指 `J1.A19/A32`（在板子最南边）—— 质心被拽到 10 mm 外， + 排出来「去耦离电源脚 9.9 mm」。取**最近的那一个**才是人排板的做法： + 旁路电容跟着芯片的那只脚走，不管这个网还去了哪儿。 + + `ref_pt` 是「从哪儿看最近」，一般给所在区的中心；不给就用件当前位置（若已摆）。 + """ + if ref not in peers: + return None + if ref_pt is None: + ref_pt = pos.get(ref, (0.0, 0.0))[:2] + xs, ys = [], [] + for _net, others in peers[ref]: + cand = [(pos[q][0] + dx, pos[q][1] + dy, n) for q, dx, dy, n in others if q in pos] + if not cand: + continue + # ⛔ 有芯片对端时**只认芯片**：`C11` 是 `U1` 的补偿电容，同网还挂着 `R6`， + # 按「最近的对端」会跟着 `R6` 跑到 9 mm 外。旁路 / 补偿件要跟着**芯片的那只脚**。 + ic = [c for c in cand if c[2] >= 4] + pick = ic or cand + q = min(pick, key=lambda c: math.hypot(c[0] - ref_pt[0], c[1] - ref_pt[1])) + xs.append(q[0]) + ys.append(q[1]) + if not xs: + return None + return (sum(xs) / len(xs), sum(ys) / len(ys)) + + +def reassign(pos, slots, peers): + u"""在**同一区、同一尺寸**的一组货架位置之间重排，让每件离自己的对端更近。 + + 先贪心（按「最想去的位置」排序取），再做 2-opt 交换到不能再降。 + 位置只在同尺寸之间换 —— 换了尺寸货架占位就错了，而**几何自检抓不到** + （它只看重叠，不看这个位置当初是给谁留的）。 + """ + moved = 0 + for (region, cls), items in sorted(slots.items(), key=lambda kv: (kv[0][0], str(kv[0][1]))): + if len(items) < 2: + continue + refs = [r for r, _xy in items] + pts = [xy for _r, xy in items] + tgt = {r: target_point(r, peers, pos) for r in refs} + if not any(tgt.values()): + continue + + def cost(assign): + c = 0.0 + for r, k in assign.items(): + t = tgt.get(r) + if t: + c += math.hypot(pts[k][0] - t[0], pts[k][1] - t[1]) + return c + + order = sorted(range(len(refs)), key=lambda i: -(1 if tgt[refs[i]] else 0)) + assign, used = {}, set() + for i in order: + r = refs[i] + t = tgt.get(r) + cand = sorted((k for k in range(len(pts)) if k not in used), + key=lambda k: (math.hypot(pts[k][0] - t[0], pts[k][1] - t[1]) + if t else k)) + assign[r] = cand[0] + used.add(cand[0]) + improved = True + while improved: + improved = False + for a in range(len(refs)): + for b in range(a + 1, len(refs)): + ra, rb = refs[a], refs[b] + c0 = cost(assign) + assign[ra], assign[rb] = assign[rb], assign[ra] + if cost(assign) < c0 - 1e-9: + improved = True + else: + assign[ra], assign[rb] = assign[rb], assign[ra] + for r, k in assign.items(): + if pos[r][:2] != pts[k]: + moved += 1 + pos[r] = (pts[k][0], pts[k][1], pos[r][2]) + return moved + + +def grid_snap(pos, only=None): + u"""把货架排布器摆的件各挪 ≤ ±0.125 mm，让焊盘尽量落在 **0.25 mm 布线网格**上。 + + `router.py` 是 0.25 网格 A*，焊盘不在格点上就要先长一段**引出脚**； + M6 欠的 5 只脚全是「出口被自家邻脚的引出脚封死」（方案 §26.6）。 + 焊盘落到格点上，这一类堵塞就没有了。 + + ⚠ 一个件只有一个 (dx, dy)：**只有焊盘间距是 0.25 的整数倍时才能全对齐** + （0402 两脚共线 ⇒ 能对齐一只；QFN 0.5 ⇒ 整排都能；TSSOP 0.65 / BM24 0.4 ⇒ 不能）。 + 判据是「对齐数变多」，不是「全对齐」。 + + ⛔ 手排件（功率链 `STACK_*` / `HAND`）和机械锚定件不许动： + 前者的净距是按 §7.2 的回路算死的（Cin 堆只有 0.65），两件相向挪 0.125 就破 0.6 的装配下限； + 后者的位置是小米8 主板定的。 + """ + if not os.path.exists(SNAP_JSON): + return 0 + offs = json.load(io.open(SNAP_JSON, encoding='utf-8')) + n = 0 + for ref, po in offs.items(): + if ref not in pos or (only is not None and ref not in only): + continue + x, y, r = pos[ref] + + def best(vals): + bd, bs = 0.0, None + for k in range(-125, 126): + d = k / 1000.0 + sc = sum(abs((v + d) / GRID - round((v + d) / GRID)) for v in vals) + if bs is None or sc < bs - 1e-9: + bd, bs = d, sc + return bd + + dx = best([x + o[0] for o in po]) + dy = best([y + o[1] for o in po]) + if dx or dy: + pos[ref] = (round(x + dx, 3), round(y + dy, 3), r) + n += 1 + return n + + +def snap_conflicts(pos, sz): + u"""网格微调之后，哪些件把净距挤到了 `GAP` 以下 —— 这些退回原位。 + + ⛔ 不能一刀切「手排件不许动」：`U2` / `U1` 这些 0.5 间距的 QFN 恰恰**最需要** + 落在格点上。也不能一刀切「都动」：Cin 堆的缝只有 0.65，两件相向挪 0.125 就破 0.6。 + ⇒ 挪完再算一遍，只把真挤到的退回去。 + """ + bad = set() + items = sorted(pos.items()) + rect = {} + for ref, (x, y, r) in items: + w, h = wh(ref, r, sz) + rect[ref] = (x - w / 2, y - h / 2, x + w / 2, y + h / 2) + for i in range(len(items)): + for j in range(i + 1, len(items)): + a, b = items[i][0], items[j][0] + ra, rb = rect[a], rect[b] + dx = max(ra[0] - rb[2], rb[0] - ra[2]) + dy = max(ra[1] - rb[3], rb[1] - ra[3]) + if dx < GAP and dy < GAP and (dx < 0 or dy < 0 or True): + if max(dx, dy) < GAP: + bad.add(a) + bad.add(b) + return bad + + +def bands(): + u"""每个组占的 y 带 —— L3 切铜面按这个来，别手抄坐标。""" + pos, _r, _u, sz = plan() + out = [] + for region, name, refs in GROUPS: + ys = [(pos[r][1] - wh(r, pos[r][2], sz)[1] / 2, + pos[r][1] + wh(r, pos[r][2], sz)[1] / 2) for r in refs if r in pos] + if ys: + out.append((region, name, round(min(a for a, _ in ys), 2), + round(max(b for _, b in ys), 2))) + return out + + +def selfcheck(pos, rects, unplaced, sz): + bad = [] + if unplaced: + bad.append(u'放不下: %s' % ', '.join(u'%s(%s)' % t for t in unplaced)) + d = json.load(io.open(BBOX, encoding='utf-8')) + missing = sorted(set(d) - set(pos)) + if missing: + bad.append(u'没安排位置: %s' % ' '.join(missing)) + bot = set(bottom_refs(pos)) + # 重叠。⚠ K1~K4 例外：四个盘的位置是**主板定的**（实测最小间距 1.78 mm、 + # 盘 Ø1.5 ⇒ 净距 0.28），通用的 GAP=0.6 会把它们互判成重叠。 + # 它们之间改按「铜净距 ≥ 0.2」单独校核。 + # ⚠ **只判同一面**：A 面的 J4/J5/C60 和 B 面的 USB/阻尼组是**故意重叠**的 + # （正背面），跨面判重叠会把这一版的核心设计意图全报成错。 + import math + keys = ['K1', 'K2', 'K3', 'K4'] + rmap = {} + for ref in pos: + if ref in keys: + continue + x, y, rr = pos[ref] + w, h = wh(ref, rr, sz) + rmap[ref] = (x - w / 2 - GAP / 2, y - h / 2 - GAP / 2, + x + w / 2 + GAP / 2, y + h / 2 + GAP / 2) + rl = sorted(rmap.items()) + for i in range(len(rl)): + for j in range(i + 1, len(rl)): + if (rl[i][0] in bot) != (rl[j][0] in bot): + continue + a, b = rl[i][1], rl[j][1] + if a[0] < b[2] - 1e-6 and b[0] < a[2] - 1e-6 and \ + a[1] < b[3] - 1e-6 and b[1] < a[3] - 1e-6: + bad.append(u'%s 和 %s 重叠' % (rl[i][0], rl[j][0])) + PAD_D = 1.5 + for i in range(len(keys)): + for j in range(i + 1, len(keys)): + ax, ay, _ = pos[keys[i]] + bx, by, _ = pos[keys[j]] + gap = math.hypot(ax - bx, ay - by) - PAD_D + if gap < 0.2: + bad.append(u'%s/%s 铜净距 %.2f < 0.2' % (keys[i], keys[j], gap)) + # 全部在板内 + for ref, (x, y, rr) in pos.items(): + w, h = wh(ref, rr, sz) + if ref == 'J1': + continue + if x - w / 2 < 0.5 or x + w / 2 > B.BW - 0.5 or \ + y - h / 2 < 0.5 or y + h / 2 > B.BH - 0.5: + bad.append(u'%s 出板框: (%.2f,%.2f) %.1fx%.1f' % (ref, x, y, w, h)) + # 金手指区（y<11）除 J1 外一件不许有 —— 两面都是（插槽体夹住的是整块板） + for ref, (x, y, rr) in pos.items(): + if ref == 'J1': + continue + if y - wh(ref, rr, sz)[1] / 2 < 11.0: + bad.append(u'%s 侵入金手指区（y=%.2f，插槽体要 ~9 mm）' % (ref, y)) + # ⛔ 铣穿的排线槽：**两面都不许有件**（摆进去等于摆在空气里）； + # B 面的排线车道也一件不放（排线要平贴着走到连接器）。 + for ref, (x, y, rr) in pos.items(): + w, h = wh(ref, rr, sz) + for (a, b, c, d2) in B.mill_cuts(): + if x + w / 2 > a - MILL_KEEP and x - w / 2 < c + MILL_KEEP and \ + y + h / 2 > b - MILL_KEEP and y - h / 2 < d2 + MILL_KEEP: + bad.append(u'%s 落进铣穿的排线槽（那里没有板子）' % ref) + break + if ref in bot and ref not in ('J4', 'J5'): + for k, (a, b, c, d2) in lanes().items(): + if x + w / 2 > a and x - w / 2 < c and y + h / 2 > b and y - h / 2 < d2: + bad.append(u'%s 压在 %s 排线车道上' % (ref, k)) + break + # A 面的手机投影里只许 K1~K4（螺柱间隙只有 1.0 mm）。 + # ⚠ **B 面不受这一条约束** —— 这正是这一版把器件翻过去的原因。 + px0, py0 = PHONE_ORG + px1, py1 = px0 + PHONE_WH[0], py0 + PHONE_WH[1] + for ref, (x, y, rr) in pos.items(): + if ref.startswith('K') or ref in bot: + continue + w, h = wh(ref, rr, sz) + if x + w / 2 > px0 and x - w / 2 < px1 and y + h / 2 > py0 and y - h / 2 < py1: + bad.append(u'%s 在 A 面落进手机投影（螺柱间隙只有 1.0 mm）' % ref) + # ⛔ B 面高度预算分两段（模块头的表）。超高件进手机投影会顶到隔壁槽的手机主板， + # 而这件事几何自检和 DRC **一条都不报**。 + for ref, hh in HEIGHT.items(): + if ref not in bot: + continue + x, y, rr = pos[ref] + w, h = wh(ref, rr, sz) + in_phone = y + h / 2 > py0 and x + w / 2 > px0 and x - w / 2 < px1 + lim = H_B_PHONE if in_phone else H_B_SVC + if hh > lim: + bad.append(u'%s 高 %.1f mm 放在 B 面%s（净空只有 %.1f）' + % (ref, hh, u'手机投影下' if in_phone else u'服务带', lim)) + # ⛔ 螺钉头避让：任何元件离主板定位孔中心都要 >= HOLE_KEEP。 + # M4c 第一版把这七个孔整个忘了 —— 高度预算和 K1~K4 的接触压力全靠它们。 + # ⚠ 两面都要让：螺钉过孔是 NPTH，头在 B 面、尼龙立柱在 A 面。 + for hname, (hx, hy) in B.phone_holes().items(): + for ref, (x, y, rr) in pos.items(): + w, h = wh(ref, rr, sz) + dx = max(abs(hx - x) - w / 2.0, 0.0) + dy = max(abs(hy - y) - h / 2.0, 0.0) + if math.hypot(dx, dy) < B.HOLE_KEEP: + bad.append(u'%s 离定位孔 %s 只有 %.2f < %.1f（螺钉头压上去）' + % (ref, hname, math.hypot(dx, dy), B.HOLE_KEEP)) + # C60 不许在手机底下（已由上一条覆盖），另外校核它确实在服务带/功率列 + cx, cy, _ = pos['C60'] + if not (12.0 <= cy - BODY['C60'][1] / 2 and cy + BODY['C60'][1] / 2 <= 28.0): + bad.append(u'C60 不在服务带里（B 面只有服务带有 18.7 的净空）') + return bad + + +OPEN_JS = (u"await eda.dmt_EditorControl.openDocument('%s');" + u"await new Promise(r=>setTimeout(r,2500));") + +# ⚠ **必须分批**：桥接服务端的单请求上限是**硬编码的 30 s** +# （`bridge-server.mjs` 的 `REQUEST_TIMEOUT_MS`，客户端 `timeout=` 调不动它）。 +# 83 件 × 2 次 modify 一口气发过去必超时，而且**超时不等于没执行** —— +# 客户端还在跑，只是结果回不来，于是「读回校验」会看到做了一半。 +PUSH_JS = u""" +const MIL = %s, P = %s, BOT = %s, ONLY = %s; +const bot = new Set(BOT), only = new Set(ONLY); +let n = 0, miss = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const d = c.designator; + if (!only.has(d)) continue; + if (!P[d]) { miss.push(d); continue; } + const id = c.getState_PrimitiveId(); + await eda.pcb_PrimitiveComponent.modify(id, {layer: bot.has(d) ? 2 : 1}); + await eda.pcb_PrimitiveComponent.modify(id, + {x: P[d][0]*MIL, y: P[d][1]*MIL, rotation: P[d][2]}); + n++; +} +await eda.pcb_Document.save(); +return {n, miss}; +""" + +BATCH = 12 + + +def push(pos): + r = run(OPEN_JS % PCB + 'return 1;', timeout=120) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + bot = json.dumps(bottom_refs(pos)) + refs = sorted(pos) + done, miss = 0, [] + for k in range(0, len(refs), BATCH): + chunk = refs[k:k + BATCH] + r = run(PUSH_JS % (MIL, json.dumps(pos), bot, json.dumps(chunk)), timeout=120) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + done += r['result']['n'] + miss += r['result']['miss'] + print(u' %d/%d' % (done, len(refs))) + print(u'已摆 %d 件；没找到位置的: %s' % (done, miss or u'无')) + + +def verify(pos, sz): + r = run("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" + "return (await eda.pcb_PrimitiveComponent.getAll()).map(" + " c=>[c.designator, c.x, c.y, c.rotation, c.layer]);" % PCB, timeout=300) + if not r.get('success'): + sys.exit(json.dumps(r, ensure_ascii=False)[:600]) + got = {a[0]: (a[1] / MIL, a[2] / MIL, a[3], a[4]) for a in r['result']} + bot = set(bottom_refs(pos)) + bad = [] + for ref, (x, y, rot) in pos.items(): + if ref not in got: + bad.append(u'板上没有 %s' % ref) + continue + gx, gy, grot, glay = got[ref] + if abs(gx - x) > 0.02 or abs(gy - y) > 0.02: + bad.append(u'%s 在 (%.2f,%.2f)，应为 (%.2f,%.2f)' % (ref, gx, gy, x, y)) + want_lay = 2 if ref in bot else 1 + if glay != want_lay: + bad.append(u'%s 在 layer %s，应为 %s' % (ref, glay, want_lay)) + print(u'读回 %d 件（A 面 %d / B 面 %d）' + % (len(got), sum(1 for v in got.values() if v[3] == 1), + sum(1 for v in got.values() if v[3] == 2))) + if bad: + print(u'[X] %d 条不过:' % len(bad)) + for b in bad[:20]: + print(u' ' + b) + else: + print(u'[OK] %d 件位置 / 层 全部对上' % len(got)) + return bad + + +if __name__ == '__main__': + pos, rects, unplaced, sz = plan() + bad = selfcheck(pos, rects, unplaced, sz) + bot = set(bottom_refs(pos)) + print(u'安排了 %d 件（含 J1）：A 面 %d / B 面 %d' + % (len(pos), len(pos) - len(bot), len(bot))) + for region, name, refs in GROUPS: + xs = [pos[r] for r in refs if r in pos] + if xs: + print(u' %-11s %-24s x %5.1f~%5.1f y %5.1f~%5.1f %d 件' + % (region, name, min(p[0] for p in xs), max(p[0] for p in xs), + min(p[1] for p in xs), max(p[1] for p in xs), len(xs))) + print(u' A 面留守: ' + ' '.join(u'%s(%.1f,%.1f)' % (k, pos[k][0], pos[k][1]) + for k in TOP_ONLY)) + if bad: + print(u'[X] 自检不过 (%d):' % len(bad)) + for b in bad[:20]: + print(u' ' + b) + if '--push' in sys.argv: + sys.exit(1) + else: + print(u'[OK] 自检通过：同面无重叠 / 全在板内 / 金手指区干净 / 槽与车道内无件 /' + u' A 面只有 K1~K4 / B 面高度分段达标 / 七个螺钉头都让开了') + if '--push' in sys.argv: + push(pos) + verify(pos, sz) + elif '--verify' in sys.argv: + verify(pos, sz) diff --git a/.claude/r2/pcb_pour.py b/.claude/r2/pcb_pour.py new file mode 100644 index 0000000..ba3854e --- /dev/null +++ b/.claude/r2/pcb_pour.py @@ -0,0 +1,402 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 的铺铜（M4c-3）。 + + /c/Python314/python .claude/r2/pcb_pour.py # 只算 + 自检 + /c/Python314/python .claude/r2/pcb_pour.py --push # 清旧铜面 + 重建 + 重填 + /c/Python314/python .claude/r2/pcb_pour.py --rebuild # 只重填（铜面没改，只是扇出/布线改了） + +## 叠层（方案 §7.1） + +| 设计 | EasyEDA | id | 内容 | +|---|---|---|---| +| L1 | Top Layer | 1 | 功率 + 信号；**D± 走这层、以 L2 为参考** | +| L2 | Inner1 | 15 | **完整地平面，不许割断** | +| L3 | Inner2 | 16 | `VO_P` 岛 + `+12V` 岛，其余 GND 底填 | +| L4 | Bottom | 2 | 控制信号 + GND 底填 | + +## 三个只有这块板才有的约束 + +1. **金手指区不许铺外层铜**：`J1` 的 64 个指是 L1/L2 上的焊盘，间距只有 0.3 mm。 + 外层铜面一旦下探到 y < 指顶(5.6)+间距，就会把相邻的指连起来 —— 而且**是不是短路 + 要看它连到哪两根**，DRC 只报间距不报「这两根本来就该分开」。 + ⇒ 外层铜面一律 `y >= TOP_POUR_Y`（11.5，比缺口顶 7.45 还高一截）。 + 内层（L2/L3）没有指，可以一直铺到板边内缩，只要避开缺口。 + +2. **缺口要挖掉**：防呆缺口是真的铣穿的，四层都要让开（含 0.5 mm 内缩）。 + +3. **优先级是「数字小的先铺、先占地盘」**（R1 `pcb_pour.py` 头上那条已经查清的翻案）。 + ⇒ `VO_P` / `+12V` 两个岛给 1 / 2，GND 底填给 9。 + +## 三个 API 坑（全部照抄 R1 `pcb_pour.py` 的结论，别再踩一遍） + +· 多边形**必须显式闭合**（末尾把首点再写一遍），否则 `create()` 一块都不建； +· `create()` **抛异常不等于失败** —— 判据只能是建完 `getAll()` 按名字（会被转成大写）核对； +· `rebuildCopperRegion()` 是坏的，**只能走 GUI**：工具 → 铺铜管理器... → 重建所有 → 确认。 + 判据是 `pcb_PrimitivePoured` 的数量，不是 `pcb_PrimitivePour`。 +""" +import json +import math +import os +import sys +import time + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 +import fp_edge # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +L_TOP, L_GND, L_PWR, L_BOT = 1, 15, 16, 2 + +INSET = 0.5 # 铜面离板边 +TOP_POUR_Y = 11.5 # 外层铜面的下沿（金手指区一点外层铜都不许有） +NOTCH_KEEP = 0.5 # 缺口周围再让 0.5 + +# L3 两个岛（x0, y0, x1, y1）—— y 段直接对着 pcb_place 的功能带切，见 --bands +VO_ISLAND = (20.0, 11.5, 97.5, 28.8) # eFuse/检流带 + 服务带：VO_P 4 A 的主通道 +# 2026-09-09 M6：J5 / 阻尼组挪到电池槽北边（y 29~40）之后岛要跟过去 —— 往北伸一个 +# 叶（L 形单环，不是第二块铜）。东沿 46 让开尾插槽 46.58；电池槽本身由挖槽区域反焊盘让开。 +VO_LOBE = (20.0, 28.8, 46.0, 46.0) +V12_ISLAND = (84.0, 55.0, 97.5, 74.0) # 12V 入口（F1 的 +12V 脚）及以上；新摆位后功率链上端只占 x 83~93 + + +def mil(v): + return round(v * MIL, 4) + + +def rrect(x0, y0, x1, y1, r=0.0, seg=8): + u"""圆角矩形点列（逆时针，闭合）。r=0 就是普通矩形。""" + if r <= 0: + pts = [(x0, y0), (x1, y0), (x1, y1), (x0, y1)] + else: + pts = [] + for cx, cy, a0 in ((x1 - r, y0 + r, 270), (x1 - r, y1 - r, 0), + (x0 + r, y1 - r, 90), (x0 + r, y0 + r, 180)): + for k in range(seg + 1): + a = math.radians(a0 + 90.0 * k / seg) + pts.append((cx + r * math.cos(a), cy + r * math.sin(a))) + out = [pts[0]] + for p in pts[1:]: + if abs(p[0] - out[-1][0]) > 1e-9 or abs(p[1] - out[-1][1]) > 1e-9: + out.append(p) + out.append(out[0]) # ⚠ 必须显式闭合 + return out + + +def notch_cut(): + u"""缺口在铜面里要挖掉的矩形（含让位）。""" + ml, mr = B.notch_break() + return (ml - NOTCH_KEEP, -1.0, mr + NOTCH_KEEP, fp_edge.NOTCH_D + NOTCH_KEEP) + + +def inner_poly(): + u"""内层铜面：板框内缩 INSET，底边在缺口处绕过去（一条闭合折线，不用挖孔）。""" + d = INSET + r = B.CORNER_R - d + x0, y0, x1, y1 = d, d, B.BW - d, B.BH - d + nx0, _ny0, nx1, ny1 = notch_cut() + pts = [(nx1, y0)] # 缺口右侧起步，沿底边往右 + pts.append((x1 - r, y0)) + for cx, cy, a0 in ((x1 - r, y0 + r, 270), (x1 - r, y1 - r, 0), + (x0 + r, y1 - r, 90), (x0 + r, y0 + r, 180)): + for k in range(9): + a = math.radians(a0 + 90.0 * k / 8) + pts.append((cx + r * math.cos(a), cy + r * math.sin(a))) + pts.append((nx0, y0)) # 底边左段走到缺口左沿 + pts.append((nx0, ny1)) # 绕缺口 + pts.append((nx1, ny1)) + out = [pts[0]] + for p in pts[1:]: + if abs(p[0] - out[-1][0]) > 1e-9 or abs(p[1] - out[-1][1]) > 1e-9: + out.append(p) + out.append(out[0]) + return out + + +def outer_poly(): + u"""外层铜面：只在 y >= TOP_POUR_Y 的部分，金手指区一点铜都没有。""" + d = INSET + r = B.CORNER_R - d + x0, x1, y1 = d, B.BW - d, B.BH - d + pts = [(x0, TOP_POUR_Y), (x1, TOP_POUR_Y)] + for cx, cy, a0 in ((x1 - r, y1 - r, 0), (x0 + r, y1 - r, 90)): + for k in range(9): + a = math.radians(a0 + 90.0 * k / 8) + pts.append((cx + r * math.cos(a), cy + r * math.sin(a))) + out = [pts[0]] + for p in pts[1:]: + if abs(p[0] - out[-1][0]) > 1e-9 or abs(p[1] - out[-1][1]) > 1e-9: + out.append(p) + out.append(out[0]) + return out + + +def src(pts): + u"""点列 -> TPCB_PolygonSourceArray（mil）: x1 y1 'L' x2 y2 'L' ...""" + a = [mil(pts[0][0]), mil(pts[0][1])] + for p in pts[1:]: + a += ['L', mil(p[0]), mil(p[1])] + return a + + +def gnd_tiles(y_lo): + u"""地铜的**若干块单环矩形**，绕开铣穿的排线槽。 + + ⛔ **不能用带洞的复杂多边形**：`pcb_MathPolygon.createComplexPolygon()` 传多个环时 + 会把客户端挂死 —— 请求 30 s 超时、铺铜边框停在半路、进度恒为 0/0， + 和「GUI 按钮失灵」完全无法区分（2026-09-08 在这上面绕了很久）。 + ⇒ 一律单环。要挖洞就拆成几块矩形拼，铜面之间同网互相接壤会自然连成一片。 + + 做法：按所有槽的 x 边把板切成竖条，每条里按 y 找槽之间的空隙。 + （2026-09-09 改：原来的「上下横带」写法假设各窗 y 区间不重叠，两条并排的排线槽 + 会把槽本身当成一条带铺进去。） + `y_lo` = 这一层铜面的下沿（外层 11.5 / 内层 0.5）。 + """ + d = INSET + x0, x1 = d, B.BW - d + y1 = B.BH - d + cuts = [(a - INSET, b - INSET, c + INSET, e + INSET) for (a, b, c, e) in B.mill_cuts()] + xs = sorted(set([x0, x1] + [v for c in cuts for v in (c[0], c[2])])) + tiles = [] + for xa, xb in zip(xs, xs[1:]): + if xb - xa < 0.6: + continue + ys = [y_lo] + for c in sorted(cuts, key=lambda c: c[1]): + if c[0] < xb - 1e-9 and xa < c[2] - 1e-9: + ys += [c[1], c[3]] + ys.append(y1) + for k in range(0, len(ys) - 1, 2): + ya, yb = ys[k], ys[k + 1] + if yb - ya > 0.6: + tiles.append((xa, ya, xb, yb)) + # ⛔ 内层的下沿会盖住金手指的**防呆缺口**（铣穿的）。把缺口那一段单独让开： + # y 抬到缺口顶之上，再补两块把缺口左右两侧的底部填回来。 + nx0, _a, nx1, ny1 = notch_cut() + if y_lo < ny1: + cut = ny1 + out = [] + for (a, b, c, e) in tiles: + if e <= cut: + continue + if b < cut and (a < nx1 and c > nx0): + out.append((a, cut, c, e)) + if a < nx0: + out.append((a, b, nx0, cut)) + if c > nx1: + out.append((nx1, b, c, cut)) + else: + out.append((a, b, c, e)) + tiles = [t for t in out if t[2] - t[0] > 0.6 and t[3] - t[1] > 0.6] + return tiles + + +def vo_poly(): + u"""VO_P 岛：主体矩形 + 北叶，拼成一个 L 形**单环**（逆时针，显式闭合）。""" + a, b = VO_ISLAND, VO_LOBE + assert abs(a[3] - b[1]) < 1e-9 and a[0] <= b[0] and b[2] <= a[2], u'北叶必须骑在主体上沿' + pts = [(a[0], a[1]), (a[2], a[1]), (a[2], a[3]), (b[2], a[3]), + (b[2], b[3]), (b[0], b[3]), (b[0], a[3]), (a[0], a[3])] + out = [pts[0]] + for q in pts[1:]: + if abs(q[0] - out[-1][0]) > 1e-9 or abs(q[1] - out[-1][1]) > 1e-9: + out.append(q) + out.append(out[0]) + return out + + +def plan(): + u"""[(name, net, layer, [环...], priority)]，priority 小的先铺、先占地盘。""" + outs = [] + outs.append(('VO-L3', 'VO_P', L_PWR, [src(vo_poly())], 1)) + outs.append(('V12-L3', '+12V', L_PWR, [src(rrect(*V12_ISLAND))], 2)) + for tag, layer, y_lo in (('L2', L_GND, INSET), ('TOP', L_TOP, TOP_POUR_Y), + ('BOT', L_BOT, TOP_POUR_Y)): + for k, (a, b, c, d2) in enumerate(gnd_tiles(y_lo)): + outs.append(('GND-%s-%d' % (tag, k), 'GND', layer, + [src(rrect(a, b, c, d2))], 9)) + return outs + + +def selfcheck(ps): + bad = [] + for name, _net, _lay, rings, _p in ps: + for k, s in enumerate(rings): + if s[0] != s[-2] or s[1] != s[-1]: + bad.append(u'%s 第 %d 个环没闭合' % (name, k)) + # 外层铜面不许下探进金手指区 + top = fp_edge.EDGE_CLR + fp_edge.LONG_L + if TOP_POUR_Y <= top: + bad.append(u'外层铜下沿 %.2f 压到指顶 %.2f' % (TOP_POUR_Y, top)) + if TOP_POUR_Y <= fp_edge.NOTCH_D: + bad.append(u'外层铜下沿 %.2f 低于缺口顶 %.2f' % (TOP_POUR_Y, fp_edge.NOTCH_D)) + # 内层铜面必须绕开缺口 + nx0, _a, nx1, ny1 = notch_cut() + if nx1 - nx0 < 2.9: + bad.append(u'缺口挖得比口部还窄') + # 两个岛不许互相重叠（同层，优先级只有 1/2 之差，重叠就说不清谁裁谁） + b = V12_ISLAND + for a in (VO_ISLAND, VO_LOBE): + if a[0] < b[2] and b[0] < a[2] and a[1] < b[3] and b[1] < a[3]: + bad.append(u'VO 岛和 +12V 岛在 L3 上重叠') + # 北叶不许伸进尾插槽/车道 + for (x0, y0, x1, y1) in B.mill_cuts(): + if x0 > VO_LOBE[0] + 1.0 and VO_LOBE[0] < x1 and x0 < VO_LOBE[2] and y0 < VO_LOBE[3] and VO_LOBE[1] < y1: + bad.append(u'VO 北叶压到槽 (%.1f~%.1f)' % (x0, x1)) + return bad + + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" % PCB) + +JS_DEL = OPEN + u""" +let n = 0; +for (const old of await eda.pcb_PrimitivePour.getAll()) { + await eda.pcb_PrimitivePour.delete(old.primitiveId); n++; } +return {deleted: n}; +""" + +JS_MAKE = OPEN + u""" +const PLAN = %s; +for (const p of PLAN) { + const poly = await eda.pcb_MathPolygon.createComplexPolygon(p.src); + if (!poly) continue; + try { await eda.pcb_PrimitivePour.create(p.net, p.layer, poly, 'solid', false, + p.name, p.prio, 10); } catch (e) {} +} +return {made: (await eda.pcb_PrimitivePour.getAll()) + .map(x => String(x.pourName || '').toUpperCase())}; +""" + +JS_PRIO = OPEN + u""" +const P = %s; +let k = 0; +for (const o of await eda.pcb_PrimitivePour.getAll()) { + const want = P[String(o.pourName || '').toUpperCase()]; + if (want === undefined) continue; + try { await eda.pcb_PrimitivePour.modify(o.primitiveId, {pourPriority: want}); k++; } + catch (e) {} +} +return {set: k, now: (await eda.pcb_PrimitivePour.getAll()) + .map(o => [String(o.pourName||''), o.pourPriority])}; +""" + +JS_REBUILD = OPEN + u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +const leaf = (txt) => { for (const el of document.querySelectorAll('*')) + if (el.children.length===0 && (el.textContent||'').trim()===txt) return el; return null; }; +const btn = (txt) => { for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()===txt && b.offsetParent!==null) return b; return null; }; +if (!fire(leaf('工具'))) return {err: 'no 工具'}; +await sleep(900); +if (!fire(leaf('铺铜管理器...'))) return {err: 'no 铺铜管理器'}; +await sleep(2500); +const b = btn('重建所有'); +if (!b) return {err: 'no 重建所有'}; +return {fired: fire(b)}; +""" + +JS_POLL = u"return {poured: (await eda.pcb_PrimitivePoured.getAll()).length};" + +JS_DONE = u""" +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +let ok = null; +for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()==='确认' && b.offsetParent!==null) { ok = b; break; } +if (ok) fire(ok); +await new Promise(r => setTimeout(r, 1500)); +await eda.pcb_Document.save(); +return {poured: (await eda.pcb_PrimitivePoured.getAll()).length, + pour: (await eda.pcb_PrimitivePour.getAll()).length}; +""" + + +def call(js, timeout=120): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def main(): + ps = plan() + print(u'计划建 %d 块铜面：' % len(ps)) + for name, net, layer, rings, prio in ps: + npt = sum((len(r) + 1) // 3 for r in rings) + print(u' %-8s net=%-6s layer=%-3d %d 环 / %3d 点 prio=%d' + % (name, net, layer, len(rings), npt, prio)) + bad = selfcheck(ps) + if bad: + print(u'[X] 自检不过:') + for b in bad: + print(u' ' + b) + sys.exit(1) + print(u'[OK] 自检通过：多边形全闭合 / 外层铜不进金手指区 / 内层绕开缺口 / 两岛不重叠') + if '--push' not in sys.argv and '--rebuild' not in sys.argv: + print(u'（未加 --push，没有下发）') + return + + if '--rebuild' not in sys.argv: + print(u'清掉旧铜面: %d 块' % call(JS_DEL)['deleted']) + for k in range(0, len(ps), 3): # 3 块一批，稳在超时以内 + batch = [{'name': n, 'net': net, 'layer': l, 'src': s, 'prio': pr} + for n, net, l, s, pr in ps[k:k + 3]] + made = call(JS_MAKE % json.dumps(batch), timeout=180)['made'] + print(u' 已建 %d 块' % len(made)) + want = {n.upper() for n, _, _, _, _ in ps} + got = set(call("return (await eda.pcb_PrimitivePour.getAll())" + ".map(x=>String(x.pourName||'').toUpperCase());")) + if not want <= got: + print(u'[X] 没建上: %s' % (want - got)) + sys.exit(1) + # ⚠ create() 的 pourPriority 参数不生效（R1 skill §9j），建完再逐块设 + r = call(JS_PRIO % json.dumps({n.upper(): pr for n, _, _, _, pr in ps}), timeout=180) + print(u' 优先级已设 %d 块: %s' % (r['set'], r['now'])) + + before = len(call("return (await eda.pcb_PrimitivePour.getAll()).map(o=>o.pourName);")) + r = call(JS_REBUILD, timeout=120) + if r.get('err'): + print(u'[X] 打不开铺铜管理器: %s' % r['err']) + sys.exit(1) + # ⚠ 退出条件是「**数量稳定**」，不是「全部填上」。 + # 有的铜面本来就填不出来（`V12-L3` 在 `+12V` 还没有过孔扎进 L3 之前是孤岛， + # 会被「移除孤岛」删掉），写成 `n >= len(ps)` 的话每次都要空转满 200 秒， + # 而且看上去像是卡死。 + prev, same = -1, 0 + for _i in range(40): + time.sleep(5) + n = call(JS_POLL, timeout=60)['poured'] + print(u' 填充 %d / %d' % (n, len(ps))) + if n >= len(ps): + break + same = same + 1 if n == prev else 0 + prev = n + if same >= 2 and n > 0: + print(u' （%d 块已稳定，另 %d 块没有可接的铜，属正常）' % (n, len(ps) - n)) + break + fin = call(JS_DONE, timeout=120) + print(u' 收尾: %s' % fin) + # ⛔ 铺铜**边框**会莫名其妙变少（实测 6→3、5→2）。哪一步删的还没查清， + # 但「静默变少」是最坏的形态：铜面没了，DRC 只报连接性，看上去像布线没做完。 + # 这里把它变成硬报错。 + if fin['pour'] < before: + print(u' [X] 铺铜边框从 %d 变成 %d —— 有东西把它们删了，**不要在这个状态下导出**' + % (before, fin['pour'])) + sys.exit(1) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/pcb_route.py b/.claude/r2/pcb_route.py new file mode 100644 index 0000000..0939fdb --- /dev/null +++ b/.claude/r2/pcb_route.py @@ -0,0 +1,323 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 布线（M4c-4）。 + + /c/Python314/python .claude/r2/pcb_route.py --dump # 重抓焊盘坐标（摆位改过就要跑） + /c/Python314/python .claude/r2/pcb_route.py --stitch # GND 缝合过孔（**铺铜之前必须先跑**） + /c/Python314/python .claude/r2/pcb_route.py --auto # 自动布线（只用 L1/L4） + /c/Python314/python .claude/r2/pcb_route.py --clear # 清掉全部布线（回到摆位后的状态） + /c/Python314/python .claude/r2/pcb_route.py --check # 逐网络算连通性 + 关键回路复核 + +## ⛔ 只准在 L1 / L4 布线 + +`layers: [1, 2]`（Top / Bottom）。**内层不许布线**： +L2(Inner1) 是方案 §7.1 明令「完整地平面，不许割断」的参考面， +L3(Inner2) 是 `VO_P` / `+12V` 的灌铜岛。自动布线器一旦被允许用内层， +就会在地平面上割出一堆缝 —— 而**这件事 DRC 一条都不报**， +只有 D± 的参考面被切断时才在实物上表现为偶发掉线。 + +## 关键回路（§7.2，自动布线器不认识这几条，跑完要逐条复核） + +| 回路 | 判据 | +|---|---| +| Buck 输入 `C1~C4 ↔ U1` | 环路面积最小 —— 电容紧贴 U1 的 VIN/GND | +| SW 节点 `U1.11/12 → L1.1` | 铜面积压到刚够载流（`SWNODE` 2.0 mm），不许绕 | +| FB 分压 `R1/R2/R7` | 走线**远离 SW**，`VDAC` 注入的 RC 在 DAC 侧 | +| **Kelvin 取样** | `U3.9→Rs1.1` / `U3.10→Rs1.2` 必须**落在 Rs1 的焊盘上**，不许就近扎孔 | +| D± 两段 | 走 L1、以 L2 为参考；`USBEDGE` / `USBPHONE` 两对差分 | + +`--check` 把 Kelvin 那一条做成了机器判据（见 `check_kelvin`）： +取样线的两个端点必须一个在 `Rs1` 的焊盘框里、一个在 `U3` 的焊盘框里， +中间不许出现过孔。**别的三条只能靠截图人眼看。** +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +PADS = os.path.join(HERE, '_blade_pads.json') + +# 只把 GND 交给灌铜（顶层铜面 + 缝合过孔），其余全让自动布线器拉。 +# ⚠ `VO_P` / `+12V` **不能**也交给灌铜：L3 上那两个岛没有任何通孔焊盘可接， +# 不布线就没有过孔，铜面会被当孤岛删掉（同 stitch_points() 的注释）。 +# 让布线器拉线，它换层时打的过孔正好把 L3 的岛接上，线宽走 PWR4A / PWR12V 规则。 +PLANE_NETS = ['GND'] + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def dump_pads(): + JS = OPEN + u""" +const MIL = %s; +const out = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let cx = p.x, cy = p.y, poly = false; + // ⛔ **POLYGON 形状的焊盘（QFN 的散热盘）没有 w/h 字段**，取不到就是 0 —— + // 于是布线器把这么一大块铜当成**一个点**，线直接从上面压过去 = 对地短路。 + // 实测 `U1.15`（VQFN-14 的散热盘，接 GND）就是这样，DRC 报「贴片焊盘到导线 0mil」。 + // ⇒ 按多边形点列算外接框。 + if (String(pad[0]) === 'POLYGON' && Array.isArray(pad[1])) { + // ⛔ **不能用外接框**：QFN 的散热盘是**十字形**（横臂只有 0.8 mm 高）， + // 外接框会把两侧引脚所在的那一圈也封掉 —— `U1` 的 p1/p7/p8/p14 + // 凭空「出不来」。⇒ 按扫描线拆成若干矩形，逐块当障碍。 + const nums = pad[1].filter(v => typeof v === 'number'); + const pts = []; + for (let k=0; k+1q[1]))].sort((a,b)=>a-b); + for (let b2=0; b2+1a-b); + for (let k=0; k+1 45 && rot < 135) { const t=w; w=h; h=t; } + out.push([c.designator, String(p.padNumber), Math.round(cx/MIL*1000)/1000, + Math.round(cy/MIL*1000)/1000, Math.round(w/MIL*1000)/1000, + Math.round(h/MIL*1000)/1000, p.layer, p.net||'', String(pad[0])]); + } +} +return out; +""" % MIL + d = call(JS, timeout=300) + io.open(PADS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) + print(u'已写 _blade_pads.json：%d 个焊盘' % len(d)) + return d + + +def pads(): + if not os.path.exists(PADS): + return dump_pads() + return json.load(io.open(PADS, encoding='utf-8')) + + +VIA_D, VIA_HOLE = 0.6, 0.3 +STITCH_PITCH = 5.0 +STITCH_CLR = 0.6 # 过孔到任何焊盘的净距 + + +def seg_dist(px, py, x1, y1, x2, y2): + u"""点到线段的距离（mm）。""" + dx, dy = x2 - x1, y2 - y1 + L2 = dx * dx + dy * dy + if L2 < 1e-12: + return math.hypot(px - x1, py - y1) + t = max(0.0, min(1.0, ((px - x1) * dx + (py - y1) * dy) / L2)) + return math.hypot(px - (x1 + t * dx), py - (y1 + t * dy)) + + +def board_tracks(): + u"""从板上读回所有铜层导线 [(x1,y1,x2,y2,半宽)]，用来给缝合过孔让路。""" + r = run(OPEN + "return (await eda.pcb_PrimitiveLine.getAll()||[])" + ".filter(l=>[1,2,15,16].includes(l.layer))" + ".map(l=>[l.startX,l.startY,l.endX,l.endY,l.lineWidth]);", timeout=300) + if not r.get('success'): + print(u' [!] 读不回导线，缝合过孔这一轮不避让导线：' + + json.dumps(r, ensure_ascii=False)[:200]) + return [] + return [(a[0] / MIL, a[1] / MIL, a[2] / MIL, a[3] / MIL, a[4] / MIL / 2.0 + 0.16) + for a in r['result']] + + +def stitch_points(): + u"""GND 缝合过孔的坐标。 + + ⛔ **不打这批过孔，四层里有三层的铜面会被当成死铜整块删掉。** + 2026-09-08 实测：六块铜面下发后只有 `GND-TOP` 填出来（213 块）， + 另外五块（`GND-L2` / `GND-L3` / `GND-BOT` / `VO-L3` / `V12-L3`）一块铜都没有 —— + 这块板**一个通孔焊盘都没有**（全贴片），内层的铜面因此一个连接点都没有， + 「移除孤岛」把整块删了。`rebuildCopperRegion()` 返回成功、铺铜管理器显示 0/0， + **两个地方都不报错**，只有截图能看出来内层是空的。 + + ⇒ 顺序必须是：**摆位 → 缝合过孔 → 布线 → 铺铜**。 + """ + import math + d = pads() + obst = [] + for p in d: + obst.append((p[2] - p[4] / 2 - STITCH_CLR, p[3] - p[5] / 2 - STITCH_CLR, + p[2] + p[4] / 2 + STITCH_CLR, p[3] + p[5] / 2 + STITCH_CLR)) + ml, mr = B.notch_break() + holes = B.phone_holes() + r = VIA_D / 2.0 + 0.3 + tracks = board_tracks() + out = [] + y = 13.0 + while y <= B.BH - 2.0: + x = 2.5 + while x <= B.BW - 2.5: + ok = True + if x - r < 0.8 or x + r > B.BW - 0.8 or y - r < 0.8 or y + r > B.BH - 0.8: + ok = False + if ok and ml - 1.0 < x < mr + 1.0 and y < 9.0: + ok = False + # ⛔ 主板定位孔的避让。不加这一条，5 mm 网格会把过孔打在孔位上 + # （实测 H6 只差 0.91 mm），而钻孔和过孔重叠 DRC 未必报得清楚。 + # 排线穿板槽（铣穿的内槽） + if ok: + for (a, b, c2, d2) in B.mill_cuts(): + if a - 0.8 < x < c2 + 0.8 and b - 0.8 < y < d2 + 0.8: + ok = False + break + if ok: + for (hx, hy) in holes.values(): + if math.hypot(x - hx, y - hy) < B.HOLE_D / 2 + r + 0.3: + ok = False + break + if ok: + for q in obst: + if q[0] < x + r and x - r < q[2] and q[1] < y + r and y - r < q[3]: + ok = False + break + if ok and tracks: + # ⛔ M7 新增：**避开已经布好的导线**。M6 的顺序是「缝合过孔 → 布线」， + # 布线器自己会绕开过孔；M7 反过来（先布线，让细间距的脚有出口）， + # 于是这批 5 mm 网格的过孔会直接压在别人的线上 —— 那是短路， + # 只有 DRC 的间距那一支报得出来，铺完铜就更难查。 + for (x1, y1, x2, y2, hw) in tracks: + if seg_dist(x, y, x1, y1, x2, y2) < r + hw: + ok = False + break + if ok: + out.append((round(x, 3), round(y, 3))) + x += STITCH_PITCH + y += STITCH_PITCH + return out + + +def stitch(): + pts = stitch_points() + print(u'GND 缝合过孔 %d 个（%g mm 网格）' % (len(pts), STITCH_PITCH)) + JS = OPEN + u""" +const MIL = %s, P = %s, D = %s, H = %s; +let old = 0; +for (const v of (await eda.pcb_PrimitiveVia.getAll()||[])) + if (String(v.net) === 'GND') { await eda.pcb_PrimitiveVia.delete(v.primitiveId); old++; } +let n = 0; +for (const p of P) { + try { await eda.pcb_PrimitiveVia.create('GND', p[0]*MIL, p[1]*MIL, H*MIL, D*MIL); n++; } + catch (e) {} +} +await eda.pcb_Document.save(); +return {deleted: old, made: n, + now: (await eda.pcb_PrimitiveVia.getAll()||[]).length}; +""" % (MIL, json.dumps(pts), VIA_D, VIA_HOLE) + print(call(JS, timeout=600)) + + +def auto(): + JS = OPEN + u""" +const IGN = %s; +const r = await eda.pcb_Document.autoRouting({layers: [1, 2], ignoreNets: IGN}); +return {success: r.success, total: r.totalNetsCount, ok: r.successNetsCount, + failed: r.failedNets, ms: r.duration}; +""" % json.dumps(PLANE_NETS, ensure_ascii=False) + r = call(JS, timeout=900) + print(u'自动布线: %s %d/%d 个网络，用时 %s ms' + % (r['success'], r['ok'] or 0, r['total'] or 0, r['ms'])) + if r.get('failed'): + print(u' 没布通: %s' % ' '.join(map(str, r['failed'][:40]))) + call(OPEN + "await eda.pcb_Document.save(); return 1;") + return r + + +def clear(): + print(call(OPEN + "const ok = await eda.pcb_Document.clearRouting('all');" + "await eda.pcb_Document.save(); return {ok};")) + + +def check_kelvin(): + u"""Kelvin 取样的机器判据：U3.9/U3.10 的取样线必须落在 Rs1 的焊盘框里，中间无过孔。""" + d = pads() + box = {} + for p in d: + if p[0] in ('Rs1', 'U3'): + box['%s.%s' % (p[0], p[1])] = (p[2] - p[4] / 2, p[3] - p[5] / 2, + p[2] + p[4] / 2, p[3] + p[5] / 2) + JS = OPEN + u""" +const MIL = %s; +const out = []; +for (const l of (await eda.pcb_PrimitiveLine.getAll()||[])) { + if (l.net !== 'VO_P' && !String(l.net||'').startsWith('$')) continue; + out.push([String(l.net), l.layer, l.startX/MIL, l.startY/MIL, l.endX/MIL, l.endY/MIL]); +} +const vias = (await eda.pcb_PrimitiveVia.getAll()||[]).map(v=>[String(v.net), v.x/MIL, v.y/MIL]); +return {lines: out, vias}; +""" % MIL + r = call(JS, timeout=300) + print(u' 取样相关导线 %d 段 / 过孔 %d 个' % (len(r['lines']), len(r['vias']))) + return box, r + + +def connectivity(): + JS = OPEN + u""" +const out = []; +for (const n of await eda.pcb_Net.getAllNets()) { + let len = 0; + try { len = await eda.pcb_Net.getNetLength(n.name); } catch (e) {} + out.push([n.name, len]); +} +return out; +""" + r = call(JS, timeout=400) + zero = [n for n, l in r if not l] + print(u' 网络 %d 个，铜长为 0 的 %d 个' % (len(r), len(zero))) + if zero: + print(u' ' + ' '.join(zero[:40])) + return r + + +if __name__ == '__main__': + if '--dump' in sys.argv: + dump_pads() + if '--clear' in sys.argv: + clear() + if '--stitch' in sys.argv: + stitch() + if '--auto' in sys.argv: + auto() + if '--check' in sys.argv: + connectivity() + check_kelvin() diff --git a/.claude/r2/pcb_rules.py b/.claude/r2/pcb_rules.py new file mode 100644 index 0000000..8296381 --- /dev/null +++ b/.claude/r2/pcb_rules.py @@ -0,0 +1,415 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 的设计规则（M4c-1）。 + + /c/Python314/python .claude/r2/pcb_rules.py # 只反查 + 打印，不下发 + /c/Python314/python .claude/r2/pcb_rules.py --push # 下发规则 + 差分对 + 网络指派 + /c/Python314/python .claude/r2/pcb_rules.py --audit # 读回审计 + +做法照抄 R1 的 `.claude/pcb1_rules.py`，**那一份的文件头是唯一的说明书**， +四个坑一个都没变： + + · `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装 + · `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状** + · 下发之后**别再去 GUI 换「配置」下拉框** —— 换一次整套重置，网络指派全部悬空 + · `overwriteNetRules` / `overwriteNetByNetRules` 都是**整表覆盖**，必须先读回再合并 + +## 和 R1 下板不同的四处 + +1. **刀片只有一路**，所以线宽表比 R1 短：没有 `FAN12V`，`PWR12V` 也从 2.0 降到 0.8 + —— 刀片 12V 满载只有 **1.45 A**（§20.7 那颗 2 A 保险就是按它选的）， + R1 的 2.0 mm 是给整机 8~10 A 的干路用的，照抄过来只会把功率列挤死。 + +2. **两对差分**，不是一对：`USB_DP/DM`（金手指 → U7 ESD）和 `USB_DPJ/DMJ`（U7 → J4 尾插） + 是被 U7 隔开的两段，各自成对。只建一对的话另一段退回默认 0.2 mm 净距规则， + 在换层过孔处会误判 —— 和 R1 §10.1b 同一个理由。 + +3. **层角色**（§7.1）：L1 功率+信号 / **Inner1(L2) = 完整地平面（不许割断）** / + Inner2(L3) = 12V + VO 灌铜 / L4(Bottom) = 控制信号。D± 走 L1、以 L2 为参考。 + +4. **自动命名网只有两个**（R1 有十几个）：SW 节点和 eFuse 输出段。 + 仍然**按「位号.引脚」当场反查、两端交叉校核**，不写死 `$1N137` 这种名字 —— + 再导入一次变更它就可能改名，而写死的后果是**静默失效**（DRC 干干净净，规则悬空）。 +""" +import io +import json +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ HERE 必须后插（在 sys.path 最前）：`.claude` 下有同名的 R1 脚本。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +U = json.load(io.open(os.path.join(HERE, 'r2-uuids.json'), encoding='utf-8')) +PCB = U['boards']['BLADE']['pcb']['uuid'] +NETS_FILE = os.path.join(HERE, '_blade_pcb_nets.json') + +# ── 线宽规则（mm，外层 1 oz）──────────────────────────────────────────── +# 载流靠灌铜保证、不靠 DRC；min 一律压到 0.15~0.3，否则 0402 焊盘（0.57 宽）扇不出去。 +TRACK_RULES = { + 'PWR12V': {'strokeWidthDefault': 0.8, 'strokeWidthMin': 0.25, 'strokeWidthMax': 4.0}, + 'SWNODE': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.30, 'strokeWidthMax': 4.0}, + 'PWR4A': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.30, 'strokeWidthMax': 6.0}, + 'PWR5V': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.20, 'strokeWidthMax': 3.0}, + 'PWR1A': {'strokeWidthDefault': 0.4, 'strokeWidthMin': 0.15, 'strokeWidthMax': 2.0}, +} + +# ── 有名字的网络 → 线宽规则 ──────────────────────────────────────────── +NET_TRACK = { + '+12V': 'PWR12V', # 金手指 B1/B2/B3 + A2/A3 → F1，1.45 A + '+12V_F': 'PWR12V', # F1 → Buck 输入，同一路电流 + 'VO': 'PWR4A', # Buck 输出 → eFuse 输入 + 'VO_P': 'PWR4A', # 检流之后 → J5 电池排线，4 A + '+5V': 'PWR5V', # 金手指 A19/A32 → U5 TPS22918 + 'VBUS': 'PWR5V', # U5 → J4 尾插，手机 VBUS + '+3V3': 'PWR1A', # 刀片逻辑（INA226 + PCA9555）≈ 3 mA，0.4 纯余量 +} + +# ── 自动命名网 → (规则, 探针, 校核端)：两端查出来必须是同一个网 ───────── +AUTO_TRACK = { + # SW 节点：TPS54622(VQFN-14) 的 SW = pin 11/12 → L1 + 'SW': ('SWNODE', ('L1', '1'), ('U1', '11')), + # eFuse 输出段：TPS25940A(WQFN-20) 的 OUT = pin 4~8 → Rs1 上游脚 + 'VO_F': ('PWR4A', ('Rs1', '2'), ('U2', '5')), +} + +# ── 铺铜焊盘全连接（理由同 R1：不是怕十字花烧，是**铺完之后断面要量得准**）── +PLANE_RULE = 'PLANE-DIRECT' +PLANE_CONNECT_DIRECT = 1 +PLANE_NETS = ['VO_P', 'VO', '+12V', '+12V_F'] +PLANE_AUTO = ['VO_F'] + +# ── 差分对（mm）── 与 R1 同一组数：W 0.28 / S 0.18，以 L2 为参考 ──────── +DIFF = {'strokeWidthDefault': 0.28, 'strokeWidthMin': 0.20, 'strokeWidthMax': 0.60, + 'differentailPairSpacingDefault': 0.18, 'differentailPairSpacingMin': 0.15, + 'differentailPairLenTolerMax': 5.0} +PAIR_RULE = 'USBPAIR' +PAIR_CLEARANCE = 0.15 +PAIRS = [('USBEDGE', 'USB_DP', 'USB_DM'), # 金手指 → U7 USBLC6 + ('USBPHONE', 'USB_DPJ', 'USB_DMJ')] # U7 → J4 BM24 尾插 + +# ⚠ **0.15，不是 R1 的 0.2**。抬到 0.2 会刷出 23 条「贴片焊盘到贴片焊盘」—— +# **全部在 `J4` BM24-50DS 内部**：0.4 mm 间距的尾插座，相邻焊盘实测净距 0.168~0.171， +# 这是买来的连接器封装本身的几何，不是摆位问题，改摆位也修不掉。 +# 0.15 仍远高于嘉立创四层板 0.09 的能力线，而板上其它最紧的一处是 +# `K1~K4` 侧键盘的 0.276（Ø1.5 盘、实测间距 1.78），也过。 +MIN_CLEARANCE = 0.15 + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" % PCB) + + +def call(body, timeout=300): + r = run(OPEN + body, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def dump_nets(): + u"""重抓「位号.引脚 → 网名」。**每次导入变更之后必跑**。""" + r = call("const out = {};" + "for (const c of await eda.pcb_PrimitiveComponent.getAll()) {" + " const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(" + " c.getState_PrimitiveId());" + " out[c.designator] = ps.map(p=>[p.padNumber, p.net]); }" + "return out;") + io.open(NETS_FILE, 'w', encoding='utf-8').write(json.dumps(r, ensure_ascii=False)) + print(u'已写 _blade_pcb_nets.json：%d 件' % len(r)) + return r + + +def resolve_auto(nets=None): + u"""按 (位号, 引脚) 反查自动网名并逐条断言。对不上就**不下发**。""" + if nets is None: + if not os.path.exists(NETS_FILE): + nets = dump_nets() + else: + nets = json.load(io.open(NETS_FILE, encoding='utf-8')) + pin = {} + for ref, pads in nets.items(): + for pn, net in pads: + pin[(ref, str(pn))] = net + + out, bad, seen = {}, [], {} + for key, (_rule, probe, cross) in sorted(AUTO_TRACK.items()): + if probe not in pin: + bad.append(u'%s: 板上没有 %s.%s' % (key, probe[0], probe[1])) + continue + if cross not in pin: + bad.append(u'%s: 板上没有校核端 %s.%s' % (key, cross[0], cross[1])) + continue + net, other = pin[probe], pin[cross] + if not net or not str(net).startswith('$'): + bad.append(u'%s: %s.%s 上是 "%s"，不是自动命名网 —— 探针写错了' + % (key, probe[0], probe[1], net)) + continue + if net != other: + bad.append(u'%s: %s.%s = %s，但校核端 %s.%s = %s —— 两端不是同一个网' + % (key, probe[0], probe[1], net, cross[0], cross[1], other)) + continue + if net in seen: + bad.append(u'%s 和 %s 查到同一个网 %s' % (key, seen[net], net)) + continue + seen[net] = key + out[key] = net + if bad: + print(u' [!!] 自动命名网反查失败，**没有下发任何东西**：') + for b in bad: + print(u' · ' + b) + print(u' 多半是 _blade_pcb_nets.json 过期了 —— 导入变更之后要重跑 --dump。') + sys.exit(1) + return out + + +def net_track_full(auto): + t = dict(NET_TRACK) + for key, net in auto.items(): + t[net] = AUTO_TRACK[key][0] + return t + + +def plane_nets_full(auto): + return list(PLANE_NETS) + [auto[k] for k in PLANE_AUTO] + + +CAP_JS = u""" +const D = eda.pcb_Drc; +const cur = await D.getCurrentRuleConfiguration(); +const c = JSON.parse(JSON.stringify(cur.config)); +const multi = (await D.getRuleConfiguration( + 'JLCPCB Capability(Multiple Layers Board)')).config; +const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s; +const PLANERULE = %s, PLANEMODE = %s; + +const setTrack = (e, mn, df, mx) => { + for (const k of Object.keys(e.form.data)) + Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx}); +}; +const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing']; + +setTrack(T['copperThickness1oz'], 0.102, 0.254, 2.54); +if (!T['copperThickness0.5oz']) { + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = 'copperThickness0.5oz'; e.isSetDefault = false; + setTrack(e, 0.089, 0.254, 2.54); + T['copperThickness0.5oz'] = e; +} +Object.assign(c['Physics']['Via Size']['viaSize'].form, + {viaOuterdiameterMin: 0.3, viaInnerdiameterMin: 0.2}); +if (!SS['copperThicknessInner0.5oz']) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = 'copperThicknessInner0.5oz'; e.isSetDefault = false; + const src = multi['Spacing']['Safe Spacing']['copperThicknessInner0.5oz'].table; + for (const k of Object.keys(e.tables)) + e.tables[k].content = JSON.parse(JSON.stringify(src)); + SS['copperThicknessInner0.5oz'] = e; +} +for (const name of Object.keys(TRACKS)) { + const f = TRACKS[name]; + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = name; e.isSetDefault = false; e.unit = 'mm'; + setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax); + T[name] = e; +} +const dp = c['Physics']['Differential Pair']['differentialPair'].form; +for (const k of Object.keys(dp.strokeWidthTables.data)) + Object.assign(dp.strokeWidthTables.data[k], + {minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault, + maxValue: DW.strokeWidthMax}); +for (const k of Object.keys(dp.diffPairSpacingTables.data)) + Object.assign(dp.diffPairSpacingTables.data[k], + {minValue: DW.differentailPairSpacingMin, + defaultValue: DW.differentailPairSpacingDefault}); +dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax; +if (!SS[PAIRRULE]) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = PAIRRULE; e.isSetDefault = false; + for (const tk of Object.keys(e.tables || {})) + for (const row of (e.tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number') row[i] = PAIRC; + SS[PAIRRULE] = e; +} +// 安全间距全表**归一到 MINC**：≤0.2 的格子（板厂能力值 0.09~0.127，以及上一版抬到 +// 0.2 的那些）一律设成 MINC；0.254 / 0.3 那几格是孔/板边相关的，**不动**。 +// ⚠ R1 那份只「抬高不降低」，所以把 MINC 从 0.2 改小是改不动的 —— 这里必须是赋值。 +let bumped = 0; +for (const key of Object.keys(SS)) + if (key !== PAIRRULE) + for (const tk of Object.keys(SS[key].tables || {})) + for (const row of (SS[key].tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number' && row[i] <= 0.2001 && + Math.abs(row[i] - MINC) > 1e-6) { row[i] = MINC; bumped++; } +const CZ = c['Plane']['Copper Zone']; +if (!CZ[PLANERULE]) { + const e = JSON.parse(JSON.stringify(CZ['copperRegion'])); + e.editName = PLANERULE; e.isSetDefault = false; + CZ[PLANERULE] = e; +} +for (const m of ['singleLayerPadModel', 'multiLayerPadModel']) + for (const k of Object.keys(CZ[PLANERULE].form[m].data)) + CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE; + +const ok = await D.overwriteCurrentRuleConfiguration(c); +return {ok: ok === true, bumped: bumped, name: cur.name, + track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)}; +""" + + +def push(): + auto = resolve_auto() + track = net_track_full(auto) + planes = plane_nets_full(auto) + print(u' 自动网反查: ' + ' '.join(u'%s=%s' % (k, v) for k, v in sorted(auto.items()))) + + r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE, + json.dumps(PAIR_RULE), PAIR_CLEARANCE, + json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT)) + if not r.get('ok'): + print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效') + sys.exit(1) + print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track'])) + print(u' 安全间距抬高 %d 格；配置名 "%s"' % (r['bumped'], r['name'])) + + n = call(""" +const P = %s; +let k = 0; +for (const d of await eda.pcb_Drc.getAllDifferentialPairs()) + await eda.pcb_Drc.deleteDifferentialPair(d.name); +for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; } +return k; +""" % json.dumps(PAIRS)) + print(u' 差分对 %d / %d 对' % (n, len(PAIRS))) + if n != len(PAIRS): + print(u' [!!] 有对没建上 —— 网络名在这块板上不存在') + + n = call(""" +const T = %s, PN = %s, PR = %s; +const pset = new Set(PN); +const rules = await eda.pcb_Drc.getNetRules(); +let k = 0, p = 0; +const seen = []; +for (const r of rules) { + if (r.type !== 'net') continue; + if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); } + if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; } +} +await eda.pcb_Drc.overwriteNetRules(rules); +return {track: k, plane: p, seen: seen}; +""" % (json.dumps(track, ensure_ascii=False), json.dumps(planes, ensure_ascii=False), + json.dumps(PLANE_RULE))) + print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(track))) + if n['track'] != len(track): + print(u' [!!] 板上找不到: %s' % ' '.join(sorted(set(track) - set(n['seen'])))) + print(u' 铺铜全连接指派 %d / %d（%s）' % (n['plane'], len(planes), ' '.join(planes))) + + n = call(""" +const PAIRS = %s, RULE = %s; +const cur = await eda.pcb_Drc.getNetByNetRules(); +const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : []; +const key = e => [e.net1.name, e.net2.name].sort().join('|'); +const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|'))); +const list = []; +let dropped = 0; +for (const e of old) { + if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; } + list.push(e); +} +const have = new Set(list.map(key)); +let k = 0; +for (const [name, dp, dm] of PAIRS) { + const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm}, + rule: RULE, copperRuleName: null, planeRuleName: null}; + if (have.has(key(e))) continue; + list.push(e); k++; +} +const ok = await eda.pcb_Drc.overwriteNetByNetRules( + {'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []}); +const back = await eda.pcb_Drc.getNetByNetRules(); +return {added: k, dropped: dropped, ok: ok === true, + now: (back['Safe Spacing'] || []).length}; +""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE))) + print(u' 对内间距：新增 %d / 清掉过期 %d，现共 %d 条（%s = %.2f mm）' + % (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE)) + + call("await eda.pcb_Document.save(); return 1;") + print(u' 已保存') + print(u'') + print(u'⚠ 别去 GUI 的 设计 → 设计规则… 里换「配置」下拉框：换一次整套重置，') + print(u' %d 个网络的线宽指派立刻悬空，而 DRC 不会报错。' % len(track)) + print(u'⚠ 再导入一次变更之后顺序是：--dump → --push，少跑 --dump 就是拿旧网名指派。') + + +AUDIT_JS = u""" +const c = await eda.pcb_Drc.getCurrentRuleConfiguration(); +const rules = await eda.pcb_Drc.getNetRules(); +const nbn = await eda.pcb_Drc.getNetByNetRules(); +return { + cfgName: c && c.name, + layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(), + track: Object.keys(c.config.Physics['Track']), + half: !!c.config.Physics['Track']['copperThickness0.5oz'], + inner: !!c.config.Spacing['Safe Spacing']['copperThicknessInner0.5oz'], + pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(), + assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default') + .map(r => [r.name, r['Track']]).sort(), + planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default') + .map(r => [r.name, r['Copper Zone']]).sort(), + nbn: ((nbn && nbn['Safe Spacing']) || []).length, +}; +""" + + +def audit(): + auto = resolve_auto() + track = net_track_full(auto) + planes = plane_nets_full(auto) + r = call(AUDIT_JS) + bad = [] + + def chk(cond, good, msg): + print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg)) + if not cond: + bad.append(msg) + + print(u'──── 审计（配置 "%s"）────' % r['cfgName']) + chk(r['layers'] == 4, u'铜层数 4', u'铜层数是 %s，应为 4' % r['layers']) + chk(r['half'] and r['inner'], u'内层 0.5 oz 的线宽/间距条目都在', + u'内层 0.5 oz 条目缺失') + miss = [k for k in TRACK_RULES if k not in r['track']] + chk(not miss, u'五条线宽条目都在', u'缺线宽条目 %s' % miss) + got = dict(r['assigned']) + wrong = [(n, got.get(n), v) for n, v in sorted(track.items()) if got.get(n) != v] + chk(not wrong, u'%d 个网络的线宽指派全对' % len(track), + u'指派不对: %s' % wrong[:6]) + chk(sorted(r['pairs']) == sorted([p[0] for p in PAIRS]), + u'差分对 %s' % r['pairs'], u'差分对是 %s，应为 %s' % (r['pairs'], [p[0] for p in PAIRS])) + chk(r['nbn'] == len(PAIRS), u'对内间距 %d 条' % r['nbn'], + u'对内间距 %d 条，应为 %d' % (r['nbn'], len(PAIRS))) + gotp = dict(r['planeAssigned']) + missp = [n for n in planes if gotp.get(n) != PLANE_RULE] + chk(not missp, u'铺铜全连接 %d 个网络' % len(planes), u'没指派上: %s' % missp) + print(u' ' + (u'[OK] 全部通过' if not bad else u'[X] %d 条不过' % len(bad))) + return bad + + +if __name__ == '__main__': + print(u'刀片 PCB=%s' % PCB) + if '--dump' in sys.argv: + dump_nets() + if '--push' in sys.argv: + push() + audit() + elif '--audit' in sys.argv: + audit() + elif '--dump' not in sys.argv: + a = resolve_auto() + t = net_track_full(a) + print(u'自动网: ' + ' '.join(u'%s=%s' % (k, v) for k, v in sorted(a.items()))) + for n, v in sorted(t.items(), key=lambda kv: (kv[1], kv[0])): + print(u' %-10s -> %s' % (n, v)) diff --git a/.claude/r2/pinmap_base.py b/.claude/r2/pinmap_base.py new file mode 100644 index 0000000..e43970e --- /dev/null +++ b/.claude/r2/pinmap_base.py @@ -0,0 +1,117 @@ +# -*- coding: utf-8 -*- +u"""底板 ESP32（`U20`）的 EFUSE_EN / PRSNT# 引脚**重新分配**（M9，2026-09-09 用户提出）。 + + /c/Python314/python .claude/r2/pinmap_base.py # 只打计划 + 读回现状 + /c/Python314/python .claude/r2/pinmap_base.py --push # 真改（删端口 → 重建） + +## 为什么要换 + +槽阵转 90° 之后，五个槽沿 y 从南到北是 **1→5**，而 `U20` 上这两组脚的顺序**正好是反的**： + + U20 东沿（南→北）：EFUSE_EN5 EN4 EN3 EN2 EN1 + U20 南沿（西→东）：PRSNT4# PRSNT3# PRSNT2# PRSNT1# + +五根线因此互相全交叉，两层板上每个交叉都要打过孔换层 —— 而**这不是布线器的问题， +是引脚分配的问题**，布线器只会报「出不来 / 没布通」。 + +## 为什么可以随便换（组内互换，零电气风险） + +`EFUSE_EN*` 是普通 GPIO 输出、`PRSNT*#` 是普通 GPIO 输入，全部经 ESP32-S3 的 +GPIO matrix 出去，不挑脚。**组内互换**不碰 strapping（IO0/45/46）、不碰 ADC1 +（NTC 要的 IO1~IO10）、不碰 USB PHY（IO19/20）—— 换的只是固件里的编号。 + +⚠️⚠️ **`setState_Net` 对 netport 是坏的**（R1 `pinmap.py` 2026-09-06 实测）： +调用之后网名变空字符串、标签也没了，而**几何验证抓不到**。⇒ 只能删掉重建。 +""" +import io +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +PAGE = '38327f806bc13133' # A3-CTRL（r2-uuids.json） +# 只动 `U20` 那一侧的端口：它们在 x=340 / 470；上拉那一侧在 x=145，不许动。 +U20_SIDE_X = (340, 470) +SWAP = { + 'EFUSE_EN1': 'EFUSE_EN5', 'EFUSE_EN5': 'EFUSE_EN1', + 'EFUSE_EN2': 'EFUSE_EN4', 'EFUSE_EN4': 'EFUSE_EN2', + 'PRSNT1#': 'PRSNT4#', 'PRSNT4#': 'PRSNT1#', + 'PRSNT2#': 'PRSNT3#', 'PRSNT3#': 'PRSNT2#', +} + +JS_READ = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 1500)); +const out = []; +for (const c of await eda.sch_PrimitiveComponent.getAll()) { + if (c.getState_ComponentType() !== 'netport') continue; + let comp = ''; try { comp = (c.getState_Component() || {}).name || ''; } catch (e) {} + out.push([c.getState_PrimitiveId(), String(c.getState_Net() || ''), + c.getState_X(), c.getState_Y(), c.getState_Rotation + ? c.getState_Rotation() : (c.rotation || 0), comp]); +} +return out; +""" + +JS_APPLY = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r => setTimeout(r, 1500)); +const DEL = %s, MK = %s; +if (DEL.length) await eda.sch_PrimitiveComponent.delete(DEL); +for (const p of MK) await eda.sch_PrimitiveComponent.createNetPort(p[0], p[1], p[2], p[3], p[4], false); +await eda.sch_Document.save(); +await new Promise(r => setTimeout(r, 1000)); +return {del: DEL.length, mk: MK.length}; +""" + + +def read(): + r = run(JS_READ % PAGE, timeout=180) + assert r.get('success'), json.dumps(r, ensure_ascii=False)[:400] + return r['result'] + + +def plan(ports): + out = [] + for pid, net, x, y, rot, comp in ports: + if net not in SWAP: + continue + if round(x) not in U20_SIDE_X: + continue # 上拉那一侧不动 + out.append((pid, net, SWAP[net], x, y, rot, comp)) + return out + + +def main(): + ports = read() + pl = plan(ports) + print(u'A3-CTRL 上端口 %d 个；要改 %d 个（只动 U20 侧 x=%s）' + % (len(ports), len(pl), '/'.join(str(v) for v in U20_SIDE_X))) + for pid, old, new, x, y, rot, comp in sorted(pl, key=lambda t: t[1]): + print(u' (%4d,%4d) %-11s → %-11s [%s]' % (x, y, old, new, comp or '?')) + if '--push' not in sys.argv: + print(u'（没加 --push，没有下发）') + return + dele = [t[0] for t in pl] + mk = [['BI' if (t[6] or '').endswith('BI') else ('IN' if (t[6] or '').endswith('IN') else 'OUT'), + t[2], t[3], t[4], t[5]] for t in pl] + r = run(JS_APPLY % (PAGE, json.dumps(dele), json.dumps(mk, ensure_ascii=False)), timeout=600) + assert r.get('success'), json.dumps(r, ensure_ascii=False)[:500] + print(u' 删端口 %d / 重建 %d' % (r['result']['del'], r['result']['mk'])) + # 读回校验 + now = {(round(x), round(y)): net for _p, net, x, y, _r, _c in read()} + bad = [] + for _pid, old, new, x, y, _rot, _c in pl: + got = now.get((round(x), round(y))) + if got != new: + bad.append(u'(%d,%d) 应为 %s，读回 %s' % (x, y, new, got)) + print(u'[%s] 读回校验%s' % ('OK' if not bad else 'X', + u'逐个对上' if not bad else u' %d 条不过: %s' % (len(bad), bad[:4]))) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/place_audit.py b/.claude/r2/place_audit.py new file mode 100644 index 0000000..aa90681 --- /dev/null +++ b/.claude/r2/place_audit.py @@ -0,0 +1,263 @@ +# -*- coding: utf-8 -*- +u"""摆位体检：外围件有没有摆在**自己那只脚的那一侧**（M7）。 + + /c/Python314/python .claude/r2/place_audit.py # 全板扫一遍 + /c/Python314/python .claude/r2/place_audit.py U2 U1 # 只看这几颗 + /c/Python314/python .claude/r2/place_audit.py --base # R2 底板 + +## 这个脚本在抓什么 + +`U2` 那一窝暴露出来的毛病：它是 WQFN-20，**四条边都有脚**，而外围 12 件全被摆在了 +西边 —— 接东边 `p17~p20` 的四件要**绕整颗芯片**才够得着。这类错： + +- **DRC 不报**（没有间距问题）， +- **几何自检不报**（没有重叠、没出板框）， +- **布线器只会报「XXX 出不来 / 没布通」**，而那是症状不是病因， +- 人眼看截图能看出来，但要一颗一颗放大。 + +⇒ 判据写成一条能算的：**从芯片的这只脚，到同网对端焊盘的直线， +如果从芯片自己的本体里穿过去，这件就是摆错边了。** + +同一条判据顺手也能抓「被第三个件挡住」（直线穿过别人的本体）， +以及「去耦电容离电源脚太远」。 + +## 判据：绕行代价，不是「穿没穿过」 + +第一版只判「直线穿不穿过本体」，结果 64 处里绝大多数是噪声 —— `U1.14` 到 `U4.14` +隔着 81 mm，线从 `U4` 自己本体上方过一下，绕行代价才 2 mm，那不是摆错边。 +⇒ 判据改成**绕行代价**：把本体当障碍，算「绕过去的最短路 − 直线」， +再看它占直线长度的比例。只有 + + · 对端是**小外围件**（≤ `SAT_PINS` 只脚，即 0402/SOT23 这类）， + · 两者相距 < `NEAR`（默认 20 mm）， + · 绕行多走 > `EXTRA_MM` 且占比 > `EXTRA_RATIO` + +三条同时成立，才算「摆错边」—— 那才是「本可以放对面、白白绕一圈」的情形。 + +平面网（`GND` / `VO_P` / `+12V`）不走线，直接排除；成员多于 `BIG_NET` 的大网 +（`+3V3` 这种）也排除，它们本来就不该按直线看。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +if '--base' in sys.argv: + import place_base as PL # noqa: E402 + PADS = os.path.join(HERE, '_base_pads.json') + PLANE = ('GND', '+12V', '+5V', '+3V3', '+3V3_HUB', + 'VIN_RAW', 'VIN_FUSED', 'VIN_SW') +else: + import pcb_place as PL # noqa: E402 + PADS = os.path.join(HERE, '_blade_pads.json') + PLANE = ('GND', 'VO_P', '+12V', '+12V_F') +BIG_NET = 6 # 成员多于这个数的网不判（+3V3 这种大网不该按直线看） +IC_PINS = 4 # 引脚数 >= 这个数才算「芯片」（两脚件不算） +MAX_IC_PINS = 24 # 脚多于这个数的当**连接器**，不参与「摆错边」 +SAT_PINS = 3 # 引脚数 <= 这个数才算「小外围件」 +INSET = 0.25 # 本体矩形往里缩多少再判相交（焊盘本来就贴着边） +NEAR = 20.0 # 只看这个距离内的（远距离网绕一下无所谓） +EXTRA_MM = 1.5 # 绕行多走多少 mm 才算数 +EXTRA_RATIO = 0.10 # 且要占直线长度的这个比例 +FAR_DECAP = 3.0 # 去耦电容离电源脚超过这个距离就提示（mm） + + +def load(): + rows = json.load(io.open(PADS, encoding='utf-8')) + pads, bynet, byref = [], {}, {} + for r in rows: + ref, pin, x, y, net = r[0], r[1], r[2], r[3], r[7] + p = {'ref': ref, 'pin': pin, 'x': x, 'y': y, 'net': net} + pads.append(p) + byref.setdefault(ref, []).append(p) + if net and net not in PLANE: + bynet.setdefault(net, []).append(p) + body = {} + for ref, ps in byref.items(): + xs = [p['x'] for p in ps] + ys = [p['y'] for p in ps] + w, h = PL.BODY.get(ref, (0, 0)) + if w: # 焊盘框量不到本体的几件（C60/L1/J4/U4），用真实本体 + cx, cy = (min(xs) + max(xs)) / 2.0, (min(ys) + max(ys)) / 2.0 + body[ref] = (cx - w / 2, cy - h / 2, cx + w / 2, cy + h / 2) + else: + body[ref] = (min(xs), min(ys), max(xs), max(ys)) + return pads, bynet, byref, body + + +def seg_rect(x1, y1, x2, y2, r, inset=INSET): + u"""线段和矩形（往里缩 inset）有没有真的相交。Liang–Barsky。""" + a, b, c, d = r[0] + inset, r[1] + inset, r[2] - inset, r[3] - inset + if a >= c or b >= d: + return False + dx, dy = x2 - x1, y2 - y1 + t0, t1 = 0.0, 1.0 + for p, q in ((-dx, x1 - a), (dx, c - x1), (-dy, y1 - b), (dy, d - y1)): + if abs(p) < 1e-12: + if q < 0: + return False + else: + t = q / p + if p < 0: + if t > t1: + return False + t0 = max(t0, t) + else: + if t < t0: + return False + t1 = min(t1, t) + return t0 < t1 + + +def detour(ax, ay, bx, by, r): + u"""把矩形 r（缩 INSET）当障碍，绕过去的最短路 − 直线 = 多走多少 mm。 + + 可见图只有 6 个点（两端 + 四角），Dijkstra 直接跑。不相交就返回 0。 + """ + if not seg_rect(ax, ay, bx, by, r): + return 0.0 + a, b, c, d = r[0] + INSET, r[1] + INSET, r[2] - INSET, r[3] - INSET + pts = [(ax, ay), (bx, by), (a, b), (a, d), (c, b), (c, d)] + n = len(pts) + INF = float('inf') + dist = [INF] * n + dist[0] = 0.0 + done = [False] * n + for _ in range(n): + u = min((k for k in range(n) if not done[k]), key=lambda k: dist[k], default=None) + if u is None or dist[u] == INF: + break + done[u] = True + for v in range(n): + if done[v]: + continue + if seg_rect(pts[u][0], pts[u][1], pts[v][0], pts[v][1], r): + continue # 这一段还是穿本体，不可走 + w = math.hypot(pts[u][0] - pts[v][0], pts[u][1] - pts[v][1]) + if dist[u] + w < dist[v]: + dist[v] = dist[u] + w + straight = math.hypot(ax - bx, ay - by) + return 0.0 if dist[1] == INF else max(0.0, dist[1] - straight) + + +def wrong_side(icpad, sat, r): + u"""外围件在不在这只脚**朝外的那一侧**；不在的话，绕过去大约要多走多少 mm。 + + ⛔ 不用「直线穿不穿本体」判：芯片的**焊盘本身就在本体框里**（甚至框边上）， + 线段起点落在障碍内部，绕行最短路直接算成「无解」，返回 0 —— 于是 + `U1.1`(EN，在西边) 配 `R3`(在东边) 这种教科书式的摆错边**一条都报不出来**。 + 这是第二版判据交的学费。 + + 改判「侧」：脚离哪条边近，那条边的**外法线**就是它的出线方向； + 外围件相对这只脚的方向和外法线反着来（点积 < -0.3），就是摆到对面去了， + 代价约等于「芯片在这个方向上的尺寸 + 两倍净距」（线得绕过去）。 + """ + x, y = icpad['x'], icpad['y'] + dists = ((x - r[0], (-1.0, 0.0)), (r[2] - x, (1.0, 0.0)), + (y - r[1], (0.0, -1.0)), (r[3] - y, (0.0, 1.0))) + _d, nrm = min(dists, key=lambda t: t[0]) + vx, vy = sat['x'] - x, sat['y'] - y + vlen = math.hypot(vx, vy) + if vlen < 1e-9: + return 0.0 + dot = (vx * nrm[0] + vy * nrm[1]) / vlen + if dot > -0.3: + return 0.0 + span = (r[2] - r[0]) if nrm[1] == 0 else (r[3] - r[1]) + return span + 2 * INSET + + +def main(): + only = [a for a in sys.argv[1:] if not a.startswith('--')] + _pads, bynet, byref, body = load() + npin = {r: len(ps) for r, ps in byref.items()} + ics = sorted(r for r in byref if npin[r] >= IC_PINS) + own, blocked, decap = [], [], [] + for net, ps in sorted(bynet.items()): + if len(ps) > BIG_NET: + continue + for i in range(len(ps)): + for j in range(i + 1, len(ps)): + a, b = ps[i], ps[j] + if a['ref'] == b['ref']: + continue + d = math.hypot(a['x'] - b['x'], a['y'] - b['y']) + if d > NEAR: + continue + # 「摆错边」：一端是芯片、另一端是小外围件，而绕自家本体要多走不少 + for (icpad, sat) in ((a, b), (b, a)): + ic = icpad['ref'] + # ⚠ `J1`(64 脚) / `J4`(50 脚) 这类连接器不判：它们的脚排成一长条， + # 「离哪条边近」对端头的脚毫无意义（`J4.51` 会被判成朝西出线）， + # 而连接器的出线方向是设计定死的，不是摆位能改的。 + if (ic not in ics or npin[ic] > MAX_IC_PINS + or npin[sat['ref']] > SAT_PINS): + continue + ex = wrong_side(icpad, sat, body[ic]) + if ex > EXTRA_MM and ex / d > EXTRA_RATIO: + own.append((ex, ex / d, ic, net, a, b)) + for ref, r in body.items(): + if ref in (a['ref'], b['ref']): + continue + ex = detour(a['x'], a['y'], b['x'], b['y'], r) + if ex > EXTRA_MM and ex / d > EXTRA_RATIO: + blocked.append((ex, ex / d, ref, net, a, b)) + for ref, ps in sorted(byref.items()): + if len(ps) != 2 or not ref.startswith('C'): + continue + if 'GND' not in [p['net'] for p in ps]: + continue + pw = [p for p in ps if p['net'] != 'GND'] + if not pw or pw[0]['net'] in PLANE: + continue + best = None + for q in bynet.get(pw[0]['net'], []): + if q['ref'] == ref or q['ref'] not in ics: + continue + dd = math.hypot(pw[0]['x'] - q['x'], pw[0]['y'] - q['y']) + if best is None or dd < best[0]: + best = (dd, q) + if best and best[0] > FAR_DECAP: + decap.append((best[0], ref, pw[0]['net'], best[1])) + + def dedup(rows): + seen, out = set(), [] + for t in sorted(rows, reverse=True): + k = (t[2], t[4]['ref'], t[4]['pin'], t[5]['ref'], t[5]['pin']) + if k not in seen: + seen.add(k) + out.append(t) + return out + + def fmt(t): + ex, ratio, key, net, a, b = t + return (u' 绕 %5.1f mm (%3.0f%%) %-5s %-10s %s.%s(%.1f,%.1f) — %s.%s(%.1f,%.1f)' + % (ex, ratio * 100, key, net, a['ref'], a['pin'], a['x'], a['y'], + b['ref'], b['pin'], b['x'], b['y'])) + + if only: + keep = lambda t: t[2] in only or t[4]['ref'] in only or t[5]['ref'] in only + own, blocked = [t for t in own if keep(t)], [t for t in blocked if keep(t)] + decap = [t for t in decap if t[1] in only or t[3]['ref'] in only] + own, blocked = dedup(own), dedup(blocked) + print(u'⛔ 外围件摆错边（要绕自家芯片本体，多走 > %.1f mm 且 > %.0f%%）：%d 处' + % (EXTRA_MM, EXTRA_RATIO * 100, len(own))) + for t in own: + print(fmt(t)) + print(u'\n⚠ 被第三个件挡住（绕得过去，只是提示）：%d 处' % len(blocked)) + for t in blocked[:15]: + print(fmt(t)) + if len(blocked) > 15: + print(u' ...（还有 %d 处）' % (len(blocked) - 15)) + print(u'\n⚠ 去耦电容离电源脚 > %.1f mm：%d 处' % (FAR_DECAP, len(decap))) + for d, ref, net, q in sorted(decap, reverse=True): + print(u' %-5s %-8s 离 %s.%s %.1f mm' % (ref, net, q['ref'], q['pin'], d)) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/place_base.py b/.claude/r2/place_base.py new file mode 100644 index 0000000..2a6e175 --- /dev/null +++ b/.claude/r2/place_base.py @@ -0,0 +1,915 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 摆位（M5，4 层 98 × 98，D15）：五个插槽在 L1，其余 133 件全部翻到 L4。 + + /c/Python314/python .claude/r2/place_base.py # 只算 + 自检 + 体检，不下发 + /c/Python314/python .claude/r2/place_base.py --push # 下发（含翻面）+ 读回校验 + /c/Python314/python .claude/r2/place_base.py --verify # 只读回校验 + /c/Python314/python .claude/r2/place_base.py --dump # 重抓焊盘 _base_pads.json + /c/Python314/python .claude/r2/place_base.py --bbox # 重抓封装外框 _base_bbox.json + /c/Python314/python .claude/r2/place_base.py --native # 由板上焊盘 + 位姿重建 _base_native_pads.json + +2 层版（南带 / 西区 / 北带、ROUTE_FIX / USER_INPUT）整份在 `archive_base2L/place_base.py`。 + +## 背面镜像（2026-09-10 实测：U13 翻面逐 rot 读焊盘） + +封装原生偏移 (dx, dy) 在底层变成 **R(rot)·(dx, −dy)**： +rot 0 → (dx, −dy)；90 → (dy, dx)；180 → (−dx, dy)；270 → (−dy, −dx)。 +`pad_off()` 就按这一条算 —— 卫星件瞄的是**翻面之后真实的脚位**，不是芯片质心。 +原生偏移表 `_base_native_pads.json` 由「板上焊盘 + 板上位姿」反推（`--native`），下发后要重建。 + +## 朝向（几何验证抓不到、错了要重画的那几条）—— `verify()` 用板上读回焊盘逐条断言 + +1. **U32 底层 rot 270**：下行口朝**北**，西 → 东 = USB1 … USB5；XTAL / 上行 / USB6 在**西**侧； + strap 在南；VDD18 在东。USB1/USB2 直接北上进 J34/J35；USB3~5 从北沿出来往东， + 绕 U32 东侧（那一边除 VDD18 / 一只 3V3 外全是 NC）南下。 + 上行 / USB6 在西侧打孔上 L1，从 U32 顶上往东走（L1 走廊是空的），不和 D± 同层交叉。 + ⛔ 顶层那种「朝西、1 脚在北」**底层做不出来**：底层 rot 0 = 朝西但 1 脚在南（五对全交叉）， + rot 180 = 朝东但晶振 / 上行在北沿，北沿到槽 J35 只剩 0.9 mm。 +2. **U20 底层 rot 90**：天线（封装 +y 端）朝东伸进缺口；EFUSE_EN1~5 / PRSNT5# 那排朝西对着槽阵。 +3. **J1 底层 rot 90** 桶口朝南；**J23 底层 rot 180** 口朝南、信号脚朝北。 +4. **Q1 底层 rot 180**：VIN_FUSED 排在南（进）、VIN_SW 排在北（出），9 A 顺着 +y 走。 + +## D± 长度 → Hub 放走廊 2（2026-09-10 用户拍板） + +分区草图原本 Hub 在走廊 3、mux 在走廊 2：USB3~5 三对都要绕 U32 东侧，最远 USB5 ≈ 80 mm。 +对调之后只有 USB4/5 绕行，估算 45 / 23 / 3 / 40 / 58 mm。方案 §6.3 的 45 mm 只有把 U32 +放进中间槽正下方的过孔带才做得到（没选）；2 层版是 ~70 mm。`report()` 每次都打出估算值。 +上面第 1 条写的「USB1/USB2 北上」是走廊 3 的情形；走廊 2 时北上的是 USB1~3，绕行的是 USB4/5。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +BBOX = os.path.join(HERE, '_base_bbox.json') +NETS = os.path.join(HERE, '_base_pcb_nets.json') +PADS = os.path.join(HERE, '_base_pads.json') +NATIVE = os.path.join(HERE, '_base_native_pads.json') +POS_JSON = os.path.join(HERE, '_base_place.json') +ROT_JSON = os.path.join(HERE, '_base_rotations.json') +LIVE_POS_JSON = os.path.join(HERE, '_base_place_live.json') + +GAP = 0.6 # 同面件间净距（装配下限，自检按它判） +# 卫星件（排布器摆的小件）之间的**排布**间距。0.6 只是装配下限，不给布线留余量： +# 第六 / 七轮剩下的信号网全卡在 U20 北沿那排上拉 / NTC 阻容、U32 西侧、mux 区 —— 0402 按 0.6 一字排开， +# 两只脚、它们的 GND 孔和进出的线全挤在一起（2026-09-10 用户选定：加大小件间距重排）。 +# 排不下时退回 GAP（`plan()` 里第二遍），所以不会出现「排不下」。 +SAT_GAP = 1.5 +STEP = 0.25 # 候选格点 = 布线网格 +ANCHOR_AREA = 9.0 # 焊盘外框面积 > 这个算「锚」（Y1 10.4 要算进来：负载电容贴晶振） + +# ── 高度（mm）：背面限高 B.H_BOTTOM ───────────────────────────────────── +HEIGHT = { + 'J1': 11.0, # DC-005 桶身 + 'C2': 12.0, 'C3': 12.0, # Φ8 直立电解 470 µF + 'J26': 11.0, 'J27': 11.0, # 2510 4P 立式 + 'J33': 11.5, # 2.54 排针立式 + 'J23': 3.3, + 'U20': 3.1, 'L3': 4.5, 'L2': 4.0, 'F1': 2.0, +} +H_DEFAULT = 2.0 + +# 焊盘外框量不到本体的件：真实本体（mm，封装原生朝向）。 +BODY = { + 'J1': (14.5, 9.0), # DC-005 桶身（桶口朝封装 −x） + 'C2': (8.0, 8.0), 'C3': (8.0, 8.0), + 'J23': (9.0, 7.5), + 'J26': (10.2, 5.0), 'J27': (10.2, 5.0), + 'J33': (12.7, 2.54), + 'L3': (7.6, 6.5), + 'U20': (19.0, 19.0), # 焊盘框；天线 7.5 mm 另由 antenna_keepout 管 +} +# 本体中心相对器件原点的偏移（封装原生坐标）。R1 实测 DC-005 本体 x −10.68~+3.92。 +BODY_OFF = {'J1': (-3.38, 0.0), 'J23': (0.0, -1.5)} +# 本体越过 / 贴着板边才对的接口件：值 = 开口朝哪条边 +EDGE_PARTS = {'J1': 'S', 'J23': 'S'} + +# 南 → 北 = 物理槽位 1..5。USB1 = J34 = 最北（pcb_base.USB_SLOT_REF）。 +SLOT_ORDER = ['J38', 'J37', 'J36', 'J35', 'J34'] + +# ── Hub 坐哪条走廊 ───────────────────────────────────────────────────────── +# 2 = **定稿**（2026-09-10 用户拍板，与分区草图相比 Hub / mux 对调）：USB1~3 北上， +# 只有 USB4/5 绕 U32 东侧南下，D± 最远 ≈ 58 mm。 +# 3 = 分区草图原样（`--hub3`，只留作对比）：USB3~5 都要绕，最远 USB5 ≈ 80 mm。 +# 两条走廊正好差一个槽距，对调 = Hub 那一窝整体 −20.32、mux 那一窝 +20.32。 +HUB_K = 3 if '--hub3' in sys.argv else 2 +MUX_K = 5 - HUB_K +_CH, _CM = B.corridor(HUB_K), B.corridor(MUX_K) +# x：走廊 3 时 USB2（−2.5）正对北邻槽 J35 的 D±（47.5/48.5）。 +# 走廊 2 时 **东移 2.5 mm（49.0 → 51.5）**，让 USB3 的脚（50.25/50.75）落在 J36 D± 的东边： +# 北去三对极性都是反的（U32 北沿 DM 在西、槽上 D+ 在西），换位靠一次 U 形掉头（左右自然对调）。 +# USB3 的目标槽就在正上方 1 mm，脚正对着焊盘就没有掉头的地方（第二轮服务器实测： +# 换位绕在北沿上把 USB1_DP / USB4_DM 封死）。东移后它从 J36 南排底下北上、在两排之间向西掉头、 +# 打孔上 L1 回到焊盘 —— 见 route_base.usb3_uturn()。 +HUB_CX = 50.5 if HUB_K == 3 else 51.5 +# y：比走廊中心南移 0.26，北沿到北邻槽焊盘留 0.9 给那一对上 L1 的过孔 +HUB_CY = round((_CH[1] + _CH[3]) / 2.0 - 0.26, 3) +MUX_CY = round((_CM[1] + _CM[3]) / 2.0, 3) +ZONES = dict(B.ZONES) +ZONES['A4H'] = (28.5, _CH[1], 69.5, _CH[3]) +ZONES['A4M'] = (28.5, _CM[1], 69.5, _CM[3]) + +# ── 布线车道（摆位禁区，只在两条放件的走廊里）────────────────────────────── +# I²C：U35（mux 走廊西段）→ 另一侧那两槽的 SCL/SDA（x 36.5/37.5 在南排），要穿过 Hub 走廊。 +# DP_H：绕 U32 东侧南下的那几对。DP_M：穿过 mux 走廊的那几对（回到 x≈48 附近）。 +# U32_WVIA：上行 / USB6 在 U32 西侧打孔上 L1 的落点。 +LANES = { + 'I2C_H': (28.5, _CH[1], 31.5, _CH[3]), + 'I2C_M': (28.5, _CM[1], 31.5, _CM[3]), + # U32 东侧焊盘外沿 + 1.2 扇出圈之后，再留 ~1.9 mm 给 VDD18 / 3V3_HUB 去耦（它们在 USB4/5 绕行环的**里面**） + 'DP_H': (round(HUB_CX + 8.0, 3), _CH[1], round(HUB_CX + 12.0, 3), _CH[3]), + 'DP_M': (46.5, _CM[1], 51.5, _CM[3]) if HUB_K == 3 else (44.0, _CM[1], 49.0, _CM[3]), + 'U32_WVIA': (round(HUB_CX - 6.6, 3), round(HUB_CY - 2.3, 3), + round(HUB_CX - 5.4, 3), round(HUB_CY + 1.7, 3)), +} +# J23 针排北侧的出口带：D±（含两座同名脚的桥，route_base.j23_bridges）/ CC / VBUS 全从这里往北出。 +# ⛔ 不留的话排布器会把 CC 下拉 R717 摆在针排正北 —— 布线静态校验实测 DM 桥离 R717 净距 −0.075。 +# J23 底层 rot 180 在 (84.0, 5.25)：信号针排 y = 7.72 ± 0.65（封装原生 +2.47），x 80.8~87.2。 +J23_XY = (84.0, 5.25) +LANES['J23_ESC'] = (J23_XY[0] - 4.2, J23_XY[1] + 3.15, J23_XY[0] + 4.2, J23_XY[1] + 5.05) +# Rs6.2 西侧 9 A 上 L1 的过孔阵（route_base.V12_PATCH / V12_VIA_*）：只禁过孔那一段，不含 Rs6 本体。 +# ⛔ 以前只写在布线脚本里，摆位不知道要避开 —— 小件间距放大重排之后 R6（BLD_A）被挤进去， +# 布线静态校验实测净距 −0.55（v12_handoff 拦下，服务器那轮没跑）。 +LANES['V12_VIAS'] = (5.3, 44.4, 10.55, 48.05) + + +# ── 扇出圈（2026-09-10 用户选定：芯片扇出上 L1 + U32 按构造画）───────────────── +# 器件全在背面，芯片的脚、它的去耦 / strap、这些件的 GND 孔全挤在 L4 同一圈里 —— +# 第三轮服务器 198 条里绝大多数是这几颗「脚出不去」。芯片正上方的 L1 是空的， +# 但要在脚边落得下过孔才上得去 ⇒ 焊盘外框外留一圈别的件不许进，给扇出过孔。 +FAN_RING = {'U32': 1.2, 'U35': 1.6, 'U6': 1.6, 'U7': 1.6, 'U20': 1.6} + + +def fan_rings(sz, pos): + u"""[(主人, 矩形)]：主人自己不受它约束。""" + out = [] + for ref, m in FAN_RING.items(): + if ref in pos: + x, y, rot = pos[ref][:3] + r = body_rect(ref, x, y, rot, sz) + out.append((ref, (r[0] - m, r[1] - m, r[2] + m, r[3] + m))) + return out + + +def zone_at(x, y): + for k, z in ZONES.items(): + if z[0] <= x <= z[2] and z[1] <= y <= z[3]: + return k + return None + +# ── 分区：原理图页 → 背面分区；个别件按功能改派 ───────────────────────────── +PAGE_ZONE = {'A1-INPUT': 'A1', 'A2-AUX': 'A2', 'A3-CTRL': 'A3', 'A4-HUB': 'A4H', + 'A6-FAN': 'A6', 'A5-SLOTS': None, 'A5B-SLOTS': None} +ZONE_OVERRIDE = {} +for _r in ('U35', 'U6', 'U7', 'C604', 'C607', 'C608', 'C609', 'C610', 'C611', 'C612', + 'R614', 'R615', 'R616', 'R617'): + ZONE_OVERRIDE[_r] = 'A4M' # mux / DAC 与各自的去耦、参考 RC +for _r in ('J23', 'U31', 'C737', 'C752', 'C753', 'R717', 'R718', 'R721', 'R722', 'RT601'): + ZONE_OVERRIDE[_r] = 'A5' # 上行口 + Hub LDO（RT601 监测 U31） +ZONE_OVERRIDE['RT602'] = 'A1' # 监测 DC-005 接触热 +for _r in ('C736', 'C739', 'R660', 'R661'): + ZONE_OVERRIDE[_r] = 'A3' # ESP32 ADC 的 NTC 分压 / 滤波 +ZONE_ORDER = ['A4H', 'A4M', 'A3', 'A5', 'A1', 'A2', 'A6'] + +BIG_NETS = ('+3V3', '+12V', '+5V', '+3V3_HUB') # 遍布全板，只当次选目标 + + +# ── 几何：镜像 + 旋转 ──────────────────────────────────────────────────── +def rot_vec(rot, a, b): + r = int(round(rot)) % 360 + return {0: (a, b), 90: (-b, a), 180: (-a, -b), 270: (b, -a)}[r] + + +def layer_of(ref): + return B.side_of(ref) + + +def pad_off(nx, ny, rot, layer): + u"""封装原生偏移 → 板上偏移。底层先 y 取反再转（实测，见文件头）。""" + return rot_vec(rot, nx, -ny if layer == B.BOTTOM else ny) + + +def native(): + return json.load(io.open(NATIVE, encoding='utf-8')) + + +def pads_at(nat, ref, x, y, rot): + u"""[(脚号, 网, 板 x, 板 y)]。""" + out = [] + for pn, nx, ny, _w, _h, net, _sh in nat.get(ref, []): + dx, dy = pad_off(nx, ny, rot, layer_of(ref)) + out.append((pn, net, round(x + dx, 4), round(y + dy, 4))) + return out + + +def sizes(): + d = json.load(io.open(BBOX, encoding='utf-8')) + out = {} + for k, v in d.items(): + bw, bh = BODY.get(k, (0.0, 0.0)) + out[k] = (max(v['w'], bw, 0.6), max(v['h'], bh, 0.6)) + return out + + +def body_rect(ref, x, y, rot, sz, pad=0.0): + w, h = sz[ref] + if int(round(rot)) % 180: + w, h = h, w + ox, oy = BODY_OFF.get(ref, (0.0, 0.0)) + dx, dy = pad_off(ox, oy, rot, layer_of(ref)) + cx, cy = x + dx, y + dy + return (cx - w / 2 - pad, cy - h / 2 - pad, cx + w / 2 + pad, cy + h / 2 + pad) + + +def height(ref): + return HEIGHT.get(ref, H_DEFAULT) + + +def _hit(r, q): + return r[0] < q[2] and q[0] < r[2] and r[1] < q[3] and q[1] < r[3] + + +def _rect_dist(px, py, r): + dx = max(r[0] - px, px - r[2], 0.0) + dy = max(r[1] - py, py - r[3], 0.0) + return math.hypot(dx, dy) + + +# ── 固定障碍（背面）───────────────────────────────────────────────────── +ANT_LEN = 7.5 # 天线段伸出焊盘框 +ANT_SIDE = 0.5 + + +def antenna_keepout(sz, pos): + u"""U20 天线净空：天线在封装 +y 端，方向 = pad_off(0, 1)。**跟着 rot 和翻面走**。""" + ax, ay, rot = pos['U20'] + w, h = sz['U20'] + if int(round(rot)) % 180: + w, h = h, w + dx, dy = pad_off(0, 1, rot, layer_of('U20')) + if dx > 0.5: + return (ax + w / 2, ay - h / 2 - ANT_SIDE, ax + w / 2 + ANT_LEN, ay + h / 2 + ANT_SIDE) + if dx < -0.5: + return (ax - w / 2 - ANT_LEN, ay - h / 2 - ANT_SIDE, ax - w / 2, ay + h / 2 + ANT_SIDE) + if dy > 0.5: + return (ax - w / 2 - ANT_SIDE, ay + h / 2, ax + w / 2 + ANT_SIDE, ay + h / 2 + ANT_LEN) + return (ax - w / 2 - ANT_SIDE, ay - h / 2 - ANT_LEN, ax + w / 2 + ANT_SIDE, ay - h / 2) + + +def blockers(sz, pos): + out = [] + k = B.HOLE_KEEP + for _n, (hx, hy) in B.MOUNT_HOLES.items(): + out.append((hx - k, hy - k, hx + k, hy + k)) + n = B.notch_rect() + out.append((n[0] - 0.5, n[1] - 0.5, n[2], n[3] + 0.5)) + out.append(antenna_keepout(sz, pos)) + out += B.via_bands() + out += list(LANES.values()) + return out + + +# ── 手排件 ─────────────────────────────────────────────────────────────── +def pick_rot(nat, ref, x, y, net, point, cands=(0, 90, 180, 270)): + u"""cands 里挑一个 rot，让 ref 上网为 net 的那只脚离 point 最近。""" + best = None + for r in cands: + for pn, n, px, py in pads_at(nat, ref, x, y, r): + if n == net: + d = math.hypot(px - point[0], py - point[1]) + if best is None or d < best[0] - 1e-6: + best = (d, r) + return best[1] + + +def hand(nat=None): + u"""{位号: (x, y, rot)}。层由 `pcb_base.side_of` 定（插槽 L1，其余 L4）。""" + nat = nat or native() + H = {} + for i, ref in enumerate(SLOT_ORDER, start=1): + H[ref] = (B.SLOT_CX, B.slot_y(i), B.SLOT_ROT) + + # ── A4H：Hub（走廊 HUB_K；x / y 的来历见 HUB_CX / HUB_CY）─────────────── + # 走廊 3 时焊盘 54.0~63.8，北沿到 J35 焊盘（64.72）留 0.9 给 USB2 那对过孔。 + H['U32'] = (HUB_CX, HUB_CY, 270) + # 晶振在 U32 西侧（XTAL1/2 在西沿北段），抬 3.1 让开 上行/USB6 的过孔带。 + H['Y1'] = (round(HUB_CX - 8.7, 3), round(HUB_CY + 3.1, 3), 270) + + # ── A4M：mux 在西段、两颗 DAC 在东段（中间 DP_M 车道） ───────────────────── + # U35 底层 rot 0：原生南排（MUX_RST#、SDA1~SCL4）翻到北边。 + H['U35'] = (39.0, MUX_CY, 0) + H['U6'] = (56.0, MUX_CY, 0) + H['U7'] = (64.0, MUX_CY, 0) + + # ── A3：ESP32 天线朝东伸进缺口（58~80）────────────────────────────────── + # 焊盘框 71.5~90.5 × 59.5~78.5，天线段 90.5~98。 + H['U20'] = (81.0, 69.0, 90) + H['J33'] = (80.0, 95.5, 0) # 应急串口，北板边内侧（让开 H4） + + # ── A5：上行 USB-C 在南板边，LDO 在它北边 ──────────────────────────────── + H['J23'] = (J23_XY[0], J23_XY[1], 180) + H['U31'] = (80.0, 26.0, 180) # 三只脚朝西（朝板中），散热片朝东 + H['RT601'] = (86.0, 26.0, 0) # 贴 U31 散热片（东侧），测 Hub LDO 最坏 ~0.7 W + # ⚠ 不能交给排布器：它的同网脚是 U20.39（NTC1），会被拉到 A5 北沿 + + # ── A1：输入链自南向北，电流顺 +y ──────────────────────────────────────── + # J1 桶身 9 × 14.5，本体 x 8~17 / y 0~14.5（让开 H1 的 3.2 圈）。 + H['J1'] = (12.5, 10.63, 90) + H['F1'] = (12.5, 17.75, 90) # VIN_RAW 在南、VIN_FUSED 在北 + H['Q1'] = (12.5, 24.5, 180) + H['D1'] = (12.5, 34.0, 90) # TVS 竖放在两颗电解中间，VIN_SW 脚朝南 + H['C2'] = (5.5, 35.0, 180) # VIN_SW 脚朝东（朝 D1 / Q1） + H['C3'] = (19.5, 35.0, 0) # VIN_SW 脚朝西 + H['Rs6'] = (12.5, 43.5, 90) # VIN_SW 在南、+12V 在北 —— +12V 在这打孔阵上 L1 大铺铜 + H['U13'] = (19.5, 43.5, 270) # INA226 Kelvin 脚（原生北排）朝西贴 Rs6 + H['RT602'] = (19.5, 8.0, 0) # 贴 J1 东侧，测 DC-005 接触热 + # 泄放链：Q3 在西头，R9A→R9E 自西向东一字排，每颗在 90/270 里挑，让相邻两颗的公共网脚在同一侧 + H['Q3'] = (2.95, 52.0, 180) # 漏极排（$1N114）朝北 + prev = ('Q3', '$1N114') + for k, (ref, x) in enumerate((('R9A', 7.6), ('R9B', 11.95), ('R9C', 16.3), + ('R9D', 20.65), ('R9E', 25.0))): + px, py = H[prev[0]][0], H[prev[0]][1] + pts = [(q[2], q[3]) for q in pads_at(nat, prev[0], px, py, H[prev[0]][2]) + if q[1] == prev[1]] + tgt = (sum(p[0] for p in pts) / len(pts), sum(p[1] for p in pts) / len(pts)) + H[ref] = (x, 52.0, pick_rot(nat, ref, x, 52.0, prev[1], tgt, (90, 270))) + prev = (ref, [q[5] for q in nat[ref] if q[5] != prev[1]][0]) + + # ── A2：两颗 Buck 一字排，IC → 电感紧邻（SW 最短）───────────────────────── + H['U19'] = (5.0, 68.5, 0) # SW 脚（原生东）朝东 + H['L2'] = (11.0, 68.5, 0) # SW 脚（原生西）朝西 + H['U30'] = (17.0, 68.5, 0) + H['L3'] = (23.5, 68.5, 0) + + # ── A6：两只风扇座贴北板边内侧 ───────────────────────────────────────── + H['J26'] = (13.5, 94.5, 0) + H['J27'] = (13.5, 88.0, 0) + return H + + +# ── 排布 ───────────────────────────────────────────────────────────────── +def page_of(): + bom = json.load(io.open(os.path.join(HERE, '_base_sch_bom.json'), encoding='utf-8')) + return {r['d']: pg for pg, rows in bom.items() for r in rows} + + +def zone_of_ref(ref, pg): + return ZONE_OVERRIDE.get(ref) or PAGE_ZONE[pg[ref]] + + +def sat_target(ref, nat, pos, sz, zone, claims): + u"""目标 = 已摆的锚上**同网的那只脚**（翻面后的真实坐标）。 + + 排序：**分区内的脚优先** → 非大网优先 → 离分区近的优先 → 被别的去耦认领得少的优先 → 锚小的优先 + （晶振负载电容认 Y1 而不是 U32；八颗 3V3_HUB 去耦分摊到 U32 的八只电源脚上）。 + ⚠ 「分区内优先」必须排第一：风扇驱动的同网脚一头在 J26/J27（A6 内）、一头在 U20（A3）， + 按「锚大优先」会全体瞄 60 mm 外的 U20，挤到 A6 的东南角。 + 返回 (x, y, 本件用来对准的网, 认领键) 或 None。 + """ + nets = [q[5] for q in nat.get(ref, []) if q[5] and q[5] != 'GND'] + if not nets: + return None + small = [n for n in nets if n not in BIG_NETS] + want = set(small or nets) + zr = ZONES[zone] + best = None + for other, (ox, oy, orot) in pos.items(): + if other == ref: + continue + area = sz[other][0] * sz[other][1] + if area <= ANCHOR_AREA and small: + pri0 = 1 + elif area <= ANCHOR_AREA: + continue + else: + pri0 = 0 + for pn, n, px, py in pads_at(nat, other, ox, oy, orot): + if n not in want: + continue + zd = round(_rect_dist(px, py, zr), 1) + key = (zd > 0, pri0 + (2 if n in BIG_NETS else 0), zd, + claims.get((other, pn), 0), area, other, pn) + if best is None or key < best[0]: + best = (key, px, py, n, (other, pn)) + if best is None: + return None + return best[1], best[2], best[3], best[4] + + +def _cands(zr, sz_ref, t): + u"""分区内格点，按离目标由近到远。""" + m = max(sz_ref) / 2.0 + xs, ys = [], [] + v = math.ceil(zr[0] / STEP) * STEP + while v <= zr[2] + 1e-9: + xs.append(round(v, 3)) + v += STEP + v = math.ceil(zr[1] / STEP) * STEP + while v <= zr[3] + 1e-9: + ys.append(round(v, 3)) + v += STEP + pts = [(x, y) for x in xs for y in ys + if zr[0] - m <= x <= zr[2] + m and zr[1] - m <= y <= zr[3] + m] + pts.sort(key=lambda p: (math.hypot(p[0] - t[0], p[1] - t[1]), p[1], p[0])) + return pts + + +TIGHT = [] # 上一次 plan() 里退回 GAP 的件（报告用） +POWER_NETS = ('+3V3', '+3V3_HUB', '+5V', '+12V', 'VDD18', 'VDD18PLL', 'VIN_SW') +_NAT = [None] + + +def is_decap(ref): + u"""两只脚、一只 GND 一只电源 ⇒ 去耦 / 储能。""" + if _NAT[0] is None: + _NAT[0] = native() + nets = set(q[5] for q in _NAT[0].get(ref, [])) + return len(_NAT[0].get(ref, [])) == 2 and 'GND' in nets and bool(nets & set(POWER_NETS)) + + +def _inside(r, zr): + return zr[0] - 1e-6 <= r[0] and r[2] <= zr[2] + 1e-6 and zr[1] - 1e-6 <= r[1] and r[3] <= zr[3] + 1e-6 + + +def plan(): + sz = sizes() + nat = native() + pg = page_of() + pos = dict(hand(nat)) + fixed = list(blockers(sz, pos)) + [r for _o, r in fan_rings(sz, pos)] + placed = [] # (ref, 带 GAP/2 的本体框)，只收背面件 + for ref, (x, y, r) in pos.items(): + if layer_of(ref) == B.BOTTOM: + placed.append((ref, body_rect(ref, x, y, r, sz, GAP / 2))) + todo = {} + for ref in sz: + if ref not in pos: + todo.setdefault(zone_of_ref(ref, pg), []).append(ref) + claims = {} + unplaced = [] + aim = {} + tight = [] # 只能按装配下限 GAP 塞进去的件 + TIGHT[:] = tight + for zone in ZONE_ORDER: + zr = ZONES[zone] + zfixed = [q for q in fixed if _hit(q, zr)] + + def _ord(r): + a = sz[r][0] * sz[r][1] + nn = len(nat.get(r, [])) + # 去耦排在其它两脚件前面：它们必须贴脚，先占近处（第一版 SAT_GAP 把 C746 挤到 U32 脚 20 mm 外） + return (0 if a > ANCHOR_AREA else 1, 0 if nn > 2 else (1 if is_decap(r) else 2), -a, r) + + for ref in sorted(todo.get(zone, []), key=_ord): + t = sat_target(ref, nat, pos, sz, zone, claims) + tgt = (t[0], t[1]) if t else ((zr[0] + zr[2]) / 2.0, (zr[1] + zr[3]) / 2.0) + net = t[2] if t else None + done = None + zplaced = [q for _r, q in placed if _hit(q, (zr[0] - 12, zr[1] - 12, + zr[2] + 12, zr[3] + 12))] + # 第一遍按 SAT_GAP 找；整个分区都找不到才按装配下限 GAP 再找一遍。 + # ⚠ 去耦不放宽：它的价值全在「贴着脚」，放宽之后近处的位子被上拉 / 阻容占走，去耦被挤到十几毫米外。 + gaps = (GAP / 2,) if is_decap(ref) else (SAT_GAP / 2, GAP / 2) + for mc in gaps: + for (x, y) in _cands(zr, sz[ref], tgt): + ok = [] + for rot in (0, 90, 180, 270): + body = body_rect(ref, x, y, rot, sz) + if not _inside(body, zr): + continue + rg = body_rect(ref, x, y, rot, sz, mc) + if any(_hit(rg, q) for q in zfixed) or any(_hit(rg, q) for q in zplaced): + continue + if net: + d = min(math.hypot(px - tgt[0], py - tgt[1]) + for _pn, n, px, py in pads_at(nat, ref, x, y, rot) if n == net) + else: + d = math.hypot(x - tgt[0], y - tgt[1]) + ok.append((d, rot)) + if ok: + d, rot = min(ok) + done = (x, y, rot, d) + break + if done is not None: + if mc < SAT_GAP / 2 and not is_decap(ref): + tight.append(ref) + break + if done is None: + unplaced.append((ref, zone)) + continue + x, y, rot, d = done + pos[ref] = (x, y, rot) + # 按 SAT_GAP 的一半存：后来的件离它也至少 SAT_GAP（它自己退回 GAP 时也一样）。 + # 去耦按 GAP 存：别的去耦可以紧挨着它（一只脚两颗去耦的常见排法）。 + placed.append((ref, body_rect(ref, x, y, rot, sz, (GAP if is_decap(ref) else SAT_GAP) / 2))) + if t: + claims[t[3]] = claims.get(t[3], 0) + 1 + aim[ref] = (t[3][0], t[3][1], net, round(d, 2)) + return pos, unplaced, sz, aim + + +# ── 自检 ───────────────────────────────────────────────────────────────── +def selfcheck(pos, unplaced, sz): + bad = [] + if unplaced: + bad.append(u'排不下 %d 件: %s' % (len(unplaced), ' '.join('%s(%s)' % u for u in unplaced))) + miss = sorted(set(sz) - set(pos)) + if miss: + bad.append(u'没摆: %s' % ' '.join(miss)) + fixed = blockers(sz, pos) + rings = fan_rings(sz, pos) + items = sorted(pos) + for i, a in enumerate(items): + x, y, r = pos[a] + br = body_rect(a, x, y, r, sz) + lay = layer_of(a) + if a in EDGE_PARTS: + if abs(br[1]) > 1.0: + bad.append(u'%s 是接口件，本体南沿 y=%.2f 没贴板边' % (a, br[1])) + if br[0] < 0.25 or br[2] > B.BW - 0.25: + bad.append(u'%s 东西向出板' % a) + elif br[0] < 0.25 or br[1] < 0.25 or br[2] > B.BW - 0.25 or br[3] > B.BH - 0.25: + bad.append(u'%s 出板或贴边: %s' % (a, tuple(round(v, 2) for v in br))) + if lay == B.BOTTOM: + if not B.height_ok(height(a)): + bad.append(u'%s 高 %.1f 超背面限高 %.0f' % (a, height(a), B.H_BOTTOM)) + if a != 'U20': + for q in fixed: + if _hit(br, q): + bad.append(u'%s 压到禁区 %s' % (a, tuple(round(v, 2) for v in q))) + break + for o, q in rings: + if o != a and _hit(br, q): + bad.append(u'%s 进了 %s 的扇出圈' % (a, o)) + for b in items[i + 1:]: + if layer_of(b) != lay: + continue + rb = body_rect(b, pos[b][0], pos[b][1], pos[b][2], sz) + if _hit((br[0] - GAP + 1e-6, br[1] - GAP + 1e-6, br[2] + GAP - 1e-6, br[3] + GAP - 1e-6), rb): + bad.append(u'%s 与 %s 挨太近（< %.1f）' % (a, b, GAP)) + return bad + + +# ── 体检 ───────────────────────────────────────────────────────────────── +def report(pos, sz, aim): + nat = native() + pg = page_of() + print(u'') + print(u'分区占用（本体面积 / 分区面积）:') + cnt = {} + for ref, (x, y, _r) in pos.items(): + if layer_of(ref) == B.BOTTOM: + cnt.setdefault(zone_at(x, y) or '?', []).append(ref) + for k in ZONE_ORDER + ['?']: + v = cnt.get(k, []) + if not v: + continue + if k == '?': + print(u' 不在任何分区: %s' % ' '.join(sorted(v))) + continue + z = ZONES[k] + area = (z[2] - z[0]) * (z[3] - z[1]) + used = sum(sz[r][0] * sz[r][1] for r in v) + print(u' %-4s %3d 件 %5.0f / %5.0f mm² (%2.0f%%)' % (k, len(v), used, area, 100.0 * used / area)) + wrong = [r for r, (x, y, _r) in pos.items() if layer_of(r) == B.BOTTOM and r in pg + and zone_at(x, y) not in (zone_of_ref(r, pg), None)] + if wrong: + print(u' ⚠ 落到别的分区: %s' % ' '.join(sorted(wrong))) + print(u'') + far = sorted(((v[3], r, v[0], v[1], v[2]) for r, v in aim.items()), reverse=True) + print(u'卫星件 → 目标脚的距离：平均 %.1f mm；最远 8 件：' % (sum(f[0] for f in far) / max(len(far), 1))) + for d, r, o, pn, net in far[:8]: + print(u' %-6s → %s.%s (%s) %.1f mm' % (r, o, pn, net, d)) + print(u'') + print(u'D± 估算（曼哈顿：U32 北沿脚 → 槽南排 D± 脚；南去的另加绕 U32 东侧）— Hub 在走廊 %d:' % HUB_K) + L = dp_lengths(pos, nat) + for i, ref, v in L: + print(u' USB%d → %s ≈ %.0f mm' % (i, ref, v)) + print(u' 最远 ≈ %.0f mm（M5 验收线 45）' % max(v for _i, _r, v in L)) + + +def dp_lengths(pos, nat): + u"""[(USB 号, 槽位号, 估算长度 mm)]。北去的直走；南去的先上到北邻槽底下、向东进 DP_H、再南下。""" + ux, uy, ur = pos['U32'] + pp = {pn: (px, py) for pn, _n, px, py in pads_at(nat, 'U32', ux, uy, ur)} + up = _CH[3] + 1.3 + east = LANES['DP_H'][0] + 1.0 + out = [] + for i in range(1, B.SLOT_N + 1): + ref = B.USB_SLOT_REF[i] + pn = {1: '2', 2: '4', 3: '7', 4: '9', 5: '12'}[i] + sx, sy = B.pin_x(-1.5), pos[ref][1] - B.PAD_ROW_DY + px, py = pp[pn] + if sy > py: + v = abs(sx - px) + abs(sy - py) + else: + v = (up - py) + (east - px) + (up - sy) + abs(east - sx) + out.append((i, ref, round(v, 1))) + return out + + +# ── 下发 / 读回 ─────────────────────────────────────────────────────────── +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + + +def call(js, timeout=300): + r = run(OPEN + js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:700]) + sys.exit(1) + return r['result'] + + +def push(pos): + u"""layer + x + y + rotation 一次 modify。⚠ rotation 0 会被当成「未传」，传 360。""" + arr = [[k, layer_of(k), round(v[0] * MIL, 4), round(v[1] * MIL, 4), + int(v[2]) % 360 or 360] for k, v in sorted(pos.items())] + r = call(""" +const P = %s; +const by = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) by[c.designator] = c; +let k = 0, miss = []; +for (const [d, lay, x, y, rot] of P) { + const c = by[d]; + if (!c) { miss.push(d); continue; } + await eda.pcb_PrimitiveComponent.modify(c.getState_PrimitiveId(), + {layer: lay, x: x, y: y, rotation: rot}); + k++; +} +await eda.pcb_Document.save(); +return {moved: k, miss: miss}; +""" % json.dumps(arr), timeout=900) + print(u'摆位下发 %d 件%s' % (r['moved'], (u'；板上没有: %s' % r['miss']) if r['miss'] else u'')) + return r + + +BBOX_JS = u""" +const MIL = %s; +const out = {}; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + let x0=1e9, y0=1e9, x1=-1e9, y1=-1e9; + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let poly = false; + if (String(pad[0])==='POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v=>typeof v==='number'); + let mnx=1e9,mny=1e9,mxx=-1e9,mxy=-1e9; + for (let k=0;k+1 45 && prot < 135) { const t=w; w=h; h=t; } + x0=Math.min(x0,p.x-w/2); x1=Math.max(x1,p.x+w/2); + y0=Math.min(y0,p.y-h/2); y1=Math.max(y1,p.y+h/2); + } + out[c.designator] = {n: ps.length, w: (x1-x0)/MIL, h: (y1-y0)/MIL, rot: c.rotation, + fp: (c.footprint && c.footprint.name) ? c.footprint.name : c.footprint}; +} +return out; +""" % MIL + + +def dump_bbox(): + u"""封装外框 → `_base_bbox.json`，**按 rot 反转回封装朝向**（翻面不换长宽）。""" + d = call(BBOX_JS, timeout=600) + for k, v in d.items(): + if int(v.get('rot') or 0) % 180 == 90: + v['w'], v['h'] = v['h'], v['w'] + v['w'] = round(v['w'], 3) + v['h'] = round(v['h'], 3) + io.open(BBOX, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False, indent=0)) + print(u'已写 _base_bbox.json：%d 件' % len(d)) + return d + + +DUMP_JS = u""" +const MIL = %s; +const out = []; +for (const c of await eda.pcb_PrimitiveComponent.getAll()) { + const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(c.getState_PrimitiveId()); + for (const p of ps) { + const pad = p.pad || []; + let w = (typeof pad[1]==='number')?pad[1]:0, h = (typeof pad[2]==='number')?pad[2]:0; + let cx = p.x, cy = p.y, poly = false; + if (String(pad[0]) === 'POLYGON' && Array.isArray(pad[1])) { + poly = true; + const nums = pad[1].filter(v => typeof v === 'number'); + const pts = []; + for (let k=0; k+1q[1]))].sort((a,b)=>a-b); + for (let b2=0; b2+1a-b); + for (let k=0; k+1 45 && rot < 135) { const t=w; w=h; h=t; } + out.push([c.designator, String(p.padNumber), Math.round(cx/MIL*1000)/1000, + Math.round(cy/MIL*1000)/1000, Math.round(w/MIL*1000)/1000, + Math.round(h/MIL*1000)/1000, p.layer, p.net||'', String(pad[0])]); + } +} +return out; +""" % MIL + + +def dump_pads(): + d = call(DUMP_JS, timeout=600) + io.open(PADS, 'w', encoding='utf-8').write(json.dumps(d, ensure_ascii=False)) + live = dump_live_positions() + io.open(ROT_JSON, 'w', encoding='utf-8').write( + json.dumps({k: v[2] for k, v in live.items()}, ensure_ascii=False, sort_keys=True)) + print(u'已写 _base_pads.json：%d 个焊盘' % len(d)) + return d + + +def dump_live_positions(): + d = call("const o={}; for(const c of await eda.pcb_PrimitiveComponent.getAll())" + " o[c.designator]=[c.x/%s,c.y/%s,(c.rotation||0)%%360,c.getState_Layer()]; return o;" + % (MIL, MIL)) + if len(d) != 138: + raise SystemExit(u'板上读到 %d 件，应为 138；拒绝覆盖 LIVE 快照' % len(d)) + out = {ref: [round(float(v[0]), 4), round(float(v[1]), 4), int(round(v[2])) % 360, v[3]] + for ref, v in sorted(d.items())} + io.open(LIVE_POS_JSON, 'w', encoding='utf-8').write(json.dumps(out, ensure_ascii=False, indent=2)) + return out + + +def rebuild_native(): + u"""`_base_pads.json` + `_base_place_live.json` → 封装原生偏移（反用镜像规则）。""" + P = json.load(io.open(PADS, encoding='utf-8')) + L = json.load(io.open(LIVE_POS_JSON, encoding='utf-8')) + nat = {} + for p in P: + x0, y0, rot, lay = L[p[0]] + a, b = rot_vec((360 - rot) % 360, p[2] - x0, p[3] - y0) + if lay == B.BOTTOM: + b = -b + w, h = (p[4], p[5]) if rot % 180 == 0 else (p[5], p[4]) + nat.setdefault(p[0], []).append([p[1], round(a, 4), round(b, 4), round(w, 4), + round(h, 4), p[7], p[8]]) + io.open(NATIVE, 'w', encoding='utf-8').write(json.dumps(nat, ensure_ascii=False)) + print(u'已重建 _base_native_pads.json：%d 件' % len(nat)) + return nat + + +def verify(pos, sz): + u"""读回位姿逐件对账 + 朝向断言（用**板上读回的焊盘**，不信离线模型）。""" + d = dump_pads() + live = json.load(io.open(LIVE_POS_JSON, encoding='utf-8')) + got, allp = {}, {} + for ref, pn, x, y, _w, _h, _lay, net, _sh in d: + got.setdefault(ref, {}).setdefault(pn, (x, y, net)) + # ⚠ 脚号会重复：插槽两个外壳盘都叫 65（u = ±19.5），J23 的 A1B12 / A4B9 各有好几块 + allp.setdefault((ref, pn), []).append((x, y)) + bad = [] + for ref, (x, y, rot) in sorted(pos.items()): + g = live.get(ref) + if not g: + bad.append(u'%s 板上没有' % ref) + continue + if abs(g[0] - x) > 0.02 or abs(g[1] - y) > 0.02 or g[2] % 360 != int(rot) % 360 \ + or g[3] != layer_of(ref): + bad.append(u'%s 读回 (%.2f,%.2f,%s°,L%s) != (%.2f,%.2f,%s°,L%s)' + % (ref, g[0], g[1], g[2], g[3], x, y, rot, layer_of(ref))) + + def pad(ref, pn): + return got.get(ref, {}).get(pn) + + # 1. 离线镜像模型 == 板上焊盘（全部件逐脚） + nat = native() + worst = (0.0, '') + for ref, (x, y, rot) in pos.items(): + for pn, _n, px, py in pads_at(nat, ref, x, y, rot): + gs = allp.get((ref, pn)) + if gs: + e = min(math.hypot(gx - px, gy - py) for gx, gy in gs) + if e > worst[0]: + worst = (e, '%s.%s' % (ref, pn)) + if worst[0] > 0.05: + bad.append(u'离线镜像模型和板上焊盘差 %.3f mm（%s）⇒ pad_off 的规则不对' % worst) + # 2. U32 下行口朝北、USB1 在西 + ux, uy = pos['U32'][0], pos['U32'][1] + p2, p12 = pad('U32', '2'), pad('U32', '12') + if not p2 or not p12: + bad.append(u'U32 的 2/12 脚没读到') + elif not (p2[1] > uy + 3.5 and p12[1] > uy + 3.5 and p2[0] < p12[0]): + bad.append(u'U32 下行口不对：USB1_DP (%.2f,%.2f) USB5_DP (%.2f,%.2f)，中心 y=%.2f' + % (p2[0], p2[1], p12[0], p12[1], uy)) + x61 = pad('U32', '61') + if x61 and x61[0] > ux - 3.5: + bad.append(u'U32 的 XTAL1 不在西侧（x=%.2f）' % x61[0]) + # 3. 插槽：+12V 在西、D± 在南排 x 47.5/48.5 + for i, ref in enumerate(SLOT_ORDER, start=1): + p2, p46, p47 = pad(ref, '2'), pad(ref, '46'), pad(ref, '47') + cy = B.slot_y(i) + if not (p2 and p46 and p47): + bad.append(u'%s 的 2/46/47 脚没读到' % ref) + continue + if p2[2] != '+12V' or p2[0] > B.SLOT_CX: + bad.append(u'%s 的 2 脚 %s 在 x=%.2f，应为西侧 +12V' % (ref, p2[2], p2[0])) + if abs(p46[0] - B.pin_x(-1.5)) > 0.05 or abs(p46[1] - (cy - B.PAD_ROW_DY)) > 0.05: + bad.append(u'%s 的 D+ 在 (%.2f,%.2f)，应在 (%.1f,%.2f)' + % (ref, p46[0], p46[1], B.pin_x(-1.5), cy - B.PAD_ROW_DY)) + # 4. U20 天线朝东、尖落在缺口里 + pa, pb = pad('U20', '1'), pad('U20', '40') + if not pa or not pb: + bad.append(u'U20 的 1/40 脚没读到') + else: + mx, my = (pa[0] + pb[0]) / 2.0, (pa[1] + pb[1]) / 2.0 + nk = B.notch_rect() + cx = pos['U20'][0] + if mx < cx + 5.0 or not (nk[1] <= my <= nk[3]) or not (nk[0] - 1.5 <= mx <= nk[0] + 0.5): + bad.append(u'U20 天线端（pin1/40 中点 %.2f,%.2f）没朝东对着缺口 x %.1f / y %.1f~%.1f' + % (mx, my, nk[0], nk[1], nk[3])) + # 5. 接口 / 输入链朝向 + j1, j1c = pad('J1', '1'), pos['J1'] + if j1 and j1[1] <= j1c[1]: + bad.append(u'J1 的 VIN_RAW 脚在南（y=%.2f），桶口朝向不对' % j1[1]) + a6 = pad('J23', 'A6') + if a6 and a6[1] <= pos['J23'][1]: + bad.append(u'J23 的信号脚在南（y=%.2f），口朝向不对' % a6[1]) + qs = [pad('Q1', n) for n in ('1', '2', '3', '5', '6', '7', '8')] + if all(qs) and not (sum(q[1] for q in qs[3:]) / 4 > sum(q[1] for q in qs[:3]) / 3): + bad.append(u'Q1 的 VIN_SW 排不在 VIN_FUSED 排北边') + if bad: + print(u'[X] 读回校验 %d 条不过:' % len(bad)) + for t in bad[:25]: + print(u' ' + t) + else: + print(u'[OK] %d 件位姿 / 层逐件对上；离线镜像模型与板上焊盘最大差 %.3f mm；' + u'U32 口朝北 USB1 在西、插槽 12V 在西 D± 在南排、U20 天线朝东入缺口、J1/J23/Q1 朝向全对' + % (len(pos), worst[0])) + return bad + + +def route_fixed_pads(pads): + u"""2 层版遗留接口：4 层版没有 ROUTE_FIX，恒等变换。""" + return pads, [] + + +if __name__ == '__main__': + if '--bbox' in sys.argv: + dump_bbox() + sys.exit(0) + if '--dump' in sys.argv: + dump_pads() + sys.exit(0) + if '--native' in sys.argv: + dump_pads() + rebuild_native() + sys.exit(0) + pos, unplaced, sz, aim = plan() + bad = selfcheck(pos, unplaced, sz) + nh = len(hand()) + print(u'底板摆位：%d 件（手排 %d + 排布 %d）；L1 %d 件 / L4 %d 件' + % (len(pos), nh, len(pos) - nh, sum(1 for r in pos if layer_of(r) == B.TOP), + sum(1 for r in pos if layer_of(r) == B.BOTTOM))) + if bad: + print(u'[X] 自检 %d 条不过:' % len(bad)) + for t in bad[:30]: + print(u' ' + t) + else: + print(u'[OK] 自检全过（全摆上 / 不出板 / 同面不重叠 / 背面限高 / 螺钉 / 过孔带 / 车道 / 天线净空）') + report(pos, sz, aim) + io.open(POS_JSON, 'w', encoding='utf-8').write( + json.dumps({k: list(v) + [layer_of(k)] for k, v in pos.items()}, ensure_ascii=False, indent=0)) + if '--push' in sys.argv: + if bad: + print(u'!! 自检不过，不下发') + sys.exit(1) + push(pos) + verify(pos, sz) + elif '--verify' in sys.argv: + verify(pos, sz) diff --git a/.claude/r2/plot_base.py b/.claude/r2/plot_base.py new file mode 100644 index 0000000..386c4c7 --- /dev/null +++ b/.claude/r2/plot_base.py @@ -0,0 +1,109 @@ +# -*- coding: utf-8 -*- +u"""离线画底板摆位（背面 L4，从上往下看）：两种 Hub 走廊并排，给用户对比。 + + /c/Python314/python .claude/r2/plot_base.py # 定稿（走廊 2）vs 草图原样（走廊 3） + /c/Python314/python .claude/r2/plot_base.py --one # 只画定稿（走廊 2） + +不碰 EasyEDA：直接调 `place_base.plan()`。背面件是**镜像后的真实本体框**（`body_rect` 已含翻面）。 +""" +import importlib +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +import matplotlib # noqa: E402 +matplotlib.use('Agg') +import matplotlib.pyplot as plt # noqa: E402 +from matplotlib.patches import Rectangle, Polygon, Circle # noqa: E402 +import pcb_base as B # noqa: E402 + +plt.rcParams['font.sans-serif'] = ['Microsoft YaHei', 'SimHei', 'DejaVu Sans'] +plt.rcParams['axes.unicode_minus'] = False + +ZCOL = {'A1': '#f4b6a0', 'A2': '#fcdcc8', 'A3': '#c9c3e0', 'A5': '#a8d1e6', + 'A6': '#cfe3ef', 'A4H': '#8fc3dd', 'A4M': '#bdb3db'} + + +def plan_for(hub3): + argv = sys.argv[:] + sys.argv = [a for a in argv if a != '--hub3'] + (['--hub3'] if hub3 else []) + import place_base as P + P = importlib.reload(P) + sys.argv = argv + pos, unplaced, sz, _aim = P.plan() + bad = P.selfcheck(pos, unplaced, sz) + return P, pos, sz, bad + + +def draw(ax, P, pos, sz, bad): + nat = P.native() + pg = P.page_of() + ax.add_patch(Polygon(B.outline_pts(), closed=True, fill=False, lw=1.2, ec='black')) + for i in range(1, B.SLOT_N + 1): + b = B.slot_body(i) + ax.add_patch(Rectangle((b[0], b[1]), b[2] - b[0], b[3] - b[1], fill=True, fc='#eeeeee', + ec='#888888', ls='--', lw=0.6, hatch='////', alpha=0.6)) + ref = B.USB_SLOT_REF[B.SLOT_N + 1 - i] + ax.text(b[2] + 0.4, (b[1] + b[3]) / 2, u'%s\n(L1)' % ref, fontsize=5, color='#666666', va='center') + # D± 脚（南排 x 47.5/48.5） + for u in (-1.5, -0.5): + ax.add_patch(Rectangle((B.pin_x(u) - 0.35, B.slot_y(i) - B.PAD_ROW_DY - 1.0), 0.7, 2.0, + fc='#7b3fa0', ec='none')) + for name, r in P.LANES.items(): + col = '#b58ad6' if name.startswith('DP') else ('#7cc47c' if name.startswith('I2C') else '#f0a040') + ax.add_patch(Rectangle((r[0], r[1]), r[2] - r[0], r[3] - r[1], fc=col, ec='none', alpha=0.35)) + for k, z in P.ZONES.items(): + ax.add_patch(Rectangle((z[0], z[1]), z[2] - z[0], z[3] - z[1], fill=False, + ec='#555555', ls=':', lw=0.6)) + ax.text(z[0] + 0.3, z[3] - 0.3, k, fontsize=6, va='top', color='#333333', weight='bold') + n = B.notch_rect() + ax.add_patch(Rectangle((n[0], n[1]), n[2] - n[0], n[3] - n[1], fc='white', ec='black', hatch='xx')) + a = P.antenna_keepout(sz, pos) + ax.add_patch(Rectangle((a[0], a[1]), a[2] - a[0], a[3] - a[1], fill=False, ec='red', ls='--', lw=0.6)) + for _n, (hx, hy) in B.MOUNT_HOLES.items(): + ax.add_patch(Circle((hx, hy), B.HOLE_D / 2, fc='white', ec='black')) + for ref, (x, y, rot) in pos.items(): + if P.layer_of(ref) != B.BOTTOM: + continue + r = P.body_rect(ref, x, y, rot, sz) + z = P.zone_of_ref(ref, pg) if ref in pg else None + ax.add_patch(Rectangle((r[0], r[1]), r[2] - r[0], r[3] - r[1], fc=ZCOL.get(z, '#dddddd'), + ec='#333333', lw=0.4)) + big = (r[2] - r[0]) * (r[3] - r[1]) > 9 + ax.text((r[0] + r[2]) / 2, (r[1] + r[3]) / 2, ref, fontsize=5.5 if big else 3.2, + ha='center', va='center', weight='bold' if big else 'normal') + # U32 下行口（USB1..5 的 DP 脚） + ux, uy, ur = pos['U32'] + for pn, _nn, px, py in P.pads_at(nat, 'U32', ux, uy, ur): + if pn in ('2', '4', '7', '9', '12'): + ax.plot(px, py, 'o', ms=2.2, color='#7b3fa0') + ax.text(px, py + 0.5, 'USB%d' % {'2': 1, '4': 2, '7': 3, '9': 4, '12': 5}[pn], + fontsize=3.5, color='#7b3fa0', ha='center', rotation=90, va='bottom') + L = P.dp_lengths(pos, nat) + txt = u' '.join(u'USB%d %.0f' % (i, v) for i, _r, v in L) + ax.set_title(u'Hub 在走廊 %d（y %.1f~%.1f） D± 最远 ≈ %.0f mm\n%s 自检 %s' + % (P.HUB_K, P._CH[1], P._CH[3], max(v for _i, _r, v in L), txt, + u'全过' if not bad else u'%d 条不过' % len(bad)), fontsize=8) + ax.set_xlim(-1, B.BW + 1) + ax.set_ylim(-1, B.BH + 1) + ax.set_aspect('equal') + ax.grid(True, lw=0.2, alpha=0.4) + ax.tick_params(labelsize=6) + + +if __name__ == '__main__': + out = sys.argv[1] + variants = [False] if '--one' in sys.argv else [False, True] + fig, axes = plt.subplots(1, len(variants), figsize=(8.5 * len(variants), 9.2), dpi=170) + if len(variants) == 1: + axes = [axes] + for ax, v in zip(axes, variants): + P, pos, sz, bad = plan_for(v) + draw(ax, P, pos, sz, bad) + fig.suptitle(u'底板背面 L4 摆位（从上往下看，背面件已镜像） 紫 = D± 车道 / 绿 = I²C 车道 / 橙 = 上行·USB6 上 L1 过孔带' + u' / 斜线 = 槽体过孔带 / 红虚线 = 天线净空', fontsize=9) + fig.tight_layout() + fig.savefig(out) + print('->', out) diff --git a/.claude/r2/plot_routes.py b/.claude/r2/plot_routes.py new file mode 100644 index 0000000..01501e9 --- /dev/null +++ b/.claude/r2/plot_routes.py @@ -0,0 +1,104 @@ +# -*- coding: utf-8 -*- +u"""离线画底板布线缓存（L4 / L1 并排，从上往下看），失败的脚标红叉。 + + /c/Python314/python .claude/r2/plot_routes.py + /c/Python314/python .claude/r2/plot_routes.py --zoom 30 25 65 50 # 只看一块（mm） + +只读 `_base_routes.json` + `_base_pads.json`，不碰 EasyEDA、不跑 A*。 +""" +import io +import json +import os +import re +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +import matplotlib # noqa: E402 +matplotlib.use('Agg') +import matplotlib.pyplot as plt # noqa: E402 +from matplotlib.patches import Rectangle, Polygon, Circle # noqa: E402 +import pcb_base as B # noqa: E402 + +plt.rcParams['font.sans-serif'] = ['Microsoft YaHei', 'SimHei', 'DejaVu Sans'] +plt.rcParams['axes.unicode_minus'] = False + +POWER = ('VIN_RAW', 'VIN_FUSED', 'VIN_SW', '+5V', '+3V3', '+3V3_HUB', 'FAN_12V_SW') + + +def color(net): + if net == 'GND': + return '#2e9e44' + if net == '+12V': + return '#d62728' + if net.endswith('_DP') or net.endswith('_DM') or net in ('UP_DP', 'UP_DM'): + return '#8e44ad' + if net in POWER: + return '#ff8c00' + return '#1f5fbf' + + +def main(): + out = sys.argv[1] + zoom = None + if '--zoom' in sys.argv: + k = sys.argv.index('--zoom') + zoom = [float(v) for v in sys.argv[k + 1:k + 5]] + c = json.load(io.open(os.path.join(HERE, '_base_routes.json'), encoding='utf-8')) + pads = json.load(io.open(os.path.join(HERE, '_base_pads.json'), encoding='utf-8')) + pads = [p for p in pads if p[4] >= 0.05 and p[5] >= 0.05] + fail = set() + for m in c['logs']: + for ref, pin in re.findall(r'([A-Z]+[0-9]+[a-z]*)\.([A-Za-z0-9#]+)', m): + fail.add(('J1' if ref == 'J1dc' else ref, pin)) + fig, axes = plt.subplots(1, 2, figsize=(19, 9.8), dpi=150) + for ax, lay, title in ((axes[0], 2, u'L4 器件面'), (axes[1], 1, u'L1 插槽面')): + ax.add_patch(Polygon(B.outline_pts(), closed=True, fill=False, lw=1.0, ec='black')) + if lay == 1: + for r in B.l1_12v_rects(): + ax.add_patch(Rectangle((r[0], r[1]), r[2] - r[0], r[3] - r[1], + fc='#f7c6c6', ec='none', alpha=0.6)) + for p in pads: + if p[6] not in (lay, 12): + continue + ax.add_patch(Rectangle((p[2] - p[4] / 2, p[3] - p[5] / 2), p[4], p[5], + fc='#bbbbbb' if p[6] == lay else '#dddddd', ec='none')) + for s in c['segs']: + if s[0] != lay: + continue + lw = max(0.3, s[5] * (3.0 if zoom else 1.2)) + ax.plot([s[1], s[3]], [s[2], s[4]], color=color(s[6]), lw=lw, solid_capstyle='round') + for v in c['vias']: + ax.add_patch(Circle((v[0], v[1]), 0.3, fc=color(v[2]), ec='black', lw=0.2)) + for p in pads: + if (p[0], str(p[1])) in fail and p[6] in (lay, 12): + ax.plot(p[2], p[3], 'x', color='red', ms=6 if zoom else 3, mew=1.2) + for _n, (hx, hy) in B.MOUNT_HOLES.items(): + ax.add_patch(Circle((hx, hy), B.HOLE_D / 2, fc='white', ec='black')) + if zoom: + ax.set_xlim(zoom[0], zoom[2]) + ax.set_ylim(zoom[1], zoom[3]) + # 放大时标出焊盘的「位号.脚」，失败的那几只一眼能认 + for p in pads: + if p[6] in (lay, 12) and zoom[0] <= p[2] <= zoom[2] and zoom[1] <= p[3] <= zoom[3]: + if p[0].startswith('J3') and p[7] in ('GND', ''): + continue + ax.text(p[2], p[3], '%s.%s' % (p[0], p[1]), fontsize=3.2, ha='center', + va='center', color='red' if (p[0], str(p[1])) in fail else '#333333') + else: + ax.set_xlim(-1, B.BW + 1) + ax.set_ylim(-1, B.BH + 1) + ax.set_aspect('equal') + ax.set_title(title, fontsize=10) + ax.tick_params(labelsize=6) + ax.grid(True, lw=0.2, alpha=0.4) + fig.suptitle(u'底板布线缓存：%d 段 / %d 孔 / %d 条未完成 紫 = D± 红 = +12V 绿 = GND 橙 = 电源 蓝 = 信号 红叉 = 失败的脚' + % (len(c['segs']), len(c['vias']), len(c['logs'])), fontsize=10) + fig.tight_layout() + fig.savefig(out) + print('->', out) + + +if __name__ == '__main__': + main() diff --git a/.claude/r2/pour_base.py b/.claude/r2/pour_base.py new file mode 100644 index 0000000..f2baf2d --- /dev/null +++ b/.claude/r2/pour_base.py @@ -0,0 +1,606 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 铺铜 + 缝合过孔 + 断面校核（M5，**4 层**，D15）。 + + /c/Python314/python .claude/r2/pour_base.py # 只算 + 自检 + 断面校核 + /c/Python314/python .claude/r2/pour_base.py --stitch # 打 GND 缝合过孔 + /c/Python314/python .claude/r2/pour_base.py --push # 清旧铜面 + 建 + 重填 + /c/Python314/python .claude/r2/pour_base.py --rebuild # 只重填 + /c/Python314/python .claude/r2/pour_base.py --clear # 清掉全部铜面 + +2 层版整份在 `archive_base2L/pour_base.py`。 + +⛔ **顺序**：摆位 → 布线（服务器）→ `route_base --push` → **缝合过孔** → **铺铜** → DRC + `board_check`。 + 重跑布线要把缝合过孔一起重跑。 + +## 叠层（D15，2026-09-10 L2 由 GND 改 +3V3） + +| 设计 | EasyEDA | id | 铺什么 | +|---|---|---|---| +| L1 | Top | 1 | 12V 大铜（`pcb_base.l1_12v_rects`，硬）+ GND 底填 | +| L2 | Inner1 | 15 | **整层 +3V3** | +| L3 | Inner2 | 16 | **整层 GND**（L4 上全部器件与 D± 的参考）| +| L4 | Bottom | 2 | 入口链 VIN_RAW / VIN_FUSED / VIN_SW（硬）+ Rs6 西侧 12V 铜块（硬）+ GND 底填 | + +「硬」= 几何算出来、要过断面校核；GND 底填优先级最低，自然绕开别人的铜。 + +## 入口链（L4，电流自南向北：J1 → F1 → Q1 → C2/C3/D1 → Rs6） + +三段是**串联**的，中间隔着 F1 / Q1 —— 铜面搭上就把器件短路了。每段取本网在入口链带里的焊盘外框再外扩， +相邻两段在 y 方向按「两网相邻焊盘的空隙中点」切开（2 层版 `clip_chain` 的教训：按重叠区中点切会切进 Q1 里面）。 +Q1 栅极网络（DZ1 / C1 / R1 与 GATE 脚）整团挖掉，给 GATE 走线。 +U13.10（Kelvin 取样）与 C4（Rs6 北侧的 VIN_SW 去耦）不撑大铜面：前者走专线，后者会把 VIN_SW 拉过 Rs6 的 +12V 端。 + +## 断面校核 + +在铜面上画断面线，数「这条线上属于本网、没被别人的焊盘 / 过孔 / 同层导线占掉」的**最宽一段**。 +入口链与 L1 12V 主块的电流都沿 y ⇒ 横切、量 x 方向净宽。串联元件本身占的 y 段跳过（量到的是元件宽度不是铜）。 +""" +import io +import json +import math +import os +import sys +import time + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 +import place_base as PL # noqa: E402 + +PCB = B.PCB +MIL = B.MIL +L1, L2, L3, L4 = 1, 15, 16, 2 # EasyEDA 层 id：Top / Inner1 / Inner2 / Bottom +LNAME = {L1: 'L1', L2: 'L2', L3: 'L3', L4: 'L4'} # ⚠ 打印用设计层名 —— 直接打 id 的话底层是「2」，看着像 L2 + +INSET = 0.5 # 铜面离板边 +CLR = 0.25 # 断面校核里别人的铜要让开多少 +VIA_D, VIA_HOLE = 0.6, 0.3 +STITCH_PITCH = 4.0 +STITCH_CLR = 0.5 # 缝合过孔到任何焊盘 / 导线 / 过孔的净距 +PADS = os.path.join(HERE, '_base_pads.json') +ROUTES = os.path.join(HERE, '_base_routes.json') +ROUTE_SCHEMA = 8 + +CHAIN = [('VIN_RAW', 1), ('VIN_FUSED', 2), ('VIN_SW', 3)] # (网, 优先级)，自南向北 +CHAIN_GROW = 1.2 +CHAIN_SKIP = {'VIN_SW': ('U13', 'C4')} # 不撑大铜面的焊盘（见文件头） +GATE_PARTS = ('DZ1', 'C1', 'R1') +NOTCH_CLR = 0.3 + +# (铜面名前缀, 标签, 网, 电流方向, 要求净宽, 是否强制, 层, 是否跳过串联元件) +CUTS = [ + ('PWR-VIN_RAW', u'J1→F1', 'VIN_RAW', 'y', 8.0, False, L4, True), + ('PWR-VIN_FUSED', u'F1→Q1', 'VIN_FUSED', 'y', 8.0, False, L4, True), + # ⚠ VIN_RAW / VIN_FUSED 的瓶颈是 DC-005 的脚与 1206 保险本身（用户 2026-09-08 接受的已知风险，设计文档 §22.6） + ('PWR-VIN_SW', u'Q1→储能→Rs6', 'VIN_SW', 'y', 6.5, True, L4, True), + # L1 主块上挂满了背面件的 GND / +3V3 / +12V 过孔（反焊盘），串联元件窗口对它没意义 + ('PWR-12V-L1', u'L1 12V 主块', '+12V', 'y', 8.0, True, L1, False), +] + + +def mil(v): + return round(v * MIL, 4) + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" % PCB) + +_PADS = [None] + + +def pads(): + u"""板上焊盘（丢掉多边形拆条的零尺寸残留，同 route_base.load_pads）。""" + if _PADS[0] is None: + _PADS[0] = [p for p in json.load(io.open(PADS, encoding='utf-8')) + if p[4] >= 0.05 and p[5] >= 0.05] + return _PADS[0] + + +_ROUTES = [None] + + +def routes(): + if _ROUTES[0] is None: + c = json.load(io.open(ROUTES, encoding='utf-8')) if os.path.exists(ROUTES) else {} + if c.get('schema') != ROUTE_SCHEMA: + _ROUTES[0] = ([], [], None) + else: + _ROUTES[0] = (c['segs'], c['vias'], c.get('v12_patch')) + return _ROUTES[0] + + +def _layers_of(p): + return (L1, L4) if p[6] == 12 else ((L1,) if p[6] == 1 else (L4,)) + + +# ── 铜面几何 ───────────────────────────────────────────────────────────── +def keepouts(): + u"""所有层都不许铺铜：U20 天线净空 + 天线缺口 + 四个 M3 孔。""" + d = json.load(io.open(os.path.join(HERE, '_base_place.json'), encoding='utf-8')) + pos = {k: (v[0], v[1], v[2]) for k, v in d.items()} + n = B.notch_rect() + out = [PL.antenna_keepout(PL.sizes(), pos), + (n[0] - INSET, n[1] - INSET, n[2] + INSET, n[3] + INSET)] + r = B.HOLE_D / 2.0 + 0.6 + for (hx, hy) in B.MOUNT_HOLES.values(): + out.append((hx - r, hy - r, hx + r, hy + r)) + return out + + +def tiles(x0, y0, x1, y1, cuts): + u"""把矩形按 `cuts` 切成若干块**单环**矩形（多环复杂多边形会把客户端挂死，刀片 §24）。""" + xs = sorted(set([x0, x1] + [v for c in cuts for v in (c[0], c[2]) if x0 < v < x1])) + out = [] + for xa, xb in zip(xs, xs[1:]): + if xb - xa < 0.6: + continue + iv = [] + for c in cuts: + # ⛔ y 方向也要真的相交：禁区整个在矩形上方 / 下方时，夹紧会得到一个倒过来的区间， + # 照样切出一块瓦片 —— 实测 VIN_RAW 被栅极缺口「切」出一块伸到 y 22.65 的瓦片（它的上沿本来是 17.62） + if c[0] < xb - 1e-9 and xa < c[2] - 1e-9 and c[1] < y1 - 1e-9 and y0 < c[3] - 1e-9: + iv.append([max(y0, c[1]), min(y1, c[3])]) + iv.sort() + merged = [] + for a, b in iv: # ⛔ 先合并再配对（嵌套禁区会让奇偶配对错位） + if merged and a <= merged[-1][1] + 1e-9: + merged[-1][1] = max(merged[-1][1], b) + else: + merged.append([a, b]) + cur = y0 + for a, b in merged + [[y1, y1]]: + if a - cur > 0.6: + out.append((round(xa, 3), round(cur, 3), round(xb, 3), round(a, 3))) + cur = max(cur, b) + return out + + +def chain_pads(net): + z = B.ZONES['A1'] + skip = CHAIN_SKIP.get(net, ()) + return [p for p in pads() if p[7] == net and p[0] not in GATE_PARTS and p[0] not in skip + and z[0] <= p[2] <= z[2] and z[1] <= p[3] <= z[3]] + + +def chain_rect(net): + ps = chain_pads(net) + if not ps: + return None + g = CHAIN_GROW + z = B.ZONES['A1'] + return (max(z[0], min(p[2] - p[4] / 2 for p in ps) - g), + max(INSET, min(p[3] - p[5] / 2 for p in ps) - g), + min(z[2], max(p[2] + p[4] / 2 for p in ps) + g), + min(z[3], max(p[3] + p[5] / 2 for p in ps) + g)) + + +def clip_chain(chain): + u"""相邻两段在 y 方向切开：刀口 = 「南段最北的焊盘上沿」与「北段最南的焊盘下沿」的中点（在 x 重叠带里取）。""" + out = [r for _n, r in chain] + for i in range(len(out) - 1): + a, b = out[i], out[i + 1] + if a[3] <= b[1]: + continue + x0, x1 = max(a[0], b[0]), min(a[2], b[2]) + pa = [p for p in chain_pads(chain[i][0]) if p[2] + p[4] / 2 > x0 and p[2] - p[4] / 2 < x1] + pb = [p for p in chain_pads(chain[i + 1][0]) if p[2] + p[4] / 2 > x0 and p[2] - p[4] / 2 < x1] + na = max([p[3] + p[5] / 2 for p in pa] or [None]) + sb = min([p[3] - p[5] / 2 for p in pb] or [None]) + m = (na + sb) / 2.0 if (na is not None and sb is not None and na < sb) else (a[3] + b[1]) / 2.0 + out[i] = (a[0], a[1], a[2], round(min(a[3], m - CLR / 2), 3)) + out[i + 1] = (b[0], round(max(b[1], m + CLR / 2), 3), b[2], b[3]) + return out + + +def gate_notch(): + u"""Q1 栅极网络整团挖掉（GATE 焊盘 + 三颗栅极件外框，外扩 NOTCH_CLR）。""" + out = [] + for p in pads(): + if p[7] == 'GATE' or p[0] in GATE_PARTS: + out.append((round(p[2] - p[4] / 2 - NOTCH_CLR, 3), round(p[3] - p[5] / 2 - NOTCH_CLR, 3), + round(p[2] + p[4] / 2 + NOTCH_CLR, 3), round(p[3] + p[5] / 2 + NOTCH_CLR, 3))) + return out + + +CHAIN_DEBUG = [] # [(网, 原始外框, 裁剪后, 挖缺口后的瓦片)]，打印核对用 + + +def plan(): + u"""[(name, net, layer, rect, priority)]，priority 小的先占地盘。""" + outs = [] + CHAIN_DEBUG[:] = [] + chain = [(net, prio, chain_rect(net)) for net, prio in CHAIN] + chain = [c for c in chain if c[2]] + chain.sort(key=lambda c: (c[2][1] + c[2][3]) / 2.0) + clipped = clip_chain([(c[0], c[2]) for c in chain]) + notch = gate_notch() + for (net, prio, raw), r in zip(chain, clipped): + parts = tiles(r[0], r[1], r[2], r[3], notch) + parts.sort(key=lambda t: -(t[2] - t[0]) * (t[3] - t[1])) + CHAIN_DEBUG.append((net, raw, r, parts)) + for k, t in enumerate(parts): + outs.append(('PWR-%s%s' % (net, '-%d' % k if k else ''), net, L4, t, prio)) + ko = keepouts() + v12 = routes()[2] + if v12: + outs.append(('PWR-12V-PATCH', '+12V', L4, tuple(v12), 2)) + # L1 12V：主块要绕开两个 M3 孔（(4,4) / (4,94) 就在主块里），同样切成单环瓦片 + k = 0 + for r in B.l1_12v_rects(): + for t in tiles(r[0], r[1], r[2], r[3], ko): + outs.append(('PWR-12V-L1%s' % ('-%d' % k if k else ''), '+12V', L1, t, 2)) + k += 1 + d = INSET + for tag, net, lay, prio in (('3V3-L2', '+3V3', L2, 5), ('GND-L3', 'GND', L3, 9), + ('GND-L1', 'GND', L1, 9), ('GND-L4', 'GND', L4, 9)): + for k, t in enumerate(tiles(d, d, B.BW - d, B.BH - d, ko)): + outs.append(('%s-%d' % (tag, k), net, lay, t, prio)) + return outs + + +def selfcheck(ps): + bad = [] + ko = keepouts() + for name, net, lay, r, _p in ps: + if r[2] - r[0] < 0.6 or r[3] - r[1] < 0.6: + bad.append(u'%s 太小: %s' % (name, r)) + if r[0] < INSET - 1e-6 or r[1] < INSET - 1e-6 or r[2] > B.BW - INSET + 1e-6 or r[3] > B.BH - INSET + 1e-6: + bad.append(u'%s 出了内缩线: %s' % (name, r)) + for k in ko: + if r[0] < k[2] - 1e-6 and k[0] < r[2] - 1e-6 and r[1] < k[3] - 1e-6 and k[1] < r[3] - 1e-6: + bad.append(u'%s 压进净空区 %s' % (name, tuple(round(v, 1) for v in k))) + hard = [(n, net, l, r) for (n, net, l, r, _p) in ps if n.startswith('PWR-')] + for i, (na, neta, la, a) in enumerate(hard): + for (nb, netb, lb, b) in hard[i + 1:]: + if neta == netb or la != lb: + continue + if a[0] < b[2] and b[0] < a[2] and a[1] < b[3] and b[1] < a[3]: + bad.append(u'%s(%s) 与 %s(%s) 同层重叠 —— 串联的两段搭上就把器件短路了' % (na, neta, nb, netb)) + return bad + + +# ── 断面校核 ───────────────────────────────────────────────────────────── +def _blocks(net, layer, axis, t): + u"""断面线（axis='y' ⇒ 横线 y=t；'x' ⇒ 竖线 x=t）上被别人占掉的区间：(切断, 孔洞)。 + + ⚠ 两类要分开：同层的**导线**把铺铜切成互不相连的几条（取最宽的一条）； + **焊盘和过孔**是孤立的岛 / 洞，铜从四周绕过去 —— 扣掉洞宽、不切断。 + 一排挨着的焊盘（缝 < 2×净距）按洞合并扣除，效果和切断一样，所以这个判据对针排也成立。 + 第一版把过孔、焊盘都当切断：L1 12V 主块被背面件的孔和 C2/C3 的通孔焊盘「切」成 4.95 / 6.20 mm。 + """ + out, holes = [], [] + for p in pads(): + if p[7] == net or layer not in _layers_of(p): + continue + if axis == 'y' and p[3] - p[5] / 2 - CLR <= t <= p[3] + p[5] / 2 + CLR: + holes.append((p[2] - p[4] / 2 - CLR, p[2] + p[4] / 2 + CLR)) + if axis == 'x' and p[2] - p[4] / 2 - CLR <= t <= p[2] + p[4] / 2 + CLR: + holes.append((p[3] - p[5] / 2 - CLR, p[3] + p[5] / 2 + CLR)) + segs, vias, _v = routes() + for s in segs: + if s[6] == net or s[0] != layer: + continue + # ⚠ 平面网（GND / +3V3 / +12V）的线都是「焊盘 → 自己的过孔」那一小截引出脚，是孤立的岛， + # 铜从四周绕过去 ⇒ 按洞扣。只有信号线会从铜面一边穿到另一边、真的切断。 + # （实测：VIN_SW 最窄的那一刀上只有 C6 地脚 0.8 mm 的引出脚，却被当成切断量成 6.07 mm。） + dst = holes if s[6] in ('GND', '+3V3', '+12V') else out + hw = s[5] / 2.0 + CLR + if axis == 'y': + y0, y1 = sorted((s[2], s[4])) + if y0 - hw <= t <= y1 + hw: + x0, x1 = sorted((s[1], s[3])) + dst.append((x0 - hw, x1 + hw)) + else: + x0, x1 = sorted((s[1], s[3])) + if x0 - hw <= t <= x1 + hw: + y0, y1 = sorted((s[2], s[4])) + dst.append((y0 - hw, y1 + hw)) + r = VIA_D / 2.0 + CLR + for v in vias: # 通孔：每一层都占，但只是洞 + if v[2] == net: + continue + c, o = (v[1], v[0]) if axis == 'y' else (v[0], v[1]) + if abs(c - t) <= r: + holes.append((o - r, o + r)) + return out, holes + + +def cut_width(net, rects, axis, t, layer): + u"""`rects` = 本网同层的几块瓦片（同网相邻即连成一片，先在断面线上合并）。返回最宽一条的净宽。""" + iv = [] + for rect in rects: + if (rect[1] <= t <= rect[3]) if axis == 'y' else (rect[0] <= t <= rect[2]): + iv.append(((rect[0], rect[2]) if axis == 'y' else (rect[1], rect[3]))) + iv.sort() + spans = [] + for a, b in iv: + if spans and a <= spans[-1][1] + 1e-6: + spans[-1] = (spans[-1][0], max(spans[-1][1], b)) + else: + spans.append((a, b)) + if not spans: + return 0.0 + cuts, holes = _blocks(net, layer, axis, t) + for (b0, b1) in cuts: + nxt = [] + for (a0, a1) in spans: + if b1 <= a0 or b0 >= a1: + nxt.append((a0, a1)) + continue + if b0 > a0: + nxt.append((a0, b0)) + if b1 < a1: + nxt.append((b1, a1)) + spans = nxt + best = 0.0 + for (a0, a1) in spans: + # 洞：合并重叠的反焊盘之后按实际落在这一条里的长度扣 + hs = sorted((max(a0, h0), min(a1, h1)) for (h0, h1) in holes if h1 > a0 and h0 < a1) + lost, cur = 0.0, a0 + for h0, h1 in hs: + if h1 > cur: + lost += h1 - max(h0, cur) + cur = h1 + best = max(best, (a1 - a0) - lost) + return best + + +def series_windows(net): + u"""这个网自己串联元件占的外框（整颗器件，不只本网那只脚）。""" + own = set(p[0] for p in pads() if p[7] == net) + by = {} + for p in pads(): + if p[0] not in own: + continue + b = by.setdefault(p[0], [1e9, 1e9, -1e9, -1e9]) + b[0] = min(b[0], p[2] - p[4] / 2); b[2] = max(b[2], p[2] + p[4] / 2) + b[1] = min(b[1], p[3] - p[5] / 2); b[3] = max(b[3], p[3] + p[5] / 2) + return by + + +def check_cuts(ps): + print(u'') + print(u'载流断面校核（逐刀切，取最窄一刀）:') + if not routes()[0]: + print(u' ⚠ 没有 4 层布线缓存（schema %d），只按焊盘 / 过孔扣' % ROUTE_SCHEMA) + bad = [] + byname = {} + for (n, _net, _l, r, _p) in ps: + byname.setdefault(n, []).append(r) + for key, label, net, axis, need, must, layer, skip_series in CUTS: + rs = [r for n, v in byname.items() if n == key or n.startswith(key + '-') for r in v] + if not rs: + print(u' %-14s %-9s [X] 这一段没有铜面' % (label, net)) + bad.append(label) + continue + r = (min(q[0] for q in rs), min(q[1] for q in rs), max(q[2] for q in rs), max(q[3] for q in rs)) + skip = [] + if skip_series: + for ref, b in series_windows(net).items(): + if b[0] > r[2] or b[2] < r[0] or b[1] > r[3] or b[3] < r[1]: + continue + skip.append((ref, (b[1] - CLR, b[3] + CLR) if axis == 'y' else (b[0] - CLR, b[2] + CLR))) + lo, hi = (r[1], r[3]) if axis == 'y' else (r[0], r[2]) + hs = [] + t = lo + 0.25 + while t <= hi - 0.25: + if not any(a <= t <= b for _ref, (a, b) in skip): + hs.append((cut_width(net, rs, axis, t, layer), t)) + t += 0.25 + worst = min(hs) if hs else (0.0, 0.0) + ok = worst[0] >= need + print(u' %-14s %-9s 铜面 %5.1f×%5.1f 最窄 %5.2f mm（%s=%.2f，要 %.1f） %s' + % (label, net, r[2] - r[0], r[3] - r[1], worst[0], axis, worst[1], need, + u'[OK]' if ok else (u'[X] 不够' if must else u'[~] 瓶颈在连接器 / 保险，不强制'))) + if skip: + print(u' （跳过串联元件 %s）' % ' '.join(sorted(ref for ref, _w in skip))) + if not ok and must: + bad.append(u'%s %s 最窄只有 %.2f mm' % (label, net, worst[0])) + return bad + + +# ── 缝合过孔 ───────────────────────────────────────────────────────────── +def _seg_d(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L = dx * dx + dy * dy + t = 0.0 if L < 1e-12 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L)) + return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + + +def stitch_points(ps): + u"""GND 缝合过孔（4 mm 网格）：L1 / L4 的 GND 底填会被信号切成岛，每块岛要有孔接到 L3，否则被当孤岛删掉 + （`rebuildCopperRegion` / 铺铜管理器 / DRC 三处都不报，刀片 §24.4）。 + ⛔ 硬功率铜面（入口链、12V 铜块、L1 12V 大铜）里不打：GND 孔只会在大电流铜上掏洞，断面校核看不到。""" + segs, vias, _v = routes() + r = VIA_D / 2.0 + STITCH_CLR + ko = keepouts() + [rr for (n, _net, _l, rr, _p) in ps if n.startswith('PWR-')] + out = [] + y = INSET + 2.0 + while y <= B.BH - INSET - 2.0: + x = INSET + 2.0 + while x <= B.BW - INSET - 2.0: + ok = not any(k[0] - r < x < k[2] + r and k[1] - r < y < k[3] + r for k in ko) + if ok: + ok = not any(p[2] - p[4] / 2 - r < x < p[2] + p[4] / 2 + r and + p[3] - p[5] / 2 - r < y < p[3] + p[5] / 2 + r for p in pads()) + if ok: + ok = not any(s[6] != 'GND' and _seg_d(x, y, s[1], s[2], s[3], s[4]) < r + s[5] / 2.0 + for s in segs) + if ok: + ok = not any(math.hypot(x - v[0], y - v[1]) < VIA_D + STITCH_CLR for v in vias) + if ok: + out.append((round(x, 3), round(y, 3))) + x += STITCH_PITCH + y += STITCH_PITCH + return out + + +def stitch(ps): + pts = stitch_points(ps) + print(u'GND 缝合过孔 %d 个（%g mm 网格）' % (len(pts), STITCH_PITCH)) + # ⚠ 只删**旧的缝合孔**：在缝合网格上、且**不在布线缓存里**的 GND 孔。 + # 布线的 GND 平面孔在 0.125 网格上，个别会恰好落在缝合网格点上 —— 只按网格删会把它们删掉，焊盘就断了。 + keep = [[round(v[0], 3), round(v[1], 3)] for v in routes()[1] if v[2] == 'GND'] + JS = OPEN + u""" +const MIL = %s, P = %s, D = %s, H = %s, PITCH = %s, OFF = %s, KEEP = %s; +const onGrid = v => { const q = (v/MIL - OFF) / PITCH; return Math.abs(q - Math.round(q)) < 1e-3; }; +const kept = (x, y) => KEEP.some(k => Math.abs(k[0] - x/MIL) < 0.01 && Math.abs(k[1] - y/MIL) < 0.01); +let old = 0; +for (const v of (await eda.pcb_PrimitiveVia.getAll()||[])) + if (String(v.net) === 'GND' && onGrid(v.x) && onGrid(v.y) && !kept(v.x, v.y)) { + await eda.pcb_PrimitiveVia.delete(v.primitiveId); old++; } +let n = 0; +for (const p of P) { + try { await eda.pcb_PrimitiveVia.create('GND', p[0]*MIL, p[1]*MIL, H*MIL, D*MIL); n++; } catch (e) {} +} +await eda.pcb_Document.save(); +return {deleted: old, made: n, now: (await eda.pcb_PrimitiveVia.getAll()||[]).length}; +""" % (MIL, json.dumps(pts), VIA_D, VIA_HOLE, STITCH_PITCH, INSET + 2.0, json.dumps(keep)) + print(call(JS, timeout=900)) + + +# ── 下发铺铜 ───────────────────────────────────────────────────────────── +JS_DEL = OPEN + u""" +let n = 0; +for (const old of await eda.pcb_PrimitivePour.getAll()) { + await eda.pcb_PrimitivePour.delete(old.primitiveId); n++; } +await eda.pcb_Document.save(); +return {deleted: n}; +""" + +JS_MAKE = OPEN + u""" +const PLAN = %s; +for (const p of PLAN) { + const poly = await eda.pcb_MathPolygon.createComplexPolygon([p.src]); + if (!poly) continue; + try { await eda.pcb_PrimitivePour.create(p.net, p.layer, poly, 'solid', false, + p.name, p.prio, 10); } catch (e) {} +} +return {made: (await eda.pcb_PrimitivePour.getAll()) + .map(x => String(x.pourName || '').toUpperCase())}; +""" + +JS_REBUILD = OPEN + u""" +const sleep = ms => new Promise(r => setTimeout(r, ms)); +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +const leaf = (txt) => { for (const el of document.querySelectorAll('*')) + if (el.children.length===0 && (el.textContent||'').trim()===txt) return el; return null; }; +const btn = (txt) => { for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()===txt && b.offsetParent!==null) return b; return null; }; +if (!fire(leaf('工具'))) return {err: 'no 工具'}; +await sleep(900); +if (!fire(leaf('铺铜管理器...'))) return {err: 'no 铺铜管理器'}; +await sleep(2500); +const b = btn('重建所有'); +if (!b) return {err: 'no 重建所有'}; +return {fired: fire(b)}; +""" + +JS_POLL = u"return {poured: (await eda.pcb_PrimitivePoured.getAll()).length};" + +JS_DONE = u""" +const propsOf = el => { for (const k of Object.keys(el)) if (k.startsWith('__reactProps$')) return el[k]; return null; }; +const fire = (el) => { let t = el; for (let i=0;i<8&&t;i++){const q=propsOf(t); + if(q&&typeof q.onClick==='function'){q.onClick({target:t,currentTarget:t,stopPropagation(){},preventDefault(){},nativeEvent:{},button:0,detail:1});return true;} t=t.parentElement;} return false; }; +let ok = null; +for (const b of document.querySelectorAll('button')) + if ((b.innerText||'').trim()==='确认' && b.offsetParent!==null) { ok = b; break; } +if (ok) fire(ok); +await new Promise(r => setTimeout(r, 1500)); +await eda.pcb_Document.save(); +return {poured: (await eda.pcb_PrimitivePoured.getAll()).length, + pour: (await eda.pcb_PrimitivePour.getAll()).length}; +""" + + +def rrect_src(x0, y0, x1, y1): + pts = [(x0, y0), (x1, y0), (x1, y1), (x0, y1), (x0, y0)] # ⚠ 必须显式闭合 + a = [mil(pts[0][0]), mil(pts[0][1])] + for p in pts[1:]: + a += ['L', mil(p[0]), mil(p[1])] + return a + + +def rebuild(): + u"""重建所有铺铜（走 GUI —— `rebuildCopperRegion()` 是坏的，刀片 §24 已查清）。""" + print(call(JS_REBUILD, timeout=180)) + last, same = -1, 0 + for _ in range(40): + time.sleep(6) + n = call(JS_POLL, timeout=120)['poured'] + print(u' 已填 %d 块' % n) + same = same + 1 if n == last else 0 + last = n + if same >= 2 and n > 0: + break + print(call(JS_DONE, timeout=180)) + + +def push(ps): + print(call(JS_DEL, timeout=300)) + arr = [{'name': n, 'net': net, 'layer': l, 'prio': p, 'src': rrect_src(*r)} + for (n, net, l, r, p) in ps] + made = [] + for k in range(0, len(arr), 12): + made += call(JS_MAKE % json.dumps(arr[k:k + 12], ensure_ascii=False), timeout=600)['made'] + want = set(n.upper() for (n, _net, _l, _r, _p) in ps) + got = set(made) + print(u'铜面建了 %d / %d 块' % (len(want & got), len(want))) + if want - got: + print(u' [!] 没建上: %s' % ' '.join(sorted(want - got))) + rebuild() + + +if __name__ == '__main__': + if '--clear' in sys.argv: + print(call(JS_DEL, timeout=300)) + sys.exit(0) + ps = plan() + bad = selfcheck(ps) + print(u'入口链（L4）逐段核对：原始外框 → 裁剪后 → 挖栅极缺口后的瓦片') + for net, raw, r, parts in CHAIN_DEBUG: + f = lambda q: u'x %.2f~%.2f y %.2f~%.2f' % (q[0], q[2], q[1], q[3]) # noqa: E731 + print(u' %-9s 原始 %s → 裁剪 %s' % (net, f(raw), f(r))) + for t in parts: + e = 0.01 # 瓦片坐标四舍五入到 0.001，裁剪框没有 + out = u' ⚠ 出了裁剪框' if (t[1] < r[1] - e or t[3] > r[3] + e or + t[0] < r[0] - e or t[2] > r[2] + e) else u'' + print(u' 瓦片 %s%s' % (f(t), out)) + if out: + bad.append(u'%s 的瓦片 %s 出了裁剪框' % (net, f(t))) + print(u'计划建 %d 块铜面：' % len(ps)) + for name, net, lay, r, prio in ps: + if name.startswith('PWR-') or name.endswith('-0'): + print(u' %-15s net=%-9s %s x %6.2f~%6.2f y %6.2f~%6.2f prio=%d' + % (name, net, LNAME[lay], r[0], r[2], r[1], r[3], prio)) + for tag in ('3V3-L2', 'GND-L3', 'GND-L1', 'GND-L4'): + print(u' （%s 瓦片 %d 块，绕开天线净空 / 缺口 / 四个 M3 孔）' + % (tag, sum(1 for p in ps if p[0].startswith(tag + '-')))) + if bad: + print(u'[X] 自检 %d 条不过:' % len(bad)) + for t in bad: + print(u' ' + t) + else: + print(u'[OK] 自检全过（不出内缩线 / 不压净空 / 入口链各段与 12V 铜块同层互不重叠）') + bad += check_cuts(ps) + if '--stitch' in sys.argv: + stitch(ps) + if '--push' in sys.argv: + if bad: + sys.exit(u'!! 自检 / 断面不过，不下发') + push(ps) + elif '--rebuild' in sys.argv: + rebuild() diff --git a/.claude/r2/push_subset.py b/.claude/r2/push_subset.py new file mode 100644 index 0000000..3e49f7c --- /dev/null +++ b/.claude/r2/push_subset.py @@ -0,0 +1,27 @@ +# -*- coding: utf-8 -*- +"""Push selected references from the current base-board placement plan.""" +import json +import sys + +import place_base as P + + +if __name__ == '__main__': + refs = sys.argv[1:] + pos = P.plan()[0] + missing = [ref for ref in refs if ref not in pos] + if missing: + raise SystemExit('unknown references: ' + ' '.join(missing)) + selected = {ref: pos[ref] for ref in refs} + P.push(selected) + got = P.call("const want=%s,o={}; for(const c of await eda.pcb_PrimitiveComponent.getAll())" + " if(want.includes(c.designator)) o[c.designator]=[c.x/%s,c.y/%s,c.rotation||0];" + " return o;" % (json.dumps(refs), P.MIL, P.MIL)) + bad = [] + for ref, (x, y, rot) in selected.items(): + if ref not in got or abs(got[ref][0] - x) > 0.02 or abs(got[ref][1] - y) > 0.02 \ + or int(round(got[ref][2])) % 360 != rot % 360: + bad.append(ref) + if bad: + raise SystemExit('readback mismatch: ' + ' '.join(bad)) + print('readback OK: ' + ' '.join(refs)) diff --git a/.claude/r2/r2-uuids.json b/.claude/r2/r2-uuids.json new file mode 100644 index 0000000..c0157ff --- /dev/null +++ b/.claude/r2/r2-uuids.json @@ -0,0 +1,92 @@ +{ + "_readme": "PhoneRail-R2（刀片式）工程的 UUID 缓存。方案见 D:/DCDC/刀片式方案规划-R2.md。R1 的工程（五路手机直供电源板 / 1e5745f4caff4b15a921694d2fd912e4）保留不动。", + "_created": "2026-09-08 (M1)", + "project": { + "uuid": "05a65c22f14846b8b95360ef8d3c1e2e", + "friendlyName": "PhoneRail-R2", + "teamUuid": "543725e8f0454017a5691e7e570aeef6" + }, + "r1_project": { + "uuid": "1e5745f4caff4b15a921694d2fd912e4", + "friendlyName": "五路手机直供电源板", + "note": "只读参照，不许改" + }, + "boards": { + "BLADE": { + "_desc": "刀片（每台手机一片，5 片相同）98x76 4层（硬上限 98x98）。⚠ 2026-09-08 起 5 页：B3 拆成 B3-PHONE / B3B-USB", + "schematic": { + "uuid": "ec5f3ca5108b618d", + "name": "r2-blade" + }, + "pcb": { + "uuid": "3b9c4e39c8d164db", + "name": "BLADE-PCB", + "note": "M4 开工。板边 = 封装的 y=0，手指朝 +Y（板内）。" + }, + "pages": { + "B1-POWER": "5338949298dcff35", + "B2-CTRL": "4f458d678c50f7a4", + "B3-PHONE": "cf32a688430fc2d1", + "B4-EDGE": "c8f10dbd1286853b", + "B3B-USB": "4ce5bfe35e90e560" + } + }, + "BASE": { + "_desc": "底板（背板）110x125 2层。⚠ 2026-09-08 起 7 页：A5 拆成 A5-SLOTS(槽1~3) / A5B-SLOTS(槽4~5 + 5 个 D± 退路座)", + "schematic": { + "uuid": "372e2399adb7a6db", + "name": "r2-base" + }, + "pcb": { + "uuid": "7b9524b6aaf6f235", + "name": "BASE-PCB" + }, + "pages": { + "A1-INPUT": "9d86e72abb1a6571", + "A2-AUX": "3361444ab04474c5", + "A3-CTRL": "38327f806bc13133", + "A4-HUB": "09d583ff95cd35d9", + "A5-SLOTS": "2c73c5bf77f34053", + "A6-FAN": "68c9ffaa578572d3", + "A5B-SLOTS": "e493f8bce3a51aae" + } + } + }, + "page_contents": { + "B1-POWER": "✅ 已画完（2026-09-08）。12V入口 F1 2A慢断保险(F1206SB2000V063TM / C310998) + D1 TVS -> U1 TPS54622 -> L1 -> Cout -> R1/R2/R7 分压注入 + R8/C12 DAC低通 -> U2 TPS25940A eFuse -> Rs1 5mR + U3 INA226 -> VO_P；Q1 反相 + Q2 放电 + R19 10R 互锁。版图搬自 R1 的 P2-CHANNEL。42 件 / 218 导线段 / 31 旗 / 13 端口；verify_sch 六项全过、port_audit 可疑 0。 ✅ **T7 已结（2026-09-08）**：F1 从同封装的 10A 占位件 C310989 换成 **F1206SB2000V063TM（C310998）** —— AEM SB 系列 = Slow Blow，1206/63V/分断 50A/熔断 I²t 0.63。根因是「lib_Device.search 只回 38 条」这句经验错了：它能翻页（itemsOfPage/page）。⚠ 刀片满载 1.45A = 额定的 73%，压在「连续 ≤75%」的降额线上；无故熔断就换 F1206SB2500V032TM（C310999），同封装、改一个常量。", + "B2-CTRL": "✅ 已画完（2026-09-08）。U4 PCA9555(0x20) + 侧键 MOS ×3(Q3~Q5 + 1k/100k) + 本槽 I²C 4.7k 上拉(R40/R41) + C40 去耦。13 件 / 55 段 / 13 旗 / 20 端口，六项全过、port_audit 可疑 0。⚠ D11b：DAC63204 已挪到底板（2 颗喂 5 路），本页不再有 DAC，位号顺移 PCA9555 U5→U4。", + "B3-PHONE": "✅ 已画完（2026-09-08）。J5 电池排线 4 焊盘(P+/P−/TEMP/ID) + R60 10k/R61 68k + C60~C65 阻尼组(2200µF+100µF×2+22µF×2+100nF) 挂 VO_P + K1~K3 侧键中框焊盘(KPAD_*) + K4 公共地 + EDL(J3 A1251-2P + U6 TS5A3157 + R63 100k 下拉 + C69)。17 件，六项全过、port_audit 可疑 0。⚠ C60 是电解，rot 语义与 R1 相反，脚本里按脚号断言。", + "B4-EDGE": "✅ 已画完（2026-09-08，M2 收口）。J1 = PCIE-X4-EDGE-64P（个人库自建，符号借 Samtec PCIE-064-02-F-D-TH 的 64 脚，脚号就是 A1~A32/B1~B32）+ J2 = A1251WV-S-4P D± 退路座。64 针 = 19 有名信号 + 39 地 + 6 悬空。2 件 / 85 段 / 7 旗 / 15 端口，六项全过、可疑 0、交叉 0。⚠ T4 揪出方案文档 §5.2 两处记忆错：B3 是 +12V 不是 RSVD（误插真 PC 会把 12V 灌进 +5V 轨），B12 是 CLKREQ# 不是 RSVD ⇒ +5V 改挂 A19/A32（每版 CEM 都是 RSVD）。VDAC 定在 A16（上下 A15/A17 都是地）。PRSNT# 用 A1↔B31（x4 全长在位），它在刀片上没有对端，已进 xpage 的 NAMING_ONLY。✅ 金手指封装已建（2026-09-08，M4a）：EDGE-64P-P1.00_PCIE-X4-GF，见 footprints 段。", + "A1-INPUT": "✅ 已画完（2026-09-08，M3a）。搬 R1 的 P1-INPUT（9a6096762e036e23），删掉 3V3 Buck 那 8 件。J1 DC-005 + F1 12A(C310990) + Q1 AO4407 反接 + DZ1/R1/C1 栅极 RC 缓启动 + D1 SMBJ13A TVS + C2/C3 470µF + C4/C5 10µF + C6 100nF 储能 + Rs6 5mΩ + U13 INA226(0x43, 挂 I2C 主干不经 mux) + U29 TL431 泄放(R4/R5/R6/Q3/R9A~E 5×2Ω=10Ω/10W) + C11。25 件 / 101 段 / 18 旗 / 10 端口，六项全过、可疑 0、交叉 0。⚠ 入口链三个节点已起名 VIN_RAW / VIN_FUSED / VIN_SW（R1 上是无名网，PCB 侧只能按 $1N… 认；这一段过 9A 要铺铜 + 断面校核）。SDA/SCL/INA_ALERT 的对端在还没画的 A3-CTRL。", + "A2-AUX": "✅ 已画完（2026-09-08，M3b）。两块都从 R1 整块搬来：3V3 块（U19/C7/C8/C9/C10/L2/R2/R3，来自 P1-INPUT，上移 230）+ 5V 块（U30/C731~C735/L3/R706/R707，来自 P1B-5V 整页，下移 110）。17 件 / 56 段 / 15 旗 / 8 端口，六项全过、可疑 0。⚠ 端口 BST 改名 BST3V3（两个 Buck 同页，不加后缀早晚被隔壁那颗的自举节点撞上）。⚠ 修了两处叠字：C733「100nF」压 U30 位号（渲染成 100uF0）、C7「2.2uF」被 BST3V3 标签划穿。保留 5V 块里两处从 R1 带来的交叉（放大确认无节点圆点，不会误读；消不掉，见方案 §19.3）。U31 AMS1117-3.3 不在本页，在 A4-HUB。", + "A3-CTRL": "U20 ESP32-S3-WROOM-1 + J33 5P 应急口(GND/TXD0/RXD0/EN/IO0) + U35 TCA9548A + I2C 上拉；J22 已删(D13)。⚠ D11b 新增：U6/U7 两颗 DAC63204(0x4A/0x4B) 喂 5 路 VDAC，挂主干总线不经 mux；INT# 的 10k 上拉一颗（五槽 wire-OR）。", + "A4-HUB": "✅ 已画完（2026-09-08，M3d）。R1 载板 C2-HUB 整页原样搬（OFF=(0,0)）+ 三处改动：① 新增 U31 AMS1117-3.3 + C752 10µF + C753 100nF + C737 22µF 固态钽 → +3V3_HUB（与 +3V3 是两条轨，只共地）；② 启用第 6 个下行口 USB6_DP/DM → A3 的 ESP32 原生 USB（D13）；③ HUB_RST 保留 R716 10k 上拉到 +3V3_HUB（保命，见方案 §8.2）。31 件 / 123 段 / 16 旗 / 61 端口，六项全过、交叉 0。✅ **T6 已结**：DS00001598C p.20 Table 7-1 的 0Ah/0Bh 端口禁用默认 00h ⇒ CFG_SEL=110 下七个口全开，第 6 口**不用改 strap，只要连线**（方案 §8.2 表第 6 条的问法反了）。口 7 全开但悬空是故意的（§21.6b）。⚠ 三处只有人眼截图才看得出来的排版问题已修：(a) VBUS_UP 分压 R721/R722 + UP_VBUS_DET 端口从 R1 带过来正好**落进 A4 标题栏**（x>455 且 y<192），整块平移 +380；(b) C737 钽电容的 rot 语义与假设相反 —— 实测 rot0 才是 1 脚(正)朝上、跨距 ±20 不是 ±15；(c) U31 说明文字被 R1 带来的地旗 (60,270) 压穿，挪到 x=100 / y246~300 并降到字号 9（全页扫过，字号 10 的四行放不下）。", + "A5-SLOTS": "✅ 已画完（2026-09-08，M3e）。J34~J36 = 槽 1~3，PCIE-064-02-F-D-TH（与刀片 J1 同一个符号）。针位直接 `from b4_edge import PIN_NET`，不抄第二份，逐脚加槽号后缀。3 件 / 195 段 / 24 旗 / 30 端口，六项全过、交叉 0。⚠ **唯一一处故意不镜像刀片：PRSNT#**。底板是主板侧 ⇒ A1 = GND、B31 = PRSNT{n}#（上拉与读取都在 A3）；刀片上 A1↔B31 才是那段短接线，插上才把 B31 拉到地。若底板也并成一个网，回路里一个对地通路都没有 ⇒ **插不插都读「未插入」，而 DRC/ERC/几何验证/跨页对账四道全过**。✅ T8 已结（2026-09-08）：换成 SOFNG PCIE-64P11L（C19188869），PC 标准 x4 64PIN。⚠ 它的**脚号是 1~64**（脚名才是 A1~B32）+ 多一根 65 屏蔽脚（接到 A1 的地短线上），引脚相对坐标与刀片金手指完全一致 ⇒ 版图没动，只加了 slot_pin() 换算层。⛔ 贴片立式，保持力只靠焊盘剪切 —— M4 必须给刀片另加固定件。", + "A6-FAN": "✅ 已画完（2026-09-08，M3f）。风扇块 24 件从 R1 P6-FAN-EDL 原样搬（拓扑一字不改，版图重排）+ NTC 块 6 件从 R1 P3-CONTROL 搬来（上臂改号 R618/R619 → R660/R661，滤波 C613/C614 → C736/C739）。30 件 / 73 段 / 26 旗 / 11 端口，六项全过、交叉 0。⚠ Q7/Q9/Q10 在 R1 上是 mirror=True 放的，而 schcheck.place() 不支持镜像 ⇒ 改用 rot180，代价是 Q9/Q10 变成**地旗在上、+3V3 上拉旗在下**（全页唯一一处违反「电源在上、地在下」，电气一致）。靠 topo_check() 兜底：把 R1 dump 和本页各自按几何反推网表、逐个「位号.脚号」比对分组，不看坐标也不看网名。⚠ RT601 的型号文字「NCP18XH103F03RB」约 65 单位宽，原来 60 的间距正好压住 C736 的值（同 A2-AUX 的 100uF0），C736/C739 已右移到 +100。⚠ 首板只装一只风扇时，空着那一路 TACH 恒低或恒高、**都是 0 脉冲** ⇒ 固件必须按配置屏蔽，否则一直报「风扇停转」。", + "B3B-USB": "✅ 已画完（2026-09-08，新增页）。J4 BM24-50DS 尾插座（脚号→网络照抄 R1 的 J71，脚本每次和 C5-J1401A 逐脚对账）+ U7 USBLC6 D± ESD + R64 56k Rp(CC1→VBUS) + R65 100k 口温 + U5 TPS22918 + C66/C67/C68 + R62 100k ON 下拉。9 件，六项全过。⚠ TPS22918 的 rot270 语义与 R1 C3-USB 相反（本页实测表在脚本里）。", + "A5B-SLOTS": "✅ 已画完（2026-09-08，M3e，**新开的第七页**）。J37/J38 = 槽 4~5 + J39~J43 = 5 个 D± 退路座（D12，逐槽镜像刀片 J2）。7 件 / 170 段 / 26 旗 / 35 端口，六项全过、交叉 0。画法全部 import 自 a5_slots，只给坐标和文字。⚠ 为什么拆页：每槽 64 针两排同高 pitch 10 ⇒ 引脚跨度 310，压到最紧每槽净宽仍要 355，5 槽 = 1815 ≫ 页面可用 1125；排两行则 820 > 802 且下面那行必然压进标题栏。⚠ 底部那行长注释原来从五个退路座的 GND 旗标签中间穿过去（同 A2-AUX 叠字），已拆成四行挪到右侧空白。" + }, + "cleanup_todo": [ + "PhoneRail-R2b (ab94ce71a50b48348f845017fb57d557) 是试参数时误建的空工程，API 无删除接口，请在工程树右键删除", + "M4 刀片 PCB：金手指到 J2（D± 退路座）之间要留一段带丝印的割断位（D12），否则两条路并联 = 长残桩。", + "下单时另外说明：金手指区**钢网不开口**（封装里的助焊扩展被客户端夹到 -0.035mm，关不死）。" + ], + "nets_B1": { + "_note": "B1-POWER 的跨页网络（对端在括号里）", + "+12V": "IN，来自 B4-EDGE 金手指", + "+12V_F": "刀片内部 12V 轨（F1 之后），本页电源旗", + "+3V3 / GND": "来自 B4-EDGE", + "VDAC": "IN，D11b 起来自 B4-EDGE 金手指（底板 DAC63204），不再来自 B2-CTRL", + "EFUSE_EN": "IN，来自 B4-EDGE（直连底板 ESP32 GPIO，不经 PCA9555）", + "EFUSE_FLT / EFUSE_PG / BUCK_PG / INA_ALERT": "OUT，去 B2-CTRL 的 PCA9555 输入", + "SDA / SCL": "BI，去 B4-EDGE", + "VO_P": "OUT，去 B3-PHONE（P+/P- 焊盘 + C801 阻尼组）" + }, + "footprints": { + "EDGE-64P-P1.00_PCIE-X4-GF": { + "uuid": "569096fb8fed4743b85c69f4b6581ead", + "libraryUuid": "543725e8f0454017a5691e7e570aeef6", + "note": "M4a 自建，脚本 .claude/r2/fp_edge.py（几何唯一事实来源）。64 指 / 1.0 pitch / 0.7 宽 / 长指 4.3 / 指尖离板边 1.3 / A1,B31 短指 3.2（PRSNT# 最后接触）。A 排=底层 B 排=顶层。缺口画在板框层(11)：4 段直线 + 12 段折线半圆，两个端点落在 y=0 的板边上 ⇒ 刀片外框底边必须在 x=-6.45 / -3.55 断开。已挂到器件 PCIE-X4-EDGE-64P，addIntoBom 已改 false。" + } + } +} \ No newline at end of file diff --git a/.claude/r2/remote_route.ps1 b/.claude/r2/remote_route.ps1 new file mode 100644 index 0000000..f4c8b69 --- /dev/null +++ b/.claude/r2/remote_route.ps1 @@ -0,0 +1,166 @@ +param( + [string]$Server = '10.5.5.13', + [int]$Passes = 1, + [switch]$PriorityCache, + [switch]$DpOnly, + # 服务器并行试算：每个元素是一组额外参数（如 '--repair --bot-pen-w 1'）， + # 各自在独立副本里跑，取未完成最少的那个走下面同一套校验 / 接受逻辑。 + [string[]]$Variants = @(), + [int]$PollSec = 60, + # 摆位 / 布线模型改过之后，旧缓存的未完成数没有可比性：用这个开关无条件接受新结果 + [switch]$AcceptAny, + # 服务器上跑布线的解释器；PyPy 见 PROGRESS（纯 Python 的 A*，JIT 通常快数倍） + [string]$Interp = 'python3' +) + +$ErrorActionPreference = 'Stop' +$Here = Split-Path -Parent $MyInvocation.MyCommand.Path +$Repo = Resolve-Path (Join-Path $Here '..\..') +$Python = 'C:\Python314\python.exe' +$Ssh = 'C:\Windows\System32\OpenSSH\ssh.exe' +$Scp = 'C:\Windows\System32\OpenSSH\scp.exe' +# 临时文件带 PID：允许同时起两批（快的单轮变体 + 慢的拆线重布），互不覆盖 +$Archive = Join-Path ([System.IO.Path]::GetTempPath()) "dcdc-remote-route-$PID.tgz" +$RunScript = Join-Path ([System.IO.Path]::GetTempPath()) "dcdc-remote-run-$PID.sh" +$RemoteArchive = Split-Path -Leaf $Archive +$Incoming = Join-Path $Here "_base_routes.server.$PID.json" +$Cache = Join-Path $Here '_base_routes.json' +$Backup = Join-Path $Here '_base_routes.pre-server.json' +$Rejected = Join-Path $Here '_base_routes.rejected.json' +$remoteRoot = $null + +if ($Passes -lt 1) { + throw 'Passes must be at least 1.' +} +if ($DpOnly -and $Variants.Count -gt 0) { + throw '-DpOnly cannot be combined with -Variants.' +} + +Push-Location $Repo +try { + & $Python '.claude\r2\route_base.py' --snapshot-vias + if ($LASTEXITCODE -ne 0) { throw 'Failed to refresh board-via snapshot.' } + + $remoteRoot = (& $Ssh $Server 'mktemp -d /tmp/dcdc-route.XXXXXX').Trim() + if ($LASTEXITCODE -ne 0 -or $remoteRoot -notmatch '^/tmp/dcdc-route\.[A-Za-z0-9]+$') { + throw "Unexpected remote work directory: $remoteRoot" + } + + & tar.exe --exclude=*.png --exclude=*.bak --exclude=__pycache__ ` + --exclude=_remote_route.tgz -czf $Archive ` + '.claude\r2' '.claude\eda.py' '.claude\pcb_pour.py' '.claude\eda-parts.json' + if ($LASTEXITCODE -ne 0) { throw 'Failed to build routing bundle.' } + + & $Scp $Archive "${Server}:${remoteRoot}/" + if ($LASTEXITCODE -ne 0) { throw 'Failed to upload routing bundle.' } + & $Ssh $Server "tar -xzf ${remoteRoot}/${RemoteArchive} -C ${remoteRoot}" + if ($LASTEXITCODE -ne 0) { throw 'Failed to extract routing bundle.' } + + $priority = if ($PriorityCache) { ' --priority-cache' } else { '' } + $scope = if ($DpOnly) { ' --dp-only' } else { '' } + $timeFmt = "/usr/bin/time -f 'REMOTE_TIME=%e sec CPU=%P RSS=%M KB'" + $remoteResult = "${remoteRoot}/.claude/r2/_base_routes.json" + + if ($Variants.Count -eq 0) { + $command = "DCDC_ROUTE_SERVER=1 $timeFmt $Interp " + + "${remoteRoot}/.claude/r2/route_base.py --offline --replan --passes $Passes$priority$scope" + & $Ssh $Server $command + if ($LASTEXITCODE -ne 0) { throw 'Remote routing failed.' } + } + else { + # 变体各自一份副本（缓存文件同名，不能共用目录），脱离 ssh 会话在后台跑： + # 拆线重布可能要跑很久，ssh 断线不能把计算带走。 + $lines = @('#!/bin/bash', "cd ${remoteRoot}") + for ($k = 0; $k -lt $Variants.Count; $k++) { + $v = $Variants[$k] + $lines += "mkdir -p v$k && cp -r .claude v$k/" + $lines += "( DCDC_ROUTE_SERVER=1 $timeFmt $Interp ${remoteRoot}/v$k/.claude/r2/route_base.py " + + "--offline --replan --passes $Passes$priority $v > v$k.log 2>&1; echo `$? > v$k.rc ) &" + } + $lines += 'wait' + $lines += 'touch done' + [System.IO.File]::WriteAllText($RunScript, (($lines -join "`n") + "`n")) + & $Scp $RunScript "${Server}:${remoteRoot}/run.sh" + if ($LASTEXITCODE -ne 0) { throw 'Failed to upload run script.' } + & $Ssh $Server "setsid nohup bash ${remoteRoot}/run.sh > /dev/null 2>&1 < /dev/null &" + if ($LASTEXITCODE -ne 0) { throw 'Failed to start remote variants.' } + for ($k = 0; $k -lt $Variants.Count; $k++) { Write-Host "v${k}: $($Variants[$k])" } + + $start = Get-Date + $poll = 0 + while ($true) { + Start-Sleep -Seconds $PollSec + $poll++ + $state = (& $Ssh $Server "test -f ${remoteRoot}/done && echo DONE || echo RUN").Trim() + if ($state -eq 'DONE') { break } + if ($poll % 5 -eq 0) { + $mins = [int]((Get-Date) - $start).TotalMinutes + Write-Host "--- $mins min ---" + & $Ssh $Server "cd ${remoteRoot} && for f in v*.log; do echo `"`$f: `$(tail -n 1 `$f)`"; done" + } + } + + $summary = & $Ssh $Server ("cd ${remoteRoot} && for k in `$(seq 0 $($Variants.Count - 1)); do " + + "echo `"v`$k rc=`$(cat v`$k.rc) `$(python3 -c 'import json,sys; d=json.load(open(sys.argv[1])); " + + "print(len(d[\`"logs\`"]), len(d[\`"segs\`"]), len(d[\`"vias\`"]))' " + + "v`$k/.claude/r2/_base_routes.json 2>/dev/null || echo NA)`"; done") + $best = $null + foreach ($row in $summary) { + Write-Host $row + if ($row -match '^v(\d+) rc=0 (\d+) (\d+) (\d+)$') { + $cand = @{ K = [int]$Matches[1]; Logs = [int]$Matches[2]; Vias = [int]$Matches[4] } + if (-not $best -or $cand.Logs -lt $best.Logs -or + ($cand.Logs -eq $best.Logs -and $cand.Vias -lt $best.Vias)) { + $best = $cand + } + } + } + for ($k = 0; $k -lt $Variants.Count; $k++) { + Write-Host "===== v${k}: $($Variants[$k]) =====" + & $Ssh $Server "grep -E '拆线重布|第 [0-9]+ 轮|REMOTE_TIME|Traceback|Error' ${remoteRoot}/v$k.log | tail -n 25" + } + if (-not $best) { throw 'No remote variant finished successfully.' } + Write-Host "Best variant: v$($best.K) ($($Variants[$best.K])) with $($best.Logs) unfinished." + $remoteResult = "${remoteRoot}/v$($best.K)/.claude/r2/_base_routes.json" + } + + if ($DpOnly) { + Write-Host 'Server-side D+/- diagnostic completed; local route cache was not changed.' + } + else { + & $Scp "${Server}:${remoteResult}" $Incoming + if ($LASTEXITCODE -ne 0) { throw 'Failed to download routing result.' } + $result = Get-Content -LiteralPath $Incoming -Raw | ConvertFrom-Json + # schema 8 = 4 层版（D15）；7 是 2 层版，必须被拒 + if ($result.schema -ne 8 -or $result.layers -ne 4 -or $result.slot_rot -ne 0 -or + $result.usb_slot_ref.'1' -ne 'J34' -or $result.usb_slot_ref.'5' -ne 'J38') { + throw 'Downloaded routing cache failed topology validation.' + } + $current = if (Test-Path -LiteralPath $Cache) { + Get-Content -LiteralPath $Cache -Raw | ConvertFrom-Json + } else { $null } + if ($current -and -not $AcceptAny -and $result.logs.Count -gt $current.logs.Count) { + Move-Item -LiteralPath $Incoming -Destination $Rejected -Force + Write-Host "Rejected worse server result: $($result.logs.Count) unfinished > current $($current.logs.Count)." + } + else { + if ($current) { + Copy-Item -LiteralPath $Cache -Destination $Backup -Force + } + Move-Item -LiteralPath $Incoming -Destination $Cache -Force + Write-Host "Accepted server result: $($result.segs.Count) segments, $($result.vias.Count) vias, $($result.logs.Count) unfinished." + } + } +} +finally { + Pop-Location + foreach ($f in @($Archive, $RunScript)) { + if (Test-Path -LiteralPath $f) { Remove-Item -LiteralPath $f -Force } + } + if ($remoteRoot -and $remoteRoot -match '^/tmp/dcdc-route\.[A-Za-z0-9]+$') { + # ⛔ 模式里的 `(v[0-9]+/)?[.]claude` 是故意的：直接写目录串的话，执行这条命令的 + # 远程 shell 命令行里也含这个串，pkill 先把自己杀了（ssh 返回 255），后面的 rm + # 根本不执行。按路径匹配而不是按 `python3`，换成 pypy3 也杀得到。 + & $Ssh $Server "pkill -f '${remoteRoot}/(v[0-9]+/)?[.]claude/r2/route_base' ; rm -rf -- '${remoteRoot}'" + } +} diff --git a/.claude/r2/repair_route.py b/.claude/r2/repair_route.py new file mode 100644 index 0000000..530c528 --- /dev/null +++ b/.claude/r2/repair_route.py @@ -0,0 +1,45 @@ +# -*- coding: utf-8 -*- +u"""补线器：在**板上现有铜**之上只布没接完的那几个网（不动其它任何线）。 + + /c/Python314/python .claude/r2/repair_route.py # 只算 + /c/Python314/python .claude/r2/repair_route.py --push # 追加下发（只推新增的段/孔） + +现有铜从 `_m6_board_copper.json`（pcb 读回）来，按网名打进占用图 —— 同网可穿， +所以 A* 从没接上的焊盘出发，碰到本网已有的铜就算到了。 +""" +import io, json, os, sys, math +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)); sys.path.insert(0, HERE) +import router as RT +import pcb_rules as R + +NETS = [a for a in sys.argv[1:] if not a.startswith('--')] or \ + ['VDAC', '$1N147', '$1N156', 'EFUSE_PG', '$1N165', 'VO', '+3V3', 'VBUS', 'SDA'] +cp = json.load(io.open(os.path.join(HERE, '_m6_board_copper.json'), encoding='utf-8')) +segs = [tuple(s) for s in cp['segs']] +vias = [tuple(v) for v in cp['vias']] +pads = RT.load_pads() +auto = R.resolve_auto() +board_vias = [(v[0], v[1], v[2], RT.VIA_D) for v in vias if v[2] == 'GND'] +_fs, _fv, launch = RT.finger_escape() +bypad = {} +for p in pads: + if p[0] == 'J1' or not p[7] or p[7] in RT.SKIP: + continue + bypad.setdefault(p[7], []).append(p) +for net, pts in launch.items(): + for (lay, x, y) in pts: + bypad.setdefault(net, []).append(['J1', 'launch', x, y, 0.3, 0.3, lay, net, 'RECT']) +n0, v0 = len(segs), len(vias) +logs = RT.route_groups(bypad, pads, segs, vias, board_vias, auto, + priority=tuple(NETS), only=set(NETS)) +new_s, new_v = segs[n0:], vias[v0:] +print(u'新增 %d 段 / %d 孔' % (len(new_s), len(new_v))) +for m in logs: + print(u' [!] ' + m) +left = RT.check_connected(pads, segs, vias) +print(u'连通性复查：%s' % (u'全通' if not left else left)) +json.dump({'segs': new_s, 'vias': new_v}, io.open(os.path.join(HERE, '_m6_repair.json'), 'w', encoding='utf-8')) +if '--push' in sys.argv and new_s: + RT.push(new_s, new_v) diff --git a/.claude/r2/route_base.py b/.claude/r2/route_base.py new file mode 100644 index 0000000..010ede6 --- /dev/null +++ b/.claude/r2/route_base.py @@ -0,0 +1,1266 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 布线（M5，**4 层**，D15）。 + + # ⛔ 计算只在服务器上跑：.claude/r2/remote_route.ps1（它会带 DCDC_ROUTE_SERVER=1 --offline --replan） + /c/Python314/python .claude/r2/route_base.py # 读缓存 + 报告（本机可跑） + /c/Python314/python .claude/r2/route_base.py --push # 下发导线 + 过孔（本机） + /c/Python314/python .claude/r2/route_base.py --clear # 清掉全部布线（本机） + /c/Python314/python .claude/r2/route_base.py --snapshot-vias + +2 层版（底层过路费 / D± 构造 / 12V 干道 / 3V3 槽墙 / 车道）整份在 `archive_base2L/route_base.py`。 +**引擎仍是刀片那份 `router.py`**（0.25 网格 + 8 邻接 A*，L1/L4 两层可布、内层做平面），这里只换板级常量、加底板的障碍、写主流程。 + +## 叠层与分工（D15） + +| 层 | 内容 | 布线器怎么看 | +|---|---|---| +| L1 | 5 个插槽 + 西侧 `+12V` 大铜（`pcb_base.l1_12v_rects`）| 可布；12V 大铜**只挡导线**（过孔可以落进去，铺铜自己挖反焊盘）| +| L2/L3 | GND 平面 | 不布线；GND 焊盘各打一个过孔下来 | +| L4 | 其余 133 件 | 主力布线层 | + +## 主流程（`plan_all`） + +1. **Kelvin**：`U13.10→Rs6.1`、`U13.9→Rs6.2` 各一条 0.3 专线，最先布。就近扎进平面的话， + INA226 量到的是「分流电阻 + 一段铜箔」的压降，读数随铜温漂，而 DRC / 连通性全过。 +2. **9 A 上 L1**：`Rs6.2` 西侧一块 L4 `+12V` 铜（`V12_PATCH`）+ 15 个过孔，落进 L1 大铜。 +3. **D± 七对**：DP 先 A*；DM 再 A*，离 DP 远的格点全收过路费（`HUG_PEN`），于是贴着 DP 走。 + ⚠ 北去三对（USB1~3）**极性是反的**：U32 北沿 DM 在西、槽上 D+ 在西（x 47.5）。同层两根线 + 不交叉换不过来 —— 交给 A*，它会让 DM 打一个过孔绕过去。四层薄介质上 0.28 线不耦合时 + Zdiff ≈ 100 Ω，仍在 USB 2.0 的 90 Ω ±15% 里，所以局部松耦合可以接受。 +4. **平面网扇出**：每只 GND 贴片焊盘一个过孔（通孔焊盘本来就穿到内层，跳过）； + 两边都 ≥ `EP_MIN` 的 GND 焊盘（U32 散热盘 / 插槽外壳盘 / DAC 底盘 / 模组底盘）在焊盘里打孔阵； + 每只 L4 的 `+12V` 焊盘一个过孔，**必须落在 L1 12V 主块里**。 +5. 其余：直连 + `router.route_groups` 按线宽分档 A*；`--repair` 拆线重布。 +""" +import io +import json +import math +import os +import sys + +# `--hash-seed N`：固定字符串哈希（只对 CPython 有意义；PyPy 按插入序遍历，结果与种子无关）。 +if '--hash-seed' in sys.argv: + _seed = sys.argv[sys.argv.index('--hash-seed') + 1] + if os.environ.get('PYTHONHASHSEED') != _seed: + os.execve(sys.executable, [sys.executable] + sys.argv, + dict(os.environ, PYTHONHASHSEED=_seed)) + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +import pcb_base as B # noqa: E402 +import router as RT # noqa: E402 +import rules_base as RB # noqa: E402 + +# 用户明确要求所有布线运算都放到 10.5.5.13。快照、缓存报告和下发仍可在本机做， +# 但任何会启动 A* 的入口必须由 remote_route.ps1 在服务器上显式解锁。 +_COMPUTE_FLAGS = ('--replan', '--dp-only') +if any(flag in sys.argv for flag in _COMPUTE_FLAGS) and os.environ.get('DCDC_ROUTE_SERVER') != '1': + sys.exit(u'!! 布线运算禁止在本机执行；请使用 .claude/r2/remote_route.ps1（服务器 10.5.5.13）') + +# ── 把 router 的板级常量换成底板的 ──────────────────────────────────────── +# `--grid G`：布线网格（默认 0.25）。规则 0.15 / 0.15 的最小线距是 0.3，0.25 网格只能按 0.5 一道排， +# 通道容量浪费约四成（0.5 / 0.65 间距的芯片周围尤其吃亏）。0.125 每轮慢 4~8 倍，只配顺序布线。 +if '--grid' in sys.argv: + RT.G = float(sys.argv[sys.argv.index('--grid') + 1]) +RT.B = B +RT.PCB = B.PCB +RT.NX = int(round(B.BW / RT.G)) + 1 +RT.NY = int(round(B.BH / RT.G)) + 1 +RT.PADS = os.path.join(HERE, '_base_pads.json') +RT.FINGER_KEEP_Y = 0.0 # 底板没有金手指区 +RT.KELVIN = [] # Kelvin 在这里自己布（router 那份只在它自己的 plan_all 里用） +RT.KELVIN_PADS = set() +RT.CLR = 0.16 # 规则 0.15（四层，同刀片），留一点给网格吸附 +RT.W_DEFAULT = 0.15 +RT.EDGE_CLR = 0.4 +RT.LAYER_DIR = {} # 八方向同价（D± 全是南北向，L1 走廊全是东西向，偏好反而添乱） +# 靠平面成网：焊盘各自一个过孔，铜在几何上本来就是分开的（+12V → L1 大铜，+3V3 → L2 整层） +RT.ISLAND_NETS = ('+12V', '+3V3') +CACHE = os.path.join(HERE, '_base_routes.json') +CACHE_SCHEMA = 8 # v8：4 层（D15）。旧的 2 层缓存（v7）必须被拒 +BOARD_VIAS = os.path.join(HERE, '_base_board_vias.json') +PLACE_JSON = os.path.join(HERE, '_base_place.json') + +# ⛔ router 里有刀片专用的 `J1` 特判（那边 J1 是金手指：不封顶、不排序、**连通性检查直接跳过**）。 +# 底板的 J1 是 DC 座，照原样 VIN_RAW 的入口脚就永远不被检查 —— 断了也报「0 条没搞定」。 +# ⇒ 载入焊盘时改名，布线结果里不含位号，下发不受影响。 +J1_ALIAS = 'J1dc' + + +class _NoNotch(object): + u"""`build_grid` 要 `pcb_pour.notch_cut()`（刀片金手指防呆缺口）—— 底板没有。""" + + @staticmethod + def notch_cut(): + return (-10.0, -10.0, -9.0, -9.0) + + +RT.P = _NoNotch + + +def _rule_min(net, auto): + u"""线宽下限查底板自己的 `rules_base`（router 那份会去 import 刀片的 pcb_rules）。""" + cls = RB.NET_TRACK.get(net) + if net in DP_NETS: + return RB.DIFF['strokeWidthMin'] + if cls is None: + return 0.15 + return RB.TRACK_RULES[cls]['strokeWidthMin'] + + +RT.rule_min = _rule_min + +# ── 通孔焊盘（layer 12）────────────────────────────────────────────────── +# 刀片全贴片，router 一句 `if lay not in LAY: continue` 就把它们漏出占用图。拆成两条： +# L4 那条可布（器件在背面），L1 那条带后缀、只当障碍（同网的线仍可从上面过）。 +TH_SUFFIX = '#t' +TH_GROW = 0.6 # J1/J23 的孔是长槽，槽比焊盘大 +TH_KEYS = set() + + +def split_th(pads): + out = [] + for p in pads: + if p[6] == 12: + # ⛔ 用**改名之后**的位号（J1 → J1dc）。第一版记的是 J1，load_pads 随后改名， + # 于是 J1 的两只通孔地脚没被认成通孔，被当成贴片散热盘在孔里打了孔阵 + # （DRC「钻孔到钻孔」4 条，J1_2 / J1_3）。 + TH_KEYS.add((J1_ALIAS if p[0] == 'J1' else p[0], str(p[1]))) + a = list(p); a[6] = 2; a[4] += TH_GROW; a[5] += TH_GROW + b = list(p); b[6] = 1; b[1] = str(p[1]) + TH_SUFFIX + b[4] += TH_GROW; b[5] += TH_GROW + out += [a, b] + else: + out.append(list(p)) + return out + + +def load_pads(): + # ⚠ 丢掉零尺寸的「幽灵焊盘」：多边形焊盘拆条时的残留（J23 的 A1B12 / A4B9 各有两块 0.30×0.00）， + # 真焊盘另有一块。留着的话平面网扇出要给它们找落孔点、信号网要去接它们，全报失败。 + pads = [p for p in split_th(RT.load_pads()) if p[4] >= 0.05 and p[5] >= 0.05] + for p in pads: + if p[0] == 'J1': + p[0] = J1_ALIAS + return pads + + +def load_board_vias(): + u"""读取板端既有过孔；`--offline` 时使用本地快照供计算服务器复现。""" + if '--offline' in sys.argv: + if not os.path.exists(BOARD_VIAS): + raise RuntimeError(u'离线计算缺少 _base_board_vias.json；先在 EDA 可达机器运行一次预检') + return [tuple(v) for v in json.load(io.open(BOARD_VIAS, encoding='utf-8'))] + vias = RT.load_vias() + io.open(BOARD_VIAS, 'w', encoding='utf-8').write(json.dumps(vias, ensure_ascii=False, indent=2)) + return vias + + +# ── 线宽 ───────────────────────────────────────────────────────────────── +PAIRS = {name: (dp, dm) for name, dp, dm in RB.PAIRS} +DP_NETS = [] +for _name, _dp, _dm in RB.PAIRS: + DP_NETS += [_dp, _dm] +DIFF_W = RB.DIFF['strokeWidthDefault'] # 0.28（L4 参考 L3 / L1 参考 L2，~90 Ω） +RT.WIDTH = { + 'VIN_RAW': 2.0, 'VIN_FUSED': 2.0, 'VIN_SW': 2.0, # 9 A 由之后的铺铜 + 断面校核保证 + 'FAN_12V_SW': 0.8, + # +5V 只给每槽刀片上的负载开关（规则 PWR5V 下限 0.2）。0.6 的干线从槽针排里出不来 —— + # +3V3 改平面网那一轮，5 个槽的 10 只 5V 针全部没接上。 + '+5V': 0.4, '+3V3': 0.4, + '+3V3_HUB': 0.3, # 要从 U32 北沿夹在 D± 中间的 5/10/13 脚出来，粗了出不来 +} +for _n in DP_NETS: + RT.WIDTH[_n] = DIFF_W +RT.WIDTH_AUTO = {} +RT.NO_CAP = tuple(DP_NETS) + ('VIN_RAW', 'VIN_FUSED', 'VIN_SW', '+5V', '+3V3', '+3V3_HUB') +# ⭐ +3V3 是平面网（2026-09-10 用户拍板：L2 整层 +3V3、L3 整层地，D15）。十轮布线信号网卡在 37~38， +# 大头是这棵 47 只脚、跨全板的电源树；改成每脚一孔扎进 L2，不再布线。 +PLANE_NETS = ('GND', '+12V', '+3V3') +LATE_PLANE_NETS = ('GND', '+3V3') # 布完信号之后才打孔的平面网（早打会封死 1 mm 针排里的信号脚） + +# ── Kelvin 取样 ────────────────────────────────────────────────────────── +KELVIN = [(('U13', '10'), ('Rs6', '1'), 0.3), # IN+ ← 分流电阻上游 + (('U13', '9'), ('Rs6', '2'), 0.3)] # IN− ← 分流电阻下游 +KELVIN_W = 0.3 + +# ── 9 A 上 L1：Rs6.2 西侧那块 L4 铜 + 过孔阵 ──────────────────────────────── +# 北边是泄放链（R9A/R9B 焊盘下沿 48.29），东边是 C4 / U13，只有西侧 x 5.3~10.8 空着。 +# 铜块东端盖住 Rs6.2 焊盘（同网），过孔 5 × 3 = 15 个（0.3 孔 1 oz 每个 ~1 A 保守）。 +V12_PATCH = (5.3, 44.4, 14.3, 48.05) +V12_VIA_X = (5.9, 7.0, 8.1, 9.2, 10.25) +V12_VIA_Y = (45.0, 46.1, 47.2) + + +def v12_vias(): + return [(x, y) for x in V12_VIA_X for y in V12_VIA_Y] + + +# ── 入口链那一条（L4）：别的网收过路费，之后 9 A 的铜面要从这里铺 ───────────── +CHAIN_STRIP = (7.5, 0.5, 18.5, 48.0) +CHAIN_PEN = 4 +CHAIN_NETS = ('VIN_RAW', 'VIN_FUSED', 'VIN_SW') + +# ── D± 贴合 ────────────────────────────────────────────────────────────── +HUG_BAND = 0.9 # DP 铜外 0.9 mm 以内不收费（DM 中心距 0.5 就落在里面） +HUG_PAD = 1.5 # DM 自己的脚周围也不收费，好起步 / 收尾 +HUG_PEN = 12 +DP_PAD_PEN = 3 # 布 D± 时的焊盘过路费（默认 10 会让它们绕着满板焊盘蜿蜒） +# ⛔ 北去三对（USB1~3）必须**先**布。第一版先布 USB5/USB4（最长），A* 从 U32 北沿横着往西抄近路， +# 把 USB1~3 的出口整排封死（服务器首轮：三对全「没布通」）。先布北去的，它们的竖线就是一道墙， +# 南去的两对只能往东绕 —— 那正是摆位时给它们留的 DP_H 车道。 +# ⚠ USB1 必须在 USB2 前面：两对都要往西绕开 USB3 的 U 形，USB2 先布就横着压过 USB1 的出口 +# （第三轮：USB1 两只脚都「出不来」）。最西的先走、走得最远。 +PAIR_ORDER = ['USB6', 'USBUP'] # USB1~5 全部按构造画（usb3_uturn / dp_construct）；这两对从 L1 的孔起步 + +# 最后一段才布的电源网（它们的脚在前两段一直收过路费）。 +# ⛔ 第二轮是按线宽分档、宽的先布：+3V3 / +5V 的干线沿走廊边一铺，正好横在 U35 两排脚、 +# U20 西排、风扇那一窝的出口上，于是几十条信号「没布通」。 +# +3V3 已是平面网（L2）；+5V 挪进信号那一段一起布（最后布时通道早被占完，10 只槽针全落空） +POWER_LATE = ('+3V3_HUB', 'FAN_12V_SW') + +# ── 平面网扇出 ──────────────────────────────────────────────────────────── +EP_MIN = 1.2 # GND 焊盘两边都 ≥ 这个 ⇒ 焊盘里打孔（散热盘 / 外壳盘） +EP_PITCH = 1.2 +EP_EDGE = 0.45 # 孔心离焊盘边 +V12_LAND = 0.6 # +12V 过孔离 L1 主块边 + + +def place_pos(): + d = json.load(io.open(PLACE_JSON, encoding='utf-8')) + return {k: (v[0], v[1], v[2]) for k, v in d.items()} + + +def keep_rects(): + u"""两层都不许有铜：天线净空 + 板框缺口（外扩板边净距）。""" + import place_base as PL + ant = PL.antenna_keepout(PL.sizes(), place_pos()) + n = B.notch_rect() + e = RT.EDGE_CLR + return [ant, (n[0] - e, n[1] - e, n[2] + 1.0, n[3] + e)] + + +_KEEP = [None] +_orig_build = RT.build_grid +_orig_pen = RT.pen_pads + + +def _build(pads, halfw, vias=()): + g = _orig_build(pads, halfw, vias) + _no_via_in_pad(g, pads) + extra = max(0.0, RT.VIA_D / 2.0 + RT.CLR - halfw) + for r in B.l1_12v_rects(): # 只打导线图：过孔可以落进大铜 + g.block_rect(1, r[0] - halfw, r[1] - halfw, r[2] + halfw, r[3] + halfw, net='+12V') + x0, y0, x1, y1 = V12_PATCH + g.block_both(2, x0 - halfw, y0 - halfw, x1 + halfw, y1 + halfw, extra, net='+12V') + if _KEEP[0] is None: + _KEEP[0] = keep_rects() + for r in _KEEP[0]: + for l in RT.LAY: + g.block_both(l, r[0] - halfw, r[1] - halfw, r[2] + halfw, r[3] + halfw, extra, net='#edge') + return g + + +# 还没打孔的 GND 贴片焊盘 + 后面阶段才布的网的焊盘：一律收过路费，给它们自己留出口。 +GND_PEN_PADS = [] +LATER_PEN_PADS = [] + + +def _pen(g, pads, halfw): + _orig_pen(g, list(pads) + GND_PEN_PADS + LATER_PEN_PADS, halfw) + g.penalize(2, CHAIN_STRIP[0], CHAIN_STRIP[1], CHAIN_STRIP[2], CHAIN_STRIP[3], CHAIN_PEN) + + +# ⛔ **贴片焊盘里不许落过孔**（散热 / 外壳盘除外，它们的孔阵是 plane_vias 专门打的）。 +# router 按「网」标归属，同网的过孔可以落进自己的焊盘 —— 插槽是手焊的，孔在焊盘里会吸锡； +# 0402 的盘上打孔也一样。第二轮已见 A* 把 D± 的孔打在槽针焊盘边上。 +def _no_via_in_pad(g, pads): + k = g.nid('#pad') + r = RT.VIA_D / 2.0 + for p in pads: + if p[6] not in RT.LAY or is_ep(p) or str(p[1]).endswith(TH_SUFFIX) or (p[0], str(p[1])) in TH_KEYS: + continue + # 只打焊盘所在那一层就够：过孔是通孔，free_via 两层都查 + g._mark(g.ownv, p[6], p[2] - p[4] / 2 - r, p[3] - p[5] / 2 - r, + p[2] + p[4] / 2 + r, p[3] + p[5] / 2 + r, k, True) + + +RT.build_grid = _build +RT.pen_pads = _pen + +# ── 12V 大铜底下三个区（L1 被 12V 占着，只能走 L4）：没有焊盘在这里的网，路过要加价 ───────── +# 第九轮：Buck 反馈分压（$2N72 / $2N70）、U13 的 I²C、风扇几个本地网「没布通」—— 它们一两毫米的路 +# 被跨半块板的 +3V3 / 风扇信号 / I²C 总线从这里穿过去占了。 +UNDER_12V_ZONES = ('A1', 'A2', 'A6') +UNDER_12V_PEN = 6 +_orig_route_net = RT.route_net + + +def _route_net(g, net, pads_of_net, *a, **k): + for z in UNDER_12V_ZONES: + r = B.ZONES[z] + if not any(r[0] <= q[2] <= r[2] and r[1] <= q[3] <= r[3] for q in pads_of_net): + g.penalize(2, r[0], r[1], r[2], r[3], UNDER_12V_PEN) + return _orig_route_net(g, net, pads_of_net, *a, **k) + + +if '--zone-pen' in sys.argv: + RT.route_net = _route_net + + +# ── 小工具 ─────────────────────────────────────────────────────────────── +def grid_now(pads, halfw, segs, vias, board_vias): + u"""按 halfw 建占用图并打进已布的铜；再建一张「引出脚口径」的图 gt。和 route_groups 同一套判据。""" + g = RT.build_grid(pads, halfw, board_vias) + for (l, a, b, c, d, ww, nn) in segs: + RT.block_track(g, l, a, b, c, d, halfw + ww / 2.0, nn, + extra=max(0.0, RT.VIA_D / 2.0 + RT.CLR - (halfw + ww / 2.0))) + for (vx, vy, nn) in vias: + rv = RT.VIA_D / 2.0 + RT.CLR + halfw + for l in RT.LAY: + g.block_rect(l, vx - rv, vy - rv, vx + rv, vy + rv, net=nn) + gt = RT.Grid() + sh = RT.W_DEFAULT / 2.0 + for (l, a, b, c, d, ww, nn) in segs: + RT.block_track(gt, l, a, b, c, d, RT.CLR + sh + ww / 2.0, nn) + for (vx, vy, nn) in vias: + r = RT.VIA_D / 2.0 + RT.CLR + sh + for l in RT.LAY: + gt.block_rect(l, vx - r, vy - r, vx + r, vy + r, net=nn) + others = {1: [RT.pad_rect(p) for p in pads if p[6] == 1], + 2: [RT.pad_rect(p) for p in pads if p[6] == 2]} + return g, gt, others + + +def route_one(net, ps, w, pads, segs, vias, board_vias, logs, pen_pads=(), hug=None, fence=()): + halfw = w / 2.0 + RT.CLR + g, gt, others = grid_now(pads, halfw, segs, vias, board_vias) + for (l, r) in fence: # 只对这一个网的禁区（导线图，按层） + g.block_rect(l, r[0], r[1], r[2], r[3], net='#fence') + RT.pen_pads(g, list(pen_pads), halfw) + if hug: + apply_hug(g, hug) + s, v, st = RT.route_net(g, net, ps, halfw, w, others, logs, gt) + out = list(s) + for (q, node, ww) in st: + out += RT.stub_emit(q, RT.wx(node[1]), RT.wy(node[2]), + [] if RT._is_launch(q) else others.get(q[6], []), ww / 2.0, ww, net, gt) + return out, list(v) + + +def apply_hug(g, band): + u"""band = {层: [矩形]}：矩形外的格点一律至少收 HUG_PEN。**在 pen_pads 之后调**（它会先清零）。""" + n = RT.NX * RT.NY + for l in RT.LAY: + field = bytearray([HUG_PEN]) * n + for (x0, y0, x1, y1) in band.get(l, []): + i0, i1 = max(0, int(x0 / RT.G)), min(RT.NX - 1, int(math.ceil(x1 / RT.G))) + j0, j1 = max(0, int(y0 / RT.G)), min(RT.NY - 1, int(math.ceil(y1 / RT.G))) + z = bytes(i1 - i0 + 1) + for j in range(j0, j1 + 1): + field[j * RT.NX + i0: j * RT.NX + i1 + 1] = z + g.pen[l] = bytearray(map(max, g.pen[l], field)) + + +def _seg_box(s, m): + return (min(s[1], s[3]) - m, min(s[2], s[4]) - m, max(s[1], s[3]) + m, max(s[2], s[4]) + m) + + +# ── 各阶段 ─────────────────────────────────────────────────────────────── +def kelvin(pads, segs, vias, board_vias, logs): + padmap = {(q[0], str(q[1])): q for q in pads} + out_s, out_v = [], [] + for aa, bb, w in KELVIN: + pa, pb = padmap.get(aa), padmap.get(bb) + if not pa or not pb: + logs.append(u'Kelvin: 找不到 %s.%s / %s.%s' % (aa + bb)) + continue + halfk = w / 2.0 + RT.CLR + g, gt, others = grid_now(pads, halfk, segs + out_s, vias + out_v, board_vias) + na = RT.pad_nodes(g, pa, halfk, others.get(pa[6], []), w / 2.0, gt) + nb = RT.pad_nodes(g, pb, halfk, others.get(pb[6], []), w / 2.0, gt) + path = RT.astar(g, na[:16], nb[:16], pa[7], halfk) + if not path: + logs.append(u'Kelvin: %s.%s → %s.%s 没布通' % (aa + bb)) + continue + sg, vv = RT.to_segments(path) + out_s += [(l, x0, y0, x1, y1, w, pa[7]) for (l, x0, y0, x1, y1) in sg] + out_v += [(x, y, pa[7]) for (x, y) in vv] + out_s += RT.stub_emit(pa, RT.wx(path[0][1]), RT.wy(path[0][2]), others.get(pa[6], []), + w / 2.0, w, pa[7], gt) + out_s += RT.stub_emit(pb, RT.wx(path[-1][1]), RT.wy(path[-1][2]), others.get(pb[6], []), + w / 2.0, w, pb[7], gt) + return out_s, out_v + + +def v12_handoff(pads): + u"""Rs6.2 西侧 L4 铜块 + 15 个过孔。铜块本身画成若干条同网宽线（铺铜阶段再用正式铜面覆盖）。""" + bad = [] + x0, y0, x1, y1 = V12_PATCH + for p in pads: + if p[6] not in (2, 12) or p[7] == '+12V': + continue + r = RT.pad_rect(p) + d = max(r[0] - x1, x0 - r[2], r[1] - y1, y0 - r[3]) + if d < RB.MIN_CLEARANCE + 0.05: + bad.append(u'%s.%s(%s) 离 V12_PATCH 只有 %.2f' % (p[0], p[1], p[7], d)) + if bad: + raise RuntimeError(u'V12_PATCH 与异网焊盘冲突（摆位改过？）：' + u'；'.join(bad)) + segs = [] + h = y1 - y0 + segs.append((2, x0 + h / 2.0, (y0 + y1) / 2.0, x1 - h / 2.0, (y0 + y1) / 2.0, h, '+12V')) + vias = [(x, y, '+12V') for (x, y) in v12_vias()] + return segs, vias + + +# ── J23（Type-C）同名 D± 脚的桥 ───────────────────────────────────────────── +# 一排里是 B6(DP) A7(DM) A6(DP) B7(DM) 交错，0.5 mm 间距。先布的那根把自己两只脚一桥， +# 正好横在另一根内侧那只脚的出口上（首轮：UP_DM「A7 出不来」）。 +# ⇒ 两座桥按构造画：DP 从焊盘**南侧**（连接器本体一侧）绕、DM 从**北侧**绕，互不交叉； +# 之后 A* 只接外侧的 B6（DP，西北方向是空的）和 B7（DM，东北方向是空的）。 +J23_BRIDGE_W = 0.15 +J23_BRIDGE_OUT = 0.6 # 桥的横段离焊盘端多远 + + +def j23_bridges(pads): + pm = {(q[0], str(q[1])): q for q in pads if q[0] == 'J23'} + need = [('B6', 'UP_DP'), ('A6', 'UP_DP'), ('A7', 'UP_DM'), ('B7', 'UP_DM')] + for pin, net in need: + if ('J23', pin) not in pm or pm[('J23', pin)][7] != net: + raise RuntimeError(u'J23.%s 不是 %s（封装 / 朝向改过？）' % (pin, net)) + b6, a6, a7, b7 = (pm[('J23', k)] for k in ('B6', 'A6', 'A7', 'B7')) + if not (b6[2] < a7[2] < a6[2] < b7[2]): + raise RuntimeError(u'J23 的 D± 脚顺序不是 B6 A7 A6 B7（西 → 东）') + ys = b6[3] - b6[5] / 2.0 - J23_BRIDGE_OUT # 南 + yn = a7[3] + a7[5] / 2.0 + J23_BRIDGE_OUT # 北 + w = J23_BRIDGE_W + segs = [(2, b6[2], b6[3], b6[2], ys, w, 'UP_DP'), (2, b6[2], ys, a6[2], ys, w, 'UP_DP'), + (2, a6[2], ys, a6[2], a6[3], w, 'UP_DP'), + (2, a7[2], a7[3], a7[2], yn, w, 'UP_DM'), (2, a7[2], yn, b7[2], yn, w, 'UP_DM'), + (2, b7[2], yn, b7[2], b7[3], w, 'UP_DM')] + bad = [] + for s in segs: + for q in pads: + if q[6] != 2 or q[7] == s[6]: + continue + d = _seg_rect_gap(s, RT.pad_rect(q)) - w / 2.0 + if d < RB.MIN_CLEARANCE - 1e-6: + bad.append(u'%s 桥离 %s.%s(%s) 只有 %.3f' % (s[6], q[0], q[1], q[7] or 'NC', d)) + if bad: + raise RuntimeError(u'J23 桥净距不够：' + u'；'.join(sorted(set(bad)))) + return segs, {('J23', 'A6'), ('J23', 'A7')} + + +# ── USB3：U 形掉头（按构造画）─────────────────────────────────────────────── +# 北去三对的极性都是反的：U32 北沿西 → 东是 DM DP，槽上南排是 D+(x 47.5) D−(x 48.5)。 +# 同层两根线不交叉换不过来，但**掉头一次左右自然对调**。USB3 的目标 J36 就在 U32 正北 1 mm， +# 所以 U32 东移 2.5 mm（place_base.HUB_CX），让它的两只脚落在 J36 D± 的东边： +# L4：两根一起北上，从 J36 南排底下穿过（焊盘在 L1，L4 空着）→ 到两排中间向西 → 南下到过孔 +# L1：过孔 → 往南进焊盘的内端（从北边进，不占南排外侧的出口） +# DM 在内圈、DP 在外圈，DP 的过孔在 DM 过孔的西北，两根 L1 引出脚互不跨越。 +U3_DMV = 1.2 # DM 过孔离焊盘内端 +U3_DMH = 0.4 # DM 横段在自己过孔北边多少 +U3_DPH = 0.8 # DP 横段在 DM 横段北边多少（外圈） +U3_DPV = 0.5 # DP 过孔在自己横段南边多少 + + +def usb3_uturn(pads): + pm = {(q[0], str(q[1])): q for q in pads} + dm0, dp0 = pm[('U32', '6')], pm[('U32', '7')] + sdp, sdm = pm[('J36', '46')], pm[('J36', '47')] + for q, net in ((dm0, 'USB3_DM'), (dp0, 'USB3_DP'), (sdp, 'USB3_DP'), (sdm, 'USB3_DM')): + if q[7] != net: + raise RuntimeError(u'%s.%s 是 %s 不是 %s' % (q[0], q[1], q[7], net)) + if not (sdp[2] < sdm[2] < dm0[2] < dp0[2]): + raise RuntimeError(u'USB3 掉头的前提不成立：要 J36 D+ < D− < U32.6 < U32.7（西 → 东），' + u'实际 %.2f %.2f %.2f %.2f —— U32 的 x 改过？' % (sdp[2], sdm[2], dm0[2], dp0[2])) + w = DIFF_W + y_in = sdp[3] + sdp[5] / 2.0 + y_dmv = y_in + U3_DMV + y_dmh = y_dmv + U3_DMH + y_dph = y_dmh + U3_DPH + y_dpv = y_dph - U3_DPV + dm = [(dm0[2], dm0[3]), (dm0[2], y_dmh), (sdm[2], y_dmh), (sdm[2], y_dmv)] + dp = [(dp0[2], dp0[3]), (dp0[2], y_dph), (sdp[2], y_dph), (sdp[2], y_dpv)] + segs = [] + for net, pts in (('USB3_DM', dm), ('USB3_DP', dp)): + segs += [(2, a[0], a[1], b[0], b[1], w, net) for a, b in zip(pts, pts[1:])] + segs += [(1, sdm[2], y_dmv, sdm[2], sdm[3], w, 'USB3_DM'), + (1, sdp[2], y_dpv, sdp[2], sdp[3], w, 'USB3_DP')] + vias = [(sdm[2], y_dmv, 'USB3_DM'), (sdp[2], y_dpv, 'USB3_DP')] + bad = [] + c = RB.MIN_CLEARANCE + for s in segs: + for q in pads: + if q[6] not in (s[0], 12) or q[7] == s[6]: + continue + d = _seg_rect_gap(s, RT.pad_rect(q)) - w / 2.0 + if d < c - 1e-6: + bad.append(u'%s 离 %s.%s(%s) %.3f' % (s[6], q[0], q[1], q[7] or 'NC', d)) + for (vx, vy, net) in vias: + for q in pads: + if q[7] == net: + continue + d = _seg_rect_gap((0, vx, vy, vx, vy), RT.pad_rect(q)) - RT.VIA_D / 2.0 + if d < c - 1e-6: + bad.append(u'%s 的过孔离 %s.%s(%s) %.3f' % (net, q[0], q[1], q[7] or 'NC', d)) + a = [s for s in segs if s[6] == 'USB3_DP'] + b = [s for s in segs if s[6] == 'USB3_DM'] + for s in a: + for t in b: + if s[0] == t[0] and _seg_seg(s, t) - w < c - 1e-6: + bad.append(u'DP/DM 对内净距 %.3f' % (_seg_seg(s, t) - w)) + for (vx, vy, net) in vias: + for t in segs: + if t[6] != net and _seg_seg((0, vx, vy, vx, vy), t) - RT.VIA_D / 2.0 - w / 2.0 < c - 1e-6: + bad.append(u'%s 的过孔离 %s 的线太近' % (net, t[6])) + if bad: + raise RuntimeError(u'USB3 掉头几何不过：' + u'；'.join(sorted(set(bad)))) + return segs, vias, {('U32', '6'), ('U32', '7'), ('J36', '46'), ('J36', '47')} + + +def geom_check(tag, segs, vias, pads, prior_s=(), prior_v=()): + u"""按构造画的铜没有 A* 占用图兜底，净距必须自己查：焊盘（同层 / 通孔）、此前构造的铜、彼此之间。""" + c = RB.MIN_CLEARANCE + bad = [] + r = RT.VIA_D / 2.0 + for s in segs: + for q in pads: + if q[6] not in (s[0], 12) or q[7] == s[6]: + continue + d = _seg_rect_gap(s, RT.pad_rect(q)) - s[5] / 2.0 + if d < c - 1e-6: + bad.append(u'%s 线离 %s.%s(%s) %.3f' % (s[6], q[0], q[1], q[7] or 'NC', d)) + for (vx, vy, net) in vias: + for q in pads: + if q[7] == net: + continue + d = _seg_rect_gap((0, vx, vy, vx, vy), RT.pad_rect(q)) - r + if d < c - 1e-6: + bad.append(u'%s 孔离 %s.%s(%s) %.3f' % (net, q[0], q[1], q[7] or 'NC', d)) + alls = list(segs) + list(prior_s) + allv = list(vias) + list(prior_v) + for s in segs: + for t in alls: + if t is s or t[6] == s[6] or t[0] != s[0]: + continue + d = _seg_seg(s, t) - s[5] / 2.0 - t[5] / 2.0 + if d < c - 1e-6: + bad.append(u'%s 线离 %s 线 %.3f' % (s[6], t[6], d)) + for (vx, vy, net) in allv: + if net == s[6]: + continue + d = _seg_seg(s, (0, vx, vy, vx, vy)) - s[5] / 2.0 - r + if d < c - 1e-6: + bad.append(u'%s 线离 %s 孔 %.3f' % (s[6], net, d)) + for (vx, vy, net) in vias: + for (wx_, wy_, n2) in allv: + if n2 != net and (wx_, wy_) != (vx, vy) and math.hypot(vx - wx_, vy - wy_) - 2 * r < c - 1e-6: + bad.append(u'%s 孔离 %s 孔 %.3f' % (net, n2, math.hypot(vx - wx_, vy - wy_) - 2 * r)) + for t in prior_s: + if t[6] != net and _seg_seg(t, (0, vx, vy, vx, vy)) - t[5] / 2.0 - r < c - 1e-6: + bad.append(u'%s 孔离 %s 线' % (net, t[6])) + if bad: + raise RuntimeError(u'%s 几何不过：%s' % (tag, u'；'.join(sorted(set(bad))))) + + +# ── U32 北沿夹在 D± 中间的三只 3V3_HUB（5 / 10 / 13）：按构造画 ──────────────────── +# 口排西 → 东：DM1 DP1 DM2 DP2 **3V3(5)** DM3 DP3 DM4 DP4 **3V3(10)** DM5 DP5 **3V3(13)** NC NC NC。 +# 五对一出来，这三只脚就被包进口袋（QFN 内圈出不去：角上缝只有 0.2 mm）。 +# 13 脚：沿北沿贴着往东（压过三只 NC 脚上方）→ 下东侧 → 接 24 脚（东侧 3V3），东侧打孔上 L1。 +# USB4/5 往东绕时从它上面过，它和 24 / VDD18 去耦一起留在绕行环的里面，靠这个孔接出去。 +# 5 脚： 北上进 USB3 掉头的口袋，在 J36 两排之间打孔上 L1。 +# 10 脚：北上夹在 USB4/USB5 之间，同样在 J36 两排之间打孔上 L1。 +# L1：两孔沿 J36 南排内端外 0.5 mm 往东连，到东头外壳盘前打孔回 L4（USB4/5 绕行车道的**外面**）。 +U32N_W = 0.2 +U32N_TOP = 0.45 # 13 脚那条横线离北排焊盘外沿 +U32N_EAST = 0.5 # 东侧竖线离东排焊盘外沿 +U32N_V = 0.5 # 5 / 10 脚的孔离 J36 南排内端 + + +def u32_north(pads, prior_s, prior_v): + pm = {(q[0], str(q[1])): q for q in pads} + p5, p10, p13, p24 = (pm[('U32', k)] for k in ('5', '10', '13', '24')) + for q in (p5, p10, p13, p24): + if q[7] != '+3V3_HUB': + raise RuntimeError(u'U32.%s 是 %s 不是 +3V3_HUB' % (q[1], q[7])) + sdp = pm[('J36', '46')] + u32 = [q for q in pads if q[0] == 'U32' and not is_ep(q)] + x_east = max(q[2] + q[4] / 2.0 for q in u32) + y_top = p13[3] + p13[5] / 2.0 + shell_e = min(q[2] - q[4] / 2.0 for q in pads if q[0] == 'J36' and q[4] >= 2.5 and q[2] > B.SLOT_CX) + n, w = '+3V3_HUB', U32N_W + t13 = round(y_top + U32N_TOP, 3) + xe = round(x_east + U32N_EAST, 3) + yv = round(sdp[3] + sdp[5] / 2.0 + U32N_V, 3) + v5 = (round(p5[2] - 0.35, 3), yv) + v10 = (round(p10[2] + 0.75, 3), yv) + v13 = (xe, round(p24[3] + 1.5, 3)) + vd = (round(shell_e - 1.0, 3), yv) + ya = round(yv - 0.6, 3) + segs = [(2, p13[2], p13[3], p13[2], t13, w, n), (2, p13[2], t13, xe, t13, w, n), + (2, xe, t13, xe, p24[3], w, n), (2, xe, p24[3], p24[2], p24[3], w, n), + (2, p5[2], p5[3], p5[2], ya, w, n), (2, p5[2], ya, v5[0], v5[1], w, n), + (2, p10[2], p10[3], p10[2], ya, w, n), (2, p10[2], ya, v10[0], v10[1], w, n), + (1, v5[0], v5[1], vd[0], vd[1], w, n)] + vias = [(v5[0], v5[1], n), (v10[0], v10[1], n), (v13[0], v13[1], n), (vd[0], vd[1], n)] + geom_check(u'U32 北沿 3V3_HUB', segs, vias, pads, prior_s, prior_v) + virt = [['U32', 'fan:e13', v13[0], v13[1], 0.3, 0.3, 1, n, 'RECT'], + ['U32', 'fan:vd', vd[0], vd[1], 0.3, 0.3, 2, n, 'RECT']] + return segs, vias, {('U32', '5'), ('U32', '10'), ('U32', '13'), ('U32', '24')}, virt + + +# ── 其余 D± 按构造画（2026-09-10 用户选定：构造 D± + 划横穿车道）──────────────────── +# A* 逐网布 D± 不认拓扑：DP 抄最短路把自家 DM 的出口封死（第四轮 USB2/4/5/6 的 DM 全「出不来」）。 +# 规则只有一条：**槽上 D+ 在西、D− 在东 ⇒ 这一对必须「向南」进焊盘**（掉头 / 绕行都保持 DM 在行进方向左侧）。 +# 北去（USB1 → J34、USB2 → J35）：出脚 45° 往西让开 USB3 的 U 形，北上到目标槽，在两排之间**向东掉头**， +# 打孔上 L1、从北边进焊盘内端。 +# 南去（USB4 → J37、USB5 → J38）：出脚向东（USB5 在 13 脚那条线上面、USB4 在 10 脚过孔上面）， +# 到 DP_H 车道南下。USB4 在内圈外侧 ⇒ 转回西时必然横过 USB5 —— 用它本来就要的 L4→L1 那一跳： +# 在 J37 两排之间打孔上 L1、在 L1 上向西进焊盘；USB5 在 L4 从它底下继续南下到 J38 再向西打孔。 +# 上行 / USB6：在 U32 西侧过孔带（place_base.LANES['U32_WVIA']）各打两颗交错孔上 L1，之后交给 A*（从 L1 起步）。 +DPC_JOG_W = 0.25 # 北去四根出脚后的转弯高度步进（45° 斜段互相平行、中心距 ≥ 0.5） +DPC_SHIFT = {'USB1': 3.5, 'USB2': 2.5} +DPC_VIA = 1.0 # 过孔离焊盘内端 +DPC_UT = 0.6 # 内圈横段在过孔外侧多少 +DPC_UT_OUT = 0.5 # 外圈横段再往外多少 +# 离 DP_H 车道西沿（DP, DM）。USB4 两根拉开到 0.7：DM 的 L4 竖线要一直下到自己的孔（在 DP 孔南边）， +# 0.5 的话它擦过 DP 的孔只剩 0.06（静态校验实测）。 +DPC_LANE = {'USB5': (0.0, 0.5), 'USB4': (1.8, 2.5)} +DPC_Y5 = 0.5 # USB5 DP 横段在 13 脚那条线上方多少 +DPC_Y4 = 0.85 # USB4 DP 横段在 10 脚过孔中心上方多少 +WVIA_DX = (0.85, 1.45) # USB6/UP 两颗孔离西排焊盘外沿（DM, DP） + + +def _poly2(layer, pts, w, net): + return [(layer, a[0], a[1], b[0], b[1], w, net) for a, b in zip(pts, pts[1:]) + if abs(a[0] - b[0]) + abs(a[1] - b[1]) > 1e-9] + + +def dp_construct(pads, prior_s, prior_v): + import place_base as PL + pm = {(q[0], str(q[1])): q for q in pads} + u = lambda k: pm[('U32', k)] # noqa: E731 + w = DIFF_W + segs, vias, done, virt = [], [], set(), [] + top = u('1')[3] + u('1')[5] / 2.0 + + def slot(i): + ref = B.USB_SLOT_REF[i] + sp, sm = pm[(ref, '46')], pm[(ref, '47')] + done.update({(ref, '46'), (ref, '47')}) + return sp, sm + + # 北去：USB1 / USB2 + order = [('USB1', '1', '2'), ('USB2', '3', '4')] + k = 0 + for name, pdm, pdp in order: + dp_net, dm_net = PAIRS[name] + i = int(name[3]) + sp, sm = slot(i) + s = DPC_SHIFT[name] + y_in = sp[3] + sp[5] / 2.0 + yv = round(y_in + DPC_VIA, 3) + yt = round(yv + DPC_UT, 3) + for net, pk, xt, ytt in ((dm_net, pdm, sm[2], yt + DPC_UT_OUT), (dp_net, pdp, sp[2], yt)): + q = u(pk) + ya = round(top + 0.3 + k * DPC_JOG_W, 3) + k += 1 + x1 = round(q[2] - s, 3) + pts = [(q[2], q[3]), (q[2], ya), (x1, round(ya + s, 3)), (x1, ytt), (xt, ytt), (xt, yv)] + segs += _poly2(2, pts, w, net) + segs += _poly2(1, [(xt, yv), (xt, sp[3])], w, net) + vias.append((xt, yv, net)) + done.add(('U32', pk)) + + # 南去：USB5（内圈）/ USB4（外圈） + lane_x = PL.LANES['DP_H'][0] + t13 = [s2 for s2 in prior_s if s2[6] == '+3V3_HUB' and s2[0] == 2 and abs(s2[2] - s2[4]) < 1e-9 + and abs(s2[1] - s2[3]) > 2.0] + y13 = max(s2[2] for s2 in t13) # 13 脚那条横线的 y + v10 = [v for v in prior_v if v[2] == '+3V3_HUB'] + y10 = max(v[1] for v in v10 if v[1] < 50) # 5 / 10 脚的孔（J36 两排之间） + sp5, sm5 = slot(5) + y_in5 = sp5[3] + sp5[5] / 2.0 + yv5 = round(y_in5 + DPC_VIA, 3) + y5dp = round(y13 + DPC_Y5, 3) + xdp5, xdm5 = round(lane_x + DPC_LANE['USB5'][0], 3), round(lane_x + DPC_LANE['USB5'][1], 3) + wdm5, wdp5 = round(yv5 + 0.64, 3), round(yv5 + 1.14, 3) + for net, pk, yh, xl, yw, xt in ((PAIRS['USB5'][0], '12', y5dp, xdp5, wdp5, sp5[2]), + (PAIRS['USB5'][1], '11', y5dp + 0.5, xdm5, wdm5, sm5[2])): + q = u(pk) + pts = [(q[2], q[3]), (q[2], yh), (xl, yh), (xl, yw), (xt, yw), (xt, yv5)] + segs += _poly2(2, pts, w, net) + segs += _poly2(1, [(xt, yv5), (xt, sp5[3])], w, net) + vias.append((xt, yv5, net)) + done.add(('U32', pk)) + sp4, sm4 = slot(4) + y_in4 = sp4[3] + sp4[5] / 2.0 + y4dp = round(y10 + DPC_Y4, 3) + xdp4, xdm4 = round(lane_x + DPC_LANE['USB4'][0], 3), round(lane_x + DPC_LANE['USB4'][1], 3) + vdp4, vdm4 = round(y_in4 + 4.32, 3), round(y_in4 + 3.52, 3) # 交错两颗孔（J37 两排之间） + for net, pk, yh, xl, yvv, xt in ((PAIRS['USB4'][0], '9', y4dp, xdp4, vdp4, sp4[2]), + (PAIRS['USB4'][1], '8', y4dp + 0.5, xdm4, vdm4, sm4[2])): + q = u(pk) + segs += _poly2(2, [(q[2], q[3]), (q[2], yh), (xl, yh), (xl, yvv)], w, net) + segs += _poly2(1, [(xl, yvv), (xt, yvv), (xt, sp4[3])], w, net) + vias.append((xl, yvv, net)) + done.add(('U32', pk)) + + # 上行 / USB6：西侧过孔带里各两颗交错孔，之后从 L1 起步 + west = [q for q in pads if q[0] == 'U32' and not is_ep(q) and q[4] > q[5]] + x_left = min(q[2] - q[4] / 2.0 for q in west) + for name, pdm, pdp in (('USB6', '53', '54'), ('USBUP', '58', '59')): + dp_net, dm_net = PAIRS[name] + for net, pk, dx, dy in ((dm_net, pdm, WVIA_DX[0], -0.25), (dp_net, pdp, WVIA_DX[1], 0.0)): + q = u(pk) + vx, vy = round(x_left - dx, 3), round(q[3] + dy, 3) + pts = [(q[2], q[3]), (round(x_left - 0.35, 3), q[3]), (vx, vy)] + segs += _poly2(2, pts, 0.2, net) + vias.append((vx, vy, net)) + virt.append(['U32', 'fan:%s' % pk, vx, vy, 0.3, 0.3, 1, net, 'RECT']) + done.add(('U32', pk)) + geom_check(u'D± 构造（USB1/2/4/5 + 上行/USB6 西侧孔）', segs, vias, pads, prior_s, prior_v) + return segs, vias, done, virt + + +# ── 通用扇出：这几颗芯片的每只非地、非 D± 脚先打一个孔上 L1，布线从 L1 的落点起步 ───────── +FANOUT_REFS = ('U35', 'U6', 'U7', 'U20') +FAN_W = 0.15 +# 这几个分区里**所有件**的非地信号脚也扇出（第五轮：D± 全通之后剩 37 个网，21 条在 U20 北沿那排上拉 / +# NTC 阻容上 —— 0402 一字排开、两头都在 L4，头顶的 L1 是空的却上不去）。 +# ⚠ A4H（U32 那条走廊）**不扇**：那里的晶振 / RBIAS / strap 要和 U32 的脚在 L4 就近连，打孔反而绕远。 +# ⚠ U31（LDO，宽电源脚）与 J23（Type-C，0.5 间距，出口带另有安排）不扇。 +# ⛔ 第七轮实测**反效果**（信号网 37 → 43、GND 打孔失败 97 → 106）：小件挨着排（0.6 mm 装配间距）， +# 每只焊盘就近打孔 = 把 L4 上的一簇件变成两层都占的一簇孔，A3 里两头都已在 L1 的脚照样「没布通」。 +# 根子在摆位间距，不在扇出。先关掉，留着代码。 +FAN_ZONES = () +FAN_ZONE_SKIP = ('U31', 'J23', 'J33') + + +def fan_zone_refs(): + import place_base as PL + pg = PL.page_of() + return set(r for r in pg if r not in FAN_ZONE_SKIP and PL.zone_of_ref(r, pg) in FAN_ZONES) + + +# U20 的脚距 1.27：最近的落点排成一列、孔距 1.27 ⇒ 在 L1 上连成一道墙（第四轮 29 条失败在 U20 周围）。 +# ⇒ 奇数脚往外多让 FAN_STAGGER，孔错成两排。 +FAN_STAGGER = {'U20': 1.0} + + +def fanout(pads, bypad, segs, vias, board_vias, logs): + u"""原地改 bypad：扇出成功的脚换成 L1 上的虚拟落点 `fan:<脚号>`。返回 (segs, vias, 成功数, 失败数)。""" + halfv = RT.VIA_D / 2.0 + RT.CLR + g, gt, others = grid_now(pads, halfv, segs, vias, board_vias) + sh = FAN_W / 2.0 + todo = [] + zref = fan_zone_refs() + for net, ps in bypad.items(): + if net in DP_NETS or net in PLANE_NETS: + continue + for q in ps: + if (q[0] in FANOUT_REFS or q[0] in zref) and not RT._is_launch(q) and q[6] in RT.LAY \ + and (q[0], str(q[1])) not in TH_KEYS: + todo.append(q) + + def cands(q): + return [nd for nd in RT.pad_nodes(g, q, halfv, others.get(q[6], []), sh, gt) + if g.free_via(nd[1], nd[2], q[7])] + + todo.sort(key=lambda q: (len(cands(q)), q[0], str(q[1]))) + out_s, out_v, ok, fail = [], [], 0, 0 + for q in todo: + cs = cands(q) + if not cs: + fail += 1 + continue + nd = cs[0] + stg = FAN_STAGGER.get(q[0], 0.0) + if stg and str(q[1]).isdigit() and int(q[1]) % 2: + d0 = math.hypot(RT.wx(cs[0][1]) - q[2], RT.wy(cs[0][2]) - q[3]) + far = [c2 for c2 in cs if math.hypot(RT.wx(c2[1]) - q[2], RT.wy(c2[2]) - q[3]) >= d0 + stg] + if far: + nd = far[0] + vx, vy = RT.wx(nd[1]), RT.wy(nd[2]) + ss = RT.stub_emit(q, vx, vy, others.get(q[6], []), sh, FAN_W, q[7], gt) + out_s += ss + out_v.append((vx, vy, q[7])) + keep = halfv + FAN_W / 2.0 + for (l, a, b, c, d, ww, nn) in ss: + RT.block_track(g, l, a, b, c, d, keep, nn) + RT.block_track(gt, l, a, b, c, d, RT.CLR + sh + ww / 2.0, nn) + rr = RT.VIA_D / 2.0 + halfv + rt = RT.VIA_D / 2.0 + RT.CLR + sh + for l in RT.LAY: + g.block_both(l, vx - rr, vy - rr, vx + rr, vy + rr, 0.0, net=q[7]) + gt.block_rect(l, vx - rt, vy - rt, vx + rt, vy + rt, net=q[7]) + bypad[q[7]] = [o for o in bypad[q[7]] if o is not q] + bypad[q[7]].append([q[0], 'fan:%s' % q[1], vx, vy, 0.3, 0.3, 1, q[7], 'RECT']) + ok += 1 + return out_s, out_v, ok, fail + + +def _p2s(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0.0 if L2 < 1e-12 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2)) + return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + + +def _seg_seg(a, b): + u"""两段中心线之间的最短距离（不相交时）。""" + return min(_p2s(a[1], a[2], b[1], b[2], b[3], b[4]), _p2s(a[3], a[4], b[1], b[2], b[3], b[4]), + _p2s(b[1], b[2], a[1], a[2], a[3], a[4]), _p2s(b[3], b[4], a[1], a[2], a[3], a[4])) + + +def _seg_rect_gap(s, r): + u"""线段（中心线）到矩形的最短距离（相交为 0）。""" + def p2s(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0.0 if L2 < 1e-12 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2)) + return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy)) + x0, y0, x1, y1 = s[1], s[2], s[3], s[4] + n = max(2, int(math.hypot(x1 - x0, y1 - y0) / 0.02)) + best = 1e9 + for k in range(n + 1): + t = k / float(n) + px, py = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + dx = max(r[0] - px, px - r[2], 0.0) + dy = max(r[1] - py, py - r[3], 0.0) + best = min(best, math.hypot(dx, dy)) + return best + + +# ⛔ 上行 / USB6 两对的脚在 U32 **西**侧，去处却在东边（J23 / U20）。首轮 A* 从 L4 绕 U32 南边， +# 贴着南沿把 strap 脚（CFGSEL0/1、NONREM0/1、HUB_RST、VBUS_DET）全封死。 +# ⇒ 布这两对时在 U32 的南 / 北 / 东三面围一道**只对它们**的 L4 栅栏（离焊盘 3 mm）， +# 逼它们在西侧打孔上 L1、从芯片顶上过去（L1 在走廊 2 是空的）。 +FENCED_PAIRS = ('USB6', 'USBUP') +FENCE_OUT = 3.0 +FENCE_IN = 0.9 # 栅栏西端离西排焊盘外沿多远（给西排脚自己的引出脚留地方） + + +def u32_fence(pads): + ps = [q for q in pads if q[0] == 'U32' and q[7] != 'GND'] + x0 = min(q[2] - q[4] / 2 for q in ps) + y0 = min(q[3] - q[5] / 2 for q in ps) + x1 = max(q[2] + q[4] / 2 for q in ps) + y1 = max(q[3] + q[5] / 2 for q in ps) + xw = x0 + FENCE_IN + return [(2, (xw, y0 - FENCE_OUT, x1 + FENCE_OUT, y0 + FENCE_IN)), # 南 + (2, (xw, y1 - FENCE_IN, x1 + FENCE_OUT, y1 + FENCE_OUT)), # 北 + (2, (x1 - FENCE_IN, y0 - FENCE_OUT, x1 + FENCE_OUT, y1 + FENCE_OUT))] # 东 + + +def route_pairs(bypad, pads, segs, vias, board_vias, logs): + u"""七对 D±：DP 先布，DM 贴着它布。返回新布的 (segs, vias)。""" + out_s, out_v = [], [] + pad_pen = RT.PAD_PEN + RT.PAD_PEN = DP_PAD_PEN + fence = u32_fence(pads) + try: + for k, name in enumerate(PAIR_ORDER): + dp, dm = PAIRS[name] + later = [q for nm in PAIR_ORDER[k + 1:] for n in PAIRS[nm] for q in bypad.get(n, [])] + fc = fence if name in FENCED_PAIRS else () + # ⛔ 上行 / USB6 的 DP：L4 上除了两端脚附近 3 mm 全收过路费，逼它上 L1 走空走廊。 + # 第二轮只有栅栏时，它从栅栏西南角绕出去、贴着 J37 底下往东，照样把 strap 脚南路堵了。 + # DM 不用单独处理：它贴着 DP 的带子走。 + lp = None + if name in FENCED_PAIRS: + lp = {1: [(0.0, 0.0, B.BW, B.BH)], + 2: [RT.pad_rect(q, 3.0) for q in bypad.get(dp, []) + bypad.get(dm, [])]} + s, v = route_one(dp, bypad.get(dp, []), DIFF_W, pads, segs + out_s, vias + out_v, + board_vias, logs, pen_pads=later + bypad.get(dm, []), fence=fc, hug=lp) + out_s += s + out_v += v + band = None + if s: + band = {1: [], 2: []} + for q in s: + band[q[0]].append(_seg_box(q, HUG_BAND)) + for (vx, vy, _n) in v: + for l in RT.LAY: + band[l].append((vx - 1.2, vy - 1.2, vx + 1.2, vy + 1.2)) + for q in bypad.get(dm, []): + r = RT.pad_rect(q, HUG_PAD) + for l in RT.LAY: + band[l].append(r) + s2, v2 = route_one(dm, bypad.get(dm, []), DIFF_W, pads, segs + out_s, vias + out_v, + board_vias, logs, pen_pads=later, hug=band, fence=fc) + out_s += s2 + out_v += v2 + finally: + RT.PAD_PEN = pad_pen + return out_s, out_v + + +def is_ep(p): + return p[7] == 'GND' and min(p[4], p[5]) >= EP_MIN + + +def plane_vias(pads, segs, vias, board_vias, logs, skip, which, done): + u"""GND / +12V 平面网：每只焊盘一个过孔（大 GND 焊盘在盘里打孔阵）。 + + `which='early'`：+12V 焊盘 + GND 散热 / 外壳盘（盘内孔阵，不占任何人的出口），布信号之前做。 + `which='late'`：其余 GND 贴片焊盘，**布完信号之后**做。 + ⛔ 首轮是全部放在信号之前：插槽 1 mm 间距的针排里，GND 脚的孔一落就把隔壁信号脚的出口 + 夹成 0.4 mm（0.15 的线都过不去）—— I²C / VDAC / EFUSE_EN / PRSNT 几十条全报「没布通」。 + `done` 记已处理的焊盘（早段孔阵没打上的，晚段按普通焊盘再试）。 + """ + halfv = RT.VIA_D / 2.0 + RT.CLR + g, gt, others = grid_now(pads, halfv, segs, vias, board_vias) + m = B.l1_12v_rects()[0] + land = (m[0] + V12_LAND, m[1] + V12_LAND, m[2] - V12_LAND, m[3] - V12_LAND) + out_s, out_v = [], [] + cnt = {'GND': 0, '+12V': 0, '+3V3': 0, 'EP': 0} + sh = RT.W_DEFAULT / 2.0 + + def occupy(ss, vx, vy, net, w): + keep = halfv + w / 2.0 + for (l, a, b, c, d, ww, _nn) in ss: + RT.block_track(g, l, a, b, c, d, keep, net) + RT.block_track(gt, l, a, b, c, d, RT.CLR + sh + ww / 2.0, net) + r = RT.VIA_D / 2.0 + halfv + rt = RT.VIA_D / 2.0 + RT.CLR + sh + for l in RT.LAY: + g.block_both(l, vx - r, vy - r, vx + r, vy + r, 0.0, net=net) + gt.block_rect(l, vx - rt, vy - rt, vx + rt, vy + rt, net=net) + + for p in pads: + net = p[7] + if net not in PLANE_NETS or p[6] not in RT.LAY: + continue + key = (p[0], str(p[1])) + if str(p[1]).endswith(TH_SUFFIX) or key in TH_KEYS or key in skip: + continue + if net == '+12V' and p[6] == 1: + continue # 槽上的 12V 针本来就在 L1 大铜里 + if key in done: + continue + # 早段：+12V、散热盘孔阵、以及几颗扇出芯片自己的 +3V3 脚（它们最容易被信号封住） + early_3v3 = net == '+3V3' and p[0] in FANOUT_REFS + if which == 'early' and not (net == '+12V' or is_ep(p) or early_3v3): + continue + if which == 'late' and net not in LATE_PLANE_NETS: + continue + if which == 'early' and is_ep(p): + x0, y0, x1, y1 = RT.pad_rect(p) + nx = max(1, int((x1 - x0 - 2 * EP_EDGE) / EP_PITCH) + 1) + ny = max(1, int((y1 - y0 - 2 * EP_EDGE) / EP_PITCH) + 1) + nx, ny = min(nx, 3), min(ny, 3) + got = 0 + for a in range(nx): + for b in range(ny): + vx = p[2] if nx == 1 else x0 + EP_EDGE + a * (x1 - x0 - 2 * EP_EDGE) / (nx - 1) + vy = p[3] if ny == 1 else y0 + EP_EDGE + b * (y1 - y0 - 2 * EP_EDGE) / (ny - 1) + i, j = RT.gx(vx), RT.gy(vy) + if g.free_via(i, j, 'GND'): + out_v.append((round(vx, 3), round(vy, 3), 'GND')) + occupy([], vx, vy, 'GND', 0.0) + got += 1 + if got: + cnt['EP'] += 1 + done.add(key) + continue # 没打上的留给晚段按普通焊盘处理 + w = max(RT.rule_min(net, {}), min(0.5 if net == '+12V' else 0.3, p[4], p[5])) + # ⛔ 落孔只看**过孔图**（free_via，两层都按过孔口径让开）。第一版还要求两层**导线图**都空， + # 而 L1 的 12V 大铜在导线图里是占着的 —— A1/A2/A6 里 40 多只 GND 脚因此全报「找不到落孔点」。 + # GND 孔落进 12V 大铜是合法的：铺铜自己挖反焊盘。 + cand = [nd for nd in RT.pad_nodes(g, p, halfv, others.get(p[6], []), w / 2.0, gt) + if g.free_via(nd[1], nd[2], net) + and (net != '+12V' or (land[0] <= RT.wx(nd[1]) <= land[2] + and land[1] <= RT.wy(nd[2]) <= land[3]))] + if not cand: + logs.append(u'%s: %s.%s 找不到落过孔的地方' % (net, p[0], p[1])) + continue + nd = cand[0] + vx, vy = RT.wx(nd[1]), RT.wy(nd[2]) + ss = RT.stub_emit(p, vx, vy, others.get(p[6], []), w / 2.0, w, net, gt) + out_s += ss + out_v.append((vx, vy, net)) + occupy(ss, vx, vy, net, w) + cnt[net] += 1 + done.add(key) + print(u' 平面网扇出（%s）：GND %d / +3V3 %d 只脚各一孔、散热/外壳盘 %d 块打孔阵、+12V %d 只脚；共 %d 孔' + % (which, cnt['GND'], cnt['+3V3'], cnt['EP'], cnt['+12V'], len(out_v))) + return out_s, out_v + + +# ── 主流程 ─────────────────────────────────────────────────────────────── +def plan_all(priority=()): + pads = load_pads() + board_vias = load_board_vias() + print(u'板上已有过孔 %d 个；通孔焊盘 %d 只（L4 可布 + L1 障碍）' % (len(board_vias), len(TH_KEYS))) + segs, vias, logs = [], [], [] + + ks, kv = kelvin(pads, segs, vias, board_vias, logs) + segs += ks + vias += kv + print(u' Kelvin：%d 段 / %d 孔' % (len(ks), len(kv))) + hs, hv = v12_handoff(pads) + segs += hs + vias += hv + print(u' 9 A 上 L1：Rs6.2 西侧铜块 + %d 个过孔' % len(hv)) + + js, jdone = j23_bridges(pads) + segs += js + print(u' J23 同名 D± 脚两座桥：%d 段（DP 南绕 / DM 北绕）' % len(js)) + us, uv, udone = usb3_uturn(pads) + segs += us + vias += uv + jdone |= udone + print(u' USB3 U 形掉头：%d 段 / %d 孔（按构造画，换位不交叉）' % (len(us), len(uv))) + ns, nv, ndone, nvirt = u32_north(pads, segs, vias) + segs += ns + vias += nv + jdone |= ndone + print(u' U32 北沿 3V3_HUB（5/10/13 + 24）：%d 段 / %d 孔（按构造画）' % (len(ns), len(nv))) + cs_, cv, cdone, cvirt = dp_construct(pads, segs, vias) + segs += cs_ + vias += cv + jdone |= cdone + nvirt = nvirt + cvirt + print(u' D± 构造（USB1/2 北去掉头、USB4/5 东绕、上行/USB6 西侧上 L1）：%d 段 / %d 孔' % (len(cs_), len(cv))) + + kel = {a for a, _b, _w in KELVIN} # U13.9/.10 已由专线接好 + bypad = {} + for p in pads: + if not p[7] or p[7] in PLANE_NETS or str(p[1]).endswith(TH_SUFFIX): + continue + if (p[0], str(p[1])) in kel or (p[0], str(p[1])) in jdone: + continue + bypad.setdefault(p[7], []).append(p) + for v in nvirt: + bypad.setdefault(v[7], []).append(v) + + ds, dv = route_pairs(bypad, pads, segs, vias, board_vias, logs) + segs += ds + vias += dv + print(u' D± 七对：%d 段 / %d 孔' % (len(ds), len(dv))) + if '--dp-only' in sys.argv: + return segs, vias, logs + + skip = set(kel) | {('Rs6', '2')} + done = set() + ps, pv = plane_vias(pads, segs, vias, board_vias, logs, skip, 'early', done) + segs += ps + vias += pv + GND_PEN_PADS[:] = [q for q in pads if q[7] in LATE_PLANE_NETS and q[6] in RT.LAY + and (q[0], str(q[1])) not in done and (q[0], str(q[1])) not in TH_KEYS + and not str(q[1]).endswith(TH_SUFFIX)] + fs, fv, fok, ffail = fanout(pads, bypad, segs, vias, board_vias, logs) + segs += fs + vias += fv + print(u' 扇出上 L1（%s）：%d 只脚打孔，%d 只没落点（留给 A* 直接接）' + % (' '.join(FANOUT_REFS), fok, ffail)) + + rest = set(bypad) - set(DP_NETS) + RT.AUTO_CACHE.clear() + blocked = [('#ant', r) for r in (_KEEP[0] or keep_rects())] + [('+12V', V12_PATCH)] + direct_nets = rest & set(priority) if priority else rest + dsegs, merged = RT.direct_links(pads, {n: bypad[n] for n in direct_nets}, segs, vias, + blocked_rects=blocked) + segs += dsegs + for net, groups in merged.items(): + drop = set() + for group in groups: + drop |= set(list(group)[1:]) + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) not in drop] + print(u' 直连：%d 段 / %d 个网络' % (len(dsegs), len(merged))) + # U32 的本地网（晶振 / RBIAS / VDD18PLL / VDD18 / strap / HUB_RST / VBUS_DET）：第六轮它们的脚全被 + # 先布的长信号在 U32 西侧落的孔、南边拉的线堵住，而要连的件就在一两毫米外 ⇒ 在长信号之前先布。 + u32_local = set(n for n in rest if n not in POWER_LATE and n not in CHAIN_NETS + and any(q[0] == 'U32' for q in bypad.get(n, []))) + fixed_s, fixed_v = len(segs), len(vias) + # 四段：输入链（短、宽、有专属条带）→ U32 本地网 → 普通信号 → 电源（最后布，脚一直收过路费） + phases = [set(CHAIN_NETS) & rest, u32_local, set(), set(POWER_LATE) & rest] + phases[2] = rest - phases[0] - phases[1] - phases[3] + if '--pf' in sys.argv: + LATER_PEN_PADS[:] = [q for n in rest - u32_local for q in bypad.get(n, [])] + logs += RT.route_groups(bypad, pads, segs, vias, board_vias, {}, priority=priority, + only=u32_local) + print(u' U32 本地网（%d 个）先布：失败 %d 条' % (len(u32_local), len(logs))) + fixed_s, fixed_v = len(segs), len(vias) + rest = rest - u32_local + # 协商式拥塞布线（router.pf_solve，PathFinder）：每轮所有网重布、被多网压着的格点逐轮涨价， + # 直到有人让路。第四轮的失败已经不是「脚出不来」而是贪心抢通道（长网先布、走最短路， + # 走廊 3 和槽体西段 x 36~43 很快被占光）—— 正是 PathFinder 要解决的那一类。 + if '--pf-iters' in sys.argv: + RT.PF_ITERS = int(sys.argv[sys.argv.index('--pf-iters') + 1]) + LATER_PEN_PADS[:] = [] + logs += RT.pf_solve({n: bypad[n] for n in rest if n in bypad}, pads, segs, vias, + board_vias, {}, fixed_s, fixed_v) + print(u' PathFinder：失败 %d 条' % len(logs)) + phases = [] + for k, ph in enumerate(phases): + later = set().union(*phases[k + 1:]) if k + 1 < len(phases) else set() + LATER_PEN_PADS[:] = [q for n in later for q in bypad.get(n, [])] + n0 = len(logs) + logs += RT.route_groups(bypad, pads, segs, vias, board_vias, {}, priority=priority, only=ph) + print(u' 第 %d 段（%d 个网）：失败 %d 条' % (k + 1, len(ph), len(logs) - n0)) + LATER_PEN_PADS[:] = [] + if logs and '--repair' in sys.argv: + print(u' 首轮 %d 条没搞定，进入拆线重布' % len(logs)) + segs, vias, logs = rip_repair(bypad, pads, segs, vias, logs, board_vias, rest, fixed_s, fixed_v) + GND_PEN_PADS[:] = [] + ps, pv = plane_vias(pads, segs, vias, board_vias, logs, skip, 'late', done) + segs += ps + vias += pv + gs, nres = gnd_rescue(pads, segs, vias, logs, done, blocked) + segs += gs + print(u' GND 打不上孔的脚：直连到邻近已接地焊盘救回 %d 只（%d 段）' % (nres, len(gs))) + segs, vias = RT.dedupe_vias(segs, vias) + for m in RT.check_connected(check_pads(pads), segs, vias): + if m not in logs: + logs.append(u'[连通性] ' + m) + return segs, vias, logs + + +GND_RESCUE_R = 2.6 # 找「邻近已接地焊盘」的半径（mm，同层） + + +def gnd_rescue(pads, segs, vias, logs, done, blocked): + u"""晚段打不上孔的 GND 脚：用 router.direct_links 直连到邻近**已接地**的同层焊盘（原地删掉救回的日志）。 + + 插槽针排里两只相邻的 GND 脚（1 mm 间距、缝 0.3）最常见：隔壁那只有孔，直连一段就接上了。 + 「已接地」= 已有平面孔（done）或通孔焊盘（本来就穿到内层地）。 + """ + tag = u'找不到落过孔的地方' + anchor = set(done) | TH_KEYS + out_s, nok = [], 0 + for net in LATE_PLANE_NETS: # GND 和 +3V3 各救各的 + head = net + ': ' + fl = [m for m in logs if m.startswith(head) and tag in m] + if not fl: + continue + fkeys = set() + for m in fl: + ref, pin = m[len(head):].split(' ')[0].rsplit('.', 1) + fkeys.add((ref, pin)) + fpads = [q for q in pads if (q[0], str(q[1])) in fkeys and q[6] in RT.LAY] + near = [q for q in pads if q[7] == net and q[6] in RT.LAY and (q[0], str(q[1])) in anchor + and not str(q[1]).endswith(TH_SUFFIX) + and any(q[6] == f[6] and abs(q[2] - f[2]) < GND_RESCUE_R + and abs(q[3] - f[3]) < GND_RESCUE_R for f in fpads)] + dsegs, merged = RT.direct_links(pads, {net: fpads + near}, segs + out_s, vias, + blocked_rects=blocked) + ok = set() + for grp in merged.get(net, []): + keys = set((k[0], str(k[1])) for k in grp) + if keys & anchor: + ok |= keys & fkeys + logs[:] = [m for m in logs + if not (m in fl and tuple(m[len(head):].split(' ')[0].rsplit('.', 1)) in ok)] + out_s += dsegs + nok += len(ok) + return out_s, nok + + +def check_pads(pads): + u"""连通性判据用的焊盘：去掉 L1 的通孔副本、L1 大铜里的 12V 针、单脚网。""" + cnt = {} + for q in pads: + cnt[q[7]] = cnt.get(q[7], 0) + 1 + return [q for q in pads if not str(q[1]).endswith(TH_SUFFIX) + and not (q[7] == '+12V' and q[6] == 1) and cnt.get(q[7], 0) >= 2] + + +def rip_repair(bypad, pads, segs, vias, logs, board_vias, rest, fixed_s, fixed_v): + u"""`router.repair` 接到底板上：只交普通信号（D± / 平面网不拆），验收用 check_pads。""" + import time + sub = {n: bypad[n] for n in rest if n in bypad} + chk_pads = [q for q in check_pads(pads) if q[7] in sub] + orig_chk, orig_rg = RT.check_connected, RT.route_groups + t0, n = time.time(), [0] + + def chk(_pads, s, v): + return orig_chk(chk_pads, s, v) + + def rg(*a, **k): + n[0] += 1 + out = orig_rg(*a, **k) + print(u' 拆线重布 #%d：重布 %d 个网，失败 %d 条（累计 %.0f s）' + % (n[0], len(k.get('only') or ()), len(out), time.time() - t0)) + sys.stdout.flush() + return out + + RT.check_connected, RT.route_groups = chk, rg + try: + return RT.repair(sub, pads, segs, vias, logs, board_vias, {}, fixed_s, fixed_v) + finally: + RT.check_connected, RT.route_groups = orig_chk, orig_rg + + +def report(segs, vias, logs): + L = lambda s: math.hypot(s[3] - s[1], s[4] - s[2]) # noqa: E731 + tot = sum(L(s) for s in segs) + top = sum(L(s) for s in segs if s[0] == 1) + print(u'导线 %d 段 / 总长 %.1f mm（L1 %.1f mm = %.0f%%）/ 过孔 %d（GND %d / +12V %d / 信号 %d）' + % (len(segs), tot, top, 100.0 * top / max(tot, 1e-9), len(vias), + sum(1 for v in vias if v[2] == 'GND'), sum(1 for v in vias if v[2] == '+12V'), + sum(1 for v in vias if v[2] not in PLANE_NETS))) + print(u'差分对实测铜长（含引出脚）/ 过孔数:') + for name, dp, dm in RB.PAIRS: + a = sum(L(s) for s in segs if s[6] == dp) + b = sum(L(s) for s in segs if s[6] == dm) + va = sum(1 for v in vias if v[2] == dp) + vb = sum(1 for v in vias if v[2] == dm) + print(u' %-6s DP %5.1f mm / %d 孔 DM %5.1f mm / %d 孔 差 %.1f mm' + % (name, a, va, b, vb, abs(a - b))) + if logs: + print(u'[!] %d 条没搞定:' % len(logs)) + for m in logs[:40]: + print(u' ' + m) + + +if __name__ == '__main__': + if '--clear' in sys.argv: + RT.clear_mine() + sys.exit(0) + if '--snapshot-vias' in sys.argv: + print(u'底板既有过孔快照：%d 个 -> %s' % (len(load_board_vias()), BOARD_VIAS)) + sys.exit(0) + c = json.load(io.open(CACHE, encoding='utf-8')) if os.path.exists(CACHE) else {} + cache_ok = (c.get('schema') == CACHE_SCHEMA and c.get('slot_rot') == B.SLOT_ROT and + c.get('usb_slot_ref') == {str(k): v for k, v in B.USB_SLOT_REF.items()}) + if '--replan' not in sys.argv and cache_ok: + segs, vias, logs = [tuple(s) for s in c['segs']], [tuple(v) for v in c['vias']], c['logs'] + print(u'（用缓存 _base_routes.json）') + elif '--replan' not in sys.argv: + sys.exit(u'!! 没有 4 层版缓存（schema %d）；布线要在服务器上算：.claude/r2/remote_route.ps1' + % CACHE_SCHEMA) + else: + best, prio = None, set() + if '--priority-cache' in sys.argv and cache_ok: + prio = set(RT._msg_net(m) for m in c.get('logs', [])) + print(u'（用上轮 %d 条失败记录优先排网）' % len(c.get('logs', []))) + if '--passes' in sys.argv: + RT.PASSES = int(sys.argv[sys.argv.index('--passes') + 1]) + for it in range(RT.PASSES): + segs, vias, logs = plan_all(prio) + print(u' 第 %d 轮：%d 条没搞定' % (it + 1, len(logs))) + if best is None or len(logs) < len(best[2]): + best = (segs, vias, logs) + if not logs: + break + prio |= set(RT._msg_net(m) for m in logs) + segs, vias, logs = best + if '--dp-only' not in sys.argv: + io.open(CACHE, 'w', encoding='utf-8').write(json.dumps({ + 'schema': CACHE_SCHEMA, 'layers': B.LAYERS, 'slot_rot': B.SLOT_ROT, + 'usb_slot_ref': B.USB_SLOT_REF, 'v12_patch': V12_PATCH, + 'segs': segs, 'vias': vias, 'logs': logs}, ensure_ascii=False)) + report(segs, vias, logs) + if '--push' in sys.argv: + # 默认仍拒绝下发不完整路由；`--force` 是 2026-09-10 用户选定的收尾方式： + # 先把最好的一版下发，剩下的在客户端手工补 / 逐条构造。 + if logs and '--force' not in sys.argv: + sys.exit(u'!! 仍有 %d 条未布通，拒绝下发不完整路由（确认要先下发再手补，加 --force）' % len(logs)) + if logs: + print(u'⚠ --force：带着 %d 条未完成下发' % len(logs)) + RT.push(segs, vias) diff --git a/.claude/r2/router.py b/.claude/r2/router.py new file mode 100644 index 0000000..fdb89bb --- /dev/null +++ b/.claude/r2/router.py @@ -0,0 +1,2118 @@ +# -*- coding: utf-8 -*- +u"""R2 刀片 PCB 的**自建布线器**（M4c-4）。 + + /c/Python314/python .claude/r2/router.py # 只算 + 打印，不下发 + /c/Python314/python .claude/r2/router.py --push # 下发导线 + 过孔 + /c/Python314/python .claude/r2/router.py --clear # 清掉本脚本布的线（保留 GND 缝合过孔） + +## 为什么要自己写 + +嘉立创 EDA 的自动布线在这台客户端上**跑不出一根铜**（方案 §24.6）： +`pcb_Document.autoRouting` 这个 API 根本不存在；GUI 的对话框能开能配， +点「运行」之后立刻关闭、铜线数 0，不报错不弹进度。⇒ 只能自己布。 + +## 做法 + +**0.25 mm 网格 + 8 邻接 A\\***，两层（L1 顶 / L4 底），换层收过孔代价。 + +- 网格选 0.25 是因为**金手指 1.0 mm 间距正好落在格点上**（32.5 / 0.25 = 130）， + 64 根指的扇出不用做特殊处理。 +- 障碍按「导线半宽 + 净距」膨胀 ⇒ 一条 0.2 mm 的线会把 0.25 外的相邻格点也占掉， + 自动保证平行线中心距 ≥ 0.5 mm。**不用另外写间距检查**。 +- 焊盘中心大多不在格点上（摆位是 0.001 精度），所以每个焊盘先出一小段 + **引出脚**（pad 中心 → 最近的可用格点），再交给 A\\*。 + +## ⛔ 三条硬约束（写死在代码里，不是注释） + +1. **只准布 L1 / L4**。L2 是「完整地平面，不许割断」（§7.1），L3 是 `VO_P` / `+12V` 的岛。 +2. **金手指区（y < 6.0）除了 J1 自己的引出脚，一根线都不许有** —— + 那一带外层铜的邻居是 0.3 mm 间距的指，蹭上就是短路，而 DRC 只报间距不报"接错了指"。 +3. **缺口（防呆键）四周 0.5 mm 内不许有铜**，缺口本身是铣穿的。 + +## `GND` / `VO_P` / `+12V` 不走 A\\*，走铜面 + +- `GND`：顶/底/L2/L3 四块铜面 + 196 个缝合过孔已经接好；**只有 J1 的 39 根地指** + 在铜面下沿（y=11.5）以下够不着，给它们各出一段引出脚 + 一个过孔。 +- `VO_P`：L3 上有整块 `VO-L3` 岛（4 A 走平面，比走线好）。每个 `VO_P` 焊盘 + 出一小段引出脚 + 一个过孔扎进岛里。 +- `+12V`：`V12-L3` 岛在功率列上半段，够不着金手指。金手指那五根 + F1 之间 + 用底层一条 0.8 mm 的走廊连过去，两端各一个过孔。 +""" +import heapq +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ 顺序不能反：`.claude` 下有同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）， +# 先插 .claude 再插 HERE 的话，`import pcb_pour` 会拿到 R1 那一份， +# 而且**不报错**，只在调到 R2 专有的函数时才炸。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_blade as B # noqa: E402 +import fp_edge # noqa: E402 +import pcb_pour as P # noqa: E402 +import b4_edge # noqa: E402 针位表的唯一事实来源 + +PCB = B.PCB +MIL = B.MIL +PADS = os.path.join(HERE, '_blade_pads.json') + +G = 0.25 # 网格（mm） +NX = int(round(B.BW / G)) + 1 +NY = int(round(B.BH / G)) + 1 +# 布线用的净距。设计规则是 0.15；这里留一点余量给网格吸附。 +# ⚠ 0.18 -> 0.16：通道宽度 = 线宽 + 2×净距，0.2+0.36=0.56 在这块板上处处卡壳， +# 0.15+0.32=0.47 才挤得过去。仍高于规则的 0.15。 +CLR = 0.16 +STUB_CLR = 0.15 # 引出脚（缩窄段）用规则值本身，见 pad_nodes +EDGE_CLR = 0.35 # 到板边 / 缺口 +# ⚠ M6（2026-09-09）0.6/0.3 -> 0.5/0.25：细间距扇出的过孔要能塞进 0.5 mm 节距的 +# 引出脚之间（0.5 − 0.25 − 0.075 = 0.175 ≥ 0.15）。规则下限 0.3/0.2，嘉立创四层做得出。 +VIA_D, VIA_HOLE = 0.6, 0.3 # `--viafan` 那一版用过 0.5/0.25，默认仍 0.6/0.3（与缓存一致） +# 换层代价（格）。⚠ 2026-09-08 器件翻面之后这条注释反过来了： +# 现在 **73 件在底层、顶层几乎全空**，换层代价定高了等于逼所有线挤在底层。 +# 12 格 = 3 mm 还是太贵，降到 8（= 2 mm）。 +VIA_COST = 8 +# 焊盘周围的「过路费」：半径（mm）与代价（格）。见 build_grid 末尾的说明。 +PAD_PEN_R = 0.55 +PAD_PEN = 10 +LAY = (1, 2) # 只准这两层 +FINGER_KEEP_Y = 6.0 # 金手指区上沿：A* 不许进 + +# 线宽（mm）—— 和 pcb_rules.py 的规则表对齐 +# 信号线宽。⚠ 0.2 -> 0.15：这块板的信号全是逻辑 / I²C，0.15 载流绰绰有余， +# 而 0.05 的差在 0.5~0.65 mm 间距的封装周围就是「过得去」和「过不去」的分界。 +# 规则里 PWR1A 的下限就是 0.15，嘉立创四层能做到 0.09。 +W_DEFAULT = 0.15 +WIDTH = {'+12V': 0.8, '+12V_F': 0.8, 'VO': 1.5, 'VO_P': 1.5, + '+5V': 0.6, 'VBUS': 0.6, '+3V3': 0.4} +WIDTH_AUTO = {'SW': 2.0, 'VO_F': 1.5} # 自动命名网，按 pcb_rules 的探针反查 + +# ⛔ **全局最优先布的网**（跨线宽档，比宽线还先）。 +# `priority` 只在同一档宽度里排序，对「这一档整个被前面几档挤没了」无能为力； +# `FIRST_NETS` 是真的第一个布。BOOT 当初就是靠它解决的。 +# ⇒ 把**已知难布的**全放进来：难的先挑路，容易的绕着走。 +FIRST_NETS = ( + '$1N138', '$1N126', # BOOT / FB：Buck 的命门 + # ⛔ M6（2026-09-09）：这五个网的焊盘会被**自家邻脚的引出脚**封死 —— + # U2.15 被 EFUSE_EN 的孔 (89.5,31) 卡到只剩 0.04 mm、U2.17 被 $1N158 的斜线拦、 + # U2.2 被 $1N164 的孔拦；R16.1 / R8.2 四面是别的网的过孔。手工绕都绕不出来 + # （+3V3 的 y=30.75 母线加缝合孔那一排把口袋封死）。只能让它们**最先**布。 + # ⇒ 试过把它们排到最前面：这五个通了，但换来 20 处别的没通（EFUSE_EN/$1N164/ +# $1N158 的 U2 脚、KEY_VUP/VDN 的 U4 脚反过来被封死）。**不是顺序问题，是 U2/U4 +# 周围一共就那么几个出口**。默认不排前（留着这行注释别再试一遍）。 + # ⚠ M7：`KEY_PWR/VUP/VDN` 三根挨着排最前面。它们接的是 `U4`(TSSOP-24) 北排 + # **相邻的三只脚**（p4/p5/p6，0.65 mm 间距，不是 0.25 网格的整数倍）， + # 三根引出脚互相挤，谁后布谁出不来（实测「KEY_VUP: U4.5 没布通」）。 + 'KEY_PWR', 'KEY_VUP', 'KEY_VDN', + 'VBUS_EN', 'EFUSE_EN', '$1N164', 'USB_DPJ', '$1N151', 'SCL', + 'INT#', 'PRSNT#', '+3V3', 'VBUS', 'EFUSE_FLT', 'EFUSE_PG', + 'SDA', 'INA_ALERT', 'BUCK_PG', 'USB_DP', 'USB_THERM', 'EDL_EN', + '$1N147', '$1N158', '$1N173', '$1N136', +) +PLANE_VIA_NETS = ('VO_P',) # 靠 L3 的岛成网，只需要每个焊盘一个过孔 +ISLAND_NETS = ('VO_P', '+12V') # 连通性判据里不按「一整块铜」要求的网（靠 L3 岛） + +# ⛔ **Kelvin 取样**（方案 §7.2 第四条）：INA226 的两个取样脚必须用**专线**落到 +# `Rs1` 的两个焊盘上，不许「就近扎个孔进 VO_P 平面」—— +# 走平面的话，取样点变成了平面上的某一处，量到的是「分流电阻 + 一段铜箔」的压降， +# 电流读数会随铜箔温度漂，而**DRC / 连通性检查全过**，只有实测才发现。 +# 所以这两条在所有网络之前单独布，布完再让 VO_P 的平面过孔接管大电流。 +KELVIN = [(('U3', '9'), ('Rs1', '1'), 0.3), + (('U3', '10'), ('Rs1', '2'), 0.3)] +KELVIN_PADS = set() +for _a, _b, _w in KELVIN: + KELVIN_PADS.add(_a) + KELVIN_PADS.add(_b) +SKIP = ('GND',) # 地靠铜面，只单独处理 J1 的地指 +# ⛔ **不按焊盘封顶线宽**的网。默认空（刀片一直是全封顶的）。 +# 底板的七对 D± 必须保持 1.2 mm 的干线口径 —— 阻抗是按线宽算的（方案 §6.3）， +# 被 U32 那颗 0.5 mm 间距 QFN 的 0.30 焊盘封顶就等于把阻抗方案作废， +# 而 DRC / 连通性 / 几何四道判据**一条都不会响**。缩颈交给 `stub_w`（只缩引出脚）。 +NO_CAP = () + + +def call(js, timeout=300): + r = run(js, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def load_pads(): + d = json.load(io.open(PADS, encoding='utf-8')) + for p in d: + if not p[4]: + p[4] = 2.2 + if not p[5]: + p[5] = 2.2 + return d + + +# ── 网格 ────────────────────────────────────────────────────────────── +def gx(x): + return int(round(x / G)) + + +def gy(y): + return int(round(y / G)) + + +def wx(i): + return round(i * G, 4) + + +def wy(j): + return round(j * G, 4) + + +class Grid(object): + u"""两层占用图。每个格点记**一个字节的归属**：0=空闲，1..250=只被这个网占着，255=被两个以上的网占着。 + + ⛔ **第一版是「blk 位图 + own 集合」，判据写错了**： + `free()` 里「本网占过」优先于「被别人占着」，而**膨胀区也算本网占过** —— + 于是一个离本网焊盘 0.93 mm、同时**落在别人焊盘正中**的格点被判成可进， + A* 就在 `U2` 的散热焊盘上打了个过孔。自算净距 −0.300，DRC 报「过孔到焊盘」。 + 换成「归属字节」之后，只要有第二个网碰过这个格点就永久变 255，谁也进不去。 + + 两套：`blk/own` 按导线半宽膨胀，`blkv/ownv` 按过孔半径膨胀（换层判据）。 + ⚠ 只有一套的话，A* 会在「线过得去、过孔过不去」的格点上换层， + DRC 报「钻孔到焊盘」，而路径本身看着完全正常。 + """ + + def __init__(self): + self.own = {l: bytearray(NX * NY) for l in LAY} + self.ownv = {l: bytearray(NX * NY) for l in LAY} + # 「过路费」层：不封死，只是让 A* 别贴着焊盘走（见 build_grid 的 PAD_PEN） + self.pen = {l: bytearray(NX * NY) for l in LAY} + # 协商式拥塞（PathFinder）用：occ = 当前有几个网压在这一格，hist = 历史拥塞代价。 + # 两者**跨宽度档共享**（它们只跟格点有关，跟线宽无关），所以是外面挂进来的引用。 + self.occ = None + self.hist = None + self._id = {} + + def nid(self, net): + u"""网名 -> 1..250 的归属号。超出就并到 250（当成同一个「其它」，偏保守）。""" + if net is None: + net = '#' + v = self._id.get(net) + if v is None: + v = len(self._id) + 1 + # ⛔ 饱和是**静默**的：溢出之后不同的网共用一个号， + # 彼此判成「同一个网」，可以随便叠着走，而检查器之外没人会报。 + if v > 250: + raise RuntimeError(u'归属号超过 250 个（%d 个不同的网/障碍），' + u'占用图会静默失效' % v) + self._id[net] = v + return v + + def idx(self, i, j): + return j * NX + i + + def _mark(self, arr, l, x0, y0, x1, y1, k, exact=False): + # ⚠ 边界默认用 floor/ceil，不用 round：round 最坏会**少封半格（0.125 mm）**， + # 那正好是 1.5 mm 宽的两根线互相压 0.02~0.19 mm 的来源。 + # + # ⛔ 但 `exact=True`（**只给焊盘用**）必须按「格点中心落在框里才算被占」： + # floor/ceil 最坏多封**一整格 0.25 mm**，而 0.65 mm 间距的 TSSOP + # 邻脚之间本来就只剩 0.34 mm 的缝 —— 多封一格这条缝就没了， + # 于是「空板上出口数 = 0」，报「U4.5 出不来」，看着像板子太挤。 + # 焊盘框传进来时**已经膨胀了 halfw（半线宽 + 净距）**，所以 + # 「中心在框外」= 线放这儿合法，不需要再留保守量。 + # 走线 / 过孔 / 板边仍然保守 —— 那几类是沿途扫描的，少封半格会真的压上。 + if exact: + i0 = max(0, int(math.ceil(x0 / G - 1e-9))) + i1 = min(NX - 1, int(math.floor(x1 / G + 1e-9))) + j0 = max(0, int(math.ceil(y0 / G - 1e-9))) + j1 = min(NY - 1, int(math.floor(y1 / G + 1e-9))) + a = arr[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + o = base + i + v = a[o] + a[o] = k if v == 0 else (v if v == k else 255) + return + i0 = max(0, int(math.floor(x0 / G))) + i1 = min(NX - 1, int(math.ceil(x1 / G))) + j0 = max(0, int(math.floor(y0 / G))) + j1 = min(NY - 1, int(math.ceil(y1 / G))) + a = arr[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + cur = a[base + i] + if cur == 0: + a[base + i] = k + elif cur != k: + a[base + i] = 255 + + def block_rect(self, l, x0, y0, x1, y1, net=None, via=False): + self._mark(self.ownv if via else self.own, l, x0, y0, x1, y1, self.nid(net)) + + def block_both(self, l, x0, y0, x1, y1, extra, net=None, exact=False): + u"""同一个障碍，分别按导线口径和过孔口径打进两张图。""" + k = self.nid(net) + self._mark(self.own, l, x0, y0, x1, y1, k, exact) + self._mark(self.ownv, l, x0 - extra, y0 - extra, x1 + extra, y1 + extra, k, exact) + + def penalize(self, l, x0, y0, x1, y1, val): + u"""给一片格点加「过路费」（不是封死）。""" + i0 = max(0, int(math.floor(x0 / G))) + i1 = min(NX - 1, int(math.ceil(x1 / G))) + j0 = max(0, int(math.floor(y0 / G))) + j1 = min(NY - 1, int(math.ceil(y1 / G))) + a = self.pen[l] + for j in range(j0, j1 + 1): + base = j * NX + for i in range(i0, i1 + 1): + o = base + i + if a[o] < val: + a[o] = val + + def reset_pen(self): + for l in LAY: + self.pen[l] = bytearray(NX * NY) + + def cost(self, l, i, j): + o = j * NX + i + c = self.pen[l][o] + if self.occ is not None: + c += PF_PRESENT[0] * self.occ[l][o] + PF_HIST_W * self.hist[l][o] + return c + + def free(self, l, i, j, net): + if i < 0 or j < 0 or i >= NX or j >= NY: + return False + v = self.own[l][self.idx(i, j)] + return v == 0 or v == self.nid(net) + + def free_via(self, i, j, net): + u"""两层都要按过孔口径让得开，才准在这里换层。""" + if i < 0 or j < 0 or i >= NX or j >= NY: + return False + k = self.nid(net) + for l in LAY: + v = self.ownv[l][self.idx(i, j)] + if v != 0 and v != k: + return False + return True + + +def load_vias(): + u"""读回板上已有的过孔（主要是 196 个 GND 缝合过孔）。 + + ⚠ **不读的话它们就不在占用图里**，A* 会直接从过孔身上压过去 —— + DRC 报「导线到过孔」，而路径看上去完全正常。 + """ + return call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" + "return (await eda.pcb_PrimitiveVia.getAll()||[])" + " .map(v=>[v.x/%s, v.y/%s, String(v.net||''), (v.diameter||%s)/%s]);" + % (PCB, MIL, MIL, VIA_D * MIL, MIL), timeout=300) + + +def build_grid(pads, halfw, vias=()): + u"""halfw = 本次布线的「线半宽 + 净距」，障碍按它膨胀； + + 同时按过孔口径（VIA_D/2 + CLR）再膨胀一份，供换层判据用。""" + g = Grid() + extra = max(0.0, VIA_D / 2.0 + CLR - halfw) + # 板边（四条带）+ 金手指区，都归到 '#edge' 这个归属号上 + for l in LAY: + m = EDGE_CLR + halfw + for (a, b, c, d) in ((-1, -1, B.BW + 1, m), + (-1, B.BH - m, B.BW + 1, B.BH + 1), + (-1, -1, m, B.BH + 1), + (B.BW - m, -1, B.BW + 1, B.BH + 1), + (-1, -1, B.BW + 1, FINGER_KEEP_Y)): + g.block_both(l, a, b, c, d, extra, net='#edge') + # 缺口 + nx0, _a, nx1, ny1 = P.notch_cut() + for l in LAY: + g.block_both(l, nx0 - halfw, 0, nx1 + halfw, ny1 + halfw, extra) + # 焊盘 + for p in pads: + ref, num, x, y, w, h, lay, net = p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7] + if lay not in LAY: + continue + # ⛔ 只按**网**标归属，别按「网+位号+脚号」—— + # 361 个焊盘会把 250 个归属号占满，之后所有网并到同一号上， + # 互相判成「同一个网」，整块板的线就叠着走了（自算净距一次报 319 条）。 + g.block_both(lay, x - w / 2 - halfw, y - h / 2 - halfw, + x + w / 2 + halfw, y + h / 2 + halfw, extra, net=net, exact=True) + # ⛔ 排线穿板槽：铣穿的内槽，两层都不许进（还要给铜到板边的净距） + for (a, b, c2, d2) in B.mill_cuts(): + k = EDGE_CLR + halfw + for l in LAY: + g.block_both(l, a - k, b - k, c2 + k, d2 + k, extra, net='#edge') + # ⛔ 主板定位孔（NPTH）：两层都不许压。孔壁到铜按 HOLE_D/2 + 净距。 + for (hx, hy) in B.phone_holes().values(): + r = B.HOLE_D / 2.0 + halfw + 0.15 + for l in LAY: + g.block_both(l, hx - r, hy - r, hx + r, hy + r, extra) + # 已有过孔（通孔，两层都占） + for (vx, vy, vnet, vd) in vias: + r = vd / 2.0 + halfw + for l in LAY: + g.block_both(l, vx - r, vy - r, vx + r, vy + r, extra, net=vnet) + # ⛔ **焊盘周围收「过路费」**。这是 28 处接不上的真正解法： + # 把失败那一刻的占用图打出来看，每个「出不来」的脚周围**全是别的网的铜** —— + # 先布的干线贴着焊盘走，顺手把后面那些脚的出口全占了。封死不行（有些线 + # 本来就得从焊盘边过），所以改成加钱：贴着焊盘走要多花 PAD_PEN， + # A* 于是优先绕开焊盘阵，把出口留给它们自己的脚。 + pen_pads(g, pads, halfw) + return g + + +def pen_pads(g, pads, halfw): + u"""给这些焊盘周围收「过路费」（先清空再打）。""" + g.reset_pen() + for p in pads: + if p[6] not in LAY: + continue + r = PAD_PEN_R + halfw + g.penalize(p[6], p[2] - p[4] / 2 - r, p[3] - p[5] / 2 - r, + p[2] + p[4] / 2 + r, p[3] + p[5] / 2 + r, PAD_PEN) + + +def block_track(g, l, x0, y0, x1, y1, halfw, net, extra=0.0): + u"""把一段已布的线打进占用图（两张都打）。""" + steps = int(max(abs(x1 - x0), abs(y1 - y0)) / (G / 2)) + 1 + for k in range(steps + 1): + t = k / float(steps) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + g.block_both(l, x - halfw, y - halfw, x + halfw, y + halfw, extra, net=net) + + +_NB8 = [(1, 0, 1.0), (-1, 0, 1.0), (0, 1, 1.0), (0, -1, 1.0), + (1, 1, 1.414), (1, -1, 1.414), (-1, 1, 1.414), (-1, -1, 1.414)] +# 每层的**优选走线方向**：'v' = 纵向（沿 y），'h' = 横向（沿 x） +LAYER_DIR = {2: 'v', 1: 'h'} # 2 = 底层 = 器件面（纵向）；1 = 顶层（横向） +CROSS_COST = 3.0 # 逆着优选方向走的倍率（斜线按分量算） + + +def _along(l, di, dj): + u"""这一步是不是顺着本层的优选方向。斜线两个分量各占一半，算「半顺」。""" + d = LAYER_DIR.get(l) + if d is None: + return True + if di and dj: # 斜线：一半顺、一半逆 + return False + return (dj != 0) if d == 'v' else (di != 0) + + +def astar(g, starts, goals, net, halfw): + u"""8 邻接 A*，两层。starts/goals 是 [(layer, i, j)]。返回 [(layer,i,j)] 路径。""" + goalset = set(goals) + if not goalset: + return None + gj = [(l, i, j) for (l, i, j) in goals] + + def h(n): + _l, i, j = n + return min(max(abs(i - a[1]), abs(j - a[2])) + + 0.414 * min(abs(i - a[1]), abs(j - a[2])) for a in gj) + + open_ = [] + gsc = {} + came = {} + for s in starts: + if not g.free(s[0], s[1], s[2], net): + continue + gsc[s] = 0.0 + heapq.heappush(open_, (h(s), s)) + # ⛔ **两层正交**：器件面（底层 L4，73 件都在这儿）**纵向**、 + # 另一面（顶层 L1，几乎空着）**横向**。2026-09-08 用户定的， + # 和 R1「顶层横向、底层纵向」是同一条约定。 + # 做法是**加钱不是封死** —— 逆着方向走要贵 `CROSS_COST` 倍， + # 于是拐弯自然变成「换层拐」，两层互补，拥塞大幅下降； + # 但引出脚那种非横即竖走不了的地方仍然出得去。 + nb = {l: [(di, dj, c * (1.0 if _along(l, di, dj) else CROSS_COST)) + for (di, dj, c) in _NB8] for l in LAY} + seen = set() + while open_: + _f, cur = heapq.heappop(open_) + if cur in seen: + continue + seen.add(cur) + if cur in goalset: + path = [cur] + while path[-1] in came: + path.append(came[path[-1]]) + return path[::-1] + l, i, j = cur + base = gsc[cur] + for di, dj, c in nb[l]: + n = (l, i + di, j + dj) + if n in seen or not g.free(l, i + di, j + dj, net): + continue + ng = base + c + g.cost(l, i + di, j + dj) + if ng < gsc.get(n, 1e18): + gsc[n] = ng + came[n] = cur + heapq.heappush(open_, (ng + h(n), n)) + other = LAY[1] if l == LAY[0] else LAY[0] + n = (other, i, j) + if n not in seen and g.free(other, i, j, net) and g.free_via(i, j, net): + ng = base + VIA_COST + if ng < gsc.get(n, 1e18): + gsc[n] = ng + came[n] = cur + heapq.heappush(open_, (ng + h(n), n)) + return None + + +def to_segments(path): + u"""路径 -> [(layer, x0,y0, x1,y1)] + 过孔 [(x,y)]，合并共线段。""" + segs, vias = [], [] + run_start = path[0] + prev = path[0] + for cur in path[1:]: + if cur[0] != prev[0]: # 换层 + if run_start != prev: + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + vias.append((wx(prev[1]), wy(prev[2]))) + run_start = cur + prev = cur + continue + d1 = (prev[1] - run_start[1], prev[2] - run_start[2]) + d2 = (cur[1] - prev[1], cur[2] - prev[2]) + if run_start != prev and (d1[0] * d2[1] - d1[1] * d2[0] != 0 or + (d1[0] * d2[0] + d1[1] * d2[1]) <= 0): + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + run_start = prev + prev = cur + if run_start != prev: + segs.append((prev[0], wx(run_start[1]), wy(run_start[2]), + wx(prev[1]), wy(prev[2]))) + return segs, vias + + +# ── 焊盘引出脚 ──────────────────────────────────────────────────────── +def pad_rect(p, inf=0.0): + return (p[2] - p[4] / 2 - inf, p[3] - p[5] / 2 - inf, + p[2] + p[4] / 2 + inf, p[3] + p[5] / 2 + inf) + + +def seg_hits_rect(x0, y0, x1, y1, r): + u"""线段是否与矩形相交（粗判：采样）。""" + n = max(2, int(math.hypot(x1 - x0, y1 - y0) / 0.05)) + for k in range(n + 1): + t = k / float(n) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + if r[0] <= x <= r[2] and r[1] <= y <= r[3]: + return True + return False + + +def pad_nodes(g, p, halfw, others, stub_half=None, gt=None): + # ⚠ `others` 必须按 **CLR + 引出脚半宽** 膨胀过再传进来。第一版按 0.05 膨胀， + # 于是引出脚可以贴着隔壁焊盘 0.05 mm 走过去 —— DRC「贴片焊盘到导线」一次报 158 条。 + u"""这个焊盘可以起步的格点，按「离盘心近 + 引出脚不蹭别的盘」排序。""" + lay, net = p[6], p[7] + # ⛔ `others` 传进来的是**未膨胀**的焊盘框，在这里按**引出脚**的口径膨胀。 + # 用干线口径（1.5 mm 线 → 0.93）膨胀的话，隔壁焊盘的膨胀区会把 + # 0.5 mm 间距 QFN 的所有出口堵死 —— 报「出不来」，看着像拥塞， + # 其实是拿干线的宽度去量那一小段缩窄的引出脚。 + if stub_half is None: + stub_half = W_DEFAULT / 2.0 + # ⚠ 引出脚用**规则净距 0.15**，不用干线那个留了余量的 CLR=0.18。 + # 那 0.03 的余量是给 A* 干线的；最后 0.5 mm 缩窄段上再留， + # 0.35 mm 间距的连接器就一个出口都没有了。router_check 判的也是 0.15。 + inf = STUB_CLR + stub_half + # ⛔ **自身焊盘按「同一个矩形」排除，不能按「谁包住我的盘心」排除。** + # 膨胀之后，0.35 mm 间距的 `J4` 隔壁脚的框正好把本脚盘心吞进去 + # （50.01 那只脚膨胀后是 49.64~50.38，本脚盘心 49.66 在里面）， + # 于是**隔壁脚被当成自己跳过**，引出脚就贴着它走了 —— 净距 0.047， + # 而 pad_nodes 全程不报错。这一条 2026-09-08 实测踩到两次（USB_THERM / CC1）。 + own = pad_rect(p) + others = [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) for r in others + if max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + for ring in range(0, 5): # 一圈找不到就往外扩，最多 4 圈（1 mm） + out = _pad_nodes_ring(g, p, halfw + ring * G, others, lay, net, gt, stub_half) + if out: + return out + return [] + + +def _oth_inflated(p, others, stub_half): + u"""把同层焊盘框按**引出脚口径**膨胀，并剔掉本盘自己那一个（按矩形本身，不是按包住盘心）。""" + inf = STUB_CLR + stub_half + own = pad_rect(p) + return [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) for r in others + if max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + + +def _axis_exit(p, stub_half): + u"""沿焊盘**长轴**向外的两个出口点（本盘自己的「车道」，两侧没有邻盘）。""" + d = STUB_CLR + stub_half + if p[5] >= p[4]: + r = p[5] / 2.0 + d + return [(p[2], p[3] + r), (p[2], p[3] - r)] + r = p[4] / 2.0 + d + return [(p[2] + r, p[3]), (p[2] - r, p[3])] + + +def stub_path(p, X, Y, oth, stub_half, g=None, net=None): + u"""盘心 → 落点的引出脚折线；走不通返回 None。 + + ⛔ **先直线，走不通再走 L 形**：`J4`（0.35 mm 间距、盘 0.18 宽）盘心到邻盘边 + 只有 0.26 mm，任何斜着出去的引出脚都会蹭上邻盘（实测 0.047 mm）， + 于是「一个出口都找不到」。但**沿着焊盘长轴直着出去**是安全的 —— + 那是本盘自己的车道，两侧的邻盘在左右不在前后。出了盘阵再拐就没事了。 + `U1`/`U2`/`U7` 那几只内侧脚同理。 + + ⛔ **候选还要过占用图那一关**（`g` / `net`，2026-09-09 M7 补）： + 这里原来只判「蹭没蹭到别的**焊盘**」，不判过孔和已布的铜 —— + 于是 L 形的拐点可以正好贴在别人的过孔边上：实测 `U2.15`($1N147) 的引出脚 + 离 `EFUSE_EN` 的孔净距 **−0.204**、`U2.2`(EFUSE_PG) 离 `$1N164` 的孔同样， + DRC 报「导线到过孔 0 mil」四条，而 A*、线与线、引出脚自己那三关全过。 + """ + def ok(pts, strict): + for a, b in zip(pts, pts[1:]): + if any(seg_hits_rect(a[0], a[1], b[0], b[1], r) for r in oth): + return False + if strict and g is not None and not _stub_clear( + g, p[6], a[0], a[1], b[0], b[1], + net if net is not None else p[7], pad_rect(p)): + return False + return True + + cand = [[(p[2], p[3]), (X, Y)]] + for (ex, ey) in _axis_exit(p, stub_half): + cand.append([(p[2], p[3]), (ex, ey), (X, Y)]) + # ⛔ 占用图那一关只用来**排序**，不用来否决：拿它当硬条件的话， + # 「落点挑得出来（`pad_nodes` 也用 `gt`）、引出脚却发不出来」， + # 实测多报 3~4 个脚「一根铜都没有」——**丢一只脚比蹭 0.05 mm 严重得多**。 + # ⇒ 先要「既不蹭盘也不蹭孔」的；没有的话退回老判据（只不蹭盘）。 + for strict in (True, False): + for pts in cand: + if ok(pts, strict): + return pts + return None + + +def stub_emit(p, X, Y, others, stub_half, w, net, g=None): + u"""发引出脚的线段（1 段或 L 形 2 段）。判据和 `stub_path` 是同一个，不许各写一份。 + + ⚠ 宽度不能低于**规则下限**：引出脚缩窄是为了从细间距里挤出来，但 DRC 不认这个理由 + （`SWNODE` 下限 0.3，而 `U1` 的 SW 脚只有 0.279，按脚缩就报「物理错误」）。 + 比焊盘宽一点点只是稍微出头，间距还够。 + + ⚠ `g` 传进来就顺带过一遍占用图（避过孔 / 已布的铜），不传就退回「只避焊盘」。 + **真正落到板上的那一次调用一定要传**，见 `plan_all` 里的注释。 + """ + w = max(w, rule_min(net, AUTO_CACHE)) + pts = stub_path(p, X, Y, _oth_inflated(p, others, stub_half), stub_half, g, net) + if pts is None: + pts = [(p[2], p[3]), (X, Y)] + out = [] + for a, b in zip(pts, pts[1:]): + if math.hypot(b[0] - a[0], b[1] - a[1]) > 1e-6: + out.append((p[6], a[0], a[1], b[0], b[1], w, net)) + return out + + +def _stub_clear(g, lay, px, py, qx, qy, net, own=None): + u"""引出脚沿途的格点必须对本网可进。 + + ⛔ `own` = 本焊盘自己的框：**落在自己盘里的采样点要跳过**。 + 引出脚从盘心出发，而盘心那一格常常被隔壁那根线的避让区盖住 + （`U1.13` 旁边 0.5 mm 就是 2 mm 宽的 SW 直连段）—— 于是**第一个采样点** + 就判死，报「出不来」，而它左边明明整片是空的。 + 焊盘里本来就有铜，这一段不该参与净距判断。 + """ + n = max(2, int(math.hypot(qx - px, qy - py) / (G / 2.0))) + for k in range(n + 1): + t = k / float(n) + x, y = px + (qx - px) * t, py + (qy - py) * t + if own is not None and own[0] <= x <= own[2] and own[1] <= y <= own[3]: + continue + if not g.free(lay, gx(x), gy(y), net): + return False + return True + + +def _pad_nodes_ring(g, p, halfw, others, lay, net, gt=None, stub_half=0.1): + x0, y0, x1, y1 = pad_rect(p, halfw) + out = [] + for j in range(max(0, gy(y0)), min(NY - 1, gy(y1)) + 1): + for i in range(max(0, gx(x0)), min(NX - 1, gx(x1)) + 1): + if not g.free(lay, i, j, net): + continue + X, Y = wx(i), wy(j) + # ⚠ 自己的焊盘框已经在 pad_nodes 里**按矩形本身**剔掉了。 + # 直线走不通还要试 L 形（见 stub_path），否则细间距的脚全报「出不来」。 + if stub_path(p, X, Y, others, stub_half) is None: + continue + # ⛔ 引出脚还要躲**已经布好的铜**。只查焊盘的话，引出脚会从先布的 + # 导线/过孔身上压过去（自算净距报 `USB_DP` 的指脚 vs `VBUS` −0.097）。 + # ⚠ 只拿**已布的铜**那张图查，不能拿主占用图查： + # 细间距器件上相邻焊盘的膨胀区互相重叠，格点会变成 + # 255（多网占用），连自己的引出脚都进不去，整网报「出不来」。 + # 焊盘那一层已经由上面的 `others` 按引出脚口径管过了。 + if gt is not None and not _stub_clear(gt, lay, p[2], p[3], X, Y, net, + pad_rect(p)): + continue + out.append((math.hypot(X - p[2], Y - p[3]), (lay, i, j))) + out.sort() + return [n for _d, n in out] + + +def stub_w(p, width): + u"""引出脚宽度按焊盘尺寸封顶。 + + ⛔ 不封顶的话，`SWNODE` 2.0 mm 的线要接进 `U1`（0.5 mm 间距 QFN）和 `C5`（0402）， + 引出脚直接盖住隔壁两个脚 —— 自算净距 −0.73，DRC 报「贴片焊盘到导线」。 + 干线仍然是全宽（A* 的路径离别人的焊盘有 halfw 的余量），**只有最后接进焊盘 + 那一小段缩窄**，这也是手工布板的做法。 + + ⚠ 下限 **0.15，不是 0.2**：`J4`（BM24-50DS）下排 0.35 mm 间距、焊盘 0.18 宽， + 盘心到隔壁盘边只有 0.26 mm。要 0.15 的净距，引出脚半宽就得 ≤ 0.11 —— + 0.2 宽的脚（半宽 0.1 + 规则 0.15 = 0.25）**只剩 0.01 余量**， + grid 一吸附就蹭上（实测 USB_THERM 对 J4.16 只有 0.047）。 + 0.15 宽 ⇒ 0.15 + 0.075 = 0.225，余 0.035。嘉立创四层线宽下限 0.09，做得出来。 + """ + return round(max(0.15, min(width, p[4], p[5])), 3) + + +# 「已经被铜连在一起」的虚拟落点：位号是这些的，`route_net` 把它们**全部当种子** +# （多源 Prim），彼此之间不布线。目前只有底板的 `+3V3` 槽墙（方案 R2 §30）。 +PRE_WIRED = ('WALL',) + + +def _is_launch(p): + u"""扇出/金手指扇出留下的**虚拟焊盘**（落点）。""" + return str(p[1]).startswith('fan:') or p[1] in ('launch', 'wall') + + +def route_net(g, net, pads_of_net, halfw, width, others_by_layer, log, gt=None, mutate=True): + u"""对一个网络做 Prim：逐个把还没连上的焊盘接进来。 + + ⚠ **落点（虚拟焊盘）不做「引出脚别蹭邻盘」那道检查**：落点就在焊盘阵的边上， + 邻盘膨胀后的框必然把它包住，于是每个候选格点都被判死 —— 报「出不来」， + 而它明明已经是扇出阶段验证过的合法落点了。 + """ + + def _oth(p): + return [] if _is_launch(p) else others_by_layer.get(p[6], []) + segs, vias, stubs = [], [], [] + if len(pads_of_net) < 2: + return segs, vias, stubs + todo = list(pads_of_net) + # 种子挑**出口最多**的那个焊盘（最自由），不是第一个碰到的 + cand = [] + for k, p in enumerate(todo): + ns = pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt) + if ns: + cand.append((len(ns), k, ns)) + if not cand: + log.append(u'%s: 一个焊盘都出不来' % net) + return segs, vias, stubs + cand.sort(reverse=True) + _n, seed, starts = cand[0] + seedpad = todo.pop(seed) + # ⛔ **种子的引出脚必须画到 A* 真正起步的那个出口上**，不能画到 `starts[0]`。 + # 下面 `src` 放的是种子的**全部**出口（那是对的，只放一个会自锁）； + # 可引出脚只画一条 —— A* 从别的出口起步时，铜就和焊盘**断开**了， + # 而布线器只看「路找到没有」，**一个字都不会报**。 + # `KPAD_PWR` 就是这么断的：K1 的引出脚停在 (7.75,34.25)， + # 干线却从 (8.75,33.25) 起步，中间 1.4 mm 是空的。 + # ⇒ 改成**惰性**：谁真被用上了，就给谁补一条引出脚。 + seed_nodes = set(starts) + stubbed = set() + + def note_seed(node): + if node not in seed_nodes or node in stubbed: + return + stubbed.add(node) + stubs.append((seedpad, node, stub_w(seedpad, width))) + if mutate: + for (_l, ax, ay, bx, by, sw, _n) in stub_emit( + seedpad, wx(node[1]), wy(node[2]), _oth(seedpad), + stub_w(seedpad, width) / 2.0, stub_w(seedpad, width), net): + block_track(g, seedpad[6], ax, ay, bx, by, halfw + sw / 2.0, net) + # ⛔ 种子集合要放**全部出口**，不能只放第一个。 + # 只放一个的话，后面每个焊盘都得 A* 到那一个格点；它一旦被先布的线围住， + # 整个网就全线报「没布通」（`+3V3` 14 个脚里 11 个失败就是这么来的）， + # 而看上去像是板子太挤。 + src = set(starts) + # ⛔ **多源种子**：`PRE_WIRED` 的落点落在**同一块已经存在的铜**上（3V3 槽墙那种）， + # 它们彼此之间不需要一根线。全部一次性进 `src` 并从 `todo` 里摘掉。 + # 不这么做的话，Prim 会把「落点」当普通节点，逼 A* 在铜上再布一条线把它们串起来 + # —— 实测 `+3V3` 因此从最北那个落点一路蜿蜒到板子最南（100 mm，横穿五条走廊， + # 正好压在 I²C 的出脚道上），而**布线器只报「布通了」**。 + # ⇒ 一只脚就近接到墙上，这才是「铜墙」的本意。 + for p in list(todo): + if p[0] in PRE_WIRED: + for n in pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt): + src.add(n) + todo.remove(p) + todo.sort(key=lambda q: math.hypot(q[2] - seedpad[2], q[3] - seedpad[3])) + done, fail = set(), {} + # 走两遍：第二遍时 src 已经长大，第一遍够不着的往往就通了 + for p in todo + [q for q in todo]: + if id(p) in done: + continue + goals = pad_nodes(g, p, halfw, _oth(p), stub_w(p, width) / 2.0, gt) + if not goals: + fail[id(p)] = u'%s: %s.%s 出不来' % (net, p[0], p[1]) + continue + path = astar(g, list(src), goals[:24], net, halfw) + if not path: + fail[id(p)] = u'%s: %s.%s 没布通' % (net, p[0], p[1]) + continue + s, v = to_segments(path) + note_seed(path[0]) # 这条路真正用的是哪个种子出口 + segs += [(l, a, b, c, d, width, net) for (l, a, b, c, d) in s] + vias += [(x, y, net) for (x, y) in v] + stubs.append((p, path[-1], stub_w(p, width))) + # ⚠ 回填占用图要按 **halfw + 本线半宽**，不能只按 halfw： + # halfw 已经含了「后来那根线的半宽 + 净距」，但**这根线自己也有宽度**。 + # 只按 halfw 填的话，同一档宽度里两根 1.5 mm 的线会被排到中心距 1.5， + # 实际净距 0 —— DRC 一口气报出 598 条，全是宽线互相压。 + keep = halfw + width / 2.0 + done.add(id(p)) + for n in path: + src.add(n) + if mutate: + g.block_rect(n[0], wx(n[1]) - keep, wy(n[2]) - keep, + wx(n[1]) + keep, wy(n[2]) + keep, net=net) + for (l, a, b, c, d) in s: + if mutate: + block_track(g, l, a, b, c, d, keep, net, + extra=max(0.0, VIA_D / 2.0 + CLR - keep)) + if gt is not None: + block_track(gt, l, a, b, c, d, CLR + W_DEFAULT / 2.0 + width / 2.0, net) + for (vx, vy) in v: # 自己刚打的过孔 + # ⛔ 净距那一项不能漏：`VIA_D/2 + halfw` 只保证「铜刚好挨上」， + # 后布的线就能贴到过孔边（DRC：导线到过孔 0 mil，实测 12 条）。 + r = VIA_D / 2.0 + CLR + halfw + if mutate: + for l2 in LAY: + g.block_both(l2, vx - r, vy - r, vx + r, vy + r, + max(0.0, VIA_D / 2.0 + CLR - halfw), net=net) + # ⛔ **刚打的过孔也要进 `gt`（引出脚校验图）**。`gt` 是每一轮开头建一次的， + # 只含开轮时已有的过孔 —— 同一轮里先布的网打的孔，对后布的网的引出脚 + # 就是隐形的。实测两处：`U2.15`($1N147) 的引出脚贴到 `EFUSE_EN` 的孔上 + # （净距 −0.204），`U2.2`(EFUSE_PG) 贴到 `$1N164` 的孔上。 + # 线与线、A* 那几关全过，只有 DRC 的「导线到过孔」报得出来。 + if gt is not None: + rt = VIA_D / 2.0 + CLR + W_DEFAULT / 2.0 + for l2 in LAY: + gt.block_rect(l2, vx - rt, vy - rt, vx + rt, vy + rt, net=net) + # 引出脚（盘心 -> 第一个格点，可能是 L 形）也要占位， + # 否则后面的线会从它身上压过去 + if mutate: + for (_l, ax, ay, bx, by, sw, _n) in stub_emit( + p, wx(path[-1][1]), wy(path[-1][2]), _oth(p), + stub_w(p, width) / 2.0, stub_w(p, width), net, g): + block_track(g, p[6], ax, ay, bx, by, halfw + sw / 2.0, net) + # ⛔ **失败必须往外报**。这个 `fail` 字典以前收完就扔了 —— 于是 + # 「某个脚没布通」全程静默：网上只剩一小段引出脚（`BUCK_PG` 0.02 mm）， + # 脚本打印「0 条没搞定」，`getNetLength()` 也非 0（有那一小段）， + # 只有 EasyEDA 的连接性 DRC 会报，而那一支平时被当成「还没布线」忽略掉。 + # 2026-09-08 就是这么漏掉 20 多个连接的。 + for p in todo: + if id(p) in done: + continue + log.append(fail.get(id(p), u'%s: %s.%s 没接上' % (net, p[0], p[1]))) + return segs, vias, stubs + + +# ── J1 金手指扇出（不走 A*，几何是确定的）─────────────────────────────── +BUS_Y = {1: 7.0, 2: 8.2} # 顶层地母线 / 底层地母线（错开，过孔互不挡） +LAUNCH_Y = 11.75 # 信号指爬到这一行，交给 A*（要落在 0.25 网格上） +STUB_Y0 = 4.0 # 引出脚从指的中段起（压在焊盘上） +BUS_W, STUB_W = 0.4, 0.2 +FINGER_W = {'+12V': 0.35, '+5V': 0.3} + + +def finger_geom(): + u"""返回 (pin -> (x, layer, net))。x 直接用封装的事实来源。""" + out = {} + # ⚠ 针位表在 `b4_edge.PIN_NET`（原理图那一份），几何在 `fp_edge`（封装那一份）。 + # 两份各是各的事实来源，**不许在这里抄第三份**。 + for pin, net in b4_edge.PIN_NET.items(): + row = pin[0] + out[pin] = (round(B.J1_X + fp_edge.PIN_X[pin], 4), fp_edge.LAYER[row], net) + return out + + +def gnd_runs(fg): + u"""每一排里连续的地指分段。""" + runs = {} + for row, lay in (('A', 2), ('B', 1)): + cur = [] + for n in range(1, 33): + pin = '%s%d' % (row, n) + if fg[pin][2] == 'GND': + cur.append(pin) + else: + if cur: + runs.setdefault(lay, []).append(cur) + cur = [] + if cur: + runs.setdefault(lay, []).append(cur) + return runs + + +def finger_escape(): + u"""地指走母线 + 过孔；信号指直上到 LAUNCH_Y。 + + ⚠ **过孔只能打在「另一排同 x 是地或悬空」的位置**：过孔是通孔， + 打在信号指正上方会把另一层那根信号的引出脚堵死。 + 这一条不写进代码的话，`B14/B15`（USB D±）和 `A16`（VDAC）会被地过孔挡住， + 而 DRC 只会报「这根线没布通」，指不到根因。 + """ + fg = finger_geom() + other = {} + for n in range(1, 33): + other['A%d' % n] = fg['B%d' % n][2] + other['B%d' % n] = fg['A%d' % n][2] + segs, vias, launch = [], [], {} + # 地指 + for lay, runs in sorted(gnd_runs(fg).items()): + y = BUS_Y[lay] + for run in runs: + xs = [fg[p][0] for p in run] + x0, x1 = min(xs), max(xs) + ok = [fg[p][0] for p in run if other[p] in ('GND', 'NC')] + if not ok: # 整段都被对排的信号占着 -> 母线往外伸 1 mm + x1 = x1 + 1.0 + ok = [x1] + segs.append((lay, x0, y, x1, y, BUS_W, 'GND')) + for p in run: + segs.append((lay, fg[p][0], STUB_Y0, fg[p][0], y, STUB_W, 'GND')) + for k, vx in enumerate(ok): + if k % 2 == 0 or len(ok) <= 2: # 每隔一根打一个，够用 + vias.append((vx, y, 'GND')) + # 信号指：爬到 LAUNCH_Y 之后**立刻换到空的那一面**。 + # ⛔ M5 时代这句是「换到**底层**」，理由是「83 件全在 A 面，底层是空的」—— + # **M6 把 83 件全翻到了 B 面（底层）之后这句就反了**，而注释没跟着改： + # 于是 19 根金手指信号全被灌进器件面，跟 78 个件的焊盘抢那几条通道， + # A* 布不出来就退化成「直连段」——直接一条铜横穿金手指区， + # 压在 16 根地指的引出脚上（DRC：`PRSNT#` 到 `GND` 净距 0，16 条）。 + # ⚠ **试过反过来（换到顶层）：更差**，20 条没搞定（原来 6 条）—— + # 78 个件的焊盘全在底层，信号换到顶层之后每根线都要再换回来， + # 每根多两个过孔，扇出区先堵死。⇒ 仍然换到底层， + # `PRSNT#` 那条横穿金手指区的铜另找原因（它是 A* 失败后的退化直连）。 + # ⚠ 例外：同一个 x 上 A/B 两排都是**不同网的信号**时不能换 —— + # 通孔会把另一排那根线在底层的去路堵死。这样的位置只有两个 + # （1 号针 A1=PRSNT# / B1=+12V，11 号针 A11=EFUSE_EN / B11=INT#）， + # 让 B 排那根留在顶层，交给 A* 自己想办法。 + sig = lambda n: n not in ('GND', 'NC') + for pin, (x, lay, net) in sorted(fg.items()): + if not sig(net): + continue + w = FINGER_W.get(net, STUB_W) + segs.append((lay, x, STUB_Y0, x, LAUNCH_Y, w, net)) + onet = other[pin] + clash = sig(onet) and onet != net + if lay == 1 and not clash: + vias.append((x, LAUNCH_Y, net)) + launch.setdefault(net, []).append((2, x, LAUNCH_Y)) + else: + launch.setdefault(net, []).append((lay, x, LAUNCH_Y)) + return segs, vias, launch + + +# ── 主流程 ──────────────────────────────────────────────────────────── +def rule_width(net, auto): + if net in WIDTH: + return WIDTH[net] + for k, n in auto.items(): + if n == net: + return WIDTH_AUTO.get(k, W_DEFAULT) + return W_DEFAULT + + +# 各线宽规则的**下限**（和 pcb_rules.TRACK_RULES 的 strokeWidthMin 对齐）。 +# ⛔ 低于下限 DRC 报「物理错误：线宽 x mil，应该在 y ~ z」—— 直连段按焊盘取宽 +# （`U1` 的 SW 脚只有 0.279）和过孔合并的连接段（固定 0.2）都会踩到。 +RULE_MIN = {'PWR12V': 0.25, 'SWNODE': 0.30, 'PWR4A': 0.30, + 'PWR5V': 0.20, 'PWR1A': 0.15} + + +def rule_min(net, auto): + u"""这个网的线宽下限。查不到就按默认 0.15。""" + import pcb_rules as R + cls = R.NET_TRACK.get(net) + if cls is None: + for name, (c, probe, chk) in R.AUTO_TRACK.items(): + if auto.get(name) == net: + cls = c + break + return RULE_MIN.get(cls, 0.15) + + +def width_of(net, auto, pads_of_net=()): + u"""线宽 = 规则宽度，但**被这个网最小的焊盘封顶**。 + + ⛔ 不封顶的后果不是「线太粗」，是**根本出不来**：找出口那张占用图是按干线宽度 + 建的，1.5 mm 的网去接 `U2`（0.5 mm 间距 WQFN，焊盘 0.3×0.9）时， + 隔壁焊盘按 0.93 mm 膨胀，把所有出口全堵死 —— 报的是「出不来」不是「没布通」， + 一眼看上去像拥塞，其实是自己把自己关在焊盘里了。 + + 这块板上这么封顶不损失载流：几个宽网要么本身就是**多脚并联的短连接** + （`$1N165` 是 eFuse 五个 OUT 脚 → `Rs1`，每脚 0.8 A，跨度 4 mm）， + 要么走的是 L3 的铜面（`VO_P` / `+12V`）。 + """ + # ⚠ 2026-09-08：**撤掉了按焊盘封顶**。那是绕开「出不来」的权宜之计， + # 代价是把 4 A 的 `SWNODE`/`PWR4A` 干路压到 0.48 mm（外层 1 oz 只带 ~2.2 A）， + # 拿载流换布通率，不能这么换。真正的根因在 `pad_nodes` 的 `others` 膨胀口径， + # 已经修好；干线保持规则宽度，只有**引出脚**按焊盘缩窄（`stub_w`）。 + return rule_width(net, auto) + + +def route_groups(bypad, pads, segs, vias, board_vias, auto, priority=(), only=None): + u"""按线宽分档把 `bypad` 里的网布完；`only` 给拆线重布用（只重布这几个网）。 + + 直接**原地**往 `segs` / `vias` 里追加，返回没搞定的日志。 + """ + logs = [] + # 其余按线宽分档，宽的先布 + groups = {} + capped = [] + for net, ps in bypad.items(): + if only is not None and net not in only: + continue + w = width_of(net, auto, ps) + # ⚠ 直连之后**才**按焊盘封顶：4 A 的干线已经由直连段承担（宽度=焊盘本身， + # IC 的脚有多宽就有多宽，再宽也没意义），剩下要 A* 的都是小脚上的支路 + # （BOOT 电容、FB 抽头）。不封顶的话，2 mm 的口径在 0.5 mm 间距的 + # QFN 上一个出口都找不到 —— 报「出不来」，看着像拥塞。 + small = w if net in NO_CAP else min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [w]) + # ⚠ 封顶不能低于**规则下限**，否则 DRC 报「物理错误：线宽不足」。 + # `SWNODE` 下限 0.3，而 `U1` 的 SW 脚只有 0.279 —— 按脚封顶就踩线了。 + w = max(W_DEFAULT, rule_min(net, auto), min(w, small)) + if w < rule_width(net, auto) - 1e-9: + capped.append(u'%s %.2f→%.2f' % (net, rule_width(net, auto), w)) + groups.setdefault(w, []).append(net) + if capped: + print(u'线宽被焊盘封顶: ' + ' '.join(capped)) + for w in sorted(groups, reverse=True): + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + # ⚠ 已布的铜要**按它自己的网名**打进占用图，不能统一记成 '#done'： + # 记成 '#done' 的话，一个网自己的金手指引出脚会把自己的落脚点堵死， + # 现象是「J1.launch 出不来」——，而且看上去像是拥塞，其实是自锁。 + for (l, a, b, c, d, ww, nn) in segs: # 已布的铜 + # ⛔ `extra` 不能用默认的 0：`block_both` 的第二张图（`ownv`）是**换层判据**， + # 不给额外膨胀的话，别人的过孔可以直接落在这根线上 —— + # DRC 报「导线到过孔 0 mil」，实测两处（`EFUSE_EN` 的孔压 `$1N147`、 + # `$1N164` 的孔压 `EFUSE_PG`），而线与线那一支干干净净，很难看出来是谁的错。 + block_track(g, l, a, b, c, d, halfw + ww / 2.0, nn, + extra=max(0.0, VIA_D / 2.0 + CLR - (halfw + ww / 2.0))) + for (vx, vy, nn) in vias: + # ⛔ 同上：少了 `CLR` 的话，后布的线会贴着别人的过孔走。 + rv = VIA_D / 2.0 + CLR + halfw + for l in LAY: + g.block_rect(l, vx - rv, vy - rv, vx + rv, vy + rv, net=nn) + # 只装已布铜的占用图，供引出脚校验用（按引出脚口径 + 那根线自己的半宽膨胀） + gt = Grid() + stub_half = W_DEFAULT / 2.0 + for (l, a, b, c, d, ww, nn) in segs: + block_track(gt, l, a, b, c, d, CLR + stub_half + ww / 2.0, nn) + for (vx, vy, nn) in vias: + r = VIA_D / 2.0 + CLR + stub_half + for l in LAY: + gt.block_rect(l, vx - r, vy - r, vx + r, vy + r, net=nn) + others = {1: [], 2: []} + for p in pads: + if p[6] in others: + others[p[6]].append(pad_rect(p)) + # 跨度大的先布：短线随便绕，长线一旦被占住走廊就真的没路了 + def span(n): + ps = bypad[n] + return -(max(q[2] for q in ps) - min(q[2] for q in ps) + + max(q[3] for q in ps) - min(q[3] for q in ps)) + + # ⛔ 但**排在跨度前面的是「引出脚有多少条路」**。 + # 只按跨度排，细间距 IC 的**内侧引脚**必然吃亏：邻脚是长线、先布， + # 两边一占，内侧那只脚就再也出不来了。实测现象是 + # 「INA_ALERT: 一个焊盘都出不来」（U4 TSSOP-24 底排第 15 脚 + U3 MSOP-10 第 3 脚）， + # 看着像拥塞，其实是**顺序**问题 —— 同样的摆位，先布它就通。 + # 判据用「在这一档刚建好的占用图上，这个网最紧的那只脚有几个可起步格点」， + # 少的先布。空 = 0，直接排最前面。 + def escapes(n): + m = 99 + for q in bypad[n]: + if q[0] == 'J1': + continue + m = min(m, len(pad_nodes(g, q, halfw, others.get(q[6], []), + w / 2.0, gt))) + return m + seq = sorted(groups[w], + key=lambda n: (0 if n in priority else 1, + escapes(n), span(n), n)) + # ⛔ **过路费只对「还没布的脚」收**。静态收费（所有焊盘一视同仁）已经把 + # 28 条降到 16 条；但布完的网还继续收费，等于白白把已经用不着的出口 + # 也围起来，后面的线被迫绕远、反而去挤别人的出口。 + # 改成每布一个网之前重算一次：**只围还没轮到的那些脚**。 + todo_nets = list(seq) + [n for ww2 in groups if ww2 != w for n in groups[ww2]] + for k, net in enumerate(seq): + left = set(todo_nets[k:]) + pen_pads(g, [q for nn in left for q in bypad.get(nn, []) + if q[0] != 'J1'], halfw) + s, v, st = route_net(g, net, bypad[net], halfw, w, others, logs, gt) + segs += s + vias += v + for (q, node, ww) in st: + # ⚠ 这里发的才是**真正落到板上的**引出脚（上面那两处只是往占用图里占位）。 + # `g` 一定要传：不传就退回「只避焊盘」的老判据， + # L 形拐点会贴到别人的过孔上（见 stub_path 的说明）。 + # ⚠ 传的是 `gt`（引出脚口径的占用图）不是 `g`（干线口径）： + # `pad_nodes` 挑落点时用的就是 `gt`，两边判据必须**同一张图** —— + # 用 `g` 更严，会出现「落点挑得出来、引出脚发不出来」， + # 实测多报 4 个脚「一根铜都没有」（U2.2 / U2.15 / U2.20 / C9.1）。 + segs += stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net, gt) + return logs + + +# 拆线半径（mm）。⚠ 2.5 太小：实测挡住失败焊盘的网**不都在它旁边** —— +# 空占用图上这些脚全都出得来，一旦别的网从三五毫米外压过来就出不来了。 +RIP_R = 6.0 +RIP_MAX = 15 # 一次最多拆几个网 +RIP_ROUNDS = 4 + + +def _seg_pt_dist(sg, x, y): + return _pt_seg(x, y, sg[1], sg[2], sg[3], sg[4]) + + +def _pt_seg(px, py, ax, ay, bx, by): + dx, dy = bx - ax, by - ay + L = dx * dx + dy * dy + t = 0.0 if L == 0 else max(0.0, min(1.0, ((px - ax) * dx + (py - ay) * dy) / L)) + return math.hypot(px - (ax + t * dx), py - (ay + t * dy)) + + +def _msg_net(m): + u"""从日志里取网名。⚠ 连通性那几条带 `[连通性] ` 前缀，不剥掉的话 + 优先队列里塞的是「[连通性] +12V_F」这种鬼名字，等于**这些网从来没被重试过**。""" + if m.startswith(u'[连通性] '): + m = m[len(u'[连通性] '):] + return m.split(':', 1)[0].strip() + + +def repair(bypad, pads, segs, vias, logs, board_vias, auto, fixed_s=0, fixed_v=0): + u"""**拆线重布**：把挡在失败焊盘出口附近的几个网拆掉，先布失败的那个，再把拆掉的补回去。 + + ⛔ 到这一步为止试过的所有招（顺序、扇出、过路费、L 形引出脚、正交方向）都 + 只能把失败数从 42 压到 13 —— 因为**剩下的全是「轮到它时出口已经被占了」**， + 而这个布线器没有回退。把占位的那几根拆掉重来，是唯一还剩的办法。 + + 判据是**总数变少才接受**：重布之后如果失败反而更多，整批回滚。 + """ + padmap = {} + for q in pads: + padmap[(q[0], str(q[1]))] = q + for rnd in range(RIP_ROUNDS): + if not logs: + break + before = len(logs) + for msg in list(logs): + if msg not in logs: + continue + net = _msg_net(msg) + if net not in bypad: + continue + q = None + try: + ref_pin = msg.split(':', 1)[1].strip().split()[0] + q = padmap.get(tuple(ref_pin.split('.'))) + except Exception: + q = None + if q is None: + # 「铜分成 N 块」这种没指名焊盘：拿这个网自己的焊盘当中心 + cand2 = [x for x in bypad[net] if x[0] != 'J1'] + if not cand2: + continue + q = cand2[0] + near = {} + for sg in segs: + if sg[6] == net or sg[6] in SKIP or sg[6] not in bypad: + continue + d = _seg_pt_dist(sg, q[2], q[3]) + if d < RIP_R: + near[sg[6]] = min(near.get(sg[6], 99), d) + victims = [n for _d, n in sorted((d, n) for n, d in near.items())][:RIP_MAX] + if not victims: + continue + redo = set(victims) | {net} + # ⛔ **前 fixed_s / fixed_v 条是前置阶段（Kelvin / VO_P 过孔 / 直连）的铜， + # 一根都不许拆** —— `route_groups` 只跑 A*，拆了它**重建不回来**， + # 而且拆掉的那些焊盘早已从 `bypad` 里摘掉了，于是**失败计数看不出来**： + # 板子断了，脚本还报「好了」。`$1N138` 只剩一段 0.06 mm 的残桩就是这么来的。 + keep_s = segs[:fixed_s] + [sg for sg in segs[fixed_s:] if sg[6] not in redo] + keep_v = vias[:fixed_v] + [v for v in vias[fixed_v:] if v[2] not in redo] + keep_logs = [m for m in logs if _msg_net(m) not in redo] + ns, nv = list(keep_s), list(keep_v) + new_logs = route_groups(bypad, pads, ns, nv, board_vias, auto, + priority=(net,), only=redo) + # ⚠ 重布完要**按几何**再查一遍：A* 说「布通了」不等于铜真的连上 + # （见 route_net 里种子引出脚那条注释）。 + for m2 in check_connected(pads, ns, nv): + if _msg_net(m2) in redo: + new_logs.append(u'[连通性] ' + m2) + # ⚠ **打平也接受**：不接受打平就会一直卡在同一个平台上 + # （12~16 来回跳）。换一组同样多的失败出来，下一轮就可能解开。 + if len(keep_logs) + len(new_logs) <= len(logs): + segs[:] = ns + vias[:] = nv + logs[:] = keep_logs + new_logs + print(u' 拆线重布第 %d 轮：%d -> %d' % (rnd + 1, before, len(logs))) + if len(logs) >= before: + break + return segs, vias, logs + + +def check_connected(pads, segs, vias): + u"""**真正的连通性判据**：按几何做并查集，看每个网的焊盘是不是真的连成一片。 + + ⛔ 为什么非要有：布线器报「0 条没搞定」只说明**它自己**觉得布完了。 + 拆线重布一旦把前置阶段的铜（直连 / Kelvin / VO_P 过孔）删掉， + 那些焊盘早就不在 `bypad` 里，于是**没人再检查它们** —— 板子断了、脚本报好。 + 这里不看布线器的账本，只看铜。 + """ + par = {} + + def find(a): + while par.get(a, a) != a: + par[a] = par.get(par[a], par[a]) + a = par[a] + return a + + def uni(a, b): + ra, rb = find(a), find(b) + if ra != rb: + par[ra] = rb + + def key(l, x, y): + return (l, round(x, 2), round(y, 2)) + + for sg in segs: + l, x0, y0, x1, y1 = sg[0], sg[1], sg[2], sg[3], sg[4] + par.setdefault(key(l, x0, y0), key(l, x0, y0)) + par.setdefault(key(l, x1, y1), key(l, x1, y1)) + uni(key(l, x0, y0), key(l, x1, y1)) + for (vx, vy, _n) in vias: + a1, b1 = key(LAY[0], vx, vy), key(LAY[1], vx, vy) + par.setdefault(a1, a1) + par.setdefault(b1, b1) + uni(a1, b1) + # 焊盘：盘框内的所有端点并到一起 + bad = [] + bynet = {} + for q in pads: + bynet.setdefault(q[7], []).append(q) + ends = {} + for k in list(par): + ends.setdefault(k[0], []).append(k) + for net, ps in bynet.items(): + if not net or net in SKIP: + continue + roots, naked = [], [] + for q in ps: + if q[0] == 'J1': # 金手指自己有扇出，另算 + continue + r = pad_rect(q, 0.05) + hit = [k for k in ends.get(q[6], []) + if r[0] <= k[1] <= r[2] and r[1] <= k[2] <= r[3]] + if not hit: + naked.append('%s.%s' % (q[0], q[1])) + continue + for h2 in hit[1:]: + uni(hit[0], h2) + roots.append(find(hit[0])) + if naked: + bad.append(u'%s: %s 一根铜都没有' % (net, ' '.join(naked[:4]))) + elif len(set(roots)) > 1 and net not in ISLAND_NETS: + # ⚠ `VO_P` / `+12V` 靠 L3 的整块铜岛成网（每个焊盘扎一个过孔进去）， + # 铜在几何上**本来就是分开的几块**，不是断线。 + bad.append(u'%s: 铜分成 %d 块' % (net, len(set(roots)))) + return bad + + +def plan_all(priority=()): + u"""`priority` 里的网络在同一档宽度里**排最前面** —— 给失败重试用。""" + import pcb_rules as R + auto = R.resolve_auto() + pads = load_pads() + board_vias = load_vias() + print(u'板上已有过孔 %d 个' % len(board_vias)) + fsegs, fvias, launch = finger_escape() + + segs = list(fsegs) + vias = list(fvias) + logs = [] + + # J1 的焊盘不再参与 A*（已经爬到 LAUNCH_Y），改成「虚拟焊盘」 + bypad = {} + for p in pads: + if p[0] == 'J1': + continue + if not p[7] or p[7] in SKIP: + continue + bypad.setdefault(p[7], []).append(p) + for net, pts in launch.items(): + for (lay, x, y) in pts: + bypad.setdefault(net, []).append(['J1', 'launch', x, y, 0.3, 0.3, lay, net, 'RECT']) + + # ── Kelvin 专线（必须在所有别的线之前）── + halfk = 0.3 / 2.0 + CLR + gk = build_grid(pads, halfk, board_vias) + for (l, a, b, c, d, ww, nn) in segs: + block_track(gk, l, a, b, c, d, halfk + ww / 2.0, nn) + padmap = {(q[0], q[1]): q for q in pads} + othersk = {1: [pad_rect(q) for q in pads if q[6] == 1], + 2: [pad_rect(q) for q in pads if q[6] == 2]} + for (aa, bb, w) in KELVIN: + pa, pb = padmap.get(aa), padmap.get(bb) + if not pa or not pb: + logs.append(u'Kelvin: 找不到 %s / %s' % (aa, bb)) + continue + na = pad_nodes(gk, pa, halfk, othersk.get(pa[6], []), w / 2.0) + nb = pad_nodes(gk, pb, halfk, othersk.get(pb[6], []), w / 2.0) + path = astar(gk, na[:12], nb[:12], pa[7], halfk) + if not path: + logs.append(u'Kelvin: %s.%s -> %s.%s 没布通' % (aa + bb)) + continue + sg, vv = to_segments(path) + segs += [(l, x0, y0, x1, y1, w, pa[7]) for (l, x0, y0, x1, y1) in sg] + vias += [(x, y, pa[7]) for (x, y) in vv] + segs += stub_emit(pa, wx(path[0][1]), wy(path[0][2]), + othersk.get(pa[6], []), w / 2.0, w, pa[7]) + segs += stub_emit(pb, wx(path[-1][1]), wy(path[-1][2]), + othersk.get(pb[6], []), w / 2.0, w, pb[7]) + + # ⚠ Kelvin 那两条已经把 `U3.9/10` 接到 `Rs1` 上了，**要把 U3 那两只脚从 + # bypad 里摘掉** —— 不摘的话 A* 会再去接一遍（`$1N165: U3.10 出不来`）， + # 而它本来就已经连上了。 + for (aa, _bb, _w) in KELVIN: + for net in list(bypad): + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) != aa] + + # VO_P：靠 L3 的岛，每个焊盘扎一个过孔就够（4 A 走平面，比走线好）。 + # ⚠ **过孔位置必须过占用图**：第一版是「往右 0.9 mm 找个点就打」， + # 于是 `U3.8`（0.5 mm 间距的 MSOP-10）的 1.5 mm 引出脚直接压住隔壁两个脚， + # DRC 一口气报 400 条「导线到导线 0 mil」。判据换成 pad_nodes + 岛的范围。 + halfv = VIA_D / 2.0 + CLR + gv = build_grid(pads, halfv, board_vias) + for (l, a, b, c, d, ww, nn) in segs: + block_track(gv, l, a, b, c, d, halfv + ww / 2.0, nn) + othersv = {1: [pad_rect(q) for q in pads if q[6] == 1], + 2: [pad_rect(q) for q in pads if q[6] == 2]} + isls = (P.VO_ISLAND, P.VO_LOBE) # M6：岛是 L 形，两块矩形任一块里都能落孔 + vo = [q for q in bypad.pop('VO_P', []) if (q[0], q[1]) not in KELVIN_PADS] + for p in vo: + if p[0] == 'J1': + continue + # ⚠ 下限是 **0.3 = PWR4A 规则的最小线宽**，不是 0.25。 + # `U3` 的 8/9 脚（VBUS 采样 / IN+）只有 0.28 宽，按焊盘缩到 0.28 就 + # 低于规则下限，DRC 报「物理错误：线宽 11mil，应该 >= 11.8mil」。 + # 0.3 的线接 0.28 的盘只是稍微出头，间距还剩 0.36-0.30=0.06，是够的。 + w = min(WIDTH['VO_P'], max(0.30, min(p[4], p[5]))) + # ⚠ 落的是**通孔**，两层都要让得开 —— 只查自己那一层的话会撞上另一面的焊盘 + # （实测 VO_P 的孔压在顶层 `C60` 的 GND 盘上，净距 0.125，DRC 报「焊盘到过孔」）。 + cand = [n for n in pad_nodes(gv, p, halfv, othersv.get(p[6], []), w / 2.0) + if any(isl[0] + 0.6 < wx(n[1]) < isl[2] - 0.6 + and isl[1] + 0.6 < wy(n[2]) < isl[3] - 0.6 for isl in isls) + and gv.free_via(n[1], n[2], 'VO_P')] + if not cand: + logs.append(u'VO_P: %s.%s 找不到落过孔的地方' % (p[0], p[1])) + continue + n = cand[0] + vx, vy = wx(n[1]), wy(n[2]) + segs += stub_emit(p, vx, vy, othersv.get(p[6], []), w / 2.0, w, 'VO_P') + vias.append((vx, vy, 'VO_P')) + keep = halfv + w / 2.0 + block_track(gv, p[6], p[2], p[3], vx, vy, keep, 'VO_P') + for l in LAY: + gv.block_rect(l, vx - keep, vy - keep, vx + keep, vy + keep, net='VO_P') + board_vias.append([vx, vy, 'VO_P', VIA_D]) + + # ── 直连：**焊盘对焊盘、中间没别人**的短连接，不走 A* ──────────────── + AUTO_CACHE.clear() + AUTO_CACHE.update(auto) + dsegs, merged = direct_links(pads, bypad, segs, vias) + segs += dsegs + if dsegs: + print(u'直连 %d 段（焊盘贴焊盘，A* 的干线口径进不去）' % len(dsegs)) + for net, groups in merged.items(): + drop = set() + for gset in groups: + drop |= set(list(gset)[1:]) # 每一簇只留一个代表 + bypad[net] = [q for q in bypad[net] if (q[0], q[1]) not in drop] + + # ── 过孔扇出（M6，`--viafan`）：细间距 IC 每只信号脚先打一个过孔上顶层 ── + if '--viafan' in sys.argv: + fs, fv, fl = via_fanout(pads, bypad, segs, vias, auto) + segs += fs + vias += fv + n_fan = 0 + for net, items in fl.items(): + for (q, vx, vy) in items: + bypad[net] = [o for o in bypad[net] if o is not q] + bypad[net].append([q[0], 'fan:%s' % q[1], vx, vy, 0.3, 0.3, 1, net, 'RECT']) + n_fan += 1 + print(u'过孔扇出 %d 只脚（%s），落点全在顶层' % (n_fan, ' '.join(FANOUT_REFS))) + + # ── 关键网络优先：在**所有**别的网之前布 ──────────────────────────── + # ⛔ `$1N126`(FB) 和 `$1N138`(BOOT) 是 Buck 的命门：少了 BOOT 高侧管不开， + # 少了 FB 环路不闭合。它们都在 `U1` 最挤的那一圈上，按线宽分档的话排在 + # 最后一档、又被别的网占完出口 —— 所以给它们一条绝对优先的通道。 + for net in FIRST_NETS: + if net not in bypad or not bypad[net]: + continue + ps = bypad[net] + w = max(W_DEFAULT, rule_min(net, auto), + min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [W_DEFAULT])) + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a1, b1, c1, d1, ww, nn) in segs: + block_track(g, l, a1, b1, c1, d1, halfw + ww / 2.0, nn) + gt = Grid() + for (l, a1, b1, c1, d1, ww, nn) in segs: + block_track(gt, l, a1, b1, c1, d1, CLR + W_DEFAULT / 2.0 + ww / 2.0, nn) + others = {1: [], 2: []} + for q in pads: + if q[6] in others: + others[q[6]].append(pad_rect(q)) + s2, v2, st2 = route_net(g, net, ps, halfw, w, others, logs, gt) + segs += s2 + vias += v2 + for (q, node, ww) in st2: + segs += stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net, gt) + bypad.pop(net, None) + + # ⚠ **独立的扇出阶段试过，反而更差**（30 -> 40 条没接上），代码留在 `fanout()` + # 里备查，默认不跑。原因：提前把每只脚的引出脚铺成铜，等于在还不知道干线 + # 往哪走的时候先占地盘；更要命的是干线从此**只能从那一个落点起步**， + # 而原来 `pad_nodes` 能给 A* 24 个候选起点。少了这份自由度，得不偿失。 + + fixed_s, fixed_v = len(segs), len(vias) + if '--pf' in sys.argv: + # 协商式拥塞布线：所有干线交给它，不再走「一次布死」那条路 + logs += pf_solve(bypad, pads, segs, vias, board_vias, auto, fixed_s, fixed_v) + else: + logs += route_groups(bypad, pads, segs, vias, board_vias, auto, priority) + if logs: + segs, vias, logs = repair(bypad, pads, segs, vias, logs, board_vias, auto, + fixed_s, fixed_v) + segs, vias = dedupe_vias(segs, vias) + for m in check_connected(pads, segs, vias): + if m not in logs: + logs.append(u'[连通性] ' + m) + return segs, vias, logs + + +PUSH_JS = u""" +await eda.dmt_EditorControl.openDocument('%s'); +await new Promise(r=>setTimeout(r,2500)); +const MIL = %s, S = %s, V = %s, H = %s, D = %s; +let ls = 0, vs = 0; +for (const s of S) { + try { await eda.pcb_PrimitiveLine.create(s[6], s[0], s[1]*MIL, s[2]*MIL, + s[3]*MIL, s[4]*MIL, s[5]*MIL); ls++; } catch (e) {} +} +for (const v of V) { + try { await eda.pcb_PrimitiveVia.create(v[2], v[0]*MIL, v[1]*MIL, H*MIL, D*MIL); vs++; } catch (e) {} +} +return {ls, vs}; +""" + + +def push(segs, vias): + n = 0 + for k in range(0, len(segs), 120): + r = call(PUSH_JS % (PCB, MIL, json.dumps(segs[k:k + 120]), + json.dumps(vias if k == 0 else []), VIA_HOLE, VIA_D), + timeout=600) + n += r['ls'] + print(u' 下发 %d 段 / %d 过孔' % (r['ls'], r['vs'])) + call("await eda.pcb_Document.save(); return 1;") + print(u' 共 %d 段' % n) + + +def clear_mine(): + print(call("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2500));" + "const ls = (await eda.pcb_PrimitiveLine.getAll()||[])" + " .filter(l=>l.layer===1||l.layer===2).map(l=>l.primitiveId);" + "if (ls.length) await eda.pcb_PrimitiveLine.delete(ls);" + "const vs = (await eda.pcb_PrimitiveVia.getAll()||[]).map(v=>v.primitiveId);" + "if (vs.length) await eda.pcb_PrimitiveVia.delete(vs);" + "await eda.pcb_Document.save();" + "return {lines: ls.length, vias: vs.length};" % PCB, timeout=600)) + + +FAN_RING = 10 # 扇出找落点最多往外扫几圈（× G = 2.5 mm） +FAN_PITCH = 1.0 # 只给「邻脚中心距 < 这个值」的密脚做扇出 + + +def _pad_axis(pads_of_comp, q): + u"""焊盘的**出线方向**：沿长轴、背对本封装的重心。""" + cx = sum(p[2] for p in pads_of_comp) / float(len(pads_of_comp)) + cy = sum(p[3] for p in pads_of_comp) / float(len(pads_of_comp)) + if q[5] >= q[4]: # 竖着的盘 -> 上下出 + return (0.0, 1.0 if q[3] >= cy else -1.0) + return (1.0 if q[2] >= cx else -1.0, 0.0) + + +FANOUT_REFS = ('U2', 'U4', 'U3') # WQFN-20 0.5 / TSSOP-24 0.65 / MSOP-10 0.5 +FAN_NEAR, FAN_FAR = 0.55, 1.15 # 过孔中心离焊盘端的距离，相邻脚交替（两排） +FAN_MAX_W = 0.4 # 只扇信号（含 +3V3）；VO/$1N165 那种粗线靠直连的铜条 + + +def via_fanout(pads, bypad, segs, vias, auto): + u"""**交错两排的过孔扇出**（手工布细间距 IC 的标准做法）。 + + 每只信号脚沿焊盘长轴直着伸出一段 0.15 的引出脚，末端打一个 Ø0.5 的过孔上顶层； + 相邻脚一近一远交替（0.55 / 1.15），于是同一排过孔的节距是脚距的两倍、 + 远排的引出脚正好从近排两个过孔中间穿过（0.5 节距：0.5 − 0.25 − 0.075 = 0.175）。 + 干线从此全在**几乎是空的顶层**起步，细间距 IC 周围的底层不再是抢出口的战场。 + + ⚠ 与 `fanout()`（同层落点、已废）的区别就在「换层」：同层落点只是把地盘 + 提前占了，干线还是要从那一堆脚中间挤出去。 + + 落点冲突（别的网的焊盘 / 已有铜 / 已有过孔）就换另一排；两排都不行的脚原样交给 A*。 + 返回 (引出脚线段, 过孔, {网: [(原焊盘, vx, vy)]})。 + """ + bycomp = {} + for q in pads: + bycomp.setdefault(q[0], []).append(q) + laid = list(segs) + fan_vias = list(vias) # (x, y, net) + out_s, out_v, out_l = [], [], {} + r_via = VIA_D / 2.0 + want = {} + for net, ps in bypad.items(): + if rule_width(net, auto) > FAN_MAX_W + 1e-9: + continue + for q in ps: + if q[0] in FANOUT_REFS and not _is_launch(q) and (q[0], q[1]) not in KELVIN_PADS: + want[(q[0], q[1])] = (q, net) + for ref in FANOUT_REFS: + comp = bycomp.get(ref, []) + sides = {} + for q in comp: + if (q[0], q[1]) not in want: + continue + ax, ay = _pad_axis(comp, q) + key = (int(round(ax)), int(round(ay))) + sides.setdefault(key, []).append((q, ax, ay)) + for key, items in sides.items(): + # 沿着这一边排序：竖排按 y，横排按 x + items.sort(key=lambda t: t[0][3] if key[0] else t[0][2]) + for k, (q, ax, ay) in enumerate(items): + net = want[(q[0], q[1])][1] + half_len = (q[5] if abs(ay) > 0.5 else q[4]) / 2.0 + sw = stub_w(q, W_DEFAULT) + order = (FAN_NEAR, FAN_FAR) if k % 2 == 0 else (FAN_FAR, FAN_NEAR) + placed = None + for dist in order: + vx = q[2] + ax * (half_len + dist) + vy = q[3] + ay * (half_len + dist) + ok = True + # 别的网的焊盘（两层都要让：通孔） + for o in pads: + if o[7] == net: + continue + r = pad_rect(o) + d = math.hypot(max(r[0] - vx, 0.0, vx - r[2]), max(r[1] - vy, 0.0, vy - r[3])) + if d < r_via + CLR: + ok = False + break + # 引出脚本身也不许蹭到同层别的盘 + if o[6] == q[6] and seg_hits_rect(q[2], q[3], vx, vy, + (r[0] - CLR - sw / 2, r[1] - CLR - sw / 2, + r[2] + CLR + sw / 2, r[3] + CLR + sw / 2)): + ok = False + break + if not ok: + continue + for (l, a1, b1, c1, d1, ww, nn) in laid + out_s: + if nn == net: + continue + if _pt_seg_d(vx, vy, a1, b1, c1, d1) < r_via + ww / 2.0 + CLR: + ok = False + break + if l == q[6] and _seg_seg_d((q[2], q[3], vx, vy), (a1, b1, c1, d1)) < sw / 2.0 + ww / 2.0 + CLR: + ok = False + break + if not ok: + continue + for (ox, oy, on) in fan_vias: + if on == net: + continue + if math.hypot(ox - vx, oy - vy) < 2 * r_via + CLR + 0.05: + ok = False + break + if _pt_seg_d(ox, oy, q[2], q[3], vx, vy) < r_via + sw / 2.0 + CLR: + ok = False + break + if ok: + placed = (vx, vy) + break + if placed is None: + continue + vx, vy = placed + out_s.append((q[6], q[2], q[3], round(vx, 3), round(vy, 3), sw, net)) + out_v.append((round(vx, 3), round(vy, 3), net)) + fan_vias.append((vx, vy, net)) + out_l.setdefault(net, []).append((q, round(vx, 3), round(vy, 3))) + return out_s, out_v, out_l + + +def _pt_seg_d(px, py, x0, y0, x1, y1): + dx, dy = x1 - x0, y1 - y0 + L2 = dx * dx + dy * dy + t = 0.0 if L2 == 0 else max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2)) + return math.hypot(px - (x0 + dx * t), py - (y0 + dy * t)) + + +def _seg_seg_d(a, b): + (x0, y0, x1, y1), (u0, v0, u1, v1) = a, b + r = (x1 - x0, y1 - y0); s2 = (u1 - u0, v1 - v0) + den = r[0] * s2[1] - r[1] * s2[0] + if abs(den) > 1e-12: + t = ((u0 - x0) * s2[1] - (v0 - y0) * s2[0]) / den + u = ((u0 - x0) * r[1] - (v0 - y0) * r[0]) / den + if 0 <= t <= 1 and 0 <= u <= 1: + return 0.0 + return min(_pt_seg_d(x0, y0, *b), _pt_seg_d(x1, y1, *b), _pt_seg_d(u0, v0, *a), _pt_seg_d(u1, v1, *a)) + + +def fanout(pads, bypad, segs, vias, board_vias, auto): + u"""**扇出阶段**：布任何干线之前，先把每只焊盘的引出脚铺成真铜。 + + ⛔ 为什么必须独立成一阶段：出口是**抢**的。谁先布谁把邻脚的格点占掉， + 细间距 IC 的内侧脚必然最后一个布、也必然抢不到 —— 一轮下来 29~42 处 + 报「出不来」，而同样的摆位单独看每只脚**都是出得来的**（空占用图上 + `U4.5` 有 7 个出口，`U2.14` 有 4 个）。这就是手工布板「先做扇出、再拉干线」 + 的顺序，不是优化，是**必须**。 + + 两段式引出脚（细间距连接器靠它）：**先沿焊盘长轴直着出去**到本盘自己的 + 「车道」尽头，再拐到格点。`J4`（0.35 mm 间距、盘 0.18 宽）只有这一条路 —— + 盘心到邻盘边只有 0.26 mm，任何斜着走的引出脚都会蹭上邻盘（实测 0.047 mm）。 + + 返回 (引出脚线段, {网: [落点虚拟焊盘]}, 没出来的日志)。 + """ + bycomp = {} + for q in pads: + bycomp.setdefault(q[0], []).append(q) + laid = list(segs) # 已经有铜的（金手指扇出 / Kelvin / 直连） + launched, logs = {}, [] + # 宽的先扇出：它的落点要求最苛刻 + order = sorted(bypad, key=lambda n: -width_of(n, auto, bypad[n])) + for net in order: + ps = [q for q in bypad[net] if q[0] != 'J1'] + if not ps: + continue + w = width_of(net, auto, ps) + w = max(W_DEFAULT, min(w, min(min(q[4], q[5]) for q in ps))) + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a1, b1, c1, d1, ww, nn) in laid: + block_track(g, l, a1, b1, c1, d1, halfw + ww / 2.0, nn) + others = [pad_rect(q) for q in pads] + out = [] + # ⚠ **只扇密脚**。把每只脚都提前铺一段引出脚，等于在还不知道干线往哪走的时候 + # 就占地盘 —— 实测反而从 30 处涨到 40 处没接上。真正抢不到出口的只有 + # 细间距 IC 的内侧脚（邻脚中心距 < 1 mm），其余交给 A* 自己找更好。 + for q in ps: + near = min([math.hypot(q[2] - o[2], q[3] - o[3]) + for o in bycomp[q[0]] if o is not q] or [99]) + if near >= FAN_PITCH: + out.append(q) # 原样交给 A* + continue + sw = stub_w(q, w) + inf = STUB_CLR + sw / 2.0 + own = pad_rect(q) + oth = [(r[0] - inf, r[1] - inf, r[2] + inf, r[3] + inf) + for r, p2 in zip(others, pads) + if p2[6] == q[6] and p2[7] != net + and max(abs(r[0] - own[0]), abs(r[1] - own[1]), + abs(r[2] - own[2]), abs(r[3] - own[3])) > 1e-9] + oth_pads = [o for o in ps if o is not q] + tx = (sum(o[2] for o in oth_pads) / len(oth_pads)) if oth_pads else q[2] + ty = (sum(o[3] for o in oth_pads) / len(oth_pads)) if oth_pads else q[3] + ax, ay = _pad_axis(bycomp[q[0]], q) + reach = (q[5] if ay else q[4]) / 2.0 + inf + ex, ey = q[2] + ax * reach, q[3] + ay * reach + best = None + for ring in range(1, FAN_RING + 1): + r = ring * G + cand = [] + for j in range(gy(ey - r), gy(ey + r) + 1): + for i in range(gx(ex - r), gx(ex + r) + 1): + X, Y = wx(i), wy(j) + if not g.free(q[6], i, j, net): + continue + if any(seg_hits_rect(q[2], q[3], ex, ey, o) for o in oth): + continue + if any(seg_hits_rect(ex, ey, X, Y, o) for o in oth): + continue + if not _stub_clear(g, q[6], q[2], q[3], X, Y, net): + continue + # ⚠ 落点**朝目的地挑**，不是挑离焊盘最近的： + # 引出脚指错方向，后面干线要绕回来，还把路占了。 + cand.append((math.hypot(X - tx, Y - ty), + math.hypot(X - ex, Y - ey), i, j)) + if cand: + cand.sort() + best = cand[0] + break + if best is None: + logs.append(u'%s: %s.%s 扇不出来' % (net, q[0], q[1])) + continue + _d, _d2, i, j = best + X, Y = wx(i), wy(j) + if math.hypot(ex - q[2], ey - q[3]) > 1e-6: + laid.append((q[6], q[2], q[3], ex, ey, sw, net)) + laid.append((q[6], ex, ey, X, Y, sw, net)) + block_track(g, q[6], q[2], q[3], ex, ey, halfw + sw / 2.0, net) + block_track(g, q[6], ex, ey, X, Y, halfw + sw / 2.0, net) + out.append([q[0], 'fan:' + str(q[1]), X, Y, 0.3, 0.3, q[6], net, 'RECT']) + if out: + launched[net] = out + return laid[len(segs):], launched, logs + + +LINK_MAX = 2.2 # 直连允许的最大焊盘净距 + + +def _pad_gap(a, b): + dx = max(abs(a[2] - b[2]) - (a[4] + b[4]) / 2.0, 0.0) + dy = max(abs(a[3] - b[3]) - (a[5] + b[5]) / 2.0, 0.0) + return math.hypot(dx, dy) + + +AUTO_CACHE = {} + + +def direct_links(pads, bypad, segs, vias, blocked_rects=()): + u"""**焊盘对焊盘**的短连接直接画一段铜，不交给 A*。 + + ⛔ 为什么非要有这一步：A* 的占用图是按**干线宽度**建的。`SWNODE` 是 2.0 mm ⇒ + 半宽 + 净距 = 1.18 mm，于是 `U1` 的 SW 脚（0.5 mm 间距）周围**一个格点都不空**， + 报「$1N137: U1.11 出不来」。可这条连接根本不需要 A* —— 摆位时就是 + **焊盘正对焊盘、净距 0.65 mm**，人手画就是一段直铜。 + 同一类的还有 `VO`(L1→C6)、`$1N165`(U2→Rs1)、`+12V_F`(Cin→U1)。 + + 宽度取**两个焊盘在垂直于连线方向上的较小者** —— 再宽也没用， + 电流的瓶颈就是 IC 自己的脚。 + + 判据：同层、同网、净距 ≤ `LINK_MAX`，且连线走廊里没有第三个焊盘、 + 没有已布的铜、没有过孔。 + """ + out, merged = [], {} + others = {} + for q in pads: + others.setdefault(q[6], []).append(q) + for net, ps in sorted(bypad.items()): + cand = [q for q in ps if q[0] != 'J1'] + groups = [] + for i in range(len(cand)): + for j in range(i + 1, len(cand)): + a, b = cand[i], cand[j] + if a[6] != b[6]: + continue + if _pad_gap(a, b) > LINK_MAX: + continue + # 垂直于连线方向的可用宽度 + dx, dy = abs(a[2] - b[2]), abs(a[3] - b[3]) + wa = a[5] if dx >= dy else a[4] + wb = b[5] if dx >= dy else b[4] + w = round(max(rule_min(net, AUTO_CACHE), min(wa, wb)), 3) + if w < 0.15: + continue + inf = CLR + w / 2.0 + bad = False + for owner, rr in blocked_rects: + if owner == net: + continue + r = (rr[0] - inf, rr[1] - inf, rr[2] + inf, rr[3] + inf) + if seg_hits_rect(a[2], a[3], b[2], b[3], r): + bad = True + break + for q in others.get(a[6], []): + # ⚠ **同网的焊盘不算障碍** —— 压上去也是同一个节点。 + # 漏了这一条，`U1` 的两只 SW 脚会互相判死：11 脚要接 L1， + # 12 脚（同网、隔 0.5 mm）挡在旁边，于是「U1.11 出不来」。 + if q[7] == net or (q[0], q[1]) in ((a[0], a[1]), (b[0], b[1])): + continue + r = pad_rect(q, inf) + if seg_hits_rect(a[2], a[3], b[2], b[3], r): + bad = True + break + if not bad: + for (l, x0, y0, x1, y1, ww, nn) in segs: + if l != a[6] or nn == net: + continue + if seg_seg_dist(a[2], a[3], b[2], b[3], x0, y0, x1, y1) < inf + ww / 2.0: + bad = True + break + if not bad: + for (vx, vy, nn) in vias: + if nn == net: + continue + if seg_hits_rect(a[2], a[3], b[2], b[3], + (vx - VIA_D / 2 - inf, vy - VIA_D / 2 - inf, + vx + VIA_D / 2 + inf, vy + VIA_D / 2 + inf)): + bad = True + break + if bad: + continue + out.append((a[6], a[2], a[3], b[2], b[3], w, net)) + ka, kb = (a[0], a[1]), (b[0], b[1]) + ga = next((g for g in groups if ka in g), None) + gb = next((g for g in groups if kb in g), None) + if ga is None and gb is None: + groups.append({ka, kb}) + elif ga is None: + gb.add(ka) + elif gb is None: + ga.add(kb) + elif ga is not gb: + ga |= gb + groups.remove(gb) + if groups: + merged[net] = groups + return out, merged + + +def seg_seg_dist(x1, y1, x2, y2, x3, y3, x4, y4): + u"""两条线段的最小距离（够用的粗算：端点到线段 + 采样）。""" + def pt_seg(px, py, ax, ay, bx, by): + dx, dy = bx - ax, by - ay + L = dx * dx + dy * dy + t = 0.0 if L == 0 else max(0.0, min(1.0, ((px - ax) * dx + (py - ay) * dy) / L)) + return math.hypot(px - (ax + t * dx), py - (ay + t * dy)) + return min(pt_seg(x1, y1, x3, y3, x4, y4), pt_seg(x2, y2, x3, y3, x4, y4), + pt_seg(x3, y3, x1, y1, x2, y2), pt_seg(x4, y4, x1, y1, x2, y2)) + + +VIA_MIN_D = VIA_D # 同网过孔的最小中心距 = 钻孔间距 0.3 + 钻孔径 0.3 + + +def dedupe_vias(segs, vias): + u"""同一个网上**挨得太近的过孔**合成一个。 + + ⛔ 占用图是「按网可进」的，所以同一个网的两条支路可以各自在几乎同一个点换层 —— + 几何上不冲突，但**钻孔到钻孔**的规则不认网：DRC 报 + 「钻孔 (SCL) 到 钻孔 (SCL) 距离为 0 mil，应该 >= 11.8 mil」。 + 自算净距那一支也抓不到（`router_check` 只判铜与铜，钻孔那一支归 EasyEDA）。 + + 合并判据：同网、中心距 < `VIA_MIN_D`(=0.6 mm)。这时两个过孔的**焊盘本来就重叠**， + 所以补一小段两层导线把被删的那个点接回保留点，不会伸出原来的铜之外。 + """ + keep, drop = [], {} + for (x, y, net) in vias: + hit = None + for (kx, ky, kn) in keep: + if kn == net and math.hypot(kx - x, ky - y) < VIA_MIN_D - 1e-9: + hit = (kx, ky) + break + if hit is None: + keep.append((x, y, net)) + else: + drop[(round(x, 4), round(y, 4), net)] = hit + if drop: + print(u'同网过孔合并 %d 个（中心距 < %.2f mm）' % (len(drop), VIA_MIN_D)) + for (x, y, net), (kx, ky) in drop.items(): + w = max(0.2, rule_min(net, AUTO_CACHE)) + for l in LAY: + segs.append((l, x, y, kx, ky, w, net)) + return segs, keep + + +PASSES = 4 # 失败重试轮数（拆线重布接手之后不必太多） +CACHE = os.path.join(HERE, '_blade_routes.json') + + +# ══════════════════════════════════════════════════════════════════════ +# 协商式拥塞布线（PathFinder） +# ══════════════════════════════════════════════════════════════════════ +# ⛔ 为什么非要换算法：这个「一次布死、不回退」的 A* 到 23 条就不动了。 +# 试过顺序、扇出、过路费、L 形引出脚、正交方向、拆线重布、难的先布 —— 全在 +# 12~23 之间打转。根因是**它没有让路机制**：谁先占住走廊，后来的就只能报失败。 +# +# PathFinder 的做法（Nair 1987 / McMurchie-Ebeling 1995）： +# 1. 每一轮**所有网都重新布一遍**，允许暂时压在别人身上（不是硬障碍，是加钱）； +# 2. 一轮结束后，把**被多个网压着的格点**的「历史代价」加一档； +# 3. 下一轮大家再抢，历史贵的地方自然有人让开 —— 谁绕路代价小谁让。 +# 反复若干轮直到没有格点被两个网同时占。这就是「协商」。 +# ⚠ 调度是 PathFinder 的命门。第一版「每轮翻倍、封顶 64」**不收敛** —— +# 冲突 1790→1062 之后在 1200 附近震荡：当前代价涨得太快，网被推得来回横跳， +# 历史代价还没来得及把「谁该让」这件事沉淀下来。 +# 改成教科书的慢涨（×1.25），并让历史按**超用量**累加。 +PF_PRESENT = [1.0] # 当前拥塞权重，每轮 ×PF_GROW +PF_GROW = 1.25 +PF_HIST_W = 4 # 历史拥塞权重 +PF_ITERS = 30 + + +def _route_cells(segs_of_net, halfw): + u"""一条线占的格点。 + + ⛔ 膨胀量是 **线半宽 + 净距/2**，不是 `halfw + w/2`（= 线宽 + 净距）。 + 两条线各膨胀「半宽 + 净距/2」之后**刚好在净距处相切** —— 这才是 + 「再近一点就违规」的判据。按 `halfw + w/2` 膨胀的话，两根**正好隔着 + 合法净距**的线也会共占格点，于是 PF 一直在追逐根本不存在的冲突， + 冲突数卡在 800 上下永远收敛不了（实测 2678→823 就不动了）。 + """ + out = set() + for (l, x0, y0, x1, y1, w, _n) in segs_of_net: + r = w / 2.0 + CLR / 2.0 + steps = int(max(abs(x1 - x0), abs(y1 - y0)) / (G / 2)) + 1 + for k in range(steps + 1): + t = k / float(steps) + x, y = x0 + (x1 - x0) * t, y0 + (y1 - y0) * t + for j in range(gy(y - r), gy(y + r) + 1): + for i in range(gx(x - r), gx(x + r) + 1): + if 0 <= i < NX and 0 <= j < NY: + out.add((l, i, j)) + return out + + +def _pf_mark(occ, cells, d): + for (l, i, j) in cells: + o = j * NX + i + v = occ[l][o] + d + occ[l][o] = max(0, min(250, v)) + + +def _exact_conflicts(cur, pads): + u"""按**精确几何**找出真正压在一起的网（判据同 router_check：净距 < MIN_CLR）。 + + ⚠ **过孔那一支不能漏**：只查线与线的话，会漏掉「过孔压在另一面的焊盘上」 + 和「两个不同网的过孔叠在一起」—— 实测漏掉了 `PRSNT#` 的孔压在 `J2.5`(GND) + 盘上（净距 −0.300）和 `+12V_F` / `$1N131` 两个孔叠了 0.041。 + 通孔是穿两层的，所以焊盘那一支**两层都要查**。 + """ + MIN = 0.15 + items = [] + allv = [] + for net, (s2, v2, _c) in cur.items(): + for t in s2: + items.append((t[0], t[1], t[2], t[3], t[4], t[5], net)) + for (vx, vy, _q) in v2: + allv.append((vx, vy, net)) + # 按 y 粗分桶，避免 O(n^2) 全比 + bad = set() + n = len(items) + for i in range(n): + a = items[i] + ay0, ay1 = min(a[2], a[4]), max(a[2], a[4]) + ax0, ax1 = min(a[1], a[3]), max(a[1], a[3]) + for j in range(i + 1, n): + b = items[j] + if b[6] == a[6] or b[0] != a[0]: + continue + if min(b[2], b[4]) > ay1 + 1.0 or max(b[2], b[4]) < ay0 - 1.0: + continue + if min(b[1], b[3]) > ax1 + 1.0 or max(b[1], b[3]) < ax0 - 1.0: + continue + d = seg_seg_dist(a[1], a[2], a[3], a[4], b[1], b[2], b[3], b[4]) + if d - a[5] / 2.0 - b[5] / 2.0 < MIN - 1e-9: + bad.add(a[6]) + bad.add(b[6]) + # 过孔 vs 焊盘（两层都查，通孔穿透） + for (vx, vy, net) in allv: + for q in pads: + if q[7] == net: + continue + dx = max(q[2] - q[4] / 2 - vx, 0.0, vx - (q[2] + q[4] / 2)) + dy = max(q[3] - q[5] / 2 - vy, 0.0, vy - (q[3] + q[5] / 2)) + if math.hypot(dx, dy) - VIA_D / 2.0 < MIN - 1e-9: + bad.add(net) + break + # 过孔 vs 过孔（异网） + for i in range(len(allv)): + for j in range(i + 1, len(allv)): + if allv[i][2] == allv[j][2]: + continue + if math.hypot(allv[i][0] - allv[j][0], allv[i][1] - allv[j][1]) - VIA_D < MIN - 1e-9: + bad.add(allv[i][2]) + bad.add(allv[j][2]) + return bad + + +def pf_solve(bypad, pads, segs, vias, board_vias, auto, fixed_s, fixed_v): + u"""对 `bypad` 里所有网做协商式拥塞布线。原地改 segs/vias，返回没搞定的日志。""" + occ = {l: bytearray(NX * NY) for l in LAY} + hist = {l: bytearray(NX * NY) for l in LAY} + base_s, base_v = segs[:fixed_s], vias[:fixed_v] + + # 每个网一份线宽 / 半宽；硬障碍图按宽度分档建一次就够 + wof, hard = {}, {} + for net, ps in bypad.items(): + w = width_of(net, auto, ps) + small = w if net in NO_CAP else min([min(q[4], q[5]) for q in ps if q[0] != 'J1'] or [w]) + wof[net] = max(W_DEFAULT, rule_min(net, auto), min(w, small)) + for w in sorted(set(wof.values())): + halfw = w / 2.0 + CLR + g = build_grid(pads, halfw, board_vias) + for (l, a, b, c, d, ww, nn) in base_s: # 前置阶段的铜是硬障碍 + # ⛔ `extra` 不能用默认的 0：`block_both` 的第二张图（`ownv`）是**换层判据**， + # 不给额外膨胀的话，别人的过孔可以直接落在这根线上 —— + # DRC 报「导线到过孔 0 mil」，实测两处（`EFUSE_EN` 的孔压 `$1N147`、 + # `$1N164` 的孔压 `EFUSE_PG`），而线与线那一支干干净净，很难看出来是谁的错。 + block_track(g, l, a, b, c, d, halfw + ww / 2.0, nn, + extra=max(0.0, VIA_D / 2.0 + CLR - (halfw + ww / 2.0))) + for (vx, vy, nn) in base_v: + for l in LAY: + g.block_rect(l, vx - VIA_D / 2 - halfw, vy - VIA_D / 2 - halfw, + vx + VIA_D / 2 + halfw, vy + VIA_D / 2 + halfw, net=nn) + g.occ, g.hist = occ, hist + hard[w] = g + + others = {1: [], 2: []} + for p in pads: + if p[6] in others: + others[p[6]].append(pad_rect(p)) + + cur = {} # net -> (segs, vias, cells) + order = sorted(bypad, key=lambda n: -wof[n]) + logs = [] + best = None + for it in range(PF_ITERS): + logs = [] + for net in order: + old = cur.pop(net, None) + if old: + _pf_mark(occ, old[2], -1) + w = wof[net] + g = hard[w] + halfw = w / 2.0 + CLR + s2, v2, st2 = route_net(g, net, bypad[net], halfw, w, others, logs, + None, mutate=False) + for (q, node, ww) in st2: + s2 = s2 + stub_emit(q, wx(node[1]), wy(node[2]), + [] if _is_launch(q) else others.get(q[6], []), + ww / 2.0, ww, net) + cells = _route_cells(s2, halfw) + _pf_mark(occ, cells, +1) + cur[net] = (s2, v2, cells) + # 一轮结束：给被多个网压着的格点按**超用量**加历史代价 + bad = 0 + for l in LAY: + oc, hi = occ[l], hist[l] + for o in range(NX * NY): + if oc[o] > 1: + bad += 1 + hi[o] = min(250, hi[o] + oc[o] - 1) + print(u' PF 第 %d 轮：冲突格点 %d，没布通 %d（present=%.1f）' + % (it + 1, bad, len(logs), PF_PRESENT[0])) + if best is None or (bad, len(logs)) < best[0]: + best = ((bad, len(logs)), {n: (list(a2), list(b2), set(c2)) + for n, (a2, b2, c2) in cur.items()}, list(logs)) + if bad == 0 and not logs: + break + PF_PRESENT[0] *= PF_GROW + # 取**冲突最少的那一轮**，不是最后一轮 + if best is not None: + cur, logs = best[1], list(best[2]) + + # ⛔ **格点冲突 ≠ 真违规**。0.25 mm 的格子表示不了 0.35 mm 间距的分离， + # 所以 PF 的冲突数里混着大量**量化假象**（卡在 ~895 下不去就是这个原因）。 + # 真正的判据是**精确几何**（和 router_check 同一套）。这里按精确距离筛一遍， + # 只把**真的**压在一起的网拿去重布。 + real = _exact_conflicts(cur, pads) + if real: + print(u' 精确几何：真违规涉及 %d 个网 —— %s' + % (len(real), ' '.join(sorted(real)[:10]))) + base_cells = {} + for n2, (s2, v2, c2) in cur.items(): + if n2 not in real: + base_cells[n2] = (s2, v2, c2) + ns = list(base_s) + [t for n2 in base_cells for t in base_cells[n2][0]] + nv = list(base_v) + [(x, y, n2) for n2 in base_cells + for (x, y, _q) in base_cells[n2][1]] + sub = route_groups(bypad, pads, ns, nv, board_vias, auto, + priority=tuple(real), only=set(real)) + logs += sub + del segs[fixed_s:] + del vias[fixed_v:] + segs += ns[len(base_s):] + vias += nv[len(base_v):] + return logs + # ⛔ **绝不能把还有冲突的解下发**（那是真短路）。还剩冲突就逐个丢掉 + # 「压着别人最多」的那个网，直到干净为止，丢掉的如实报成没布通。 + while True: + occ2 = {l: bytearray(NX * NY) for l in LAY} + for _n, (_s, _v, c2) in cur.items(): + _pf_mark(occ2, c2, +1) + blame = {} + for net, (_s, _v, c2) in cur.items(): + k = sum(1 for (l, i, j) in c2 if occ2[l][j * NX + i] > 1) + if k: + blame[net] = k + if not blame: + break + worst = max(blame, key=lambda n: (blame[n], wof[n])) + del cur[worst] + logs.append(u'%s: 让路（协商后仍有冲突，整条丢弃）' % worst) + del segs[fixed_s:] + del vias[fixed_v:] + for net, (s2, v2, _c) in cur.items(): + segs += s2 + vias += [(x, y, net) for (x, y, _n) in v2] + return logs + + +if __name__ == '__main__': + if '--clear' in sys.argv: + clear_mine() + sys.exit(0) + # 算一次要好几分钟，结果落盘；--push 默认吃缓存，加 --replan 才重算。 + if '--replan' not in sys.argv and os.path.exists(CACHE): + c = json.load(io.open(CACHE, encoding='utf-8')) + segs, vias, logs = c['segs'], c['vias'], c['logs'] + print(u'（用缓存 _blade_routes.json）') + else: + # ⛔ **一轮布不完是正常的**：谁先布谁占走廊，后布的就没路。 + # 没有 rip-up 的话，最有效的补救是「**这一轮没接上的，下一轮排最前面**」， + # 跑几轮取最好的一轮。实测 30 -> 个位数。 + best, prio = None, set() + for it in range(1 if '--pf' in sys.argv else PASSES): + segs, vias, logs = plan_all(prio) + print(u' 第 %d 轮：%d 条没搞定' % (it + 1, len(logs))) + if best is None or len(logs) < len(best[2]): + best = (segs, vias, logs) + if not logs: + break + prio |= set(_msg_net(m) for m in logs) + segs, vias, logs = best + io.open(CACHE, 'w', encoding='utf-8').write( + json.dumps({'segs': segs, 'vias': vias, 'logs': logs}, ensure_ascii=False)) + tot = sum(math.hypot(s[3] - s[1], s[4] - s[2]) for s in segs) + print(u'导线 %d 段 / 总长 %.1f mm / 过孔 %d' % (len(segs), tot, len(vias))) + nets = {} + for s in segs: + nets[s[6]] = nets.get(s[6], 0) + 1 + print(u'涉及 %d 个网络' % len(nets)) + if logs: + print(u'[!] %d 条没搞定:' % len(logs)) + for m in logs[:40]: + print(u' ' + m) + if '--push' in sys.argv: + push(segs, vias) diff --git a/.claude/r2/router_check.py b/.claude/r2/router_check.py new file mode 100644 index 0000000..6d26cf4 --- /dev/null +++ b/.claude/r2/router_check.py @@ -0,0 +1,178 @@ +# -*- coding: utf-8 -*- +u"""对**布线器算出来的几何**自算净距 —— 不过桥接、不等 DRC。 + + /c/Python314/python .claude/r2/router_check.py [--list N] + +## 为什么要有这个 + +EasyEDA 的 DRC 一轮要 ~10 分钟（下发 → 重铺 → 读面板），而且**明细行读不回来** +（`drc_read.py` 能读到分类计数，读不到每一条的对象和坐标）。 +靠它迭代等于每改一行代码等十分钟、还看不到是哪两个东西撞了。 + +⇒ 这里按**真实几何**（线段-线段 / 线段-矩形 / 圆-圆 …）自算， +判据和设计规则一致（净距 `MIN_CLR`）。布线器的占用图是 0.25 mm 网格上的 +轴对齐盒子，是个**近似**；这个检查器算的是精确距离，两者的差就是 DRC 会报的那些。 + +⚠ 判据只覆盖「铜与铜」。**铺铜（pour）与过孔/钻孔的关系不在这里** —— + 那一支归 EasyEDA 自己按规则裁，DRC 里显示成「到 过孔 / 到 钻孔」。 +""" +import io +import json +import math +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +import pcb_blade as B # noqa: E402 +import router as R # noqa: E402 + +MIN_CLR = 0.15 # 设计规则里的安全间距 + + +def seg_seg(a, b): + u"""两条线段的最小距离。""" + (x1, y1, x2, y2), (x3, y3, x4, y4) = a, b + + def pt_seg(px, py, ax, ay, bx, by): + dx, dy = bx - ax, by - ay + L = dx * dx + dy * dy + t = 0.0 if L == 0 else max(0.0, min(1.0, ((px - ax) * dx + (py - ay) * dy) / L)) + return math.hypot(px - (ax + t * dx), py - (ay + t * dy)) + + d1, d2 = x2 - x1, y2 - y1 + d3, d4 = x4 - x3, y4 - y3 + den = d1 * d4 - d2 * d3 + if abs(den) > 1e-12: + t = ((x3 - x1) * d4 - (y3 - y1) * d3) / den + u = ((x3 - x1) * d2 - (y3 - y1) * d1) / den + if 0 <= t <= 1 and 0 <= u <= 1: + return 0.0 + return min(pt_seg(x1, y1, x3, y3, x4, y4), pt_seg(x2, y2, x3, y3, x4, y4), + pt_seg(x3, y3, x1, y1, x2, y2), pt_seg(x4, y4, x1, y1, x2, y2)) + + +def seg_rect(s, r): + u"""线段到轴对齐矩形的最小距离（相交为 0）。""" + x1, y1, x2, y2 = s + rx0, ry0, rx1, ry1 = r + for (px, py) in ((x1, y1), (x2, y2)): + if rx0 <= px <= rx1 and ry0 <= py <= ry1: + return 0.0 + e = [(rx0, ry0, rx1, ry0), (rx1, ry0, rx1, ry1), + (rx1, ry1, rx0, ry1), (rx0, ry1, rx0, ry0)] + return min(seg_seg(s, q) for q in e) + + +def pt_rect(px, py, r): + dx = max(r[0] - px, 0.0, px - r[2]) + dy = max(r[1] - py, 0.0, py - r[3]) + return math.hypot(dx, dy) + + +def main(): + cache = json.load(io.open(os.path.join(HERE, '_blade_routes.json'), encoding='utf-8')) + segs, vias = cache['segs'], cache['vias'] + pads = R.load_pads() + holes = B.phone_holes() + # 缝合过孔也算进来 + import pcb_route as PR + stitch = [(x, y, 'GND') for (x, y) in PR.stitch_points()] + allv = [(v[0], v[1], v[2]) for v in vias] + stitch + + bad = {} + + def hit(kind, msg): + bad.setdefault(kind, []).append(msg) + + # ── 线 ↔ 线（同层异网）── + bylay = {1: [], 2: []} + for (l, x0, y0, x1, y1, w, net) in segs: + if l in bylay: + bylay[l].append((x0, y0, x1, y1, w, net)) + for l, lst in bylay.items(): + for i in range(len(lst)): + a = lst[i] + for j in range(i + 1, len(lst)): + b = lst[j] + if a[5] == b[5]: + continue + if max(a[0], a[2]) + 3 < min(b[0], b[2]) or max(b[0], b[2]) + 3 < min(a[0], a[2]): + continue + if max(a[1], a[3]) + 3 < min(b[1], b[3]) or max(b[1], b[3]) + 3 < min(a[1], a[3]): + continue + d = seg_seg(a[:4], b[:4]) - (a[4] + b[4]) / 2.0 + if d < MIN_CLR: + hit(u'线-线', u'%s / %s 净距 %.3f @ L%s (%.1f,%.1f)' + % (a[5], b[5], d, l, a[0], a[1])) + + # ── 线 ↔ 焊盘（同层异网）── + for (l, x0, y0, x1, y1, w, net) in segs: + for p in pads: + if p[6] != l or p[7] == net: + continue + d = seg_rect((x0, y0, x1, y1), R.pad_rect(p)) - w / 2.0 + if d < MIN_CLR: + hit(u'线-焊盘', u'%s 线 vs %s.%s(%s) 净距 %.3f @ L%s' + % (net, p[0], p[1], p[7], d, l)) + + # ── 线 ↔ 过孔（异网）── + for (l, x0, y0, x1, y1, w, net) in segs: + for (vx, vy, vnet) in allv: + if vnet == net: + continue + d = seg_seg((x0, y0, x1, y1), (vx, vy, vx, vy)) - w / 2.0 - R.VIA_D / 2.0 + if d < MIN_CLR: + hit(u'线-过孔', u'%s 线 vs %s 过孔(%.1f,%.1f) 净距 %.3f' % (net, vnet, vx, vy, d)) + + # ── 过孔 ↔ 焊盘 / 过孔 ↔ 过孔（异网）── + for k, (vx, vy, vnet) in enumerate(allv): + for p in pads: + if p[7] == vnet: + continue + d = pt_rect(vx, vy, R.pad_rect(p)) - R.VIA_D / 2.0 + if d < MIN_CLR: + hit(u'过孔-焊盘', u'%s 过孔(%.1f,%.1f) vs %s.%s(%s) 净距 %.3f' + % (vnet, vx, vy, p[0], p[1], p[7], d)) + for (wx_, wy_, wnet) in allv[k + 1:]: + if wnet == vnet: + continue + d = math.hypot(vx - wx_, vy - wy_) - R.VIA_D + if d < MIN_CLR: + hit(u'过孔-过孔', u'%s vs %s (%.1f,%.1f) 净距 %.3f' % (vnet, wnet, vx, vy, d)) + + # ── 定位孔（NPTH）↔ 铜 ── + for hname, (hx, hy) in holes.items(): + hr = B.HOLE_D / 2.0 + for (l, x0, y0, x1, y1, w, net) in segs: + d = seg_seg((x0, y0, x1, y1), (hx, hy, hx, hy)) - w / 2.0 - hr + if d < MIN_CLR: + hit(u'钻孔-线', u'%s vs %s 线 净距 %.3f' % (hname, net, d)) + for (vx, vy, vnet) in allv: + d = math.hypot(vx - hx, vy - hy) - hr - R.VIA_D / 2.0 + if d < MIN_CLR: + hit(u'钻孔-过孔', u'%s vs %s 过孔(%.1f,%.1f) 净距 %.3f' % (hname, vnet, vx, vy, d)) + for p in pads: + d = pt_rect(hx, hy, R.pad_rect(p)) - hr + if d < MIN_CLR: + hit(u'钻孔-焊盘', u'%s vs %s.%s 净距 %.3f' % (hname, p[0], p[1], d)) + + n = sum(len(v) for v in bad.values()) + print(u'自算净距（判据 %.2f mm）：%d 条' % (MIN_CLR, n)) + for k in sorted(bad, key=lambda k: -len(bad[k])): + print(u' %-8s %d' % (k, len(bad[k]))) + lim = 8 + for a in sys.argv: + if a.startswith('--list'): + lim = int(sys.argv[sys.argv.index(a) + 1]) + for k in sorted(bad, key=lambda k: -len(bad[k])): + print(u'── %s ──' % k) + for m in bad[k][:lim]: + print(u' ' + m) + return n + + +if __name__ == '__main__': + sys.exit(1 if main() else 0) diff --git a/.claude/r2/rules_base.py b/.claude/r2/rules_base.py new file mode 100644 index 0000000..01d7d45 --- /dev/null +++ b/.claude/r2/rules_base.py @@ -0,0 +1,390 @@ +# -*- coding: utf-8 -*- +u"""R2 底板 PCB 的设计规则（M8b）。 + + /c/Python314/python .claude/r2/rules_base.py # 只反查 + 打印，不下发 + /c/Python314/python .claude/r2/rules_base.py --dump # 重抓「位号.引脚 → 网名」 + /c/Python314/python .claude/r2/rules_base.py --push # 下发规则 + 差分对 + 网络指派 + /c/Python314/python .claude/r2/rules_base.py --audit # 读回审计 + +做法与 `pcb_rules.py`（刀片）同源，**那一份的文件头是唯一的说明书**，四个坑一个没变： + + · `overwriteCurrentRuleConfiguration(x)` 要 config **本体**，不要 `{name,config}` 包装 + · `getCurrentRuleConfiguration()` 是**嵌套形状**，`getRuleConfiguration(能力集)` 是**平形状** + · 下发之后**别再去 GUI 换「配置」下拉框** —— 换一次整套重置，网络指派全部悬空 + · `overwriteNetRules` / `overwriteNetByNetRules` 都是**整表覆盖**，先读回再合并 + +## 和刀片那份不同的四处 + +1. **四层板**（D15，2026-09-10 由 2 层改）。建工程时是 2 层，`--push` 先 + `setTheNumberOfCopperLayers(4)`（换层数会换基准能力集，方案 §24.1）， + 再照刀片补 `copperThickness0.5oz` 线宽 + `copperThicknessInner0.5oz` 间距 + （内层表从 `JLCPCB Capability(Multiple Layers Board)` 拷）。 + 叠层：L1 插槽面 / L2 GND / L3 GND / L4 器件面，内层只做地平面、不布线。 + +2. **入口链是 9 A**（方案 §6.4），不是刀片的 1.45 A。线宽规则给到 + `strokeWidthMax = 12`，真正的载流靠 `pour_base` 的断面校核保证，不靠 DRC。 + +3. **七对差分**：五个槽 + ESP32 原生 USB（D13）+ 上行 USB-C。 + D± 走 L4、参考 L3，和刀片同一种薄介质微带 ⇒ 直接用刀片那组 **W 0.28 / S 0.18**（~90 Ω）。 + ⛔ 两层版的 W 1.2 / S 0.2 在四层上阻抗严重偏低，别拿回来。 + intra-pair skew 仍按方案 §6.3 卡 1 mm（刀片放到 5）。 + +4. **自动命名网一个都不指派**：底板上 22 个 `$xNyy` 全是小信号 + （泄放电阻串、Buck 反馈、DAC 的 RC、风扇 MOS 栅极），走默认线宽即可。 + ⇒ 没有「按位号.引脚反查自动网名」那一步，也就没有那一类静默失效。 +""" +import io +import json +import os +import sys + +sys.stdout.reconfigure(encoding='utf-8') +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +PCB = B.PCB +LAYERS = 4 +NETS_FILE = os.path.join(HERE, '_base_pcb_nets.json') + +# ── 线宽规则（mm，外层 1 oz）──────────────────────────────────────────── +# 载流靠灌铜断面保证、不靠 DRC；min 一律压到 0.15~0.3，否则 0402 焊盘扇不出去。 +TRACK_RULES = { + 'PWR9A': {'strokeWidthDefault': 2.0, 'strokeWidthMin': 0.30, 'strokeWidthMax': 12.0}, + 'PWR12V': {'strokeWidthDefault': 1.5, 'strokeWidthMin': 0.30, 'strokeWidthMax': 12.0}, + 'FAN12V': {'strokeWidthDefault': 0.8, 'strokeWidthMin': 0.25, 'strokeWidthMax': 3.0}, + 'PWR5V': {'strokeWidthDefault': 0.6, 'strokeWidthMin': 0.20, 'strokeWidthMax': 3.0}, + 'PWR3V3': {'strokeWidthDefault': 0.5, 'strokeWidthMin': 0.15, 'strokeWidthMax': 3.0}, +} + +# ── 有名字的网络 → 线宽规则 ──────────────────────────────────────────── +# ⚠ `+12V` 是**一个网**：从 Rs6 下游一路到 5 个槽的 12V 针（43 只脚）。 +# 干路 9 A 那一段和「母线 → 单槽」1.5 A 那一段线宽不同，DRC 只能按一条规则判 ⇒ +# 取干路的 `PWR9A`（default 2.0 只是画线的起手宽度），断面由 `pour_base` 逐段校核。 +NET_TRACK = { + 'VIN_RAW': 'PWR9A', # J1 中心极 → F1 + 'VIN_FUSED': 'PWR9A', # F1 → Q1 反接保护 + 'VIN_SW': 'PWR9A', # Q1 → 储能 → Rs6 上游 + '+12V': 'PWR9A', # Rs6 下游 → 母线 → 5 槽 + 两颗 Buck + 风扇 + 'FAN_12V_SW': 'FAN12V', # 风扇下管开关点（R1 §22.6 定的 0.8） + '+5V': 'PWR5V', # U30 → 5 槽（每槽给刀片 U5 TPS22918） + '+3V3': 'PWR3V3', # U19 → ESP32 / mux / DAC / 5 槽逻辑 + '+3V3_HUB': 'PWR3V3', # U31 AMS1117 → U32（与 +3V3 只共地） +} + +# ── 铺铜焊盘全连接（理由同刀片：不是怕十字花烧，是**铺完之后断面要量得准**）── +PLANE_RULE = 'PLANE-DIRECT' +PLANE_CONNECT_DIRECT = 1 +PLANE_NETS = ['VIN_RAW', 'VIN_FUSED', 'VIN_SW', '+12V'] + +# ── 差分对（mm）── L4 微带参考 L3，同刀片：W 0.28 / S 0.18 ⇒ ~90 Ω ── +DIFF = {'strokeWidthDefault': 0.28, 'strokeWidthMin': 0.20, 'strokeWidthMax': 0.60, + 'differentailPairSpacingDefault': 0.18, 'differentailPairSpacingMin': 0.15, + 'differentailPairLenTolerMax': 1.0} # intra-pair skew 目标 ≤1 mm（§6.3） +PAIR_RULE = 'USBPAIR' +PAIR_CLEARANCE = 0.15 # 必须 ≤ 对内间距 0.18，否则整对自己判违规 +PAIRS = [('USB1', 'USB1_DP', 'USB1_DM'), + ('USB2', 'USB2_DP', 'USB2_DM'), + ('USB3', 'USB3_DP', 'USB3_DM'), + ('USB4', 'USB4_DP', 'USB4_DM'), + ('USB5', 'USB5_DP', 'USB5_DM'), + ('USB6', 'USB6_DP', 'USB6_DM'), # D13：Hub 第 6 口 → ESP32 原生 USB + ('USBUP', 'UP_DP', 'UP_DM')] # J23 USB-C → U32 上行 + +# 0.15，同刀片。两层版取 0.2 是为了走 JLC 两层标准工艺；四层能力 0.09，0.15 不加价， +# 而 133 件挤在一面上，布线通道比两层版更紧。 +MIN_CLEARANCE = 0.15 + +OPEN = ("await eda.dmt_EditorControl.openDocument('%s');" + "await new Promise(r=>setTimeout(r,2000));" % PCB) + + +def call(body, timeout=300): + r = run(OPEN + body, timeout=timeout) + if not r.get('success'): + print(u'失败: ' + json.dumps(r, ensure_ascii=False)[:600]) + sys.exit(1) + return r['result'] + + +def dump_nets(): + u"""重抓「位号.引脚 → 网名」。**每次导入变更之后必跑**。""" + r = call("const out = {};" + "for (const c of await eda.pcb_PrimitiveComponent.getAll()) {" + " const ps = await eda.pcb_PrimitiveComponent.getAllPinsByPrimitiveId(" + " c.getState_PrimitiveId());" + " out[c.designator] = ps.map(p=>[p.padNumber, p.net]); }" + "return out;") + io.open(NETS_FILE, 'w', encoding='utf-8').write(json.dumps(r, ensure_ascii=False)) + print(u'已写 _base_pcb_nets.json：%d 件' % len(r)) + return r + + +def nets(): + if not os.path.exists(NETS_FILE): + return dump_nets() + return json.load(io.open(NETS_FILE, encoding='utf-8')) + + +def check_names(): + u"""下发前先确认：要指派的网名在板上真的存在（写错名字 = 规则悬空，DRC 不报）。""" + have = set() + for _ref, pads in nets().items(): + for _pn, net in pads: + if net: + have.add(net) + miss = [n for n in sorted(set(list(NET_TRACK) + PLANE_NETS)) if n not in have] + pmiss = [p for t in PAIRS for p in t[1:] if p not in have] + if miss or pmiss: + print(u' [!!] 板上没有这些网，**不下发**：线宽/铺铜 %s；差分 %s' % (miss, pmiss)) + sys.exit(1) + return True + + +CAP_JS = u""" +const D = eda.pcb_Drc; +const cur = await D.getCurrentRuleConfiguration(); +const c = JSON.parse(JSON.stringify(cur.config)); +const multi = (await D.getRuleConfiguration( + 'JLCPCB Capability(Multiple Layers Board)')).config; +const TRACKS = %s, DW = %s, MINC = %s, PAIRRULE = %s, PAIRC = %s; +const PLANERULE = %s, PLANEMODE = %s; + +const setTrack = (e, mn, df, mx) => { + for (const k of Object.keys(e.form.data)) + Object.assign(e.form.data[k], {minValue: mn, defaultValue: df, maxValue: mx}); +}; +const T = c['Physics']['Track'], SS = c['Spacing']['Safe Spacing']; + +// 四层：外层 1 oz + 内层 0.5 oz。这两段照抄刀片 pcb_rules.py（§24.1）。 +setTrack(T['copperThickness1oz'], 0.102, 0.254, 2.54); +if (!T['copperThickness0.5oz']) { + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = 'copperThickness0.5oz'; e.isSetDefault = false; + setTrack(e, 0.089, 0.254, 2.54); + T['copperThickness0.5oz'] = e; +} +Object.assign(c['Physics']['Via Size']['viaSize'].form, + {viaOuterdiameterMin: 0.3, viaInnerdiameterMin: 0.2}); +if (!SS['copperThicknessInner0.5oz']) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = 'copperThicknessInner0.5oz'; e.isSetDefault = false; + const src = multi['Spacing']['Safe Spacing']['copperThicknessInner0.5oz'].table; + for (const k of Object.keys(e.tables)) + e.tables[k].content = JSON.parse(JSON.stringify(src)); + SS['copperThicknessInner0.5oz'] = e; +} +for (const name of Object.keys(TRACKS)) { + const f = TRACKS[name]; + const e = JSON.parse(JSON.stringify(T['copperThickness1oz'])); + e.editName = name; e.isSetDefault = false; e.unit = 'mm'; + setTrack(e, f.strokeWidthMin, f.strokeWidthDefault, f.strokeWidthMax); + T[name] = e; +} +const dp = c['Physics']['Differential Pair']['differentialPair'].form; +for (const k of Object.keys(dp.strokeWidthTables.data)) + Object.assign(dp.strokeWidthTables.data[k], + {minValue: DW.strokeWidthMin, defaultValue: DW.strokeWidthDefault, + maxValue: DW.strokeWidthMax}); +for (const k of Object.keys(dp.diffPairSpacingTables.data)) + Object.assign(dp.diffPairSpacingTables.data[k], + {minValue: DW.differentailPairSpacingMin, + defaultValue: DW.differentailPairSpacingDefault}); +dp.differentailPairLenTolerMax = DW.differentailPairLenTolerMax; +if (!SS[PAIRRULE]) { + const e = JSON.parse(JSON.stringify(SS['copperThickness1oz'])); + e.editName = PAIRRULE; e.isSetDefault = false; + for (const tk of Object.keys(e.tables || {})) + for (const row of (e.tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number') row[i] = PAIRC; + SS[PAIRRULE] = e; +} +// 安全间距全表**归一到 MINC**：≤0.2 的格子一律赋值成 MINC（不是「只抬不降」）； +// 0.254 / 0.3 那几格是孔/板边相关的，不动。 +let bumped = 0; +for (const key of Object.keys(SS)) + if (key !== PAIRRULE) + for (const tk of Object.keys(SS[key].tables || {})) + for (const row of (SS[key].tables[tk].content || [])) + for (let i = 0; i < row.length; i++) + if (typeof row[i] === 'number' && row[i] <= 0.2001 && + Math.abs(row[i] - MINC) > 1e-6) { row[i] = MINC; bumped++; } +const CZ = c['Plane']['Copper Zone']; +if (!CZ[PLANERULE]) { + const e = JSON.parse(JSON.stringify(CZ['copperRegion'])); + e.editName = PLANERULE; e.isSetDefault = false; + CZ[PLANERULE] = e; +} +for (const m of ['singleLayerPadModel', 'multiLayerPadModel']) + for (const k of Object.keys(CZ[PLANERULE].form[m].data)) + CZ[PLANERULE].form[m].data[k].connectMode = PLANEMODE; + +const ok = await D.overwriteCurrentRuleConfiguration(c); +return {ok: ok === true, bumped: bumped, name: cur.name, + track: Object.keys(T), spacing: Object.keys(SS), plane: Object.keys(CZ)}; +""" + + +def set_layers(): + u"""铜层数 → LAYERS。**必须在下发规则之前**：换层数会换基准能力集，先下规则再换等于白下。""" + r = call("const was = await eda.pcb_Layer.getTheNumberOfCopperLayers();" + "if (was !== %d) await eda.pcb_Layer.setTheNumberOfCopperLayers(%d);" + "await new Promise(r=>setTimeout(r,1500));" + "return {was: was, now: await eda.pcb_Layer.getTheNumberOfCopperLayers()," + " cfg: (await eda.pcb_Drc.getCurrentRuleConfiguration()).name};" % (LAYERS, LAYERS)) + print(u' 铜层数 %s → %s（当前配置 "%s"）' % (r['was'], r['now'], r['cfg'])) + if r['now'] != LAYERS: + print(u' [!!] 铜层数没改成 %d，不下发规则' % LAYERS) + sys.exit(1) + + +def push(): + check_names() + set_layers() + r = call(CAP_JS % (json.dumps(TRACK_RULES), json.dumps(DIFF), MIN_CLEARANCE, + json.dumps(PAIR_RULE), PAIR_CLEARANCE, + json.dumps(PLANE_RULE), PLANE_CONNECT_DIRECT)) + if not r.get('ok'): + print(u' [!!] overwriteCurrentRuleConfiguration 返回非 true，没生效') + sys.exit(1) + print(u' 规则配置已下发：线宽条目 %s' % ' '.join(r['track'])) + print(u' 安全间距归一 %d 格 → %.2f mm；配置名 "%s"' % (r['bumped'], MIN_CLEARANCE, r['name'])) + + n = call(""" +const P = %s; +let k = 0; +for (const d of await eda.pcb_Drc.getAllDifferentialPairs()) + await eda.pcb_Drc.deleteDifferentialPair(d.name); +for (const [name, p, m] of P) { if (await eda.pcb_Drc.createDifferentialPair(name, p, m)) k++; } +return k; +""" % json.dumps(PAIRS)) + print(u' 差分对 %d / %d 对' % (n, len(PAIRS))) + if n != len(PAIRS): + print(u' [!!] 有对没建上 —— 网络名在这块板上不存在') + + n = call(""" +const T = %s, PN = %s, PR = %s; +const pset = new Set(PN); +const rules = await eda.pcb_Drc.getNetRules(); +let k = 0, p = 0; +const seen = []; +for (const r of rules) { + if (r.type !== 'net') continue; + if (T[r.name]) { r['Track'] = T[r.name]; k++; seen.push(r.name); } + if (pset.has(r.name)) { r['Copper Zone'] = PR; p++; } +} +await eda.pcb_Drc.overwriteNetRules(rules); +return {track: k, plane: p, seen: seen}; +""" % (json.dumps(NET_TRACK, ensure_ascii=False), json.dumps(PLANE_NETS, ensure_ascii=False), + json.dumps(PLANE_RULE))) + print(u' 线宽指派 %d / %d 个网络' % (n['track'], len(NET_TRACK))) + if n['track'] != len(NET_TRACK): + print(u' [!!] 板上找不到: %s' % ' '.join(sorted(set(NET_TRACK) - set(n['seen'])))) + print(u' 铺铜全连接指派 %d / %d（%s）' % (n['plane'], len(PLANE_NETS), ' '.join(PLANE_NETS))) + + n = call(""" +const PAIRS = %s, RULE = %s; +const cur = await eda.pcb_Drc.getNetByNetRules(); +const old = (cur && cur['Safe Spacing']) ? cur['Safe Spacing'] : []; +const key = e => [e.net1.name, e.net2.name].sort().join('|'); +const want = new Set(PAIRS.map(([n, dp, dm]) => [dp, dm].sort().join('|'))); +const list = []; +let dropped = 0; +for (const e of old) { + if (e.rule === RULE && !want.has(key(e))) { dropped++; continue; } + list.push(e); +} +const have = new Set(list.map(key)); +let k = 0; +for (const [name, dp, dm] of PAIRS) { + const e = {net1: {type: 'net', name: dp}, net2: {type: 'net', name: dm}, + rule: RULE, copperRuleName: null, planeRuleName: null}; + if (have.has(key(e))) continue; + list.push(e); k++; +} +const ok = await eda.pcb_Drc.overwriteNetByNetRules( + {'Safe Spacing': list, 'Creepage Distance': (cur && cur['Creepage Distance']) || []}); +const back = await eda.pcb_Drc.getNetByNetRules(); +return {added: k, dropped: dropped, ok: ok === true, + now: (back['Safe Spacing'] || []).length}; +""" % (json.dumps(PAIRS), json.dumps(PAIR_RULE))) + print(u' 对内间距：新增 %d / 清掉过期 %d，现共 %d 条（%s = %.2f mm）' + % (n['added'], n['dropped'], n['now'], PAIR_RULE, PAIR_CLEARANCE)) + + call("await eda.pcb_Document.save(); return 1;") + print(u' 已保存') + print(u'') + print(u'⚠ 别去 GUI 的 设计 → 设计规则… 里换「配置」下拉框：换一次整套重置，') + print(u' %d 个网络的线宽指派立刻悬空，而 DRC 不会报错。' % len(NET_TRACK)) + print(u'⚠ 再导入一次变更之后顺序是：--dump → --push，少跑 --dump 就是拿旧网名指派。') + + +AUDIT_JS = u""" +const c = await eda.pcb_Drc.getCurrentRuleConfiguration(); +const rules = await eda.pcb_Drc.getNetRules(); +const nbn = await eda.pcb_Drc.getNetByNetRules(); +return { + cfgName: c && c.name, + layers: await eda.pcb_Layer.getTheNumberOfCopperLayers(), + track: Object.keys(c.config.Physics['Track']), + pairs: (await eda.pcb_Drc.getAllDifferentialPairs()).map(d => d.name).sort(), + assigned: rules.filter(r => r['Track'] && r['Track'] !== 'default') + .map(r => [r.name, r['Track']]).sort(), + planeAssigned: rules.filter(r => r['Copper Zone'] && r['Copper Zone'] !== 'default') + .map(r => [r.name, r['Copper Zone']]).sort(), + nbn: ((nbn && nbn['Safe Spacing']) || []).length, +}; +""" + + +def audit(): + r = call(AUDIT_JS) + bad = [] + + def chk(cond, good, msg): + print((u' [OK] ' if cond else u' [!!] ') + (good if cond else msg)) + if not cond: + bad.append(msg) + + print(u'──── 审计（配置 "%s"）────' % r['cfgName']) + chk(r['layers'] == LAYERS, u'铜层数 %d' % LAYERS, u'铜层数是 %s，应为 %d' % (r['layers'], LAYERS)) + miss = [k for k in TRACK_RULES if k not in r['track']] + chk(not miss, u'%d 条线宽条目都在' % len(TRACK_RULES), u'缺线宽条目 %s' % miss) + got = dict(r['assigned']) + wrong = [(n, got.get(n), v) for n, v in sorted(NET_TRACK.items()) if got.get(n) != v] + chk(not wrong, u'%d 个网络的线宽指派全对' % len(NET_TRACK), u'指派不对: %s' % wrong[:6]) + chk(sorted(r['pairs']) == sorted([p[0] for p in PAIRS]), + u'差分对 %d 对: %s' % (len(r['pairs']), ' '.join(r['pairs'])), + u'差分对是 %s，应为 %s' % (r['pairs'], [p[0] for p in PAIRS])) + chk(r['nbn'] == len(PAIRS), u'对内间距 %d 条' % r['nbn'], + u'对内间距 %d 条，应为 %d' % (r['nbn'], len(PAIRS))) + gotp = dict(r['planeAssigned']) + missp = [n for n in PLANE_NETS if gotp.get(n) != PLANE_RULE] + chk(not missp, u'铺铜全连接 %d 个网络' % len(PLANE_NETS), u'没指派上: %s' % missp) + print(u' ' + (u'[OK] 全部通过' if not bad else u'[X] %d 条不过' % len(bad))) + return bad + + +if __name__ == '__main__': + print(u'底板 PCB=%s（%d 层）' % (PCB, LAYERS)) + if '--dump' in sys.argv: + dump_nets() + if '--push' in sys.argv: + push() + audit() + elif '--audit' in sys.argv: + audit() + elif '--dump' not in sys.argv: + check_names() + print(u'线宽规则:') + for k, v in sorted(TRACK_RULES.items()): + print(u' %-8s 默认 %.2f 最小 %.2f 最大 %.2f' + % (k, v['strokeWidthDefault'], v['strokeWidthMin'], v['strokeWidthMax'])) + print(u'网络指派:') + for k, v in sorted(NET_TRACK.items()): + print(u' %-12s → %s' % (k, v)) + print(u'差分对 %d：%s' % (len(PAIRS), ' '.join(p[0] for p in PAIRS))) + print(u'安全间距 %.2f；铺铜全连接 %s' % (MIN_CLEARANCE, ' '.join(PLANE_NETS))) diff --git a/.claude/r2/schcheck.py b/.claude/r2/schcheck.py new file mode 100644 index 0000000..9a5de6c --- /dev/null +++ b/.claude/r2/schcheck.py @@ -0,0 +1,319 @@ +# -*- coding: utf-8 -*- +u"""R2 原理图页脚本的公共部分：几何自检 + 下发。 + +`b2_ctrl.py` 里那一套（本地并查集反推 + 旗端口端点判据 + 文字越界）抽出来复用， +`b3_phone.py` / `b3b_usb.py` / `b4_edge.py` 都吃这一份。 + +判据出处见 `easyeda-sch-geometry` skill： +§3/§8a-2b 坐标必须是 5 的倍数、§8a-2/§8a-3 旗端口必须落在导线端点且不能是母线中段、 +§10b 推送前先本地反推网表、§12 文字宽度经验值、§9c 分批下发、§6b/§6c 放完读回断言。 +""" +import io +import json +import os +import sys +from collections import defaultdict + +HERE = os.path.dirname(os.path.abspath(__file__)) +# ⚠ `.claude` 下有和 r2 同名的 R1 脚本（pcb_pour / pcb_rules / pcb_place）。 +# 只插父目录的话，**后面任何一个 `import pcb_rules` 都会拿到 R1 那一份**， +# 而且不报错，只在调到 R2 专有的函数时才炸（2026-09-08 踩过）。 +# 规矩：两行都要写，HERE 后插（在 sys.path 最前）。 +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 + +PARTS = json.load(io.open(os.path.join(os.path.dirname(HERE), 'eda-parts.json'), + encoding='utf-8'))['parts'] + + +def call(js, timeout=180): + r = run(js, timeout=timeout) + if not r.get('success'): + raise RuntimeError(json.dumps(r, ensure_ascii=False)[:900]) + return r['result'] + + +class Sheet(object): + u"""攒一页的导线 / 旗 / 端口 / 文字，带下发前的全部自检。""" + + def __init__(self, page, name): + self.page, self.name = page, name + self.W, self.F, self.PT, self.TX = [], [], [], [] + + # ── 声明 ────────────────────────────────────────────────────────── + def w(self, net, *pts): + for a, b in zip(pts, pts[1:]): + if a != b: + self.W.append((a, b, net)) + + def gnd(self, x, y, rot): + self.F.append(['Ground', 'GND', x, y, rot]) + + def pwr(self, net, x, y, rot): + self.F.append(['Power', net, x, y, rot]) + + def port(self, d, net, x, y, rot): + self.PT.append([d, net, x, y, rot]) + + def txt(self, x, y, s, size=10): + self.TX.append((x, y, s, size)) + + # ── 自检 ────────────────────────────────────────────────────────── + def assert_grid(self): + for a, b, net in self.W: + assert (a[0] == b[0]) != (a[1] == b[1]), \ + u'%s 段不是横平竖直: %s->%s' % (net, a, b) + for v in (a[0], a[1], b[0], b[1]): + assert v % 5 == 0, u'%s 坐标 %d 不是 5 的倍数' % (net, v) + for it in self.F + self.PT: + assert it[2] % 5 == 0 and it[3] % 5 == 0, \ + u'旗/端口 %s 坐标不是 5 的倍数' % (it[1],) + assert 20 <= it[2] <= 1145 and 10 <= it[3] <= 812, \ + u'旗/端口 %s 出框' % (it[1],) + # 文字越界（skill §12 宽度经验值 + §8c 标题栏 x>455 且 y<192） + for x, y, s, size in self.TX: + cjk = sum(1 for ch in s if ord(ch) > 0x2E7F) + right = x + size * (cjk + 0.5 * (len(s) - cjk)) + limit = 455 if y < 192 else 1145 + assert right <= limit, \ + u'文字右边界 %.0f 越过 %d（y=%d）: %s' % (right, limit, y, s[:24]) + + def netcheck(self, pins, nc, allow_split): + u"""并查集反推 + 与声明的网络名比对。返回错误列表。""" + errs = [] + W = self.W + n = len(W) + par = list(range(n)) + + def find(i): + while par[i] != i: + par[i] = par[par[i]] + i = par[i] + return i + + for i in range(n): + for j in range(i + 1, n): + a1, a2, _ = W[i] + b1, b2, _ = W[j] + if (_on(a1, b1, b2) or _on(a2, b1, b2) + or _on(b1, a1, a2) or _on(b2, a1, a2)): + ri, rj = find(i), find(j) + if ri != rj: + par[ri] = rj + grp = defaultdict(list) + for i in range(n): + grp[find(i)].append(i) + pieces = defaultdict(int) + for _root, idx in grp.items(): + names = sorted(set(W[i][2] for i in idx)) + if len(names) > 1: + errs.append(u'短路: ' + ' + '.join(names) + u' :: ' + ' | '.join( + '%s%s-%s' % (W[i][2], W[i][0], W[i][1]) for i in idx[:6])) + pieces[names[0]] += 1 + for name, cnt in sorted(pieces.items()): + if cnt > 1 and name not in allow_split: + errs.append(u'网络 %s 被拆成 %d 块（漏连）' % (name, cnt)) + + for d, pd in pins.items(): + for num, xy in pd.items(): + if num in nc.get(d, []): + continue + if not any(_on(tuple(xy), s[0], s[1]) for s in W): + errs.append(u'悬空引脚: %s.%s @ %s' % (d, num, tuple(xy))) + + for kind, lst in ((u'旗', self.F), (u'端口', self.PT)): + for it in lst: + p = (it[2], it[3]) + through = any( + (s[0][0] == s[1][0] and p[0] == s[0][0] + and min(s[0][1], s[1][1]) < p[1] < max(s[0][1], s[1][1])) + or (s[0][1] == s[1][1] and p[1] == s[0][1] + and min(s[0][0], s[1][0]) < p[0] < max(s[0][0], s[1][0])) + for s in W) + ends = [s for s in W if s[0] == p or s[1] == p] + if through: + errs.append(u'%s %s @ %s 压在导线中段' % (kind, it[1], p)) + elif not ends: + errs.append(u'%s %s @ %s 不在任何导线端点上' % (kind, it[1], p)) + else: + ax = set(('V' if s[0][0] == s[1][0] else 'H') for s in ends) + if len(ends) > 1 and len(ax) == 1: + errs.append(u'%s %s @ %s 两段共线，合并后会变成中段' + % (kind, it[1], p)) + return errs + + def crossings(self): + u"""不相连的交叉点。不是错误，但要人眼确认可读性。""" + out = [] + W = self.W + for i in range(len(W)): + for j in range(i + 1, len(W)): + a1, a2, na = W[i] + b1, b2, nb = W[j] + if na == nb: + continue + ha, hb = a1[1] == a2[1], b1[1] == b2[1] + if ha == hb: + continue + h, v = ((a1, a2), (b1, b2)) if ha else ((b1, b2), (a1, a2)) + y, x = h[0][1], v[0][0] + if (min(h[0][0], h[1][0]) < x < max(h[0][0], h[1][0]) + and min(v[0][1], v[1][1]) < y < max(v[0][1], v[1][1])): + out.append((na, nb, x, y)) + return out + + # ── 下发 ────────────────────────────────────────────────────────── + def clear(self): + n = call(""" + await eda.dmt_EditorControl.openDocument('%s'); await new Promise(r=>setTimeout(r,1200)); + const nm=(await eda.dmt_Schematic.getCurrentSchematicPageInfo()).name; + if (nm!=='%s') throw new Error('page='+nm); + let k=0; + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()==='sheet') continue; + await eda.sch_PrimitiveComponent.delete(c.getState_PrimitiveId()); k++; + } + for (const w of await eda.sch_PrimitiveWire.getAll()) await eda.sch_PrimitiveWire.delete(w.getState_PrimitiveId()); + for (const t of await eda.sch_PrimitiveText.getAll()) await eda.sch_PrimitiveText.delete(t.getState_PrimitiveId()); + return k; + """ % (self.page, self.name)) + print(u'%s 已清空（删掉 %d 个图元）' % (self.name, n)) + + def place(self, place, exp): + u"""放件 -> 认领位号 -> 逐脚回读比对，对不上就翻 180 重试（skill §6b/§6c）。""" + put = [] + for d, lcsc, x, y, rot in place: + assert lcsc in PARTS, u'eda-parts.json 里没有 %s' % lcsc + put.append([d, PARTS[lcsc]['uuid'], x, y, rot, PARTS[lcsc]['lib']]) + for it in put: + assert len(it) == 6 and it[5], u'placement 少了 libraryUuid: %s' % (it,) + for i in range(0, len(put), 4): + call(""" + for (const [d,uuid,x,y,rot,lib] of %s){ + await eda.sch_PrimitiveComponent.create({libraryUuid:lib, uuid}, x, y, undefined, rot, false, true, true); + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + if (Math.round(c.getState_X())!==x || Math.round(c.getState_Y())!==y) continue; + await c.toAsync().setState_Designator(d).done(); + } + } + return 1; + """ % json.dumps(put[i:i + 4])) + # ⚠ skill §6e：`create(..., rot)` 在 rot=90/270 时，**紧接着读回的引脚坐标是错的** + # —— 实测（A2-AUX 空页，0402 电容 rot 90）： + # create 之后第一次读 pin1 (0,+20) / pin2 (0,−20) + # 再写一次 setState_Rotation(90) 之后 pin1 (0,−20) / pin2 (0,+20) + # 两者差 180°，非极性件看不出来，**极性件（电解、TVS、二极管）就是接反**。 + # 下面这一遍「用同一个角度再写一次」把内部状态刷正，读回才是真的。 + # 不做这一步的话，下面那个翻转重试循环会绕两圈才碰对， + # 而且真有一件放错时，循环可能替它「碰」出一个假的通过。 + call(""" + for (const [d,rot] of %s){ + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + if (c.getState_Designator()!==d) continue; + await c.toAsync().setState_Rotation(rot).done(); + } + } + return 1; + """ % json.dumps([[d, rot] for d, _l, _x, _y, rot in place])) + print(u'已放置 %d 个元件' % len(put)) + + READ = """ + const out={}; + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + out[c.getState_Designator()] = (await c.getAllPins()).map( + p=>[p.getState_PinNumber(), Math.round(p.getState_X()), Math.round(p.getState_Y())]); + } + return out; + """ + rots = dict((d, rot) for d, _l, _x, _y, rot in place) + for rnd in range(4): + got = call(READ) + bad = [] + for d, want in exp.items(): + if d not in got: + raise SystemExit(u'读不到元件 %s' % d) + have = dict((p, (x, y)) for p, x, y in got[d]) + if '?' in want: + if set(have.values()) != want['?']: + bad.append((d, sorted(want['?']), sorted(have.values()))) + else: + for p, xy in sorted(want.items()): + if have.get(p) != xy: + bad.append((d, p, xy, have.get(p))) + break + if not bad: + print(u'引脚坐标逐个核对通过（%d 个元件）' % len(exp)) + return + if rnd == 3: + raise SystemExit(u'引脚坐标对不上：\n ' + + '\n '.join(repr(b) for b in bad)) + names = sorted(set(b[0] for b in bad)) + print(u'第 %d 轮：翻转 %d 件重试 %s' % (rnd + 1, len(names), names)) + call(""" + for (const [d,rot] of %s){ + for (const c of await eda.sch_PrimitiveComponent.getAll()){ + if (c.getState_ComponentType()!=='part') continue; + if (c.getState_Designator()!==d) continue; + await c.toAsync().setState_Rotation(rot).done(); + } + } + return 1; + """ % json.dumps([[d, (rots[d] + 180 * (rnd + 1)) % 360] for d in names])) + + def push_geometry(self): + def batch(items, size, js): + for i in range(0, len(items), size): + call(js % json.dumps(items[i:i + size], ensure_ascii=False)) + + batch([[a[0], a[1], b[0], b[1]] for a, b, _ in self.W], 40, + "for (const s of %s) await eda.sch_PrimitiveWire.create(s); return 1;") + batch(self.PT, 25, "for (const p of %s) await eda.sch_PrimitiveComponent.createNetPort(p[0],p[1],p[2],p[3],p[4],false); return 1;") + batch(self.F, 25, "for (const f of %s) await eda.sch_PrimitiveComponent.createNetFlag(f[0],f[1],f[2],f[3],f[4],false); return 1;") + batch([list(t) for t in self.TX], 12, + "for (const t of %s) await eda.sch_PrimitiveText.create(t[0],t[1],t[2],0,null,null,t[3],false,false,false,0); return 1;") + print(u'推送完成') + + def report(self, nparts, errs): + print(u'元件 %d 导线 %d 旗 %d 端口 %d 文字 %d' + % (nparts, len(self.W), len(self.F), len(self.PT), len(self.TX))) + xs = self.crossings() + print(u'交叉点（不相连，供人工确认）: %d' % len(xs)) + for c in xs: + print(u' %s x %s @ (%d,%d)' % c) + if errs: + print(u'本地自检 %d 条问题：' % len(errs)) + for e in errs: + print(u' ! ' + e) + raise SystemExit(1) + print(u'本地自检通过（短路 0 / 漏连 0 / 悬空 0 / 旗端口全在端点）') + + +def _on(p, a, b): + if a[0] == b[0]: + return p[0] == a[0] and min(a[1], b[1]) <= p[1] <= max(a[1], b[1]) + return p[1] == a[1] and min(a[0], b[0]) <= p[0] <= max(a[0], b[0]) + + +def two_pin(x, y, half=20): + u"""两脚件的期望：只比坐标集合（非极性件翻转只换脚号，无害）。""" + return {'?': set([(x, y + half), (x, y - half)])} + + +def by_rel(x, y, rel): + return dict((k, (x + dx, y + dy)) for k, (dx, dy) in rel.items()) + + +def pins_of(exp): + u"""把 EXPECT 摊平成 netcheck 要的 {位号: {脚号: (x,y)}}。""" + out = {} + for d, want in exp.items(): + if '?' in want: + a, b = sorted(want['?']) + out[d] = {'1': a, '2': b} + else: + out[d] = dict(want) + return out diff --git a/.claude/r2/shot_base.py b/.claude/r2/shot_base.py new file mode 100644 index 0000000..9825af2 --- /dev/null +++ b/.claude/r2/shot_base.py @@ -0,0 +1,32 @@ +# -*- coding: utf-8 -*- +u"""截底板 PCB 的当前渲染：python .claude/r2/shot_base.py + +`.claude/shot.py` 是原理图版（读 dmt_Schematic 的页名），PCB 页上会抛错，所以另起这一份。 +""" +import base64 +import json +import os +import sys + +HERE = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, os.path.dirname(HERE)) +sys.path.insert(0, HERE) +from eda import run # noqa: E402 +import pcb_base as B # noqa: E402 + +out = sys.argv[1] +js = """ +const sleep = ms => new Promise(r => setTimeout(r, ms)); +await eda.dmt_EditorControl.openDocument('%s'); +await sleep(1500); +await eda.dmt_EditorControl.zoomToAllPrimitives(); +await sleep(1500); +const img = await eda.dmt_EditorControl.getCurrentRenderedAreaImage(); +const bytes = new Uint8Array(await new Response(img).arrayBuffer()); +let s=''; for (let i=0;i', out) diff --git a/.claude/r2/tree.js b/.claude/r2/tree.js new file mode 100644 index 0000000..af013cb --- /dev/null +++ b/.claude/r2/tree.js @@ -0,0 +1,7 @@ +const cur = await eda.dmt_Project.getCurrentProjectInfo(); +const boards = (await eda.dmt_Board.getAllBoardsInfo() || []).map(b => b.name); +const schs = (await eda.dmt_Schematic.getAllSchematicsInfo() || []).map(s => [s.uuid, s.name]); +const pcbs = (await eda.dmt_Pcb.getAllPcbsInfo() || []).map(p => [p.uuid, p.name]); +const pages = (await eda.dmt_Schematic.getAllSchematicPagesInfo() || []) + .map(p => [p.parentSchematicUuid, p.uuid, p.name]); +return { project: [cur.uuid, cur.friendlyName], boards, schs, pcbs, pages }; diff --git a/.claude/sch_text.py b/.claude/sch_text.py index fefb7b9..3553b9b 100644 --- a/.claude/sch_text.py +++ b/.claude/sch_text.py @@ -52,9 +52,9 @@ TEXT = { ], 'P3B': [ # ⚠️ 这三行右边 x=445 起是【B】PCA9555 那一块，末端要留在 430 以内 - (45, 806, u'【A】74HC595 ×3 的前两片（U21 / U22）'), - (45, 795, u'链序 U21 → U22 → U33（在 P6），整条链 24 位；'), - (45, 784, u'SRCLK/RCLK/OE# 三片共用，OE# 上拉 100k ⇒ 复位全高阻'), + (45, 806, u'【A】（已搬走）74HC595 ×3 与 15 颗按键 MOS 2026-09-06 整窝挪到载板'), + (45, 795, u'（载板 C6-KEYS / C4-SITEn，§26.23）。KEY_SER/SRCLK/RCLK/OE#'), + (45, 784, u'四根线从 P3 的 ESP32 直接去 P5-BTB 的 J25 北排 3~6 行。'), (445, 790, u'【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）'), (445, 779, u'IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，'), (445, 768, u'固件严禁把 Port0[7] / Port1[7:5] 配成输出。'), @@ -69,11 +69,8 @@ TEXT = { (45, 111, u'U7 = VDAC3/5（去东半板）。四通道对等，只改固件通道号。'), ], 'P6': [ - (45, 806, u'【A】第三片 74HC595（U33）—— CH2 / CH3 的六个侧键 + EDL_EN1 + HUB_RST'), - (45, 790, u"级联在 U22 之后：U22.QH'(9) -> U33.SER(14)，网络名 SR_CAS2，整条链 24 位。"), - (45, 774, u'2026-09-06 按 PCB 几何重排（§26.18）：U33 在 y≈70 mm，正对北排的 CH2 / CH3，'), - (45, 758, u'比原来从 U21(y≈50) 拉过去近 20~30 mm。Q0=EDL_EN1，Q1~Q3=K2，Q4~Q6=K3，Q7=HUB_RST。'), - (45, 742, u'EDL_EN 与按键的 100k 下拉不放这一页 —— 放在载板上紧挨模拟开关（§8.1 复位安全）。'), + (45, 806, u'【A】（已搬走）第三片 74HC595（U33）2026-09-06 随整条链挪到载板 C6-KEYS（§26.23）。'), + (45, 790, u'EDL_EN1~5 / HUB_RST 从此是载板内部网络，不再过排针。这一页只剩风扇。'), (45, 520, u'【B】风扇：低边 N-MOS + PWM，5 个风扇并一路（§22.6）'), (45, 500, u'Q6 AO3400A 切风扇回流，D2 SS34 做续流 —— 风扇是感性负载，'), (45, 484, u'少了它 MOS 会被反峰打穿。FAN_PWM = IO18（模块脚 11），FAN_TACH = IO16（模块脚 9）。'), diff --git a/.claude/shot_pcb_layers.py b/.claude/shot_pcb_layers.py index fcc03b2..eb15050 100644 --- a/.claude/shot_pcb_layers.py +++ b/.claude/shot_pcb_layers.py @@ -3,7 +3,7 @@ u"""只显示指定铜层截一张 PCB 图，截完把图层可见性恢复原 /c/Python314/python .claude/shot_pcb_layers.py <层号,逗号分隔> [pcbUuid] [x0 y0 x1 y1] -例：`shot_pcb_layers.py L2-inner1.png 15,12 f126ffb29c92f9b2` +例：`shot_pcb_layers.py L2-inner1.png 15,12 942ed1560d81c1e7` —— 15 = Inner1，12 = 多层（通孔焊盘），不带这一层的话内层看不到焊盘位置。 ⚠️ `setLayerVisible(list, true)` 的第二个参数是「把其余层设为不可见」。 @@ -17,7 +17,7 @@ from eda import run out = sys.argv[1] layers = [int(v) for v in sys.argv[2].split(',')] -uuid = sys.argv[3] if len(sys.argv) > 3 else 'f126ffb29c92f9b2' +uuid = sys.argv[3] if len(sys.argv) > 3 else '942ed1560d81c1e7' MIL = 39.3701 # 可选的框选区域（mm）。⚠️ zoomToRegion 的参数顺序是 (left, right, top, bottom)。 if len(sys.argv) > 7: diff --git a/.claude/skills/easyeda-sch-geometry/SKILL.md b/.claude/skills/easyeda-sch-geometry/SKILL.md index bc471e4..25b3558 100644 --- a/.claude/skills/easyeda-sch-geometry/SKILL.md +++ b/.claude/skills/easyeda-sch-geometry/SKILL.md @@ -1362,3 +1362,447 @@ DRC 照样报旧线的错 —— 看上去就是「改了没生效」。 顺带：把多个库 API 塞进同一个 `/execute` 里跑，其中一个挂住（本次是 `lib_LibrariesList` / `lib_Classification`） 整条请求 30 s 超时，**但前面已经执行的 create/copy 仍然生效** —— 超时后先去库里搜一遍有没有留下半成品再重试。 + +## 9z. 改库里的器件**不会传到原理图实例** —— 换封装要走「封装管理器」的 DOM（2026-09-07）⚠️⚠️ + +**现象**：`lib_Device.modify()` 把器件 `1c8e0ea1…` 的封装换成 `PAD-D1.5_MI8-KEY` 之后， +原理图里 20 个 J41~J60 的 `footprint` 仍是 `POGO-SMD1P_D1.9`，`component.uuid` 甚至指向一个 +`lib_Device.get()` 已经查不到的旧 uuid（`7904eff7…`）—— 实例是放置时的快照，和库脱钩。 +于是「从原理图导入变更」一行都不出。 + +**API 改不动**：`sch_PrimitiveComponent.modify()` 的签名里没有 `footprint` / `component`， +塞进去被静默忽略（实测读回不变）。`更新工程库...` 菜单只弹出一个「封装需要关联器件」的提示框。 + +**能用的路**：原理图页 **工具 → 封装管理器...**（`lc_modal_dialog_box_*` 模态框），全程 DOM： + +1. 左表 `input[placeholder="过滤"]` 用 React 的 value setter + `input` 事件填旧封装名，只剩要换的行； + 表是**虚拟滚动**的（`lc-table-body_*`，一次只渲染 ~12 行），要边 `scrollTop += 60` 边找 `J41…J60` 的叶子元素； + 点**叶子文本元素**（不是 ``）才选中（`lc-table-row--selected_*`），`ctrlKey: true` 累加多选，20 个逐个点。 +2. 右侧点「个人」页签（`div.tree-content_*`），`input[placeholder^="搜索"]` 填封装名 + Enter， + 结果表里点封装那一格的叶子。 +3. ⚠️ **「更新」按钮要等右下「检查封装尺寸」表出现焊盘尺寸（`1|1.5 * 1.5`）才会去掉 `*_disabled_*` 类** + —— 之前 `onClick` 调了也没反应、模态还在、封装没变。等 1~2 s 再点，toast「更新成功!」， + 左表按旧名过滤会变空（因为都换掉了）。 +4. 读回：`c.footprint.name` 全变新名（uuid 是**工程库副本**的新 uuid，不是个人库那个），`component` 仍指旧器件 —— 不影响导入。 + +**BOM 字段在实例上**：`sch_PrimitiveComponent.modify(id, {addIntoBom: false})` 生效； +`manufacturer / manufacturerId / supplier / supplierId` 传 `''` 或 `null` 都被忽略 —— 清不掉，靠 addIntoBom=false 把它挡在 BOM 外。 + +**顺带**：`lib_Device.modify` 的 `property`（Add into BOM 等）同样被忽略（§上一轮），所以这两处都不要指望 API。 + +⚠️ 一个卡了半小时的假象：之前留在页面上的「封装需要关联器件使用…/ 关联器件 / 取消」提示框 +（`lc-tips-modal-*`，`fp_keypad.py` 的 `openInEditor` 留下的）会挡住后面所有菜单动作， +菜单探测脚本第一件事先把可见的「取消」按钮点一遍。 + +## 9aa. PCB 收尾顺序：reload 会丢铺铜填充，API 新建的铜要 reload 之后 DRC 才认（2026-09-07）⚠️⚠️ + +第三十轮实测（载板）： + +- `pcb2_reload.py`（关对话框 → 存盘 → 页面 reload）之后 `getState_PourFills` 回读 **0 块** —— 填充没了， + 只剩铺铜边框。此时跑 DRC 会把所有只靠内层铜面连通的对象（GND 397 条、VOn_P 65 条）全报「断开」。 +- 反过来，用 API 新建了几百段导线之后**不 reload 直接 DRC**，刚建的那几个网络成片报「与其他相同网络的对象断开」 + （171 条），reload 之后同一份数据 DRC 归零 —— 连接性索引不跟着 API 创建更新。 +- ⇒ **固定顺序：`pcb2_reload.py` → `pcb2_pour.py --push` → `inner1_verify.py` → `drc_read.py --pcb2`**。 + pour 之后不许再 reload；DRC 之前必须 reload 过一次。 + +DRC 面板里的图元 ID（`e16831` 这种）**不是** `getState_PrimitiveId()`，`pcb_PrimitiveLine.get('e16831')` 返回空数组； +要定位只能按网络 + 坐标自己找（`_drc_conn.py` 读分类明细，再用几何去对）。 + +## 9ab. 「挖槽区域」= 封装自带的 NPTH，不是 layer 12 填充（2026-09-07） + +DRC 报「挖槽区域 到 过孔 0mil」的 `e56`，在 `pcb_PrimitiveFill.getAll()`（只有 10 条穿线槽）和 `pcb_PrimitiveRegion`（空）里都找不到 —— +它是 J23 封装自带的 Ø0.6 非金属化孔（§9u 说过 API 读不出来，`pcb2_npth.py --write` 反解出的 `_pcb2_npth.json`）。 +布线脚本要把这份清单当无网络的通孔盘加进障碍表（`pcb2_route_dp.geom()` 已加）。 + +## 9ac. `pcb_PrimitiveLine.create()` 建一条穿过本网焊盘的线，会在焊盘中心截断（2026-09-07）⚠️ + +实测（载板 KEY_RCLK 穿 U22.12）：路径 (126.896,66.7)→(126.865,70.521) 从焊盘中心 (126.865,69.236) 旁 0.01 mm 穿过去接出线段末端， +建完板上只剩 (66.7→69.236) 那一半，后半段和同位置的出线段一起没了，DRC 报焊盘 + 一个过孔「断开」。 +而两条**完全重合**的线 create 两次只留一条（后建的替换先建的）。 +⇒ 下发前把离本网焊盘中心 < 0.15 mm 的线段在中心处拆成两段（`pcb2_route_sig.push_sig` 已做），别让任何一段"穿过"焊盘。 + +## 6e. SOT-23 想要「G 左 / S 上 / D 下」只能靠 **rot + mirror**（2026-09-07）⚠️ + +画高边 P-MOS（源极接 +12V 在上、漏极接负载在下、栅极朝左）时， +**单靠 rotation 做不出来**。四种组合实测（AO3401A `be56508f…`，偏移是相对元件中心）： + +| create 参数 | G | S | D | 用在 | +|---|---|---|---|---| +| `rot 0, mirror false` | 左 (−20,0) | **下** (+10,−20) | 上 (+10,+20) | 低边 N-MOS（源极接地）| +| `rot 0, mirror true` | **右** (+20,0) | 下 (−10,−20) | 上 (−10,+20) | **栅极朝右接收信号**（信号从右往左流的接收电路）| +| `rot 180, mirror false` | 右 (+20,0) | 上 (−10,+20) | 下 (−10,−20) | —— | +| **`rot 180, mirror true`** | **左 (−20,0)** | **上 (+10,+20)** | **下 (+10,−20)** | **高边 P-MOS** | + +`mirror` 是**水平镜像**（只把 G 换到另一侧），rot 180 才上下翻。两个都要才凑得出第四行。 + +P6 的两路 TACH 接收就是靠第二行：原始信号从右边的风扇座过来， +栅极朝右接住，漏极向上接 3V3 上拉、源极向下接地 —— 一根绕线都不用。 + +⚠️ `mirror` 只影响原理图符号，不镜像 PCB 封装。但**放完照样要 `getAllPins()` 断言**（§6c）。 + +## 2b. `createNetFlag('Power', …)` 的网络名可以是任意串（2026-09-07） + +不限于 `+3V3` / `+12V` / `+5V`。实测 `createNetFlag('Power', 'FAN_12V_SW', x, y, 0, false)` +读回来就是 `FAN_12V_SW`，rot 0 / 180 都一样。 + +⇒ **开关后的电源轨（本项目的 `FAN_12V_SW`）用电源旗最省事**： +7 个接点各挂一个旗，不用画母线，也不会像 netport 那样被 `xpage.py` 当成漏接 +（旗有 7 个实例）。真正只有一个实例的局部网络才需要进 `xpage.NAMING_ONLY`。 + +⚠️ 但 §3b 那条不变：**旗建好之后不能移动、不能改名**，只能删了重建。 + +## 12a. 地旗的 `GND` 字样掉在符号下方约 15 个单位（2026-09-07） + +`createNetFlag('Ground','GND',x,y,0)` 的符号占 `y−20 ~ y`，但**文字还在更下面**， +大约 `y−28 ~ y−15`。所以「旗底 y−20 以下就安全」是错的，实际要留到 **y−30**。 + +实测踩到：P6 的地旗放在 `(250,225)`，把 `y=190` 那一行标题压掉了一半。 +`verify_sch.py` / `port_audit.py` / 本地几何自检**四道全过** —— 这类问题只有截图看得见。 + +⇒ 本地自检里给旗留净空按 **30** 算，不是 20。同理端口标签的纵向净空按 ±10 算。 + +## 8a-3. 旗放在「自己分两段建的母线」中点上 —— 照样不连（2026-09-07）⚠️⚠️ + +§8a-2 的第三种成因，比前两种更容易上当，因为**看起来是端点**。 + +给一排电阻做共地母线时的自然写法：把母线拆成两段，让旗的位置正好是两段的公共端点。 + +```python +w('GND', (190, 250), (230, 250)) # 以为 (230,250) 是端点 +w('GND', (230, 250), (310, 250)) +F.append(('Ground', 'GND', 230, 250, 0)) +``` + +**EasyEDA 会把共线的两段合并成一条** `(190,250)→(310,250)`， +于是旗又落回中段，判定不相连。 + +实测（C2-HUB 的 R903~R906 共地母线）：旗放在 x=250（几颗电阻分支点之间的空档）时， +PCB 网表里那四颗的地端是 **`$16N236` 而不是 `GND`**； +而右边那条母线的旗恰好放在 x=820 = R907 的分支点上，就正常。 + +**判据：旗/端口的坐标必须是某条「真的从别处接进来」的导线的端点** —— +也就是那里得有一根**垂直方向**的支线（元件的引出线）落进来，光靠把水平母线切两段没用。 + +两种可靠写法： + +1. **把旗放在某颗元件的分支点上**（本项目采用：`LBUS = (190, 310, 230)`，230 是 R905 的分支 x）； +2. 给旗单独接一根**拐弯的**短线：`w('GND', (250,250), (250,225))` 再把旗放 `(250,225)`。 + +⚠️ **`verify_sch.py` 抓不到**（它的判据是「落在某条线段上」）， +`port_audit.py` 在旗被合并线包住时也可能放过。 +**真正的判据是 PCB 那边的网表** —— 从原理图导入变更之后， +把关键网络的焊盘网名读回来对一遍（`pcb_PrimitivePad.getState_Net()`）， +共地/共电源的那一组尤其要看。本项目就是靠这一步抓到的。 + +--- + +## 9o-2. 「从原理图导入变更」按 **uniqueId** 配对，不是按位号 —— 错位时它会提出一份**看着像在修错、实则会改坏板子**的清单（2026-09-08）⚠️⚠️⚠️ + +§9o 说整页重画会让元件 uuid 全新。**后果比"摆位归零"严重得多**： +重画那一页的元件 `uniqueId` 会整体重编，而 PCB 侧还是旧的一套。 +导入对话框按 uniqueId 把两边配对，于是**整块区域错开一格**。 + +下板 2026-09-08 实测（P6-FAN-EDL 重画过）： + + 位号 PCB 原理图 + J26 gge418 gge419 + J27 gge419 gge420 ← 板上 J27 拿着原理图 J26 的 ID + Q9 gge423 gge424 + R753 gge413 gge414 + +全板 301 件里错了 20 个，**全在那一页，整齐地差 +1**。 +对话框据此提出：`J27→J26`、`Q10→Q9`、`R753→R752`、`Q7` 换成 4 脚座封装、 +`R747` 换成 DC 座封装…… 一大串「改位号 / 改封装 / 改网络」。 + +### ⛔ 最贵的一点：那份清单**看起来像在修真错误** + +它会说 `修改网络 J26:3 FAN_OUT_TACH_RAW → FAN_IN_TACH_RAW`， +而 J26 确实是进风扇、确实该是 `IN` —— 于是很容易得出「板子接反了，导入正好修好它」。 +**实际是反的**：板上 J26.3 本来就是 `FAN_IN_TACH_RAW`， +对话框说的那个「J26」是它配错的那个对象（板上的 J27）。应用下去才真的接反。 + +### 判据：不要拿对话框当判据，按**四项**直接对账 + +对话框是**结果**不是**原因** —— 它用错位的配对去算差异，算出来的自然也是错位的。 + +| 对账项 | 怎么查 | 能不能单独定案 | +|---|---|---| +| 位号 | `pcb1_import.py --verify` | ❌ 光这个不够 | +| 封装名 | 同上 | ❌ **同封装之间的错位它看不见**（J26/J27 都是 `CONN-TH_4P`，Q9/Q10 都是 SOT-23-3）| +| **器件值** | 两边 `getState_Component().name` 按位号比 | ❌ 同型号之间也看不见 | +| **焊盘网络** | PCB `pad.getState_Net()` vs 原理图连通性 | ✅ 这一项才有判别力 | + +四项全对 = 板子是对的，对话框在胡说。任何一项对不上 = 先查 uniqueId 再说。 + +### 修法：把 PCB 的 uniqueId 按位号写成原理图的那一套 + +`pcb_PrimitiveComponent` 上**有 `setState_UniqueId()`**（`setState_Footprint` 没有， +所以换封装只能删了重建，见 §9z 一节的 PCB 版）。 + +⚠️ **必须两阶段写**：这是一个**排列**（J27 的 ID 要给 J26）， +直接按目标值挨个写会在中途出现两个元件同 ID。 +先全部写成临时值（`zzsync`），再写成目标值。 + +⚠️ 改的是**元件身份**，`DRC / 几何检查 / 连通性一条都不会报` —— +唯一的验收是「重开导入对话框看它还剩几条」。写之前先存快照。 + +`.claude/pcb1_uid_sync.py` 就是这件事：对账 → 两阶段写 → 回查逐个一致且无重号。 +下板实测：20 处对齐之后，变更清单从一大串塌成**一行** +（`J1:通道ID (空) → $1I219`，那是 API 新建的元件本来就没有通道ID）， +应用之后再开对话框 **0 条变更**，而风扇块 20 件的焊盘网络逐条未变。 + +> 💡 `getState_UniqueId()` 返回的 `ggeNNN` 和对话框里显示的「通道ID」`$17I175` +> 不是同一个字段，但**配对用的是前者** —— 对齐 `ggeNNN` 之后错位就消失了。 + +## 9o-3. 读导入对话框：**别用滚动容器的 `innerText`**（2026-09-08） + +那张表是**多列分开渲染**的，`offsetTop` 在列之间碰撞。 +按 `innerText` 拼接读出来，表头（位号）和明细行会被拼错， +读出来的清单似是而非 —— 同一份数据能读出两种互相矛盾的「错位方向」。 + +逐 `` 读、每行自带单元格（`.claude/p1_import_rows2.py`）才是对的。 +**但即使读对了，结论仍以上面那四项对账为准。** + + +## 9ah. 「假板框」不止坑摆位 —— 校核脚本的**栅格原点**同样会把负坐标静默吃掉（2026-09-08）⚠️⚠️ + +本项目的板框在两板对齐那一轮从 `160×125 @(0,0)` 改成了 `220×135 @(−30,−5)`。 +`pcb1_place.py` 当时改了，**`pcb1_pour.py` 没改** —— 它的栅格一直是 +`nx, ny = int(BW/G), int(BH/G)` 加 `int(x / G)`，从 (0,0) 起索引。 + +平时看不出来：所有铜都在第一象限。直到把元件挪到 x<0 —— 三块顶层铺铜 +当场报「碎成 0 块」「断面 0.00 mm」。**板上的铜其实没问题** +（多边形是原样下发给 EasyEDA 的，由它去填），坏的只是本地校核。 + +⇒ 判据：**校核报 0 而实测回读正常时，先怀疑校核的坐标系，别去改设计。** + 两边对不上，信实测那一边（`--verify` 读 `getState_PourFills()`）。 + +修法是把毫米↔栅格收进四个函数（`gi/gj/gx/gy`），**禁止再直接写 `int(x / G)`**。 + +### 9ah-2. ⛔ 但改共享常量会**震到别的模块**，而且是静默的 + +`pcb1_netlist.py` 里写着 `G = PO.G`，还自己用 `int(x / G)` 判「焊盘/过孔落没落在铺铜上」。 +`pcb1_pour.BW/BH` 一改，它的栅格尺寸跟着变大、原点却还在 (0,0) +⇒ **坐标整体偏 30 mm**。现象是「靠平面连通的网络（+12V / GND / +3V3 / VOn_P） +忽然从 4 个碎片炸成 23 个」，而同一时刻 `pcb1_pour --verify` 回读的实测铺铜 +「+12V 一个连通域、58 个焊盘没着落 0」完全健康。 + +**代价是真的**：`pcb1_orphan_cu.py` 走的就是这套栅格，据此把 12 个过孔判成悬空删掉了 +（所幸那些碎片本来就不含焊盘 —— 那一半判据不依赖栅格 —— 所以电气上无损）。 + +⇒ 两条规矩： +1. **改共享的几何常量之后，把 `import` 了它的模块全部跑一遍**，不能只验改动的那个； +2. 「连通性突然大面积变差」和「实测回读健康」同时出现时，**先怀疑度量，再怀疑板子**。 + + +## 3c. `create()` 会把**元件**坐标也吸附到 5 的倍数（2026-09-08）⚠️⚠️ + +§3 说「元件坐标不受此限」——那是对**移动**（`setState_X/Y`）说的。 +**`sch_PrimitiveComponent.create()` 会吸附**：R1 页上 679 / 639 / 654 / 589 这些 +非 5 倍数的位置（都是当年 create 完再拖出来的），照搬到新工程里放下去会落在 +680 / 640 / 655 / 590，差 1~2 个单位。 + +后果：整页导线是按原坐标算的，差 1 就全断；而「按 (x,y) 精确匹配认领位号」的 +惯用写法会**一个都认不上**（本项目实测 42 件只认到 28 件，另外 14 件停在 `U?` / `C?`）。 + +⇒ 跨工程重放版图的固定写法：**就近认领（容差 3）→ 认完立刻 `setState_X/Y` 拉回精确坐标**。 + +## 6f. 跨工程重放：**27/42 件的 `create(rot)` 语义与源页相反**（2026-09-08） + +§6b/§6c 说「方向表一张都别信」，本轮给出了量级：把 R1 一页 40 个件原样搬到另一个工程， +**27 件的 rot=270 得到的引脚顺序与源页相反**。其中 + +- 25 件是两脚对称件（0402 R/C），只有引脚**编号**互换，坐标集相同 ⇒ 连线不受影响； +- **2 件致命**：33nF（`C13594`）是 **+20 / −15 的不对称跨距**，翻过来两个脚的**坐标真的差 5**， + 照源页坐标画线会断在这两颗上。这正是 §8d「跨距同族也不统一」的后果被放大。 + +⇒ 做法：把源页的**引脚坐标连同脚号**一起 dump 下来当基准，放完逐脚比对， +对不上的 `setState_Rotation(rot+180)` 再回读，循环到全对。 + +⚠️ **第一轮往往「看起来没生效」**：`create(270)` 与 `setState_Rotation(270)` 差 180°（§6b）， +所以要翻**两次**才落到源页的语义上。别以为脚本卡住了 —— 本项目日志里就是同一批 27 件 +连打两行「翻转 27 件重试」，第三轮才空。 + +### 6f-2. ✅ 那两圈空转可以直接省掉：**放完立刻用同一个角度再写一次**（2026-09-08） + +受控实验（A2-AUX 空页，0402 电容，`create(..., 90)`）： + +| | pin1 | pin2 | +|---|---|---| +| `create(90)` 之后第一次读回 | (0, **+20**) | (0, −20) | +| 紧接着 `setState_Rotation(90)`（**同一个角度**）再读 | (0, **−20**) | (0, +20) | + +两者差 180°，就是 §6b 那条。**后者才是最终落盘的语义。** +⇒ `place()` 里在 create 之后加一遍「按 placement 表把每件的 rotation 用同一个角度再写一次」， +第一次读回就是真的：R2 底板 A1-INPUT 那 14 件 rot 90/270 的件， +从「翻转 14 件重试 ×2 轮」变成**一轮直接通过**。已并入 `.claude/r2/schcheck.py` 的 `place()`。 + +> 这不只是省时间。**盲目翻转循环有可能替一个真放错的件「碰」出一个假的通过** —— +> 循环最多转 4 轮，rot+180 / +360 / +540 里总有一个可能与错误的期望值凑上。 +> 先把语义刷正，再让逐脚断言去判，判据才是干净的。 + +## 3e. 读回来的旗/端口坐标带浮点尾巴（2026-09-08） + +`rot=180` 的旗和端口，`getState_X()` 读回来是 `789.9999999999999` / `520.0000000000001`。 +直接拿去做「必须是 5 的倍数」「必须落在导线端点」两道自检 ⇒ **全部误报**。 +⇒ dump 出来先 `int(round(...))`。（导线的 `getState_Line()` 没有这个问题。） + +顺带：**旗的符号名读回来是 `Ground-GND` / `Power-5V`**，而 `createNetFlag()` 的第一个参数 +只认 `Ground` / `Power` —— 重建时取 `name.split('-')[0]`。 +（`Power-5V` 里的 `5V` 只是符号默认网络名，正是 §3b 里「移动电源旗会掉回 `+5V`」的那个默认值。） + + +# 附录 A：外部来源的四条 PCB 陷阱（2026-09-07 并入） + +⚠️ **本节与全文其余部分性质不同**：以上每一条都是本项目亲手踩出来的， +下面这四条来自 [`v0id-byte/easyeda-pro-claude-skill`](https://github.com/v0id-byte/easyeda-pro-claude-skill) +（MIT）§10，是**别人**在一块密集四层板上的实测记录，**本项目尚未复现**。 +按「可信但待验证」对待：判据照做，但别把它当成本项目已确认的事实。 + +> 同一份文档里有一条**我们已经证伪**的说法：它称 +> `overwriteCurrentRuleConfiguration()` 是 BETA、调用会永久 hang、只能走 GUI 改规则。 +> 本项目 `.claude/pcb1_rules.py:315` 是跑通的 —— 失败原因在参数： +> **要传 config 本体，不要传 `{name, config}` 包装**（见该文件头第 10 行）。 +> ⇒ 外部 skill 的结论要逐条对着本项目的实测过一遍，不要整段照抄。 + +## 9ad. `save()` 返回 true 也可能没落盘 —— 判据是回查图元数 ⚠️⚠️ + +文档上下文过期时，API `save()` **返回 `true` 但盘上文件仍是旧状态**。 +对方因此丢了一整版布线：界面上线都在，重开文件只剩铺铜。 + +**判据**：`save()` 的返回值不算数。落盘的证据是**重新读一次图元计数**—— +```python +before = count_tracks() # 下发前 +... # 下发 +call('await eda.pcb_Document.save()') +after = count_tracks() # 必须等于 before + 本次新增 +``` +本项目 30 多个脚本（`pcb1_place.py` / `pcb2_route_sig.py` / …）目前**都只看 `save()` 的返回值**， +没有一个做回查。新写的下发脚本按上面这个形状补。 + +> 与 §9p 是同一类判据：「跑完了 ≠ 生效了，重开数一次才算」。 +> §9p 已经在自动布线上踩过，这条是它在 `save()` 上的同构版本。 + +## 9ae. 关掉再打开 PCB 标签页 → 桥接失去同步（API 读到 0 图元）⚠️⚠️ + +关闭 PCB 文档标签页再重新打开之后，API 会读回 `0 tracks` / 陈旧上下文， +**而画面上明明有线**。此时任何「先读回再增量下发」的脚本都会做出错误决策 +（把有线的板子当空板重画）。 + +**恢复**：EDA 里 `API Gateway → 重新连接`。 +**判据**：脚本开头读回的图元数如果是 0，但你知道板子非空，**先怀疑桥接而不是怀疑板子**—— +这正是 §9v「只加不删的脚本必须自己记账」最怕的输入。 + +顺带：一个工程里常有多个 PCB 副本（`PCB1` / `PCB1_1`…），重开时确认打开的是对的那一个。 + +### 9ae-2. ⚠️⚠️⚠️ 失同步状态下**再 save() 一次，会把「空」写回文档**（2026-09-07，真丢了一块板） + +上面那条说的是「读到 0 会让脚本做出错误决策」。**比这严重得多的是写。** + +实际发生的一次（载板 PCB2，223 元件 / 2649 导线 / 896 过孔）： + +``` +pcb2_cfgsel.py --push # 建 6 线 2 孔 + save()，一切正常 +pcb2_reload.py # 删铺铜边框 → save() → location.reload()，报告「已重载」 +pcb2_pour.py --push # 建 7 块铺铜边框 → 填充一直 0/7 → 中途 save() ← 就是这一下 +``` + +第二步重载回来之后，**铜层已经读回全 0**（就是 §9ae 那个陈旧上下文）， +但当时的判据只有「windowId 变了 = 重载成功」，没人去数图元，于是直接往下走。 +第三步在那个状态里调了 `save()`，把客户端内存里那个「没有电气对象」的模型写回了文档。 + +**事后的样子非常有迷惑性**：完整重启客户端之后， + +| 层 | 读数 | +|---|---:| +| 铜层（1/2/15/16）：元件 / 导线 / 过孔 / 焊盘 / 铺铜 | **全 0** | +| 板框层 11 | 1 条 ✅ | +| 底层丝印 4 / 底层锡膏 8 / 元件外形 48 / 元件标识 49 | 1321 / 216 / 185 / 186 ✅ | +| 挖槽 12 / 文档层 13 | 12 / 39 ✅ | + +也就是说**丝印、锡膏、装配、板框这些非铜层图形一条不少，只有电气对象没了** —— +第一眼很像「API 又失同步了」，其实是数据真没了。 +`pcb_PrimitiveComponent.get('U32')` 甚至还能返回一个对象，但它所有 `getState_*` 都是 `null` +（**空壳，别把它当成「找到了」**）。同一工程里的另一块板（PCB1，301 件）读起来完全正常， +所以「换块板读读看」是区分「客户端坏了」和「这块板坏了」最快的判据。 + +**规矩三条** + +1. **「重载成功」的判据不是 `windowId` 变了，是重载后数一遍图元、数字不为零。** + `pcb2_reload.py` 已经把这条做成硬断言（`assert_alive()`），不过关直接 `sys.exit`。 +2. **读回 0 的时候，绝对不许再 save()。** 先 `API Gateway → 重新连接`， + 不行就重启客户端，确认数字回来了再动。任何「建完东西顺手 save」的脚本 + 在这个状态下都是破坏性的。 +3. 真丢了就走 **`文件 → 工程历史...`**（另有 `版本控制` / `回收站...`）恢复到写入之前， + 再把这一轮的下发按脚本重放一遍 —— 所以**每一步都要能用脚本重放**， + 这也是本项目坚持「改动写成脚本而不是手工操作」的理由之一。 + +⚠️ 顺带：这个状态下 `getCurrentRenderedAreaImage()` / `zoomToAllPrimitives()` 会**挂到超时** +（不是 §9t 那种 88 字节空 PNG）。截图挂住 + 另一块板正常 = 这块板的编辑器实例有问题，别再往下写。 + +### 9ae-3. 结局与更正：**毁数据的是失同步后的 save，不是 `reload()` 本身**（2026-09-08） + +上一节读起来容易得出「别再用 `location.reload()`」的结论。**那是错的**，同日的收尾证伪了它： + +- 损坏的文档最终**连删都删不掉**（右键删除，服务端直接回 `delete failed !`）， + 只能靠 `文件 → 工程历史...` 还原到事故前的版本把它移除，再新建一块 PCB 按快照重建。 +- ⚠️ 顺带更正：曾以为「工程历史点不开」，其实是**当时的活动文档正是卡死的那块板**。 + 换个健康文档再点就开了。⇒ **某个 GUI 功能点不开时，先怀疑当前活动文档卡住。** +- 在**新建的健康文档**上，`pcb2_reload.py`（内含 `location.reload()`）**完全正常**： + 重载后回查 216 元件 / 2644 线 / 896 孔 / 1000 焊盘全对。 + 而且它是**唯一能清掉「卡在 0% 的后台任务」的办法** —— 不清掉，铺铜「重建所有」永远填 0 块。 + +⇒ 正确的规矩不是「不许重载」，而是： + +1. **重载前先 `save()` 并回读验证**（图元数对得上再重载）； +2. **重载后必须数一遍图元**（`pcb2_reload.py:assert_alive()`），为 0 就停手、**绝不 save**； +3. 读到 0 时先 `API Gateway → 重新连接`，不行就整个重启 EasyEDA； + **如果重启之后某块板仍然读 0 而另一块正常，那就是这块板的文档坏了**，修不了，只能换。 + +### 9ae-4. 铺铜「重建所有」填 0 块的另一个成因：飞线还在算 + +§9k 说填 0 块 = 客户端卡在后台任务上，判据是底部那条 0% 进度条。 +2026-09-08 补一条**具体是什么任务**：刚导入几百个元件 + 两千段铜之后， +`pcb_Document.getCalculatingRatlineStatus()` 返回 **`active`** —— 飞线在算。 + +⚠️ 但 `stopCalculatingRatline()` 停掉它（`active` → `inactive`）**并不能**让铺铜通， +0% 进度条也不消失。**最后还是要重载。** ⇒ 这个 API 可以用来*确认*后台确实有任务在跑， +但别指望它能解开死结。 + +## 9af. 布线质量的客观判据：**绕行比** = 走线长 ÷ 焊盘跨距 + +不用截图就能给走线打分： + +- 每网络走线总长 `L = Σ hypot(endX-startX, endY-startY)`（`pcb_PrimitiveLine`，只数铜层） +- 焊盘跨距 `S = max` 两两焊盘距离 +- **绕行比 = L / S** + +判据（两脚网络）：**1.0 ~ 1.5 = 直连；> 2 = 绕远路**。 +对方靠这一个数抓出一条 13 个过孔 / 2.2× 的 PWM 网络，全程没开截图。 + +⚠️ 长度本身没有判别力（跨距大的网络本来就长），**要判的是路径不是长度**。 + +⇒ 这条正好补上本项目 CLAUDE.md 里那句「几何验证证明不了看着对」的一部分： +绕行比能把「连上了但绕了一圈」从人眼截图挪进脚本。建议加进 §10 验证流程的 PCB 侧。 + +## 9ag. 自动布线忽略 GND → DRC 连通性开路，而**飞线不显示** ⚠️⚠️ + +把 GND 加进自动布线的「忽略网络」（指望铺铜兜住）， +则**没有被 GND 铜实际盖住的 GND 焊盘会判为连通性开路**——对方那块板 62 处。 + +**最坑的是飞线数远小于 DRC 数**：GND 的飞线被部分抑制，看飞线会以为没事。 +**判据：信 DRC 的连通性计数，不信飞线。** + +两条出路，二选一： +1. 把 GND 也交给布线器（代价：顶/底层拥挤 + 几处过孔间距吃紧）； +2. 给每个开路的 GND 焊盘**打一个过孔下到内层 GND 平面**。 + +本项目走的是 2（`pcb2_strap_gnd.py` / `pcb2_vo_vias.py`）， +但**开路的判定来源**要按这条改：以 DRC 连通性计数为准，不要拿飞线数收工。 + +### 顺带：对方在 Freerouting 上的结论（本项目没走这条路，存档备查） +DSN→jar→SES 往返**跑得通但结果不可制造**，两个死因： +① 铺铜导出成 `plane 0`（= 没导出），布线器看不见铜，会把 GND/电源当普通线布； +② **逐对象类型的间距矩阵在 DSN 里塌成单一 class 间距** —— track-via 6mil / track-copper 10mil 全丢， +只剩 track-track。导入后 track-过孔间隙落在 0~4 mil，**改 DSN 间距重布结果一模一样**（属 SES 导入的产物）。 +⇒ 用 EasyEDA 自带的自动布线器（本项目 §9p 走的就是这条），别在 Freerouting 上耗时间。 diff --git a/.claude/xpage.py b/.claude/xpage.py index b56396e..fcd5e3e 100644 --- a/.claude/xpage.py +++ b/.claude/xpage.py @@ -38,7 +38,20 @@ PENDING = tuple('EFUSE_EN EFUSE_FLT EFUSE_PG VDAC K2_ K3_ K4_ K5_ VBUS_EN'.split # 2026-09-04 两板拆分之后，VO2_P~VO5_P 在 P5-BTB 上都有了对端（每路 3 针）， # 原来那条「只为命名、天然单实例」的豁免已经不需要了。 # 这个集合先留空：真出现单实例就该报出来，别再默默放行。 -NAMING_ONLY = set() +# 2026-09-06 595 上载板之后：POGOn_* 只在 C4-SITEn 一页上（按键 MOS 漏极 -> 顶针那一段）， +# 端口只是给 PCB 网络起名（pcb2_route_sig 等按名字认它），天然单实例。 +NAMING_ONLY = {'POGO%d_%s' % (n, k) for n in range(1, 6) for k in ('PWR', 'VUP', 'VDN')} +# 2026-09-07 FAN-R2：两路 TACH 的风扇侧原始节点只在 P6 一页上（座子 -> 上拉 -> 串阻）， +# 端口只是给 PCB 网络起名，天然单实例。开关后的 FAN_12V_SW 用电源旗，不在这里。 +NAMING_ONLY |= {'FAN_IN_TACH_RAW', 'FAN_OUT_TACH_RAW'} +# 2026-09-08 R2 刀片 B4-EDGE：PRSNT# 只是金手指 A1↔B31 在刀片内部短接的那一根， +# 刀片这一侧天生没有对端（对端在**底板**的 A5-SLOTS，另一份原理图，xpage 看不到）。 +# 端口只为给网络起名，否则 EasyEDA 会给个 $4N... 默认名。 +NAMING_ONLY |= {'PRSNT#'} +# 2026-09-08 R2 底板 A1-INPUT：入口链三个节点（J1→F1→Q1→Rs6）在 R1 上本来是无名网络， +# PCB 侧只能按 $1N223/$1N227/$1N236 认。这一段过 9A、要铺铜 + 断面校核（方案 §6.4）， +# 所以各挂一面 Power 旗起名 —— 天然单实例，本页内部的节点，不该有对端。 +NAMING_ONLY |= {'VIN_RAW', 'VIN_FUSED', 'VIN_SW'} print('%-14s %-8s %-4s %s' % ('网络', '类型', '实例', '出现在哪些页')) print('-' * 78) diff --git a/.gitignore b/.gitignore index 5a4a34b..354069d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,28 +1,35 @@ -# ---- 构建产物 ---- -firmware/build/ -firmware/host/build/ -firmware/sdkconfig -firmware/sdkconfig.old -firmware/managed_components/ -firmware/dependencies.lock - -# ---- site（VitePress 文档站）---- -site/node_modules/ -site/.vitepress/cache/ -site/.vitepress/dist/ - -# ---- Python ---- -__pycache__/ -*.pyc - -# ---- EasyEDA 桥接的运行时垃圾 ---- -# _bridge.log 是桥接服务器的日志，能长到几 MB，跟工程状态无关 -.claude/_bridge.log -# *.stale 是脚本自己标记的过期中间结果（见 PROGRESS.md） +# ---- 构建产物 ---- +firmware/build/ +firmware/host/build/ +firmware/sdkconfig +firmware/sdkconfig.old +firmware/managed_components/ +firmware/dependencies.lock + +# ---- site（VitePress 文档站）---- +site/node_modules/ +site/.vitepress/cache/ +site/.vitepress/dist/ + +# ---- Python ---- +__pycache__/ +*.pyc + +# ---- EasyEDA 桥接的运行时垃圾 ---- +# _bridge.log 是桥接服务器的日志，能长到几 MB，跟工程状态无关 +.claude/_bridge.log +# *.stale 是脚本自己标记的过期中间结果（见 PROGRESS.md） *.stale - -# ---- 编辑器 / 系统 ---- -.vscode/ -.idea/ -Thumbs.db -desktop.ini +.claude/r2/_remote_route.tgz + +# ---- EasyEDA -> KiCad 转换的中间产物 ---- +# 工程源码 dump / 几何 JSON / .epro 整包，约 20 MB，全部可由 +# k_dump.py + k_extract.py + k_dump_epro.py 从 EasyEDA 重新生成（需桥接在线）。 +# 产物本身（kicad/）是跟踪的。 +.claude/eda_src/ + +# ---- 编辑器 / 系统 ---- +.vscode/ +.idea/ +Thumbs.db +desktop.ini diff --git a/CLAUDE.md b/CLAUDE.md index 65776a4..0bcb886 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -10,6 +10,15 @@ |---|---| | **`五路直供电源板设计.md`** | 设计定稿 v1.6。规格、拓扑、逐项计算、保护链、BOM、PCB 要点、调试顺序、小米8 侧接口引脚定义。**改任何设计决定都要同步更新它。** | | **`PROGRESS.md`** | 当前进度与下一步。原理图画到哪一页、还有哪些阻塞项。 | +| **`刀片式方案规划-R2.md`** | **R2 新架构**（底板 4 层 98×98、器件全在背面 + 5 片相同刀片、PCIe 竖插；D15，2026-09-10 由 2 层改），2026-09-08 起与 R1 并行。工程 UUID 在 `.claude/r2/r2-uuids.json`。**R1 保留不动。** | + +## 布线计算硬规则 + +**所有 PCB 布线运算统一在 `10.5.5.13` 服务器执行。** 本机只允许刷新 EasyEDA +快照、校验服务器结果、下发和跑 DRC；不得在本机运行 `route_base.py --replan`、 +`--dp-only` 或其他 A* 试算。底板统一从 `.claude/r2/remote_route.ps1` 进入。 +服务器上优先用 PyPy（`-Interp /root/pypy/bin/pypy3`，单轮快约 4.7 倍，输出确定）； +`-Variants @('...','...')` 并行跑多组参数、自动取未完成最少且不比当前缓存差的结果。 设计文档里 **§0.1 是决策清单**（13 条已定稿，不要再重新讨论）， **§12 是待确认项**。动手前先扫这两节。 diff --git a/PROGRESS.md b/PROGRESS.md index d5327c9..c58112a 100644 --- a/PROGRESS.md +++ b/PROGRESS.md @@ -1,2805 +1,4565 @@ -# 进度与交接 - -更新：2026-09-06 **第二十四轮（I²C 干线改走 Inner2）**。 -详见设计文档 **§26.20**（上一轮是 §26.17 / §26.18 / §26.19）。 - ---- - -## ⭐ 新会话从这里开始 - -### 一句话现状 - -原理图 **11 页全部验证通过**。 -下板 PCB1：摆位 342 件、扇出、15 块铺铜、五路功率级 195 段全部下发并回读过。 -这一轮把 **I²C 的跨板长干线挪到了 Inner2**（302 mm 内层，§26.20）—— -目的是**腾外层通道给布不通的线**，然后立刻跑了第三遍信号布线（`--ripup`）验证效果： - -| | 挪之前 | 挪之后 + 第三遍布线 | -|---|---|---| -| 已连通网络 | 148 | **163** | -| 还欠连接 | 87 条 / 74 网络 | **68 条 / 59 网络** | -| DRC 连接性错误 | 1044 | **855** | -| 板上铜 | 3196 线 / 1000 孔 | 3516 线 / 1084 孔 | - -铺铜已重铺回读（Inner2 浮铜从 1312.8 mm² 降到 **0.2 mm²**，剩的那点是新布线蹭出来的碎屑）。 - -### ⬅️ 下一步 - -**⛔ 那 74 条 DRC 间距错误的真因已查清（§26.21）：漏跑 `pcb1_parts_dump.py`。** -§26.18 重排的 44 个焊盘**导进 PCB 了，但缓存没重抓** ⇒ 后面两轮布线里 -**33 个网络的铜连的是错信号**。已拆掉那 530 段 / 2482 mm / 138 孔并重布（跑完对一遍 DRC）。 -⚠️ **规矩：`pcb1_import.py --apply` 之后下一条命令就是 `pcb1_parts_dump.py`。** -中间插别的操作，后面全部几何和布线都建在沙子上，而**六道自检一条都不会响** -（它们读的是同一份缓存，自洽得很）。 - -> 期间走过两条弯路，都记在 §26.21 末尾：**多边形焊盘不许按包围盒判** -> （QFN 散热盘的盒子会套住邻脚，凭空报 21 处假「重叠」）； -> **DRC 的「间距」那一支不陈旧**（重载前后逐字相同，不能当旧数据糊弄）。 - -剩下 **68 条连接性**（59 个网络，大多各欠 1~2 条）。还能腾外层的两个大头： - -| 候选 | 现状 | 说明 | -|---|---|---| -| `BUCK_PG` | 已连通，**顶层 234 mm**、跨 121 mm | 剩下最大的一块外层占用，挪进 Inner2 能再腾一大片 | -| `INA_ALERT` | 欠 2 条 | **试过，没跑通**：铜整片在顶层且挤在控制块，主碎片周围一个合法孔位都没有 | -| `USB_DP/DM` | 各欠 2 条 | **不许进内层**（90 Ω 以 L2 为参考，§10.1），只能在外层解 | - -常规循环（一步都不能省）： - - /c/Python314/python -u .claude/pcb1_route_sig.py --refresh --ripup --push - /c/Python314/python .claude/pcb1_pour.py --push --refresh - /c/Python314/python .claude/drc_read.py - -⚠️ **`pcb1_route_sig.py --ripup` 认「哪些铜是自己画的」靠覆盖判据，不是坐标比对** —— -`pcb1_i2c_l3.py` 画的 **Inner2 干线**和 `pcb1_gnd_stitch.py` 的 6 个缝合孔它都不认得。 -2026-09-06 实测跑完一轮 `--ripup` 之后 **55 段内层线一段没丢**，但这不是保证 —— -跑完对一遍 `_i2c_l3_snapshot.json`（或 `pcb1_i2c_l3.py` 不带参数跑一遍数碎片）。 - -⚠️ **引擎的层数已经不是写死的 2 了**（2026-09-06 改）：`pcb2_route_sig.Field` 现在按 -障碍表里真正出现过的层建数组、`viafree` 取**全层**最小值。不这么改的话，板上一有 -layer 16 的走线就 `KeyError: 16` 当场崩；就算滤掉，它打的新过孔也**不会**对内层干线 -做净距判断（旧的 `viafree` 只看 Top/Bottom），孔会直接压在内层线上。 - -⚠️ **`pcb1_route_pwr.py --push --verify` 是只 verify，不下发** —— -`main()` 里 `--verify` 在 `--push` 之前 `return`，而它照样打「✅ 全部校核通过」， -只在最后一行回读里露馅（「195 段里没被实测铜盖住的 **195** 条」）。**要下发就只写 `--push`。** - -⚠️ **`pcb_fanout.py --clean` 会把板上全部走线删光**，包括 `pcb1_route_pwr` 的 195 段。 -所以「改了扇出」= 扇出三步 → **重铺铜 → 重跑 route_pwr** → 再 route_sig，一步都不能省。 - -⏱ **实测速率**：`route_sig` 前两个网络（`SDA`/`SCL`，各挂 14 个焊盘横跨整板）要 **1516 s**， -之后 5 个网络只要 **68 s**。**别拿头几个网络外推总时长**；全程约 60~90 分钟。 -它是**跑完才一次性下发**的 —— 中途停掉板上一根铜都不会变，但也等于全白跑。 - ---- - -### ✅ 第二十四轮（2026-09-06，用户拍板）：I²C 干线改走 Inner2（§26.20） - -`SDA`/`SCL` 是全板最长的两个网络（各 14 个焊盘、横跨整板）， -既吃布线时间（1516 s）又占着外层最好的通道。用户拍板：**走内层，只挪跨板长干线**。 -新工具 **`.claude/pcb1_i2c_l3.py`**（三层迷宫布线 Top / Bottom / Inner2）。 - -| | 改之前 | 改之后 | -|---|---|---| -| I²C 总铜长 | 596 mm，**内层 0** | 609 mm | -| Inner2 | — | **302 mm** | -| 顶层 / 底层 | 596 mm | 157 / 150 mm | -| 连通性 | SCL 3 片 / SDA 4 片 | **一模一样** | - -**中桥那 13 mm 是唯一留在外层的一段**：`12V-SW+BR` 的中桥（x 61.5~72.6，喂 3.6 A） -是 Inner2 上东西两半唯一不能割的隔断，I²C 过去就必须横着割 ⇒ 只能外层跳。 -（上一轮 `route_sig` 给 `SDA` 布的就是这个跳法，殊途同归。） - -三条这一轮踩到的坑（细节全在 §26.20）： - -1. **`PEN_3V3` 决定的不是长度，是平面会不会被切出孤岛。** 1.8 的时候两根线在 - `3V3-SW` 里围出 7.2 mm² 孤岛，**里面有 R415.2 的 +3V3 焊盘** —— - 浮铜检查 / 焊盘覆盖检查 / 连接性 DRC **三样全都不响，只有数连通域看得见**。 - 堵孤岛重绕**不收敛**（7.2 → 25.4 → 26.8 → 32.5 mm²）。改成 **4.0**： - 干线走 GND 底填，只在器件旁边**扎盲端**进平面。 -2. **`expand()` 会静默丢掉最后一点上的过孔** —— 引擎 `_end_via` 的注释早写着，又踩一遍。 -3. **`own`（本网铜放行）要按半线宽内缩**，过孔则根本不吃这条放行。 - -**顺带修掉一块和这次无关的浮铜**：板子南沿 y 0.5~9 那条 GND 底填（**1312.8 mm²**） -在 Inner2 上是孤立的，一个落脚点都没有 —— 它原本靠 x 115~116 那条 1.0 mm 缝接出去， -被上一轮信号布线的三个过孔的反焊盘掐断了。新脚本 **`.claude/pcb1_gnd_stitch.py`** -在南沿补了 6 个 GND 缝合孔。⚠️ 这一条**只有铺铜下发后 `verify()` 回读实测铜才量得出来**， -下发前的 `report()` 栅格不含别的铺铜，算出来 GND 是一整块。 - -**验收**：净距/拐角/孔距 ✅ · 平面完整性 ✅（+12V 1 块 / +3V3 2 块）· -`pcb1_pour.py --push --verify` ✅ 实测和计划对得上 · DRC 里**没有一条**牵涉 SDA/SCL。 - ---- - -### ✅ 这一轮 C（2026-09-06）：8 A 的源只有 3 个过孔（§26.19） - -第一次跑信号布线跑到 35/196 中止 —— 不是布线器的问题，是它报出来的失败把两个上游问题照了出来。 - -1. **`Rs6.2` → +12V 平面只有 3 个 Ø0.3 过孔 ≈ 3~4.5 A，而它要过 8 A。** - 它是全板 +12V 平面**唯一的源**。这一条**四道验证一条都不管**：铺铜断面只量平面本身、 - 扇出只报「孔放下了没有」、连接性 DRC 只看「连上没有」、逃逸审计只看「出得去吗」。 - ⇒ `pcb_fanout.py` 新增 **`FORCE_ARRAY`**（整片阵列钉死，逐个仍走全套净距校核）， - Rs6.2 钉 **12 个孔（≈12 A）**，摆在焊盘正南那片空地。 - **规矩：>4 A 的「焊盘 → 平面」转换点，过孔数必须手写。** -2. **顺带把 U13 的 I²C 放了出来。** 原来那 3 个孔有两个甩到西边，两根 1 mm 引线 - （端帽再往西探 0.5）压死了 U13 南排五个脚唯一的通道；`VINSW-TOP` 北柱又只差 0.379 mm。 - 12 个孔改朝南 + 北柱在 y>87 收窄到 x 1.5~5.3（3.8 mm → 8.4 A）， - U13 南边变成一整片 x 5.5~14 / y 91.6~96 的空地。 -3. **扇出不对称又发作了一次**：`C%06.2` 的 GND 孔在 rot 0 的三路往东落到局部 (10.02,27.10)、 - 在 rot 180 的 CH2/CH3 往西落到 (6.75,27.10)，正压在 eFuse 脚 14/15 的出线口上。 - 已加进 `_CH_FORCE_LOCAL`。 -4. **剩下 10 个「被围死」不是板上的铜** —— 报出来的挡路物去 `pcb-copper.json` 里查不到， - 是**审计自己给邻脚预留的出线段**。判据就是这个：**查得到才是真障碍**。 - ---- - -### ✅ 这一轮 A（2026-09-06）：v11 的两行排法把 8 A 输入链卡死了，已修（§26.17） - -§26.16-E 换 XT30 之后把 N-L 块改成两行，摆位的**本地检查六项全过**， -可是回去重画 §26.11 的顶层宽铜时第一刀就下不去： -**`VIN_RAW` 从 J1 出来根本没有 3.49 mm 的路** —— XT30 rot 270 之后 GND 在北针 (13.5,74.5)、 -VIN 在南针 (13.5,69.5)，而 F1 卧着放和 GND 针同一行，中间又被 D1(17.5,69.5) 堵住， -实测通道只剩 **1.674 mm**（1 oz 外层约 4.5 A，这里要 8 A）。 - -> **这一类错误几何检查一条都报不出来** —— 不重叠、不越框、高度也够。 -> 抓到它的是「照新坐标把顶层宽铜的多边形重推一遍」这个动作本身。 -> ⇒ **摆位改完不能只看本地检查，必须把 §26.11 那三块多边形重推一次**。 - -三处改动（`pcb1_place.py` 的 N-L 表）： - -| # | 改动 | 拿回了什么 | -|---|---|---| -| ① | **F1 卧 → 竖**（rot 0 → **90**），(17.5,74.5) 不动 | `F1.1` 落到 (17.5, **73.06**)，正对 J1.2 那片空地 | -| ② | **D1 (17.5,69.5) → (31.0,74.5)** rot 270 | 通道里最后一个障碍搬走，TVS 贴到漏极铜东缘 | -| ③ | **C4/C5/C6 x 25 → 30.5，rot 0 → 180** | 让出 y 78.85~83.5 那条 **4.64 mm** 的 VIN_SW 西行干道 | - -顶层三块宽铜重画后实测断面全过：RAW 颈 **3.50**（要 3.49）、FUSED 5.25、SW 干道 4.75、北柱 5.25 mm。 -面积 59 / 30 / 263 mm²，各 1 个连通域，`check_top_clearance()` 零侵入。 - -**⚠️ 顺带抓到一个静默失效：`Rs6.2` 一个过孔都没打。** -`12V-N` 为了让开 U13 的 Kelvin 脚，在西边咬了个缺口 `(0.5,93.0)-(12.5,101.5)`， -而 Rs6.2 的焊盘中心 (9.57,93.50) **正落在缺口里** ⇒ 扇出判成「不在铜面上」， -**全板唯一的 8 A 源不接电源平面**。`--push` 照样报「失败 0 个」，连接性 DRC 也不响 -（+12V 靠别的 55 个焊盘照样连通，只有**源**那一端是断的）。缺口收成 `(0.5,95.6)-(12.5,102.4)`。 - ---- - -### ✅ 这一轮 B（2026-09-06，用户拍板）：三组引脚按几何重排（§26.18） - -「哪个信号落在哪个物理脚」有三处是自由的，而原来全是按**逻辑顺序**排的， -和它们在板上要去哪儿一点关系都没有。目标函数用**绕开芯片本体的直角最短路** -（HPWL 量不出「东边的脚要去西边」有多贵：同一批改动 HPWL 说省 7%，绕障路长说省 15%）。 - -| 组 | 结果 | 挪了几个 | -|---|---|---| -| **ESP32-S3 U20** 22 个信号 | 1195 → **1020 mm**（−15%），绕模块的线 3 根 → **0** | 12 | -| **DAC63204 U6/U7** 5 个通道 | 422 → **352 mm**（−17%），**一根线都不用新画** | 4 | -| **74HC595 U21/U22/U33** 21 个位 | 1286 → **1141 mm**（−11%），每路三键成束 | 17 | - -合计省 **约 390 mm**。三处关键决定： - -1. **放开 IO39~IO42**（原留给引脚 JTAG）—— 西边从 4 个坑变 8 个。 - 调试本来就走**原生 USB-Serial-JTAG**（IO19/IO20 → J22，出厂 eFuse 默认就是它）， - 板上没有 JTAG 排针。⚠️ **永远别烧 `DIS_USB_JTAG`**，烧了两边都没有。 - 让出去的只是「USB 起不来时还能进去」这个兜底。 - `EFUSE_EN1 → IO39`、`VBUS_EN1 → IO40`、`EFUSE_EN4 → IO41`、`VBUS_EN4 → IO42`。 - 空出来的是 **IO4 / IO5 / IO7（三个都带 ADC1）+ RXD0/IO44**。 -2. **DAC 只在已画好线的 5 个通道里置换**（U6 管去西半板的 VDAC1/2/4，U7 管去东半板的 VDAC3/5）。 - 动用 U6.OUT3 / U7.OUT2/3 还能再省 6 mm，但要新画 OUT/FB 两根线，不值。 -3. **595 加了「每路 3 个按键必须落在同一片的连续三个南脚上」的约束** —— 比自由指派多 40 mm， - 换来三根线出芯片就是一束。U33（y≈70）从「EDL 专用片」变成「北边那一片」， - 接管 CH2/CH3 的六个按键 + HUB_RST，因为它正对 y 87~94 的北排两路。 - -**⛔ U33 现在在 `P6-FAN-EDL` 那一页上带着 CH2/CH3 的按键网络** —— 页面语义乱了一点， -但三片本来就是一条 24 位链，功能上没区别。 - -#### 落地时踩到的两条 API - -1. ⚠️⚠️ **`setState_Net` 对 netport 是坏的**：调用之后网络名变成**空字符串**，标签也没了 - （和 skill §3b 的 `setState_X/Y` 同一个毛病）。⇒ 端口只能 **删掉重建**。 -2. ✅ **skill §8b 那句「端口的 dir 读不回来」是错的**： - `getState_Component().name` 就是 `Netport-BI` / `Netport-IN` / `Netport-OUT`。 - 重建前读它原样传回去即可 —— `p1_add.py` 当年「端口只增不重建」的限制可以解除了。 - -#### 顺手治了：图面文字叠了好几代 - -P3 有 **44** 条 `sch_PrimitiveText`、P3B **64** 条、P6 **76** 条，大量是**同坐标同内容的完全重复** -（历代脚本只 `create` 不 `delete`），还有互相矛盾的旧说明叠在一起。 -**四道验证（verify_sch / xpage / port_audit / DRC）一条都不管文字**，所以它烂了很久没人发现。 -`.claude/sch_text.py` 整页重写：44→13 / 64→14 / 76→16，顺带改掉换脚后变成假话的几条。 - -### 这一轮新增的脚本 - -| 文件 | 用途 | -|---|---| -| **`pinmap.py`** | ⭐ 三组「逻辑信号 → 物理脚」映射的**事实来源** + 落地 + `--check` 回读对账 | -| **`sch_text.py`** | 三页图面文字整页重写（删光旧的再写一套） | - -### ⚠️ 还欠人眼确认 - -- `PCB1-v11-NL.png`（北左输入链改动前）与改动后的截图 —— **还没截改动后的** -- `P3-CONTROL-v2.png` / `P3B-EXPAND-v2.png` / `P6-FAN-EDL-v2.png` 三张换脚后的原理图 -- 摆位总图 `PCB1-v11-place.png`（v11 那一版，D1/C4/C5/C6 的新位置还没进图） - ---- - -### 上一轮（2026-09-06 第二十二轮）：拆线重布 + 两处换件 + 控制块按几何重排（§26.16） - -| # | 改动 | 依据 | -|---|---|---| -| 1 | **J1**：`KF128-5.08-2P` → **`XT30PW-M`**(C53373776)，(8.5, 72.0) **rot 270** | 用户要插拔式；12V 是 8 A，DC-002 那类只有 1 A | -| 2 | **J26~J30**：`KF2510-3A`(弯针) → **`2510-3A`(直针)**(C2803349) | 用户要立式；进深 12.01 → **5.81** | -| 3 | **N-L 块重排** | XT30 比 KF128 宽一圈，原位放不下 ⇒ **这一版被第二十三轮推翻，见上面 A** | -| 4 | **控制块**：`affine()` → `CTRL` 表（退火求解，`pcb1_ctrl_place.py`）| 原来 U21/U22 中心只隔 8.04 mm，中间塞不进一根线 | -| 5 | **22 个附属 R/C**：`affine()` → `SAT` 表（逐个贴对端引脚）| `R602`/`R603` 是 USB-C 的 CC 下拉，**离 J22 有 77 mm** | - -全板 HPWL **9416 → 8935 mm**。摆位大改之后 `pcb1_wipe.py --push` 把板上**全部铜**清空过一次 -（走线 / 过孔 / 铺铜，元件 / 板框 / 丝印不动），13 个旧账本改名成 `.stale`。 - -**这一轮沉淀的脚本**（仍然有效）： - -| 文件 | 用途 | -|---|---| -| **`fp_body.py`** | ⭐ 从器件的 `3D Model Transform` 直接读**本体框**（`--scan` / `--check`）。⚠️ 只给 XY，**Z 读不出来** | -| **`p1p6_conn.py`** | J1 / J26~J30 换件（做到一根导线不动） | -| **`pcb1_ctrl_place.py`** | 控制块五颗芯片退火求位置（目标 HPWL）。⚠️ 它写的 `_pcb1_ctrl_pos.json` **只是参考**，`pcb1_place.CTRL` 是硬编码的事实来源 | -| **`pcb1_wipe.py`** | 清空板上全部铜（铜层白名单 1/2/15/16） | - -**⛔ 三个要记住的地雷（仍然有效）** - -1. `pcb1_route_sig.py` 的 `--net` / `--limit` 试水以前会把计划缓存清成 `{}`（已修）。 -2. `clean()` 以前只删得掉 59% 的自己的铜（已修，改成覆盖判据）—— - EasyEDA 会合并共线段、在 T 形接点劈线，坐标精确比对认不出来。 -3. 「两个端点钉死 ⇒ 连通性不变」是破的 —— 链会 T 在别的链**中段**上。 - 现在先按搭接点切开（409 → 797 条），拆完还要用 `pcb1_netlist.analyze()` 实算碎片数兜底。 - -**⚠️ 已知偏差（是决定，不是遗漏）** - -- **立式风扇座把装配顺序锁死了**（用户 2026-09-06 拍板接受）：立式插口朝上正对载板底面， - 座 + 胶壳约 11.5 mm，13 mm 净空里插拔只剩 1.5 mm ⇒ **必须先插好五根风扇线再合载板**。 -- **`H_FP` 里 XT30 的 11.0 和直针座的 9.0 是估计值** —— `3D Model Transform` 给不出 Z， - **打样前拿实物量**。 -- ~~控制块的通道分配还没改~~ → **第二十三轮已经做完**（§26.18）。 -- `POGO2_VUP` / `POGO2_VDN` 离 SW 节点 0.54 / 0.74 mm（§10.3 要「远离」）， - `sw_keepaway()` 会一直报，当提示不当错误。 - ---- - -### ✅ 这一轮（2026-09-06 第二十一轮）：五路母版三处整改 + 全链重跑（用户拍板 A+B+C） - -设计文档 **§26.15**。§26.14 抓出的 22 个「几何上没有出路」的引脚，这一轮动手改掉， -改的全是**母版**（= 五路一起改），改完整条链重跑。 - -| # | 改了什么 | 结果 | -|---|---|---| -| A | **SW 不再往南潜**：`C%05` 北移 0.6，`SW-run` 平着走 y 12.500（1.2 宽），删掉 `SW-down` | 五路 `EN` 全部解放；SW 节点 9.6 → **8.9 mm** / 铜面积 10.9 → **9.4 mm²** | -| B | **`U%8` + `Rs%01` + `C%13` 整体北移 0.8** | eFuse 北排那条缝 0.33 → **1.13 mm** | -| C | 跟着 B 改的三处：`_CH_FORCE_LOCAL['U%__8','1']`、`F-trunk` 北端、`K-IN±` | 相对几何一格没变 | -| — | 全链重跑：place → clear → dump → fanout → pour → route_pwr | 342 件 / 498 孔 / 15 铜面，功率级 195 段回读 **0 条对不上** | - -**「几何上出不去」的焊盘：22 → 8**（`pcb1_escape_audit.py` 实测）。 -剩下 8 个是**和邻脚预留出线段抢地方**，不是硬几何 —— 单独布都能通。 - -#### ⭐ 这一轮踩到的三条 - -**1. 「端帽比端点往外探半个线宽」这一条，一轮里踩了两次。** -先是 `SW-run` 1.5 mm 的西端帽把 `EN` 封死（在 y=11.5 那一行往西探到 x 11.007， -比端点多探 0.743）；改完起点又发现同一个端帽离 `U%1.13`(BOOT 引脚) 只有 **0.080**。 -⇒ **凡是宽线的端点，心里都要按「端点 ± w/2 的圆」去想**，§26.11 已经写过一次了。 - -**2. 挪 0.1 mm 解决不了拓扑问题。** A 组先试过「`SW-run` 起点东移 0.35」和「收窄到 0.9」， -两次都卡在 5~20 µm 上 —— 因为 COMP 和 EN **两个脚**要并排出来，缺的不是余量是**车道**。 -把 `C%05` 北移 0.6、让 SW 整条不再下潜，才是解。 - -**3. `verify()` 只认「同宽」的线会报假阳性。** -一段窄线整个落在宽线的圆头端帽里时 EasyEDA 会**直接吞掉它** —— 铜一点没少， -回读却报 5 条对不上。判据改成「实测线不窄于计划线，且中心距 ≤ (o_w − p_w)/2」。 - -**4. `chamfer_routes(smooth=True)` 会挪线（最多 0.15 mm），不只是拿掉铜。** -而它的净距校核拿的是**切之前**的自身路径 ⇒ 两条本轮新画的线会被各自抹到对方身上 -（实测 `$1N227` vs `POGO1_PWR` 压成 **−0.199**，2255 段里 2 段）。 -⇒ 切完再跑一遍 `check()`，**把牵涉到违规的整条退回未切的版本**，最多退 4 轮。 - ---- - -### ✅ 这一轮（2026-09-06 第二十轮）：下板信号布线 —— 工具全套建好，⛔ 没下发 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | 新增 **`pcb1_netlist.py`**：按**实测铜**（含回读的铺铜）算全板连通性 | 还欠 **200 个网络 / 384 条连接**；顺带发现 GND 其实早就通了 | -| 2 | 新增 **`pcb1_route_sig.py`**：下板信号布线器（复用载板栅格引擎，只加不拆）| 379 条里布通 **284 条（75%）**，净距 / 钻孔 / 铺铜 **三样全 0** | -| 3 | 新增 **`pcb1_escape_audit.py`**：逐个焊盘算「能不能走得出去」 | 563 个待接焊盘里 **22 个几何上出不去** | -| 4 | Kelvin 三条（`U13.8/9/10` ↔ `Rs6`）单独钉死，不许就近扎平面 | 3 / 3 条，w 0.30 | -| 5 | USB 差分对「**一整束布线 + 平行偏移**」 | 束长 58.1 mm，W 0.28 / S 0.18，**对内偏斜 0.00 mm** | -| 6 | 修掉 4 个真 bug（见下） | — | - -#### ⭐⭐ 这一轮最值得记住的四条 - -**1. POLYGON 焊盘的**包围盒**不是它的形状 —— 又一次。** -§26.13 抓的是它的 `hole` 是假的；这一次是 `pad[1], pad[2]` 那对宽高。 -TPS54622 的散热盘是个**带四个缺口的多边形**（缺口正是让给 pin 1/7/8/14 的）， -按 2.032 × 4.320 的包围盒当障碍，这四个脚**整个泡在 GND 铜里**： -`entry_stub` 一个出线方向都找不到，`BUCK_PG` 报「五路全布不通」。 -⇒ **POLYGON 焊盘的任何标量属性都不能直接当几何用**，只能读 `pad[1]` 那串点。 - 现在 `pcb1_route_sig.poly_pads()` 把 11 个多边形盘按真实轮廓光栅化成矩形条。 - -**2. 网名里带 `#` 的网络会被引擎的 `netof()` 拆坏。** -引擎用 `key.split('#')[0]` 从「路径 key」还原网名，而下板有 `KEY_OE#` 和 `IOEXP_INT#`。 -`'IOEXP_INT#' + '#0'` 拆回来是 `IOEXP_INT` ⇒ 校核时它和**自己的焊盘**被当成异网， -报「线-焊盘 净距 −0.100」，看上去像压线，其实两者本来就该连在一起。 -⇒ 分隔符改成 `chr(0)`。**凡是「用某个字符拼 key」的地方，都要先问一句这个字符会不会出现在数据里。** - -**3. 45° 切角会切进铺铜里 —— `seg_slack()` 不认铺铜。** -切角是往拐角**内侧**补铜（不是只拿掉铜），而引擎的切角校核只看焊盘 / 过孔 / 走线。 -实测 `SDA` 在 (6.10, 65.50) 被切进 `VO1_P` 小岛，只剩 0.043。 -⇒ 把铺铜矩形条包装成「假焊盘」一起喂给 `chamfer_routes()` 和 `check()`。 - -**4. 0.5 脚距的脚，「放得下」和「栅格上走得通」是两回事。** -`U8.3`（INA226 的 ALERT）：西边 1.00 mm 是 GND 扇出孔，东边 1.00 mm 是邻脚的出线段。 -0.20 的线需要 **1.005 mm**（差 5 µm 过不去），0.15 的线只要 0.955 mm —— -可 0.1 mm 栅格上判据要各加一个 QERR 0.0707，变成 1.096 mm，**整片不可达**。 -0.025 mm 栅格的 QERR 只有 0.0177，同一条缝就通了。 -⇒ 新增「**细栅格逃逸**」：0.1 栅格上出不来的脚，先在 4 mm 内用 0.025 栅格单独走出去。 - 实测 47 个脚里救回 **25 个**。 - -#### ⛔ 剩下 22 个脚是**几何上就没有出路**，必须动板子 - -| 组 | 焊盘 | 卡在哪 | 差多少 | -|---|---|---|---| -| **A** | `U1.10 U2.10 U3.10 U4.10 U5.10`（Buck 的 `EN`）| `pcb1_route_pwr` 的 **SW-run 1.5 mm 铜**，圆头端帽从 (20.05,27.10) 往西探到 x 19.30 | 脚东边净空 0.376，一根 0.2 的线要 0.6 | -| **B** | `U14.2/3` `U15.2/3/14/15` `U16.2/3/14/15` `U17.2/3` `U18.2/3`（eFuse 北排）| 上面 INA226 的焊盘边 **只隔 0.33 mm**，下面自己的散热盘 **0.25 mm** | 要 ≥ 0.6，缺 ~0.7 mm | -| **C** | `U10.3`（ALERT）`U13.4`(SDA) `U13.5`(SCL) | 隔壁 GND 扇出孔正对着出线走廊 | **5 µm** | - -**A 组的解**：EN 是每路都有的信号，本来就该进 §10.2 母版 —— 在 `pcb1_route_pwr.R` 里 -加一条 `EN` 路径，并把 `SW-run` 的起点往东挪 ~0.35 mm（或前 2 mm 收窄到 1.2）。 -收窄反而**符合** §10.2-2「SW 铜箔面积压到刚好够载流」。 - -**B 组的解**：CH1 那一列从下往上是 `C106(顶 43.46) → U14(43.85~47.75) → U8(48.08~53.92) -→ Rs101(54.27~57.73)`，缝一律 0.33~0.39 mm，**一点余量都没有**。 -唯一的空地在 Rs101 顶到通道北界 y 59 之间的 **1.27 mm** -⇒ 把 `U8 + Rs101` 整体北移 **0.7~0.8 mm**（母版改一处 = 五路一起改）。 -⚠️ 这会连带作废 **扇出 + 铺铜 + 五路功率级布线**（`U*.9 → Rs*01.1` 的 Kelvin 线也在母版里）。 - -**C 组的解**：给那两三个 GND 扇出孔在 `pcb_fanout._CH_FORCE_LOCAL` 里钉一个偏 0.1~0.2 mm 的位置。 - -#### ⚠️ 另外 95 条是**拥挤**，要拆线重布才能再往前 - -失败集中在**控制块（U21~U23，x 75~107 / y 43~58）**和 **J24/J25 排针**周边； -按网络族数：`$14N` 9 / `$8N` 7 / `$12N` 7 / `EFUSE_PG` 6 / `$10N` 6 / `INA_ALERT` 5 … -现在这个布线器是**一遍过、只加不拆**（这是有意的：板上已有 691 条线不能被抹掉）， -所以先布的把后布的堵死了 —— 这正是商业布线器用 **rip-up & reroute**（协商式拥塞）解决的那一类。 -⇒ 下一轮要么加拆线重布，要么等 A/B/C 三组改完再看还剩多少。 - -#### 顺带记两条 - -- `POGO2_VUP` / `POGO2_VDN` 离 SW 节点只有 **0.54 / 0.64 mm**（§10.3 要求「远离」）。 - 已经有 `sw_keepaway()` 在报，不当错误、只列出来。 -- 8 个 45° 切不动的拐角（转向 89~90°），都在细缝里，`chamfer45` 试到 0.05 半径仍撞墙。 - -#### 这一轮的产出（都在 `.claude/` 下，**没有一个动过板子**） - -| 文件 | 用途 | -|---|---| -| **`pcb1_netlist.py`** | 按**实测铜**算连通性：焊盘 / 过孔 / 走线 / **回读的铺铜**当图的节点，`--todo` 列还欠几条，`--json` 出任务表。⚠️ 判据不能只测焊盘中心那一格：同网通孔盘在回读的环里是个**洞** | -| **`pcb1_route_sig.py`** | 下板信号布线器。`--net` / `--limit` / `--push` / `--clean --push` / `--verify` / `--refresh`。内含 Kelvin 强制表 `FORCE`、USB 束 + 偏移、细栅格逃逸、铺铜障碍、`sw_keepaway()` | -| **`pcb1_escape_audit.py`** | 逐焊盘的**逃逸可达性**：两层泛洪 + `via_ok()` 打通，走不到 4 mm 外就报。`--why <焊盘>` 列出挡路的铜。⚠️ 判据环不能取自由区最外圈（那一圈 `free()` 永远是假的）| - ---- - -### ✅ 这一轮（2026-09-06 第十九轮）：五路功率级精调（§26.13） - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | **修 POLYGON 焊盘的假 `hole`**（`dump_pads` / `pcb_fanout` / `pcb1_parts_dump` 三处）| 七个散热盘回到扇出名单 | -| 2 | 盘内阵列改成**按真实多边形**撒点 + 自适应间距 + 补中心孔 | U1~U5 **0 → 5** 个孔；U6/U7 0 → 4；eFuse 2 → 6 | -| 3 | 摆位 v9：`L*01` / `U*14` / `Rs*01` 各转 180°，`C*05` 与三颗输出电容挪位 | 四条回路的朝向全部理顺 | -| 4 | 新增 **`pcb1_route_pwr.py`**：母版 27 条路径 × 5 路 = 210 段，全部顶层 | 一路 74.8 mm，**SW 13.1 → 9.7 mm** | -| 5 | 新增 `pcb_fanout._CH_FORCE_LOCAL`：5 个焊盘 × 5 路 = 25 个 `FORCE_VIA` | 五路的扇出终于**真的一样** | -| 6 | 重跑全链：place → 扇出三步 → 铺铜 → 布线 → DRC | 495 孔 / 691 线 / 间距 0 / 物理 0 / 连接性 594 | - -#### ⭐⭐ 这一轮最值得记住的四条 - -**1. 「有孔 = 通孔盘」是错的判据 —— POLYGON 盘的 `hole` 是假的。** -板上 11 个 POLYGON 盘无一例外满足 `hole = 0.600 × min(w,h)`（U1 的 2.032×4.320 → 1.2192， -U6 的 1.70×1.70 → 1.02，J22 的 1.30×0.60 → 0.36），EasyEDA 渲染出来是实心的。 -判据应该是**层号**：`layer == 12` 才是多层通孔盘。 - -**2. 五路的扇出结果并不相同 —— 明明摆位一模一样。** -扇出规划器的候选角度按**板坐标**排，而 CH2/CH3 整路转了 180°， -同一个焊盘在 CH1 往东扇、在 CH2 就往西扇。母版里算好的走廊于是在 CH2/CH3 上被堵死， -而报出来的是「CH2 的 F-trunk 撞到一个 GND 过孔」——**看上去像布线画错了**。 -⇒ 关键焊盘按 CH1 的解钉死（`FORCE_VIA`），钉死之后照样走全套净距校核。 - -**3. DRC 的「物理错误」那一支平时是空的，容易漏看。** -0.28/0.25 的线下发之后：**间距错误 0、连接性还降了 125 条** —— -而 `物理错误·导线` 里躺着 50 条「线宽 11mil，应该 ≥ 11.8mil」 -（`SWNODE`/`PWR4A` 的 `strokeWidthMin` 都是 0.30）。加宽到 0.30 清零。 - -**4. 回读走线不能按端点比：EasyEDA 会在 T 形接点上把已有的线劈成两条。** -西侧那条 +12V 母线下发之后在板上是两条（支线接在中间）。 -按端点比报「210 段里 40 段对不上」，而铜一点没少。 -⇒ `verify()` 用**覆盖判据**：每 0.2 mm 取一个点，要求被同网同层同线宽的实测线盖住。 - -#### ⚠️ Kelvin 的那一条：`U*8.9` 不许有过孔 - -`U*8.9`（INA226 的 IN−）已经写进 `pcb1_pour.ROUTED_PADS`。 -让它走 `VO*_P` 小岛的话，取样点在岛上而不是分流电阻的焊盘上，中间隔着 -`Rs*01` 那三个扇出孔（并联约 0.5 mΩ）。Rs 只有 5 mΩ、满载才 20 mV， -**0.5 mΩ × 4 A = 2 mV = 10% 的读数误差**，而 DRC 和连通性检查都看不出来 -（IN− 和 `VO*_P` 本来就是同一个网）。pin 8 是 VBUS，照旧进岛。 - ---- - -### ✅ 上一轮（2026-09-06 第十八轮）：F1 → 12 A / R9 → 5 × 2Ω 2512 - -两件都是用户拍板的选型改动，走完整链路：改原理图 → 导入变更 → 重推摆位 → -重扇出 → 重铺铜 → DRC。详见设计文档 **§26.12**。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | F1 `F1206HC10A0TM` → **`F1206HC12A0TM`**（C310990）| 同是 1206，**摆位一格没动**；封装对象换了(`F1206`)但焊盘几乎一样 | -| 2 | R9 立式水泥电阻 → **R9A~R9E 5 × 2Ω 2512 串联** | 10Ω/**10W**，高 **22 → 0.8 mm** | -| 3 | `pcb1_import.py` 加 **`--bom`** | 原来 `_p1_sch_bom.json` 在仓库里**没有生产者** | -| 4 | `pcb_fanout.py` 加 **`guard_not_pushed_twice()`** | 我推重了一次，888 个过孔（见下）| -| 5 | P1-INPUT 文字收拾 | 66 → 14 条，清掉一整代旧说明 | -| 6 | 结果 | 342 件 / 444 过孔（重复 0）/ 15 块铜面 / DRC **间距 0** + 连接性 725 | - -#### ⚠️ 先纠一条我上一轮写错的 - -「F1 封装是 1206 但 BOM 写 10A、1206 做不到 10A」—— **错的**。 -`F1206HC10A0TM` 本来就是 1206/10 A，BOM 和封装从来没对不上。 -换 12 A 的真实理由是**降额**：8/10 = 80% 超过保险丝常规的 75% 线，且 I²t 只有 15 A²s。 - -#### ⭐⭐ 这一轮最值得记住的两条 - -**1. `pcb_fanout.py --net all --push` 不幂等 —— 我连推了两遍。** -板上变成 **888 个过孔**（每个都有同坐标同网的副本），而**短线数没变**（444）： -EasyEDA 把共线重叠的新线并进了旧线。**连接性 DRC 一个字不报**（副本同网，电气上「没错」）。 -唯一判据是**回读过孔数**。现在 `--push` 前会硬拦；重推必须 -`--clean → dump_pads.py → --push` 一次跑完。 - -**2. `H_FP` 里那个 9.5 是照封装名 `W9.5` 抄的，而 R9 是立式件。** -`RES-TH_L13.5-W9.5-P5.80-D0.7`：**本体 13.5 长、脚距只有 5.80 ⇒ 它站着** -（同族 3D 模型标 `H52.0`）。那一片 hmax 只有 12.0， -所以「高度预算全过」在它身上假了整整一轮，**是用户看出来的，不是检查看出来的**。 -⇒ 往 `H_FP` 加直插件的判据：**脚距和本体长度对不上就是立式**， -高度不是封装名里的 W，是那个对不上的方向。 - -#### ⛔ 新增的两个地雷标记 - -- **`p1_add.py` 已过期**，底稿 `p1-base.json` 停在 2026-09-04。再推一次会把 - R9A~R9E 之间那 6 段导线**静默回退**。已加硬闸门（要跑得带 `--i-know-it-is-stale`）。 - ⇒ **改完一页就问一遍：还有哪个脚本会重画这一页。** -- **改过原理图必须 `pcb1_import.py --bom` 再 `--verify`**，否则是拿新 PCB 和旧原理图对账。 - -截图：**`PCB1-v8-r9f1.png`**（R9A~R9E 的 1+2+2 蛇形）/ **`P1-INPUT-v2.png`**（原理图）。 -**还没等到用户回话。** - ---- - -### ✅ 这一轮（2026-09-06 第十七轮）：8 A 顶层宽铜 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `pcb1_pour.REGIONS` 加三块顶层铜面 | `VINRAW-TOP` 46 / `VINFUSED-TOP` 19 / `VINSW-TOP` 284 mm²（实测）| -| 2 | 网名用 `pcb1_rules.resolve_auto()` 当场反查 | `$1N223` / `$1N227` / `$1N236`，**一个字没写死** | -| 3 | **`Grid` 分内层 / 外层两套障碍模型** | 外层连贴片焊盘一起挡；新增 `obstacles()` 把 438 个过孔 + 441 条走线算进去 | -| 4 | 新校核 **`check_top_clearance()`**（不过格子）| 当场抓出两处侵入，**其中一处栅格看不见** | -| 5 | 新校核 **`poly_vs_rects()`** | 手写的 24 个点 vs 它该等于的 8 个矩形，0.05 mm 逐格对照 | -| 6 | 下发 + 回读实测铜 | 15 块铜面全部铺出来，三段各 **1 个连通域** | -| 7 | DRC | 间距 **0** / 连接性 **719**（铺顶层铜前是 733）| - -#### ⭐⭐ 这一轮最值得记住的：**线的端点不是铜的端点** - -北柱东缘写在 x 6.8，Rs6.2 那条 +12V 出线的端点在 x 7.401 —— 看起来隔 0.6 mm。 -但那条线 **1.0 mm 宽、圆头端帽往外再探 0.5 mm**，实际铜到 x **6.901**， -真实净距只有 **0.101 mm**。而 0.25 mm 的栅格上这 0.1 mm 一个格心都落不进去 -⇒ **栅格全绿**。真下发下去 EDA 自己会往回缩一点点铜，板子不会报 DRC， -但**板上那块铜就不再是计划里那块铜，后面所有断面数字全部作废**。 - -⇒ 凡是手画的铜，都要过一遍 `check_top_clearance()` 这种**真实几何**的校核， -栅格只能用来算连通域和断面。 - -#### 顶层三段长什么样（实测断面，顶层 1 oz） - -最窄两处：干道 x=12 处 **4.75 mm（10.0 A）**、北柱 y=92 处 **5.00 mm（10.4 A）**， -8 A 下 ΔT 分别约 12 / 11 °C。其余各点 8.75~21.5 mm。 - -截图：**`PCB1-v7-top8A.png`**（只开顶层 + 焊盘 + 顶丝印）。**还没等到用户回话。** - -#### ⚠️ 顺带看出来的一件：**F1 的封装是 1206，但 BOM 写的是 10 A** - -`FUSE-SMD_L3.2-W1.6-1` = 1206，而 §7 的 BOM 写「保险丝 10A 慢断」。 -**1206 的贴片保险丝一般做到 5 A 左右就到顶了**。8 A 的铜宽本身没问题， -是**器件选型和封装对不上**。换大封装会动 J1→F1 那一段的摆位 -⇒ 要**重推摆位 + 重扇出 + 重铺铜**。这一条留给用户拍板。 - ---- - -### ✅ 这一轮（2026-09-06 第十六轮）做完的 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | **修去耦电容摆位**：新增 `pcb1_place.DECAP` 表 + `place_decaps()` | 7 颗跟着本尊走，最远的储能 3.31 mm，其余 0.76~2.24 mm | -| 2 | **修 `pcb1_parts_dump.py` 漏了焊盘自身旋转** | 8 个元件的 bb 各长 0.26~0.30 mm（U1~U5 / U6 / U7 / U20）| -| 3 | 新增 **`pad_clearance_errs()`**：焊盘到焊盘净距 0.2 mm | 全板 1171 个焊盘一条不报 | -| 4 | 修 `pcb_fanout.TARGET`（还停在 §26.8 之前）| 删掉 `VOn` / `+5V` / 8 A 三段，它们不上 Inner2 | -| 5 | 修 `_pour_filter()`（指着单板时代的 `pcb_pour.py`）| 改指 `pcb1_pour.REGIONS`；实测滤掉 17 个铜面外的 `+3V3` 焊盘 | -| 6 | 扇出规划器补五条（见 §26.9）| GND/+12V/+3V3/VOnP **全部失败 0 个** | -| 7 | 扇出下发 | 438 过孔 + 441 短线，**DRC 间距 0** | -| 8 | **实现 `pcb1_pour.py --push` / `--verify`** | 12 块铜面已下发；回读实测铜 **24 项全 OK** | -| 9 | 下发前 / 下发后**共用同一段 `grid_checks()`** | 分两套写只能证明两套代码各自自洽 | -| 10 | 新校核：**每块碎片都要有本网过孔落脚**（浮铜）| 9 组 (网络,层) 的 12 块碎片全部有落脚 | - -#### ⭐⭐ 第 1 条是这一轮最重要的发现：ESP32 的储能电容在 48 mm 外 - -追「U6.15 为什么扇不出去」追出来的。全板 20 个 IC 的 `+3V3` 电源脚里 -**只有 1 个的去耦在 3 mm 以内**；`C601`（22 µF「ESP32 储能」）离 U20.2 **48.2 mm**， -`C602`（100 nF）**45 mm**，U20 电源脚周围 12 mm 内一个元件都没有。 - -根因：控制块是 `affine(['P3-CONTROL','P3B-EXPAND'], ...)` 按**原理图坐标**仿射映射摆的， -它保「原理图上挨着的板上也挨着」，保不住「去耦贴着电源脚」； -而 **U20 是上面手工单独摆的 —— 芯片被拎出了仿射集合，去耦却留在原地**。 - -⇒ **动控制块布局时先看 `DECAP` 表**，它是这件事的事实来源，`check()` 里有硬校核。 -表的顺序 = 抢位置的顺序，**小的高频那颗必须排在大的储能之前**（理由见 §26.9）。 - -#### ⭐⭐ 第 2/3 条：本地检查曾经「全绿而板子是错的」 - -改完摆位本地六项全过，DRC 却报 4 条间距错误：`C607_2` 到 `U6_13` 只有 **0.096 mm**。 -两个原因叠在一起 —— -`pcb1-parts.json` 的包围盒漏了**焊盘自身的旋转**（QFN 侧边脚是长条焊盘转 90° 用的， -U6 的 bb 在 y 上短 0.26 mm）；而 `check()` 只查「包围盒重不重叠」，**不重叠不等于够净距**。 -现在两条都修了，新检查直接照 DRC 那条 0.2 mm 的规则算，量焊盘不量包围盒。 - -> ⚠️ 同一套 API 里 `getAllPinsByPrimitiveId` 的 rotation 是**度**， -> `pcb_PrimitivePad.getAll()` 的是**弧度**。 - -### 下板 PCB1 接下来的顺序 - -0. **让用户人眼确认摆位 v9 + 功率级布线**（截图已出，见上面「一句话现状」）。 - 不算硬阻塞，但这一轮动过五路的摆位，值得看一眼。 -1. ~~设计规则~~ ✅ §26.7　2. ~~定铺铜几何~~ ✅ §26.8 -3. ~~扇出~~ ✅ **§26.9 / §26.13**　4. ~~铺铜~~ ✅ **§26.10，已下发并回读复核** -5. ~~8 A 输入链顶层宽铜~~ ✅ **§26.11，已下发并回读复核** -6. ~~五路功率级精调~~ ✅ **§26.13，已下发并回读复核** -7. ~~写下板信号布线器~~ ✅ **`pcb1_route_sig.py` 已建好并跑通 75%（第二十轮）**， - `pcb1_route_pwr.py` 那 210 段一根没动（这个布线器只加不拆，删除只按坐标删自己画过的）。 - -8. ~~A/B/C 三组几何整改~~ ✅ **§26.15，用户拍板 A+B+C，已全链重跑并下发**。 - 全链的正确顺序（动过摆位就照这个走，一步都不能省）： - `pcb1_place --push` → `pcb1_clear --push` → `dump_pads` → `pcb_fanout --net all --push` - → `pcb1_pour --refresh --push` → `pcb1_route_pwr --push` → `pcb1_route_sig --push` - → `pcb1_pour --refresh --push`（**给新过孔补反焊盘**）→ `pcb1_reload` → `drc_read`。 - -9. ⬅️ **下一步：给 `pcb1_route_sig.py` 加拆线重布**（rip-up & reroute），收掉剩下的 91 条。 - ⚠️ 直接再跑一遍 `pcb1_route_sig.py --refresh --push` 也会有进展（它读板上的铜、 - 只补还缺的），但一遍过的策略已经到顶了 —— 真要清零得能拆别人的线。 - - ⚠️ **北左角的顶层现在被 8 A 宽铜占了大半**（x 1.5~28.9 / y 68.6~93）。 - U13 的 I2C、U29、R9 那几条信号得**走底层**—— 底层整层基本是空的，不占地方。 - 三条还没布的细线已经有名有姓地写在 `pcb1_pour.ROUTED_PADS` 里： - `U13.10`（Kelvin VIN+，接北柱顶端那一小截死头）/ `DZ1.1` / `C1.1`（栅极）。 - -⚠️ **动了铺铜或摆位就要重跑 `pcb1_pour.py --push`**，它自己会先把计划跑绿再下发； -下发完自动 `--verify` 回读实测铜。只想看不想改板就 `--verify`（加 `--cache` 用上次的回读）。 - -⚠️ **动过摆位就要重跑扇出三步，不能省也不能并**： -`pcb_fanout.py --clean` → `dump_pads.py` → `pcb_fanout.py --net all --push`。 - -⚠️ **连接性数字扇出之后会先涨再跌**：布线前基线 1145 → 扇出完 **1336** → 铺完铜 **733**。 -过孔本身是新对象，铺铜之前每一个都是自己网络里的孤岛。 -**只看扇出完那一步会以为扇出把事情弄坏了。** - -⚠️ **EasyEDA 客户端这一轮掉线过三次**（`EDA window ... disconnected`）。 -掉线时命令**可能已经执行完**只是回话丢了 —— 别直接重试，先回读板上对象数再决定。 - -### ⚠️⚠️ 一条永远别忘的：J24 / J25 的针号是**故意错一位**的（§26.5，用户已拍板选 A） - -`p5_btb.py` 的 **`MATE_SWAP = True`** 让下板这一侧的网络按针号奇偶对调 -（两颗封装焊盘编号同手性 + 母座在载板底层、顶视图镜像一次，不改的话下板 `VO1_P` -会顶在载板 `GND` 上）。`c1_conn.py`（载板 C1-CONN）用的是原始表，**一个字没动**。 -⇒ **判据是网络不是针号**：下板 pin(2r−1) 正对载板 pin(2r)，差一位是**预期的**。 -每次动完摆位跑 `pcb1_place.py --verify` 逐个焊盘核。 - -### Inner2 分块的结论（详见设计文档 §26.8） - -| 层 | 网络 | 名称 | 形状 | -|---|---|---|---| -| Inner2 | `+12V` | `12V-N` | 北带 y 88~124.5 通板 + 风扇指下伸到 y 66.5，挖掉 U13 那一角 | -| Inner2 | `+12V` | `12V-SW+BR` | 南西块 (0.5~72, 9~34) + 中桥 (61.5~72, 34~88)，⌐ 形 | -| Inner2 | `+12V` | `12V-SE+RC` | 南东块 (116~159.5, 9~34) + 右通道 (153.5~159.5, 34~88)，L 形 | -| Inner2 | `+3V3` | `3V3-SW` / `3V3-SE` | 南部两块，**故意不连通**（见下）| -| Inner2 | `GND` | `GND-FILL-L3` | 剩余全部 | -| Bottom | `VOn_P` | 五块小岛 | 各约 18 × 13 mm | -| Inner1 | `GND` | `GND-L2` | 整板，只挖 ESP32 天线区 | - -**退回走线的四类**（都算过，不是省事）：`+5V` 底层 1.2 mm 干线 / `VOn` 顶层 1.5~2.0 mm / -`VOn_P` 底层小岛 / **8 A 输入链顶层宽铜 ≥3.5 mm**。 -关键数：内层 0.5 oz 与外层 1 oz 差约 **4 倍**（8 A 内层要 18.2 mm，外层只要 3.49 mm）， -而这块板**底层整层是空的** ⇒ 短距离大电流根本不该上内层。 - -⚠️ **`+3V3` 在 Inner2 上是 2 个连通域，是设计意图不是漏接。** 中桥必须纵向穿过 -y 41~58.5 那条带，而 `+3V3` 的南部焊盘横向铺满同一条带 —— 同一层上两个都要连通的 -2-D 区域，交叉拓扑上避不开。让 0.5 A 的那个换层：南西 / 南东各自从北边引一条底层干线。 - -### ⭐ 这一轮校核当场抓到的一个错：孤岛判定是**按铺铜对象**算的，不是按网络 - -第一版把 +12V 写成六个矩形，栅格连通性说「1 个连通域」，看着完全正常。 -新加的孤岛规则校核报出来：`12V-RC`（右通道）**里一个 +12V 焊盘都没有** —— -哪怕它和北带紧挨着、铺出来是连续铜，它自己那一块里没有本网焊盘/过孔照样被整块删光 -（边框还在、`nPoured` 是 0）。⇒ 并成三个 L / ⌐ 形多边形，每块各自含风扇座的通孔针。 - -另外两条：**只有通孔焊盘在内层挖反焊盘**（贴片对内层透明，板上实测 122 个通孔）； -**区域间净距不能用包围盒估**（L 形的 `3V3-SE` 包围盒把 `12V-FAN` 整个罩住， -算出来 0.00 mm 像严重违规，实际相距 0.50 mm）。 - -### 下板还欠的几件（都不影响现在动手） - -- **C2 / C3 罐高必须 ≤ 11.5 mm**（现在按 12.0 建模，`H_FP` 里那一条）。 - 载板底面在那块地方是光板，hmax = 12.0，卡着上限过；换一颗矮罐才有余量。§22.3f -- **CH2 的 `POGO2_*` 三根要横穿 60 mm**（信号在 J25、电源在 J24，载板那边决定的，§26.3）。 -- U20 的天线端离下板边只有 1.5 mm，而且上面还盖着载板 —— **这块板的 WiFi 本来就指望不上**， - 真要用就得把天线引出机箱。 -- 北中块 x 58~118 / y 85~125 有一块约 60 × 40 的空地（CH2/CH3 的排线车道从这里过）， - 留给电源面和风扇线，暂时不填。 - -### 下板 v6 的布局长什么样（设计文档 §26.3 / §26.4） - -``` - y 125 ┌──────────────────────────────────────────────────────────────┐ - │ P1-INPUT │ CH2 (北,rot180) │ P1B + P6 + J28 │ CH3 (北,rot180) │ - │ J1/F1/Q1/D1 │ x 30.1~57.3 │ x 58~118 │ x 118.5~145.7 │ - │ C2/C3/R9/U19 │ │ │ │ - y 66 ├───────────────┴──────────────────┴────────────────┴─────────────────┤ - 62.5 │ ==== J24 (x 5.3~58.7) ==== ==== J25 (x 101.3~154.7) ==== │ - y 59 ├───────────────┬──────────────┬─────────────────┬────────────────────┤ - │ CH1 (南) │ CH4 (南) │ P3/P3B 控制块 │ CH5 (南) │ - │ x 10.6~37.8 │ x 42.3~69.5 │ U20/U6/U21~23 │ x 121.8~149.0 │ - y 0 └───────────────┴──────────────┴─────────────────┴────────────────────┘ - J26/J27 左板边 J29/J30 右板边 J28 顶板边 J22 调试口在右板边 -``` - -### 下板新加的工具（`.claude/` 下） - -| 文件 | 用途 | -|---|---| -| **`pcb1_import.py`** | 下板「从原理图导入变更」：`--probe` 读全部变更行 / `--apply` 真的导 / **`--verify` 拿 PCB 元件表和原理图 BOM 逐条对账** | -| **`pcb1_parts_dump.py`** | 抓 `pcb1-parts.json`（每件的真实焊盘框 + 每个焊盘的本地坐标）。**导入变更之后必须跑** | -| **`pcb1_env.py`** | 把载板底面折算成下板的**高度预算图** `pcb1-env.json`（zones / lanes / slots / J24-J25 锚点）；`hmap()` 打一张 ASCII 高度地图 | -| **`pcb1_place.py`** | 下板摆位模型 + 本地六项检查 + `--push` / `--verify`（回读焊盘核对插）| -| **`pcb1_clear.py`** | 拆掉下板全部铜（导线 / 过孔 / 铺铜边框），保留板框、M3 焊盘、丝印 | -| **`pcb1_rules.py`** | 下板设计规则：线宽 5 档 / 差分 1 对 / 铺铜全连接；**自动命名网按位号+引脚反查**。`--push` / `--check` | -| **`pcb1_place.DECAP`** | **去耦电容跟着本尊走**的事实来源（第十六轮加）。表里的电容不参与仿射摆位，芯片摆完之后自动贴到电源脚旁边；`check()` 里有硬校核 | -| **`pcb1_place.pad_clearance_errs()`** | 全板**焊盘到焊盘**净距（0.2 mm，照 DRC 那条规则）。「不重叠」不等于「够净距」 | -| **`FANOUT_WHY=U6.15`** | 环境变量。打印这个焊盘所有候选孔位**卡在哪一道校核上**，按次数排序 | -| **`p1_r9f1.py`** | P1-INPUT 换件（F1 → 12 A / R9 → R9A~R9E）。**增量**改法：先 create 后 delete、旗删掉重建、坐标全 5 的倍数、引脚坐标断言不过就停手 | -| **`p1_text_fix.py`** | P1-INPUT 文字去重 + 挪位。幂等（新增块也走「先删再建」），逐条对账最终 14 条 | -| **`pcb1_import.py --bom`** | 逐页重抓原理图 BOM（`_p1_sch_bom.json`）。**改过原理图先跑它再 `--verify`**，一页一个请求（`eda.py` 截 20000 字符）| -| **`pcb_fanout.guard_not_pushed_twice()`** | 板上已有过孔就拒绝 `--push`。这脚本**只加不删不幂等**，推两遍会叠出同坐标副本而**短线数和 DRC 都看不出来** | -| **`pcb1_pour.check_top_clearance()`** | 顶层手画铜面到异网铜的**真实几何净距**（不过格子）。0.25 mm 栅格漏得掉 0.1 mm 的侵入；**走线的圆头端帽比端点还往外探半个线宽** | -| **`pcb1_pour.poly_vs_rects()`** | 手写的复杂多边形 vs 它该等于的矩形并集，0.05 mm 逐格对照。写错一个坐标，别的检查一个都发现不了 | -| **`pcb1_pour.obstacles()`** | 板上已有的铜（438 过孔 + 441 走线）。**顶层铺铜要躲它们**，内层只躲过孔 | -| **`pcb1_route_pwr.py`** | 五路功率级手工布线的**事实来源**（§10.2 四条回路）。路径写在 CH1 母版局部坐标里，仿射到五路。不带参数 = 计划 + 五项校核；`--push` 下发（`--clean --push` 先删本轮旧线）；`--verify` 按实测铜核**覆盖**；`--ch N` 只看一路 | -| **`pcb1_netlist.py`** | 下板连通性的**事实来源**：按实测铜（含回读的铺铜）算每个网络还欠几条。`--todo` / `--json` / `--refresh`（第二十轮加）| -| **`pcb1_route_sig.py`** | 下板信号布线器（**只加不拆**）。Kelvin 强制表 / USB 束+偏移 / 细栅格逃逸 / 铺铜当障碍 / `sw_keepaway()`（第二十轮加）| -| **`pcb1_escape_audit.py`** | 逐焊盘的**逃逸可达性**。「布不通」到底是这一头出不来还是中间挤，只有它分得清（第二十轮加）| -| `pcb1_reload.py` | 下板专用的客户端重载（DRC 的连接性那一支要 reload 之后才准）。⚠️ **别拿 `pcb2_reload.py` 当通用工具**：那一份写死载板 uuid，而且会把板上全部铺铜边框删掉 | -| `pcb_fanout._CH_FORCE_LOCAL` | 五路通道里必须**五路一样**的那几个孔（按 CH1 的解钉死再展开）。不钉的话 CH2/CH3 会往反方向扇 | -| **`pcb1_pour.py`** | 下板铺铜的**事实来源**：`REGIONS` 定义每一块。不带参数 = 计划 + 五类校核 + ASCII 分块图；**`--push`** = 校核跑绿才下发，完事自动回读复核；**`--verify`**（`--cache` 用上次回读）= 只按**实测铜**再跑一遍。下发前后走的是同一段 `grid_checks()` | - -⚠️ `pcb_rules.py` 是**单板时代**的，已被 `pcb1_rules.py` 取代，别再 `--push` 它。 -⚠️ `pcb_fanout.py` **仍然是下板在用的**（`PCB = 7e94…`），载板的 `pcb2_fanout.py` 是它的壳。 - -⚠️ `pcb_place.py` / `pcb-parts.json` / `pcb-pads.json` 是**单板时代**的，别再拿来摆下板。 - -### ✅ 已拍板并落地：C745 往南挪 2.7 mm（2026-09-06，用户选 A） - -`C745` 从 A 圈上的 (100.05, 61.70) 挪到 **(100.0, 59.02)**（`pcb2_place.hub_layout()` 里单列一条， -不再跟着 A 圈的 `for` 循环走）。GND 脚 (100.0, 58.60) / +3V3 脚 (100.0, 59.44)， -扇出孔实际打在**正东** (100.87, 58.60)，引线 0.65。 -`pcb2_place --push` → `pcb2_clear`（跨元件净距全过）→ `pcb2_fanout --only C745.2 --push` -→ reload → pour → `inner1_verify`（五块岛仍各 1 连通域）→ DRC **115 间距（基线）+ 332 连接性**。 - -⇒ **载板上除了 J7n 那 65 个 GND 脚（归 `bm24_pre()` 管），贴片 GND 焊盘已经全部扇出。** - -`pcb_fanout.py` 顺手加了 `--only 位号[.引脚],...`：板上已经有整轮扇出、只想补一两个漏网的时候用， -不会重复下发另外那 247 个。 - -
当初为什么非挪不可（留作记录） - -| 方向 | 挡住的东西 | 余量 | -|---|---|---| -| 南 | `UP_DM` 东行段 y=60.60（宽 0.28）| 孔要 0.64，只有 0.41 | -| 北 | 自己的 pin1 → 再往北是 U32 南排焊盘 y=63.55 | 缝 0.73，要 1.0 | -| 东 | R715 pin2 | 缝 0.667，要 1.0 | -| 西 | `UP_DM` 竖段 x=99.25 / `UP_DP` 竖段 x=98.75（相距 0.5）| 塞不下 Ø0.6 的孔 | - -并到邻近同网焊盘也不行 —— 最近的 GND 是 C743 pin2（2.70 mm 外），中间横着这两条竖段。 -
- -### （已作废）等用户拍板：C745 的 GND 脚被 UP 差分对堵死 - -`C745`（Hub 的 +3V3_HUB 去耦 0402，GND 脚在 (100.05, 61.28)）是全板**唯一**扇不出去的焊盘。 -不是搜索不够狠，是几何上真的没有位置： - -| 方向 | 挡住的东西 | 余量 | -|---|---|---| -| 南 | `UP_DM` 东行段 y=60.60（宽 0.28）| 孔要 0.64，只有 0.68−0.27=0.41 | -| 北 | 自己的 pin1（+3V3_HUB）→ 再往北是 U32 南排焊盘 y=63.55 | 缝 0.73，要 1.0 | -| 东 | R715 pin2 | 缝 0.667，要 1.0 | -| 西 | `UP_DM` 竖段 x=99.25 / `UP_DP` 竖段 x=98.75（相距 0.5）| 两条之间塞不下 Ø0.6 的孔；西边那条缝只有 0.01 mm 宽 | - -并到邻近同网焊盘也不行 —— 最近的 GND 是 C743 pin2（2.70 mm 外），中间横着这两条竖段。 - -**三个选项**（都要改布局，所以留给用户定）： -- **A. C745 转 90° 并东移到 (100.0, 61.7) 一带**（脚变成东西向，GND 脚在西）。 - 实算过：孔打在 (100.0, 62.47) 时离 UP_DM 竖段 0.75、离 U32 pin56 焊盘框 0.15，都过。 -- **B. 把 UP_DM / UP_DP 那两条东行段整体往南挪 0.3~0.5 mm**（要重推 `pcb2_dp_long.py`， - 下游 J23 那一头也要跟着动）。 -- **C. 不管它** —— 那一颗去耦电容的地就只能靠 `pcb2_gnd_patch.py` 想办法， - 想不出来就是一条连接性 DRC，实物上等于这颗电容白焊。**不推荐**。 - -### ✅ 这一轮（2026-09-06 第十三轮）：**载板 77 个信号网络全部布通并下发，DRC 回到基线** - -| | 结果 | -|---|---| -| `pcb2_route_sig.py` | **87 个网络 / 459 条路径 / 1030 线 / 210 孔**，一个没布通的都没有 | -| 本地净距校核 | 全部通过 ✔ | -| `pcb2_gnd_patch --check` | 板上悬空的 GND 连通域 **0 个** | -| `inner1_verify` | 五块岛各 1 主域、3 焊盘 + 11 过孔全在主域，最窄 29.20 / 7.05 / 7.20 / 7.70 / 7.60 | -| `pcb2_route_dp`（回归） | 11 对差分偏斜全部 ✔（最大 4.75 mm） | -| **DRC** | **115 条 = 全部是封装自带的「贴片焊盘到贴片焊盘」基线；间距 0 新增、连接性 0** | - -⇒ **载板 PCB2 布线完成。** 截图 `PCB2-v6-routed-all.png` / `PCB2-v6-hub.png` / `PCB2-v6-site4.png`。 - -#### BM24 那一段是整个重写的（v4 的常量在 v5 上全错） - -v5 把 J7n 从 rot 180 改成 rot 0 又挪了位置，站内坐标整体差 -**`u' = u − 5.00` / `v' = 32.00 − v`（v 轴是镜像的）**。 -照抄映射也不行 —— v 一镜像，「前排外侧那条缝」换到了另一边，而那边站着 R76n/R77n。 -v5 的走法（和 v4 反过来，因为**后排 25 个脚在 v5 里全是 GND**，没有信号脚要往外挤）： - -- **前排 5 个 GND（pin 2/8/12/16/24）→ 往内进中央通道**，v=35.00 的 0.30 梳子，4 个孔（跳过 u 50.05） -- **后排 7 个 GND（pin 1/19/23/29/37/41/47）→ 往外**，v=33.10 的梳子，5 个孔（那一带一路空到 v 26） -- **pin52** 往东平出到 u=59.60 打一个孔 -- **THERM / CC1 独占前排外侧**：CC1 一根直线上去（R76n 中心特意取 52.233，让 pin1 正好落在 J7n.22 正北）； - THERM 打两个孔走顶层跨过 CC1 - -新增 `j7_assert()`：**每次跑都拿板上实际焊盘核一遍那一堆手写常量**（五个站 × 13 个 GND 脚 + THERM/CC1 + R76n/R77n）。 -没有它的时候，坐标失配的表现是「在空地上画了五套梳子」—— 净距校核当然全过（空地不撞人）， -只有 DRC 的连接性会含糊地多出几十条。 - -#### 这一轮修掉的四个真 bug（都在 `pcb2_route_sig.py` 里） - -1. **搜索窗口边上没有墙**。障碍是裁到窗口里再栅格化的，**完全落在窗外的铜一格都不标**， - 于是贴着窗口边走的线看不见它。实测 `SCL` 的窗口从 x=44.02 起，J31.6 的焊盘框（42.10~43.80） - 整个在窗外，布线器就在 (44.10, 67.40) 打了个孔，离那焊盘只有 0.134。 - 改法：数组往外扩 `RIM=1.2` 标障碍，**再把外面这一圈整体标成占用** —— 可走区域不变，但看得见窗外的铜。 -2. **钻孔间距不分网络，但 `viafree` 只看异网铜**。于是布线器紧挨着 `pcb2_dp_long` 已经打好的孔又打一个 - （(92.500,70.000) 与 (92.400,70.500) 中心只隔 0.510），DRC 报「钻孔到钻孔 8.1mil，应 ≥ 11.8mil」， - 净距校核一声不吭。新增 `holefree` 距离场（**所有过孔、不分网络**）。 -3. **手写前置段没有一开始就进障碍表**。原来只有 GND 的在循环里补进去，THERM/CC1/+3V3 的要等轮到自己 —— - 排在前面的网络照样从这些手写坐标上碾过去。 -4. **`+3V3_HUB` 上 `pcb2_dp_long` 画的三条会被静默删掉**。`push_sig()` 是「本脚本负责的网络整网删掉重画」， - 而那三条被 D± 夹着、后面再也挤不进去。改成从**同一个事实来源**（`pcb2_dp_long.build`）取回来当前置段， - 既让最小生成树知道那些焊盘已经连上，下发时也原样重画。 - -#### 四段手写坐标（栅格布线器进不去的地方，理由都写在代码注释里） - -| 网络 | 为什么手写 | -|---|---| -| `THERM_n` | 出阵列后第一次拐弯的 v **只有 0.053 mm 的窗口**（下受前排焊盘、上受 `*_DPJ` 换层孔），而且那一段必须保持 0.11 | -| `+3V3_HUB` U32.52→U32.46 | pin46 在东排被 VBUS_DET/NONREM0 围死，唯一出路是往 QFN **肚子里**走（南排焊盘上沿与散热盘之间那条 1.6 mm 死带）| -| `+3V3_HUB` C750.1→R716.2 | R716.2 是最东那颗 +3V3 焊盘，南北被两个 GND 脚夹住，只能翻顶层斜拉过来 | -| `HUB_RST` / `VBUS_DET` | R709 与 R712 之间只有 **0.66 mm** 的缝。0.15 的线走得过去（上下各 0.23），但栅格判据要 0.371 而半缝只有 0.33 | - -#### 一处已知的口子（不是错，是要记住的事） - -`+3V3_HUB` 现在由 **`pcb2_route_sig.py` 下发**（含 `pcb2_dp_long` 那三条）。 -⚠️ **再单独跑 `pcb2_dp_long.py --push` 会把 route_sig 布的整个 +3V3_HUB 删掉重画**（它按网络整删）。 -要改差分的话，顺序是 `dp_long --push` → `route_sig --push`，不能只跑前一半。 -另外 45° 化把那条顶层干线的近直角拐点切成了两个 **51°** 的转折（`sharp_corners` 报「切不动」）—— -净距校核过、不是直角，属于可接受；但它意味着板上那条干线的几何**已经和 `pcb2_dp_long.py` 里写的不完全一样**。 - -#### 为此动的两处布局（都验过并重扇出） - -- **R76n/R77n：v 37.15 → 38.0**，R76n 的 u 顺带改成 52.233。 - 理由：J7n 前排逃逸带原来只剩 0.58 mm，THERM 和 CC1 一个往东一个往北**必然交叉**，同层无解， - 想让 THERM 翻顶层又打不下孔（要离前排 0.5 ⇒ v ≥ 36.80，又要离 R76n 0.5 ⇒ v ≤ 36.38）。 - 挪完逃逸带 1.43 mm，两条各走各的。挪之前先用新写的 `pcb2_del_box.py` 把 R77n.2 的旧扇出孔删掉。 -- **C745 往南 2.7 mm**（用户拍板，见下）。 - -#### 新工具 - -`pcb2_del_box.py`：删掉指定框里某个网络的线与过孔（板坐标或**站内坐标**，站内会自动展开到五个位）。 -板上的铜是好几个脚本各画各的，挪了元件之后那颗扇出孔就成了没人认领的孤儿 —— -谁的删除逻辑都不管，DRC 只报一条「过孔没连上任何东西」，很容易被当噪声放过。 -判据是**完全落在框里才删**（半进半出一律不动）。 - -`pcb_fanout.py --only 位号[.引脚],...`：板上已经有整轮扇出、只想补一两个漏网的时候用。 - -### 上一轮（2026-09-06 第十二轮）：GND 扇出 + VOn_P 进岛，两步都下发并复核 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `pcb_fanout.py` 补三个缺口（见下）；`pcb2_fanout.py --push` | **247 孔 / 122 短线**，只有 C745 pin2 扇不出去 | -| 2 | `pcb2_vo_vias.py` 扩到 35 个焊盘（补 `C8n1.1` 与 `J8n.1`，各 3 孔）并修出线层 | **55 孔 / 55 线**，净距全过、0 个直角 | -| 3 | `pcb2_reload` → `pcb2_pour --push` → `_refresh_geo` → `inner1_verify` | 五块岛各 **1 连通域**，3 焊盘 + 11 过孔全在主域；最窄 31.30 / 7.05 / 7.20 / 7.70 / 7.60（下限 7.0）| -| 4 | `drc_read --pcb2` | **450 = 间距 115（与基线一模一样，无新增）+ 连接性 335**（布线前 519，−184）| -| 5 | 截图 `PCB2-v5-fanout-all.png` / `PCB2-v5-fanout-site1.png` / `PCB2-v5-inner1.png` | | - -#### 这一轮修掉的四个「一直在但没暴露」的 bug - -- **扇出规划器从来不看板上已有的走线**（只看焊盘 / 过孔 / 钻孔）。下板做扇出时板上一根线都没有， - 所以从没暴露；载板 v5 是先布了 178 条差分 + 3V3 才扇出的，不修的话过孔会直接压在 D± 上， - 而**几何验证抓不到**（它只查连通性）。现在 `EXIST_LAYERS` 把 1/2/15/16 层的线全登记成障碍， - **线对线分层比、过孔对线不分层**（过孔贯穿）。 -- **`dump_pads.py` 有 88 个焊盘认不到位号**：pad 坐标是干净的、pin 坐标带 1 µm 噪声， - 两边各自 `Math.round` 到 0.01，落在 `.xx5` 上的值进了不同的桶。改成 Python 端最近邻配（容差 0.02）， - 846 个里认到 805（剩下 41 个是螺钉孔和手机定位柱，本来就不属于任何元件）。 - **这个 bug 会静默传染**：J75 pin15/16 认不到主人，「J7n 的 GND 脚整批跳过」就漏掉两个。 -- **第三遍「并到旁边的同网络焊盘」没有长度上限、也不查走线/钻孔**，实测把 C745 pin2 - 一路并到 **9.78 mm** 外的 J64 pin3（而且那是另一层的焊盘，画出来根本不通）。 - 现在 `LINK_MAX = 3.0`，并且要求目标是通孔焊盘或同层。 -- **`pcb2_vo_vias.py` 的出线层写死 `L_TOP`**。v1 时代器件全在顶层没事；v2 之后 VOn_P 的 35 个焊盘 - **全在底层**，照旧会画出 35 条悬在顶层、一头不搭焊盘的线 —— 而且 `fits()` 拿这个 lay 去筛障碍， - 连净距校核都是照着空荡荡的顶层算的，一条都不会报。 - -#### 两处和上一轮的计划不一样（都是实算之后改的） - -- **U32 pin13 的孔位没有钉在 (94.6, 71.4)。** 那个位置过孔放得下（西边走廊 x ∈ [94.59, 94.625]）， - 但**引线出不去**：pin13 与 pin14 之间只有 0.20 mm，斜着往西北一定切进 pin14 的净距圈； - 平着往西的话过孔又躲不开 `USB5_DP` 的横段（y 69.75，只差 0.5 < 0.64）。 - 正解是往**东**打进 QFN 肚子里 —— 引脚环东沿 95.975 到散热盘西沿 97.600 有 1.625 mm 净宽， - 自动搜索把 pin13 放在 (96.50, 70.25)、pin19 放在 (97.25, 71.50)，离差分车道都在 2 mm 以上。 -- **J7n 的 65 个 GND 脚整批不扇了**（`SKIP_PAD`）。它们是 `bm24_pre()` 手写死的两条梳子 + pin52 单独出线； - 让自动扇出去碰的后果实测是「十个必然失败 + pin 1/2/52 三个『成功』的孔正好落在梳子和车道上」， - route_sig 还得写个删除框把它们收回去。 - -#### 一处对设计文档 §10.3 的有意偏离 - -§10.3 写的是「功率网络每个焊盘打 3 个过孔」。这一轮 `VOn_P` 只给 -**`J8n.1`（这一路 4 A 的唯一去路）和 `C8n1.1`（2200 µF 主储能）各 3 个**， -`C8n2`~`C8n6` 仍是各 1 个 —— 全按 3 个来会往五块岛里再钻 50 个反焊盘， -最窄断面（下限 7.0）扛不住。这五颗只承担高频纹波，单孔 1~1.5 A 够用。 - -### 上一轮（2026-09-06 第十一轮）：v5 差分布线全部落地 - -**详见设计文档 §25.16 补 6。** 走法表、顶层参考面、45° 斜段规矩都在那里，这里只记做了什么和踩了什么。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `pcb2_dp_long.py` 整个重写（v3 存 `obsolete/`）：pair 1 直西、pair 2 正北、pair 3 绕 Hub 北边东行、**pair 4 整段顶层**、pair 5 绕北边再南下跨 UP、UP 底层直东 | 本地净距全过 | -| 2 | `SITE_J` 按 v5 站内坐标重写：DMJ 底层 45° 斜进、**DPJ 翻顶层**跳过去（两排之间只有 1.515 mm，孔只能落在 y 36.805~37.31）| 五站同构 | -| 3 | pin5 / pin10 两条 +3V3 车道 + 顶层干线一起画（被 D± 夹住，后面的布线器进不去）；C747 → (88.2, 71.5)、C748 → (92.5, 71.2) | `pcb2_place --push`、`pcb2_clear` 过 | -| 4 | VO4 岛主体东界 89 → 87（顶层段不许跨岛边）；`topref` 检查 0 处跨界 | reload → pour → `inner1_verify` 五块全 ✅ | -| 5 | `--push`：182 线 / 26 孔；DRC 634 = 间距 115（基线）+ 连接性 519 | 无新增间距错误 | - -#### ⚠️ 这一轮踩到的 - -- **0.5 脚距的车道之间打不了孔**（孔要离两边车道各 0.645）。出 QFN 的次序只能是「最外侧先拐走，邻居走了才打孔」， - pair 4 的两个孔为此上下错 0.9、DP4 先抬 0.6 再打。想改走法先在纸上按这条排一遍。 -- **`chamfer()` 不能对 45° 拐再切一刀**：切出来的 22.5° 小段向内挪 0.1，实测把 DP4 抬升段切进 pin10 车道净距圈。已改成转向角 ≤ 46° 不切。 -- 上一版脚本里的 U32 坐标（x 105.55）是 v1 的，U32 早搬到 (100, 68) 了 —— 改布局后**所有写死坐标的布线脚本都要重推**，别只改一处。 -- 同宽共线的两段下发后被 EDA 合并成一条（182 → 178），但**不同宽**的共线段（BM24 出线 0.11 / 0.20 / 0.28 三档）保留 —— 换挡点安全。 - -### ✅ 这一轮（2026-09-06 第八轮）：载板 v4 —— 尾插槽到 J1401 正下方，J7n 到主板下方远处 - -**详见设计文档 §25.16「2026-09-06 补 3」。** 用户指令：尾插槽放在主板尾插接口下方；载板尾插座放在主板下方远处、50 mm 排线能到的地方；连接时排线走载板背面。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `SLOTS['tail']` → u 45~65 / v 1.4~4.4（J1401 正下方）；`TAIL_LANE` u 44.6~62.6 / v 4.4~38.3 不放元件（`check()` 新增一条）| 本地检查过 | -| 2 | J7n → (53.5, 37.0) **rot 0**；U5n (49.8, 41.5, rot 180) / R76n (52.8, 39.15) / R77n (55.8, 39.15) 挪到 J7n 北边；J6n (62.5, 41)；行 D 西移 4.5 | 离 H1 4.0 / H3 2.9，`pcb2_clear` 816 焊盘净距 ≥ 0.20 | -| 3 | `--outline --push --verify --heights` | 槽 10/10；J71 回读 pin51(VBUS) 西端 (52.47)、pin4/6 北排西端 (54.65/55.0, 121.06)、奇数排南 ✔ | -| 4 | `pcb2_reload` → `pcb2_pour --push` → `_refresh_geo` → `inner1_verify` | 五块岛各 1 连通域、焊盘全在主域，最窄 7.05 / 7.20 / 7.70 / 7.60 / 20.85（下限 7.0）| -| 5 | 截图 `PCB2-v4-bottom.png` / `PCB2-v4-ch1.png` | 自己看过：槽在 J1401 下、J7n 在远端、U5n 在北 —— **还要用户确认** | - -#### 为什么 J7n 从 rot 180 改成 rot 0（不是拍脑袋） - -排线只绕 u 轴弯（接口边一个 U 形回折 + 槽里一个台阶），不在面内转 ⇒ J7n 的触点图案是 J1401 图案的**平移**； -J1401 的 pin1/2 端（G1）在 +u ⇒ J7n 的 pin1/2 端要在 −u；封装 pin51 在本地 −X、底层翻层不改 x ⇒ rot 0。 -v3b 的 rot 180 把 VBUS 端放到了东边，和 §24.3「VBUS 落到 −X 端」矛盾。翻面次数（回折 1 次、台阶 0 次）算出来公头朝 +z，正好插朝 −z 的 J7n。 -剩下唯一没定的是封装奇/偶排分配（§24.3 镜像位），错了只改焊盘编号，D± 换到南排西端。 - -### 上一轮（2026-09-06 第七轮）：载板 v3 + C8n1 换矮封装（槽位置已被 v4 取代） - -**详见设计文档 §25.16 末尾「2026-09-06 补」。** - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | 槽挪到主板远端边（v 45.5~48.5），手机位内移 2.5，器件全部收进主板下方 | 本地检查 / 净距 / 镜像回读全过 | -| 2 | `pcb2_pour.py` ISLANDS v3：走廊主体 + 主板下方整条带，VO2/VO4 为顶层差分收边 | `inner1_check` / `inner1_verify` 五块全 ✅（最窄 7.05）| -| 3 | C8n1 → Rubycon 6.3TPV2200M10X10.5（C3828985）：个人库建器件、`c4_site.py` 五页重画、PCB 导入 80+80 | 极性丝印核过（`PCB2-v3-c801.png`）| -| 4 | 为差分让位挪 C747/C748、U31 组、U34/C760、R721/722、R717/718 | 见 `pcb2_place.py` 注释 | -| 5 | 新工具 `pcb2_reload.py`（重载客户端解卡）、`pcb2_snapshot.py` | | - -#### ⚠️ 这一轮踩到的 - -- **`lib_Device.create()` 返回 undefined 但器件已建出来**；`copy()` 从系统库复制返回 null 且真没建； - 个人库内 `copy()` 可用；给个人库器件 `modify(association.footprint = 系统库封装)` 会把封装**复制进个人库**（新 uuid）。 - 建完一律 `search` + `get` 核对，别看返回值（skill §9y）。 -- **铺铜「重建所有」在大量 API 改动之后必卡**（本轮三次），重载后一次就通 ⇒ `pcb2_reload.py` 然后 `--push`。 -- `pcb2_place.py --push` 的 `modify()` 里 layer 和 x/y/rot 分两次下发（一次下发 rot 偶发不生效）。 - -### 上一轮（2026-09-06 第六轮）：载板 v2 —— 全部到底层 + 穿线槽（已被 v3 部分取代） - - - -**详见设计文档 §25.16。** 用户两条指令：正面器件全放背面并在背面重新布局；排线通过板内细长槽穿到载板。 -中途补充：器件可以放到主板投影下方（底层），方便布线。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `pcb2_snapshot.py`：先把 v1 全部铜/元件抓成 `_pcb2_snap_topside.json` | 161 件 / 1586 线 / 416 孔 / 7 铺铜，可回滚 | -| 2 | 实测底层镜像语义（U51/J71/R761 翻到底层读焊盘再翻回来） | 本地 y 翻 → 再转 rot；两脚件 pin1 方向不变，SOT23/BM24 南北排对调 | -| 3 | `pcb2_place.py` 重写成 v2 | 顶层 20 / 底层 141；槽 10 条；C8n1 卧倒 keep-out；新增「压槽 / 螺钉头 / 顶层只许顶针」三项检查 | -| 4 | `--clean-copper --outline --mech --push --verify --heights` | 清 1416 线 + 416 孔 + 7 铺铜（另有 16 条漏网线第二遍才删掉）；槽建 10/10；镜像回读全 ✔ | -| 5 | `pcb2_clear.py` | 跨元件净距全部 ≥ 0.20 | -| 6 | `pcb2-bottom-heights.json` | 底层 141 件高度图 + 10 条槽，给下板布局避让 | - -#### ⚠️ 这一轮踩到的三条（都写进 skill） - -- **底层元件的焊盘位置不能推**：翻层不是绕 y 轴镜像，是本地 y 翻。J23 用顶层那版的 rot 90 放到底层， - 口会朝板内；改 rot 270 并把 R717/R718 的 y 对调，`--verify` 回读核过。 -- **挖槽区域 = `pcb_PrimitiveFill.create(12, polygon)`**（layer 12 = MULTI）。跑道形用两段 90° 弧， - 和板框一样逆时针、正角度。 -- **批量 `delete()` 一遍删不干净**：1416 条按 `getAll()` 删完，回读还剩 16 条（旧 BM24 GND 梳子， - 正好压在新槽上）。删除循环要跑到剩余为 0 再收。 - -### 上一轮（2026-09-06 第五轮）：载板收尾 —— **已被 v2 整体作废，只留作历史** - - - -**详见设计文档 §25.15。** - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | `.claude/pcb2_vo_vias.py`：25 个贴片电容各打一个过孔下到 Inner1 的岛 | 25 线 / 25 孔，**全部一段直线**，连接性 −31 | -| 2 | `.claude/pcb2_gnd_patch.py`：自己算出悬空的 GND 连通域再补孔 | 5 个域（`C749.2`/`R710.2`/`U32.19`/`J23.A1B12`/`J23.B1A12`）→ 6 线 / 5 孔，连接性 −10 | -| 3 | `.claude/pcb2_npth.py`：从铺铜反焊盘反解**封装自带的非金属化孔** | J23 里两个 **Ø0.600 @ (213.660, 59.100) / (213.660, 64.900)** | -| 4 | `inner1_verify.py` 加了**过孔**校核 | 五块岛 **5 焊盘 + 5 过孔全在主域**，最窄断面 7.20/9.10/10.15/7.35/7.60（下限 7.0）| -| 5 | `pcb2_gnd_patch.py --check` | 板上悬空 GND 连通域 **0 个** | -| 6 | DRC | **125** = 同封装内 115（与基线一模一样）+ 连接性 10 + 间距 0 + 物理 0 | - -#### ⚠️⚠️ 这一轮最值得记住的：**封装自带的孔，API 一个都读不出来** - -J23 的封装里有两个 Ø0.60 非金属化定位孔，正卡在 `A1B12`/`B1A12` 两个 GND 焊盘的外侧角上。 -`pcb_PrimitivePad.getAll()` 里没有、`pcb_PrimitiveRegion`/`pcb_PrimitiveFill` 是空的、 -`getPrimitiveByPrimitiveId('e55')` 返回空、`getPrimitiveAtPoint()` 只回最上面那条线。 -**只有 DRC（「挖槽区域 到 导线」）和内层铺铜的反焊盘看得见它们。** -⇒ `pcb2_npth.py` 拟合铺铜环里的圆弧，用「已知过孔的反焊盘半径 − 过孔半径」标定净距 -（实测 0.3583，234 个样本，离散度 0.005），再反推孔径。 - -#### 另外三条 - -- **净距校核只看铜，钻孔是另一条规则。** 第一版打的孔落在同网 `J23_4` 的**焊盘里**， - 校核全过，DRC 报「钻孔 到 钻孔 距离 0mil」。同网的通孔焊盘/过孔都要按 `DRILL=0.33` 再判一遍。 -- **金属化的槽孔焊盘和非金属化孔待遇完全不同**：线可以压在焊盘自己的孔上， - 不能压在非金属化孔上。混在一起判的话，`J23.1`/`J23.4` 这种槽孔焊盘**连碰都碰不得** - （焊盘上任何一点离自己的槽都不足 0.80 mm）。 -- **只加不删的下发必须记账。** `pcb2_gnd_patch` 把自己画的坐标存 `_pcb2_gnd_patch.json`， - 下次先删再画。不记账实测多出一对旧坐标的过孔，而且新画的细线被 EasyEDA 并进旧的粗线里。 - -### ✅ 这一轮（2026-09-06 第四轮）：栅格迷宫布线器，载板剩下的 77 个网络 - -**详见设计文档 §25.14。** 事实来源是 `.claude/pcb2_route_sig.py`（BM24 周围的车道 -是手写死的几何，其余交给布线器）。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | 新写布线器 `pcb2_route_sig.py` | 栅格 0.1/0.05/0.025 三档 + scipy 稀疏图 Dijkstra + 45° 整形；**产出过同一份 `check()`** | -| 2 | 77 个网络 | 431 条路径 / **991 段导线** / **160 个过孔**，净距校核全过 | -| 3 | BM24 的 65 个 GND 脚（§25.8 的待办）| 两条梳子 + 12 个过孔/站，**中央通道那 1.64 mm 是这一轮才用上的** | -| 4 | 抓到并修掉 `R76n` 装反 | rot 0 → **180**。不改的话五个站的 `VBUSn` 全布不通 | -| 5 | `+5V` 线宽 0.80 → **0.60** | §25.10 说了段电流 ≤0.6 A；0.80 在走廊里挤不过去 | -| 6 | `PWR1A` 的 `strokeWidthMin` 0.25 → **0.15** | `+3V3_HUB` 要穿 Hub 卫星圈 0.659 mm 的缝；载流够（420 mA / 0.15 mm 可载 ~0.8 A）| -| 7 | 布完线重新铺铜 | 不铺的话 DRC 多出 **445 条**「铺铜区域到过孔/钻孔」（新过孔没有反焊盘）| -| 8 | DRC | **166** = 同封装内 115（**与 §25.8 基线一模一样**）+ 连接性 51 + 间距 0 + 物理 0 | -| 9 | **45° 化**（用户拍板）| `sharp_corners` / `chamfer45` / `smooth_micro` 三个工具放在 `pcb2_route_dp.py`，两个脚本共用。差分对 10 → 0、信号线 72 → 0，**DRC 不变** | - -#### ⚠️⚠️ 这一轮最值得记住的一条：**`expand()` 会静默丢掉路径末端的过孔** - -`pcb2_route_dp.expand()` 打过孔的条件里有 `i + 1 < n - 1` —— **最后一个点被显式跳过**。 -于是「走到目标正上方再换层落下去」这种路径，过孔没了，两层的铜各画各的、中间断开。 - -**三道校核全都抓不到**：净距校核只看撞没撞（断开当然不撞）、 -`inner1_verify` 只看铜面、DRC 的连接性又要 `location.reload()` 才刷新。 - -踩到两次：布线器自己的路径断了 5 个网络；**手写的 `bm24_pre()` 断了 50 个 GND 过孔** -（DRC 里 GND 55 条，补上之后掉到 10）。 -⇒ `_end_via()`：末点上有换层就补一个重复点，**所有**路径（含手写的）都要过这一道。 - -#### 另外三条（都写在 §25.14 里） - -- **障碍要先胀 `QERR` 再栅格化**，否则距离场高估 0.08 mm，净距校核在下发前一刻才炸。 -- **`location.reload()` 会被「离开该页面」确认框挡下来**（文档有未保存改动）， - 点「留在该页面」= 根本没重载，客户端仍卡在后台任务上， - 于是 `铺铜管理器…` 点了没反应。**重载前先 `save()`。** -- **先给所有焊盘留好出线段再开始布线**（escape routing 先行）， - 否则先布的网络会把后布的网络出焊盘那 0.6 mm 占掉。 - -### ✅ 这一轮（2026-09-06）：载板 Inner1 分割电源面 - -**详见设计文档 §25.11。** 事实来源是 `.claude/pcb2_pour.py` 的 `ISLANDS`，改铜面改那里再 `--push`。 - -| # | 做了什么 | 结果 | -|---|---|---| -| 1 | 五块 `VOn_P` 岛 + GND 底填落到 Inner1 | 优先级 L15 `VO1= 0.2 mm ✔ 814 个焊盘 - pcb2_clear.py 同封装内负间距 ✔ 0 对 - 铜层数 ✔ 2 -> 4（id 1/15/16/2） - -截图 `PCB2-carrier-v2.png`。 - -### 上一轮（2026-09-04 晚）做完的两件 - -1. ✅ **顶针占位型号换掉了**：`C9900001338` → **YTC1P-2510-01（立创 C5221288）**， - 配 **3.0 mm 立柱**（原来文档写的 2.0 mm **买不到**，见 §22.3e 的整族对照表）。 - `c4_site.py` 已改，C4-SITE1~5 五页重生成，六项验证 + 跨页对账 + port_audit 全过。 -2. ✅ **C1-CONN 抓到并修好一处真断线**：GND 旗写在 y=362，旗被吸附到 360、导线端点留在 362， - 旗压在导线中段 → **J31 pin1 的地是断的**。`verify_sch` / DRC / 跨页对账全过， - 只有 `port_audit.py` 抓得到。已在 `c1_conn.py` / `c4_site.py` 加「坐标必须是 5 的倍数」断言， - 成因写回 skill §8a-2b。⚠️ **上一轮记的「可疑 0」不能当数，每轮都要重跑。** - -### 上一轮（2026-09-04 深夜）：USB 定为方案 D，载板改造已完成 - -**方案 D**（设计文档 §13.5）：手机 J1401 ──原厂「主板→尾插」排线── -载板上一颗同型号 BM24-50DS 座 ──> 载板上的 USB 电路。 -用户拍板：天线自己另买插主板上，麦克风 / 震动马达不要，「只要能开机正常运行系统就行」。 - -**载板改造做完了，三道验证全绿**（verify_sch 每页 PASS / xpage 0 漏接 / -port_audit 载板 330 个可疑 0、下板 513 个可疑 0）： - -| 页 | 改了什么 | 脚本 | -|---|---|---| -| **C5-J1401A / B**（新）| 五颗 **J71~J75** BM24-50DS 座（`C424561`），A 放 CH1~3、B 放 CH4~5 | `.claude/c5_j1401.py` | -| **C5-AUX**（新）| 每路 **U5n** USBLC6 ESD + **R76n** 56k(CC1→VBUS) + **R77n** 100k(口温→GND) | `.claude/c5_aux.py` | -| **C3-USB**（改）| **删掉 J17~J21** 五个 1.25mm 出线座；D± 不再经过这一页，只留 VBUS 负载开关 | `.claude/c3_usb.py` | - -USB 链路现在是：`C2-HUB 的 U32 → C5-AUX 的 U5n → C5-J1401 的 J7n → 原厂排线 → 手机 J1401`。 -NC 清单 `.claude/c5-nets-nc.json`（每颗座子 34 个悬空脚，含必须悬空的 CC2）。 -截图：`C3-USB.png` / `C5-J1401A.png` / `C5-AUX.png`，都看过。 - -**调试串口（pin24 TX / pin29 RX）故意没引**：1.8V 电平接 ESP32 要加电平转换， -且 pin29 夹在两个地脚中间会把排版挤垮。要用是一次改板。 - -### 上一轮（2026-09-04 深夜）：Board3 画完又作废 —— USB 方案改回 A（后又改成 D） - -先按方案 C 画完了 Board3（J1401 转接小板），当晚用户确认「用排线连接」之后 -**改回方案 A：装原厂尾插小板 + 一根改端子的 USB-A 转 C 线**。 -Board3 / `phonerail-usbtap` / `PCB3-USBTAP` 已从工程删除， -生成脚本挪到 `.claude/obsolete/t1_usbtap.py`。理由对照表见设计文档 **§13.5**。 - -方案 A 当时是最优的，但用户随后提出「直接用原厂排线连主板和载板」—— -那就是方案 D，比 A 更紧凑、电路全在载板上好改。**方案 A 已作废**， -它唯一的优势（保留天线馈点）被「用户自己另买天线」抵消了。 - -作废但仍有效的四条结论留在 **§23**：立创 BM24 封装编号是错的（同时佐证了 §13.4 的引脚表）、 -BM24 只有 10 次插拔寿命、Rp/Rd 分压核算、以及两条 EasyEDA API 经验（skill §8b / §8c）。 - -### 上一轮（2026-09-04 深夜）：BM24-50DS 封装自建完成 - -**下一步四件里的第 2 件做完了。** 器件在个人库：`BM24-50DS/2-0.35V(51) HRS-PIN` -（`771dbf002b714bb79cde47cf86aa0fb1`，封装 `940f093c1578426aa81e91ebf0bfbd76`）， -`c5_j1401.py` 已改用它，C5-J1401A/B 重生成，**三道验证全绿** -（verify_sch 两页 PASS / xpage 0 漏接 / port_audit 载板 330 个可疑 0）。 -生成脚本 `.claude/fp_bm24.py`，封装截图 `FP-BM24.png`。逐项尺寸与来源写在设计文档 **§24**。 - -几何**不是外推、也不是抄立创**：从 Hirose 官方样本（D47680_en）的 PDF 矢量图里 -逐段反算的，50 芯的 A/B/C 表直接可用。信号焊盘 0.18 × 0.48 @ 0.35 间距、两排 y = ±1.06、 -电源焊盘 0.49 × 0.76 @ x = ±6.03。 - -#### ⚠️⚠️ 但是多出一件必须做的事：**镜像位实测**（§24.3） - -原来文档里写「两种候选正好差一个 180° 旋转，转贴片方向就能切换」——**这句是错的**， -候选有 **4 个**：2（1 脚在哪一端）× 2（**奇数脚在哪一排**）。 -前一位靠旋转能纠，后一位是**镜像，错了要重打载板**（D+ 会落到 45 脚 `SPKR_OUT_P`）。 - -BM24 的 DS 座是**完全对称件**（Hirose 样本注 2：*no polarity*，本体两端与上下两排全一样）， -所以「哪一排是奇数排」查图纸查不到 —— 它是**小米8 那块板的布局事实**，只能量。 - -**量法（两个探点，零成本零风险，打样前必做）**： -1. 两个电源触点（焊盘大好戳）分别对主板地量电阻，~0 Ω 的是 **G1 = 1/2 脚那一端**。 -2. 从 G1 端数，两排各自的**第 2 个信号触点**对地量：通的那排是奇数排（pin3 = GND； - 偶数排第 2 个是 pin4 = `VREG_L19A_3P0`，不通）。 - -结果若是「奇数排在 −Y」，把 `fp_bm24.py` 的 `ODD_ROW_TOP` 改成 `False` 重跑一遍即可。 - -### 上一轮（2026-09-04 深夜）：载板 PCB 从零布起 - -**板框 220 × 135（R5 圆角）**，五块主板 **3+2 双排面对面、第二排居中**（用户拍板）。 -原理图 161 个元件全部导入并摆好，本地四项检查全过（位号齐全 / 不越框 / 分层重叠 / 顶层不压主板投影）。 -逐项见设计文档 **§25**，脚本 `.claude/pcb2_place.py`，截图 -`PCB2-carrier-v1.png`（全板）/ `PCB2-site1.png`（CH1 位）/ `PCB2-j23.png`。 - -已落盘的东西：板框 1 条闭合多段线、载板自己 4 个 M3、**35 个手机定位孔（NPTH Φ2.5）**、 -5 个手机位丝印外框 + 标签、161 个元件（顶层 133 / 底层 28）。 - -#### ⚠️ 抓到一个会让侧键永久短路的封装错误（§25.3） - -立创给顶针 `C5221288` 的封装焊盘是 **Ø2.5**，而小米8 四个侧键触点最近的一对 -（J601↔J604）只隔 **2.217 mm** —— 两个焊盘直接叠在一起，音量+ 会被永久按住。 -顶针法兰其实只有 Ø2.0，是立创把焊盘开大了。**原理图侧完全看不出来**。 - -已自建 `POGO-SMD1P_D1.9`（焊盘 Ø1.9，净间距 0.317 mm），`c4_site.py` 改用新器件， -C4-SITE1~5 重生成、三道验证全绿、PCB 重新导入。 - -#### 三条布局上的硬决定 - -1. **J31/J32 排母在底层**（下板公头朝上，载板母座必须朝下）。 - 「第 r 行对第 r 行」不靠脑补：`--push` 会把载板侧 80 个焊盘坐标导出到 - `.claude/pcb2-header-pads.json`，下板照数值摆即可（下板目标 = 导出值 − (30,5)）。 -2. **USB Hub 也在底层、压在通道正中 (110,67)** —— 放左右口袋的话最远那台 D± 要走 - 200+ mm，超 USB2517I 手册的 152 mm 上限；放中间后最长 92 mm。 - ⚠️ 布下板时别让 C2/C3（12 mm 电解）撞上载板底面的元件。 -3. **35 个定位孔做 NPTH，立柱必须用尼龙** —— 金属化 + 金属立柱 = 五台手机的地 - 在载板上并成一根，4 A 回流会绕开专用 `P−` 针，违反 §6.4。 - -#### 载板这一版还欠的（详见 §25.5） - -✅ J23 已定稿（rot=270、x=5.134，壳体前端面与板边齐平）· ⬜ Hub 那 26 个件是网格粗排、布线前要手调 -· ⬜ 设计规则 / 铺铜 / 布线一根没做 · ⬜ 主板 7 个定位孔的孔径没量 - -### 上一轮写的「下一步四件」（第 1/2/5 件已完成，剩下的搬到文首） - -| # | 做什么 | 备注 | -|---|---|---| -| 1 | ✅ **排母选型 + 换件实施全部完成**（2026-09-05 夜，见文首）| -| 2 | ✅ **自建 BM24-50DS 封装 + 镜像位实测**（§24.3）—— 全部完成，结论是当前的 `ODD_ROW_TOP = True` 就对 | -| 3 | **下板 PCB 导入变更** | 删了 15 个连接器 + 53 个 7xx 器件，新增 J24~J30 / U33，接口区要重排，最后统一重铺铜。⚠️ 下板的铜面 2026-09-05 被误重铺过一次（无损失，本来就要重做）| -| 4 | 🟡 **载板 PCB** —— 摆位 + 规则 + 差分对 + Inner2 地平面 + 6 个 M3 + GND 扇出 + 换件重摆/重扇/重铺 + **Inner1 分割电源面**都已完成。⬜ 只剩 **布线** | -| 5 | ✅ **载板上半部分的安装点** —— 已加两个中跨 M3 (76.6, 80.1) / (148.1, 80.1)，§25.7 ③ | - -改完照例：`verify_sch.py`（当前页）+ 跨页对账 + `port_audit.py` -（载板加 `--board Board2`），三个都干净了再让用户看截图。 -**动 PCB 的话再加一条 `pcb2_clear.py`**（焊盘级净间距，自由焊盘只有它管）。 - -#### 载板布线的下一步，按顺序 - -1. ✅ **换设计规则** —— `.claude/pcb2_rules.py --push`，`--check` 十一项全过（§25.7 ①）。 -2. ✅ **建差分对** —— **11 对**（5 长 + 5 短 `*J` + UPSTREAM），短段也建了对。 -3. ✅ **Inner2 整板 GND** —— 一块 `GND-INNER2`，81 块填充，已存盘（`.claude/pcb2_pour.py --push`）。 -4. ✅ **GND 扇出** —— `.claude/pcb2_fanout.py`，换件后已 clean → dump → push 重来一遍， - **210 个过孔**。J31/J32 那 33 个 GND 脚**不再需要扇出**（通孔件自己就是过孔， - `one_net()` 的 `todo` 带 `not p['hole']`）。 - ⬜ 只剩五颗 BM24 的 51 个 GND 脚（**过孔塞不进 0.35 间距，只能逃逸布线**，§25.8）。 -5. ✅ **Inner1 分割电源面** —— **2026-09-06 铺完**（五块 `VOn_P` 岛 + GND 底填， - §25.11 / `pcb2_pour.py` 的 `ISLANDS`）。三个校核脚本全过： - `inner1_check.py`（下发前预测）/ `inner1_verify.py`（下发后实测，最窄颈 7.20 mm）/ - `inner1_diffref.py`（§10.1 参考面）。 - ⇒ `+5V` / `+3V3_HUB` / `VOn_P` 的扇出现在可以做了（之前扇过去全是悬空过孔）。 -6. 🟡 **布线** —— 先 D±（长的先走），再电源，最后杂散信号。 - ⚠️ **BM24 的逃逸布线单独排一项**：前排往南、后排往北，同排横向穿不过去（净距 0.17 mm）。 - -#### Inner1 分割电源面的规划（⚠️ 这是 09-05 的规划稿；**落地结果与实测见设计文档 §25.11**） - -**层角色**：Inner1 = 电源面（分割），Inner2 = 完整地平面（§25.6 ①，和下板是镜像的）。 - -**只做三类岛，其余全部 GND 底填**（不是原来写的「+5V / +3V3_HUB / VO1~5_P / VBUS1~5」 -十二块）——理由是内层是 0.5 oz，按 IPC-2221 内层算 4 A 要 **6.97 mm** 净宽、 -2.8 A 要 **4.3 mm**，而两排手机之间的走廊（y 49.66~85.5）只有 35.8 mm 高： - -| 岛 | 网络 | 为什么要 | 最小颈宽 | -|---|---|---|---| -| 5 块 | `VO1_P`~`VO5_P` | 每路 4 A，这是上四层的头号理由 | ≥7.0 mm | -| 底填 | `GND` | 剩余全部，**优先级数字给最大** | — | - -> ⚠️ **2026-09-05 夜简化：`+5V` 和 `+3V3_HUB` 两块岛取消了**（§25.10）。 -> 排母逐针分配按几何重排之后，`+5V` 从 3 针变成 **10 针、分散在两颗排母的南北四处**， -> 每个入口只喂本站的 `U2n` + `C70n`、段电流 ≤0.6 A ⇒ **顶层 0.5~0.8 mm 走线就够**， -> 内层不用给它留地方。`+3V3_HUB`（420 mA、局部）同理。 -> ⇒ Inner1 只剩「**五块 `VOn_P` + GND 底填**」，五路 4 A 各走各的，互不挤。 - - -**`VBUS1~5` 不做岛**：每口 0.5 A、走线只在本服务带内约 18 mm，`PWR1A`(0.6 mm) 走线足够。 -额外好处：顶层那 5 段 `*J` 差分（U5n→J7n，5 mm）下方的 Inner1 就是**完整的 GND 底填**， -参考面比分割的电源面干净得多（§25.7 ① 那条警告因此自动消解）。 - -**走廊里已知的障碍**（Inner1 只怕直插焊盘，不怕表贴件）： -`C801/C811/C821` 三个 Ø12.5 电解在 y 68.25~80.75，`C831/C841` 在 y 54.41~66.91， -两个新中跨 M3 的 Ø6 焊盘在 (76.6, 80.1) / (148.1, 80.1)， -外加 J31/J32 的 **80 个通孔焊盘**（坐标已定稿：J31 x 37.869~86.129 / J32 x 133.869~182.129， -两行 y = 66.23 / 68.77，见 `pcb2-header-pads.json`）。 -⚠️ 2.54 间距的通孔在内层会把铜面打成筛子（Ø1.7 焊盘 + 0.2 净距 ⇒ 相邻反焊盘之间只剩 0.44 mm 网）， -电源岛的颈宽要绕开这两条带，别指望从排母底下横穿过去。 - -### 还欠用户的五件事 - -0. ~~BM24 的镜像位实测~~ → ✅ **2026-09-05 已完成，结论「不用改」**（§24.3）。 - 可选的零成本复核（还没做）：奇数排上从 G1 端数，位置 17-18-19 与 22-23-24 各自三连导通 - （`SPKR_OUT_N` 33/35/37 和 `SPKR_OUT_P` 43/45/47），偶数排没有这种三连。 -0b. ~~量排线两个公头之间的距离~~ → ✅ 用户拍板不管，装配时折叠（余量约 80 mm，会占手机上方高度）。 -1. **h_up**：主板**正面**（朝上那面）最高元件高出板面多少。只影响压板高度与整机层高。 -2. ✅ **排针/排母选型已定**（§22.3f）：`C55020601` + `C5307344`，对插 13.0 mm。顶针已定稿。 - ⬜ **到货要核两件**：母座触头镀层（商城只写了「黄铜」，没写镀层）、 - 对插后实测板间距是否真的 13.0 mm（确认是塑料贴合、不是针先顶死）。 -2b. **首件上电前量一次**：`VBUSn` 对 GND 的电阻（确认电源触点 G1/G2 没接反，§13.5）。 - 负载开关默认关断，所以这一步零风险、零成本。 -3. **顶针首件必验**：±1 mm 公差链对 1.2~2.2 mm 的侧键触点是危险的，而且 - **选定的顶针冠径只有 Ø0.9 球头、又是贴片不可调**，所以首件实测是**唯一**对策（§22.3c）。 -4. **用卡尺重量那 7 个定位孔**：±1 mm 里有 ±0.5 来自「孔位是从照片提的」， - 量一遍能直接砍掉一半误差 —— 这是眼下性价比最高的一项。 - ---- - -## 这一轮做了什么（2026-09-04 傍晚，载板画完） - -### 载板 8 页 - -`C1-CONN`（排母 J31/J32 + U31 5V→3.3V + U34 LM75BD 温度芯片 0x48）、 -`C2-HUB`、`C3-USB`、`C4-SITE1~5`（每台手机一页：P+/P− 焊盘 + §6.3 电容组 + -4 根侧键顶针 + EDL 座/模拟开关/下拉/去耦）。逐页内容与位号见 §22.7。 - -**手机位一台一页**，和下板「一路一页」保持同一结构；五页由 `.claude/c4_site.py` -同一段代码生成，改一处五页一起变。 - -### 这一轮自己发现并补上的两个洞 - -1. **`UP_VBUS_DET` 在载板上没有源头。** §22.2 给它留了一根排针，但 J23 的 VBUS 是 5V， - 排针那头是 3.3V 域的 IO44。在 C2-HUB 上补了 **R721 10k / R722 20k 分压**（3.33V）。 -2. **载板上原来没有 3.3V。** 排针只送 +5V，而 Hub、温度芯片、五颗 EDL 开关都要 3.3V。 - U31 从下板搬过来后画在 **C1-CONN**（+5V 进来的那一页）；§9.5 要求的「就近 Hub 供电」 - 是 PCB 摆位约束，与分页无关，已在文档里说清楚。 - -### 两个明知不对、故意先放着的占位型号（⚠️ 顶针那条已于当晚解决，见文首） - -| 占位 | 差在哪 | -|---|---| -| ~~顶针 `C9900001338`~~ ✅已换 | 自由高 **9.0 mm**，§22.3e 要的是工作高 2.0 / 自由高 3.0~3.5 / 冠径 Ø1.5~2 | -| 排母 `C9900025309` | 高度没按 13 mm 净空选；而且编号体系和公头不同（§22.2 有对照表）| - -放占位是为了让网表先连通、能跑完整验证；**两个都在 §22.7 里单列了一节，打样前必换。** - -### ⚠ 一个必须记住的编号陷阱 - -下板公头（DIP 式）第 r 行 = 引脚 r / 41−r；载板母座（IDC 奇偶式）第 r 行 = 引脚 2r−1 / 2r。 -**只能按行对，不能按引脚号对**（`VO1_P` 在下板是 1/2/3 脚，在载板是 1/3/5 脚）。 -原理图这边不会错 —— `c1_conn.py` 直接 import `p5_btb.py` 的行表，两边同一个事实来源。 -**风险在 PCB**：焊盘编号 + 摆放镜像决定第 r 行会不会真对上第 r 行，布板时要实打实核一次。 - -### 新踩的两条 EDA 坑（已写进 skill §6c / §6d） - -1. **同一颗电解、同样 `create(270)`，在两个图页里 pin1 方向相反。** 方向表一张都别信， - 极性元件放完必须断言（`c4_site.py` 里断言「电解 pin1 的 y 必须大于 pin2」）。 -2. **红黑两个测试点的引脚偏移不一样**（−20 / −10），按名义值算线会画出斜线， - 而 `create()` 对斜线直接抛 `create failed!` 并让整批下发中途断掉。 - 现在下发前统一断言「横平竖直且非零长度」。 - ---- - - -## 状态一览 - -| 阶段 | 状态 | -|---|---| -| 方案设计 | ✅ 定稿 v1.6（`五路直供电源板设计.md`） | -| 小米8 侧接口引脚定义 | ✅ 已从原理图逐脚追踪（设计文档 §13） | -| 器件选型 | ✅ 全部立创有货，UUID 缓存在 `.claude/eda-parts.json` | -| **P1-INPUT** | ✅ **补完输入侧 INA226（U13+Rs6+C11，§19），六项验证全过，需重新看一眼** | -| **P2-CHANNEL（CH1）** | ✅ **已删 J2/J7，侧键漏极改挂 `POGO1_*` 端口**，六项全过 | -| **P2B-CH2 ~ P2E-CH5** | ✅ **同样删了 J3~J6 / J8~J11，改挂 `POGO2~5_*`**，各自六项全过 | -| **P3-CONTROL** | ✅ 画完，六项验证全过，**等用户看截图** | -| **P3B-EXPAND** | ✅ 画完，六项验证全过，**等用户看截图** | -| ~~P4-USB~~ | ➡️ **已整页搬到 Board2 载板，改名 C3-USB**；下板已删 | -| ~~P4B-HUB~~ | ➡️ **已整页搬到 Board2 载板，改名 C2-HUB**；下板已删。⬜ 还要在载板上补 U31 | -| **P1B-5V** | ✅ **已摘掉 U31 + C736/C737**（跟 Hub 一起上载板），现在是纯 12V→5V，9 元件，六项全过 | -| **P5-BTB**（原 P5-HARNESS）| ✅ **整页重画**：J24/J25 两条 2×20，47 信号 + 33 地，六项全过（截图 `P5-BTB.png`）| -| **P6-FAN-EDL** | ✅ **新建**：U33 第三片 595（EDL_EN1~5）+ 风扇低边驱动 + J26~J30，六项全过（截图 `P6-FAN-EDL.png`）| -| 跨页网络对账 | ✅ 下板 11 页 **0 漏接 / 0 待补**；✅ 载板 62 个网络 **0 漏接** | -| `port_audit.py` | ✅ 下板 513 个、载板 260 个，**可疑 0 个**（载板加 `--board Board2`）。⚠️ 2026-09-04 晚重跑时载板曾报 1 个（C1-CONN 的 GND 旗），已修 —— **每轮都要重跑，别信上一轮的数** | -| **Board2 载板原理图** | ✅ **8 页全部画完**：C1-CONN / C2-HUB / C3-USB / C4-SITE1~5，六项验证 + 跨页对账 + port_audit 全过 | -| **Board2 载板 PCB** | 🟡 4 层 / 220×135 板框 / 35 个定位孔 / **6 个 M3**（含 2 个中跨）/ 161 个元件已摆完（§25、§25.6、§25.7）；⬜ 未布线 | -| **Board2 载板 GND 扇出** | 🟡 **210 个过孔已落盘**（§25.8），脚本 `pcb2_fanout.py`；⬜ 差 J31/J32 的 33 个（等换件）+ BM24 的 51 个（要逃逸布线）| -| **Board2 载板 设计规则** | ✅ **整套已下发，`pcb2_rules.py --check` 十三项全过**（四层能力集 / PWR4A·PWR5V·PWR1A / 11 对差分 / USBPAIR 0.15 / 12 个网络指派 / **`PLANE-DIRECT` 铺铜全连接 + 5 个网络指派**）| -| **Board2 载板 铺铜** | ✅ **两层内层都铺完**：Inner2 整板 GND + **Inner1 五块 `VOn_P` 岛 + GND 底填**（§25.11）。脚本 `pcb2_pour.py`（`ISLANDS` 是事实来源，`--verify` 回读）+ 三个校核脚本 `inner1_check` / `inner1_verify` / `inner1_diffref` | -| **BM24-50DS 封装** | ✅ **自建完成**（§24），个人库器件 `771dbf00…`，几何来自 Hirose 官方样本。⬜ 镜像位待实测（§24.3）| -| **PCB 转板** | ⚠️ **已过期**：原理图这一轮删了 15 个连接器 + 53 个 7xx 器件、新增 J24~J30/U33，**还没导入变更** | -| PCB 板框 | ✅ **160 × 125 mm**，四角 R5 圆角 + 4 个 M3 金属化定位孔（接 GND）| -| PCB 布局 | 🟡 **第五遍：8 A 输入链整条重排（见下），等用户看 `PCB-layout-v5.png`** | -| 设计规则 | ✅ **整套已下发，`--check` 七项全 OK**（能力集 / PWR4A / PWR12V / 差分对 / 0.2 mm 间距 / 7 对 / 12 个指派）。上一轮说的「只能手动」是错的，见下 | -| **PCB 板框** | ⚠️ **改成一条闭合 polyline 了**（原来的 4 直线 + 4 圆弧自动布线器不认，见下）| -| 设计规则 | ✅ 等长容差 5 mm；新增 `USBPAIR` 0.15 mm，**只挂在每一对自己的两个网络之间** | -| 铺铜 | ✅ **19 块**（新增 `+5V` / `+3V3_HUB` / `+3V3`×2），三条低压轨的 91 个焊盘已扇出 | -| **7 对 USB 差分** | ✅ **6 / 7 布通**（USB1~5 + UPSTREAM）。⬜ 只剩 ESP32 调试口 `USB_DP/DM` | -| PCB 布线 | 🟡 **1208 过孔 / 5814 导线已落盘**（save 后重开验证过）。⚠️ 铺铜是旧填充、接口区马上要大改 —— **先别继续布** | -| Kelvin / 灌铜网络的漏网焊盘 | ⬜ **要手工布**：INA226 的 VIN±、五路泄放电阻 R*19、输入侧 U13 —— 5 mΩ 分流器满量程才 20 mV，多 1 mΩ 走线就是 20% 误差 | -| GND 漏网焊盘 | ⬜ 20 个（459 个扇出过孔之外的）| -| 丝印整理 | ⬜ 位号大面积压字，打样前要单独跑一遍 | -| **原理图 SCL 断线** | ✅ **U13 的 SCL 压在导线中段、根本没接上，已修**（设计文档 §19.4）。新增全工程扫描 `.claude/port_audit.py` | -| **板载 USB Hub 改造** | ✅ **原理图 + PCB 布局都做完了** | -| **两板架构（2026-09-04 拍板）** | ✅ 设计文档 §22 定稿；✅ **下板原理图改造已做完（§22.7）**；⬜ 载板 C1-CONN 未画 | -| **上板（载板）** | ✅ 原理图 8 页画完；⬜ PCB 还是空板；✅ 顶针已定稿 YTC1P-2510-01；⬜ 只剩排母占位（§22.7）| -| 散热 | ✅ 定稿 + **电路已画**（P6-FAN-EDL：Q6/D2/J26~J30 + TACH 分压）。⬜ 风扇型号未定（若选 4 线风扇，§22.6 那段 MOS+分压可整段删）| -| 小米8 主板机械数据 | ✅ **全部到手**：44.66×67.09 实测、7 个定位孔 ±0.5、触点 ±0.3（§22.3）。数据在 `.claude/mi8_mech.json` / `mi8_contacts.json` | -| **EDL(9008) 控制口** | ✅ **两侧都画完**：下板 U33（第三片 595）→ `EDL_EN1~5` → 排针 → 载板 U41~U45（TS5A3157DBVR）+ J61~J65（1.25mm 2P）+ R741~R745 下拉 | - -下板原理图 **11 页**（顺序已排）： -P1-INPUT / P1B-5V / P2-CHANNEL / P2B-CH2 / P2C-CH3 / P2D-CH4 / P2E-CH5 / -P3-CONTROL / P3B-EXPAND / **P5-BTB** / **P6-FAN-EDL**。 - -载板原理图 **8 页**（顺序已排）： -**C1-CONN** / C2-HUB / C3-USB / **C4-SITE1~5**。 - -截图：**12 页里已截 10 页**（缺 P2B/P2C/P2D，它们是 P2 的机械复制）—— -`P1-INPUT.png`、`P1B-5V.png`、`P2-CHANNEL.png`、`P2E-CH5.png`、`P3-CONTROL.png`、 -`P3B-EXPAND.png`、`P4-USB.png`、`P4B-HUB.png`、`P5-HARNESS.png`，PCB 最新是 `PCB-layout-v4.png`。 -（上一轮那三张空白 PNG 是渲染没出来，不是图元缺失；这一轮重截，都是好的。） - -## 这一轮做了什么（2026-09-04，方案转向） - -### 一、自动布线（转向前完成的部分） - -见下面「自动布线终于跑起来了」那节。**结果保留着**：1208 过孔 / 5814 导线， -6/7 对 USB 差分布通，间距/物理错误 0。但接口区马上要大改，别在这上面继续投入。 - -**三条最贵的教训**（每条都卡了很久）： - -1. **板框必须是一条闭合 polyline**，不能是 4 直线 + 4 圆弧。 - 自动布线器取板框走 `fu()`，只扫 polygon 管理器；独立线/弧不在那个表里 → - `getFilterBoard()` 返回空 → 弹「请先绘制板框！」然后**静默退出**。 - 正确写法：`pcb_MathPolygon.createPolygon(SRC)` → `pcb_PrimitivePolyline.create('', 11, poly, 5)`。 - ⚠️ 直接把源数组喂给 `create()` 会抛「无法创建多边形图元」而且**真的没建** - —— 跟铺铜那条「抛了也算成功」方向相反。 -2. **布线跑的时候什么都别碰**。不要 `save()`、不要 `pcb_Drc.check()`、 - 连 `getAll()` 这种只读调用都别做。被打断时 `routerResult()` 里 - `state!==1` 会**直接丢弃**结果 —— 画布上看得见、`getAll()` 数得到， - 但没进文档模型。**判据只有一个：save 后重新 `openDocument` 再数一次。** -3. **差分对要一次统筹全部 7 对**。一对一对布会互相堵死（`保留` 模式下先布的成了障碍）。 - 正确姿势：全选 7 对的焊盘 + 「已有导线/过孔 = **移除**」+「布线网络 = 所选网络」。 - -其它：重载客户端会清空自动布线对话框的设置；DRC 面板刷不出来时走 -`设计 → 清除错误` → `设计 → 检查DRC`。 - -### 二、方案转向：两块板（用户 2026-09-04 拍板） - -用户的原始需求分四次说清楚： -1. 「做成两块板，五路 usb 移到上板，排针对接，上板加五块主板定位」 -2. 「进入 9008 的控制接口也接入」 -3. 「与主板连接的 usbhub 移到上板，不用排针，排针只需要把下板的电源部分接上来」 -4. 「侧键做顶针，EDL 做 2 针 1.25mm 座子我自己接线，VBUS 通断走排针」 -5. 「不要散热垫，加风扇」→「侧面两侧各 2 个小风扇吸入，顶部 1 个大风扇排出」→「风扇装 3D 打印外壳上」 - -**完整规格写在设计文档 §22**，这里不重复。 - -### 三、⭐ 小米8 主板机械数据：**一直就在我们自己的 PDF 里** - -**旧结论「PDF 是电气原理图、不含机械尺寸、只能实测」是错的。** -`小米8原理图/Xiaomi_Mi_8_Schematic.pdf` 共 46 页， -**前 2 页是正反面位号图**（含完整板框轮廓 + 全部位号），后 44 页才是原理图。 -当初只按「原理图」去读，`get_text()` 一看全是位号就跳过了，**从没渲染出来看一眼**。 - -拿到的数据（方法与精度分档见 §22.3a / §22.3b）： -- 比例尺 **17.0 pt/mm**（从 464 个 0201 封装反推，卡尺验证 0.7%） -- 主板 **44.66 × 67.09 mm**（卡尺实测） -- **7 个定位孔**（从用户标红框的照片提取，±0.5 mm） -- EDL / 尾插 / 侧键触点（从**器件本体图元**提取，±0.3 mm，并被两个卡尺读数交叉验证） - -### 四、⚠️ 这一轮我判错了四次，都是同一个毛病 - -**没有实物对照就从矢量图元硬推。** 记下来，别再犯： - -| 判错 | 错因 | -|---|---| -| 「主板没有定位孔」 | 轮廓用「逐行取最外侧墨点」提取，**这方法看不见板内的孔和挖空** | -| 「定位孔就是图纸上那 7 个圆」 | 抓到的是测试点和圆焊盘。摆成横向和用户照片一对就露馅 | -| 把两个卡尺读数当成「板厚」 | 用户说的是**侧键到板边的距离** | -| 把 **7.61** 读成 **1.76** | 卡尺屏是旋转的，数字看反了 | - -**规矩**：卡尺读数先跟用户确认再落档；从图纸推的几何结论， -必须有一个实物基准交叉验证才能写进文档。 - -### 五、EDL(9008) 电路（原理图 Sheet 17，比维修站的付费短接图可靠） - -``` -VREG_S4A_1P8 ──[R1204 1.8kΩ 0201]── TP1204 ← 0.75 mm 测试点 -FORCED_USB_BOOT ──┬── TP1205 ← 0.75 mm 测试点 - └── CR1209 PESD3V3V1BCSF ── GND -``` - -短接两点 = 把 `FORCED_USB_BOOT` 拉到 1.8V → 进 9008。 -**串了 1.8 kΩ，短路电流只有 1 mA**，一颗模拟开关就够。详见 §22.4。 - ---- - -## 这一轮：自动布线终于跑起来了（2026-09-04） - -### ⚠️⚠️ 头号发现：**板框必须是一条闭合多段线，不能是 4 直线 + 4 圆弧** - -`布线 → 自动布线... → 运行` **静默失败**：对话框正常关闭、一根导线不画、 -`console` 没有任何异常、也没有网络请求。三次尝试（React onClick / 原生 -dispatchEvent / 等 90 秒）现象完全一样。 - -顺着客户端 bundle 追下去才找到： - -``` -pcb_ManufactureData.getAutoRouteJsonFile() - → ui.js getAutoRouteJson() → windowBridge.rpcCall('getNewAutoRouteJson', …) - → pcb.js vP.autoRouting() → createPangolinJson() - → getFilterBoard() → fu() → [] ← 就是这里 - → 弹 "Please draw a board outline first!" 然后 return undefined -``` - -`fu()` 的判据是（pcb.js 反编译）： - -```js -[Ni.getInstance().getAllItem(), tn…, Yi…] // 只有 polygon 管理器 - .forEach(t => t.forEach(e => { - !e.isEmpty && (e.type == "Board Outline" || e.type == "Line" && e.layerId == 11) && o.push(e) - })) -``` - -**它只扫多段线（polygon）管理器**。我们的板框是 -`pcb_PrimitiveLine.create()` × 4 + `pcb_PrimitiveArc.create()` × 4， -八个独立图元，压根不在那个表里 —— 于是 `fu()` 恒返回空。 - -这个错**极难往板框上想**，因为除了自动布线，板框在别处全都是好的： -渲染正常、铺铜按它的几何铺好了、DRC/ERC 全过、Gerber 也认。 -同一个 `fu()` 还卡着 `getDsnFile()` 和 `getAutoRouteJsonFile()` -（两个都返回 `undefined`，等于 freerouting 那条路也被堵死了）。 - -**正确姿势（两步，缺一不可）**： - -```js -const poly = await eda.pcb_MathPolygon.createPolygon(SRC); // ⚠️ 必须先过这一步 -await eda.pcb_PrimitivePolyline.create('', 11, poly, 5); -``` - -⚠️ 把 `TPCB_PolygonSourceArray` **直接**喂给 `pcb_PrimitivePolyline.create()` -会抛「错误：无法创建多边形图元」，而且是**真的没建**（`getAll()` 仍是 0）—— -注意这跟铺铜那条「`create()` 抛了也算成功」的经验**方向正好相反**，别混用。 - -`pcb_place.py` 的 `push_outline()` 已经改成这个写法（新增 `outline_poly()`）。 - -### 一路排查中间踩到的三件事 - -1. **`pcb_PrimitiveArc.getAll()` / `getAllPrimitiveId()` 在本工程恒返回 0。** - 排查时我以为四个 R5 圆角不存在，又补建了四段 —— 于是 layer 11 上现在有 - **8 段重叠圆弧 + 4 条重叠直线**（几何完全重合，Gerber 上是同一条路径描两遍）。 - 它们不在 `fu()` 的表里，不影响布线；但**删不掉**（枚举不到就没有 primitiveId）， - 要清只能在客户端里手删，或者隐藏其它层后框选 layer 11 全删再重建 polyline。 -2. **桥接的 WS 请求 30 秒硬超时**，`eda.py` 的 `timeout=` 只管 HTTP 那一段。 - JS 里 `sleep` 超过 30 s 一律拿到 `Request … timed out after 30000ms`。 - 要等就分多次短调用轮询。 -3. **客户端重连会换 `windowId`**。`curl http://127.0.0.1:49620/eda-windows` 可以确认 - 当前只有一个窗口 —— 排查「是不是打到另一个窗口去了」时先看这个，别猜。 - -### 抓静默失败的通用手法（这轮就是靠它破的） - -页面里挂三层钩子，再触发一次，就能看见吞掉的错误： - -```js -// ① console 全接管 ② window.onerror / unhandledrejection ③ fetch / XHR / Worker -// ④ 最关键：postMessage —— 父窗口与编辑器 iframe 之间的 rpc 都走这里 -window.addEventListener('message', e => { …记录 topic 与 message… }, true); -document.querySelector('iframe.editframe').contentWindow - .addEventListener('message', …, true); -``` - -回包里 `{"topic":"getNewAutoRouteJson_MSG_BUS_RPC_64600","type":"push"}` -**没有 message 字段** —— 一眼就能断定是 iframe 里的处理函数返回了 undefined， -而不是参数没传对或者按钮没点上。 - -再配合 `console.warn` 里打 `new Error().stack`，能直接定位到 -`ui.js:1819` 的 `getAutoRouteJson`，然后把 `pro-ui/…/js/ui.js`（17 MB）和 -`pro-pcb/…/js/pcb.js`（10 MB）下下来 grep —— 这两个包是公开 CDN，随便下。 - -### 自动布线的设置（对话框里的状态是持久化的，改一次就记住） - -| 项 | 取值 | 为什么 | -|---|---|---| -| 布线网络 | 所有网络 | | -| 布线拐角 | 45° | | -| 已有导线/过孔 | **保留** | 708 个扇出过孔和平面层不能被冲掉 | -| 效果优先级 | 完成度优先 | | -| 布线图层 | **只勾顶层 + 底层** | 内层1 是完整地平面、内层2 是电源平面，**不许被信号线割开** | -| 忽略网络 | **15 个** | `GND`（459 个扇出过孔已经接到地平面了，让它布会刷出一堆顶层地线）+ 7 对差分的 14 个网络（`USB1~5_DP/DM`、`UP_DP/DM`、`USB_DP/DM`，打算之后按对单独布） | - -对话框是 React 的，`忽略网络` 那个下拉可以直接从 fiber 上取 `onChange` 逐个灌： - -```js -const p = /* 从 [data-id^="selectOptionKey_"] 往上找带 {list, onChange} 的 fiber */; -p.onChange('GND'); // 每加一个 list 就少一个，要重新取 fiber -``` - -### ⚠️ 自动布线的结果**不到最后不落盘** —— 中途被打断就白跑 - -第二趟（补差分对）跑完，`getAll()` 报 6196 条导线、几何上逐段查过 -**USB1_DP 从 U32.2 一路连到 J17.3、并查集只有一个连通块**， -但 DRC 咬定这两个焊盘断开。`pcb_Document.save()` 之后 -**重载客户端，板子回到了第一趟的 1095 过孔 / 3455 导线** —— 第二趟一根线都没进文档。 - -原因在 `routerResult()`： - -```js -routerResult(t){ if(this.state!==1){ console.error("Auto Routing is stop!", this.state); return; } … } -``` - -布线结果是一批一批推回来的，`state!==1`（被打断）时**直接丢掉**。 -画布上看得见、`getAll()` 数得到，但那只是 `historyGroup` 里的预览，没有进文档模型 —— -**所以 DRC 是对的，错的是我**。 - -**判据只有一个：save 之后重新 `openDocument`，再数一次导线/过孔。** -数字对不上就是没落盘。别信 `getAll()`，也别信画布。 - -跑的时候不要碰客户端：不要 `save()`、不要 `pcb_Drc.check()`、 -连 `pcb_PrimitiveVia.getAll()` 这种只读调用都先别做 —— 第二趟就是这么被打断的 -（第一趟跑满 ~50 分钟、进度条自己消失，结果就落盘了）。 -盯进度只读 DOM 文本：`document.body.innerText` 里那行 `自动布线中...(NN%)`。 - -### 顺带两条 - -- **重载客户端会把自动布线对话框的设置清空**（忽略网络清零、四个布线图层全勾回来）。 - 重载之后必须重新配一遍再跑。 -- **DRC 面板刷不出来时走菜单**：`设计 → 清除错误`（`全部 (0)`）→ `设计 → 检查DRC`。 - 面板上那个「刷新」按钮不是 DRC 的，`pcb_Drc.check()` 单独调有时也不刷新。 - -### 局部返工：把 7 对 USB 差分抢回通道（2026-09-04，用户拍板） - -第一趟自动布线之后，**7 对差分只布上 2 对**（USB1/USB2），其余 5 对 -连「所选网络」单独重跑都一根线不画 —— 板子已经被普通信号线占满了。 -用户拍板走「局部返工」而不是整体回滚。四步： - -**① 先改规则**（`pcb_rules.py --push`），否则布完还是一堆假违规： - -| 改动 | 从 | 到 | 为什么 | -|---|---|---|---| -| `differentailPairLenTolerMax` | 0.5 mm | **5 mm** | USB 2.0 HS 对内偏斜预算 ≈100 ps ≈ 15 mm；实测偏差 1.6~1.9 mm ≈ 10 ps。为凑 0.5 去绕蛇形线是拿串扰换数字 | -| 新增安全间距条目 `USBPAIR` | — | **0.15 mm** | 只通过 `overwriteNetByNetRules` 挂在**每一对自己的两个网络之间**；对其它网络仍是 0.2 mm | - -`USBPAIR` 那条**不能**用全表抬下限的循环扫到（会被抬回 0.2），代码里单独跳过了。 - -net-by-net 的条目形状文档没写，是从 `pcb.js` 的 `getBetweenNetDataItem()` 反出来的： - -```js -{net1:{type:'net',name:'USB1_DP'}, net2:{type:'net',name:'USB1_DM'}, - rule:'USBPAIR', copperRuleName:null, planeRuleName:null} -``` - -⚠️ `overwriteNetByNetRules` 是**整表覆盖**，要先 `getNetByNetRules()` 读回来再合并。 -改完 DRC 172 → 166，4 条对内间距 + 2 条等长违规一起消失。 - -**② 三条低压轨改成铺铜**（铜面 15 → **19** 块）： - -| 铜面 | 网络 | 层 | 范围 | 盖住 | -|---|---|---|---|---| -| 5V-L3 | `+5V` | L3 | x 11~151 / y 5.5~14 | 10 / 16 | -| 3V3HUB-L3 | `+3V3_HUB` | L3 | x 59~111 / y 15~31 | **21 / 21** | -| 3V3-CTRL-L3 | `+3V3` | L3 | x 95.5~150.5 / y 33.5~67 | 合计 45 / 61 | -| 3V3-CH-L3 | `+3V3` | L3 | x 5~155 / y 100.3~124 | 同上 | - -都塞在 12V 那三条带子之间的空地里，互相与 12V 都留 ≥0.5 mm。 -`3V3-CTRL-L3` 的右边界 150.5 是被 ESP32 天线禁铺区（x≥151）逼的。 - -这带出两个工具改动： - -- **`pcb_pour.audit()` 要按网络做并集**。`+3V3` 是**两块**铜面，逐块判「焊盘在不在里面」 - 会让每一块都把另一块盖住的焊盘报成「意外漏掉」。 -- **新增 `POUR_PARTIAL = ('+5V', '+3V3')`**：这两条轨的铜面**故意只盖一部分**， - 漏在外面的焊盘靠走线接，不算错。 - -**③ `pcb_fanout.py` 只对「落在自己铜面里」的焊盘扇出**（新增 `_pour_filter()`）。 -在没有铜的地方打一个下到 L3 的过孔 = 一个悬空过孔，DRC 反而多一条断连。 -三条轨一共扇出 91 个过孔，5 个焊盘周围太挤放不下，留给走线。 - -**④ 局部返工的选取判据**（`_snap_before.json` 是基准）： - -``` -删掉「布线器加的」且满足下面任一条的**整个网络**的线与过孔： - a) 网络已经改成铺铜（+5V / +3V3 / +3V3_HUB） - b) 该网络在 y < 28 mm 的下带里有走线，且不是 GND/12V/VOn 这类扇出网络、也不是差分对 -``` - -结果：**34 个网络 / 678 条导线 / 68 个过孔**，只占布线器产物的 18%。 -整网删、不留断头，剩下的 80% 一根没动。 - -### ⚠️ 差分对必须**一次统筹全部 7 对**，一对一对布会互相堵死 - -下带清空之后，选中 5 对跑「所选网络」，**只布上 USB4/USB5**；再跑一次， -一根线都不加。原因是 `保留` 模式下先布好的那两对成了后面的障碍 —— -USB3 与上游 UP 要横穿它们，而下带就那么宽。 - -正确姿势是**把 7 对全选中 + 「已有导线/过孔 = 移除」**，让布线器把已布的两对 -一起拆掉重排。`clearRoute(false, undefined, this.selectNets)` 只清选中的网络， -不会波及别处（pcb.js 里确认过）。一趟下来 **6 / 7 对布通**（USB1~5 + UPSTREAM）， -只剩 ESP32 那条调试口 `USB_DP/DM`。 - -顺带澄清一条之前的误判：**「所选网络」模式是好的**。早先它「跑完却一根线不画」 -不是模式坏了，是那时候板子上真的没路了 —— 日志里 `routingRange:1`、选中 24 个焊盘 -都对，弹的也是「自动布线已完成」而不是报错。 - -### 布线跑完之后要做的（按顺序） - -1. **DRC** —— `python .claude/drc_read.py`。看「间距错误」和「物理错误」两支， - 连接性错误剩多少 = 还有多少没布上。 -2. **七对差分单独布**（`USB1~5_DP/DM`、`UP_DP/DM`、`USB_DP/DM`）。 - 规则里已经建好 7 对、W 0.28 / S 0.18 / 等长容差 0.5 mm。 - ⚠️ **顺序上其实应该先布差分再自动布线**——这一轮是为了先验证布线器能不能跑才反过来的。 - 如果跑完发现差分对已经无路可走，就按快照回滚，改成「先差分后自动」重跑。 -3. **重新铺铜**。底层（layer 2）上有 VO1~5_P 五块铜面，自动布线在底层加了信号线， - 铜面要重建才会让开它们：`工具 → 铺铜管理器... → 重建所有` - （`pcb_pour.py --rebuild` 里已经把这一串打好了；`rebuildCopperRegion()` API 是坏的）。 -4. **丝印整理** —— 位号大面积压字，打样前要单独跑一遍。 -5. Gerber 预览复核板框闭合 + 四个 M3 定位孔。 - -### 跑之前先存了个快照（`.claude/_snap_before.json`） - -布线前把 708 个过孔 + 575 条导线的 `primitiveId` 全存了下来。 -万一自动布线的结果不能要，**删掉不在这张表里的线和过孔**就能精确回滚， -比 `清除布线`（会连扇出一起清）干净得多。 - ---- - -## 上一轮：开始布线（2026-09-03） - -顺序是「先把面铺好，再拉线」—— 平面定了，信号线的参考面和过孔位置才有依据。 - -### 1. 先抓到一个真的断线：U13 的 SCL 没接上 ⚠️ - -追 12V 母线的网络时发现 PCB 里 `U13.2 / U13.5` 挂在一个只有两个焊盘的 -`$1N257` 上，而 `SCL` 网络 11 个焊盘里没有 U13。**输入侧检流那片 INA226 是死的。** - -根因不是漏画线，是 **`SCL` 端口的引脚压在一条导线的中段而不是端点** -（端口在 (920,340)，导线是 `[920,320 → 920,570]`）。EasyEDA 只在端点认连接。 -同一页的 SDA 端口恰好落在端点上，所以 SDA 是好的 —— **两个端口在图上一模一样**。 - -DRC / ERC / `verify_sch --nets` / 跨页对账**四道全过**，因为 -`verify_sch` 的判据是「引脚落在某条导线段上」，中段搭接满足这一条。 - -新增 **`.claude/port_audit.py`**：全工程 572 个旗/端口逐个判「是不是某条导线段的端点」。 -修之前 1 个不合格（就是它），修完 0 个。写进 `easyeda-sch-geometry` **§8a-2** 与设计文档 **§19.4**。 - -> 写这个检查时踩了个自伤的坑：第一版按折线解析导线，572 个里报出 **197 个可疑**， -> 其中一大片是工作正常的 GND 旗。`getState_Line()` 返回的是**端点对**（skill §5）， -> 按折线解析会凭空造出斜线段。误报到这个程度的检查等于没有检查。 - -### 2. 8 A 输入链整条重排 - -原来这一串是仿射映射甩出来的，`J1(x5.8) → F1(x46.6) → Q1(x53) → 体电容(x66/75) -→ Rs6(x84.6~90.7)`：**8 A 要从 x5.8 走到 x90.7，85 mm**，其中 `$1N223`（J1→F1） -单独一段就 42 mm。8 A 在 0.5 oz 内层要 ΔT=20 °C 得 **18 mm 宽**铜面 -（IPC-2221 内层按外层 50% 取，面积翻倍），band B 一共才 36 mm 高，塞不下四条。 - -而且这一串在 y 上来回折（F1.2 在 y60.08，Q1 源极在 y62.85，中间还夹着 -`$1N236` 在 y60.56 的一个焊盘），L3 上按 y 切开分块，切线最窄处只剩 0.2 mm。 - -**改成 J1 右手边一条走廊 x 11.5~46 / y 49.5~68.5**（栅极网络放 J1 上方口袋）： - -| | 之前 | 现在 | -|---|---|---| -| `$1N223` J1→F1 | 42 mm | **6.9 mm** | -| 8 A 段的横跨 | x 5.8 ~ 90.7 | x 12 ~ 40 | -| 分叉点 | x 90.7 | x ≈ 40（Rs6 下游）| -| 母线最大截面电流 | 8 A 全程 | 顶带 ≤ 6.4 A（往左喂 CH1、往右喂 CH2~5）| - -顺带把 13.7 × 9.7 的立式泄放电阻 R9 也钉死了 —— 仿射区右缩之后它被推到 x95， -**本体框伸到 x102 压进 P3 区**。`relax()` 只夹中心坐标、不看外框，这类件必须手钉。 - -### 3. 平面层（`.claude/pcb_pour.py`） - -| 铜面 | 层 | 网络 | 范围 | -|---|---|---|---| -| GND-L2 | L2 | GND | 整板（板框内缩 0.5，挖 ESP32 天线区）| -| VIN-RAW-L3 | L3 | `$1N223` | x 3~14 / y 45.5~55.5 | -| VIN-FUSED-L3 | L3 | `$1N227` | x 14.6~19 / y 49.5~56.5 | -| VIN-SW-L3 | L3 | `$1N236` | L 形，x 14.4~35 / y 49~66.5 | -| 12V-L3 | L3 | `+12V` | 下带 x14.6~95 y33~48.3 + 中带 x38.5~95 + 顶带全板 y67.5~81.9 | -| VO1~5-L3 | L3 | `VOn` | 每路 30 mm 宽 / y 82.5~99.5 | -| VO1~5_P-L4 | **L4** | `VOn_P` | 每路 30 mm 宽 / y 110~116.2，带一条下伸臂到分流电阻 | - -分界线是**焊盘边**定的不是整数：+12V 顶边 81.9 卡在 C102 那排 1210 焊盘（y80.2~81.7）； -VOn 底边 82.5 是因为 C107 pin1 是 rot90 的 1210，焊盘跨到 y83.07~84.55 —— -按「元件中心在 y85.4」算会把它漏在两块铜面之间的缝里。 - -**U8~U13 的 0.5 mm 间距 Kelvin 脚一律不进铜面**（U13.10 是 VIN+、U13.9 是 VIN−， -相距 0.5 mm，任何分界线都塞不进去），走顶层细线，本来也不载流。 -`pcb_pour.py` 里 `audit()` 会把「本网焊盘在铜面外」的逐条列出来， -`EXPECT_OUT` 是白名单，漏在名单外的就要查。 - -### 4. 铺铜 API 的三个坑（都实测过） - -1. **`rebuildCopperRegion()` 是坏的**，四种写法都抛 - `Cannot read properties of undefined (reading 'length')`。 - 唯一能填充的路子是 GUI：**工具 → 铺铜管理器... → 重建所有 → 确认**， - 已用 React 的 `onClick` 打进 `pcb_pour.py`。判据是 `nPoured` 不是 `nPour`。 -2. **多边形必须显式闭合**（末尾把首点再写一遍）。文档说「首尾不重合会自动重合」 - 对铺铜边框**不成立**：不闭合就直接不建。`board_poly()` 一直能用是因为 - 它最后那段圆弧正好回到起点。 -3. **`create()` 成功了也会抛** `错误：无法创建覆铜边框图元`。返回值和 try/catch - 都不能当判据，只能建完 `getAll()` 按名字核对 —— 而且**名字会被转成大写**。 - -排查时分不清 1 和 2 的办法：不闭合的矩形建完 `getAll()` 数量不变，闭合的 +1， -**两者抛一模一样的异常**。 - -### 5. GND 扇出：改布局之后必须按这个顺序重跑 - -```bash -python .claude/pcb_fanout.py --clean # 1. 先清空板上的过孔与走线 -python .claude/dump_pads.py # 2. 再重新抓障碍表 -python .claude/pcb_fanout.py --push # 3. 最后规划 + 下发 -``` - -`--clean --push` 写成一条**会用旧的 `pcb-copper.json`**：清是清干净了， -规划器看的还是那 459 个已经不存在的过孔，把它们当障碍绕 —— -实测 459 → 292 个过孔、五路 Buck 的 pin2 全扇不出去、27 个散热盘只打进 4 个孔。 -反过来先 dump 再 `--clean --push` 更糟，板上会剩两套（747 个）。 - -正确顺序的结果（15 个网络一趟跑完）：**708 个过孔 / 0 个失败**， -其中 GND 459、+12V 128、输入链三条 48、五路 VOn 各 17、五路 VOn_P 各 8。 - -### 6b. 出线宽度必须**按焊盘**算，不能按网络算 - -第一版给功率网络一刀切 1.0 mm（= 线宽规则的最小值），结果 **29 个焊盘扇不出去**： -`+12V` 上挂着 R104 那种 0402 分压抽头，焊盘只有 0.57 × 0.54 mm， -**1.0 mm 的线比焊盘还宽**。退回 0.3 mm 硬扇出去，又被判 -「线宽 11.8 mil，应在 39.4 ~ 393.7 mil」—— 34 条物理错误。 - -两处一起改才对： - -1. `PWR4A` / `PWR12V` 的**最小值 1.0 → 0.3**（默认值仍是 1.5 / 2.0）。 - 这就是 §10.1 那条「载流靠灌铜保证，不靠 DRC」再走一步。 -2. 出线宽度按**焊盘短边 × 0.9** 取，夹到 [0.3, 1.0]；过孔数按焊盘短边 ≥ 0.8 mm 给 3 个、 - 否则 1 个 —— 0402 抽头本来就不载功率电流，多打过孔只会把平面打成筛子。 - -### 6c. 扇出的障碍模型漏掉的两件事（DRC 抓出来的） - -| 现象 | 根因 | -|---|---| -| 10 条「导线到过孔 3.4 mil，应 ≥ 7.9 mil」 | 板上已有的过孔只按**钻孔半径 0.15** 登记进 holes，没按**焊盘半径 0.3** 登记进 grid。差的正好是 0.15 mm | -| 1 条「导线到导线 6.2 mil」 | **出线之间的间距压根没查**过 —— 原来只查了线对焊盘、线对钻孔 | - -两条都补进 `pcb_fanout.py` 了（`trk_grid` + `seg_seg_dist`）。 -补完重跑：**间距错误 0、物理错误 0**。 - -### 6. 顺手发现的两条 EasyEDA 路子 - -- **设计 → 从原理图导入变更（Alt+I）** 能用 DOM 打开并读出变更表， - 逐条列 `U13:2 $1N257 → SCL`。改完原理图必须走这一步，PCB 才会跟着变。 -- **布线 → 扇出布线... / 自动布线... / 差分对布线 / 等长调节** 都在菜单里。 - 信号线那 400 多条不必自己写布线器，下一轮直接驱动它。 - -## 最新一轮：设计规则不用手动了（2026-09-03 深夜，收尾） - -上一轮结论「规则配置只能在 GUI 里手建」**是错的**。原因是参数形状给错了， -现在 `python .claude/pcb_rules.py --push` 一条命令把五项全下发，`--check` 七项全 OK： - -``` -[OK] 四层板能力集已就位（最小线宽 0.102 / 过孔 0.30-0.20，含 0.5oz 内层条目） -[OK] 线宽规则 PWR12V 存在 [OK] 线宽规则 PWR4A 存在 -[OK] 差分对几何 W 0.280 / S 0.180 mm -[OK] 安全间距下限 0.2000 mm -[OK] 差分对 7 对: DEBUG UPSTREAM USB1 USB2 USB3 USB4 USB5 -[OK] 线宽指派 12 个网络 -``` - -### 当初为什么以为不行 —— 两个坑叠在一起 - -1. **`overwriteCurrentRuleConfiguration(x)` 要 config 本体，不要 `{name, config}` 包装。** - 传包装返回 `undefined` 且静默无效；传本体返回 `true`。 - （`saveRuleConfiguration(cfg, name, allowOverwrite)` 确实是三个参数 —— - 上一轮只传了一个 —— 但补齐了照样返回 `false`。**它是真的不能用**， - 好在我们并不需要存命名配置。） -2. **两种 config 的形状不一样，混用会被默默吃掉。** - - | 来源 | 线宽 | 安全间距表 | - |---|---|---| - | `getRuleConfiguration('<系统能力集>')` | **平**：`form.strokeWidthDefault` | `entry.table` | - | `getCurrentRuleConfiguration()` | **嵌套**：`form.data['1'].defaultValue` | `entry.tables['1'].content` | - - 正确姿势：**拿 `getCurrentRuleConfiguration().config` 改，原形状送回去**。 - 系统能力集只当数据源用（那张内层 0.5 oz 间距表是从它身上抄的）。 - -### 「切到多层板能力集」其实只是五个字段 - -把两个能力集逐值 diff 过：**只差 3 个数 + 2 条默认不启用的条目**，其余 300 多个数完全一致。 - -| 项 | Two Layers | Multiple Layers | -|---|---|---| -| `Track/copperThickness1oz` 最小线宽 | 0.127 | **0.102** | -| 过孔外径最小 | 0.5 | **0.3** | -| 过孔内径最小 | 0.3 | **0.2** | -| `Track/copperThickness0.5oz` | 无 | 有（min 0.089，`isSetDefault=false`）| -| `Safe Spacing/copperThicknessInner0.5oz` | 无 | 有（`isSetDefault=false`）| - -也就是说，能力集之间的差别**全是放宽限制**，两层板那套只是更保守。 -真正必要的是最小线宽 0.102（U32 那个 0.5 mm 间距 QFN-64 的扇出要用）。 - -### ⚠️ 下发之后千万别做的一件事 - -**别再去 GUI 的 设计 → 设计规则… 里动“配置”下拉框。** -换一下就是整套重置：`PWR4A` / `PWR12V` 两条线宽规则会被冲掉， -12 个功率网络的指派立刻变回悬空（**DRC 不报错，线宽也就不生效** —— 查不出来的那种坏）。 -要改规则就改 `pcb_rules.py` 再 `--push`。 - -配置名下发后会自动变成 **“自定义配置”**，这是对的 —— -说明它已经从系统能力集上摘下来了。 - -### 顺带踩到的一个坑：mm 值会被换算成 mil 再换回来 - -写进去 `0.2`，回读是 `0.19999959999999997`（差 4e-7 mm）。 -**任何几何值都不能做精确比较**，`--check` 的容差已放到 1e-4。 -（第一版容差 1e-9，结果安全间距那项在明明写对的情况下报红。） - -### DRC 结果读得回来（`.claude/drc_read.py`），而且真抓到了 9 个错 - -先说一句：本轮早些时候写的「DRC 结果读不回来」**是错的**，已推翻。 - -`pcb_Drc.check()` 确实只返回一个 boolean，40 多个方法里没有结果 getter， -也没有 DRC 标记层可读。**但 DRC 面板在 DOM 里是挂载着的** -（跟设计规则对话框不一样，那个窗口不前台就不挂载）。三个手法： - -1. 左边分类树要用 **React 的 onClick** 点 —— 从元素上找 `__reactProps$*`， - 一路往上找到带 `onClick` 的那层直接调。`el.click()` 不管用，不点就不选中， - 右边明细区一直是「空列表」。 -2. **「清除错误」那个反过来**，它是原生 `