72 行
5.1 KiB
Plaintext
72 行
5.1 KiB
Plaintext
=== [PCB1] drc retry
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全部 79 条 = 间距错误 0 + 连接性错误 79（连接性 = 还没布线，预期之内）
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✅ 没有间距错误。
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=== [PCB1] outline
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assert des in PARTS, u'位号不存在: %s' % des
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^^^^^^^^^^^^
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AssertionError: 位号不存在: J2
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=== [PCB2] place push
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布局已下发并保存：218 个元件
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排母焊盘坐标已导出: D:\DCDC\.claude\pcb2-header-pads.json（80 个）
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R761 (L2) pin1 [20.29, 89.659, 2] pin2 [19.423, 89.659, 2]
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U24 (L2) pin1 [36.241, 100.711, 2] pin4 [38.941, 102.611, 2]
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J31 (L2) pin1 [37.869, 68.77, 12] pin2 [37.869, 66.23, 12]
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=== heights/env
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J64 h=3.6 x 99.1~107.4 y 46.2~51.5
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J65 h=3.6 x 170.6~178.9 y 46.2~51.5
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CH4-tail x 55.75~ 74.75 y 0.00~ 1.30
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CH5-bat x 101.05~111.05 y 0.00~ 1.30
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CH5-tail x 127.25~146.25 y 0.00~ 1.30
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=== [PCB1] place check
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C610 -> U7 .15 1.31 mm（上限 3.0） 摆在 (109.49, 37.49) rot 0
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安排了 290 / 290 个元件
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本地检查通过：焊盘净距≥0.2 / 无重叠 / 无越框 / 不压定位孔 / 高度预算全过 / 排针阵列对上锚点 / 去耦贴身
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=== [PCB2] dumps
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ImportError: cannot import name 'build' from 'pcb2_dp_long' (consider renaming 'D:\\DCDC\\.claude\\pcb2_dp_long.py' if it has the same name as a library you intended to import)
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-> D:\DCDC\.claude\pcb2-copper.json
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=== [PCB2] route_sig --push
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[!!] +3V3_HUB 布不通：(88.20,71.08) -> (35.79,106.66)
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[!!] EDL_EN3 布不通：(179.57,106.66) -> (114.76,60.41)
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[!!] KEY_SRCLK 布不通：(120.24,60.41) -> (129.24,60.41)
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[!!] KEY_SRCLK 布不通：(120.24,60.41) -> (126.02,71.40)
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[!!] K1_PWR 布不通：(113.48,54.06) -> (63.59,119.14)
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[!!] K1_VUP 布不通：(113.48,55.33) -> (60.09,119.14)
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[!!] K1_VDN 布不通：(113.48,56.60) -> (56.59,119.14)
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[!!] K3_PWR 布不通：(117.98,71.40) -> (206.59,119.14)
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[!!] K3_VUP 布不通：(117.98,70.13) -> (203.09,119.14)
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[!!] K3_VDN 布不通：(117.98,68.86) -> (199.59,119.14)
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[!!] K4_PWR 布不通：(49.25,16.02) -> (122.48,54.06)
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[!!] K4_VUP 布不通：(52.75,16.02) -> (122.48,55.33)
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[!!] K4_VDN 布不通：(56.25,16.02) -> (122.48,56.60)
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[!!] K5_PWR 布不通：(120.75,16.02) -> (122.48,61.68)
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[!!] K5_VUP 布不通：(124.25,16.02) -> (123.76,60.41)
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[!!] K5_VDN 布不通：(127.75,16.02) -> (122.48,59.14)
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123 个网络 / 597 条路径 / 1314 段导线 / 236 个过孔 （779 秒）
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⚠️ 15 个网络没布通：+3V3_HUB EDL_EN3 KEY_SRCLK K1_PWR K1_VUP K1_VDN K3_PWR K3_VUP K3_VDN K4_PWR K4_VUP K4_VDN K5_PWR K5_VUP K5_VDN
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[!!] 切不动: $22N139 (82.00, 87.80) 转向 47°
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[!!] 切不动: +3V3_HUB 3 (90.46, 69.98) 转向 51°
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[!!] 切不动: +3V3_HUB 3 (90.96, 70.37) 转向 51°
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净距校核（0.20 mm）:
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[!!] 线-过孔 POGO2_PWR vs GND L1 净距 -0.405 段(140.48,120.75)-(139.80,121.50)
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[!!] 线-过孔 POGO2_VDN vs GND L1 净距 -0.405 段(138.18,121.14)-(131.70,121.10)
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[!!] 线-旧线 $22N139 vs GND L2 净距 -0.200 段(81.72,88.11)-(82.00,87.80)
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!! 净距还有问题，不下发。
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=== [PCB2] reload+drc
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已重载，新 windowId d633e26c-bfd3-4c62-b24f-3d1bef8f5b9e（5 s）
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全部 961 条 = 间距错误 145 + 连接性错误 701（连接性 = 还没布线，预期之内）
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── 贴片焊盘 到 导线 (24) ──
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1. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (K1_VUP): U21_2底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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2. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 : U21_4底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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3. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (K1_PWR): U21_1底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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4. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (EDL_EN2): U21_7底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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5. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (K1_VDN): U21_3底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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6. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (EDL_EN3): U21_6底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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7. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (EDL_EN5): U21_5底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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8. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (GND): U21_8底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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9. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DP): e9867贴片焊盘 (GND): C604_1底层对象 1到对象 2距离为2.7mil，应该>= 7.9mil
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10. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DM): e9872贴片焊盘 (K1_VUP): U21_2底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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11. [间距错误] 贴片焊盘 到 导线copperThickness1oz导线 (UP_DM): e9872贴片焊盘 : U21_4底层对象 1到对象 2距离为0mil，应该>= 7.9mil
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