zhou yang和Claude Opus 5
2bfe308b30
原理图/PCB 已在 EasyEDA 里做到 12 页跨页 0 漏接，固件刚完成骨架包 A1。 这次是把已有的一切一次性纳入版本控制，没有改动任何设计内容。 纳入： - 设计与需求文档、PROGRESS.md、小米8 参考原理图 PDF 与追脚脚本 - .claude/ 下的 EasyEDA 桥接工具链与几何/网表缓存（eda-parts.json、 pcb-parts.json、pcb-pads.json、p2-ch1.json 等，是重画各页的唯一事实来源） - 117 张验证截图（本项目所有方向问题都是靠人眼看截图发现的，属于证据不是垃圾） - firmware/ 的 A1 骨架与 site/ 文档站源码 .gitignore 排除：构建产物（firmware/build、host/build、sdkconfig）、 site/node_modules、__pycache__、桥接日志 _bridge.log、脚本自标的 *.stale。 .gitattributes 默认 `* -text`：现有 .py/.json 大多是 CRLF，原样存， 不让 git 重写行尾。唯一例外是 *.sh 强制 LF —— 带 \r 的 shell 脚本 bash 跑不了。 Co-Authored-By: Claude Opus 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01QYuExfgyYa6DzRRcUso8M8
78 行
1.3 KiB
JSON
78 行
1.3 KiB
JSON
{
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"new": {
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"EFUSE_EN1": 32,
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"EFUSE_EN2": 25,
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"EFUSE_EN3": 6,
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"EFUSE_EN4": 34,
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"EFUSE_EN5": 12,
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"FAN_PWM": 11,
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"FAN_TACH": 9,
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"IOEXP_INT#": 31,
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"KEY_OE#": 23,
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"KEY_RCLK": 17,
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"KEY_SER": 21,
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"KEY_SRCLK": 20,
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"NTC1": 39,
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"NTC2": 38,
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"SCL": 8,
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"SDA": 22,
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"UP_VBUS_DET": 24,
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"VBUS_EN1": 33,
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"VBUS_EN2": 18,
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"VBUS_EN3": 19,
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"VBUS_EN4": 35,
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"VBUS_EN5": 10
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},
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"old": {
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"EFUSE_EN1": 4,
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"EFUSE_EN2": 5,
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"EFUSE_EN3": 6,
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"EFUSE_EN4": 7,
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"SCL": 8,
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"KEY_SER": 9,
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"KEY_SRCLK": 10,
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"KEY_RCLK": 11,
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"EFUSE_EN5": 12,
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"VBUS_EN1": 17,
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"VBUS_EN2": 18,
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"VBUS_EN3": 19,
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"VBUS_EN4": 20,
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"VBUS_EN5": 21,
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"SDA": 22,
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"KEY_OE#": 23,
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"FAN_PWM": 24,
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"FAN_TACH": 25,
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"IOEXP_INT#": 31,
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"UP_VBUS_DET": 36,
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"NTC2": 38,
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"NTC1": 39
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},
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"pin2io": {
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"4": "IO4",
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"5": "IO5",
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"6": "IO6",
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"7": "IO7",
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"8": "IO15",
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"9": "IO16",
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"10": "IO17",
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"11": "IO18",
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"12": "IO8",
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"17": "IO9",
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"18": "IO10",
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"19": "IO11",
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"20": "IO12",
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"21": "IO13",
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"22": "IO14",
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"23": "IO21",
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"24": "IO47",
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"25": "IO48",
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"31": "IO38",
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"36": "IO44",
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"38": "IO2",
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"39": "IO1",
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"32": "IO39",
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"33": "IO40",
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"34": "IO41",
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"35": "IO42"
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}
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} |