zouyang/phonerail
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文件
284571de201e10586e02100d89080bdbaeb9e2f1
phonerail/.claude/r2/_p3b_live.json
T
zhou yang和Claude Opus 5 efcba30a0c R2 底板改 4 层（D15）：规则 / 几何 / 背面摆位 / 4 层布线与铺铜，已下发 
- 规则：铜层 2→4，差分 0.28/0.18，间距 0.15，过孔 0.3/0.2（rules_base）
- 几何：98×98 板框 + 4×M3，槽阵居中，L1 12V 大铜 + 指头（pcb_base）
- 摆位：五插槽留 L1，其余 133 件翻到 L4；背面镜像规则实测；Hub 放走廊 2、
  东移 2.5 mm；扇出圈 / 小件间距 1.5（去耦例外）/ 9 A 过孔阵禁区（place_base）
- 叠层按用户决定改为 L1 槽面 / L2 整层 +3V3 / L3 整层 GND / L4 器件面
- 布线：D± 七对按构造布通（USB3 掉头、USB1/2 北去掉头、USB4/5 东绕、
  J23 桥），+3V3 / GND / +12V 平面网每脚一孔，0.125 网格 + PathFinder
  开关（route_base、remote_route.ps1）；剩 37 个网待手工补
- 铺铜：4 层重写，入口链自南向北切段 + 断面校核（pour_base）；
  已下发布线 / 缝合孔 / 铜面轮廓，填铜未成功（待查）
- 工具：plot_base / plot_routes / shot_base，board_check 通孔两层都算

Co-Authored-By: Claude Opus 5 <[email protected]>
Claude-Session: https://claude.ai/code/session_0168Bu6SEx3cXXCJLkdnE6zB
2026-09-10 21:02:10 +08:00

2661 行
29 KiB
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820,
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890,
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1010,
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890,
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820,
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890,
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980,
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[
820,
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[
980,
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980,
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[
1050,
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1020,
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1050,
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1050,
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[
860,
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[
820,
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[
860,
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[
860,
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[
920,
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[
860,
370
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[
860,
375
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[
860,
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[
860,
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860,
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920,
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920,
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950,
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820,
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950,
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950,
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965,
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950,
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950,
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950,
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1030,
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1005,
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1030,
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1030,
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970,
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820,
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970,
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970,
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840,
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820,
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840,
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840,
330
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"texts": [
[
45,
806,
"[A] 74HC595 x2 —— 15 路侧键驱动（U21 在前，Q7S 级联到 U22 的 DS）",
0,
12
],
[
45,
795,
"先移入的位落到 U22.Q7；OE# 上拉 100k，ESP32 复位期间输出高阻",
0,
12
],
[
445,
790,
"[B] PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
0,
12
],
[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
0,
12
],
[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
200,
"[C] DAC63204 x2 —— 5 路调压（U6 = 0x4A / A0->SDA，U7 = 0x4B / A0->SCL）",
0,
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],
[
45,
189,
"三处 datasheet 强制要求，图上看不出来但接错就出问题：",
0,
12
],
[
45,
178,
" 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈",
0,
12
],
[
45,
167,
" 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）",
0,
12
],
[
45,
156,
" 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD",
0,
12
],
[
45,
145,
"内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）",
0,
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[
45,
806,
"[A] 74HC595 x2 —— 15 路侧键驱动（U21 在前，Q7S 级联到 U22 的 DS）",
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[
45,
795,
"先移入的位落到 U22.Q7；OE# 上拉 100k，ESP32 复位期间输出高阻",
0,
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[
445,
790,
"[B] PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
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[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
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12
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[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
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45,
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"[C] DAC63204 x2 —— 5 路调压（U6 = 0x4A / A0->SDA，U7 = 0x4B / A0->SCL）",
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[
45,
189,
"三处 datasheet 强制要求，图上看不出来但接错就出问题：",
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12
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[
45,
178,
" 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈",
0,
12
],
[
45,
167,
" 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）",
0,
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[
45,
156,
" 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD",
0,
12
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[
45,
145,
"内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）",
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45,
806,
"[A] 74HC595 x2 —— 15 路侧键驱动（U21 在前，Q7S 级联到 U22 的 DS）",
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[
45,
795,
"先移入的位落到 U22.Q7；OE# 上拉 100k，ESP32 复位期间输出高阻",
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445,
790,
"[B] PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
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[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
0,
12
],
[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
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45,
205,
"[C] DAC63204 x2 —— 5 路调压（U6=0x4A / A0->SDA，U7=0x4B / A0->SCL）",
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45,
190,
"三处 datasheet 强制要求，图上看不出来但接错就出问题：",
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45,
175,
" 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈",
0,
12
],
[
45,
160,
" 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）",
0,
12
],
[
45,
145,
" 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD",
0,
12
],
[
45,
130,
"内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）",
0,
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45,
806,
"[A] 74HC595 x2 —— 15 路侧键驱动",
0,
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600,
806,
"[B] PCA9555 输入扩展（地址 0x20）",
0,
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[
45,
205,
"[C] DAC63204 x2 —— 5 路调压",
0,
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[
45,
190,
"595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。",
0,
12
],
[
45,
178,
"OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。",
0,
12
],
[
45,
166,
"PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），",
0,
12
],
[
45,
154,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
142,
"DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。",
0,
12
],
[
45,
130,
"FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时",
0,
12
],
[
45,
118,
"100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。",
0,
12
],
[
95,
790,
"[A] 74HC595 x2 —— 15 路侧键驱动",
0,
12
],
[
600,
785,
"[B] PCA9555 输入扩展（地址 0x20）",
0,
12
],
[
150,
205,
"[C] DAC63204 x2 —— 5 路调压",
0,
12
],
[
45,
190,
"595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。",
0,
12
],
[
45,
178,
"OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。",
0,
12
],
[
45,
166,
"PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），",
0,
12
],
[
45,
154,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
142,
"DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。",
0,
12
],
[
45,
130,
"FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时",
0,
12
],
[
45,
118,
"100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。",
0,
12
],
[
45,
806,
"[A] 74HC595 x2 —— 15 路侧键驱动",
0,
12
],
[
600,
806,
"[B] PCA9555 输入扩展（地址 0x20）",
0,
12
],
[
150,
205,
"[C] DAC63204 x2 —— 5 路调压",
0,
12
],
[
45,
190,
"595: U21 在前，Q7S 级联到 U22.DS；先移入的位落到 U22.Q7。",
0,
12
],
[
45,
175,
"U22.Q7 = HUB_RST，远程复位板载 USB Hub（§21.7）；OE# 高阻时靠 R716 上拉保持不复位。",
0,
12
],
[
45,
178,
"OE# 上拉 100k —— ESP32 复位期间 15 路输出全部高阻。",
0,
12
],
[
45,
166,
"PCA9555 备用脚 IO0_7 / IO1_5~7 直接接地（上电默认即输入），",
0,
12
],
[
45,
154,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
142,
"DAC 地址：U6 = 0x4A（A0->SDA），U7 = 0x4B（A0->SCL）。",
0,
12
],
[
45,
130,
"FBx 必须接回 OUTx；CAP 接 2.2uF 到 AGND；VREF 空置时",
0,
12
],
[
45,
118,
"100nF 到地 + 10k 上拉 VDD。内部基准 1.212V x2 = 2.424V。",
0,
12
],
[
45,
806,
"【A】74HC595 ×3 的前两片（U21 / U22）—— 侧键驱动 + HUB_RST",
0,
12
],
[
45,
795,
"链序 U21 → U22 → U33（在 P6-FAN-EDL），SR_CAS / SR_CAS2 级联，整条链 24 位；",
0,
12
],
[
45,
784,
"SRCLK / RCLK / OE# 三片共用，OE# 上拉 100k ⇒ ESP32 复位期间 24 路输出全部高阻。",
0,
12
],
[
445,
790,
"【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
0,
12
],
[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
0,
12
],
[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
205,
"【C】DAC63204 ×2 —— 5 路调压（U6 = 0x4A / A0→SDA，U7 = 0x4B / A0→SCL）",
0,
12
],
[
45,
190,
"三处 datasheet 强制要求，图上看不出来但接错就出问题：",
0,
12
],
[
45,
178,
" 1) FBx 必须接回 OUTx —— 电压输出模式下这是运放的闭环反馈",
0,
12
],
[
45,
167,
" 2) CAP 接 2.2uF 到 AGND（内部 LDO 旁路，允许 0.5~15uF）",
0,
12
],
[
45,
156,
" 3) VREF 不用外部基准时要 100nF 到地 + 10k 上拉到 VDD",
0,
12
],
[
45,
145,
"内部基准 1.212V，增益 2x -> 满量程 2.424V（不是 2.5V）",
0,
12
],
[
45,
130,
"通道 2026-09-06 按 PCB 几何重排（§26.18）：U6 = VDAC2 / VDAC4 / VDAC1（都去西半板），",
0,
12
],
[
45,
119,
"U7 = VDAC3 / VDAC5（都去东半板）。四个通道完全对等，改的只是固件里的通道号。",
0,
12
],
[
45,
806,
"【A】74HC595 ×3 的前两片（U21 / U22）",
0,
12
],
[
45,
795,
"链序 U21 → U22 → U33（在 P6），整条链 24 位；",
0,
12
],
[
45,
784,
"SRCLK/RCLK/OE# 三片共用，OE# 上拉 100k ⇒ 复位全高阻",
0,
12
],
[
445,
790,
"【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
0,
12
],
[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
0,
12
],
[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
205,
"【C】DAC63204 ×2 —— 5 路调压",
0,
12
],
[
45,
194,
"U6 = 0x4A（A0→SDA），U7 = 0x4B（A0→SCL）",
0,
12
],
[
45,
180,
"三处 datasheet 强制要求，接错也不报错：",
0,
12
],
[
45,
169,
" 1) FBx 必须接回 OUTx（电压模式的闭环反馈）",
0,
12
],
[
45,
158,
" 2) CAP 接 2.2uF 到 AGND（LDO 旁路 0.5~15uF）",
0,
12
],
[
45,
147,
" 3) VREF 空置时 100nF 到地 + 10k 上拉 VDD",
0,
12
],
[
45,
136,
"内部基准 1.212V，×2 -> 满量程 2.424V（不是 2.5V）",
0,
12
],
[
45,
122,
"通道按几何重排（§26.18）：U6 = VDAC2/4/1（去西半板），",
0,
12
],
[
45,
111,
"U7 = VDAC3/5（去东半板）。四通道对等，只改固件通道号。",
0,
12
],
[
45,
806,
"【A】（已搬走）74HC595 ×3 与 15 颗按键 MOS 2026-09-06 整窝挪到载板",
0,
12
],
[
45,
795,
"（载板 C6-KEYS / C4-SITEn，§26.23）。KEY_SER/SRCLK/RCLK/OE#",
0,
12
],
[
45,
784,
"四根线从 P3 的 ESP32 直接去 P5-BTB 的 J25 北排 3~6 行。",
0,
12
],
[
445,
790,
"【B】PCA9555 输入扩展 —— 地址 0x20（A0/A1/A2 全接地）",
0,
12
],
[
445,
779,
"IO0_7 与 IO1_5~7 备用脚直接接地：上电默认即输入，",
0,
12
],
[
445,
768,
"固件严禁把 Port0[7] / Port1[7:5] 配成输出。",
0,
12
],
[
45,
205,
"【C】DAC63204 ×2 —— 5 路调压",
0,
12
],
[
45,
194,
"U6 = 0x4A（A0→SDA），U7 = 0x4B（A0→SCL）",
0,
12
],
[
45,
180,
"三处 datasheet 强制要求，接错也不报错：",
0,
12
],
[
45,
169,
" 1) FBx 必须接回 OUTx（电压模式的闭环反馈）",
0,
12
],
[
45,
158,
" 2) CAP 接 2.2uF 到 AGND（LDO 旁路 0.5~15uF）",
0,
12
],
[
45,
147,
" 3) VREF 空置时 100nF 到地 + 10k 上拉 VDD",
0,
12
],
[
45,
136,
"内部基准 1.212V，×2 -> 满量程 2.424V（不是 2.5V）",
0,
12
],
[
45,
122,
"通道按几何重排（§26.18）：U6 = VDAC2/4/1（去西半板），",
0,
12
],
[
45,
111,
"U7 = VDAC3/5（去东半板）。四通道对等，只改固件通道号。",
0,
12
]
],
"nRect": 0,
"nPoly": 0
}
在新工单中引用 查看 Git Blame 复制永久链接