R2：底板 / 刀片布局布线脚本、快照、截图与规划文档更新（含外壳、打印件、布线归档）
Co-Authored-By: Claude Opus 5.5 <[email protected]>
这个提交包含在：
zhou yang
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# -*- coding: utf-8 -*-
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u"""R2 底板：把 PCB 元件的 uniqueId 按位号对齐到原理图（skill §9o-2，照搬 `.claude/pcb1_uid_sync.py`）。
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/c/Python314/python .claude/r2/uid_sync_base.py # 只对账，不动板
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/c/Python314/python .claude/r2/uid_sync_base.py --push # 两阶段写回 + 存盘 + 回查
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为什么要有：A4-HUB 页整页重画（`a4_hub.py --push`）后原理图元件 uuid / uniqueId 全新，
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「从原理图导入变更」按 uniqueId 配对 ⇒ 那一页 31 件全变成「移除 + 增加」（2026-09-10 实测），
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应用下去整窝 Hub 会被删掉重建、摆位归零。对齐之后对话框只剩真实差异（新增件 + 改网络）。
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写之前把 PCB 侧旧 uniqueId 存到 `_base_uid_pre_sync.json`（只改这一个字段，这份就是快照）。
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⚠ DRC / 几何 / 连通性都看不出这一步错没错，唯一验收是重开导入对话框看剩几条。
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"""
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import io
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import json
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import os
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import sys
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sys.stdout.reconfigure(encoding='utf-8')
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HERE = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, os.path.dirname(HERE))
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from eda import run # noqa: E402
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U = json.load(io.open(os.path.join(HERE, 'r2-uuids.json'), encoding='utf-8'))
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# `--blade` 对刀片做同一件事（2026-09-11：B4-EDGE / B3B-USB 整页重画后，导入对话框同样错开一格）
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BOARD = 'BLADE' if '--blade' in sys.argv else 'BASE'
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PCB = U['boards'][BOARD]['pcb']['uuid']
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PAGES = U['boards'][BOARD]['pages']
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SNAP = os.path.join(HERE, '_%s_uid_pre_sync.json' % BOARD.lower())
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# 导入对话框若还开着（`pcb_import.py --probe` 不关它），先点「取消」再动板。
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CLOSE_DLG = u"""
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for (const b of document.querySelectorAll('button'))
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if (b.offsetParent !== null && (b.innerText||'').trim() === '取消') {
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const o={bubbles:true,cancelable:true,view:window,button:0};
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for (const t of ['pointerdown','mousedown','pointerup','mouseup','click'])
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b.dispatchEvent(new (t.startsWith('pointer')?PointerEvent:MouseEvent)(t,o));
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await new Promise(r => setTimeout(r, 800));
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}
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"""
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JS_PCB = CLOSE_DLG + u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 2000));
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const o = {};
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for (const c of await eda.pcb_PrimitiveComponent.getAll())
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o[c.getState_Designator()] = c.getState_UniqueId() || '';
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return o;
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""" % PCB
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JS_SCH = u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 1500));
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const cur = await eda.dmt_Schematic.getCurrentSchematicPageInfo();
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const o = {};
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for (const c of await eda.sch_PrimitiveComponent.getAll()) {
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if (c.getState_ComponentType() !== 'part') continue;
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if (c.getState_AddIntoPcb && c.getState_AddIntoPcb() === false) continue;
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o[c.getState_Designator()] = c.getState_UniqueId() || '';
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}
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return {page: cur.name, uids: o};
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"""
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def call(js, timeout=300):
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r = run(js, timeout=timeout)
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if not r.get('success'):
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raise RuntimeError(json.dumps(r, ensure_ascii=False)[:1200])
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return r['result']
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def collect():
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pcb = call(JS_PCB)
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sch = {}
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for name, uuid in sorted(PAGES.items()):
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r = call(JS_SCH % uuid)
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if str(r['page']).upper() != name.upper():
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raise RuntimeError(u'openDocument 打到了 %s（要 %s）' % (r['page'], name))
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for d, u in r['uids'].items():
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if d in sch:
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print(u' ⚠️ 位号 %s 在多页出现（%s）' % (d, r['page']))
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sch[d] = u
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return pcb, sch
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def main():
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push = '--push' in sys.argv
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pcb, sch = collect()
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print(u'PCB %d 件 / 原理图 %d 件' % (len(pcb), len(sch)))
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only_pcb = sorted(set(pcb) - set(sch))
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only_sch = sorted(set(sch) - set(pcb))
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if only_pcb:
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print(u'⚠️ PCB 有原理图没有 %d: %s' % (len(only_pcb), only_pcb))
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if only_sch:
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print(u' 原理图有 PCB 没有 %d（等导入新增）: %s' % (len(only_sch), ' '.join(only_sch)))
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diff = {d: (pcb[d], sch[d]) for d in sorted(set(pcb) & set(sch)) if pcb[d] != sch[d]}
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print(u'\n通道ID 对不上的：%d / %d' % (len(diff), len(set(pcb) & set(sch))))
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for d, (a, b) in diff.items():
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print(u' %-6s PCB=%-10s 原理图=%-10s' % (d, a or '(空)', b or '(空)'))
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if not diff:
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print(u'\n✅ 全部一致，导入对话框应当只报真实差异。')
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return
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tgt = {}
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for d, (_a, b) in diff.items():
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tgt.setdefault(b, []).append(d)
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dup = {k: v for k, v in tgt.items() if len(v) > 1 or not k}
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if dup:
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sys.exit(u'⛔ 目标 uniqueId 撞车 / 为空，不能自动修：%s' % dup)
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# 目标值不能和板上**不改的**件撞号。
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# ⚠ 「PCB 有、原理图没有」的件（导入时要删的，如 2026-09-11 刀片的 J2）不算：它们占着的号
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# 正是错位那一串要用的（J2 = gge74 = J4 的目标）。同一次写入里把它们挪到 `zzdel_<位号>`，
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# 原理图里不可能有这个号，导入对话框照样把它们报成「移除元件」。
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keep = {pcb[d]: d for d in pcb if d not in diff and d not in only_pcb and pcb[d]}
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clash = {b: (d, keep[b]) for d, (_a, b) in diff.items() if b in keep}
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if clash:
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sys.exit(u'⛔ 目标 uniqueId 与板上不改的件撞号：%s' % clash)
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if not push:
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print(u'\n加 --push 写回（两阶段：先临时 ID 再目标 ID，避免中途重号）')
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return
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io.open(SNAP, 'w', encoding='utf-8').write(json.dumps(pcb, ensure_ascii=False, indent=0))
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print(u'已存旧 uniqueId 快照 %s' % os.path.basename(SNAP))
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plan = [[d, b] for d, (_a, b) in sorted(diff.items())]
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plan += [[d, 'zzdel_' + d] for d in only_pcb]
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r = call(CLOSE_DLG + u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 2000));
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const PLAN = %s;
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const by = {};
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for (const c of await eda.pcb_PrimitiveComponent.getAll()) by[c.getState_Designator()] = c;
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let n1 = 0, n2 = 0;
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for (let i = 0; i < PLAN.length; i++) {
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const c = by[PLAN[i][0]];
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if (!c) continue;
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c.toAsync().setState_UniqueId('zzsync' + i).done();
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n1++;
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}
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for (const [des, uid] of PLAN) {
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const c = by[des];
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if (!c) continue;
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c.toAsync().setState_UniqueId(uid).done();
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n2++;
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}
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await eda.pcb_Document.save();
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return {n1, n2};
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""" % (PCB, json.dumps(plan)))
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print(u'\n两阶段写入：临时 %d / 目标 %d，已存盘' % (r['n1'], r['n2']))
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pcb2, sch2 = collect()
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left = {d: (pcb2[d], sch2[d]) for d in sorted(set(pcb2) & set(sch2)) if pcb2[d] != sch2[d]}
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if left:
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print(u'⛔ 回查还有 %d 个对不上：' % len(left))
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for d, (a, b) in left.items():
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print(u' %-6s PCB=%-10s 原理图=%s' % (d, a or '(空)', b or '(空)'))
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sys.exit(1)
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seen = {}
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for d, u in pcb2.items():
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if u:
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seen.setdefault(u, []).append(d)
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dup2 = {k: v for k, v in seen.items() if len(v) > 1}
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if dup2:
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sys.exit(u'⛔ PCB 上出现重号：%s' % dup2)
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print(u' ✔ 回查：%d 个元件的通道ID 与原理图逐个一致，且无重号' % len(pcb2))
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print(u'\n接着重开导入对话框核对：pcb_import.py --base --probe')
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if __name__ == '__main__':
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main()
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