R2：底板 / 刀片布局布线脚本、快照、截图与规划文档更新（含外壳、打印件、布线归档）
Co-Authored-By: Claude Opus 5.5 <[email protected]>
这个提交包含在：
zhou yang
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# -*- coding: utf-8 -*-
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u"""P1-INPUT：把 12V 输入座 `J1` 从 XT30PW-M 换成**圆形 DC 电源座** DC-005-5.5*2.5。
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/c/Python314/python .claude/p1_dcjack.py # 干跑，只打印计划
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/c/Python314/python .claude/p1_dcjack.py --push # 执行 + 存盘
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用户 2026-09-08 拍板：换圆座、**不降载**，接受插座超额定运行。
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## ⛔ 这颗件是全板唯一一处「明知超额定还要装」的地方
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整机 12V 最坏工况 **9.99 A**（设计文档 §22.6），而 DC-005 家族的额定是
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**2~5 A**（立创同族 XKB `DC-005-2.5A-2.5` = C319098 官方标 2.5 A）。
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发热点在**插头内芯与插座弹片的接触面**，不在板上的铜 —— 板子这边再加强也救不了那一处。
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⇒ 这不是「算过没问题」，是**已知风险、用户明确接受**。设计文档 §1 / §22.6 要同步写明。
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## 引脚定义（查过三处，两处互相印证）
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| 脚 | 含义 | 本设计接法 |
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|---|---|---|
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| 1 | 中心极，**正** | `VIN_RAW` → F1.1 |
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| 2 | 负极**静触点**（无插头时与 3 短接）| GND |
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| 3 | 负极**动触点**（插头外壳压这一片）| GND |
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**2 和 3 一起接地**，理由两条：
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1. **安全**：不同厂家对「哪一片是常驻外壳极」的叫法不一致 —— 有的把 2 当外壳、
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有的把 3 当外壳。两个都接地就与这个分歧无关，且**两者都是负极侧**，
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无论如何接不出「插拔瞬间把适配器正极对地短路」这种事故。
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（反过来，若把 3 当成「开关信号」接到别处，一旦它其实是外壳极，回流路径就断了。）
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2. **正好帮到超额定**：两个负极触点**并联分流**，接触电阻减半、发热减半。
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这是本轮唯一一处能在板端缓解 10 A 问题的地方。
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⚠️ 装配前用万用表核一次：无插头时 2-3 应导通、1 对 2/3 应断开。
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## 版面（原理图单位 0.01 inch，Y 向上，坐标一律 5 的倍数）
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元件放 `(110, 700)` rot 0 —— 该符号 rot 0 时三个脚都在**右侧** `+30`：
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pin1 (+) (140, 710) → 复用原有导线 [250,710 → 140,710] 到 F1.1
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pin3 (−) (140, 700) → [140,700 → 185,700 → 185,665] → 地旗 (185,665)
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pin2 (−) (140, 690) → [140,690 → 140,655] → 原有地旗 (140,655)
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⚠️ 原来那条地线 `[140,700 → 140,655]` **必须删掉**：新符号的 pin2 落在 (140,690)
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正好在它中间，而 §8b「导线在元件引脚处被截断」会把它劈成两段，
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接出来的东西看着连着、实际是断的。
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"""
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import io
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import json
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import os
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import sys
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HERE = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, HERE)
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from eda import run
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PAGE = '9a6096762e036e23' # P1-INPUT
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LIB = '0819f05c4eef4c71ace90d822a990e87'
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DEV = '66ed565d4c984ace901de00bbc83af82' # DC-005-5.5*2.5，立创 C9900017043
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CX, CY = 110, 700 # 新 J1 的中心
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PIN = {'1': (140, 710), '3': (140, 700), '2': (140, 690)} # rot 0 时的绝对坐标
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# 新画的导线（扁平数组，见 §4）
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WIRES = [
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[140, 690, 140, 655], # pin2 -> 原有地旗
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[140, 700, 185, 700, 185, 665], # pin3 -> 新地旗
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]
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# 新建的旗：(kind, net, x, y, rot)
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FLAGS = [('Ground', 'GND', 185, 665, 0)]
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def _seg(a, b, c, d):
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u"""一段导线的规范化键 —— 两端顺序无关（`getState_Line()` 会把两端反过来，§5）。"""
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return ','.join(str(v) for v in min((a, b, c, d), (c, d, a, b)))
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def _mine():
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u"""本脚本负责的那几段线（把折线拆成段）。"""
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out = set()
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for w in WIRES:
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for i in range(0, len(w) - 3, 2):
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out.add(_seg(w[i], w[i + 1], w[i + 2], w[i + 3]))
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return out
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def call(js, timeout=240):
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r = run(js, timeout=timeout)
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if not r.get('success'):
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raise RuntimeError(json.dumps(r, ensure_ascii=False)[:1200])
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return r['result']
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def selfcheck():
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u"""下发前的本地几何自检（§6d / §8a-2b）。"""
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for w in WIRES:
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assert len(w) % 2 == 0 and len(w) >= 4, u'导线点数不对: %s' % (w,)
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for v in w:
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assert v % 5 == 0, u'导线坐标不是 5 的倍数: %s' % (w,)
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for i in range(0, len(w) - 2, 2):
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ax, ay, bx, by = w[i], w[i + 1], w[i + 2], w[i + 3]
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assert (ax == bx) != (ay == by), u'不是横平竖直或零长度: %s' % ((ax, ay, bx, by),)
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for _k, _n, x, y, _r in FLAGS:
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assert x % 5 == 0 and y % 5 == 0, u'旗坐标不是 5 的倍数'
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# 每条导线的起点都必须落在某个引脚上，否则就是算错了位置
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starts = {(w[0], w[1]) for w in WIRES}
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assert starts == {PIN['2'], PIN['3']}, u'导线起点和引脚对不上: %s' % (starts,)
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print(u'本地自检通过：%d 条导线 / %d 个旗，坐标全是 5 的倍数、横平竖直' % (len(WIRES), len(FLAGS)))
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JS_SURVEY = u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 1500));
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const cur = await eda.dmt_Schematic.getCurrentSchematicPageInfo();
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if (cur.name !== 'P1-INPUT') return {err: 'wrong page: ' + cur.name};
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const out = {page: cur.name, parts: [], wires: [], flags: []};
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for (const c of await eda.sch_PrimitiveComponent.getAll()) {
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const t = c.getState_ComponentType();
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const pid = c.getState_PrimitiveId();
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const x = c.getState_X(), y = c.getState_Y();
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if (t === 'part') {
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const nm = (c.getState_Component() || {}).name || '';
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if (c.getState_Designator() === 'J1' || nm.indexOf('DC-005') === 0)
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out.parts.push({pid, des: c.getState_Designator(), nm, x, y, rot: c.getState_Rotation()});
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} else if (t === 'netflag' && x < 320 && y > 590 && y < 820) {
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out.flags.push({pid, net: c.getState_Net(), x, y, rot: c.getState_Rotation()});
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}
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}
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for (const w of await eda.sch_PrimitiveWire.getAll()) {
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const pts = w.getState_Line();
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const xs = pts.filter((_, i) => i %% 2 === 0), ys = pts.filter((_, i) => i %% 2 === 1);
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if (Math.min(...xs) > 320 || Math.max(...ys) < 590 || Math.min(...ys) > 820) continue;
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out.wires.push({pid: w.getState_PrimitiveId(), pts});
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}
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return out;
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""" % PAGE
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def survey():
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s = call(JS_SURVEY)
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if s.get('err'):
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sys.exit(s['err'])
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return s
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def main():
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push = '--push' in sys.argv
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selfcheck()
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s = survey()
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print(u'\n当前 P1-INPUT 上：')
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for p in s['parts']:
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print(u' 元件 %-4s %-18s (%d,%d) rot %s %s' % (p['des'], p['nm'], p['x'], p['y'], p['rot'], p['pid']))
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for f in s['flags']:
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print(u' 旗 %-6s (%d,%d) rot %s %s' % (f['net'], f['x'], f['y'], f['rot'], f['pid']))
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for w in s['wires']:
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print(u' 导线 %s %s' % (w['pid'], w['pts']))
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old_j1 = [p for p in s['parts'] if p['des'] == 'J1' and p['nm'].find('DC-005') != 0]
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dcs = [p for p in s['parts'] if p['nm'].find('DC-005') == 0]
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# 那条要删的地线：起点/终点里同时出现 (140,700) 和 (140,655)
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gnd_old = [w for w in s['wires']
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if [140, 700] == w['pts'][:2] or [140, 700] == w['pts'][-2:]]
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print(u'\n计划：')
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print(u' 删 旧 J1（XT30） %d 个' % len(old_j1))
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print(u' 删 旧地线 [140,700→140,655] %d 条' % len(gnd_old))
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print(u' 留 现有 DC-005 实例 %d 个（多余的删掉，留一个 rot 0 的改名 J1）' % len(dcs))
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print(u' 新建导线 %d 条 / 地旗 %d 个' % (len(WIRES), len(FLAGS)))
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if not push:
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print(u'\n加 --push 执行')
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return
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keep = None
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for p in dcs:
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if p['rot'] == 0 and keep is None:
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keep = p
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if keep is None:
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sys.exit(u'⛔ 页面上没有 rot 0 的 DC-005 实例 —— 先手动 create 一个再跑')
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drop = [p['pid'] for p in dcs if p['pid'] != keep['pid']] + [p['pid'] for p in old_j1]
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r = call(u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 1500));
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const cur = await eda.dmt_Schematic.getCurrentSchematicPageInfo();
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if (cur.name !== 'P1-INPUT') return {err: 'wrong page: ' + cur.name};
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const DROP = %s, WDROP = %s;
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let nd = 0, nw = 0;
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for (const id of DROP) { try { await eda.sch_PrimitiveComponent.delete(id); nd++; } catch (e) {} }
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for (const id of WDROP) { try { await eda.sch_PrimitiveWire.delete(id); nw++; } catch (e) {} }
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// 留下来的那颗：挪到位、改位号。**只动 x/y，不动 rotation**（§6b）
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const all = await eda.sch_PrimitiveComponent.getAll();
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const k = all.find(c => c.getState_PrimitiveId() === '%s');
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if (!k) return {err: 'kept component vanished'};
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await k.toAsync().setState_X(%d).setState_Y(%d).setState_Designator('J1').done();
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return {nd, nw};
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""" % (PAGE, json.dumps(drop), json.dumps([w['pid'] for w in gnd_old]),
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keep['pid'], CX, CY))
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if r.get('err'):
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sys.exit(r['err'])
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print(u'\n删元件 %d / 删导线 %d，已把 %s 挪到 (%d,%d) 并改名 J1'
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% (r['nd'], r['nw'], keep['pid'], CX, CY))
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# ⚠️ 挪完必须读回引脚，不能按偏移量推（§6c / §8d）
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pins = call(u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 1200));
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for (const c of await eda.sch_PrimitiveComponent.getAll()) {
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if (c.getState_ComponentType() !== 'part') continue;
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if (c.getState_Designator() !== 'J1') continue;
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const o = {};
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for (const p of await c.getAllPins())
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o[p.getState_PinNumber()] = [p.getState_X(), p.getState_Y()];
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return {x: c.getState_X(), y: c.getState_Y(), rot: c.getState_Rotation(),
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nm: (c.getState_Component() || {}).name, pins: o};
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}
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return null;""" % PAGE)
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print(u'回读 J1：%s (%s,%s) rot %s 引脚 %s'
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% (pins['nm'], pins['x'], pins['y'], pins['rot'], pins['pins']))
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for n, (ex, ey) in PIN.items():
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got = pins['pins'].get(n)
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assert got and got[0] == ex and got[1] == ey, \
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u'⛔ J1.%s 落在 %s，期望 (%d,%d) —— 方向或位置不对，导线先别画' % (n, got, ex, ey)
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print(u' ✔ 三个引脚坐标与计划逐个对上')
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r2 = call(u"""
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await eda.dmt_EditorControl.openDocument('%s');
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await new Promise(r => setTimeout(r, 1200));
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// ⚠️ 幂等：重跑时先删掉本脚本画过的导线和地旗，否则会叠一层
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// （§9v：只加不删的脚本不幂等；重叠的细线还会被 EasyEDA 并进旧线里，看着像"没生效"）
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// ⚠️⚠️ 比对必须按**线段集合**，不能按 getState_Line() 的原数组：
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// 它返回的是端点对（§5），而且两端顺序会反过来 —— 按数组比一条都匹配不上，
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// 于是"清理"静默落空、每跑一次多画一份。
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const W = %s, F = %s;
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const seg = (a, b, c, d) => [a, b, c, d] < [c, d, a, b] ? [a, b, c, d].join(',') : [c, d, a, b].join(',');
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const mine = new Set();
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for (const w of W)
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for (let i = 0; i + 3 < w.length; i += 2) mine.add(seg(w[i], w[i+1], w[i+2], w[i+3]));
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let nrm = 0;
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for (const w of await eda.sch_PrimitiveWire.getAll()) {
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const p = w.getState_Line();
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let all = p.length >= 4, any = false;
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for (let i = 0; i + 3 < p.length; i += 4) { // 端点对：每 4 个数一段
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const s = seg(p[i], p[i+1], p[i+2], p[i+3]);
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if (mine.has(s)) any = true; else all = false;
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}
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if (all && any) { await eda.sch_PrimitiveWire.delete(w.getState_PrimitiveId()); nrm++; }
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}
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for (const c of await eda.sch_PrimitiveComponent.getAll())
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if (c.getState_ComponentType() === 'netflag')
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for (const f of F)
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if (c.getState_X() === f[2] && c.getState_Y() === f[3]) {
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await eda.sch_PrimitiveComponent.delete(c.getState_PrimitiveId()); nrm++;
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}
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let nw = 0, nf = 0;
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for (const w of W) { await eda.sch_PrimitiveWire.create(w); nw++; }
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for (const f of F) { await eda.sch_PrimitiveComponent.createNetFlag(f[0], f[1], f[2], f[3], f[4], false); nf++; }
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// 原理图存盘是 sch_Document.save()，不是 dmt_EditorControl.save()（后者不存在）
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const saved = await eda.sch_Document.save();
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return {nw, nf, nrm, saved};
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""" % (PAGE, json.dumps(WIRES), json.dumps(FLAGS)))
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print(u'清掉重跑残留 %d 个；新建导线 %d 条 / 地旗 %d 个，save() 返回 %s'
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% (r2['nrm'], r2['nw'], r2['nf'], r2['saved']))
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# §9ad：save() 的返回值不算数，回读一遍才是落盘的证据。
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# ⚠️ 按**线段集合**比，不是按数组：getState_Line() 回来的是端点对，顺序还会反（§5）。
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back = survey()
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got = set()
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for w in back['wires']:
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p = w['pts']
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for i in range(0, len(p) - 3, 4):
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got.add(_seg(p[i], p[i + 1], p[i + 2], p[i + 3]))
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dup = sum(1 for w in back['wires']
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for i in range(0, len(w['pts']) - 3, 4)
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if _seg(*w['pts'][i:i + 4]) in _mine())
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for s in sorted(_mine()):
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assert s in got, u'⛔ 导线没落盘: %s' % (s,)
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assert dup == len(_mine()), u'⛔ 本脚本的线在板上有 %d 段，应该是 %d 段（重复了）' % (dup, len(_mine()))
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got_f = {(f['net'], f['x'], f['y']) for f in back['flags']}
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for _k, n, x, y, _r in FLAGS:
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assert (n, x, y) in got_f, u'⛔ 地旗没落盘: %s (%d,%d)' % (n, x, y)
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print(u' ✔ 回读确认：%d 段导线（无重复）+ %d 个地旗都在盘上' % (len(_mine()), len(FLAGS)))
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print(u'\n接着跑：verify_sch.py --nets → port_audit.py --board Board1 → xpage.py')
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if __name__ == '__main__':
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main()
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在新工单中引用
屏蔽一个用户