kicad：EasyEDA→KiCad 工程（Board1/Board2）、库、脚本与评审文档（IC 引脚、风扇、热、EDL 供电、布局规则）
Co-Authored-By: Claude Opus 5.5 <[email protected]>
这个提交包含在：
zhou yang
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"""Install explicit net classes and the R2 routing contract without altering nets."""
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import json
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import re
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import shutil
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import pcbnew as pcb
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from optimize_pcb_layout import ROOT, OUT, digest
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def main():
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contract = {
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'revision':'R2',
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'direction':{'F.Cu':'horizontal','B.Cu':'vertical',
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'max_transverse_escape_mm':2.0,
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'exceptions':[],
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'policy':'Long transverse/diagonal tracks require explicit reviewed UUID exceptions; copper zones are exempt'},
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'stackup_status':'PRELIMINARY_FABRICATOR_CONFIRMATION_REQUIRED',
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'usb':{'target_ohms':90,'tolerance_percent':10,'width_mm':.28,'gap_mm':.18,
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'max_pair_skew_mm':.5,'max_uncoupled_mm':5,'max_vias_per_leg':2,
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'pair_names_native_recognized':False,
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'reference_policy':'F.Cu requires uninterrupted In1.Cu GND; B.Cu requires uninterrupted In2.Cu GND. Reserve local GND corridors in the nominal power layer before changing signal layers',
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'max_return_via_distance_mm':1.0},
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'power':{'input_design_continuous_A':10,'input_fuse_A':12,'phone_channel_A':4,
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'main_bus_preferred_width_mm':6,'main_bus_min_trunk_mm':4,
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'phone_preferred_width_mm':2,'phone_min_trunk_mm':1.5,
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'max_narrow_escape_mm':2,'via_drill_mm':.3,'via_diameter_mm':.6,
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'phone_parallel_vias_min':6,'input_parallel_vias_min':12,
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'note':'Starting geometry only: qualify current, voltage drop, thermal rise and via plating with board house'},
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'placement':{'min_body_spacing_mm':.35,'battery_bulk_lower_projection_margin_mm':1,
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'max_buck_vin_cap_pin_distance_mm':5,'max_bootstrap_pin_distance_mm':5,
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'max_feedback_pin_distance_mm':5,'max_shunt_ina_pin_distance_mm':10,
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'max_crystal_pin_distance_mm':7,'max_hub_bypass_pin_distance_mm':5,
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'height_gap_mm':13,'height_status':'Bulk-cap projections reserved; remaining component heights unverified'},
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'boards':{},
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}
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for n in (1,2):
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name = f'PhoneRail-Board{n}'
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path = ROOT/name/(name+'.kicad_pro')
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project = json.loads(path.read_text(encoding='utf-8'))
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source = OUT / ('rules-input-'+name+'.kicad_pcb')
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shutil.copy2(path.with_suffix('.kicad_pcb'),source)
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b = pcb.LoadBoard(str(source))
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parts = {f.GetReference():f for f in b.GetFootprints()}
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def net(ref,pin):
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return next(p.GetNetname() for p in parts[ref].Pads() if p.GetNumber()==str(pin))
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nets = {p.GetNetname() for f in b.GetFootprints() for p in f.Pads() if p.GetNetname()}
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mapping = {s:'Default' for s in nets}
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usb_pairs = [('USB_DP','USB_DM')] if n == 1 else [('UP_DP','UP_DM')]+[
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(f'USB{ch}_DP{suffix}',f'USB{ch}_DM{suffix}') for ch in range(1,6) for suffix in ('','J')]
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for plus,minus in usb_pairs:
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assert plus in nets and minus in nets
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mapping[plus] = mapping[minus] = 'USB90'
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for s in nets:
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if s in {'SCL','SDA','INA_ALERT'}:
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mapping[s] = 'I2C'
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elif s.startswith('VDAC') or s.startswith('NTC'):
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mapping[s] = 'ANALOG'
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elif re.fullmatch(r'VO[1-5](_P)?',s):
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mapping[s] = 'PWR4A'
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elif s == '+5V' or re.fullmatch(r'VBUS[1-5]',s):
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mapping[s] = 'PWR5V'
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elif s.startswith('+3V3') or s in {'VDD18','VDD18PLL'}:
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mapping[s] = 'PWR3V3'
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elif s == '+12V':
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mapping[s] = 'PWR12V'
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elif 'FAN_12V_SW' in s:
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mapping[s] = 'FAN_PWR'
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if n == 1:
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for ref,pin in [('J1',2),('F1',2),('Q1',5)]:
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mapping[net(ref,pin)] = 'PWR12V'
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for ch in range(1,6):
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mapping[net(f'U{ch}',11)] = 'SWITCH'
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mapping[net(f'U{ch}',7)] = 'FEEDBACK'
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mapping[net(f'U{ch}',8)] = 'FEEDBACK'
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mapping[net(f'U{ch+13}',4)] = 'PWR4A'
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for pin in (15,17,18,19):
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mapping[net(f'U{ch+13}',pin)] = 'ANALOG'
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for ref in ('U19','U30'):
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mapping[net(ref,2)] = 'SWITCH'
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mapping[net(ref,4)] = 'FEEDBACK'
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else:
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for s in ('XTAL1','XTAL2','RBIAS'):
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mapping[s] = 'CLOCK_LOCAL'
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net_settings = project['net_settings']
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base = dict(next(c for c in net_settings['classes'] if c['name']=='Default'))
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base.update(clearance=.15,track_width=.25,via_diameter=.6,via_drill=.3,
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diff_pair_width=.28,diff_pair_gap=.18,diff_pair_via_gap=.25)
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classes = [('Default',.25,.15),('USB90',.28,.15),('I2C',.25,.15),('ANALOG',.2,.15),
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('FEEDBACK',.2,.15),('CLOCK_LOCAL',.2,.15),('SWITCH',1,.15),
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('PWR4A',2,.2),('PWR5V',1,.2),('PWR12V',4,.2),('FAN_PWR',1.2,.2),('PWR3V3',.5,.15)]
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net_settings['classes'] = [dict(base,name=c,track_width=w,clearance=gap) for c,w,gap in classes]
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# Use exact escaped net names; patterns cannot accidentally capture BOOT/FB.
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net_settings['netclass_assignments'] = {k:[v] for k,v in sorted(mapping.items()) if v!='Default'}
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net_settings['netclass_patterns'] = [{'pattern':k,'netclass':v} for k,v in sorted(mapping.items()) if v!='Default']
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ds = project['board']['design_settings']
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ds['rules'].update(min_clearance=.127,min_track_width=.127,min_via_diameter=.6,
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min_through_hole_diameter=.3,min_hole_to_hole=.25,
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min_via_annular_width=.15,min_copper_edge_clearance=.3,
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min_connection=.2,solder_mask_clearance=.05,solder_mask_min_width=.1)
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ds['track_widths'] = [0,.15,.2,.25,.28,.5,1,1.2,1.5,2,3,4,6]
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ds['via_dimensions'] = [{'diameter':0,'drill':0},{'diameter':.6,'drill':.3},{'diameter':.8,'drill':.4}]
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ds['diff_pair_dimensions'] = [{'width':0,'gap':0,'via_gap':0},{'width':.28,'gap':.18,'via_gap':.25}]
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ds['defaults']['zones'].update(min_clearance=.2,min_thickness=.2,thermal_relief_gap=.25,
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thermal_relief_spoke_width=.4,min_island_area=5)
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path.write_text(json.dumps(project,indent=2,ensure_ascii=False)+'\n',encoding='utf-8')
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rules = '''(version 1)
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# F.Cu horizontal, B.Cu vertical. Direction and explicit pair checks:
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# scripts/verify_pcb_layout.py + pcb-routing-rules.json.
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# Net names are unchanged; DP/DM suffixes are not presumed native pairs.
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(rule "R2 inner layers reserved for reference and power zones"
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(condition "A.Layer == 'In1.Cu' || A.Layer == 'In2.Cu'")
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(constraint disallow track))
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(rule "R2 USB differential target - requires recognized pair"
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(condition "A.hasNetclass('USB90')")
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(constraint track_width (min 0.15mm) (opt 0.28mm) (max 0.30mm))
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(constraint diff_pair_gap (min 0.15mm) (opt 0.18mm) (max 0.21mm))
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(constraint diff_pair_uncoupled (max 5mm))
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(constraint skew (max 0.5mm)))
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(rule "R2 switch copper stays on component side with no vias"
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(condition "A.hasNetclass('SWITCH')")
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(constraint disallow via)
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(constraint length (max 12mm)))
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(rule "R2 feedback and oscillator do not change layers"
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(condition "A.hasNetclass('FEEDBACK') || A.hasNetclass('CLOCK_LOCAL')")
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(constraint disallow via)
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(constraint length (max 15mm)))
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(rule "R2 switch tracks isolated from sensitive nets"
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(condition "A.Type == 'Track' && A.hasNetclass('SWITCH') && (B.hasNetclass('FEEDBACK') || B.hasNetclass('ANALOG') || B.hasNetclass('USB90') || B.hasNetclass('CLOCK_LOCAL'))")
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(constraint clearance (min 0.5mm)))
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(rule "R2 ordinary vias stay outside SMD lands"
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(condition "A.Type == 'Via' && B.Type == 'Pad' && B.Pad_Type == 'SMD'")
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(constraint physical_clearance (min 0.1mm)))
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'''
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path.with_suffix('.kicad_dru').write_text(rules,encoding='utf-8')
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contract['boards'][name] = {'ground_reference_layer':'In1.Cu' if n==1 else 'In2.Cu',
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'power_zone_layer':'In2.Cu' if n==1 else 'In1.Cu',
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'usb_pairs':[{'positive':p,'negative':m} for p,m in usb_pairs], 'net_classes':mapping}
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(ROOT/'pcb-routing-rules.json').write_text(json.dumps(contract,indent=2)+'\n',encoding='utf-8')
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manifest = OUT/'placement.json'
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data = json.loads(manifest.read_text(encoding='utf-8'))
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# KiCad normalizes project JSON during schematic/DRC operations. Placement
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# protects the board and DRU files it can overwrite, not that mutable cache.
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data['generated_files'] = {k:v for k,v in data['generated_files'].items() if not k.endswith('.kicad_pro')}
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for n in (1,2):
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name = f'PhoneRail-Board{n}'
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for ext in ('.kicad_dru',):
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p = ROOT/name/(name+ext)
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data['generated_files'][str(p.relative_to(ROOT))] = digest(p)
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manifest.write_text(json.dumps(data,indent=2)+'\n',encoding='utf-8')
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print('R2 classes, native rules, explicit pair/direction contract installed')
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if __name__=='__main__':
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main()
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