kicad：EasyEDA→KiCad 工程（Board1/Board2）、库、脚本与评审文档（IC 引脚、风扇、热、EDL 供电、布局规则）

Co-Authored-By: Claude Opus 5.5 <[email protected]>

kicad/pcb2-usb-topology.json

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+{
+  "board": "PhoneRail-Board2",
+  "status": "TOPOLOGY_DEFINED_NOT_ROUTED",
+  "sequence": [
+    "upstream_usb",
+    "hub_crystal_and_decoupling",
+    "downstream_usb_pairs",
+    "hub_control",
+    "port_vbus",
+    "power_and_ground_planes"
+  ],
+  "reference_layers": {
+    "F.Cu": "In1.Cu continuous ground for USB where F.Cu is used",
+    "B.Cu": "In2.Cu continuous ground for USB where B.Cu is used"
+  },
+  "upstream": {
+    "path": ["J23", "USB_ESD", "U32"],
+    "layer": "B.Cu",
+    "max_connector_fanout_mm": 3.0,
+    "forbid_stubs": true
+  },
+  "downstream": {
+    "source": "U32",
+    "destinations": ["J31", "J32", "PHONE_PORT_3", "PHONE_PORT_4", "PHONE_PORT_5"],
+    "layer": "F.Cu",
+    "pair_length_mismatch_max_mm": 0.5,
+    "same_via_count": true
+  },
+  "power": {
+    "hub_3v3": "U32_each_supply_pin_to_local_decoupler_then_3V3_zone",
+    "vbus": "per_port_switch_output_to_local_connector",
+    "usb_ground_is_not_vbus_return": true
+  },
+  "review_gates": [
+    "verify_port_net_mapping",
+    "verify_reference_plane_continuity",
+    "verify_pair_skew_and_via_symmetry",
+    "verify_no_crossing_power_split",
+    "verify_return_via_within_1mm_of_signal_via"
+  ]
+}