kicad：EasyEDA→KiCad 工程（Board1/Board2）、库、脚本与评审文档（IC 引脚、风扇、热、EDL 供电、布局规则）

Co-Authored-By: Claude Opus 5.5 <[email protected]>

kicad/PhoneRail-Board2/PhoneRail-Board2.kicad_dru

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+(version 1)
+# F.Cu horizontal, B.Cu vertical. Direction and explicit pair checks:
+# scripts/verify_pcb_layout.py + pcb-routing-rules.json.
+# Net names are unchanged; DP/DM suffixes are not presumed native pairs.
+(rule "R2 inner layers reserved for reference and power zones"
+  (condition "A.Layer == 'In1.Cu' || A.Layer == 'In2.Cu'")
+  (constraint disallow track))
+(rule "R2 USB differential target - requires recognized pair"
+  (condition "A.hasNetclass('USB90')")
+  (constraint track_width (min 0.15mm) (opt 0.28mm) (max 0.30mm))
+  (constraint diff_pair_gap (min 0.15mm) (opt 0.18mm) (max 0.21mm))
+  (constraint diff_pair_uncoupled (max 5mm))
+  (constraint skew (max 0.5mm)))
+(rule "R2 switch copper stays on component side with no vias"
+  (condition "A.hasNetclass('SWITCH')")
+  (constraint disallow via)
+  (constraint length (max 12mm)))
+(rule "R2 feedback and oscillator do not change layers"
+  (condition "A.hasNetclass('FEEDBACK') || A.hasNetclass('CLOCK_LOCAL')")
+  (constraint disallow via)
+  (constraint length (max 15mm)))
+(rule "R2 switch tracks isolated from sensitive nets"
+  (condition "A.Type == 'Track' && A.hasNetclass('SWITCH') && (B.hasNetclass('FEEDBACK') || B.hasNetclass('ANALOG') || B.hasNetclass('USB90') || B.hasNetclass('CLOCK_LOCAL'))")
+  (constraint clearance (min 0.5mm)))
+(rule "R2 ordinary vias stay outside SMD lands"
+  (condition "A.Type == 'Via' && B.Type == 'Pad' && B.Pad_Type == 'SMD'")
+  (constraint physical_clearance (min 0.1mm)))