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初始导入：PhoneRail 五路手机直供电源板

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原理图/PCB 已在 EasyEDA 里做到 12 页跨页 0 漏接，固件刚完成骨架包 A1。
这次是把已有的一切一次性纳入版本控制，没有改动任何设计内容。

纳入：
- 设计与需求文档、PROGRESS.md、小米8 参考原理图 PDF 与追脚脚本
- .claude/ 下的 EasyEDA 桥接工具链与几何/网表缓存（eda-parts.json、
  pcb-parts.json、pcb-pads.json、p2-ch1.json 等，是重画各页的唯一事实来源）
- 117 张验证截图（本项目所有方向问题都是靠人眼看截图发现的，属于证据不是垃圾）
- firmware/ 的 A1 骨架与 site/ 文档站源码

.gitignore 排除：构建产物（firmware/build、host/build、sdkconfig）、
site/node_modules、__pycache__、桥接日志 _bridge.log、脚本自标的 *.stale。

.gitattributes 默认 `* -text`：现有 .py/.json 大多是 CRLF，原样存，
不让 git 重写行尾。唯一例外是 *.sh 强制 LF —— 带 \r 的 shell 脚本 bash 跑不了。

Co-Authored-By: Claude Opus 5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01QYuExfgyYa6DzRRcUso8M8
这个提交包含在：
zhou yang
2026-09-06 18:18:14 +08:00
共同撰写人 Claude Opus 5
当前提交 2bfe308b30
共修改 526 个文件，包含 80633 行新增和 0 行删除
下载 Patch 文件 下载 Diff 文件 展开所有文件 折叠所有文件
.claude/p3-pins.json
+495
查看文件
@@ -0,0 +1,495 @@
{
"U20": {
"1": [
295,
440,
"GND"
],
"2": [
205,
615,
"3V3"
],
"3": [
205,
605,
"EN"
],
"4": [
295,
760,
"IO4"
],
"5": [
295,
750,
"IO5"
],
"6": [
295,
740,
"IO6"
],
"7": [
295,
730,
"IO7"
],
"8": [
295,
650,
"IO15"
],
"9": [
295,
640,
"IO16"
],
"10": [
295,
630,
"IO17"
],
"11": [
295,
620,
"IO18"
],
"12": [
295,
720,
"IO8"
],
"13": [
295,
610,
"IO19"
],
"14": [
295,
600,
"IO20"
],
"15": [
295,
770,
"IO3"
],
"16": [
295,
490,
"IO46"
],
"17": [
295,
710,
"IO9"
],
"18": [
295,
700,
"IO10"
],
"19": [
295,
690,
"IO11"
],
"20": [
295,
680,
"IO12"
],
"21": [
295,
670,
"IO13"
],
"22": [
295,
660,
"IO14"
],
"23": [
295,
590,
"IO21"
],
"24": [
295,
480,
"IO47"
],
"25": [
295,
470,
"IO48"
],
"26": [
295,
500,
"IO45"
],
"27": [
295,
800,
"IO0"
],
"28": [
295,
580,
"IO35"
],
"29": [
295,
570,
"IO36"
],
"30": [
295,
560,
"IO37"
],
"31": [
295,
550,
"IO38"
],
"32": [
295,
540,
"IO39"
],
"33": [
295,
530,
"IO40"
],
"34": [
295,
520,
"IO41"
],
"35": [
295,
510,
"IO42"
],
"36": [
205,
595,
"RXD0"
],
"37": [
205,
585,
"TXD0"
],
"38": [
295,
780,
"IO2"
],
"39": [
295,
790,
"IO1"
],
"40": [
295,
430,
"GND"
],
"41": [
295,
400,
"EPAD"
]
},
"J22": {
"1": [
65,
345,
"EH"
],
"2": [
65,
335,
"EH"
],
"3": [
65,
325,
"EH"
],
"4": [
65,
315,
"EH"
],
"A1B12": [
135,
235,
"GND"
],
"A4B9": [
135,
245,
"VBUS"
],
"B8": [
135,
255,
"SBU2"
],
"A5": [
135,
265,
"CC1"
],
"B7": [
135,
275,
"DN2"
],
"A6": [
135,
285,
"DP1"
],
"A7": [
135,
295,
"DN1"
],
"B6": [
135,
305,
"DP2"
],
"A8": [
135,
315,
"SBU1"
],
"B5": [
135,
325,
"CC2"
],
"B4A9": [
135,
335,
"VBUS"
],
"B1A12": [
135,
345,
"GND"
]
},
"C601": {
"1": [
105,
690,
"1"
],
"2": [
135,
690,
"2"
]
},
"C602": {
"1": [
100,
635,
"1"
],
"2": [
140,
635,
"2"
]
},
"R601": {
"1": [
120,
590,
"1"
],
"2": [
120,
550,
"2"
]
},
"C603": {
"1": [
120,
510,
"1"
],
"2": [
120,
470,
"2"
]
},
"R602": {
"1": [
180,
265,
"1"
],
"2": [
220,
265,
"2"
]
},
"R603": {
"1": [
180,
325,
"1"
],
"2": [
220,
325,
"2"
]
},
"R604": {
"1": [
650,
620,
"1"
],
"2": [
650,
580,
"2"
]
},
"R605": {
"1": [
730,
620,
"1"
],
"2": [
730,
580,
"2"
]
},
"R606": {
"1": [
810,
620,
"1"
],
"2": [
810,
580,
"2"
]
},
"R607": {
"1": [
890,
620,
"1"
],
"2": [
890,
580,
"2"
]
},
"R608": {
"1": [
980,
620,
"1"
],
"2": [
980,
580,
"2"
]
},
"R618": {
"1": [
660,
400,
"1"
],
"2": [
660,
360,
"2"
]
},
"RT601": {
"1": [
660,
320,
"1"
],
"2": [
660,
280,
"2"
]
},
"C613": {
"1": [
720,
330,
"1"
],
"2": [
720,
290,
"2"
]
},
"R619": {
"1": [
880,
400,
"1"
],
"2": [
880,
360,
"2"
]
},
"RT602": {
"1": [
880,
320,
"1"
],
"2": [
880,
280,
"2"
]
},
"C614": {
"1": [
940,
330,
"1"
],
"2": [
940,
290,
"2"
]
}
}