初始导入：PhoneRail 五路手机直供电源板

原理图/PCB 已在 EasyEDA 里做到 12 页跨页 0 漏接，固件刚完成骨架包 A1。
这次是把已有的一切一次性纳入版本控制，没有改动任何设计内容。

纳入：
- 设计与需求文档、PROGRESS.md、小米8 参考原理图 PDF 与追脚脚本
- .claude/ 下的 EasyEDA 桥接工具链与几何/网表缓存（eda-parts.json、
  pcb-parts.json、pcb-pads.json、p2-ch1.json 等，是重画各页的唯一事实来源）
- 117 张验证截图（本项目所有方向问题都是靠人眼看截图发现的，属于证据不是垃圾）
- firmware/ 的 A1 骨架与 site/ 文档站源码

.gitignore 排除：构建产物（firmware/build、host/build、sdkconfig）、
site/node_modules、__pycache__、桥接日志 _bridge.log、脚本自标的 *.stale。

.gitattributes 默认 `* -text`：现有 .py/.json 大多是 CRLF，原样存，
不让 git 重写行尾。唯一例外是 *.sh 强制 LF —— 带 \r 的 shell 脚本 bash 跑不了。

Co-Authored-By: Claude Opus 5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01QYuExfgyYa6DzRRcUso8M8

.claude/_p1_hdr_nets.json

@@ -0,0 +1,326 @@
+{
+ "J25": [
+  [
+   "1",
+   "+5V"
+  ],
+  [
+   "2",
+   "+5V"
+  ],
+  [
+   "3",
+   "+5V"
+  ],
+  [
+   "4",
+   "+5V"
+  ],
+  [
+   "5",
+   "POGO2_PWR"
+  ],
+  [
+   "6",
+   "VBUS_EN5"
+  ],
+  [
+   "7",
+   "POGO2_VUP"
+  ],
+  [
+   "8",
+   "EDL_EN5"
+  ],
+  [
+   "9",
+   "POGO2_VDN"
+  ],
+  [
+   "10",
+   "GND"
+  ],
+  [
+   "11",
+   "EDL_EN2"
+  ],
+  [
+   "12",
+   "GND"
+  ],
+  [
+   "13",
+   "VBUS_EN2"
+  ],
+  [
+   "14",
+   "GND"
+  ],
+  [
+   "15",
+   "HUB_RST"
+  ],
+  [
+   "16",
+   "GND"
+  ],
+  [
+   "17",
+   "GND"
+  ],
+  [
+   "18",
+   "VO5_P"
+  ],
+  [
+   "19",
+   "GND"
+  ],
+  [
+   "20",
+   "VO5_P"
+  ],
+  [
+   "21",
+   "GND"
+  ],
+  [
+   "22",
+   "VO5_P"
+  ],
+  [
+   "23",
+   "POGO3_PWR"
+  ],
+  [
+   "24",
+   "POGO5_PWR"
+  ],
+  [
+   "25",
+   "POGO3_VUP"
+  ],
+  [
+   "26",
+   "POGO5_VUP"
+  ],
+  [
+   "27",
+   "POGO3_VDN"
+  ],
+  [
+   "28",
+   "POGO5_VDN"
+  ],
+  [
+   "29",
+   "VO3_P"
+  ],
+  [
+   "30",
+   "GND"
+  ],
+  [
+   "31",
+   "VO3_P"
+  ],
+  [
+   "32",
+   "GND"
+  ],
+  [
+   "33",
+   "VO3_P"
+  ],
+  [
+   "34",
+   "GND"
+  ],
+  [
+   "35",
+   "EDL_EN3"
+  ],
+  [
+   "36",
+   "GND"
+  ],
+  [
+   "37",
+   "VBUS_EN3"
+  ],
+  [
+   "38",
+   "GND"
+  ],
+  [
+   "39",
+   "+5V"
+  ],
+  [
+   "40",
+   "+5V"
+  ]
+ ],
+ "J24": [
+  [
+   "1",
+   "VO1_P"
+  ],
+  [
+   "2",
+   "GND"
+  ],
+  [
+   "3",
+   "VO1_P"
+  ],
+  [
+   "4",
+   "GND"
+  ],
+  [
+   "5",
+   "VO1_P"
+  ],
+  [
+   "6",
+   "GND"
+  ],
+  [
+   "7",
+   "+5V"
+  ],
+  [
+   "8",
+   "GND"
+  ],
+  [
+   "9",
+   "+5V"
+  ],
+  [
+   "10",
+   "GND"
+  ],
+  [
+   "11",
+   "POGO1_PWR"
+  ],
+  [
+   "12",
+   "POGO4_PWR"
+  ],
+  [
+   "13",
+   "POGO1_VUP"
+  ],
+  [
+   "14",
+   "POGO4_VUP"
+  ],
+  [
+   "15",
+   "POGO1_VDN"
+  ],
+  [
+   "16",
+   "POGO4_VDN"
+  ],
+  [
+   "17",
+   "EDL_EN1"
+  ],
+  [
+   "18",
+   "EDL_EN4"
+  ],
+  [
+   "19",
+   "VBUS_EN1"
+  ],
+  [
+   "20",
+   "VBUS_EN4"
+  ],
+  [
+   "21",
+   "SDA"
+  ],
+  [
+   "22",
+   "+5V"
+  ],
+  [
+   "23",
+   "SCL"
+  ],
+  [
+   "24",
+   "+5V"
+  ],
+  [
+   "25",
+   "GND"
+  ],
+  [
+   "26",
+   "UP_VBUS_DET"
+  ],
+  [
+   "27",
+   "GND"
+  ],
+  [
+   "28",
+   "GND"
+  ],
+  [
+   "29",
+   "GND"
+  ],
+  [
+   "30",
+   "VO4_P"
+  ],
+  [
+   "31",
+   "GND"
+  ],
+  [
+   "32",
+   "VO4_P"
+  ],
+  [
+   "33",
+   "GND"
+  ],
+  [
+   "34",
+   "VO4_P"
+  ],
+  [
+   "35",
+   "VO2_P"
+  ],
+  [
+   "36",
+   "GND"
+  ],
+  [
+   "37",
+   "VO2_P"
+  ],
+  [
+   "38",
+   "GND"
+  ],
+  [
+   "39",
+   "VO2_P"
+  ],
+  [
+   "40",
+   "GND"
+  ]
+ ]
+}